# COM+ # COM-HPC® Carrier Design Guide # Guidelines for Designing COM-HPC® Carrier Boards February 16, 2024 # Rev. 2.2 This Design Guide is not a specification. It provides COM-HPC® Carrier implementation information but does not replace the PICMG COM-HPC® specification. The full COM-HPC® specification is needed in conjunction with this Design Guide for signal descriptions, signal integrity information and loss budgets, Module and Carrier connector pinouts, PCB mechanical details and more. © Copyright 2021, 2022, 2023, 2024 PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG® specifications may require use of an invention covered by patent rights. PICMG® shall not be responsible for identifying patents for which a license may be required by any PICMG® specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). IMPORTANT NOTICE: This document includes references to specifications, standards or other material not created by PICMG. Such referenced materials will typically have been created by organizations that operate under IPR policies with terms that vary widely, and under process controls with varying degrees of strictness and efficacy. PICMG has not made any enquiry into the nature or effectiveness of any such policies, processes or controls, and therefore ANY USE OF REFERENCED MATERIALS IS ENTIRELY AT THE RISK OF THE USER. Users should therefore make such investigations regarding referenced materials, and the organizations that have created them, as they deem appropriate. PICMG®, COM-HPC®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COM-HPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and cPCI Serial Space™, xTCA™, IRTM™ and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. # Table of Contents 1. Preface....................... C 1.1. About This Document.. 1.2. Intended Audience... 1.3. No Special Word Usage... 1.4. No Statements of Compliance.. 1.5. Correctness Disclaimer.... 1.6. Name and Logo Usage.. .10 1.7. Intellectual Property... .11 1.7.1. Necessary IPR Claims (Referring to Mandatory or Recommended Features). ..11 1.7.2. Unnecessary Claims (Referring to Optional Features or Non-normative Elements).. ..11 1.7.3. Third Party Disclosures.. ..12 1.7.4. Copyright Notice.. ..12 1.7.5. Trademarks.. .12 1.8. Acronyms, Abbreviations and Definitions Used.. ..13 1.9. Applicable Documents and Standards....... ..16 2. COM-HPC Interfaces....................... ... 18 2.1. COM-HPC Client and Server Pinout Differences..... ..18 2.2. COM-HPC Client and COM-HPC Mini Pinout Differences.... .21 3. Reference Schematics and Block Diagrams... .22 3.1. Sources for Technical Materials...... .22 3.2. Schematic Conventions....... .22 3.3. Ethernet NBASE-T... .23 3.4. Ethernet KR and KR4... .24 3.4.1. Ethernet KR CEI Block Diagrams.. ..24 3.4.2. PHY Addresses.. 3.5. Serial ATA.. .33 3.5.1. Cabled SATA... ..33 3.5.2. mSATA SSDs.. ..34 3.5.3. M.2 SATA SSDs.. ..34 3.6. PCI Express......... .35 3.6.1. General Notes.... ..35 3.6.2. PCI Express Coupling Capacitor Locations.. ..36 3.6.3. PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key.. ..37 3.6.4. Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High... ..43 3.6.5. PCIe x16 Slot Card Site on PCIe Group 1.. ..46 3.6.6. PCIe Group 2.. ..47 3.6.7. MXM-3 Graphics Card Module on Carrier... ..51 3.6.8. PCIe Reference Clocks.. .52 3.6.9. PCIe Redrivers and Retimers.. ..57 3.7. USB... .58 3.7.1. USB Terms and General Information.. ..58 3.7.2. USB 2.0 Type-A Example.. ..60 3.7.3. USB 3.2 Gen 1 and Gen 2 Type-A.. ..61 3.7.4. USB 3 Redrivers.. ..62 3.7.5. USB Type-C Overview.. ..63 3.7.6. USB Type-C Port Multiplexers.. ..67 3.7.7. USB Type-C Power Delivery Controllers.. ..68 3.7.8. USB Type-C Port Protection Components.. ..69 3.7.9. USB 3.2 Gen 2x1 Type-C Basic Implementation. ..70 3.7.10. USB 3.2 Gen 2x2 Type-C Example Implementation.. ..72 3.7.11. USB4.. ...78 3.8. Boot SPI on Carrier........ ..81 3.9. eSPI.... ..85 3.10. DisplayPort Over DDI... ..86 3.11. HDMI Over DDI... .89 3.12. eDP.. .92 3.12.1. eDP / DP Conversions to Other Video Formats...... ..94 3.13. MIPI-CSI Camera Interface... .95 3.14. Audio Interfaces.... .96 3.14.1. General Discussion.. .96 3.14.2. MIPI SoundWire Summary...... ..96 3.14.3. I2S Implementations on COM-HPC.. ..99 3.14.4. High Definition Audio (HDA) on COM-HPC Client and Mini.. ..99 3.15. Asynchronous Serial Port Interfaces........ ....100 3.15.1. COM-HPC UART Interfaces... ..100 3.15.2. Legacy Compatibility With 16C550 UART Register Set.. ..102 3.15.3. Alternative / Additional Carrier Board UART Implementations.. ...102 3.16. I2C / I3C Ports..... ... 103 3.16.1. I2C Addressing... ..104 3.16.1. I2C0 Example: Carrier I2C Device in S0 Power Domain. ...105 3.16.2. I2C Bus Buffers / Level Translators. ..106 3.16.3. I2C1 (COM-HPC) and Optional I3C Support.. ...107 3.16.4. I2C on COM-HPC Mini.. ..108 3.17. Port 80h Debug Display Over COM-HPC USB\_PD\_I2C.. ...109 3.18. Carrier BMC with IPMB Link to Module........ .....110 3.19. General Purpose SPI.... .... 114 3.20. Rapid Shutdown......... ....114 3.21. Thermal Protection.......... ....115 3.22. System Management Bus (SMBus)............. ....116 3.23. General Purpose Inputs / Outputs.......... ..... 117 3.24. Module Type Detection and Protection........... .....118 3.25. COM-HPC Mini SGMII Ethernet Interface Example.......... .....120 4. PCB Design Rule Summaries... ..122 4.1. High Speed PCB Design Information – Design Guides and Books...... ...122 4.1.1. Intel and AMD Design Guides.. ..122 4.1.2. Books on High Speed PCB Design Principles.. ..123 4.2. High Speed Serial Interfaces – General PCB Design Rules........ ....124 4.3. PCB Design Rule Summaries – High Speed Differential Pair Serial Interfaces....... ....127 4.3.1. NBASE-T Design Rule Summary.... ..127 4.3.2. Ethernet KR Design Rule Summary.. ..128 4.3.3. SATA Design Rule Summary.. ..129 4.3.4. PCIe Design Rule Summary.. ..130 4.3.5. USB 2.0 Design Rule Summary.. ..131 4.3.6. USB 3.2 and USB4 Design Rule Summaries.. ..132 4.3.7. DisplayPort Design Rule Summary.. ..134 4.3.8. eDP Design Rule Summary.. ..135 4.3.9. HDMI Design Rule Summary... ...136 4.4. PCB Design Rules for Single Ended (SE) Interfaces........ ....137 5. Mechanical Considerations................... ... 138 5.1. Heat Spreader / Module / Carrier Attachment Details... ...138 5.1.1. Heat Spreader to Module Attachment Notes. ..138 5.1.2. Heat Spreader / Module Assembly Attachment to Carrier and Chassis. 5.2. Alternative COM-HPC Board Stack Assembly Suggestion.......... ....144 5.2.1. Precision Jack Screw Standoffs.. ..144 5.3. Carrier Board Stiffener.... ..146 6. Appendices... ..150 6.1. Appendix A: Synchronous Ethernet... ....150 6.2. Appendix B: Alternative eDP Example....... ....154 6.3. Appendix C: eSPI Header Example........ ....161 6.4. Appendix D: Useful Books – General x86 Computer Topics... ....162 6.5. Appendix E: Revision History....... ....163 # Index of Tables Table 1: Acronyms, Abbreviations and Definitions Used.. ..13 Table 2: Client and Server Type Pinout Difference Table.. ..18 Table 3: Power Net Naming.. .22 Table 4: MDIO Addresses for Intel POR External PHYs.. ..32 Table 5: mSATA Pin Mapping Relative to miniPCIe.. ..34 Table 6: PCIe Maximum Allowable Clock Jitter.. .52 Table 7: PCIe Clock Buffer Modes.. .53 Table 8: PCIe Clock Buffer Vendors and Part Numbers.. ..54 Table 9: PCIe Redrivers and Retimers.. ..57 Table 10: USB.org Branding Term Summary.. ..58 Table 11: USB Type-A Pin-Out.. ..59 Table 12: USB 3 Redrivers...... ..62 Table 13: USB Type-C Connector Pinout.. ..64 Table 14: USB Type-C Port Multiplexers – Possible Modes... ..67 Table 15: Boot SPI Socket Suggestions... ..83 Table 16: DisplayPort Redrivers and Retimers... ..88 Table 17: SoundWire Audio CODECs.. .97 Table 18: Alternative / Additional Carrier Board UART Implementations. ...102 Table 19: I2C Operating Modes... ..103 Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation.. ..106 Table 21: COM-HPC Type Definitions... ...118 Table 22: Intel and AMD Design Guides.. ..122 Table 23: General Design Rules for High Speed Serial interfaces... ..125 Table 24: NBASE-T Design Rule Summary... ..127 Table 25: Ethernet KR Design Rule Summary.. ..128 Table 26: SATA Design Rule Summary.. ..129 Table 27: PCIe Design Rule Summary.. ..130 Table 28: USB 2.0 Design Rule Summary.. ..131 Table 29: USB 3.2 and USB4 Design Rule Summaries.. ..132 Table 30: DisplayPort Design Rule Summary... ..134 Table 31: HDMI Design Rule Summary... ..136 Table 32: Design Rules for Single Ended Interfaces.. ...137 Table 33: SDP Use in Figure 73 above..... ...152 Table 34: SyncE / PTP Matrix... ..153 Table 35: General Books on x86 Computer Topics.. ..162 Table 36: Revision History.. ..163 # Table of Figures Figure 1: Schematic Conventions... .22 Figure 2: NBASE-T.. .23 Figure 3: Intel SoC with CEI Boundary... ..25 Figure 4: Intel CEI 4x SFP28.. ..26 Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827.. ..27 Figure 6: Intel CEI QSFP28 with Retimer C827/XL827.. ..28 Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4.. .29 Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543. ..30 Figure 9: AMD SoC 4xSFP+ with CS4223 Retimer.. ..31 Figure 10: Serial ATA – Cabled... ..33 Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded).. ..36 Figure 12: PCIe Device Down on Carrier – PCIe Group 0 Low – PCIe Lane 0.. ..37 Figure 13: Mini-PCIe Site – PCIe Group 0 Low – PCIe Lane 1... ..38 Figure 14: M.2 E-Key Site – WiFi Cards – PCIe Group 0 Low – PCIe Lane 2.. ..39 Figure 15: M.2 B-Key Site – Cell Modem Cards – PCIe Group 0 Low – PCIe Lane 3.. ..40 Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11.. ...43 Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 High PCIe Lanes 12:15.. ..44 Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High. ..45 Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31.. ..46 Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39. ..47 Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43.. ..48 Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47.. ..49 Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example.. ..50 Figure 26: USB 2.0 Type-A Example.. ...60 Figure 27: USB Type-C Receptacle and Plug Images.. ..64 Figure 28: USB Type-C Receptacle Pin-Out – Looking Into Carrier Receptacle.. ...64 Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2.. ..71 Figure 30: USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A.. ..72 Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver... ..73 Figure 32: USB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD Protection.. ..74 Figure 33: USB 3.2 Gen 2x2 Type-C (4 of 6): Port Port Mux / Redriver Coupling Capacitors. ..75 Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller... ..76 Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection.. ..77 Figure 36: USB4 on COM-HPC Client.. ..79 Figure 37: USB4 on COM-HPC Mini.. ..80 Figure 38: Boot SPI on Carrier (Example 1)... ..81 Figure 39: Boot SPI on Carrier – Socketed Flash and Multiplexer to External Programmer.. ..84 Figure 40: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device........85 Figure 41: DisplayPort Over DDI.. ..86 Figure 42: HDMI Over DDI.. ..89 Figure 43: eDP Schematic Example.. ..92 Figure 44: eDP Connector Pin Numbering.. ..93 Figure 45: MIPI-CSI.. ..95 Figure 46: MIPI SoundWire Routing Topologies.. ..98 Figure 47: MIPI SoundWire Point to Point Connection With SI Components.. ..98 Figure 48: UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports.. ..101 Figure 49: I2C0 Example: Carrier EEPROM in S5 Power Domain.. ..104 Figure 50: I2C0 Example: Carrier Temperature Sensor in S0 Power Domain.. ...105 Figure 51: Port 80h Debug Display Over COM-HPC USB\_PD\_I2C.. ...109 Figure 52: Carrier BMC with IPMB Link to Module – Sheet 1... ...111 Figure 53: Carrier BMC with IPMB Link to Module – Sheet 2.. ...112 Figure 54: Carrier BMC with IPMB Link to Module – Sheet 3.. ...113 Figure 55: Module Type Detection / Protection – ATX Power Supply and Client Type Module / Carrier.........119 Figure 56: Module Type Detection / Protection – AT Power Supply and Server Type Module / Carrier..........119 Figure 57: Module Type Detection / Protection – COM-HPC Mini Module.. ...120 Figure 59: PCB Cross Section Terms and Notations.. ...124 Figure 60: Vendor Specific Heat Spreader to Module Attachment – Bottom Side Module PCB Access.........138 Figure 61: Heat Spreader Assembly Mounting to Carrier – Bottom Side Screw Access.. ..139 Figure 62: Heat Spreader Assembly Mounting to Carrier – Top Side Screw Access. ..140 Figure 63: Heat Spreader Assembly Mounting to Carrier With Broaching Nut – Top Side Screw Access......141 Figure 64: Heat Spreader Assembly Mounting to Carrier and Chassis – Top Side Screw Access... ...142 Figure 65: JSOM (Jack Screw Standoff – Micro) Diagram and Application Cutaway... ..144 Figure 66: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns....145 Figure 67: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware.. ...145 Figure 68: FEM Simulation Results – 0.0625” FR4 Carrier – No Stiffener..... ...146 Figure 69: Mechanical Carrier Stiffener Possibility.. ..147 Figure 70: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier).. ...148 Figure 71: Application Specific Part Number (ASP) Reference Guide.. ...149 Figure 72: Synchronous Ethernet Overview... ...151 Figure 73: Synchronous Ethernet Example Implementation.. ..152 Figure 74: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options – eDP and DSI. ...155 Figure 75: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options.. ...156 Figure 76: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly.. ...157 Figure 77: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver...... ...158 Figure 78: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED. ..159 Figure 79: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight.. ...160 Figure 80: eSPI Header Example.. ...161 # 1. Preface # 1.1. About This Document This document provides information for designing project specific Carrier Boards for systems using COM-HPC Modules. This document is a design guide and not a specification document. It should be used by together with the COM-HPC Base Specification, with other industry specifications (listed in Section 1.9. below), with silicon and component vendor’s documentation and with your COM-HPC Module vendor’s product documentation. The PICMG COM Express Carrier Board Design Guide is also a very useful additional source of information. The COM-HPC and COM Express pin names are not the same, but it is not hard to correlate them. The COM Express design guide document is available for free download on the public PICMG website (www.picmg.org). No membership is required to down load the design guides. Revision 2.2 of this document includes numerous notes that clarify how COM-HPC Client examples need to be modified slightly for use in COM-HPC Mini designs. The differences between the COM-HPC Client and the Mini are well described in the COM-HPC Module Base Specification Rev. 1.20, primarily in Section 10 of that document. The notes that clarify the COM-HPC Mini differences are presented in this bold italic blue font to make the notes stand out. # 1.2. Intended Audience This design guide is intended for electronics engineers and PCB layout engineers designing Carrier Boards for PICMG COM-HPC Modules. It may also be useful to COM-HPC Module designers for them to better understand how COM-HPC Modules are used, and to understand how some of the design rules (trace length recommendations, trace length matching recommendations etc.) are shared between Module and Carrier designs. # 1.3. No Special Word Usage Unlike a PICMG specification, which assigns special meanings to certain words such as ”shall”, “should” and “may”, there is no such usage in this document. That is because this document is not a specification; it is a non-normative design guide. # 1.4. No Statements of Compliance As this document is not a specification but a set of guidelines, there should not be any statements of compliance made with reference to this document. # 1.5. Correctness Disclaimer The schematic examples given in this document are believed to be correct but no guarantee is given. # 1.6. Name and Logo Usage The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows: Permission to use the PICMG® organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at www.picmg.org) during the period of time for which their membership dues are paid. Nonmembers may not use the PICMG® organization logo. The PICMG® organization logo must be printed in black or color as shown in the files available for download from the member’s side of the Web site. Logos with or without the “Open Modular Computing Specifications” banner can be used. Nothing may be added or deleted from the PICMG® logo. The use of the COM-HPC® logo is a privilege granted by the PICMG® organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and that believe their products comply with these specifications. Manufacturers' distributors and sales representatives may use the COM-HPC® logo in promoting products sold under the name of the manufacturer. Use of the logos by either members or non-members implies such compliance. Only PICMG Executive and Associate members may use the PICMG® logo. PICMG® may revoke permission to use logos if they are misused. The COM-HPC® logo can be found on the PICMG web site, www.picmg.org. The COM-HPC® logo must be used exactly as shown in the files available for download from the PICMG® Web site. The aspect ratios of the logos must be maintained, but the sizes may be varied. Nothing may be added to or deleted from the COM-HPC® logo. The PICMG® name and logo and the COM-HPC® name and logo are registered trademarks of PICMG®. Registered trademarks must be followed by the ® symbol, and the following statement must appear in all published literature and advertising material in which the logo appears: PICMG, the COM-HPC® name and logo and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group. # 1.7. Intellectual Property The PICMG Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ("IPR"). The PICMG Consortium takes no position concerning the evidence, validity or scope of this IPR. The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-Members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium. Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. The Consortium shall not be responsible for identifying any or all such IPR. No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification. This specification conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made: # 1.7.1. Necessary IPR Claims (Referring to Mandatory or Recommended Features) Samtec Inc. has the following patents, which may cover some aspects of the PICMG® COM-HPC® Module and Carrier Board Connectors. Contact Samtec Inc. at royalties@samtec.com for further information.
China201480061913.2
China202111274151.2
China201921051845.8
China202030159171.5
EPO007814686-0001
EPO007814686-0002
EPO007814686-0003
EPO007814686-0004
EPO19830502.1
Taiwan109138672
TaiwanM589915
TaiwanD209464
Taiwan109304816
Taiwan505072
US29/70951
US9374900
# 1.7.2. Unnecessary Claims (Referring to Optional Features or Non-normative Elements)
US9374900
CN201480061913.2
TWM505072
PCT2021207390
TW110112769
CN11566924
US17/817659
# 1.7.3. Third Party Disclosures (Note that third party IPR submissions do not contain any claim of willingness to license the IPR.) US 10,404,014 B2, FCI USA LLC, Sep. 3, 2019, “STACKING ELECTRICAL CONNECTOR WITH REDUCED CROSS TALK” Refer to PICMG® IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage. PICMG® makes no judgment as to the validity of these claims or the licensing terms offered by the claimants. THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INFRINGEMENT IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, SHALL HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING FROM THE USE OF THIS SPECIFICATION. Compliance with this specification does not absolve manufacturers of COM-HPC® equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COM Express®, COM-HPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and xTCA™, IRTM™ and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. # 1.7.4. Copyright Notice © 2021, 2022, 2023 PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from PICMG. PICMG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”. # 1.7.5. Trademarks Intel is a registered trademark of Intel Corporation. PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). COM-HPC® is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registered trademark of NXP Semiconductors. Samtec is a registered trademark of Samtec Inc. All product names and logos referenced in this document are property of their owners. Thunderbolt is a registered trademark of the Intel corporation. Accelerate is a trademark of Samtec Inc. # 1.8. Acronyms, Abbreviations and Definitions Used Table 1: Acronyms, Abbreviations and Definitions Used
TermDefinition
10GBASE-KR10 Gbps internal copper interface. Operates over a single lane and uses the same physical layer coding (defined in IEEE 802.3 Clause 49) as 10GBASE-LR (Single Mode Fiber 1310 nm) / ER (Single Mode Fiber 1550 nm) /SR (Multi Mode Fiber 850 nm)
25GBASE-KR25 Gb/s internal copper interface using 25GBASE-R encoding over one lane in each direction
AC CoupledThis term means that series capacitors are inserted in the differential pair lines. This allows the transmit and receive lines to have their own, possibly separate DC common mode voltages.
ACPIAdvanced Configuration Power Interface
AMOLEDActive Matrix Organic (semiconductor) Light Emitting Diode (a flat panel display technology)
ARMAdvanced RISC Machine – a low power alternative CPU architecture widely used in mobile and embedded systems
ATXAdvanced Technology Extended – Industry standard PC Motherboard form factor and power supply definitions
BIDIRBidirectional (in reference to electrical signals)
BIOSBasic Input Output System
BMCBaseboard Management Controller or Board Management Controller – located on Carrier for COM-HPC, if implemented
Carrier BoardAn application specific circuit board that accepts a COM-HPC Module
CCCCurrent Carrying Capability
DDIDigital Display Interface – an interface that can serve DisplayPort and HDMI/DVI,
DIMMDual In-line Memory Module – larger format SDRAM memory module used in desk top systems and server PCs
DisplayPort DPDisplayPort is a digital display interface standard put forth by the Video Electronics Standards Association (VESA). It defines a new license free, royalty free, digital audio/video interconnect, intended to be used primarily between a computer and its display monitor.
DPLLDigital Phase Locked Loop
DRAMDynamic Random Access Memory
DVIDigital Visual Interface – a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digital and analog video signals. The digital signals use TMDS.
EAPIEmbedded Application Programming Interface
ECEmbedded Controller
ECNEngineering Change Notice
EEPROMElectrically Erasable Programmable Read-Only Memory
Embedded Dis-playPort eDPEmbedded DisplayPort (eDP) is a digital display interface standard defined by the Video Electronics Standards Association (VESA) for digital interconnect of Audio and Video within a closed system such as a laptop computer or a piece of laboratory instrumentation.
ESDElectro Static Discharge
eSPIEnhanced Serial Peripheral Interface
FAEField Application Engineer
FETField Effect Transistor – available as N-Channel (nFET) or P-Channel (pFET) devices
FlashEEPROM memory used for code storage. It can be updated in place (“flashed”).
FPGAField Programmable Gate Array
FR4A type of fiber-glass laminate commonly used for printed circuit boards.
GbGigabit
GbEGigabit Ethernet
GbpsGigabits per second
GPIGeneral Purpose Input
GPSGlobal Positioning System
GPIOGeneral Purpose Input Output
GPOGeneral Purpose Output
GPUGraphics Processing Unit
GtpsGiga Transfers per Second
HDAIntel High Definition Audio (HD Audio) refers to the specification released by Intel in 2004 for delivering high definition audio.
HDMIHigh Definition Multimedia Interface – digital display interface widely used in consumer electronics such as digital TVs
I2CInter Integrated Circuit – 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to read and load register values.
I2SInter IC Sound – a 5 wire serial data interface, used primarily for transmitting and receiving digital audio data
I3CImproved Inter Integrated Circuit – builds on I2C and offers higher speeds and in-band interrupts
IPMBIntelligent Platform Management Bus
IPMIIntelligent Platform Management Interface
IPRIntellectual Property Rights
LANLocal Area Network
Legacy DeviceRelics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial port, parallel printer port, PS-2 keyboard, and mouse. Definitions vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device.
LPCLow Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC.
LSLeast Significant
M.2A small form factor add in card, for storage, WiFi, Cell Modems, etc. Interface options include PCIe x1, x2 or x4, SATA, USB and asynchronous serial. The standard is maintained by the PCI-SIG.
MACMedia Access Control – in this document, MAC refers to the physical hardware bridge device between a CPU interface such as PCIe, and a network interface such as MDI or 10GBASE-KR or many others. A PHY is needed between the MAC and the Ethernet physical layer
MAFSTerm for Master Attached Flash Sharing where the Flash component is attached to the processor interface.
MDIMedia Dependent Interface between an Ethernet PHY and the system magnetics and copper twisted pairs
MDIOManagement Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs).
MEManagement Engine – Intel term for a management microcontroller embedded into the chipset silicon. It is active before the main x86 CPU boots.
MIPIIndustry trade group that sets standards for mobile devices
MMCModule Management Controller – a small microcontroller on the Module that works in conjunction with a Carrier BMC to implement IPMI functions. Implementation is optional.
MSMost Significant
NA or N/ANot Available, Not Applicable
NBASE-KREthernet back plane signaling on PCB differential pairs. 'N' signifies the speed – 25Gbps or 10Gbps
NBASE-TEthernet physical layer signaling on twisted pairs. 'N' signifies the speed – 10Gbps, 5Gbps, 2.5Gbps, 1Gbps, 100Mbps or 10Mbps
NCNo Connect
NDANon-Disclosure Agreement
Nyquist FrequencyThe critical frequency, sometimes called the "folding frequency", for a digital sampling system. It is (usually) $\frac{1}{2}$ of the maximum data rate for the system.
NVMENon Volatile Memory Express – non volatile memory with a PCIe interface – x1, x2 or x4 – often in an M.2 card form factor
OCXOOven Controlled Xtal (crystal) Oscillator
OEMOriginal Equipment Manufacturer
OTPOne Time Programmable – an option offered by some silicon vendors to change IC parameters by programming or blowing device fuses once, before shipment.
PC-AT"Personal Computer – Advanced Technology" – an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s
PCBPrinted Circuit Board
PCIPeripheral Component Interconnect
PCI Express PCIePeripheral Component Interconnect Express – serialized point-to-point version of PCI
PEGPCI Express Graphics
PHYPhysical layer device, usually used in the context of
PMDPhysical Medium Dependent – the physical layer of computer network protocols
PORPlan of Record
PPSPulse Per Second (for Ethernet)
PTPPrecision Time Protocol (for Ethernet)
PU PDPull Up – A connection between a signal and a specified power rail, through a resistor Pull Down
RaRoughness Average – a measure of surface roughness, expressed in units of length.
ROMRead Only Memory – a legacy term – often the device referred to as a ROM can actually be written to, in a special mode. Such writable ROMs are sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM.
RSVDReserved. If a pin is marked RSVD, nothing should be connected to it
RTCReal Time Clock – battery backed circuit in PC-AT systems that keeps system time and date
S0, S1, S2, S3, S4, S5System states describing the power and activity levelS0 Full power, all devices poweredS1 CPU powered, CPU and bus clocks off, not in common useS2 Not usedS3 Suspend to RAM System context stored in RAM; only standby power rail presentS4 Suspend to Disk System context stored on disk; only standby power rail presentS5 Soft Off Main power rail off, only standby power rail present
SAFSTerm for Slave Attached Flash Sharing where the Flash component is attached behind a BMC component.
SATASerial Advanced Technology Attachment – serial interface standard for hard disks
SDPSoftware Definable Pin
SKUStock Control Unit (a part number for a specific stockable item)
SGMIISerial Gigabit Media Independent Interface
SMASub Miniature type A – a small form factor circular connector used for miniature coax cables, for WiFi, GPS and Cell Modem antennas
SMBusSystem Management Bus – a 3 wire bus – clock, data and alert – based in I2C – for system management
SOCSystem On Chip
SO-DIMMSmall Outline Dual In-line Memory Module – small form factor SDRAM module
SPDSerial Presence Detect – refers to serial EEPROM on DRAMs that has DRAM Module configuration information
SPISerial Peripheral Interface
Super I/OAn integrated circuit, typically interfaced via the LPC or eSPI bus that provides legacy PC I/O functions including PS2 keyboard and mouse ports, serial and parallel port(s) and a floppy interface.
TFTThin Film Transistor – refers to technology used in active matrix flat-panel displays, in which there is one thin film transistor per display pixel.
TMDSTransition Minimized Differential Signaling – a digital signaling protocol between the graphics subsystem and display. TMDS is used for the DVI digital signals.
TPMTrusted Platform Module, chip to enhance the security features of a computer system.
USBUniversal Serial Bus
VgsGate to Source voltage to turn a FET on
WDTWatch Dog Timer.
XAUI10 Gbps Attachment Unit Interface.
XGMII10 Gbps Media Independent Interface
XOXtal (crystal) Oscillator
# 1.9. Applicable Documents and Standards The list below is a partial list of documents and standards applicable to COM-HPC®. Many of the standards groups listed below (MIPI, PCI-SIG, USB, VESA etc.) have much more additional information available – ECNs, supplemental documents, test specifications, SI masks etc. These are too numerous to list here. Please explore the links below for additional documents that may be relevant. Advanced Configuration and Power Interface (ACPI) Specification Version 6.3, January 2019, Copyright © 2018, Unified Extensible Firmware Interface (UEFI) Forum, Inc. All rights reserved. https://uefi.org/specifications ATX Specification Version 2.2 © Intel Corp. 2004  ATX12V Power Supply Design Guide, Version 2.2, March 2005 © Intel Corp. eSPI Enhanced Serial Peripheral Interface, Interface Base Specification Revision 1.0, Copyright © 2016, Intel Corporation. January 2016 https://downloadcenter.intel.com/download/27055/  HDMI (High Definition Multimedia Interface) specifications. http://www.hdmi.org High-Definition Multimedia Interface specification versions 1.3, 1.4b, 2.1 HDMI Alt Mode USB Type-C I2C Specifification NXP UM10204 “I2C-bus specification and user manual” Rev 7 October 1, 2021 http://www.nxp.com use NXP site search tool to locate UM10204 IEEE standards http://www.ieee.org IEEE Std 802.3™-2018 (Revision of IEEE Std 802.3-2015), IEEE Standard for Information technology, Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements – Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications IEEE1588 – 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, July 24, 2008, Copyright 2016 Intelligent Platform Management Interface Specification Second Generation, v2.0, Document Revision 1.1, October 1, 2013 (c) Intel, Hewlett-Packard, NEC, Dell An E7 red-line markup version of this document, dated April 21 2015, is available – see https:// www.intel.com/content/www/us/en/servers/ipmi/ipmi-technical-resources.html Intel Low Pin Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright © 2002 Intel Corporation. All rights reserved. https://www.intel.com/content/www/us/en/design/technologies-and-topics/low-pin-count-interface-specification.html MIPI Alliance specifications https://www.mipi.org MIPI-CSI-2 Camera Serial Interface MIPI-CSI-3 Camera Serial Interface  MIPI DSI Display Serial Interface MIPI DSI-2 Display Serial Interface  MIPI C-PHY Physical layer spec for CSI-2 and DSI-2 (alternative) MIPI D-PHY Physical layer spec for CSI-2 and DSI-2  MIPI M-PHY Physical layer spec for CSI-3 MIPI SoundWire Serialized audio interface  MIPI I3C Two wire serial data interface, successor to I2C MXM Graphics Module Mobile PCI Express Module Electromechanical Specification Version 3.0 Revision 1.1 (c) 2009 Nvidia Corporation Note: this document is not publicly available at the time of this writing but it does exist NEBS (Network Equipment – Building Systems) This is a collection of documents describing reliability criteria for telecom equipment. The NEBs documents are maintained by Telcordia / Ericsson https://telecom-info.telcordia.com  PCI-SIG (Peripheral Component Interconnect Special Interest Group) specifications https://www.pcisig.- com PCI Express Base Specification Revision 5.0  PCI Express Card Electromechanical Specification Revision 4.0  PCI Express Mini Card Electromechanical Specification Revision 2.1  Add USB 3.0 to the Mini Card  PCI Express M.2 Specification Revision 4.0 V1.0  PCI Local Bus Specification Revisions 3,4 and 5.  PICMG (PCI Industrial Computer Manufacturing Group) documents http://www.picmg.org/  PICMG COM.0 COM Express Module Base Specification Revision 3.0  PICMG EAPI Embedded Application Software Interface Specification Revision 1.0  PICMG EEEP Embedded EEPROM Specification Revision 1.0 (for COM-Express) PICMG COM-HPC EEEP Embedded EEPROM Specification Revision 1.0  PICMG COM-HPC Carrier Design Guide Revision 2.2 (this document0  PICMG COM-HPC Base Specification Revision 1.2  PICMG COM Express Carrier Design Guide Revision 2.0  PICMG COM-HPC Platform Management Interface Specification Revision 1.0  PICMG Policies and Procedures for Specification Development, Revision 2.0 Serial ATA Revision 3.5a Specification (March 2021) http://www.sata-io.org/ SFP+, SFF-8083 Rev 3.1, SFF-8083 Specification for SFP+ 1X 10 Gb/s Pluggable Transceiver Solution (SFP10) Rev 3.1, Sep. 13, 2014 ftp://ftp.seagate.com/sff/SFF-8083.PDF  SGET (Standardization Group for Embedded Technologies) standards and documents (www.sget.org)  SMARC Hardware Specification Revision 2.1.1 (Smart Mobility ARChitecture) SMARC Design Guide Revision 2.1.1 SPI, Serial Peripheral Interface Bus See http://elm-chan.org/docs/spi\_e.html for some general information on SPI System Management Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright © 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. see http://www.smbus.org  Trusted Computing Group Specifications https://www.trustedcomputinggroup.org Trusted Platform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007 TPM 2.0 Library Specification  Underwriters Laboratories UL 1642 Standard for Safety for Lithium Batteries USB Specifications https://www.usb.org/  USB 2.0 USB 3.0, 3.1, 3.2 USB4 also known as “Thunderbolt 4” USB Type-C Connector and Power Delivery specifications VESA (Video Electronics Standards Association) https://www.vesa.org DisplayPort Interoperability Guideline Version 1.1a, February 5, 2009 http://www.vesa.org/vesa-standards/free-standards/ DisplayPort Standard Version 1.4 DisplayPort Standard Version 2.0  Embedded DisplayPort (eDP) Specification Rev. 1.4b, Oct 10, 2015 # 2. COM-HPC Interfaces # 2.1. COM-HPC Client and Server Pinout Differences The complete listings of signal descriptions and connector pin assignments for the COM-HPC Client and Server pinout types are found in the PICMG COM-HPC Module Base Specification and are not repeated here. Table 2 below details the Module connector pin assignments that differ between the Client and Server types. Table 2: Client and Server Type Pinout Difference Table
PinRowClientServer
20ADDI1_SDA_AUX-ETH4_RX-
21ADDI1_SCL_AUX+ETH4_RX+
23ADDI1_PAIR0-ETH5_RX-
24ADDI1_PAIR0+ETH5_RX+
26ADDI1_PAIR1-ETH6_RX-
27ADDI1_PAIR1+ETH6_RX+
29ADDI1_PAIR2-ETH7_RX-
30ADDI1_PAIR2+ETH7_RX+
32ADDI1_PAIR3-RSVD
33ADDI1_PAIR3+RSVD
35AeDP_AUX-ETH4_TX-
36AeDP_AUX+ETH4_TX+
38AeDP_TX0-ETH5_TX-
39AeDP_TX0+ETH5_TX+
41AeDP_TX1-ETH6_TX-
42AeDP_TX1+ETH6_TX+
44AeDP_TX2-ETH7_TX-
45AeDP_TX2+ETH7_TX+
47AeDP_TX3-USB1_AUX-
48AeDP_TX3+USB1_AUX+
19BI2S_LRCLK/SNDW_CLK3RSVD
20BI2S_DOUT/SNDW_DAT3RSVD
21BI2S_MCLKRSVD
22BI2S_DIN/SNDW_DAT2RSVD
23BI2S_CLK/SNDW_CLK2RSVD
45BLID#RSVD
46BSLEEP#RSVD
20CSNDW_DMIC_CLK1ETH0_TX-
21CSNDW_DMIC_DAT1ETH0_TX+
23CSNDW_DMIC_CLK0ETH1_TX-
24CSNDW_DMIC_DAT0ETH1_TX+
26CDDI0_DDC_AUX_SELETH2_TX-
27CDDI1_DDC_AUX_SELETH2_TX+
28CDDI0_HPDGND
29CDDI1_HPDETH3_TX-
30CeDP_HPDETH3_TX+
31CeDP_VDD_ENGND
32CeDP_BKLT_ENUSB3_SSRX-
33CeDP_BKLTCTLUSB3_SSRX+
35CUSB1_AUX-USB2_SSRX-
36CUSB1_AUX+USB2_SSRX+
19DDDI0_SDA_AUX-ETH0_RX-
20DDDI0_SCL_AUX+ETH0_RX+
22DDDI0_PAIR0-ETH1_RX-
23DDDI0_PAIR0+ETH1_RX+
25DDDI0_PAIR1-ETH2_RX-
26DDDI0_PAIR1+ETH2_RX+
28DDDI0_PAIR2-ETH3_RX-
29DDDI0_PAIR2+ETH3_RX+
31DDDI0_PAIR3-USB3_SSTX-
32DDDI0_PAIR3+USB3_SSTX+
34DAC_PRESENTUSB2_SSTX-
35DRSVDUSB2_SSTX+
3EDDI2_SDA_AUX-RSVD
4EDDI2_SCL_AUX+RSVD
6EDDI2_PAIR0-RSVD
7EDDI2_PAIR0+RSVD
9EDDI2_PAIR1-RSVD
10EDDI2_PAIR1+RSVD
12EDDI2_PAIR2-RSVD
13EDDI2_PAIR2+RSVD
15EDDI2_PAIR3-RSVD
16EDDI2_PAIR3+RSVD
18EDDI2_DDC_AUX_SELRSVD
19EDDI2_HPDRSVD
69ERSVDPCIe48_TX-
70ERSVDPCIe48_TX+
71ERSVDGND
72ERSVDPCIe49_TX-
73ERSVDPCIe49_TX+
74ERSVDGND
75ERSVDPCIe50_TX-
76ERSVDPCIe50_TX+
77ERSVDGND
78ENBASET1_CTREFPCIe51_TX-
79ENBASET1_SDPPCIe51_TX+
80ENBASET1_LINK_MID#GND
81ENBASET1_LINK_ACT#PCIe52_TX-
82ENBASET1_LINK_MAX#PCIe52_TX+
84ERSVDPCIe53_TX-
85ERSVDPCIe53_TX+
87EETH0_RX-PCIe54_TX-
88EETH0_RX+PCIe54_TX+
90EETH1_RX-PCIe55_TX-
91EETH1_RX+PCIe55_TX+
1FRSVDETH2_SDP
2FRSVDETH3_SDP
3FRSVDETH4_SDP
4FRSVDETH5_SDP
5FRSVDETH6_SDP
6FRSVDETH7_SDP
7FRSVDETH4-7_I2C_CLK
8FRSVDETH4-7_I2C_DAT
9FRSVDETH4-7_INT#
10FRSVDETH4-7_MDIO_CLK
11FRSVDETH4-7_MDIO_DAT
12FRSVDETH4-7_PHY_INT#
13FRSVDETH4-7_PHY_RST#
14FRSVDETH4-7_PRSNT#
68FRSVDPCIe48_RX-
69FRSVDPCIe48_RX+
71FNBASET1_MDIO-PCIe49_RX-
72FNBASET1_MDIO+PCIe49_RX+
74FNBASET1_MDII-PCIe50_RX-
75FNBASET1_MDII+PCIe50_RX+
77FNBASET1_MDII-PCIe51_RX-
78FNBASET1_MDII2+PCIe51_RX+
80FNBASET1_MDI3-PCIe52_RX-
81FNBASET1_MDI3+PCIe52_RX+
83FRSVDPCIe53_RX-
84FRSVDPCIe53_RX+
86FETH0_TX-PCIe54_RX-
87FETH0_TX+PCIe54_RX+
88FETH1_TX-PCIe55_RX-
90FETH1_TX+PCIe55_RX+
95FRSVDPCIe_CLKREQ3#
96FETH0-1_PRSNT#ETH0-3_PRSNT#
97FETH0-1_PHY_RST#ETH0-3_PHY_RST#
2GGNDRSVD
3GUSB2_SSRX0-RSVD
4GUSB2_SSRX0+RSVD
5GGNDRSVD
6GUSB2_SSRX1-RSVD
7GUSB2_SSRX1+RSVD
8GGNDRSVD
9GUSB3_SSRX0-RSVD
10GUSB3_SSRX0+RSVD
11GGNDRSVD
12GUSB3_SSRX1-RSVD
13GUSB3_SSRX1+RSVD
15GUSB3_LSRXRSVD
16GUSB3_LSTXRSVD
17GUSB2_LSRXRSVD
18GUSB2_LSTXRSVD
19GPEG_LANE_REV#RSVD
69GRSVDPCIe56_RX-
70GRSVDPCIe56_RX+
72GCSI0_RX0-PCIe57_RX-
73GCSI0_RX0+PCIe57_RX+
75GCSI0_RX1-PCIe58_RX-
76GCSI0_RX1+PCIe58_RX+
78GCSI0_RX2-PCIe59_RX-
79GCSI0_RX2+PCIe59_RX+
81GCSI0_RX3-PCIe60_RX-
82GCSI0_RX3+PCIe60_RX+
84GCSI0_CLK-PCIe61_RX-
85GCSI0_CLK+PCIe61_RX+
87GCSI0_I2C_CLKPCIe62_RX-
88GCSI0_I2C_DATPCIe62_RX+
89GCSI0_MCLKGND
90GCSI0_RST#PCIe63_RX-
91GCSI0_ENAPCIe63_RX+
93GRSVDPCIe_REFCLK3-
94GRSVDPCIe_REFCLK3+
96GETH0-1_I2C_CLKETH0-3_I2C_CLK
97GETH0-1_I2C_DATETH0-3_I2C_DAT
98GETH0-1_PHY_INT#ETH0-3_PHY_INT#
99GETH0-1_INT#ETH0-3_INT#
1HGNDRSVD
2HUSB2_SSTX0-RSVD
3HUSB2_SSTX0+RSVD
4HGNDRSVD
5HUSB2_SSTX1-RSVD
6HUSB2_SSTX1+RSVD
7HGNDRSVD
8HUSB3_SSTX0-RSVD
9HUSB3_SSTX0+RSVD
10HGNDRSVD
11HUSB3_SSTX1-RSVD
12HUSB3_SSTX1+RSVD
13HGNDRSVD
14HUSB2_AUX-RSVD
15HUSB2_AUX+RSVD
16HGNDRSVD
17HUSB3_AUX-RSVD
18HUSB3_AUX+RSVD
68HRSVDPCIe56_TX-
69HRSVDPCIe56_TX+
71HCSI1_RX0-PCIe57_TX-
72HCSI1_RX0+PCIe57_TX+
74HCSI1_RX1-PCIe58_TX-
75HCSI1_RX1+PCIe58_TX+
77HCSI1_RX2-PCIe59_TX-
78HCSI1_RX2+PCIe59_TX+
80HCSI1_RX3-PCIe60_TX-
81HCSI1_RX3+PCIe60_TX+
83HCSI1_CLK-PCIe61_TX-
84HCSI1_CLK+PCIe61_TX+
86HCSI1_I2C_CLKPCIe62_TX-
87HCSI1_I2C_DATPCIe62_TX+
88HCSI1_MCLKGND
89HCSI1_RST#PCIe63_TX-
90HCSI1_ENAPCIe63_TX+
98HETH0-1_MDIO_CLKETH0-3_MDIO_CLK
99HETH0-1_MDIO_DATETH0-3_MDIO_DAT
# 2.2. COM-HPC Client and COM-HPC Mini Pinout Differences The pinout differences between the COM-HPC Client and the COM-HPC Mini are well covered in the COM-HPC Base Specification Revision 1.20 Section 10. Please refer to that document. # 3. Reference Schematics and Block Diagrams # 3.1. Sources for Technical Materials The schematic diagrams, block diagrams and mechanical diagrams in this document were contributed by several companies and organizations, including Adlink, Advantech, Avnet Integrated, Bielefeld University, congatec, Intel, Kontron, Samtec and SECO. Hence the graphic styles vary a bit. An effort has been made to provide part numbers in the drawings that can be located in a web search (except for small generic parts). # 3.2. Schematic Conventions Schematic examples are drawn with signal directions shown per the Figure below. Signals that connect directly to the COM-HPC connector are flagged with the text “COM” in the off-page connect symbol, as shown in Figure 1 below. Nets that connect to the COM-HPC Module are named per the PICMG COM-HPC specification in almost all cases. Figure 1: Schematic Conventions ![The diagram depicts a central block labeled **IC** (a blue rectangle) with connections on both its left and right sides. **Left Side Connections:** * **Output from IC**: Connects to a red-outlined arrowhead pointing left (away from the IC). * **Input to IC**: Connects to a red-outlined arrowhead pointing right (towards the IC). * **Bidir Signal**: Connects to a red-outlined arrowhead pointing left (away from the IC). * **Output from IC to Module**: Connects to a red-outlined box containing the text **COM**, with an arrowhead pointing left (away from the IC). * **Input to IC from Module**: Connects to a red-outlined box containing the text **COM**, with an arrowhead pointing right (towards the IC). * **Bidir Signal to / from Module**: Connects to a red-outlined box containing the text **COM**, with an arrowhead pointing left (away from the IC). **Right Side Connections:** * **Output from IC**: Connects from the IC to a red-outlined arrowhead pointing right (away from the IC). * **Input to IC**: Connects from the IC to a red-outlined arrowhead pointing left (towards the IC). * **Bidir Signal**: Connects from the IC to a red-outlined arrowhead pointing right (away from the IC). * **Output from IC to Module**: Connects from the IC to a red-outlined box containing the text **COM**, with an arrowhead pointing right (away from the IC). * **Input to IC from Module**: Connects from the IC to a red-outlined box containing the text **COM**, with an arrowhead pointing left (towards the IC). * **Bidir Signal to / from Module**: Connects from the IC to a red-outlined box containing the text **COM**, with an arrowhead pointing right (away from the IC).](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/332460568a30a45b516015229041981878d3eaa97c30070f2765ca8231962fea.jpg) Power nets shown in the sample schematics and drawings are labeled, for the most part, per the Table below. The power rail behavior under the various system power states is shown in the Table. Table 3: Power Net Naming
Power NetS0 OnS3 Suspend to RAMS4 Suspend to DiskS5 Soft OffG3 Mechanical Off
+12V_S12Voffoffoffoff
+5V_S5Voffoffoffoff
+3.3V_S3.3Voffoffoffoff
+1.5V_S1.5Voffoffoffoff
+2.5V_S2.5Voffoffoffoff
+5V_A5V5V5V5Voff
+3.3V_A3.3V3.3V3.3V3.3Voff
VCC_RTC3.0V3.0V3.0V3.0V3.0V
# 3.3. Ethernet NBASE-T A typical NBASE-T implementation is shown in Figure 2 below. The “N” refers to the link speed, and may be 10 Mbps, 100 Mbps, 1 Gbps, 2.5 Gbps, 5 Gbps or 10 Gbps. However not all speeds may be available on all Module designs. All COM-HPC Modules are required to support at least the 1 Gbps rate. This example shows a “Mag-Jack” (an 8 pin RJ45 jack with integrated isolation magnetics) from Wurth Electronics, p/n 7499611420. This part is claimed by Wurth to support 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps data rates. There are many similar parts from Wurth and from vendors such as Bel-Fuse, Pulse Electronics and others. It may be advisable to check with your Module vendor on the suitability of chosen parts. Ethernet RJ45 jacks (including Mag-Jacks and jacks that require external magnetics) come in “tab-up” and “tab-down” versions. The Wurth part shown here is “tab-up”. If a “tab-down” part is used then the PCB layout is impacted as the pin orientation is effectively flipped 180 degrees. Implementing magnetics that are external to the jack is of course possible but it is trickier. It may be necessary in certain situations that require a higher than normal isolation between the Ethernet magnetics primary and secondary sides. This can be the case in safety critical designs such as medical equipment. The colors and meanings of the colors used for NBASE-T LEDs are not standardized in the industry. The scheme shown in the diagram below is suggested for COM-HPC but not required The diagram below shows ESD protection diode arrays (Texas Instruments TPD4E02B04) protecting the NBASE-T differential pairs. Many similar parts are available from other vendors. Make sure the selected part has a suitably low pin capacitance. It is very important that the parts (D43 and D44 in the Figure 2) are placed close to the connector and are routed in a “no stub” fashion. For example the net NBASET0+ in the Figure 2 should hit D43 pin 6 and continue under the D43 package to catch pin 5 and then on to the RJ45 connector. Pins may be swapped for easier routing, as long as the pairs are kept together and the no-stub routing is followed. Figure 2: NBASE-T ![X37 NBASET0_MD10+ COM NBASET0_MD10+ 8 NBASET0_MD10- COM NBASET0_MD10- 9 NBASET0_MD11+ COM NBASET0_MD11+ 3 NBASET0_MD11- COM NBASET0_MD11- 2 NBASET0_MD12+ COM NBASET0_MD12+ 4 NBASET0_MD12- COM NBASET0_MD12- 5 NBASET0_MD13+ COM NBASET0_MD13+ 11 NBASET0_MD13- COM NBASET0_MD13- 12 D1+ CD1 D1- D2+ CD2 D2- D3+ CD3 D3- D4+ CD4 D4- LED2_GK LED2_GA G G/Y WE_7499611420 +3.3V_A 13 14 NBASET0_LA# C608 470p 0402 50V R394 330R 0402 COM NBASET0_LINK_ACT# COM NBASET0_LINK_ACT# LED1_YK LED1_GA/YA LED1_GK NBASET0_LMAX# 15 16 17 NBASET0_LMID# R397 330R 0402 COM NBASET0_LINK_MAX_SPEED# R398 330R 0402 COM NBASET0_LINK_MAX_SPEED# COM NBASET0_LINK_MAX_SPEED# SH2 SH1 C609 470p 0402 50V C610 470p 0402 50V](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/a06fdd03e7582c938a405450581eb19d17d03977d32c43cfd0f6aee3409eed98.jpg) ![D43 NBASET0_MD10+ 6 5 NBASET0_MD10+ NBASET0_MD10- 7 4 NBASET0_MD10- NBASET0_MD11- 8 3 NBASET0_MD11- NBASET0_MD11+ 9 2 NBASET0_MD11- NBASET0_MD11+ 10 1 NBASET0_MD11+ TI_TPD4E02B04 D44 NBASET0_MD12+ 6 5 NBASET0_MD12+ NBASET0_MD12- 7 4 NBASET0_MD12- NBASET0_MD13- 8 3 NBASET0_MD13- NBASET0_MD13+ 9 2 NBASET0_MD13+ NBASET0_MD13+ 10 1 NBASET0_MD13+ TI_TPD4E02B04](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/1c0fb697aeff9ca94101629f8533f60f20be0d6fdb5ddb913e47e49642376ede.jpg) ![NBASET0_SDP COM 1 2 1 2 X36 XMOLEX530470210 NBASET0_CTREF COM R393 DNI 0R 0402 NBASET0_CT0 R395 DNI 0R 0402 NBASET0_CT1 R396 DNI 0R 0402 NBASET0_CT2 R399 DNI 0R 0402 NBASET0_CT3 C607 1u 0603 25V C611 C612 C613 C614 4x 100n 0402 25V Note: Connection of Center Tap should be adjusted depending on Phy used on COM-HPC module. Schematic shown here should offer stuffing options for all common architectures (separated caps at center tap, individual center taps shorted, adjustable CT capcitor values)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/7df7048338df5cf6e524eb6419fb057f812b7944ea0d7348ce4f5d5571215ad4.jpg) This example applies to the COM-HPC Mini as well. The LED voltage feeds are left at 3.3V to allow sufficient forward voltage to operate the LEDs. # 3.4. Ethernet KR and KR4 This document section is not relevant for the COM-HPC Mini. The Ethernet KR interfaces consist of a single TX pair and single RX pair. These pairs are capacitively coupled off of the COM-HPC Module – either on the Carrier board (for Module to PHY or Module to Module situations) or within the SFP assemblies. Ethernet KR4 interfaces are comprised of four TX pairs and four RX pairs, capacitively coupled off of the COM-HPC Module, as per the KR interfaces. In order to save pins, the side band signals for the 10G / 25G / 40G / 100G Ethernet KR interfaces are serialized on the Module silicon per an Intel convention known as CEI. This is an acronym for “Common Electrical Interface”. The serialized CEI signals need to be deserialized on the Carrier Board. The block diagrams in this section describe which components are needed and what the functions of the deserialized nets are. The Ethernet KR LED information is carried on one I2C bus per four Ethernet KR channels, known as a Quad. The I2C buses are named ETH0-3\_I2C\* (where the \* indicates the final characters of the net name in that signal group) and ETH4-7\_I2C\* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1\_I2C\*. There is one MDIO bus per Quad available to configure the PHYs on the Carrier Board. The MDIOs are named ETH0-3\_MDIO\* and ETH4-7\_MDIO\* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1\_MDIO\*. The Reset and Interrupt signals also follow the same naming convention. The SDP signals are more critical in timing and are available directly. # 3.4.1. Ethernet KR CEI Block Diagrams Ethernet KR CEI concepts are illustrated in block diagram format in Figures 3 through 9 on the following pages. Many of the details of these implementations are vendor NDA protected. Some references to vendor document numbers for confidential material are listed after each Figure, if material is available. Designers interested in these materials need to contact the silicon vendors directly and work out the necessary NDAs. Figure 3: Intel SoC with CEI Boundary ![The diagram illustrates the signal connections between three main vertical sections: **Intel SoC** (labeled 'New'), **Connector** (labeled 'COM-HPC Server'), and **CEI0 Boundary** / **CEI1 Boundary**. **Top Section (ETH0-3 / CEI0):** * **Blocks:** * **Intel SoC:** ETH(0..3), ETH0-3_MDIO, ETH_I2C_0, ETH_TIMESYNC0, ETH_TIMESYNC1, ETH_TIMESYNC2, ETH_TIMESYNC3, ETH_LED11, ETH_LED9, ETH_LED10. * **Connector:** ETH(0:3), ETH0-3_MDIO, ETH0-3_I2C, ETH0_SDP, ETH1_SDP, ETH2_SDP, ETH3_SDP, ETH0-3_PRSNT#, ETH0-3_PHY_RST#, ETH0-3_INT#, ETH0-3_PHY_IN#. * **CEI0 Boundary:** CEI_PMD_L(0:3), CEI_ADDR0=0, CEI_ADDR1=1, CEI_ADDR2=0, CEI_MDIO, CEI_I2C, CEI_PRSNT#, CEI_RESET#, CEI_INT#. * **Connections:** * **ETH(0..3)** connects bidirectionally (blue arrows) to **ETH(0:3)**, which connects bidirectionally (blue arrows) to **CEI_PMD_L(0:3)**. * **ETH0-3_MDIO** connects bidirectionally (red arrows) to **ETH0-3_MDIO**, which connects bidirectionally (red arrows) to **CEI_MDIO**. * **ETH_I2C_0** connects bidirectionally (green arrows) to **ETH0-3_I2C**, which connects bidirectionally (green arrows) to **CEI_I2C**. * **ETH_TIMESYNC0** through **ETH_TIMESYNC3** connect bidirectionally (orange arrows) to **ETH0_SDP** through **ETH3_SDP** respectively. * **ETH_LED11** is connected from **ETH0-3_PRSNT#** (purple arrow left), which is connected from **CEI_PRSNT#** (purple arrow left). * **ETH_LED9** is connected from **ETH0-3_PHY_RST#** (purple arrow left), which is connected from **CEI_RESET#** (purple arrow left). * **ETH_LED10** is connected from **ETH0-3_INT#** (red arrow left), which is connected from **CEI_INT#** (red arrow left). * **ETH0-3_PHY_IN#** is connected from **CEI_INT#** (red arrow left). **Bottom Section (ETH4-7 / CEI1):** * **Blocks:** * **Intel SoC:** ETH(4..7), ETH4-7_MDIO, ETH_I2C_1, ETH_TIMESYNC4, ETH_TIMESYNC5, ETH_TIMESYNC6, ETH_TIMESYNC7, ETH_GPIO5, ETH_GPIO3, ETH_GPIO4. * **Connector:** ETH(4:7), ETH4-7_MDIO, ETH4-7_I2C, ETH4_SDP, ETH5_SDP, ETH6_SDP, ETH7_SDP, ETH4-7_PRSNT#, ETH4-7_PHY_RST#, ETH4-7_INT#, ETH4-7_PHY_IN#. * **CEI1 Boundary:** CEI_PMD_L(4:7), CEI_ADDR0=1, CEI_ADDR1=1, CEI_ADDR2=0, CEI_MDIO, CEI_I2C, CEI_PRSNT#, CEI_RESET#, CEI_INT#. * **Connections:** * **ETH(4..7)** connects bidirectionally (blue arrows) to **ETH(4:7)**, which connects bidirectionally (blue arrows) to **CEI_PMD_L(4:7)**. * **ETH4-7_MDIO** connects bidirectionally (red arrows) to **ETH4-7_MDIO**, which connects bidirectionally (red arrows) to **CEI_MDIO**. * **ETH_I2C_1** connects bidirectionally (green arrows) to **ETH4-7_I2C**, which connects bidirectionally (green arrows) to **CEI_I2C**. * **ETH_TIMESYNC4** through **ETH_TIMESYNC7** connect bidirectionally (orange arrows) to **ETH4_SDP** through **ETH7_SDP** respectively. * **ETH_GPIO5** is connected from **ETH4-7_PRSNT#** (purple arrow left), which is connected from **CEI_PRSNT#** (purple arrow left). * **ETH_GPIO3** is connected from **ETH4-7_PHY_RST#** (purple arrow left), which is connected from **CEI_RESET#** (purple arrow left). * **ETH_GPIO4** is connected from **ETH4-7_PHY_IN#** (red arrow left), which is connected from **CEI_INT#** (red arrow left). * **ETH4-7_INT#** is connected from **CEI_INT#** (red arrow left) and points left towards **ETH_GPIO3**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/07a2126e63bdd55534c4a07e4b47a001e96059161309322818be69125102dc88.jpg) For further details on this configuration, refer to NDA protected Intel documents 620640 and 631178. Figure 4: Intel CEI 4x SFP28 ![**Labeled Blocks:** * Connector (COM-HPC Server) * CEI0 Boundary * CEI1 Boundary * PCA 9546 A MUX * PCA 9575 I/O * EEPROM * PCA9685 LED * PMD SFP_0 * PMD SFP_1 * PMD SFP_2 * PMD SFP_3 * P0_SPD_A LED * P0_SPD_B LED * P0_ACT_LED * P1_SPD_A LED * P1_SPD_B LED * P1_ACT_LED * P2_SPD_A LED * P2_SPD_B LED * P2_ACT_LED * P3_SPD_A LED * P3_SPD_B LED * P3_ACT_LED **Connections:** * **From Connector to CEI0 Boundary:** * `ETH(0:3)` connects to `CEI_PMD_L(0:3)` * `ETH0-3_MDIO` connects to `CEI_MDIO` * `ETH0-3_I2C` connects to `CEI_I2C` * `ETH0-3_PRSNT#` connects to `CEI_PRSNT#` * `ETH0-3 PHY_RST#` connects to `CEI_RESET#` * `ETH0-3_INT#` connects to `CEI_INT#` * **From Connector to CEI1 Boundary:** * `ETH(4:7)` connects to `CEI_PMD_L(4:7)` * `ETH4-7_MDIO` connects to `CEI_MDIO` * `ETH4-7_I2C` connects to `CEI_I2C` * `ETH4-7_PRSNT#` connects to `CEI_PRSNT#` * `ETH4-7 PHY_RST#` connects to `CEI_RESET#` * `ETH4-7_INT#` connects to `CEI_INT#` * **Between CEI0 and CEI1 Boundaries:** * `CEI_I2C` (CEI0) connects to `CEI_I2C` (CEI1) * `CEI_PRSNT#` (CEI0) connects to `CEI_PRSNT#` (CEI1) * `CEI_RESET#` (CEI0) connects to `CEI_RESET#` (CEI1) * **From CEI Blocks to PCA 9546 A MUX:** * `CEI_I2C` connects to `I2C` * **From PCA 9546 A MUX to SFP Blocks:** * `I2C0` connects to `I2C` of PMD SFP_0 * `I2C1` connects to `I2C` of PMD SFP_1 * `I2C2` connects to `I2C` of PMD SFP_2 * `I2C3` connects to `I2C` of PMD SFP_3 * **From CEI Blocks to PCA 9575 I/O:** * `CEI_I2C` connects to `I2C` * `CEI_PRSNT#` connects to `ResetN` * `CEI_RESET#` connects to `ResetN` * **From PCA 9575 I/O to SFP Blocks:** * `P0.0` connects to `RX_Loss` of PMD SFP_0 * `P1.0` connects to `ModPresN` of PMD SFP_0 * `P1.1` connects to `RS` of PMD SFP_0 * `P0.1` connects to `RX_Loss` of PMD SFP_1 * `P1.2` connects to `ModPresN` of PMD SFP_1 * `P1.3` connects to `RS` of PMD SFP_1 * `P0.2` connects to `RX_Loss` of PMD SFP_2 * `P1.4` connects to `ModPresN` of PMD SFP_2 * `P1.5` connects to `RS` of PMD SFP_2 * `P0.3` connects to `RX_Loss` of PMD SFP_3 * `P1.6` connects to `ModPresN` of PMD SFP_3 * `P1.7` connects to `RS` of PMD SFP_3 * **From PCA 9575 I/O to EEPROM:** * `P0.4` connects to `WP` * **From PCA 9575 I/O to CEI0 Boundary:** * `IntN` connects to `CEI_INT#` * **From CEI0 Boundary to SFP Blocks (PMD):** * `CEI_PMD_L(0:3)` connects to `PMD` of PMD SFP_0, PMD SFP_1, PMD SFP_2, and PMD SFP_3 * **From PCA 9575 I/O to EEPROM:** * `I2C` connects to `I2C` (Shared bus) * **From CEI Blocks to EEPROM:** * `CEI_I2C` connects to `I2C` * **From CEI Blocks to PCA9685 LED:** * `CEI_I2C` connects to `I2C` * **From PCA9685 LED to LED Blocks:** * `LED0` connects to P0_SPD_A LED * `LED1` connects to P0_SPD_B LED * `LED2` connects to P0_ACT_LED * `LED3` connects to P1_SPD_A LED * `LED4` connects to P1_SPD_B LED * `LED5` connects to P1_ACT_LED * `LED6` connects to P2_SPD_A LED * `LED7` connects to P2_SPD_B LED * `LED8` connects to P2_ACT_LED * `LED9` connects to P3_SPD_A LED * `LED10` connects to P3_SPD_B LED * `LED11` connects to P3_ACT_LED * **PCA9685 LED Inputs:** * `EXTCLK` (Input) * `OEn` (Input)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/3f3d0ff7548e08422f4840c0684b374e7615196a1ed493241e26ee966d36a46d.jpg) This configuration is not supported by additional Intel documentation at the time of this writing. Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827 ![Flowchart](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/0568bcd7c1013f7ef5b980d54dbd8cfdfb0c22872917b9626f52a6b75528df27.jpg) For further details on this configuration, refer to NDA Intel document 636564. Figure 6: Intel CEI QSFP28 with Retimer C827/XL827 ![Based on the provided block diagram, here are the labeled blocks and their connections: **Labeled Blocks:** 1. **Connector COM-HPC Server** 2. **CEI0 Boundary** 3. **CEI1 Boundary** 4. **C82 7/XL827 Parkvale** 5. **QSFP** 6. **PCA 9575 I/O** 7. **EEPROM** 8. **PCA9685 LED** **Connections:** * **Blue PMD Lines:** * `ETH(0:3)` connects to `CEI_PMD_L(0:3)`, which connects to `PMD(0...3)` in **C82 7/XL827**, which connects to `PMD(0...3)` in **QSFP**. * `ETH(4:7)` connects to `CEI_PMD_L(4:7)` (endpoint). * **Red MDIO & Control Lines:** * `ETH0-3_MDIO` connects to `CEI_MDIO`, which connects to `MDIO` in **C82 7/XL827**. * `ETH4-7_MDIO` connects to `CEI_MDIO` in **CEI1 Boundary** (endpoint). * `ETH0-3_PHY_RST#` connects to `CEI_RESET#` in **CEI0 Boundary**, which connects to `ResetN` in **PCA 9575 I/O**. * `ETH0-3_INT#` and `ETH0-3_PHY_INT#` connect to `CEI_INT#` in **CEI0 Boundary**, which connects to `IntN` in **PCA 9575 I/O**. * `ETH4-7_PHY_RST#` connects to `CEI_RESET#` in **CEI1 Boundary**, which connects to `ResetN` in **PCA 9575 I/O**. * `ETH4-7_INT#` and `ETH4-7_PHY_INT#` connect to `CEI_INT#` in **CEI1 Boundary**, which connects to `IntN` in **PCA 9575 I/O**. * **Green I2C Bus Lines:** * `ETH0-3_I2C` connects to `CEI_I2C` in **CEI0 Boundary**. * `ETH4-7_I2C` connects to `CEI_I2C` in **CEI1 Boundary**. * These lines merge and connect to `I2C` in **C82 7/XL827**, which connects to `I2C` in **PCA 9575 I/O**, which connects to `I2C` in **EEPROM**, which connects to `I2C` in **PCA9685 LED**. * `CEI_PRSNT#` (from both boundaries) connects to the I2C bus line (indicated by green dots), routing to `I2C` in **PCA 9575 I/O**. * **Purple Address/Status Lines:** * `CEI_ADDR0=0`, `CEI_ADDR1=1`, `CEI_ADDR2=0` (from **CEI0 Boundary**) connect to `Addr0`, `Addr1`, `Addr2` in **C82 7/XL827**. * `Addr4=0` in **C82 7/XL827** connects to `P0.0` in **PCA 9575 I/O**. * **PCA 9575 I/O to QSFP Connections:** * `P0.1` and `P1.1` connect to `ResetN` in **QSFP**. * `P0.2` and `P1.2` connect to `IntN` in **QSFP**. * `P0.3` connects to `PresentN` in **QSFP**. * `P0.4` connects to `LP Mode` in **QSFP**. * **Other Connections:** * `P1.6` in **PCA 9575 I/O** connects to `WP` in **EEPROM**. * **PCA9685 LED** outputs connect to LED labels: * `LED0` → `P0_SPD_A_LED` * `LED1` → `P0_SPD_B_LED` * `LED2` → `P0_ACT_LED` * `LED3` → `P1_SPD_A_LED` * `LED4` → `P1_SPD_B_LED` * `LED5` → `P1_ACT_LED` * `LED6` → `P2_SPD_A_LED` * `LED7` → `P2_SPD_B_LED` * `LED8` → `P2_ACT_LED` * `LED9` → `P3_SPD_A_LED` * `LED10` → `P3_SPD_B_LED` * `LED11` → `P3_ACT_LED` * `LED12` → `P0_DISABLE` * `LED13` → `P1_DISABLE` * `LED14` → `P2_DISABLE` * `LED15` → `P3_DISABLE` * `EXTCLK` and `OEn` have input arrows pointing to **PCA9685 LED**. * **Unconnected Labels:** * `ETH0_SDP`, `ETH1_SDP`, `ETH2_SDP`, `ETH3_SDP`, `ETH4_SDP`, `ETH5_SDP`, `ETH6_SDP`, `ETH7_SDP` are listed in the Connector block but have no visible connection lines.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/090e8810c983d5768c26c281710a25fb542404b1672480763030f54721e2eca3.jpg) For further details on this configuration, refer to NDA Intel document 636566. Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4 ![Based on the provided block diagram, here is a concise description of the labeled blocks and their connections: **Labeled Blocks:** 1. **Connector COM-HPC Server** (Leftmost column) 2. **CEI0 Boundary** (Top left) 3. **CEI1 Boundary** (Bottom left) 4. **X557-AT4 Coppervale** (Top middle) 5. **4x RJ-45 10GBASE-T** (Top right) 6. **PCA 9575 I/O** (Middle right) 7. **EEPROM** (Bottom middle) 8. **PCA9685 LED** (Bottom right) **Connections:** * **Connector COM-HPC Server to Boundaries:** * Connects to **CEI0 Boundary** via: `ETH(0:3)` (Blue), `ETH0-3_MDIO` (Red), `ETH0-3_I2C` (Green), `ETH0_SDP`/`ETH1_SDP`/`ETH2_SDP`/`ETH3_SDP` (Purple), `ETH0-3_PRSNT#` (Purple), `ETH0-3_PHY_RST#` (Purple), and `ETH0-3_PHY_INT#` (Red). * Connects to **CEI1 Boundary** via: `ETH(4:7)` (Blue), `ETH4-7_MDIO` (Red), `ETH4-7_I2C` (Green), `ETH4_SDP`/`ETH5_SDP`/`ETH6_SDP`/`ETH7_SDP` (Purple), `ETH4-7_PRSNT#` (Purple), `ETH4-7_PHY_RST#` (Purple), and `ETH4-7_PHY_INT#` (Red). * **CEI0 Boundary to X557-AT4 Coppervale:** * `CEI_PMD_L(0:3)` (Blue) (-) `PMD(0_3)` * `CEI_ADDR0=0`, `CEI_ADDR1=1`, `CEI_ADDR2=0` (Purple) connect to `Addr0`, `Addr1`, `Addr2`. * `CEI_MDIO` (Red) connects to `MDIO` (Red arrow pointing left). * `CEI_RESET#` (Purple) and `CEI_INT#` (Red) are inputs/outputs. * **X557-AT4 Coppervale to 4x RJ-45 10GBASE-T:** * `MDI0_(0:3)`, `MDI1_(0:3)`, `MDI2_(0:3)`, `MDI3_(0:3)` (Blue) connect to corresponding `MDI0`, `MDI1_(0:3)`, `MDI2_(0:3)`, `MDI3_(0:3)`. * `LED_P0`, `LED_P1`, `LED_P2`, `LED_P3` (Red) connect to corresponding `LED_P0`, `LED_P1`, `LED_P2`, `LED_P3`. * **X557-AT4 Coppervale to PCA 9575 I/O:** * `Addr0`, `Addr1`, `Addr2`, `Addr3` (Purple) connect to `P0.4`, `P0.5`, `P0.6`, `P0.7`. * `LED_P0`, `LED_P1`, `LED_P2`, `LED_P3` (Red) connect to `P0.0`, `P0.1`, `P0.2`, `P0.3`. * **CEI0 Boundary to PCA 9575 I/O:** * `CEI_I2C` (Green) connects to `I2C`. Note: `CEI_PRSNT#` has a green dot connecting it to the `I2C` line. * `CEI_RESET#` (Purple) connects to `ResetN`. * `CEI_INT#` (Red) connects to `IntN`. * **PCA 9575 I/O to EEPROM:** * `P1.6` (Red) connects to `WP`. * **I2C Bus Connections:** * The green line from `CEI_I2C` connects to `I2C` on **PCA 9575 I/O**, **EEPROM**, and **PCA9685 LED**. * **PCA9685 LED Outputs:** * `LED0` to `LED15` connect to the rightmost labels: `P0_SPD_A_LED`, `P0_SPD_B_LED`, `P0_ACT_LED`, `P1_SPD_A_LED`, `P1_SPD_B_LED`, `P1_ACT_LED`, `P2_SPD_A_LED`, `P2_SPD_B_LED`, `P2_ACT_LED`, `P3_SPD_A_LED`, `P3_SPD_B_LED`, `P3_ACT_LED`, `P0_DISABLE`, `P1_DISABLE`, `P2_DISABLE`, `P3_DISABLE`. * **CEI1 Boundary:** * While labeled with `CEI_PMD_L(4:7)`, `CEI_MDIO`, `CEI_I2C`, etc., there are no visible connections extending from this block to the right-side components (X557-AT4, PCA 9575, etc.) in this diagram.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/dfad09baff1d5a80f2f1241cc48464fca10c4dd0fc83256d3ed63225bce94088.jpg) For further details on this configuration, refer to NDA Intel document 613899. Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543 ![Flowchart](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6a81ef39676fc547d486c2410bd299dfb2117a58842677342db6c07fa11af8d3.jpg) For further details on this configuration, refer to NDA Intel document 613900. Figure 9: AMD SoC 4xSFP+ with CS4223 Retimer ![The flowchart/block diagram depicts the signal connections between an AMD SoC, a connector, interface boundaries, and external components (CS42 23, PCA9545A MUX, PCA9555 I/O) leading to SFP modules. **Labeled Blocks:** * AMD SoC EPYC3000 * Connector COM-HPC Server * CEI0 Boundary * CEI1 Boundary * CS42 23 * PCA9545A MUX * PCA9555 I/O * PMD SFP_0 * PMD SFP_1 * PMD SFP_2 * PMD SFP_3 **Connections:** * **AMD SoC EPYC3000 to Connector COM-HPC Server:** * ETH(0:3) (bidirectional) * SM Bus (bidirectional) * INTy# (input to SoC) * PLTRST# (input to SoC) * INTx# (input to SoC) * **Connector COM-HPC Server to CEI0 Boundary:** * ETH(0:3) to CEI_PMD_L(0:3) * ETH0-3_MDIO to CEI_MDIO * ETH0-3_PRSNT# to CEI_PRSNT# * ETH0-3_PHY_RST# to CEI_RESET# * ETH0-3_PHY_INT# to CEI_INT# * ETH0-3_INT# to CEI_INT# * **Connector COM-HPC Server to CEI1 Boundary:** * ETH4-7_PRSNT# to CEI_PRSNT# * ETH4-7_PHY_RST# to CEI_RESET# * **CEI0 Boundary to External Components:** * CEI_PMD_L(0:3) to CS42 23 PMD(0..3) * CEI_PRSNT# to PCA9545A MUX ResetN * CEI_INT# to PCA9555 I/O IntN * **Connector COM-HPC Server to PCA9545A MUX:** * ETH0-3_I2C to PCA9545A MUX I2C * **CS42 23 to PMD SFP Modules:** * PMD0 to PMD SFP_0 * PMD1 to PMD SFP_1 * PMD2 to PMD SFP_2 * PMD3 to PMD SFP_3 * **PCA9545A MUX to PMD SFP Modules:** * I2C0 to PMD SFP_0 I2C * I2C1 to PMD SFP_1 I2C * I2C2 to PMD SFP_2 I2C * I2C3 to PMD SFP_3 I2C * **PCA9555 I/O to PMD SFP Modules:** * P1.7 to PMD SFP_0 TX_Disable * P1.6 to PMD SFP_1 TX_Disable * P1.5 to PMD SFP_2 TX_Disable * P1.4 to PMD SFP_3 TX_Disable * P1.3 to PMD SFP_0 TX_Fault * P1.2 to PMD SFP_1 TX_Fault * P1.1 to PMD SFP_2 TX_Fault * P1.0 to PMD SFP_3 TX_Fault * P0.7 to PMD SFP_0 RX_Loss * P0.6 to PMD SFP_1 RX_Loss * P0.5 to PMD SFP_2 RX_Loss * P0.4 to PMD SFP_3 RX_Loss * P0.3 to PMD SFP_0 ModPresN * P0.2 to PMD SFP_1 ModPresN * P0.1 to PMD SFP_2 ModPresN * P0.0 to PMD SFP_3 ModPresN](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/dcbb2ea21dc961c79135c006dde860612bf1deeb8aabb687b39524143cef4661.jpg) For further details on this configuration, contact AMD. # 3.4.2. PHY Addresses Table 4: MDIO Addresses for Intel POR External PHYs
PHYMDIO Address (Decimal)Ethernet Quad / Port
Intel “Parkvale”2Quad0
3Quad1
Intel “Coppervale”8Quad0 Port0
9Quad0 Port1
10Quad0 Port2
Marvell offers a similar PHY11Quad0 Port3
12Quad1 Port0
13Quad1 Port1
14Quad1 Port2
15Quad1 Port3
# 3.5. Serial ATA # 3.5.1. Cabled SATA The COM-HPC pinouts offer up to two SATA ports, designated SATA0 and SATA1. The implementation for a cabled interface is straightforward, as illustrated in Figure 10 below. No Carrier coupling capacitors are needed as they are specified to be present on the Module. The connections between the Module and the SATA connector are simple differential pairs. Some routing rules may be found in Section 4. below. Two common connector styles used for cabled SATA implementations are shown in the Figure 10. The upper image shows a 7 pin data-only connector. Power to the SATA drive is handled separately in this case. The lower image in the Figure 10 shows a 22 pin connector that handles SATA data and power. There are three power rails defined on this connector, but all three are not necessarily used. Smaller format drives tend to use just one or two of these rails, Check the drive specifications. Figure 10 below shows two typical COM-HPC cabled SATA. Note how the data pair polarity order flips along the connector pins: TX+ TX- GND RX- RX+ … this is not a mistake, but is part of the SATA specification. Figure 10: Serial ATA – Cabled ![SATA0_TX+ SATA0_TX- SATA0_RX- SATA0_RX+ 1 2 3 4 5 6 7 SATA1 GND TX+ TX- GND RX- RX+ GND H1 LOTES_ABA-SAT-010-K21 H2](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/964dc68d9fc09d905bc6cf08f6404cc36775c1bd72b32fd55cd0eca8c3a24b6f.jpg) ![+12V_S +5V_S +3.3V_S SATA0_RX+ SATA0_RX- SATA0_TX- SATA0_TX+ P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 S7 S6 S5 S4 S3 S2 S1 H4 H2 SATA1 1 2V 1 2V 1 2V GND RSVD GND VCC VCC VCC GND GND GND VCC3 VCC3 VCC3 GND RX+ RX- GND TX- TX+ GND H3 H1 MOLEX_47018-4001](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/8d1d006a86ace2b1e37661d01a9fc0dfe1e1122e2c6a7c58f7bf1a17a88f6cc4.jpg) This Figure 10 applies to the COM-HPC Mini except that Carrier based coupling caps on the SATA TX and RX pairs (4 capacitors) are needed. See COM-HPC Base Specification Rev. 1.20 Section 10. # 3.5.2. mSATA SSDs The SATA specification defines a small form factor card for SATA SSDs that is almost identical in mechanical and electrical definition to the PCI-SIG miniPCIe format. The same card connector and mounting holes are used. Both half size and full size cards are in use. Sometimes dual mini-PCIe / mSATA implementations are executed. This involves multiplexing four signals per the following Table: Table 5: mSATA Pin Mapping Relative to miniPCIe
MiniPCIe Card Pin NameMiniPCIe / mSATA Card Pin NumberPCIE Signal Relative to COM-HPC ModuleSATA Signal Relative to COM-HPC Module
PETPO33PCIe TX+SATA TX+
PETNO31PCIe TX-SATA TX-
PERPO25PCIe RX+SATA RX-
PERNO23PCIe RX-SATA RX+
The SATA\_RX- mapping to miniPCIe PERP0 and SATA\_RX+ to PERN0 is intentional per the SATA specification. The signals do not have to be multiplexed if a mSATA only or miniPCIe only implementation is desired. SSD implementations are largely moving away from the miniPCIe format and to M.2 formats. In the M.2 formats, there are PCIe interfaces defined (x1, x2 and x4) and a SATA interface defined, similar to the miniPCIe / mSATA pin sharing format shown in the Table above. The M.2 PCIe x 4 format, sometimes referred to as NVMe, offer a much higher interface bandwidth than mSATA. This mSATA information applies to the COM-HPC Mini as well. However the coupling capacitors on the SATA TX and RX pairs are moved off the Module for the Mini and onto the Carrier, close to the Mini Module connector pins. See the COM-HPC Base Specification Rev. 1.20 Section 10. # 3.5.3. M.2 SATA SSDs The PCI Express M.2 Specification defines several M.2 format SATA SSD options that may be used in COM-HPC systems. These include (but are not limited to): Socket 2 B-M Key (Table 3-23 in the PCI-SIG Version 4.0 M.2 document) Socket 3 M Key (Table 3-28) These are not diagrammed here as SATA SSD implementations seem to be losing ground to PCIe based SSD implementations. This M.2 SATA information applies to the COM-HPC Mini as well. However the coupling capacitors on the TX pair(s) are located on the Carrier, not on the Module, for the Mini. The coupling capacitors for the Module RX pair (the M.2 SATA card TX pair) are on the M.2 card. See COM-HPC Base Specification Rev. 1.2 Section 10. # 3.6. PCI Express # 3.6.1. General Notes The COM-HPC PCIe resources are divided into 5 Groups: Group 0 Low (8 lanes) ◦ Generally used for smaller links (x1, x2, x4) and slower PCIe link speeds (PCIe Gen 1,2,3). Group 0 High (8 lanes) ◦ Recommended for use with one or two PCIe x4 NVME SSD instances ◦ The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group Group 1 (16 lanes) 。 Recommended for PEG use ◦ The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group Group 2 (16 lanes) ◦ General purpose links – x16 or combinations of x8 and / or x4 Group 3 (16 lanes) ◦ Available on the Server pinout only Each PCIe Group listed above has it’s own 100 MHz PCIe Reference Clock pair from the COM-HPC Module. Additionally, there is a CLKREQ# (Clock Request) input to the Module for each PCIe Group. There is one additional PCIe link available on both the Client and Server pinouts. This is a x1 link for use with a Carrier BMC (Board Management Controller). The BMC PCIe link makes use of the Group 0 PCIe Reference Clock pair. If only a single PCIe link (of any link width – x1, x2, x4, x8 or x16) is used from a PCIe Group, then the COM-HPC PCIe Reference Clock pair may be used directly with the link target. If a Group uses more than one link (i.e. 2 or more links) then a Carrier Board PCIe Reference Clock buffer is needed for that Group. Many PCIe clock buffer products are available on the market. Buffers with 2,4,6 or 8 and more output pairs are available. The buffer must be appropriate for the fastest PCIe link in the Group (PCIe Gen 3, 4 or 5). Several examples are shown in the schematics below. If the link’s PCIe target is located on a slot card or a mezzanine board such as an M.2 site, the connector involved must be rated for the fastest PCIe link in use for that target. At the time of this writing, most such connectors are PCIe Gen 3 capable. Gen 4 and Gen 5 capable connectors are becoming available, most visibly from Amphenol FCI. The COM-HPC Mini allows the implementation of PCIe Groups 0 Low and 0 High, but the coupling caps for the Mini Module TX PCIe Group 0 Low pairs are located on the Carrier. Coupling caps for Mini RX Module lines are located on the add-in card EXCEPT for MXM cards and Carrier “device down” situations in which case the PCIe RX coupling caps are on the Carrier. The Mini further divides PCIe Group 0 low into two 4 lane groups, designated Group 0 Low A and Low B. See the COM-HPC Base Specification Revision 1.2 Section 10. COM-HPC Mini PCIe fill order guidelines are also covered there. # 3.6.2. PCI Express Coupling Capacitor Locations The proper positions for PCIe data pair coupling capacitors on COM-HPC Client and Server implementations is shown in Figure 11 below. COM-HPC Module TX pair coupling caps are on the COM-HPC Module. COM-HPC Module RX pair coupling caps are NOT on the COM-HPC Module. ◦ For most Device Up mezzanine card implementations (Slot card, Mini-PCIe, and M.2 card) the coupling caps are up on the mezzanine card, close to the mezzanine target device TX pins. The exception to this rule is with MXM-3 graphics cards: there are no PCIe coupling caps at all on a MXM-3 graphics card. The COM-HPC Module TX lines are AC coupled on the COM-HPC Module. The COM-HPC Module RX lines are AC coupled on the Carrier, near the MXM-3 Module TX pins. ◦ For Device Down implementations, the coupling caps are down on the Carrier board, close to the target device TX pins. Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded) ![This block diagram illustrates the connection topology between a module and PCIe add-in devices. **Labeled Blocks:** * **COM-HPC Module**: Located on the left, containing two sets of connection pins labeled: * Top set: **TX+**, **TX-**, **RX+**, **RX-** * Bottom set: **TX+**, **TX-**, **RX+**, **RX-** * **Connector**: A central block. * **Device Up**: Located in the top right grey area. It contains a white box with connection pins labeled **RX+**, **RX-**, **TX+**, **TX-** and the text **PCIe**, **Add-in**, **Device**. * **Device Down**: Located in the bottom right grey area. It contains a white box with connection pins labeled **RX+**, **RX-**, **TX+**, **TX-** and the text **PCIe**, **Add-in**, **Device**. * **Carrier Board**: Text label located at the bottom right. **Connections:** * **Top Path**: Four lines connect the top **TX+**, **TX-**, **RX+**, **RX-** pins of the **COM-HPC Module** to the **Connector**. From the **Connector**, lines connect to the **RX+**, **RX-**, **TX+**, **TX-** pins in the **Device Up** box. Capacitor symbols appear on the lines originating from **TX+** and **TX-** on the module side, and on the lines entering **TX+** and **TX-** on the device side. * **Bottom Path**: Four lines connect the bottom **TX+**, **TX-**, **RX+**, **RX-** pins of the **COM-HPC Module** directly to the **RX+**, **RX-**, **TX+**, **TX-** pins in the **Device Down** box. Capacitor symbols appear on the lines originating from **TX+** and **TX-** on the module side, and on the lines entering **TX+** and **TX-** on the device side.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/08ec838d3bb8fdea47c3646e81935760f47c0686c25a6df62840cfec392d0c3c.jpg) For COM-HPC Mini implementations, the TX pair caps for PCIe Group 0 Low move off the Module and onto the Carrier. See the COM-HPC Base Specification Revision 1.2 Section 10. # 3.6.3. PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key Figure 12: PCIe Device Down on Carrier – PCIe Group 0 Low – PCIe Lane 0 ![The diagram depicts a schematic for an Intel i210 Ethernet controller (labeled **U9** and **i210**), specifically showing 'SECTION 1 OF 4' of the device. It illustrates the PCIe, Wake, and Clocking interfaces. **Central Block:** * **U9 / i210**: The main chip block containing the pin connections. **Left Side Connections (Inputs/Outputs):** * **PCIe Transmits:** * Pin 24 (**PE_R+**) connects to **PCle0 TX+**, which leads to a **COM** block. * Pin 23 (**PE_R-**) connects to **PCle0 TX-**, which leads to a **COM** block. * **PCIe Clock:** * Pin 26 (**PECLK+**) connects to **PCle CLK G0L 0+**. * Pin 25 (**PECLK-**) connects to **PCle CLK G0L 0-**. * **Reset & Wake:** * Pin 17 (**PE_RST#**) connects to **PCI RESET G0L 0#**. * Pin 16 (**PE_WAKE#**) connects to **WAKE G0L 1#**. This line originates from a hexagonal connector labeled **WAKE0#**, passing through a 0 Ohm resistor (**R55**, 0402). * **SMBus Interface:** * Pin 34 (**SMB_CLK**) connects to **LAN1 SMB SCL**. It is pulled up by resistor **R64** (5.1Kohms) to **+3.3V S**. * Pin 36 (**SMB_DATA**) connects to **LAN1 SMB SDA**. It is pulled up by resistor **R65** (5.1Kohms) to **+3.3V S**. * Pin 35 (**SMB_ALRT#**) connects to **LAN1 SMB ALERT#**. It is pulled up by resistor **R66** (5.1Kohms) to **+3.3V S**. **Right Side Connections (Inputs/Outputs):** * **PCIe Receives:** * Pin 21 (**PE_T+**) connects via capacitor **C44** (0.22uF, 10V, 0402) to **PCle0 RX+**, which leads to a **COM** block. * Pin 20 (**PE_T-**) connects via capacitor **C45** (0.22uF, 10V, 0402) to **PCle0 RX-**, which leads to a **COM** block. * **MDIO / SII Interface (connected to tri-state buffers):** * Pin 2 (**NC_SI_CLK_IN**) connects to **NCSIO LAN CLK**. * Pin 3 (**NC_SI_CRS_DV**) connects to **NCSIO LAN CRS_DV**. * Pin 7 (**NC_SI_TX_EN**) connects to **NCSIO LAN TXEN**. * Pin 43 (**NC_SI_ARB_IN**) connects to **NCSIO LAN ARB_IN**. * Pin 44 (**NC_SI_ARB_OUT**) connects to **NCSIO LAN ARB_OUT**. The text 'To i210 Strapping Resistors' is located near these connections. * Pin 9 (**NC_SI_TXD0**) connects to **NCSIO LAN TXD(0)**. * Pin 8 (**NC_SI_TXD1**) connects to **NCSIO LAN TXD(1)**. * Pin 6 (**NC_SI_RXD0**) connects to **NCSIO LAN RXD(0)**. * Pin 5 (**NC_SI_RXD1**) connects to **NCSIO LAN RXD(1)**. **Footer Text:** * 'This reference sheet does not show the full Intel WGI210T device but only shows the PCIe, Wake, and Clocking interfaces'](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/afeb9e016d8d7c77b22522747b03fd7124cddd8b8acafb826828477a9a4102df.jpg) Figure 12 shows a portion of an Intel i210 Gigabit Ethernet implementation, the portion that is relevant to the COM-HPC Module interface. This Figure 12 shows the interface to the COM-HPC and to some Carrier board circuit elements such as an appropriate PCIe Clock buffer, shown later in this section. The key point of this Figure is that coupling caps (C44 and C45 in the Figure) are needed on the Carrier, for the Carrier target device TX pair pins. These are the PCIe RX lines for the Module. These Carrier coupling caps are to be placed close to the i210 device, in a symmetric manner consistent with high speed PCB design practices. Coupling caps for COM-HPC PCIe TX lines are on the Module. If the PCIe target device is a slot or mezzanine card, the coupling caps for the target device are on the slot or mezzanine card and not on the Carrier. - except for MXM graphics card implementations. This case is discussed in Section 3.6.7. below. The Figure 12 above applies to the COM-HPC Mini as well, except that series coupling capacitors are needed for the PCIe TX pair at the upper left portion of the Figure 12. There may need to be level translation on the WAKE0# signal if it is destined for a 1.8V level I/O. Figure 13: Mini-PCIe Site – PCIe Group 0 Low – PCIe Lane 1 ![+3.3V_S +3.3V_A +3.3V_S_GOL_MPCIE +3.3V_S_GOL_MPCIE +3.3V_S_GOL_MPCIE PCIe_CLK_GOL_1+ PCIe_CLK_GOL_1- PCIe1_RX+ PCIe1_RX- PCIe1_TX+ PCIe1_TX- PCI_RESET_GOL_1# PCIe_CLKREQ_GOL_1# WAKE0# R50 0ohms 400mA L1 USB4+ USB4- 2 3 PCIe_CLK_SDA 0ohms R47 0ohms R48 0ohms R42 0ohms 0402 0ohms WAKE_GOL_2# L1 USB4_CMC + USB4_CMC - 38 USB4_CMC_ 36 USB4_CMC_ 32 USB4_CMC_ 30 USB4_CMC_ 29 USB4_CMC_ 28 USB4_CMC_ 27 USB4_CMC_ 26 USB4_CMC_ 25 USB4_CMC_ 24 USB4_CMC_ 23 USB4_CMC_ 22 USB4_CMC_ 21 USB4_CMC_ 20 USB4_CMC_ 19 USB4_CMC_ 18 USB4_CMC_ 17 USB4_CMC_ 16 USB4_CMC_ 15 USB4_CMC_ 14 USB4_CMC_ 13 USB4_CMC_ 12 USB4_CMC_ 11 USB4_CMC_ 10 USB4_CMC_ 9 USB4_CMC_ 8 USB4_CMC_ 7 USB4_CMC_ 6 USB4_CMC_ 5 USB4_CMC_ 4 USB4_CMC_ 3 USB4_CMC_ 2 USB4_CMC_ 1 USB4_CMC_ 0.1uF C31 50V 0.1uF C30 50V 0.1uF C29 50V 0.1uF C28 50V 0.1uF C27 50V 0.1uF C26 50V 0.1uF C25 50V 0.1uF C24 50V 0.1uF C23 50V 0.1uF C22 50V 0.1uF C21 50V 0.1uF C20 50V 0.1uF C19 50V 0.1uF C18 50V 0.1uF C17 50V 0.1uF C16 50V 0.1uF C15 50V 0.1uF C14 50V 0.1uF C13 50V 0.1uF C12 50V 0.1uF C11 50V 0.1uF C10 50V 0.1uF C9 50V 0.1uF C8 50V 0.1uF C7 50V 0.1uF C6 50V 0.1uF C5 50V 0.1uF C4 50V 0.1uF C3 50V 0.1uF C2 50V 0.1uF C1 50V 0.1uF C0 50V 0.1uF C9 50V 0.1uF C8 50V 0.1uF C7 50V 0.1uF C6 50V 0.1uF C5 50V 0.1uF C4 50V 0.1uF C3 50V 0.1uF C2 55V 0HND C33 45×NC C32 47×NC C31 49×NC C30 52×NC C29 53×NC C28 54×NC C27 55×NC C26 56×NC C25 57×NC C24 58×NC C23 59×NC C22 60×NC C21 61×NC C20 62×NC C19 63×NC C18 64×NC C17 65×NC C16 66×NC C15 67×NC C14 68×NC C13 69×NC C12 70×NC C11 71×NC C10 72×NC C9 73×NC C8 74×NC C7 75×NC C6 76×NC C5 77×NC C4 78×NC C3 79×NC C2 80×NC C1 81×NC C0 82×NC C9 83×NC C8 84×NC C7 85×NC C6 86×NC C5 87×NC C4 88×NC C3 89×NC C2 90×NC C1 91×NC C9 92×NC C8 93×NC C7 94×NC C6 95×NC C5 96×NC C4 97×NC C3 98×NC C2 99×NC C1 100×NC R39 R38 R37 R36 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 FBN FB SS GND GND THMPAD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GUND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GDN HUHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHTHT HTTTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTNTTANTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTG T U V=1.5V IOUT=0.4A DC tolerance=2% +3.3V_S Vout=1.5V IOUT=0.4A DC tolerance=2% R49 R47 R46 R44 R42 R39 R38 R37 R36 R35 R34 R33 R32 R31 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 FBN FB SS S V D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N DN D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D N D MSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6ae50317209834de2dcb6ddf15fd2d3257f66c0590e4ca5a38f3ac2cc7294929.jpg) Figure 12 above applies to the COM-HPC Mini as well, except that series coupling capacitors are needed for the PCIe TX pair at the left portion of the Figure. Coupling caps for the PCIe RX pair are on the Mini-PCIe card. There may need to be level translation on the some of the single ended sideband signals (e.g. WAKE0# etc.) if they destined for a 1.8V level I/O. Figure 14: M.2 E-Key Site – WiFi Cards – PCIe Group 0 Low – PCIe Lane 2 ![ Component Value :--- :--- +3.3V_S_G0L_M2_1 74 +3.3V_S_G0L_M2_1 72 +3.3V_S_G0L_M2_1 70 +3.3V_S_G0L_M2_1 68 +3.3V_S_G0L_M2_1 66 +3.3V_S_G0L_M2_1 64 +3.3V_S_G0L_M2_1 62 +3.3V_S_G0L_M2_1 60 +3.3V_S_G0L_M2_1 58 +3.3V_S_G0L_M2_1 56 +3.3V_S_G0L_M2_1 54 +3.3V_S_G0L_M2_1 52 +3.3V_S_G0L_M2_1 50 +3.3V_S_G0L_M2_1 48 +3.3V_S_G0L_M2_1 46 +3.3V_S_G0L_M2_1 44 +3.3V_S_G0L_M2_1 42 +3.3V_S_G0L_M2_1 40 +3.3V_S_G0L_M2_1 38 +3.3V_S_G0L_M2_1 36 +3.3V_S_G0L_M2_1 34 +3.3V_S_G0L_M2_1 32 +3.3V_S_G0L_M2_1 30 +3.3V_S_G0L_M2_1 28 +3.3V_S_G0L_M2_1 26 +3.3V_S_G0L_M2_1 24 +3.3V_S_G0L_M2_1 22 +3.3V_S_G0L_M2_1 20 +3.3V_S_G0L_M2_1 18 +3.3V_S_G0L_M2_1 16 +3.3V_S_G0L_M2_1 14 +3.3V_S_G0L_M2_1 12 +3.3V_S_G0L_M2_1 10 +3.3V_S_G0L_M2_1 8 +3.3V_S_G0L_M2_1 6 +3.3V_S_G0L_M2_1 4 +3.3V_S_G0L_M2_1 2 +3.3V_S_G0L_M2_1 77 PCie_CLK_SCL 74 PCie_CLK_SDA 72 W_DISABLE# 70 W_DISABLE# 68 W_DISABLE# 66 W_DISABLE# 64 W_DISABLE# 62 PCie_CLK_SCL 60 PCie_CLK_SDA 58 W_DISABLE# 56 W_DISABLE# 54 PCi_RESET_GOL_2# 52 PCi_RESET_GOL_2# 50 PCi_RESET_GOL_2# 48 PCi_RESET_GOL_2# 46 PCi_RESET_GOL_2# 44 PCi_RESET_GOL_2# 42 PCi_RESET_GOL_2# 40 PCi_RESET_GOL_2# 38 PCi_RESET_GOL_2# 36 PCi_RESET_GOL_2# 34 PCi_RESET_GOL_2# 32 PCi_RESET_GOL_2# 30 PCi_RESET_GOL_2# 28 PCi_RESET_GOL_2# 26 PCi_RESET_GOL_2# 24 PCi_RESET_GOL_2# 22 PCi_RESET_GOL_2# 20 PCi_RESET_GOL_2# 18 PCi_RESET_GOL_2# 16 PCi_RESET_GOL_2# 14 PCi_RESET_GOL_2# 12 PCi_RESET_GOL_2# 10 PCi_RESET_GOL_2# 8 PCi_RESET_GOL_2# 6 PCi_RESET_GOL_2# 4 PCi_RESET_GOL_2# 2 GND: -9999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999999(nl)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/7e00a55514b546e2918af5bb5663addd42c2f6e088b73aadf10c830e13fe9552.jpg) Mounting hole for M.2 EXPANSION ![MM_DS_M2.5x0.45x2.5MM DNI HW4 0402 R59 DNI 1% 0ohms GND ZNL1 Move solderpaste layer of HW5 to top side. MM_DS_M2.5x0.45x2.5MM HW5 0402 R58 1% 0ohms GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6558d4c6332adaba582d2f475676e628dc5c25f93e83acd270970123fc8c2bc0.jpg) ![+3.3V A +3.3V S 0ohms R62 50mR 0805 0ohms DNI R63 50mR 0805 2.5 A +3.3V_S_G01_M2_1 C26 0603 10uF 16V C27 0603 10uF 16V C402 50V 0.1uF C35 0402 50V 0.1uF C36 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6d2556173b9ceb5080f062211aa0822af330dbd704522eecd33509617eee6282.jpg) Figure 14 above applies to the COM-HPC Mini as well, except that series coupling capacitors are needed for the PCIe TX pair at the right side of the Figure 14. Coupling caps for the PCIe RX pair are on the M.2 card. The single ended sideband signals will need level translation if they are sourced by or destined for the COM-HPC Mini Module. The PCIe Reset signal into the M.2 card needs to be at a 3.3V logic level. Figure 15: M.2 B-Key Site – Cell Modem Cards – PCIe Group 0 Low – PCIe Lane 3 ![+3.3V_S_3V7_3V3 J2 74 V_3V3_74 72 V_3V3_72 70 V_3V3_70 68 UIM_DETECT_GOL_BL KC x UIM_DETECT_GOL_BL WAKEO# R53 0ohms WAKE_GOL_2# 5 5 PCIe_CLKREQ_GOL_3# PCI_RESET_GOL_3B# V_IUM_VCC_GOL_BU UIM_RST_GOL_BU UIM_CLK_GOL_BU UIM_DATA_GOL_BU UIM-State_GOL_BU GPIO External Buff 0402 R9 DNI 1% 10Kohms 0402 DNI 1% 10Kohms GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/34db5cd737d2b48ecde8d54db77456dce1e7204b297f37e4ba8613340b7daf8f.jpg) This example may be used on a COM-HPC Mini design, but Carrier board coupling capacitors have to be added for the PCIe TX pair shown at the right side of the Figure 15. The single ended sideband signals will need level translation if they are sourced by or destined for the COM-HPC Mini Module. The PCIe Reset signal into the M.2 card needs to be at a 3.3V logic level. Other sideband signals may need level translation. Figure 16: Clock and Reset Buffers for PCIe Group 0 Low Example Circuits ![+3.3V_S 600 2A FB1 0805 C37 10V C5 0.1uF 0.25V C6 0.1uF 0.25V GND +3.3V_S_VDD +3.3V_S_VDD +3.3V_S_VDDR +3.3V_S_VDD +3.3V_S_VDDA 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16S +3.3V_S_VDDR +3.3V_S_VDDA +3.3V_S_VDD U1 HIBW_BYPM_LOBW# CLK_PWRGD_PD# SADR V_3V3_DIG V_3V3_VDDR V_3V3_VDDA SDATA_3V3 SCLK_3V3 PCle_CLKREQ_GOL_1# PCle_CLKREQ_GOL_2# PCle_CLKREQ_GOL_3# PCle_CLKREQ_GOL_4# PCle_CLKREQ_GOL_5# PCle_CLKREQ_GOL_6# PCle_CLKREQ_GOL_7# PCle_CLKREQ_GOL_8# PCle_CLKREQ_GOL_9# PCle_CLKREQ_GOL_10# PCle_CLKREQ_GOL_11# PCle_CLKREQ_GOL_12# PCle_CLKREQ_GOL_13# PCle_CLKREQ_GOL_14# PCle_CLKREQ_GOL_15# PCle_CLKREQ_GOL_16# PCle_CLKREQ_GOL_17# PCle_CLKREQ_GOL_18# PCle_CLKREQ_GOL_19# PCle_CLKREQ_GOL_20# PCle_CLKREQ_GOL_21# PCle_CLKREQ_GOL_22# PCle_CLKREQ_GOL_23# PCle_CLKREQ_GOL_24# PCle_CLKREQ_GOL_25# PCle_CLKREQ_GOL_26# PCle_CLKREQ_GOL_27# PCle_CLKREQ_GOL_28# PCle_CLKREQ_GOL_29# PCle_CLKREQ_GOL_30# PCle_CLKREQ_GOL_31# PCle_CLKREQ_GOL_32# PCle_CLKREQ_GOL_33# PCle_CLKREQ_GOL_34# PCle_CLKREQ_GOL_35# PCle_CLKREQ_GOL_36# PCle_CLKREQ_GOL_37# PCle_CLKREQ_GOL_38# PCle_CLKREQ_GOL_39# PCle_CLKREQ_GOL_40# PCle_CLKREQ_GOL_41# PCle_CLKREQ_GOL_42# PCle_CLKREQ_GOL_43# PCle_CLKREQ_GOL_44# PCle_CLKREQ_GOL_45# PCle_CLKREQ_GOL_46# PCle_CLKREQ_GOL_47# PCle_CLKREQ_GOL_48# PCle_CLKREQ_GOL_49# PCle_CLKREQ_GOL_50# PCle_CLKREQ_GOL_51# PCle_CLKREQ_GOL_52# PCle_CLKREQ_GOL_53# PCle_CLKREQ_GOL_54# PCle_CLKREQ_GOL_55# PCle_CLKREQ_GOL_56# PCle_CLKREQ_GOL_57# PCle_CLKREQ_GOL_58# PCle_CLKREQ_GOL_59# PCle_CLKREQ_GOL_60# PCle_CLKREQ_GOL_61# PCle_CLKREQ_GOL_62# PCle_CLKREQ_GOL_63# PCle_CLKREQ_GOL_64# PCle_CLKREQ_GOL_65# PCle_CLKREQ_GOL_66# PCle_CLKREQ_GOL_67# PCle_CLKREQ_GOL_68# PCle_CLKREQ_GOL_69# PCle_CLKREQ_GOL_70# PCle_CLKREQ_GOL_71# PCle_CLKREQ_GOL_72# PCle_CLKREQ_GOL_73# PCle_CLKREQ_GOL_74# PCle_CLKREQ_GOL_75# PCle_CLKREQ_GOL_76# PCle_CLKREQ_GOL_77# PCle_CLKREQ_GOL_78# PCle_CLKREQ_GOL_79# PCle_CLKREQ_GOL_80# PCle_CLKREQ_GOL_81# PCle_CLKREQ_GOL_82# PCle_CLKREQ_GOL_83# PCle_CLKREQ_GOL_84# PCle_CLKREQ_GOL_85# PCle_CLKREQ_GOL_86# PCle_CLKREQ_GOL_87# PCle_CLKREQ_GOL_88# PCle_CLKREQ_GOL_89# PCle_CLKREQ_GOL_90# PWRGD_PD_GOLD# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +3.3V_S_VDD +3.3V_S_VDDAR SADR: SMBUS ADDR 0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit) (Default) BW_MODE 0 LOW BW_MODE M BYPASS_MODE (Default) 1 HIGH BW_MODE +3.3V_S_VDDAR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVDADIR/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/ +3.3V_S_VDDAR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTDAI/SPRCHD/DWTCAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAI/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/SPRCHD/DVTDAi/ +3.3V_S_VDDAR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCK_DVDADIR/SPRCNDS/A/B/C/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/A/B/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/C/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK/SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /TMSBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SMBCLK /SBBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBACK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/SMBCK/TMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/SMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK/TMSBACK TSMBSBank/B/M/PALTRST# 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G120 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G125 74LVC1G12](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/0c1e68c7310a24f2c82fed412f069749159287919048cbcd225872b203debced.jpg) \*Push/Pull design use LVC07 wih PU resistor for OC designsThis example might be used in a COM-HPC Mini system, with some modifications – the circuits at the bottom of the page (U2, U3, U4) need to become 1.8V compliant to interface to the COM-HPC Mini Module. It may be preferable but not strictly necessary to use a 1.8V I/O compliant clock buffer for COM-HPC Mini designs. For example, the Diodes Inc PI6CB18200. Diodes Inc, Parade Technology, Renesas, Texas Instruments and others may have suitable parts. The Mini PCIe Reference Clocks do not need level translation. They come out of the Mini at the requisite PCI SIG defined levels. The PLTRST# signal comes out of the Mini at a 1.8V logic level and needs level translation if it is to drive 3.3V I/O level loads. # 3.6.4. Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High The following three figures 17, 18 and 19 illustrate a dual PCIe x4 M.2 M Key deployment for NVME SSDs. The COM-HPC specification recommends that PCIe Group 0 High be used for this purpose. Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11 ![22x80mm M-type 4.2mm connector height +3.3V_S C28 61 22uF 6.3V 1005 62 22uF 6.3V 1005 63 0.9V 10V 1000 64 0.9V 10V 1000 65 0.1uF 0.1uF 0.1uF 66 0.1uF 0.1uF 0.1uF 67 0.1uF 0.1uF 0.1uF 68 0.1uF 0.1uF 0.1uF 69 0.1uF 0.1uF 0.1uF 70 0.1uF 0.1uF 0.1uF 71 0.1uF 0.1uF 0.1uF 72 0.1uF 0.1uF 0.1uF 73 0.1uF 0.1uF 0.1uF 74 V_3V3_74 V_3V3_72 V_3V3_70 V_3V3_68 V_3V3_66 V_3V3_64 V_3V3_62 V_3V3_60 V_3V3_58 V_3V3_56 V_3V3_54 G0H_M2_1_SUBCLK 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 77 57 GND_75 75 73 71 69 NC. 67 NC. 65 NC. 63 NC. 61 NC. 59 NC. 57 NC. 55 NC. 53 NC. 51 NC. 49 NC. 47 NC. 45 NC. 43 NC. 41 NC. 39 NC. 37 NC. 35 NC. 33 NC. 31 NC. 29 NC. 27 NC. 25 NC. 23 NC. 21 NC. 19 NC. 17 NC. 15 NC. 13 NC. 11 NC. 9 NC. 7 NC. 5 NC. 3 NC. 2 NC. 1 NC. TE-Connectivity_1-2199230_CARD PCIe_CLKREQ_G0H_1# PCI_RESET_G0H_1# Not connecting SMBus on connectors to COM/HPQ main SMBus due to the inability to guarantee unique SMBus addresses M2_G0H_1_SSD_ACT# SMB_DAT_G0H_1 SMB_CLK_G0H_1 M2_G0H_1_DEVSLP R13 10kohms R12 10kohms R27 4.5kohms R25 2.2kohms R24 5.5kohms R23 4.5kohms R22 4.5kohms R21 4.5kohms R20 4.5kohms R19 4.5kohms R18 4.5kohms R17 4.5kohms R16 4.5kohms R15 4.5kohms R14 4.5kohms R13 4.5kohms R12 4.5kohms R11 4.5kohms R10 4.5kohms R9 4.5kohms R8 4.5kohms R7 4.5kohms R6 4.5kohms R5 4.5kohms R4 4.5kohms R3 4.5kohms R2 4.5kohms R1 4.5kohms R0 4.5kohms R9 4.5kohms R8 4.5kohms R7 4.5kohms R6 4.5kohms R5 4.5kohms R4 4.5kohms R3 4.5kohms R2 4.5kohms R1 4.5kohms R0 4.5kohms R8 4.5kohms R7 4.5kohms R6 4.5kohms R5 4.5kohms R4 4.5kohms R3 4.5kohms R2 4.5kohms R1 4.5kohms R0 4.5kohms R9 4.5kohms R8](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/cd8669a17a1d380a7273248c0894ed9b19abec73f88ffe5b67ddb1e9d7999a14.jpg) This example may be used on a COM-HPC Mini designs, using PCIe Group 0 High. The PCIe\_CLKREQ\_G0H\_1# signal and the PCI\_RESET\_G0H\_ 1# signal need level translation if they are sourced from or destined to the Mini Module. Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 High PCIe Lanes 12:15 ![The image displays a schematic diagram for an M.2 connector interface and an SSD activity LED circuit. **Header Text:** '22x80mm M-type' '4.2mm connector height' **Top Left Section:** - Power rail '+3.3V_S' connects to capacitors C26 (0.4uF), C1 (0.1uF), C2 (0.1uF), C3 (0.1uF), C4 (0.1uF), C5 (0.1uF), and C6 (0.1uF), all tied to GND. - Signals 'PCIe_CLKREQ_G0H_2#' and 'PCI_RESET_2#' are shown. - Resistors R2 (10Kohms 1% 0402) pull up 'GOH_M2_2_SUSCLK' and 'GOH_2_PEWAKE#'. **Connector J1 (Center):** - Labeled 'REV 1.1'. - **Left Side Pins (Even):** - 74: V_3V3_74 - 72: V_3V3_72 - 70: V_3V3_70 - 68: SUSCLK - 66: CONNECTOR_KEY_66 - 64: CONNECTOR_KEY_64 - 62: CONNECTOR_KEY_62 - 60: CONNECTOR_KEY_60 - 58: NC_58 - 56: NC_56 - 54: PEWAKE# - 52: CLKREQ# - 50: PERST# - 48: NC_48 - 46: NC_46 - 44: ALERT# - 42: SMB_DATA - 40: SMB_CLK - 38: DEVSLP - 36: NC_36 - 34: NC_34 - 32: NC_32 - 30: NC_30 - 28: NC_28 - 26: NC_26 - 24: NC_24 - 22: NC_22 - 20: NC_20 - 18: V_3V3_18 - 16: V_3V3_16 - 14: V_3V3_14 - 12: V_3V3_12 - 10: DAS/DSS/LED1# - 8: NC_8 - 6: NC_6 - 4: V_3V3_4 - 2: V_3V3_2 - 77: MTG_77 (GND) - Label: 'TE-Connectivity_1-2199230_CARD' - **Right Side Pins (Odd):** - 75: GND_75 - 73: GND_73 - 71: GND_71 - 69: PEDET - 67: NC_67 - 65: CONNECTOR_KEY_65 - 63: CONNECTOR_KEY_63 - 61: CONNECTOR_KEY_61 - 59: CONNECTOR_KEY_59 - 57: GND_57 - 55: REFCLK+ - 53: REFCLK- - 51: GND_51 - 49: PET0+/SATA-A+ - 47: PET0-/SATA-A- - 45: GND_45 - 43: PERO+/SATA-B+ - 41: PERO-/SATA-B- - 39: GND_39 - 37: PET1+ - 35: PET1- - 33: GND_33 - 31: PER1+ - 29: PER1- - 27: GND_27 - 25: PET2+ - 23: PET2- - 21: GND_21 - 19: PER2+ - 17: PER2- - 15: GND_15 - 13: PET3+ - 11: PET3- - 9: GND_9 - 7: PER3+ - 5: PER3- - 3: GND_3 - 1: GND_1 - 76: MTG_76 (GND) **Middle Section:** - Text: 'Not connecting SMBus on connectors to COM-HFD main SMBus due to the inability to guarantee unique SMBus addresses' - Resistors R7, R6 (10Kohms 1% 0402) pull up '+1.8V_S_G0H'. - Resistor R4 (10Kohms 1% 0402) pulls up 'SMB_CLK_G0H_2'. - Resistor R26 (1.5Kohms 1% 0402) pulls up '+3.3V_S'. - Resistor R24 (2.21Kohms 1% 0402) connects 'M2_G0H_2_SSD_ACT#' to GND. - Text block: 'Stagered spin-up isn't disabled by default. From SATA specification, DAS pullup voltage is Vth = 1.8V to 2.1V max. It must be buffered to drive a LED.' **M.2 Retention Hardware Box:** - Title: 'M.2 Retention Hardware' - Diagram shows switch HW1 connected to GND. - Label: 'M2.5x2.5MM' **SSD Activity LED Section (Bottom):** - Title: 'SSD Activity LED' - Schematic includes resistor R30 (270ohms 0402), resistor R5 (10Kohms 1% 0402), two LEDs, transistor Q2 (MMBT3904 SOT23), and transistor Q1 (MMBT3904 SOT23). - Signals: '+3.3V_S', 'M2_G0H_2_SSD_ACT_D#', 'M2_G0H_2_SSD_ACT_O#', 'M2_G0H_2_SSD_ACT'. - Text block: '90 to 180mcd @ 20mA, 25C', '22 to 45mcd @ 6mA, 25C', 'VF @ 20mA = 1.9V min; 2.0V typ; 2.4V max', 'VF @ 6mA = 1.85V typ.'](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/b929c6356121355341dd8e58d19204a38d6840944cc4b53c17d7535a68b56c87.jpg) The M.2 M-Key connector used must have a PCIe “speed rating” at least as high as the link speed being used (PCIe Gen 3, 4 or 5). PCIe Gen 3 and Gen 4 capable M.2 connectors are common. At the time of this writing, PCIe Gen 5 capable M.2 connectors are not common. PCIe Gen 3, 4, and 5 capable M.2 connectors are available from Amphenol FCI. This example may be used on a COM-HPC Mini design. The PCIe\_CLKREQ\_G0H\_2# signal and the PCI\_RESET\_G0H\_ 2# signal need level translation if they are directly sourced from or destined to the Mini Module. Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High ![+3.3V_S_G0H_VDD +3.3V_S_G0H_VDD SADR: SMBUS ADDR 0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit) (Default) BW_MODE 0 LOW BW MODE M BYPASS MODE (DEFAULT) 1 HIGH BW MODE U4 HIBW_BYPM_LOBW# V_3V3_DIG CLK_PWRGD_PD# V_3V3_VDDR SADR V_3V3_VDDA SDATA_3V3 V_3V3_VDDO_21 SCLK_3V3 OE0# OE1# CLK_IN+ CLK_IN- FB_DNC+ FB_DNC- GND_DIG GND_PAD 9DBL0252 NC_11 NC_12 NC_20 11 NC 12 NC 20 NC +3.3V_S_G0H_VDDR +3.3V_S_G0H_VDD +3.3V_S_G0H_VDDA COM SMB_DAT SMB_CLK PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_REFCLK0_HI- PCIe_CLKREQ0_HI# +3.3V_S U1 VCC 74LVC1G08 GND 0.1uF C20 4 2 1 2 +3.3V_S FB1 1206 +3.3V_S_G0H_VDD +3.3V_S_VDD +3.3V_S_G0H_VDDR +3.3V_S_VDD +3.3V_S_G0H_VDDA +3.3V_S U3 VCC 5 4 PCI_RESET# COM PLTRST# 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 SADR: SMBUS ADDR 0 X6B (7-bit) M X6C (7-bit) 1 X6D (7-bit) (Default) COM SMB_DAT SMB_CLK PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_REFCLK0_HI- PCIe_CLKREQ0_HI# +3.3V_S_G0H_VDDA +3.3V_S_G0H_VDDR +3.3V_S_G0H_VDDA COM SMB_DAT SMB_CLK PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_REFCLK0_HI- PCIe_CLKREQ0_HI# +3.3V_S_G0H_VDDA COM SMB_DAT SMB_CLK PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_REFCLK0_HI- PCIe_CLKREQ0_HI# +3.3V_S_G0H_VDDA COM SMB_DAT SMB_CLK PCIe_CLKREQ_G0H_1# PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_CLKREQ_G0H_2# COM PCIe_REFCLK0_HI- PCIe_CLKREQ_O H I#](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/60ed8965dc475aaa26e02fcf5530ead2d4deaa31eac884e85f38efc633099b8e.jpg) A dual channel clock buffer is used as there are two PCIe x4 links implemented in this PCIe Group 0 High example. The COM-HPC PCIe\_CLKREQ0\_HI# signal is driven by logic gate U1 in the Figure 19 above, resulting in a clock request if either one or both of the NVMe cards are present. Alternatively, U1 could be removed and the COM-HPC Group 0 High clock request line held low by R34, in which case the Group 0 High PCIe clock pair would always run. The clock buffer shown is the 9DBL0252 from Renesas / IDT. It is PCIe Gen 1,2,3,4 and 5 capable. The PLTRST# buffer shown, U3, is a 74LVC1G125 device that tolerates a signal input between 0 and 5.5V even in the absence of the VCC to the device. The PLTRST# signal is in the S5 power domain; the VCC applied to U3 is in the S0 domain. This example is not directly applicable to the COM-HPC Mini, due to most of the Mini I/O voltage levels being defined to be at 1.8V on the Mini rather than 3.3V. The concepts above can be converted to a 1.8V implementation. It may be preferable but not strictly necessary to use a 1.8V I/O compliant clock buffer for COM-HPC Mini designs. For example, the Diodes Inc PI6CB18200. Diodes Inc, Parade Technology, Renesas, Texas Instruments and others may have suitable parts. # 3.6.5. PCIe x16 Slot Card Site on PCIe Group 1 Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31 ![ICT1 ICT2 ICT3 ICT4 ICT5 PCIe_REFCLK1+ PCIe_REFCLK1- PCIe16_TX+ PCIe16_TX- PCIe17_TX+ PCIe18_TX+ PCIe19_TX+ PCIe20_TX+ PCIe21_TX+ PCIe22_TX+ PCIe23_TX+ PCIe24_TX+ PCIe25_TX+ PCIe26_TX+ PCIe27_TX+ PCIe28_TX+ PCIe29_TX+ PCIe30_TX+ PCIe31_TX+ PCIe31_TX- WAKE# 0ohms R5 B11 SMB_CLK 0ohms R6 SMB_DAT 0ohms R7 R402 Not connecting SMBus on connectors to COM-HFD main SMBus due to the inability to guarantee unique SMBus addresses EPRBRK_G1_1# FCL_10141523-123A SECTION 1 OF 2 SECTION 2 OF 2 SECTION 2 OF 2 A4 GND_A4 GND_B4 B4 A12 GND_A12 GND_B7 B7 A15 GND_A15 GND_B13 B13 A18 GND_A18 GND_B16 B16 A20 GND_A20 GND_B18 B18 A23 GND_A23 GND_B21 B21 A27 GND_A27 GND_B25 B25 A28 GND_A28 GND_B26 B26 A31 GND_A31 GND_B29 B29 A34 GND_A34 GND_B32 B32 A37 GND_A37 GND_B35 B35 A38 GND_A38 GND_B36 B36 A41 GND_A41 GND_B39 B39 A42 GND_A42 GND_B40 B40 A45 GND_A45 GND_B43 B43 A46 GND_A46 GND_B44 B44 A49 GND_A49 GND_B47 B47 A51 GND_A51 GND_B49 B49 A54 GND_A54 GND_B52 B52 A55 GND_A55 GND_B53 B53 A58 GND_A58 GND_B56 B56 A59 GND_A59 GND_B57 B57 A62 GND_A62 GND_B60 B60 A63 GND_A63 GND_B61 B61 A66 GND_A66 GND_B64 B64 A67 GND_A67 GND_B65 B65 A70 GND_A70 GND_B68 B68 A71 GND_A71 GND_B69 B69 A74 GND_A74 GND_B72 B72 A75 GND_A75 GND_B73 B73 A78 GND_A78 GND_B76 B76 A79 GND_A79 GND_B77 B77 A82 GND_A82 GND_B80 B80 M1 M1 M2 M2 FCL_10141523-123A SECTION 2 OF 2 A2 +12V_S +3.3V_S +3.3V_A A3 A9 A10 A10 B1 B2 B3 B8 B10 B3 PCI_RESET_G1_1# PERST# PER0+ PER0- PER1+ PER1- PER2+ PER2- PER3+ PER3- PER4+ PER4- PER5+ PER5- PER6+ PER6- PER7+ PER7- PER8+ PER8- PER9+ PER9- PER10+ PER10- PER11+ PER11- PER12+ PER12- PER13+ PER13- PER14+ PER14- PER15+ PER15- PRSNT# PRSNT# PER0- PER0- PER1- PER1- PER2- PER2- PER3- PER3- PER4- PER4- PER5- PER5- PER6- PER6- PER7- PER7- PER8- PER8- PER9- PER9- PER10- PER10- PER11- PER11- PER12- PER12- PER13- PER13- PER14- PER14- PER15- PER15- PRSNT# PRSNT# PER0+ PER0- PER0- PER0- PER1+ PER1- PER2- PER2- PER3- PER3- PER4- PER4- PER5- PER5- PER6- PER6- PER7- PER7- PER8- PER8- PER9- PER9- PER10- PER10- PER11- PER11- PER12- PER12- PER13- PER13- PER14- PER14- PER15- PER15- PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT# PSNRT## PCI_RESET_G1_1# PCI_REFCLK1+ PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCLK1- PCI REFCK TX+ PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX- PCI REFCLKTX+ PCI REFCLKTX- PCI REFCLKTX- PCI REFCK TX+ PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCK TX- PCI REFCA TX+ PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFCA TX- PCI REFNA TX+ PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PCI REFNA TX- PSENUT# PSENUT# PRSNT# PSENUT# PSENUT# PRSNT# PSENUT# PSENUT# PRSNT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENUT# PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT # PSENAT ? GND A4 A5 A6 A7 A8 A9 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 GND A4 A5 A6 A7 A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A8 GND A4 A5 A6 A7 A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A8 GND A4 A5 A6 A7 A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 D N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N S GND CINR RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN REN Signal can also be used as a present O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O=O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = O = S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3V_S +3.3 V S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S/S VCC NC U 5 4 2 GPIO EPRBRK_G1_1# OPEN Drain Signal GND CINR RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN L VCC NC U 5 4 2 GPIO EPRBRK_G1_1# GND CINR RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN RAN L VCC NC U 5 4 2 GPIO EPRBRK_G1_1# GND CINR L VCC NC U 5 4 2 GPIO EPRBRK_G1_1# GND CINR L VCC NC U 5 4 2 GPIO EPRBRK_G1_1# GND CINR L VCC NC U 5 4 2 GPIO EPRBRK_G1_1# GND CINR L VCC NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5 4 2 GPIO EPRBRK_G1__NC U 5](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/355214e7b40581084e58c3d25092fe3e307511ceb2516f9ba580b49395afc758.jpg) No PCIe clock buffer is needed as there is only one PCIe link in this example. The COM-HPC Group 1 PCIe clock pair is used directly. If the group is split into two or more links, then a PCIe clock buffer would be required. The slot connector used must be rated and qualified for the PCIe link speed expected. Slot connectors rated for PCIe Gen 3 and 4 are common. Connectors rated for PCIe Gen 5 are at the time of this writing are still new. Such parts are available from Amphenol FCI and others. This example does not directly apply to the COM-HPC Mini as there is no PCIe Group 1 on the Mini. # 3.6.6. PCIe Group 2 Figures 21 through 24 below illustrate the implementation of 3 PCIe slots on COM-HPC PCIe Group 2, along with a PCIe clock buffer appropriate for use with PCIe Gen 4 and below. The slot RESET# signals come from a buffer in Figure 24. Additional notes are provided after the last Figure in this series. These examples do not apply to the COM-HPC Mini. Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39 ![The image is a schematic diagram for a connector labeled **J1** (FCI 10141523-122Y). It details pin assignments, net names, and connections for PCIe, power, and control signals. **Top Section (JTAG & Power)** * **JTAG/ICT Connections (Left):** * **ICT11** connects to pin **A5** (labeled **JTAG2_TCK**) * **ICT12** connects to pin **A6** (labeled **JTAG2_TDI**) * **ICT13** connects to pin **A7** (labeled **JTAG4_TDO**) * **ICT14** connects to pin **A8** (labeled **JTAG5_TMS**) * **ICT15** connects to pin **B9** (labeled **JTAG1_TRST#**) * **PCIe CLK G2 1+** connects to pin **A13** (labeled **REFCLK+**) * **PCIe CLK G2 1-** connects to pin **A14** (labeled **REFCLK-**) * **Power Rails (Right):** * **+12V_S** connects to pins **A2**, **A3**, **B1**, **B2**, **B3** (internally labeled **V_12V0_A2**, **V_12V0_A3**, **V_12V0_B1**, **V_12V0_B2**, **V_12V0_B3**). * **+3.3V_S** connects to pins **A9**, **A10**, **B8** (internally labeled **V_3V3_A9**, **V_3V3_A10**, **V_3V3_B8**). * **+3.3V_A** connects to pin **B10** (internally labeled **V_3V3_AUX**). **Middle Section (PCIe Data & PER Signals)** * **TX Pairs (Left):** * **PCIe32 TX+** (**B14**) / **PCIe32 TX-** (**B15**) connect to **PET0+** / **PET0-** * **PCIe33 TX+** (**B19**) / **PCIe33 TX-** (**B20**) connect to **PET1+** / **PET1-** * **PCIe34 TX+** (**B23**) / **PCIe34 TX-** (**B24**) connect to **PET2+** / **PET2-** * **PCIe35 TX+** (**B27**) / **PCIe35 TX-** (**B28**) connect to **PET3+** / **PET3-** * **PCIe36 TX+** (**B33**) / **PCIe36 TX-** (**B34**) connect to **PET4+** / **PET4-** * **PCIe37 TX+** (**B37**) / **PCIe37 TX-** (**B38**) connect to **PET5+** / **PET5-** * **PCIe38 TX+** (**B41**) / **PCIe38 TX-** (**B42**) connect to **PET6+** / **PET6-** * **PCIe39 TX+** (**B45**) / **PCIe39 TX-** (**B46**) connect to **PET7+** / **PET7-** * **RX Pairs & PER (Right):** * **PERST#** (**A11**) connects to **PCI_RESET_G2_1#** * **PER0+** (**A16**) / **PER0-** (**A17**) connect to **PCIe32_RX+** / **PCIe32_RX-** * **PER1+** (**A21**) / **PER1-** (**A22**) connect to **PCIe33_RX+** / **PCIe33_RX-** * **PER2+** (**A25**) / **PER2-** (**A26**) connect to **PCIe34_RX+** / **PCIe34_RX-** * **PER3+** (**A29**) / **PER3-** (**A30**) connect to **PCIe35_RX+** / **PCIe35_RX-** * **PER4+** (**A35**) / **PER4-** (**A36**) connect to **PCIe36_RX+** / **PCIe36_RX-** * **PER5+** (**A39**) / **PER5-** (**A40**) connect to **PCIe37_RX+** / **PCIe37_RX-** * **PER6+** (**A43**) / **PER6-** (**A44**) connect to **PCIe38_RX+** / **PCIe38_RX-** * **PER7+** (**A47**) / **PER7-** (**A48**) connect to **PCIe39_RX+** / **PCIe39_RX-** **Lower Section (Control, SMBus, & Ground)** * **Left Side:** * **WAKE0#** connects through resistor **R28** (0ohms 1%) to **WAKE0_G2_3#**, which connects to pin **B11** (labeled **WAKE#**). * **PCIe CLK SCL** connects through resistor **R33** (0402, DNI, 0ohms 1%) to pin **B5** (labeled **SMCLK**). * **PCIe CLK DAT** connects through resistor **R34** (0402, DNI, 0ohms 1%) to pin **B6** (labeled **SMDAT**). * **Red Text Note:** 'Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses'. * **RSVD** (Reserved/No Connect): **NC x A19** (**RSVD_A_19**), **NC x A32** (**RSVD_A_32**), **NC x A33** (**RSVD_A_33**), **NC x B12** (**RSVD_B_12**), **NC x B30** (**RSVD_B_30**). * **EPRBRK G2 1#** connects to pin **B30**. * **Right Side:** * **PRSNT1#** (**A1**) connects to **PCIe_CLKREQ_G2_1#**. Red text note: 'Signal can also be used as a present'. * **PRSNT2#** pins: **PRSNT2#_B17** (**B17**), **PRSNT2#_B31** (**B31**), **PRSNT2#_B48** (**B48**). * **Ground Pins:** * **B4** (**GND_B4**), **B7** (**GND_B7**), **B13** (**GND_B13**), **B16** (**GND_B16**), **B18** (**GND_B18**), **B21** (**GND_B21**), **B22** (**GND_B22**), **B25** (**GND_B25**), **B26** (**GND_B26**), **B29** (**GND_B29**), **B32** (**GND_B32**), **B35** (**GND_B35**), **B36** (**GND_B36**), **B39** (**GND_B39**), **B40** (**GND_B40**), **B43** (**GND_B43**), **B44** (**GND_B44**), **B47** (**GND_B47**), **B49** (**GND_B49**). * **A4** (**GND_A4**), **A12** (**GND_A12**), **A15** (**GND_A15**), **A18** (**GND_A18**), **A20** (**GND_A20**), **A23** (**GND_A23**), **A24** (**GND_A24**), **A27** (**GND_A27**), **A28** (**GND_A28**), **A31** (**GND_A31**), **A34** (**GND_A34**), **A37** (**GND_A37**), **A38** (**GND_A38**), **A41** (**GND_A41**), **A42** (**GND_A42**), **A45** (**GND_A45**), **A46** (**GND_A46**), **A49** (**GND_A49**). **Bottom Capacitors:** * **+12V_S** connects to **C3** (100uF 25V PTA) to **GND**. * **+3.3V_S** connects to **C6** (100uF 10V X6S) to **GND**. * **+3.3V_A** connects to **C11** (10uF 16V X6S) to **GND**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6c2c45c2ca8cd2bc325957558c086688830a45bcc03c56063bbd597217a03c6c.jpg) ![EPRBRK G2 1# Open Drain Signal +3.3V_S R16 1% 10Kohms 25V 0.1uF C14 +3.3V_S R17 1% 10Kohms Optional U5 NC VCC GND 3 4 5 GND 74LVC1G07 Driven from any source as GPIO logic](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/fa79daf863b7c9c74f138e7e0c131839943c1eb19a6be40c0726a25417810baa.jpg) Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43 ![ Component Pin Label Value ----------- ----------- ------- PCS1_RESET_G2_2# A1 PRSNT1# PCS1_RESET_G2_2# A2 V_12V0_A2 PCS1_RESET_G2_2# A3 V_12V0_A3 PCS1_RESET_G2_2# A4 GND_A4 PCS1_RESET_G2_2# A5 JTAG2_TCK PCS1_RESET_G2_2# A6 JTAG3_TDI PCS1_RESET_G2_2# A7 JTAG4_TDO PCS1_RESET_G2_2# A8 JTAG5_TMS PCS1_RESET_G2_2# A9 V_3V3_A9 PCS1_RESET_G2_2# A10 V_3V3_A10 PCS1_RESET_G2_2# A11 PERST# PCS1_RESET_G2_2# A12 GND_A12 PCS1_RESET_G2_2# A13 REFCLK+ PCS1_RESET_G2_2# A14 REFCLK- PCS1_RESET_G2_2# A15 GND_A15 PCS1_RESET_G2_2# A16 PER0+ PCS1_RESET_G2_2# A17 PER0- PCS1_RESET_G2_2# A18 GND_A18 PCS1_RESET_G2_2# A19 RSVD_A19 PCS1_RESET_G2_2# A20 GND_A20 PCS1_RESET_G2_2# A21 PER1+ PCS1_RESET_G2_2# A22 PER1- PCS1_RESET_G2_2# A23 GND_A23 PCS1_RESET_G2_2# A24 GND_A24 PCS1_RESET_G2_2# A25 PER2+ PCS1_RESET_G2_2# A26 PER2- PCS1_RESET_G2_2# A27 GND_A27 PCS1_RESET_G2_2# A28 GND_A28 PCS1_RESET_G2_2# A29 PER3+ PCS1_RESET_G2_2# A30 PER3- PCS1_RESET_G2_2# A31 GND_A31 PCS1_RESET_G2_2# A32 RSVD_A32 PCS1_RESET_G2_2# MTG1 CASE1 PCS1_RESET_G2_2# GND FCI_10141523-121Y PCS1_RESET_G2_2# GND J2 PCS1_RESET_G2_2# GND V_3V3_A9 PCS1_RESET_G2_2# GND V_3V3_A10 PCS1_RESET_G2_2# GND V_3V3_AUX_B10 PCS1_RESET_G2_2# GND WAKE# PCS1_RESET_G2_2# NC B11 PCS1_RESET_G2_2# NC B12 × NC PCS1_RESET_G2_2# NC B13 PCS1_RESET_G2_2# NC B14 PCS1_RESET_G2_2# NC B15 PCS1_RESET_G2_2# NC B16 PCS1_RESET_G2_2# NC B17 PCS1_RESET_G2_2# NC B18 PCS1_RESET_G2_2# NC B19 PCS1_RESET_G2_2# NC B20 PCS1_RESET_G2_2# NC B21 PCS1_RESET_G2_2# NC B22 PCS1_RESET_G2_2# NC B23 PCS1_RESET_G2_2# NC B24 PCS1_RESET_G2_2# NC B25 PCS1_RESET_G2_2# NC B26 PCS1_RESET_G2_2# NC B27 PCS1_RESET_G2_2# NC B28 PCS1_RESET_G2_2# NC B29 PCS1_RESET_G2_2# NC B30 PCS1_RESET_G2_2# NC B31 PCS1_RESET_G2_2# NC B32 PCS1_RESET_G2_2# NC MTG2 PCS1_RESET_G2_2# NC GND PCS1_CLK_SCL_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLKAT_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK_DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLK DAT_PCE_CLKAT_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCL_PCE_CLK_SCLK_LPCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCle_CLK_SCL PCle_CLK_SCL - PCCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle_CLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCPLCle/KPCLK_SCFLPCCl_e_clkREQ_GZ_### / Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to guarantee unique SMBus addresses. Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to guarantee unique SMBus addresses.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/cddff4c19fd60fd72def26fc85cd995e7ac84db5f6e04e23dfa5772e0400b2b7.jpg) ![+3.3V S R13 0402 1% 10Kohms 25V 0.1uF C12 Optional U3 VCC NC 5 4 3 GND 74LVC1G07 1 NC 2 10Kohms 1% R12 0402 EPRBRK G2 2# Open Drain Output Signal Driven from any source os GPIO logic](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/4cfc8fc4c26f10c791d519b80ee873e9622c9141d4956620481a364ff9435862.jpg) This example does not apply to the COM-HPC Mini. Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47 ![The image is an electronic schematic diagram for a connector interface labeled **J3** at the top and **FCI 10141523-121Y** at the bottom. It details the pinout for two columns of pins, **A1-A32** (left) and **B1-B32** (right), along with power rails, ground connections, and signal networks. **Left Side (Pins A1-A32):** * **Power/Ground:** Pins A2, A3 connect to **+12V_S**. Pins A4, A12, A15, A18, A20, A23, A26, A29, A31 connect to **GND**. * **Signals:** * **A1:** PRSNT1# * **A5-A8:** JTAG signals (JTAG2_TCK, JTAG3_TDI, JTAG4_TDO, JTAG5_TMS) * **A9/A10:** V_3V3_B8, V_3V3_A9 * **A11:** PERST# * **A13/A14:** REFCLK+, REFCLK- (connected to COM PCIe_CLK_G2_3+/-) * **A16/A17:** PER0+, PER0- (connected to COM PCIe44_RX+/-) * **A21/A22:** PER1+, PER1- (connected to COM PCIe45_RX+/-) * **A24/A25:** PER2+, PER2- (connected to COM PCIe46_RX+/-) * **A27/A28:** PER3+, PER3- (connected to COM PCIe47_RX+/-) * **Reserved/Ground:** A19 (RSVD_A19, marked NC), A30 (RSVD_A30, marked NC), A32 (RSVD_A32). * **Bottom:** MTG1, CASE1, GND. **Right Side (Pins B1-B32):** * **Power/Ground:** Pins B1, B2, B3 connect to **+12V_S**. Pins B4, B7, B13, B16, B18, B21, B22, B25, B26, B29, B32 connect to **GND**. * **Signals:** * **B5/B6:** SMCLK, SMDAT * **B9:** JTAG1_TRST# * **B11:** WAKE# * **B14/B15:** PET0+, PET0- (connected to COM PCIe44_TX+/-) * **B17:** PRSNT2# * **B19/B20:** PET1+, PET1- (connected to COM PCIe45_TX+/-) * **B23/B24:** PET2+, PET2- (connected to COM PCIe46_TX+/-) * **B27/B28:** PET3+, PET3- (connected to COM PCIe47_TX+/-) * **B31:** PRSNT2# (connected to EPRBRK_G2_3#, PCIe_CLKREQ_G2_3#) * **Reserved:** B12 (RSVD_B12, marked NC), B30 (RSVD_B30). * **Bottom:** MTG2, CASE2, GND. **Annotations & Components:** * **Top Left:** Capacitors **C2** (100uF), **C5** (100uF), **C10** (10uF) are connected to ground. * **Top Right:** Power rails **+12V_S**, **+3.3V_S**, **+3.3V_A** are shown. * **Resistors:** * **R29** and **R30** (0ohms, 1%, 0402) are labeled **DNI** and connect to **PCIe_CLK_SCL** and **PCIe_CLK_DAT** respectively. * **R26** (0ohms, 1%, 0402) connects **WAKE0_G2_3#** to **WAKE0#**. * **Test Points:** ICT7, ICT8, ICT9, ICT10 (left), ICT6 (right). * **Red Text Note:** 'Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses'. * **Bottom Right Text:** 'Signal can also be used as a present'.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/0aba07e95f2cfed19c4cd03289631a0ea6fc7160ddec40a5d27d514fe1cc9be0.jpg) ![+3.3V_S R25 0402 1% 25V 0.1uF C13 Optional EPRBRK_G2_3# 10Kohms 1% 5 U4 VCC NC GND 3 GND 74LVC1G07 1 NC 2 10Kohms GPIO_EPRBRK_G2_3# Driven from any source os GPIO logic](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/dbca02383f8e3c3e3f12ca118c39f37962d4db1bcd9652fbdb14d250213d0c86.jpg) This example does not apply to the COM-HPC Mini. Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example ![PCIe_CLK_SCL 0ohms DNI R36 10 PCIe_CLK_SDA 0ohms DNI R35 32 PCIe_CLKREQ_G2_1# PCIe_CLKREQ_G2_2# PCIe_CLKREQ_G2_3# COM PCle_REFCLK2+ 5 COM PCle_REFCLK2- 6 U22 VDD_DIG 9 SCLK SDATA VDD_R 4 SADR_TRI VDD_O1 16 BW_SEL_TRI VDD_O2 25 PD# VDD_A 21 P16CB18401ZH1EX Q0+ 13 PCIe_CLK_G2_0+ Q0- 14 PCIe_CLK_G2_0- Q1+ 18 PCIe_CLK_G2_1+ Q1- 19 PCIe_CLK_G2_1- Q2+ 22 PCIe_CLK_G2_2+ Q2- 23 PCIe_CLK_G2_2- Q3+ 27 PCIe_CLK_G2_3+ Q3- 28 PCIe_CLK_G2_3- +1.8V_S +1.8V_S_Pi6CB148401 R59 1ohms 1% 0402 C31 0803 C39 0402 10hms 0.1uF 10V 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uM GND GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND-GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_C33 PCle_CLKREQ G2_3# PCIe_CLKREQ G2_2# PCIe_CLKREQ G2_3# PCIe_CLKREQ G2_1# PCIe_CLKREQ G2_2# PCIe_CLKREQ G2_3# PCIe_CLKREQ G2_4# PCIe_CLKREQ G2_5# PCIe_CLKREQ G2_6# PCIe_CLKREQ G2_7# PCIe_CLKREQ G2_8# PCIe_CLKREQ G2_9# PCIe_CLKREQ G2_10# PCIe_CLKREQ G2_11# PCIe_CLKREQ G2_12# PCIe_CLKREQ G2_13# PCIe_CLKREQ G2_14# PCIe_CLKREQ G2_15# PCIe_CLKREQ G2_16# PCIe_CLKREQ G2_17# PCIe_CLKREQ G2_18# PCIe_CLKREQ G2_19# PCIe_CLKREQ G2_20# PCIe_CLKREQ G2_21# PCIe_CLKREQ G2_22# PCIe_CLKREQ G2_23# PCIe_CLKREQ G2_24# PCIe_CLKREQ G2_25# PCIe_CLKREQ G2_26# PCIe_CLKREQ G2_27# PCIe_CLKREQ G2_28# PCIe_CLKREQ G2_29# PCIe_CLKREQ G2_30# PCIe_CLKREQ G2_31# PCIe_CLKREQ G2_32# PCIe_CLKREQ G2_33# PCIe_CLKREQ G2_34# PCIe_CLKREQ G2_35# PCIe_CLKREQ G2_36# PCIe_CLKREQ G2_37# PCIe_CLKREQ G2_38# PCIe_CLKREQ G2_39# PCIe_CLKREQ G2_40# PCIe_CLKREQ G2_41# PCIe_CLKREQ G2_42# PCIe_CLKREQ G2_43# PCIe_CLKREQ G2_44# PCIe_CLKREQ G2_45# PCIe_CLKREQ G2_46# PCIe_CLKREQ G2_47# PCIe_CLKREQ G2_48# PCIe_CLKREQ G2_49# PCIe_CLKREQ G2_50# PCIe_CLKREQ G2_51# PCIe_CLKREQ G2_52# PCIe_CLKREQ G2_53# PCIe_CLKREQ G2_54# PCIe_CLKREQ G2_55# PCIe_CLKREQ G2_56# PCIe_CLKREQ G2_57# PCIe_CLKREQ G2_58# PCIe_CLKREQ G2_59# PCIe_CLKREQ G2_60# PCIe_CLKREQ G2_61# PCIe_CLKREQ G2_62# PCIe_CLKREQ G2_63# PCIe_CLKREQ G2_64# PCIe_CLKREQ G2_65# PCIe_CLKREQ G2_66# PCIe_CLKREQ G2_67# PCIe_CLKREQ G2_68# PCIe_CLKREQ G2_69# PCIe_CLKREQ G2_70# PCIe_CLKREQ G2_71# PCIe_CLKREQ G2_72# PCIe_CLKREQ G2_73# PCIe_CLKREQ G2_74# PCIe_CLKREQ G2_75# PCIe_CLKREQ G2_76# PCIe_CLKREQ G2_77# PCIe_CLKREQ G2_78# PCIe_CLKREQ G2_79# PCIe_CLKREQ G2_80# PCIe_CLKREQ G2_81# PCIe_CLKREQ G2_82# PCIe_CLKREQ G2_83# PCIe_CLKREQ G2_84# PCIe_CLKREQ G2_85# PCIe_CLKREQ G2_86# PCIe_CLKREQ G2_87# PCIe_CLKREQ G2_88# PCIe_CLKREQ G2_89# PCIe_CLKREQ G2_90# PCIe_CLKREQ G2_91# PCIe_CLKREQ G2_92# PCIe_CLKREQ G2_93# PCIe_CLKREQ G2_94# PCIe_CLKREQ G2_95# PCIe_CLKREQ G2_96# PCIe_CLKREQ G2_97# PCIe_CLKREQ G2_98# PCIe_CLKREQ G2_99# PCIe_CLKREQ G2_100# +3V3_S +1V8_S R1 0.1uF C8 1.0V H/O R1/0.400 C8/0.400 R1/0.400 C8/0.400 R1/0.400 C8/0.400 R1/0.400 C8/0.400 R1/0.400 C8/0.400 R1/0.400 C8/0.400 R1/0.400](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/adf1d1be212741dc843fa6d2fb31c70204863a6583bf641f03f4bdd26ab328e5.jpg) \*Max 4 outputs per buffer \*Push/Pull design use LVC07 wih PU resistor for OC designs This example does not apply to the COM-HPC Mini. # 3.6.7. MXM-3 Graphics Card Module on Carrier The COM Express Carrier Design Guide Rev 2.0 Section 2.6 has a good schematic example of a MXM-3 graphics card implementation on COM Express Carriers. The net names used are not the same as the COM-HPC net names, but the correlation is straightforward. MXM-3 cards use a 16 lane PCI Express interface. Most MXM cards also allow x8 implementations (and all PCIe devices must work in x1 configurations per the PCI-SIG specification). COM-HPC recommends but does not require that COM-HPC PCIe Group 1 be used for PEG (PCI Express Graphics). No Carrier PCIe clock buffer is needed for the MXM card (assuming that the MXM card is only PCIe device used in the COM-HPC PCIe Group). The COM-HPC PCIe reference clock that goes with the COM-HPC PCIe group can be used directly with the MXM card. Coupling capacitors for the COM-HPC Module PCIe RX pairs (MXM card PCIe TX pairs) must be present on the Carrier, preferably close to the MXM connector. Use discrete 0402 or 0201 package size parts. The MXM-3 specification document is currently hard to find. The document was created and is owned by Nvidia but is not publicly available. Information found in the COM Express Carrier Design Guide, from the MXM-3 connector vendors (Aces, Amphenol / FCI, Foxconn, JAE, Yamaichi), from the MXM GPU card vendors and from the COM-HPC Module vendor should be sufficient to carry out a design. The Amphenol / FCI MXM-3 connector part number 10151114-001TLF supports all PCIe signal rates up to and including Gen 5. Note that MXM cards operate in the S0 power domain only. Any signals that are active in the S5 (suspend) power state must be isolated, in the S5 power state, from the MXM card. Note also that MXM-3 connectors have 314 individual pins, but the MXM-3 specification gangs multiple connector pins together for power delivery. The 314 individual connector pins are grouped together in the NVIDIA MXM-3 specification into PWR and GND blocks labeled E1, E2, E3 and E4, and then the pins left over are numbered 1 through 281. The MXM-3 connector drawings from the connector vendors usually illustrate this. MXM graphics cards may be used in a system with the COM-HPC Mini, but series coupling capacitors for any PCIe Group 0 Low TX pairs and all of the PCIe RX pairs (Group0 Low and High) must be present on the Carrier. They are not present on the MXM card. Any Carrier TX caps should be placed close to the COM-HPC Module pins. The RX caps (RX relative to the COM-HPC Module; TX from MXM) should be placed close to the relevant MXM pins. I/O signals between the MXM card and the COM-HPC Mini may need to be level translated for COM-HPC Mini signals that are at a 1.8V level. # 3.6.8. PCIe Reference Clocks COM-HPC, like COM Express and like most commercial and embedded PCI Express implementations, uses the “Common Clock” architecture defined in the PCI-SIG PCI Express Base Specification, Revisions 1 through 5. In this arrangement, there is a common 100 MHz reference clock source that feeds the PCIe Root complex and copies are fed to each PCIe Target device serviced by that Root. The maximum skew allowed between any two PCIe reference clocks, at their destinations, is 10 ns for PCIe Gen 1 and 12 ns for Gen 2 through 5. In most cases, the 100 MHz reference source is integrated into the SOC or chipset and the reference clock routing to the Root is internal to the SOC or chipset. In some cases, a clock generator IC that is external to the SOC or chipset is used. In any case, the 100 MHz reference source for a COM-HPC Root device is on the COM-HPC Module, either internal or external to the SOC or chipset. The SOC or chipset may provide one or multiple copies of the PCIe reference clock. If the SOC, chipset or Module does not provide enough copies of the reference clock for the Carrier PCIe targets then one or more PCIe clock buffers are used, on and / or off Module, depending on the situation. The PCIe targets use the 100 MHz reference clock copy, along with the clocking information embedded into the PCIe data stream to quickly form a local copy of the appropriate high frequency clock (2.5 GHz for Gen1, 5 GHz for Gen 2, and so on) needed to correctly interpret the incoming PCIe data stream, and to correctly time and encode the target’s outgoing data stream. Table 6 below lists the maximum clock jitter allowed for each PCIe generation, per the PCI-SIG source specifications, for the Common Clock architecture. Note the ever shrinking jitter allowance as the generations advance. For example, the Gen 5 jitter allowance is only 15% of the Gen 3 allowance. However, PCIe Gen 5 uses a different filtering transfer function than Gen 3 and Gen 4, so the comparison is more nuanced than indicated here. Table 6: PCIe Maximum Allowable Clock Jitter
PCIe GenerationSignaling RateReference Clock Max Jitter AllowedNotes
12.5 Gbps86 ps PTPPTP is Peak to Peak
25.0 Gbps3.1 ps RMSRMS is Root Mean Square
38.0 Gbps1.0 ps RMS
416.0 Gbps0.5 ps RMS
532.0 Gbps0.15 ps RMS
664.0 Gbps0.10 ps RMS
Table 7 on the following page defines some PCIe Clock Buffer mode terminology. Table 7: PCIe Clock Buffer Modes
ModeDescriptionPros and Cons
Zero DelayA Clock Buffer PLL keeps the output clock copies in phase with the input clock.Also known as ZDB (Zero Delay Buffer) mode or as PLL mode.Some clock buffers have High Bandwidth and Low Bandwidth PLL modes.Pro: Zero delay makes it easier to meet the maximum skew of 12 ns between any two clocks, especially if the PCIe traces are very long, or if buffers are cascadedThe PLL tends average out the jitter contribution from the source clock (see jitter discussion later in this document section, following Table 8)Con: PLLs buffers may have trouble with a Spread Spectrum source (see discussion following Table 8)
Fan Out or PLL BypassNo PLL used. The output clock copies are an exact frequency copy of the input but are not in phase with the input.Pro: lower jitter from the buffer itself, in most cases (but the source clock jitter must be added to the that of the fan out buffer, per discussion following Table 8)Fan out buffers track a SpreadSpectrum clock source easilyCon: may be harder to meet 12 ns max clock skewAlthough the fan out buffer jitter itself is low, the source clock jitter adds to the fan out buffer jitter
# Timing Delay Discussion For Various PCIe Clock Buffer Scenarios Regarding the max PCIe Reference Clock skew of 12 ns (or 10 ns for PCIe Gen 1) and the use of Fan Out (non – PLL) based clock buffers: a modern Fan Out buffer will have a worst case skew of well under 5 ns (several vendors claim 3 ns max, and at least one claims 1.5 ns max). Signals propagate at about 6 inches per ns, so a system with a 5 ns buffer delay and about 12 inches of PCB trace (2 ns delay) would have a worst case skew of 7 ns which is comfortably within the 12 ns Gen 2 through Gen 5 skew limit. Very long PCIe trace situations might need the Zero Delay Buffer – be aware of the possible issues with spread spectrum sources. However .. if there is a clock buffer on the COM-HPC Module in-between the Root complex PCIe reference clock and the clock(s) going out to the COM-HPC pins, then there will likely be an additional delay time that factors into the analysis in the previous paragraph. Check with your Module vendor on that. As: “what is the skew between the PCIe Reference Clock to the CPU or SOC Root Complex, and the COM-HPC PCIe Clock Reference pins” … it could be anywhere from 0 ns to 5 ns, depending on Module design details. Also: “what is the jitter contribution of a Module PCIe clock buffer” - if there is one. # PCIe Clock Buffer Options – Keep Them Open A PCIe Clock Buffer IC usually has pin-strap(s) and / or SMBus options allowing the Clock Buffer operational modes to be set. It is best to keep access to these options open as sometimes issues can be resolved late in the design cycle (i.e. during regulatory and compliance testing) by changing the operational mode of the PCIe Clock Buffer. For example, Spread Spectrum PCIe reference clock operation may work with some but not all of the Clock Buffer modes. Additionally, some PCIe Clock Buffer devices have mechanisms (such as SMBus registers or OTP ordering options) to change parameters such as output clock slew rate, signal amplitude and / or the output termination values. # Sample PCIe Clock Buffer List A sample collection of PCIe Clock Buffers is given in Table 8 below. Of course this is just a snapshot of what is available and appropriate at the time of this writing. Fan Out Mode jitter is additive (meaning the Module source jitter needs to be added together with the Fan Out buffer jitter). PLL Mode jitter is not additive, hence is marked as Total in the Table. The Module source jitter tends to get averaged out in the PLL. This is described in more detail on the page following Table 8. Table 8: PCIe Clock Buffer Vendors and Part Numbers
VendorPart NumbersNotesRMS Jitter(picoseconds)
Diodes Inc.(Pericom)PI6CB18200 (dual, no internal term)PI6CB18401 (quad, internal term)PI6CB18601 (hex, internal term)PI6CB18801 (octal, internal term)An internal termination value for 100 ohmdifferential traces is implied in the data sheet but not explicitly stated.PCIe Gen 4 capable1.8V suppliesOE# on each outputSMBus configuration optionPin strap configuration optionZero Delay Buffer modesHigh BW PLLLow BW PLLPLL Bypass (aka Fan Out) ModePLL Mode (Total)Gen 1 5.0Gen 2 0.3Gen 3 0.1Gen 4 0.05Fan Out ModeValues not shown in public data sheet
Diodes Inc.(Pericom)PI6CB33202 (dual, 85 ohm internal term)PI6CB33402 (quad, 85 ohm internal term)PI6CB33602 (hex, 85 ohm internal term)PI6CB33802 (octal, 85 ohm internal term)PI6CB33201 (dual, 100 ohm internal term)PI6CB33401 (quad, 100 ohm internal term)PI6CB33601 (hex, 100 ohm internal term)PI6CB33801 (octal, 100 ohm internal term)PCIe Gen 5 capable3.3V power supplyOE# on each outputSMBus configuration optionPin strap configuration optionZero Delay Buffer modesHigh BW PLLLow BW PLLPLL Bypass (aka Fan Out) ModePLL Mode (Total)Gen 1 0.05Gen 2 0.05Gen 3 0.05Gen 4 0.05Gen 5 0.05
Diodes Inc.(Pericom)PI6CB332001A (20 outputs, 85 ohm internal term)PCIe Gen 5 capable3.3V power supplyOE# for 8 outputsSMBus, Side-Band interface support20 HCSL outputs with On-chip TerminationFan Out (Additive)Gen 1 0.03Gen 2 0.03Gen 3 0.03Gen 4 0.03Gen 5 0.12
Renesas(IDT)9DBL0252 (dual, 85 ohm internal term)9DBL0452 (quad, 85 ohm internal term)9DBL0651 (hex, 85 ohm internal term)9DBL0851 (octal, 85 ohm internal term)9DBL0242 (dual, 100 ohm internal term)9DBL0442 (quad, 100 ohm internal term)9DBL0641 (hex, 100 ohm internal term)9DBL0841 (octal, 100 ohm internal term)PCIe Gen 5 capable3.3V power suppliesOE# on each outputSMBus configuration optionPin strap configuration optionZero Delay Buffer modesHigh BW PLLLow BW PLLPLL Bypass (aka Fan Out) ModeFan Out (Additive)Gen 1 5.0Gen 2 0.428Gen 3 0.149Gen 4 0.156Gen 5 0.05PLL Mode (Total)Gen 1 33Gen 2 1.9Gen 3 0.53Gen 4 0.48Gen 5 0.149
Renesas (IDT)9DBL0255 (dual, 85 ohm internal term)9DBL0455 (quad, 85 ohm internal term)Ultra low jitterPCIe Gen 5 capable100 ohm option with ext resistors3.3V power suppliesOE# for each outputFan Out (Additive)Gen 3 0.033Gen 4 0.033Gen 5 0.012
Renesas (IDT)9ZXL0451E (quad, 85 ohm internal term)9ZXL0651E (hex, 85 ohm internal term)9ZXL0851E (octal, 85 ohm internal term)9ZXL1251E (12 out, 85 ohm internal term)PCIe Gen 5 capable3.3V power suppliesOE# on each outputSMBus configuration optionZero Delay Buffer modesHigh BW PLLLow BW PLLPLL Bypass (aka Fan Out) ModeFan Out (Additive)Gen 1 1.9Gen 2 0.126Gen 3 0.062Gen 4 0.062Gen 5 0.024Low BW PLL Mode(Total Jitter)Gen 1 6.8Gen 2 0.12Gen 3 0.07Gen 4 0.07Gen 5 0.018
Skyworks (Silicon Labs)Si53204-A02 (quad, 85 ohm internal term)Si53208-A02 (octal, 85 ohm internal term)Si53212-A02 (12 out, 85 ohm internal term)Si53204-A01 (quad, 100 ohm internal term)Si53208-A01 (octal, 100 ohm internal term)Si53212-A01 (12 out, 100 ohm internal term)Silicon Labs has many other PCIe Clock Buffers, too numerous to list here.PCIe Gen 5 capable1.8V power suppliesOE# on each outputSMBus configuration optionFan Out Mode only (no PLL)Fan Out (Additive)Gen 1 17 (PTP)Gen 2 0.2Gen 3 0.06Gen 4 0.06Gen 5 0.021
Texas InstrumentsLMK00334 (quad output, external term)PCIe Gen 4 capable3.3V and 2.5V suppliesSingle OE#Fan Out Mode onlyFan Out (Additive)Gen 3 0.15Gen 4 0.05
Texas InstrumentsLMK00338 (octal output, external term)PCIe Gen 3 capable3.3V and 2.5V suppliesSingle OE#Fan Out Mode onlyFan Out (Additive)Gen 3 0.15
Texas InstrumentsCDCB2000 (20 outputs, 85 ohm int term)PCIe Gen 5 capable3.3V suppliesOE# for 8 outputsSMBus configuration optionSide Band Interface config optionPLL Mode (Total)Gen 1 5.0Gen 2 0.2Gen 3 0.15Gen 4 0.08Gen 5 0.03
Texas InstrumentsCDCDB800 (octal output, 85 or 100ohm software selectable term)PCIe Gen 5 capable3.3V suppliesOE# on each outputSMBus configuration optionsFan Out Mode onlyPropagation delay 0.5 ns typically3 ns maxFan Out (Additive)Gen 3 0.1Gen 4 0.1Gen 5 0.025
There may be more subtleties in the jitter numbers than is immediately apparent here. For example, some buffers allow the clock output slew rate to be adjusted, but the slew rate may in turn affect the jitter values. Check the vendor data sheets and make use of the vendor application engineers. # Note on the Additive and Total Jitter values in Table 8 Above: These values are taken from silicon vendor data sheets and are meant here as a rough guide. The jitter values for all operational modes (e.g. high PLL BW, low PLL BW etc) of the clock buffer devices may not be shown here. The values in the Table for Fan Out buffers are the “Maximum Additive Jitter” values listed in the vendor data sheets. For PLL buffers, the typical values are usually much lower, often less than half, of the maximum values. Jitter analysis can be tricky. Designers should consult the actual vendor data sheets and vendor application notes before making design decisions. # Note on Fan – Out Buffer Jitter vs. PLL or Zero Delay Buffers If a Fan-Out mode PCIe clock buffer is used, then the clock jitter at the target is the square root of the sum of the squares of the COM-HPC Module clock source and of the Fan-Out buffer jitter, per the expression shown here: $$ \sqrt {J _ {\text {source}} ^ {2} + J _ {\text {buffer}} ^ {2}} $$ For PLL or Zero – Delay mode buffers, the clock jitter at the target is simply the jitter of the PLL buffer as listed in the vendor data sheet. The PLL buffer tends to average out the source clock jitter, unless it is extreme. In other words, with regard to the jitter values shown in Table 8 above, the Fan-Out buffer jitter values are not the full story, as the clock generator source jitter values need to be factored in per the equation above. The source clock generator jitter values need to be obtained from the Module vendor or the SOC vendor data sheets. # Note on the Internal Termination Impedances in Table 8 Above: PCIe Clock Buffer internal output termination values suitable for both 85 ohm and 100 ohm differential traces are shown as being available in Table 8 above. The COM-HPC Base Specification recommends an 85 ohm differential impedance for the PCIe Reference Clocks coming off the Module, and hence into the Carrier Clock Buffer. Designers are free to choose either 85 ohms or 100 ohm differential impedances for their Clock Buffer output distribution. The phrasing “85 ohm internal term” in the Table above means that the device internal termination is appropriate for 85 ohm differential pairs, and similarly for “100 ohm internal term”. # Spread Spectrum Clock (SSC) Operation SSC profiles for different PCIe generations are different, so a PLL based buffer with support for SSC needs to have an appropriate loop bandwidth for the PFD (Phase Frequency Detector) within the PLL. Therefore, it is advisable to check whether a PLL based buffer supports SSC for the PCIe generation it is to be used with. Some clock buffer vendors recommend against using a Spread Spectrum Clock source with their PLL mode parts and recommend the use of a Fan Out buffer instead. Check with your clock buffer vendor and allow for a PLL bypass mode (Fan Out Mode) option if possible. # COM-HPC Reference Clocks vs COM Express / Use of Clock Buffers COM Express Rev 3.0 defines a single PCIe Reference Clock in it’s pinout. COM-HPC Rev 1.0 allows up to five PCIe Reference Clock pairs – there is one COM-HPC Module PCIe Reference Clock pair for each of the five COM-HPC PCIe groups, as outlined in Section 3.6.1. above. # 3.6.9. PCIe Redrivers and Retimers PCIe maximum trace length guidelines are given in Section 4.3.4. below and are presented along with loss budgets and more context in the COM-HPC Base Specification. However, PCIe Gen 3, 4, and 5 implementations may well need a redriver or retimer on the Carrier to make up for signal degradation. A redriver is an analog circuit that reshapes the PCIe signal using sophisticated analog techniques. A nearly closed PCIe signal eye can become a compliant open eye with a redriver. Redrivers may have a digital section in the form of I2C accessible registers or strap pins to set redriver parameters. A retimer is a digital and analog circuit that clocks in the PCIe signal using the PCIe 100 MHz reference clock and an on-chip PLL and reissues the reclocked signal in pristine form. Two popular vendors for PCIe redriver and retimer products are Diodes Inc. (formerly Pericom) (www.diodes.com) and Texas Instruments (www.ti.com). A retimer may possibly yield better results than a redriver, at a cost. Table 9: PCIe Redrivers and Retimers
VendorP/NNotes
Diodes IncPI3EQX16904GLPCIe Gen 4 capable quad lane redriver (4 lanes in one direction)
PI3EQX16908GLPCIe Gen 4 capable octal lane redriver (8 lanes in one direction)
Texas InstrumentsDS160PR410PCIe Gen 4 capable quad lane redriver (4 lanes in one direction)
DS160PR810PCIe Gen 4 capable octal lane redriver (8 lanes in one direction)
DS160PT801PCIe Gen 4 capable 16 lane retimer (8 lanes TX and 8 lanes RX)
DS320PR810PCIe Gen 5 capable octal lane redriver (8 lanes in one direction)
DS320PR822PCIe Gen 5 capable quad 2x2 crosspoint redriver
The items shown in Table 9 above represent only a small sample of parts available on the market. Texas Instruments, for example, has quite a few additional redriver and retimer parts not listed here. Some of the unlisted parts incorporate redriver or retimer functions along with analog multiplexer and cross-point switch functions. # 3.7. USB # 3.7.1. USB Terms and General Information Table 10: USB.org Branding Term Summary
USB.orgCurrent BrandingNominal Bit RatesNotesUSB.orgFormer Branding
USB 2.0480 Mbps(High Speed mode)Single half duplex DC coupled pairAlso supports slower USB 1.1 and 1.0 legacy modesUSB 2.0
USB 3.2 Gen 15 GbpsDual simplex AC coupled transmit pair and a receive pair. Also requires a specific USB 2.0 link, on a separate set of conductors.USB 3.0USB 3.1 Gen 1
USB 3.2 Gen 210 GbpsDual simplex AC coupled transmit pair and a receive pair. Also requires a specific USB 2.0 link, on a separate set of conductors.USB 3.1USB 3.1 Gen 2
USB 3.2 Gen 2x210 Gbps (per lane)20 Gbps (two lanes)Two AC coupled transmit pairs and two receive pairs allowing 20 Gbps operation in each direction. Also requires a specific USB 2.0 link, on a separate set of conductors.
USB4 Gen 2x210 Gbps (per lane)20 Gbps (two lanes)Incorporates USB 3.2 Gen 2x2 and USB 2.0 features, along with additional features such as DisplayPort operation, USB Type-C (reversible) connector, and Thunderbolt 4 support.
USB4 Gen 3x220 Gbps (per lane)40 Gbps (two lanes)Features 20 Gbps bit rate per lane and uses 2 lanes TX and 2 lanes RX. Also includes USB 2.0 features, along with additional features such as DisplayPort operation, USB Type-C (reversible) connector, and Thunderbolt 4 support.
USB SuperSpeedUSB SuperSpeed+5 Gbps10 or 20 GbpsThe high speed interface used in USB 3.2 Gen 1, Gen 2, Gen 2x2 and USB4 is referred to as the SuperSpeed or SuperSpeed+ interface. A USB 3.2 Gen 1, Gen 2, Gen 2x2 or USB4 implementation require both SuperSpeed / SuperSpeed+ support and USB 2.0 support. The SuperSpeed / SuperSpeed+ interface is implemented on a separate set of pins from the USB 2.0 interface. However, every SuperSpeed implementation needs a specific companion USB 2.0 interface.
Actual payload data rates are lower than what is implied by the “Nominal Bit Rates” in the chart above, due to the encoding methods used in the serialized data stream. The most common connector for USB host ports is the Type-A connector. Figure 25 below is a view looking into a USB 3 Type-A host receptacle (the Carrier connector is receptacle, the cable connector is the plug). Some points about this illustration: • A USB 2.0 Type-A connector only has pins 1 through 4 present. Pinout details are in Table 11 below. A USB 3 Type-A connector has 9 pins: ◦ Pins 1 through 4 from the USB 2.0 definition are used for power, GND and a USB 2.0 data pair. ◦ Pins 5 through 9 are used for SuperSpeed or SuperSpeed+ TX and RX pairs and a GND. • A USB 2.0 cable plug may be used with a USB 3 receptacle, but only the USB 2.0 link will function. • A USB 3 cable plug may be used with a USB 2.0 receptacle, but only the USB 2.0 link will function. ◦ The USB 3 pins 5 through 9 are cleverly positioned so that they are invisible to the USB 2.0 plug. • USB 2.0 target devices are allowed to consume up to 500 mA at 5V on a Type-A connector. • USB 3 target devices are allowed to consume up to 900 mA at 5V on a Type-A connector. Figure 25: USB 3 Type-A Connector Receptacle – Looking Into the Receptacle ![9 8 7 6 5 1 2 3 4](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/26b3f642f7032e968c673fe875db56318f3b59cf059db5cf363cc2cd33809b98.jpg) Table 11: USB Type-A Pin-Out
PinSignalSignal DescriptionNotes
1VBUS5V current limited USB target power500mA (USB 2) or 900mA (USB 3)
2D-USB 2.0 differential signal (-)
3D+USB 2.0 differential signal (+)
4GNDGND for USB 2.0 pair and power
5SSRX-USB SuperSpeed RX(-)Not used / not present on USB 2.0
6SSRX+USB SuperSpeed RX(+)Not used / not present on USB 2.0
7GNDGND for SuperSpeed RX and TX cable drain wireNot used / not present on USB 2.0
8SSTX-USB SuperSpeed TX(-)Not used / not present on USB 2.0
9SSTX+USB SuperSpeed TX(+)Not used / not present on USB 2.0
# Type-A Connector Electrical Distinctions There are three general categories of USB Type-A connectors: USB 2.0 480 Mbps USB 2.0 signaling (no USB 3) – 4 pin connector • USB 3.2 Gen 1 5 Gbps SuperSpeed signaling (along with USB 2.0) - 9 pin connector • USB 3.2 Gen 2 10 Gbps SuperSpeed+ signaling (along with USB 2.0) – 9 pin connector For USB 2.0 and USB 3.2 Gen 1 Type-A connectors, there are many vendors and styles (R/A, vertical, single, dual, quad combinations, combinations with other standards such as GbE etc). For USB 3.2 Gen 2 (10 Gbps pair signaling), there are not many Type-A connector parts available as of this writing. Amphenol FCI is a connector vendor that has several 10 Gbps capable Type-A connectors available. Amphenol FCI GSB4111312HR, for example is a single R/A version of such a part. Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5. through 3.7.11. below. # 3.7.2. USB 2.0 Type-A Example Figure 26: USB 2.0 Type-A Example ![+5V_A C201 C202 1u 16V 100n 25V D402 D402 R155 1 2 10K 3 EN FAULT# RT9728AHGE R2138 0 0402 EN_RSMRST +5V_A C206 C207 1u 16V 100n 25V D402 D402 R157 1 2 10K 3 EN FAULT# RT9728AHGE R2140 0 0402 EN_RSMRST +5V_A C201 U32 VOUT 6 VIN GND ILIM 5 EN FAULT# R156 4 43K 0402 C203 FB7 C204 +5V_USB5 Size C 150u 10V D32 ESD9X5.0ST5G USB5- USB5+ COM COM DLW21HN900SQ2 USB5 N USB5 P 3 4 CN20 TE 5787745 UPPER USB +5VA D- D+ GNDA LOWER USB +5VB D- D+ GNDB SH(4) SHIELD R301 0603 +5V_A R2146 4.7K 0402 EN_RSMRST Q76A 2N7002DW RSMRST_OUT# COM R2147 100K 0402 Q76B 2N7002DW D33 D33 USB5_N USB5_P 3 USB4_P 4 USB4_N DRTR5V0U4LP16](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/5564a784bb749701e47691b9378f00bb6eb455f2abb514971456975bc567510c.jpg) Figure 26 above illustrates a typical USB 2.0 implementation on a Carrier. The USB 2.0 data lines must be routed as differential pairs, in a no-stub fashion. Components T9 and T10 are common-mode chokes that are an EMI mitigation measure. Component D33 is a ESD protection diode array. Pins 1,3,4,6 may be exchanged if needed to provide the easiest no-stub routing. Components U32 and U33 are USB power switches and current limiters. For USB 2.0, the current delivered to a USB target device is to be limited to about 500 mA. ◦ The power switch / current limiter shown is from Richtek. There are many similar parts available from Texas Instruments, Micrel, Microchip and others. The current limiter IC FAULT# pins are tied to the COM Module USB port 4 and 5 over-current input. There are 4 such inputs (for USB 0,1 and USB 2,3 and USB 4,5 and USB 6,7). The 5V power traces involved between the USB power switches, through FB7 and FB8 and on to connector CN20 must be sized to carry the 1A current (and this should be increased to 1.5 or 2 A to allow for a safety factor). The power switches are enabled by the COM-HPC RSMRST\_OUT# signal. This signal going high indicates that the +5V\_A power rail is stable. This example applies to the Mini, except that the RSMRST\_OUT# signal is a 1.8V signal and the gate threshold of the 2N7002 FET (Q76B) can be as high as 2.5V. A different FET with a lower threshold needs to be used, or the RSMRST\_OUT# needs to be level shifted using an alternate method. The Rohm RA1C030LD is a suitable part with a Vgs gate threshold between 0.5V and 1.5V. The USB over-current signal (net USB45\_OC#) is not a problem for the Mini as the current limiting IC outputs driving this net are open drain pins on U32 and U33 and the signal is pulled up on the Mini Module. # USB 2.0 Allocation Notes – Client and Server Modules The COM-HPC Client and Server pinouts allow up to eight USB 2.0 ports each. Note however that the first four USB 2.0 ports (COM-HPC USB0+/- through USB3+/-) are paired with the corresponding USB SuperSpeed ports (COM-HPC USB0\_SSTX0+/- and USB0\_SSRX0+/- through USB3\_SSTX0+/- and USB3RX0+/-). A USB SuperSpeed port needs a specific companion USB 2.0 pair for certain setup functions. Thus … if the Carrier needs one or more USB 2.0 only ports (no SuperSpeed) in addition to the four SuperSpeed capable ports, the above pairings need to be considered. COM-HPC USB4+/- through USB7+/- are USB 2.0 only ports. # USB 2.0 Allocation Notes – COM-HPC Mini Modules USB 2.0 resource allocations are different on the COM-HPC Mini than on the Client and Server. The allocations on the Mini are well described in the COM-HPC Base Specification Section 10. USB 2.0 channels 6 and 7 are reserved for USB 2.0 use only on the Mini. # 3.7.3. USB 3.2 Gen 1 and Gen 2 Type-A A USB 3.2 Gen 1 example on a Type-A connector is given in the COM Express Carrier Design Guide Rev 2.0 Section 2.9. At the time that the COMe Design Guide was written, USB 3.2 Gen 1 (single SuperSpeed TX pair and single RX pair, 5 Gbps signaling, plus a USB 2.0 pair) was referred to as USB 3.0. A USB 3.2 Gen 2 Type-A connector implementation (single SuperSpeed+ TX pair and single RX pair, 10 Gbps signaling) is basically the same as a Gen 1 implementation, except that the components involved may need an upgrade for the 10 Gbps signaling: lower capacitance ESD diodes, different common mode choke choices and a connector receptacle appropriate for 10 Gbps signaling. An additional consideration is that there may be a greater need for a redriver. Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5. through 3.7.11. below. No USB 3 redriver is shown in the COM Express Carrier Design Guide example. If the traces from the COM-HPC Module connector to the Type-A host receptacle are more than a few inches, then a Carrier redriver may be advisable. # 3.7.4. USB 3 Redrivers Table 12: USB 3 Redrivers
VendorP/NNotes
Diodes IncPI3EQX7841USB 3.1 Gen 1 capable single port redriver (1 TX pair and 1 RX pair)5 Gbps per pair
PI3EQX1004EUSB 3.1 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs)10 Gbps per pair
Texas InstrumentsTUSB522PUSB 3.2 Gen 1 capable single port redriver (1 TX pair and 1 RX pair)5 Gbps per pair
TUSB1002AUSB 3.2 Gen 2 capable single port redriver (1 TX pair and 1 RX pair)10 Gbps per pair
TUSB1004USB 3.2 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs)10 Gbps per pairMay be used to support two USB 3.2 Gen 2 ports
The items shown in Table 12 above represent only a small sample of such parts available on the market. USB Type-C Port Multiplexers, which may include redriver and retimer capabilities, are listed in Table 14 below. USB Type-C implementations are covered in Sections 3.7.5. through 3.7.10. below, and USB4 in Section 3.7.11. . # USB Hubs – May Serve as Retimers USB 2 and USB 3 hubs are plentiful and may be considered as a form of a USB retimer: they clock the USB 2 and 3 signals in, process them and clock them out in fresh form. Of course the downstream bandwidth is shared, if more than one downstream hub port is used. Microchip Technologies (www.microchip.com) seems to be the dominant USB hub supplier and has dozens of offerings. Granted, there may be some software subtleties concerning the use of USB hubs versus true USB retimers (a true retimer should be invisible to software apart from possible setup; a hub has to be enumerated by the operating system, etc.). # 3.7.5. USB Type-C Overview USB Type-C refers to a small form factor reversible connector definition (reversible cable plug, no polarity, can be inserted with either orientation), and to the USB and other data and negotiated power delivery formats that it supports. Some highlights include: Polarity free operation ◦ Cable plug can be used in either orientation USB 2.0 ( 480 Mbps signaling) • USB 3.2 Gen 1 x1 and Gen 2 x 1 ( 5 Gbps, 10 Gbps signaling) (single lane) • USB 3.2 Gen 1 x2 and Gen 2 x 2 ( 10 Gbps, 20 Gbps signaling) (2 lanes) “Alternate Modes” including ◦ DisplayPort (2 lanes) + USB 3.2 ◦ DisplayPort (4 lanes) 。 HDMI 。 Intel Thunderbolt 。 Other vendor specific Alternate Modes USB4, described Section 3.7.11. below. USB Power Delivery (PD) protocol and implementation 。 Allows negotiated power delivery, from 5V up to 20V and up to 100W. • Active cable support (electronics within the USB cable assembly) For an excellent explanation of USB Type-C features, capabilities and details on how they work, see the Microchip Technologies Application Note AN1953 Introduction to USB Type-C. Much of the information in this section has been adapted from this note. A typical Type-C receptacle is shown in Figure 27 below, at the left. A typical cable plug is shown at the right. The connector is fairly small, with an overall width less than 9mm and body height just under 3mm. These dimensions are similar but slightly larger than the Apple Computer “Lightening” connectors that are popular on consumer cell phones. The USB Type-C connector system has more capabilities than the “Lightening” system. The receptacle and corresponding cable plugs are mechanically symmetrical and the cable plug can be used in either orientation. The connector pinout, presented on the following page, is almost completely symmetrical. There are some locking versions of the USB Type-C connector available. Figure 27: USB Type-C Receptacle and Plug Images ![Two electronic connectors shown: a metallic USB connector and a black USB cable (no text or symbols visible)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/830572d8158d6537c81fdc5929630a4cb0fc368fe3e9d16d5b9f48cbb10988d4.jpg) Figure 28: USB Type-C Receptacle Pin-Out – Looking Into Carrier Receptacle ![ Position Gene Set Position Label --- --- --- A1 GND TX1+ A2 GND TX1- A3 GND VBUS A4 GND CC1 A5 GND D+ A6 GND D- A7 GND SBU1 A8 GND VBUS A9 GND RX2- A10 GND RX2+ B12 B12 B11 B10 B10 B9 B9 B9 B8 B8 B8 B7 B7 B7 B6 B6 B6 B5 B5 B5 B4 B4 B4 B3 B3 B3 B2 B2 B2 B1 A12 A12 GND ](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/987d41295c785da1e1a60d401d854463b6692acf4a83300fd4f7436d2cec3a3f.jpg) Note that the Type-C receptacle connector pinout is mostly symmetrical with respect to flipping the plug connector. If the connector plug is inserted “right side up” (plug A1 to receptacle A1 etc.), all plug and receptacle signals match. If the connector plug is inserted “upside down” (plug A1 to receptacle B1 etc) then a few things must be sorted out by Carrier hardware, as explained on the following pages. Table 13: USB Type-C Connector Pinout
PinSignal NameSignal Description
A1GND
A2TX1+SuperSpeed TX1+
A3TX1-SuperSpeed TX1-
A4VBUSBus Power to Peripheral USB device
A5CC1Configuration Channel 1 or VCONN
A6D+USB 2.0 D+
A7D-USB 2.0 D-
A8SBU1Side Band Use 1
A9VBUSBus Power to Peripheral USB device
A10RX2-SuperSpeed RX2-
A11RX2+SuperSpeed RX2+
A12GND
PinSignal NameSignal Description
B12GND
B11RX1+SuperSpeed RX1+
B10RX1-SuperSpeed RX1-
B9VBUSBus Power to Peripheral USB device
B8SBU2Side Band Use 2
B7D-USB 2.0 D-
B6D+USB 2.0 D+
B5CC2Configuration Channel 2 or VCONN
B4VBUSBus Power to Peripheral USB device
B3RX1-SuperSpeed TX2-
B2RX1+SuperSpeed TX2+
B1GND
For the yellow shaded cells in the Table above, the ‘A’ and ‘B’ signals have complete symmetry and nothing at all needs to be done to sort them out if the cable plug is “upside down”. The non-shaded signals need some help in the “upside down” case – to get the plug signals to the correct Carrier destinations. Multiplexers are involved, and, to reduce stubs and preserve signal integrity, the “right side up” signals are usually routed through multiplexers along with the “upside down”. signals. # USB 2.0 D+ and D- The USB 2.0 D+ and D- differential pair data lines are arranged in a symmetrical block in the USB Type-C pinout definition. This arrangement has the result that no signal multiplexing is needed for “right side up” and “upside down” cable plug insertions. However, as a consequence of this arrangement, there are some short signal stubs. Since the USB 2.0 signaling rate is relatively low (480 Mbps), this is not a problem. # VBUS VBUS is the power source provided by the host system (the COM-HPC Carrier in this case) to the attached downstream port. It can be the traditional fixed 5V current limited supply per USB 2.0 or USB 3.x, or it can be a higher voltage supply, up to 20V, and up to 100W, as negotiated by implementations following the USB Type-C Power Delivery Specification. The Power Delivery (PD) negotiation and implementation capability is optional, but necessary for higher powered peripherals. The PD negotiation happens over one of the two CC lines. Note that there are four VBUS pins and four GND pins. All eight pins should be used, to handle the possibly high power and current levels. # VCONN VCONN is 5V nominal 1W max power source for active USB cables. Active cables have internal electronics that boost the signals carried, allowing longer cable assembles. The electronics in an Active cable may take their power from VCONN or VBUS. VCONN is routed to the receptacle CC2 pin if the plug is “right side up” or to the receptacle CC1 pin if the plug is “upside down”. # CC1 and CC2 Configuration Channel Signals The CC1 and CC2 signals serve several purposes in USB Type-C implementations: The CC1 and CC2 pins are used by the host system to identify whether the cable plug is inserted “right side up” or “upside down”, through an analog detection process, relying on certain resistor values on the host side and on the downstream port side. The CC1 and CC2 signals are also used to identify the basic host power delivery requirements to the downstream peripheral. A resistor scheme and analog measurements are used to identify 5V 500 mA. 1.5A and 3A possibilities. The receptacle CC1 pin (if the plug connector is “rightside up”) or the receptacle CC2 pin (plug connector is “upside down”) may be used to negotiate the USB Type-C Power Delivery using a one – wire protocol defined in the USB Power Delivery Specification. This is optional but necessary if the peripheral needs a VBUS voltage over 5V. VCONN power is distributed to the “unused” CC pin (CC2 for plug “rightside up” and CC1 for plug “upside down”). • The Microchip application note AN1953 explains the CC1 and CC2 operational details very well. # SuperSpeed TX1+, TX1-, RX1+, RX1- If the cable plug is “rightside up” then these pins are used for the USB 3.2 Gen 1 and Gen 2 single lane SuperSpeed signals, or for the first lane of a two lane implementation. If the cable plug is “upside down” then the cable TX1+, TX1-, RX1+ and RX1- signals land on the receptacle TX2+, TX2-, RX2+ and RX2- pins. In this case, Carrier hardware has to route these signals to the proper TX1+, TX1-, RX1+ and RX1- destinations on the Carrier board. In practice, a Carrier Board multiplexer is used to route the receptacle TX1 and RX1 pairs to the proper Carrier destination, as the signals are high speed and stubs must be avoided. In some cases, the TX1 and RX1 high speed pairs are used for “Alternate Mode” purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol. # SuperSpeed TX2+, TX2-, RX2+, RX2- If the cable plug is “rightside up” then these pins may be used for the second lane set of a USB 3.2 Gen 1x2 or Gen 2x2 implementation. If the cable plug is “upside down” then the cable TX2+. TX2-, RX2+ and RX2- signals land on the receptacle TX1+, TX1-, RX1+ and RX1- pins. In this case, Carrier hardware has to route these signals to the proper TX2+. TX2-, RX2+ and RX2- destinations on the Carrier board. In practice, a Carrier Board multiplexer is used to route the receptacle TX2 and RX2 pairs to the proper Carrier destination. In some cases, the TX2 and RX2 high speed pairs are used for “Alternate Mode” purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol. • A common Alternate Mode usage of these pairs is for a DisplayPort implementation. # SBU1 and SBU2 SBU is an acronym for Side Band Use. • These are optional signals, not needed for USB only implementations. • For the DisplayPort Alternate Mode, these signals are used for the DisplayPort Aux Channel pair. For an HDMI Port Alternate Mode, these signals are used for the HDMI I2C channel. # 3.7.6. USB Type-C Port Multiplexers Selecting a USB Type-C Port Multiplexer can be tricky. It is important to understand what it does, and does not do, and what software support is available. Tables 14 lays out some of the possibilities. It is best to work with the silicon vendor and Module vendor FAEs on the details. It’s pretty difficult, but not impossible, to cover all the possible USB Type-C modes in a single design. All the USB Type-C Port Multiplexers listed in this Table incorporate redriver or retimer functions, reducing part count. Table 14: USB Type-C Port Multiplexers – Possible Modes
RefModeNotesPossible Part(s)Part Notes
1USB 3.2 Gen 1x15 Gbps signaling single SuperSpeed TX pair and single RX pair usedTUSB542TUSB1042TUSB1104TUSB1142TUSB1146Intel JHL9040RTUSB542 is 5 GbpsOthers are 10 Gbps capable
2USB 3.2 Gen 2x110 Gbps signaling single SuperSpeed+ TX pair and single RX pair usedTUSB1042TUSB1044TUSB1046TUSB1104TUSB1142TUSB1146Intel JHL9040R10 Gbps capable parts
3USB 3.2 Gen 1x25 Gbps signaling per pair dual SuperSpeed TX pairs and dual RX pairs used10 Gbps net TX speed, 10 Gbps net RX speedTUSB1104
4USB 3.2 Gen 2x210 Gbps signaling per pair dual SuperSpeed+ TX pairs and dual RX pairs used20 Gbps net TX speed, 20 Gbps net RX speedTUSB1104
5DisplayPort Alternate Mode2 DP lanes + USB 3 Separate DP SourceUSB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1Two DP pairs on TX2 / RX2 (RX2 used as DP TX pair)DP sourced externally, from GPU pinsTUSB546A-DCITUSB1044TUSB1046TUSB1046A-DCITUSB1146TUSB546A-DCI is 5 GbpsOthers are 10 Gbps capable
6DisplayPort Alternate Mode4 DP lanesSeparate DP SourceNo USB 3 at all (USB 2 remains)Four DisplayPort pairs on TX1,RX1,TX2,RX2DP sourced externally, from GPU pinsTUSB546A-DCITUSB1046A-DCITUSB1046TUSB1146TUSB546A-DCI is 5 GbpsOthers are 10 Gbps capable
7DisplayPort Alternate Mode2 DP lanes + USB 3USB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1Two DP pairs on TX2 / RX2 (RX2 used as DP TX pair)DP multiplexed with USB 3 within chip-setTUSB544TUSB1044Intel JHL9040R
8DisplayPort Alternate Mode4 DP lanesNo USB 3 at all (USB 2 remains)Four DisplayPort pairs on TX1,RX1,TX2,RX2DP multiplexed with USB 3 within chip-setTUSB544TUSB1044Intel JHL9040R
9HDMI Alternate ModesSimilar to DP Alternate ModesTUSB546
10USB4: 20 Gbps onlyAll USB3 modesUSB4: 20 Gbps signaling using 2 lanesDP Alternate ModesIntel JHL9040R
11Thunderbolt ModesAll USB 3 modesUSB4: 20 Gbps signaling, 40 Gbps using 2 lanesDP Alternate ModesPCIe Alternate ModeIntel JHL8940R
# Notes on Table 14: • All the “TUSB” prefixed parts listed above are from Texas Instruments • The Intel JHL9040R is a USB4 retimer part, formerly known as the “Hayden Bridge”. # 3.7.7. USB Type-C Power Delivery Controllers The USB Type-C specification is an ambitious specification with many features. For Power Delivery, the specification allows up to 100W of power, over a voltage range from 5V to 20V, to be delivered either out of the device in question or accepted into the device. For example, a laptop computer might want to provide power to an external display or printer in some situations. In a different situation, the same laptop may want to accept power from an external charger for battery recharging. The Power Delivery options are negotiated over the USB Type-C CC lines. If there is no negotiation, than a simple old style USB 3.0 or USB 2.0 Type-A power delivery out of the COM-HPC host is assumed Sections 3.7.10. and 3.7.11. below, and more specifically in Figures 34 and 35 below show a USB Type-C Power Delivery solution that allows 15W max power at 5V, out of the COM-HPC carrier to an external device. The Texas Instruments TPS65994 Power Delivery controller is shown. This is actually a dual part that could support two USB Type-C ports. Only one port is used in the Section 3.7.10. USB 3.2 Gen 2x2 example, and similarly for the Section 3.7.11. USB4 port example. Higher power levels (up to 100W, voltages over 5V to 20V range), either out or into the COM-HPC Carrier are possible with other PD controllers. For example, the Texas Instruments TPS65987D device allows up to 100W power delivery, over a 5V to 20V range, out of or into the system, using integrated power FETs. The voltage level, the current level and the current direction are negotiated over the CC lines before power is applied to, or accepted from, the USB Type-C VBUS. The TPS65994 device used in the USB 3,2 Gen 2x2 and USB4 design examples below has a provision, using external power FETs, for up to 100W to come in to the design, but this capability is not used in these examples. There are many additional USB Type-C Power Delivery controllers available from Cypress Semiconductor (now part of Infineon), Microchip Technologies, NXP, On Semiconductor, Texas Instruments and others. # 3.7.8. USB Type-C Port Protection Components It is important to protect USB Type-C port pins against accidental exposure to 20V VBUS contact, and against ESD events. The USB 3.2 Gen 2x2 and USB4 schematic examples (Sections 3.7.10. and 3.7.11. below) illustrate this. The example here uses a Texas Instruments TPD6S300 USB Type-C Port Protector to protect the Type-C CC lines (2 pins), SBU lines (2 pins) and the USB 2.0 lines (4 pins, in the Type-C implementation). This is shown in Figure 35 below. Note: since these examples were created, Texas Instruments has upgraded their Type-C Port Protector to the TPD6S300A and that should be used for new designs. The high speed data pairs (2 TX pairs and 2 RX pairs, for USB, DP, HDMI etc) are protected separately in these schematic examples, using discrete low capacitance ESD diodes. This is shown in Figure 35 below. There are many other possible USB Type-C Port Protection components, from Texas Instruments, Microchip Technologies, On Semiconductor, NXP and others. If the COM-HPC is implementing a battery powered option, then there are battery charging and dead battery concerns to consider. Refer to the Texas Instruments and Microchip Technologies data sheets and application notes for more technical information on this. # 3.7.9. USB 3.2 Gen 2x1 Type-C Basic Implementation A basic USB Type-C implementation that supports USB 2.0, USB 3.2 Gen 1 x1 and USB 3.2 Gen 2x1 is straightforward. An example is presented in Figure 29 on the following page. Although this example is in block diagram format and does not include the many passive components needed for a complete design, it only requires two small ICs. This Type-C example is hardly any more complex than a traditional USB 3 Type A , design, especially if a redriver is included in the Type A design. The example in Figure 29 includes a USB Type-C port multiplexer and USB 3 redriver in a single IC package that can be placed close to the Type-C connector receptacle to best launch the signal over the USB cable. Note that TX line coupling capacitors are needed on the redriver output pins. The example also includes a USB Type-C Power Source controller that performs cable detection, provides cable orientation information, provides VBUS power and VCONN power and current limiting for both, along with fault detection. This part does not implement the full USB Power Delivery protocol – this is not necessary here as the VBUS power is limited to traditional USB 3 values of 5V nominal, 1A operational and 1.5A fault current. An implementation that allows the full USB Type-C Power Delivery gamut (5V to 20V, up to 100W) requires a more complex Power Source or Delivery part, that implements the one-wire negotiation on the CC1 or CC2 lines (depending on cable plug insertion polarity). There are many useful parts for USB Type-C support available from Texas Instruments, Microchip Technology, Diodes Inc. and other vendors. Figure 29 below uses the COM-HPC USB0 port as an example (for USB 2.0 and USB 3.2 signals). Any of the first four COM-HPC USB ports (USB0 through USB3) may be used. Remember that COM-HPC USB 2 and USB 3 ports are paired together. See the notes on this in the COM-HPC Base Specification V1.0 Table 15. Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2 ![Based on the provided block diagram, here is the accurate description of the labeled blocks and connections: **1. Left Side Inputs and Power Source** * **COM Blocks:** Several diamond-shaped blocks labeled 'COM' serve as input sources. * `USB0+` and `USB0-` originate from the top COM blocks. * `USB0_SSTX0+` and `USB0_SSTX0-` originate from the middle COM blocks. * `USB0_SSRX0+` and `USB0_SSRX0-` originate from the lower middle COM blocks. * `USB01_OC#` originates from the bottom COM block. * **Power:** `5V BUS POWER` connects to the bottom block's `IN` pin. **2. Top Block: USB Type-C Mux and Redriver** * **Labels:** 'USB Type-C Mux and Redriver USB 3.1 Gen 2 Capable (10 Gbps)' and 'Texas Inst TUSB1142 or TUSB1042'. * **Internal Components:** Contains a 'TX PAIR MUX' and an 'RX PAIR MUX'. * **TX Path (Transmit):** * `USB0_SSTX0+` and `USB0_SSTX0-` enter the 'TX PAIR MUX' after passing through capacitors (encircled by a dashed blue line). * *Note:* A text box states, 'These series caps are needed on the Carrier for the COM-HPC Mini. For a COM-HPC Client implementation, these caps are on the Module'. * Outputs `TX1+`, `TX1-`, `TX2+`, and `TX2-` exit the mux, pass through capacitors, and connect to the right-side block. * **RX Path (Receive):** * Signals `RX1+`, `RX1-`, `RX2+`, and `RX2-` enter the 'RX PAIR MUX' from the right side after passing through capacitors (enclosed in a dashed purple box). * *Note:* A text box states, 'These series coupling caps are optional and are only needed if they are not present on the device being attached.' * Outputs `USB0_SSRX0+` and `USB0_SSRX0-` exit the mux, pass through capacitors, and return to the COM blocks. * **Control Pins:** `FLIP` and `CTL0` pins connect to the bottom block. **3. Bottom Block: Power Source Controller** * **Labels:** 'Texas Inst TPS25820' and 'USB Type-C Power Source Controller'. * **Connections:** * `IN` pin receives `5V BUS POWER`. * `OUT` pin outputs `VBUS` (red line) to the right-side block. * `CC1` and `CC2` pins connect to lines labeled `CC or VCONN` which go to the right-side block. * `POL#` connects to the `FLIP` pin of the top block. * `SINK#` connects to the `CTL0` pin of the top block. * `FAULT#` connects to `USB01_OC#` from the left COM block. **4. Right Side Block: Receptacle** * **Label:** 'USB Type-C Receptacle' (vertical text). * **Connections:** Receives connections from `USB0+`, `USB0-`, the TX lines (`TX1+/TX1-`, `TX2+/TX2-`), `VBUS`, `CC or VCONN` lines, and the RX lines (`RX1+/RX1-`, `RX2+/RX2-`).](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/31a037e886048ec6039b168725c32d603cb7ed516b64868069430e508934f550.jpg) # 3.7.10. USB 3.2 Gen 2x2 Type-C Example Implementation A detailed schematic example of a USB 3.2 Gen 2x2 implementation (meaning two USB SuperSpeed TX pairs and two RX pairs, each pair capable of 10 Gbps signaling) is shown in Figures 30 through 35 below. The net TX signaling over two pairs is 20 Gbps, and the net RX signaling over two pairs is 20 Gbps This is delivered over a Type-C reversible connector. A Type-C port multiplexer shown in Figure 31 below Texas Instruments (TI) TUSB1104 is an optimal part for this application. A single TX and RX SuperSpeed pair Type-A connector option is implied by some resistor stuffing options in Figure 30 below (R5W6 through R5W9, not populated) but the Type-A connector details are not shown in this Figure set. The Type-A implementation is discussed in Section 3.7.3. above. This example includes a USB Power Delivery controller, Texas Instruments TPS65994, in Figure 34 below. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7. above more some discussion on Power Delivery controllers. Figure 30: USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A ![Based on the provided circuit diagram, here is the accurate and concise description: **Top Section (FROM COM-HPC CONN)** * **Header:** 'CAD NOTE:', 'TRI-PAD OPTION', 'FROM COM-HPC CONN' * **Blocks (Resistors):** * **R5W9:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R5W8:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R4W15:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R4W14:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R5W7:** '0201 EMPTY 0 0%' (Pins 1-2) * **R5W6:** '0201 EMPTY 0 0%' (Pins 1-2) * **R4W9:** '0201 EMPTY 0 0%' (Pins 1-2) * **R4W8:** '0201 EMPTY 0 0%' (Pins 1-2) * **Connections:** * **USB0_SSTX0-:** Originates from 'COM'. Splits to **R5W9** (pin 1) and **R5W7** (pin 1). **R5W9** (pin 2) connects to 'OUT' (USB0_SSTX0_TCP-). **R5W7** (pin 2) connects to 'OUT' (USB0_SSTX0_TYPA-). * **USB0_SSTX0+:** Originates from 'COM'. Splits to **R5W8** (pin 1) and **R5W6** (pin 1). **R5W8** (pin 2) connects to 'OUT' (USB0_SSTX0_TCP+). **R5W6** (pin 2) connects to 'OUT' (USB0_SSTX0_TYPA+). * **USB0_SSRX0-:** Originates from 'COM'. Splits to **R4W15** (pin 1) and **R4W9** (pin 1). **R4W15** (pin 2) connects to 'IN' (USB0_SSRX0_TCP-). **R4W9** (pin 2) connects to 'IN' (USB0_SSRX0_TYPA-). * **USB0_SSRX0+:** Originates from 'COM'. Splits to **R4W14** (pin 1) and **R4W8** (pin 1). **R4W14** (pin 2) connects to 'IN' (USB0_SSRX0_TCP+). **R4W8** (pin 2) connects to 'IN' (USB0_SSRX0_TYPA+). **Bottom Section** * **Header:** 'CAD NOTE:', 'TRI-PAD OPTION' * **Blocks (Resistors):** * **R6J10:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R6J5:** '0201 RES 0.05W 0 0%' (Pins 1-2) * **R6J11:** '0201 EMPTY 0 0%' (Pins 1-2) * **R6J6:** '0201 EMPTY 0 0%' (Pins 1-2) * **Connections:** * **USB0-:** Originates from 'COM'. Splits to **R6J10** (pin 1) and **R6J11** (pin 1). **R6J10** (pin 2) connects to 'BI' (USB2_P0_TCP-). **R6J11** (pin 2) connects to 'BI' (USB2_P0_TYPA-). * **USB0+:** Originates from 'COM'. Splits to **R6J5** (pin 1) and **R6J6** (pin 1). **R6J5** (pin 2) connects to 'BI' (USB2_P0_TCP+). **R6J6** (pin 2) connects to 'BI' (USB2_P0_TYPA+). **Footer:** 'H30143-001'](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/59796a8a9bc03975598b0cd409ed7c89d22621fcb84a2631109f29db8641a4d9.jpg) Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver ![Note: For COM-HPC Mini these resistors need to be changed to capacitors. COM-HPC Mini: There may need to be level translation on the some of the single ended sideband signals if they destined for a 1.8V level I/O. PIN STRAP MODE = F (I2C MODE) VIO_SEL = F (3.3V I2C) A1 = F A0 = 0 I2C ADR = 0X10 (7BIT) AEQENC = SDA AEQCFG = CTRL BY FULLAEQ_UPPER_EQ REGISTER 4-Level Control Pin Settings LEVEL SETTINGS 0 Option 1: Tie 1-4Ohm 5% to GND Option2: Tie directly to GND R Tie 20+Ohm 5% to GND F Float (leave pin open) 1 Option 1: Tie 1-4Ohm 5% to VCC Option2: Tie directly to VCC CU5W9 A36096-125 10UF 0.1UF 10% 10V 25V X5R 0402 C5W10 0.1UF 10% 10V 25V X7R 0402 C4W14 0.1UF 10% 10V 25V X7R 0402 C4W7 A36096-112 0.1UF 10% 10V 25V X7R 0402 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 TUSB1104 U5W2 IC EN VCC 6 SLP_SO_N VCC 20 SSTX2_DP CTX2_DP OUT SSTX2_DN CTX2_DN OUT SSRX2_DP CRX2_DP OUT SSRX2_DN CRX2_DN IN SSTX1_DP CTX1_DP OUT SSTX1_DN CTX1_DN OUT SSRX1_DP CRX1_DP OUT SSRX1_DN CRX1_DN IN SSEQ1/AI TESTOUT2 NC USBCO RDVR TESTOUT2 SSEQ/AID TESTOUT1 NC USBCO RDVR TESTOUT1 TEST1 MODE FLIP/SCL AEQENZ/SDA CEQ1 NC NC USBCO RDVR 5 NC USBCO RDVR 5 CEQ0 NC NC USBCO RDVR 11 NC USBCO RDVR 11 CEQ0 NC NC USBCO RDVR 24 NC USBCO RDVR 24 VIO_SEL NC NC USBCO RDVR 23 NC USBCO RDVR 23 AEQCFG NC NC USBCO RDVR 32 NC USBCO RDVR 32 EQCFG TP_TPD GND M28498-001 GND +V3P3_A R4W36 R4W56 R4W40 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W56 R4W36 R4W55 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W57 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W56 R4W57 R4W56 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W57 R4W58 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 A3939-023 BRS DREF EN RES EQUITY COLDING TO PIN 21/22 CLOSE TO IC +V3P3_A SETTINGS Tie 20+Ohm 5% to GND Float (leave pin open) Option 1: Tie 1-4Ohm 5% to VCC Option2: Tie directly to VCC](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/95ede80adf488215bb4796013ca0f4891783c5d6672588588e84485d3e0169da.jpg) Figure 32: USB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD ProtectionFROM REDRIVER ![This block diagram depicts four differential signal pairs, split into transmission (Tx) and reception (Rx) sections. **Section 1: USB0_SSTX0** * **Top Trace:** `IN` connects to `USB0_SSTX0_RDVR-`. This node connects in parallel to `R4Y6` (pins 1, 2) and `L4Y3` (pins 1, 2). * `R4Y6` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * `L4Y3` text: `J16541-001`, `CHOKE`, `100MA`, `SM_A`, `90 30%`. * Output: `USB0_SSTX0_L-` connects to `OUT`. * **Bottom Trace:** `IN` connects to `USB0_SSTX0_RDVR+`. This node connects to `R4Y5` (pins 1, 2). * `R4Y5` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * Output: `USB0_SSTX0_L+` connects to `OUT`. Text `H30143-001` is near the output. **Section 2: USB0_SSTX1** * **Top Trace:** `IN` connects to `USB0_SSTX1_RDVR+`. This node connects in parallel to `R4Y12` (pins 1, 2) and `L4Y6` (pins 1, 2). * `R4Y12` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * `L4Y6` text: `J16541-001`, `CHOKE`, `100MA`, `SM_A`, `90 30%`. * Output: `USB0_SSTX1_L+` connects to `OUT`. * **Bottom Trace:** `IN` connects to `USB0_SSTX1_RDVR-`. This node connects to `R4Y11` (pins 1, 2). * `R4Y11` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * Output: `USB0_SSTX1_L-` connects to `OUT`. Text `H30143-001` is near the output. **Section 3: USB0_SSRX0 (Flow is Right to Left)** * **Top Trace:** `IN` connects to `USB0_SSRX0_L-`. This node connects in parallel to `R4Y18` (pins 1, 2) and `L4Y7` (pins 1, 2). * `R4Y18` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * `L4Y7` text: `J16541-001`, `CHOKE`, `100MA`, `SM_A`, `90 30%`. * Output: `USB0_SSRX0_RDVR-` connects to `OUT`. * **Bottom Trace:** `IN` connects to `USB0_SSRX0_L+`. This node connects to `R4Y21` (pins 1, 2). * `R4Y21` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * Output: `USB0_SSRX0_RDVR+` connects to `OUT`. Text `H30143-001` is near the output. **Section 4: USB0_SSRX1 (Flow is Right to Left)** * **Top Trace:** `IN` connects to `USB0_SSRX1_L+`. This node connects in parallel to `R4Y8` (pins 1, 2) and `L4Y4` (pins 1, 2). * `R4Y8` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * `L4Y4` text: `J16541-001`, `CHOKE`, `100MA`, `SM_A`, `90 30%`. * Output: `USB0_SSRX1_RDVR+` connects to `OUT`. * **Bottom Trace:** `IN` connects to `USB0_SSRX1_L-`. This node connects to `R4Y7` (pins 1, 2). * `R4Y7` text: `EMPTY`, `0201`, `0.05W`, `0 0%`. * Output: `USB0_SSRX1_RDVR-` connects to `OUT`. Text `H30143-001` is near the output.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/f4748ac41d06f2564f765e69e4a6d87b5f5b41fcff55f8895ae67646b19478fa.jpg) ![USB0 SSRX1 L- USB0 SSRX1 L+ USB0 SSTX1 L- USB0 SSTX1 L+ 2 CR4Y13 2 CR4Y12 2 CR4Y8 2 CR4Y7 K74755-001 PESD3V321BSF 20KV ESD SM 20KV ESD SM 20KV ESD SM GND CAD NOTE: PLACE ESD CLOSE TO CONNECTOR USB0 SSRX0 L+ USB0 SSRX0 L- USB0 SSTX0 L+ USB0 SSTX0 L- 2 CR4Y6 2 CR4Y5 2 CR4Y14 2 CR4Y16 K74755-001 PESD3V321BSF 20KV ESD SM 20KV ESD SM +V3P3S R4V28 A93549-027 100K 5% 0.0625W EMPTY 0402 COM USB0 AUX- C4V10 A36096-112 0.1UF 10% 25V EMPTY 0402 C4V9 A36096-112 0.1UF 10% 25V EMPTY 0402 COM USB0 AUX+ USB0 AUX R+ USB0 AUX R+ BI COM R4V27 A93549-027 100K 5% 0.0625W EMPTY 0402 BI DESIGN NOTE: USBCO REDRIVER NOT SUPPORT DP MODE, AUX PATH DEFAULT DISCONNECTED R6K6 1 2 A93549-001 0402 EMPTY 0.0625W 0 0% L6K3 752402-015 90 25% 0.4A IND 1 4 USB2_P0_L- BI USB2_P0_TCP- USB2_P0_TCP+ 2 G SM 3 USB2_P0_L+ BI R6K5 1 2 A93549-001 0402 EMPTY 0 0% GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/610f7449b81baa6b2b1bda1f400ba06b828498a2b6b5052417739b5e6dc67dda.jpg) Figure 33: USB 3.2 Gen 2x2 Type-C (4 of 6): Port Port Mux / Redriver Coupling Capacitors ![The diagram displays four parallel horizontal signal paths, each connecting an 'IN' block to an 'OUT' block via a capacitor. **Top Path:** * **Block:** IN * **Connection:** USB0_SSTX0_L- * **Component Label:** C4Y6 * **Component Symbol:** Capacitor with pins labeled **1** and **2**. * **Text below pin 1:** 0201 * **Text below gap:** 10% 25V * **Text to right:** X5R * **Connection:** 220NF * **Connection:** USB0_SSTX0_C- * **Block:** OUT **Second Path:** * **Block:** IN * **Connection:** USB0_SSTX0_L+ * **Component Label:** C4Y5 * **Component Symbol:** Capacitor with pins labeled **1** and **2**. * **Text below pin 1:** 0201 * **Text below gap:** 10% 25V * **Text to right:** X5R * **Connection:** 220NF * **Connection:** USB0_SSTX0_C+ * **Block:** OUT **Third Path:** * **Block:** IN * **Connection:** USB0_SSTX1_L- * **Component Label:** C4Y9 * **Component Symbol:** Capacitor with pins labeled **1** and **2**. * **Text below pin 1:** 0201 * **Text below gap:** 10% 25V * **Text to right:** X5R * **Connection:** 220NF * **Connection:** USB0_SSTX1_C- * **Block:** OUT **Bottom Path:** * **Block:** IN * **Connection:** USB0_SSTX1_L+ * **Component Label:** C4Y10 * **Component Symbol:** Capacitor with pins labeled **1** and **2**. * **Text below pin 1:** 0201 * **Text below 0201:** J95198-001 * **Text below gap:** 10% 25V * **Text to right:** X5R * **Connection:** 220NF * **Connection:** USB0_SSTX1_C+ * **Block:** OUT](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/d9db6a53cd5601dd55f6f97806a9aaab55f8643b304274ffe6910e05839f04fe.jpg) RC SHORT PROTECTION ![C4Y17 J96611-001 330NF 10% 25V X5R 1 2 USB0_SSRX0_C- OUT USB0_SSRX0_L- 0201 C4Y19 J96611-001 330NF 10% 25V X5R 1 2 USB0_SSRX0_C+ OUT USB0_SSRX0_L+ 0201 C4Y7 J96611-001 330NF 10% 25V X5R 1 2 USB0_SSRX1_C- OUT USB0_SSRX1_L- 0201 C4Y8 J96611-001 330NF 10% 25V X5R 1 2 USB0_SSRX1_C+ OUT USB0_SSRX1_L+ 0201 R4Y17 R4Y22 R4Y14 R4Y13 1 220K 1 220K 1 220K 1 220K 1 RES RES RES RES RES 0201 0201 0201 0201 0201 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/455b5ab8222e3dcb0ae2bca96a4fac28d694a7f34b34beefab97e545925e3b67.jpg) Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller ![Electrical schematic diagram of an ESROM and USB controller with component labels, pin connections, and a PCB design table.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/256df33528525204292ab01af0bb6e0213b9739de8df9680cba28efe1fd614b8.jpg) Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection ![+V_TCP_C0 VBUS_CONN CR5Y2 J58608-001 NSR20F30NXT5G 2A DIO SM A GND DESIGN NOTE: SUPPORT USB MODE ONLY J5K4 SCON USB3_C_SHLD_24P_6M GND_A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 GND_B2 TX1_DP TX1_DN VBUS_A1 CC1 D_A_DP D_A_DN SBU1 VBUS_A2 RX2_DN RX2_DP GND_A2 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 C5Y16 0.1UF 10% 10V X5R 0402 C5Y17 0.1UF 10% 10V X5R 0402 C5Y13 0.1UF 10% 10V X5R 0402 C5Y14 A36096-043 0.1UF 10% 10V X5R 0402 IN IN +VTCPD0_CC1_CONN USB0_SSTX0_C+ USB0_SSTX0_C- USB2_P0_L+ USB2_P0_L- TCP0_SBU1_CONN USB0_SSRX1_C- USB0_SSRX1_C+ OUT OUT GND J40583-001](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/a9e755c857842b79e6be57fe733d052cab8412cea52f3df5184eb71c92cc7fa3.jpg) ![+V3P3_PD1_LDO R4V13 A93549-027 1 100K 5% 0.0625W RES 0402 +V3P3_PD1_LDO +VBIAS_TCP0 C4V20 602433-020 0.1UF 10% 50V X7R 0603 C4V12 A36096-088 2.2UF 20% 6.3V X5R 0402 +VTCPC0 CC2 CONN R4V17 1 2 TCP0_RPD_G2 RES 0% TCP0_RPD_G1 RES 0% TPD6S300 U4V1 IC VBIAS 3 VPWR 10 C_SBU1 1 TCP0_SBU1 CONN BI C_SBU2 2 TCP0_SBU2 CONN BI C_CC1 4 +VTCPC0 CC1 CONN BI C_CC2 5 +VTCPC0 CC2 CONN BI CC1 12 +VTCPC0 CC1 BI CC2 11 +VTCPC0 CC2 BI USB0_AUX_R+ USB0_AUX_R- USB0_AUX_R- J52027-001 GND_1 8 GND_2 13 GND_3 18 GND_TPD 21 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/1972020bbc1daab4c7f8fc5fb7d264967403b02c5ed733751f23e90eee930d5c.jpg) ![+VTCP0 CC1 CONN C4V18 1 220PF 10% 50V X7R 0402 GND GND +VTCP0 CC2 CONN 1 220PF 10% 50V X7R 0402 A36096-050 GND TCP0 SBU1 CONN 1M 1% 0.0625W EMPTY 0402 TCP0 SBU2 CONN 1M 1% 0.0625W EMPTY 0402 A93548-209 GND R4V24 R4V25 1M 1% 0.0625W EMPTY 0402](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/8960f6562735926266c8f7fb8f177447965a64005d83c6df193fec4452110ee4.jpg) ![USB2 P0 L+ BI SM DIO 3.5A ESD131-B1-W201 J76907-001 CR6K3 GND USB2 P0 L- BI SM DIO 3.5A ESD131-B1-W201 J76907-001 CR6K4](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/d97433dc31a9d25e3c6344235ccfb8248829c0bffb213863f3016a26707ee243.jpg) # 3.7.11. USB4 # USB4 – COM-HPC Client and Server An example COM-HPC USB4 implementation, that supports all USB modes up to USB4 Gen 3x2 and the USB Type-C Alternate Modes is shown in Figure 36 below. Of course this support requires that the COM-HPC Module used supports these modes as well. See Table 10 above for a summary of all the USB modes. The Intel JHL9040R “Hayden Bridge” USB4 retimer is used. Intel considers further details to be NDA protected material. Contact Intel for further details on the Intel part and implementation details. This example includes a USB Power Delivery controller, Texas Instruments TPS65994. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7. above more some discussion on Power Delivery controllers. Additionally, a Texas Instruments TPD6S300A “Port Protector” is used to protect the USB Type-C port from adverse conditions. # USB4 – COM-HPC Mini An example COM-HPC USB4 implementation for the COM-HPC Mini Module, that supports all USB modes up to USB4 Gen 3x2 and the USB Type-C Alternate Modes is shown in Figure 37 below. Of course this support requires that the COM-HPC Module used supports these modes as well. See Table 10 above for a summary of all the USB modes. The Intel JHL9040R “Hayden Bridge” USB4 retimer is used. Intel considers further details to be NDA protected material. Contact Intel for further details on the Intel part and implementation details. This example includes a USB Power Delivery controller, Texas Instruments TPS65994. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7. above more some discussion on Power Delivery controllers. Additionally, a Texas Instruments TPD6S300A “Port Protector” is used to protect the USB Type-C port from adverse conditions. Figure 36: USB4 on COM-HPC Client ![The diagram illustrates a USB4 hub interface connecting a host connector to USB4 ports via controllers. **Labeled Blocks:** * **COM-HPC Client Connector** (Left) * **JHL9040R** (Top Center) * **JHL9040R** (Bottom Center) * **8Mbit Flash** (Top Right) * **TPD6S300A (VBUS Short Protection)** (Middle Right, Top) * **TPD6S300A (VBUS Short Protection)** (Bottom Right, Bottom) * **USB4#0** (Top Right Connector Icon) * **USB4#1** (Bottom Right Connector Icon) * **I2C EEPROM** (Middle Left) * **TPS65994 (Dual Port Controller)** (Center) **Connections:** * **COM-HPC Client Connector**: * Outputs `USB1+/−` to `USB4#0`. * Outputs `USB0+/−` to `USB4#1`. * Outputs `USB_RT_ENA` to `RESET_N` and `FORCE_PWR` on both `JHL9040R` blocks. * Outputs `USB SuperSpeed` signals (`USB0_SSTX(0:1)+/-`, `USB0_SSRX(0:1)+/-`, `USB0_LSTX/RX`, `USB0_AUX+/−`) to `PortA` of the top `JHL9040R`. * Outputs `SML0_DAT`, `SML0_CLK` (`SML0_DAT/CLK`) to `I2C EEPROM` and `SMBUS` inputs on both `JHL9040R` blocks. * Outputs `USB_PD_I2C_DAT`, `USB_PD_I2C_CLK`, `USB_PD_ALERT#` (`USB_PD_I2C_DAT/CLK/ALERT#`) to `I2C EEPROM`, `I2C` input on the bottom `JHL9040R`, and `I2C3` input on `TPS65994`. * Outputs `SML1_DAT`, `SML1_CLK`, `PMCALERT#` (`SML1_DAT/CLK/PMCALERT#`) to `I2C1` input on `TPS65994`. * Outputs `USB1_AUX+/−`, `USB1_LSTX/RX`, `USB SuperSpeed` (`USB1_SSTX(0:1)+/-`, `USB1_SSRX(0:1)+/-`) to `PortA` of the bottom `JHL9040R`. * **Top JHL9040R**: * `PortB` connects via `SPI` and `RT01_SPI` to `8Mbit Flash`. * `PortB` connects via `USB0_SSTX+/-, RX+/- (2 pairs)` to `USB4#0`. * `PortB` connects via `USB0_SBU` to `TPD6S300A (VBUS Short Protection)` (Top). * `PortB` connects via `RT0_RST#` to `I2C3` on `TPS65994`. * `PortA` connects to `SML0_DAT/CLK` via `SMBUS`. * `PortA` connects to `I2C_PD-RT` via `I2C`. * **Bottom JHL9040R**: * `PortB` connects via `SPI` and `RT01_SPI` to `8Mbit Flash`. * `PortB` connects via `USB1_SSTX+/-, RX+/- (2 pairs)` to `USB4#1`. * `PortB` connects via `USB1_SBU` to `TPD6S300A (VBUS Short Protection)` (Bottom). * `RESET_N` receives `RT1_RST#` from `I2C2` on `TPS65994`. * `PortA` connects to `SML0_DAT/CLK` via `SMBUS`. * `PortA` connects to `USB_PD_I2C_DAT/CLK/ALERT#` via `I2C`. * **TPS65994 (Dual Port Controller)**: * Outputs `USB0_CCx` and `3.3v_LDO` to `TPD6S300A` (Top). * Outputs `USB1_CCx` to `TPD6S300A` (Bottom). * Outputs `USB0_VBUS` to `USB4#0`. * Outputs `USB1_VBUS` to `USB4#1`. * **TPD6S300A (VBUS Short Protection) (Top)**: * Receives `USB0_SBU` from Top `JHL9040R`. * Receives `USB0_C_SBU` from `USB4#0`. * Outputs `USB0_C_CCx` to `USB4#0`. * **TPD6S300A (VBUS Short Protection) (Bottom)**: * Receives `USB1_SBU` from Bottom `JHL9040R`. * Receives `USB1_C_SBU` from `USB4#1`. * Outputs `USB1_C_CCx` to `USB4#1`.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/064d65e002e6a477a8d393660cc56b922fd0a2e209b63f9a87f2875c2274351b.jpg) Figure 37: USB4 on COM-HPC MiniUSB4 Mini Carrie ![Based on the provided block diagram, here are the labeled blocks and their connections: **Labeled Blocks:** 1. **COM-HPC Mini Connector** (Left) 2. **JHL9040R** (Top Middle) 3. **8Mbit Flash** (Top Right) 4. **TPD6S300A (VBUS Short Protection)** (Top Right, below Flash) 5. **I2C EEPROM** (Middle Left) 6. **TPS65994 (Dual Port Controller)** (Center) 7. **JHL9040R** (Bottom Middle) 8. **TPD6S300A (VBUS Short Protection)** (Bottom Right) 9. **USB4#0** (Top Right Connector) 10. **USB4#1** (Bottom Right Connector) **Connections:** * **From COM-HPC Mini Connector:** * `USB_RT_ENA` connects to `RESET_N` on both JHL9040R blocks. * `USB1+/-` and `USB0+/-` connect directly to **USB4#0**. * `USB SuperSpeed SS(2:3)_TX+/-` connects to `USB4_0_SSTX(0:1)+/- / USB4_0_SSRX(0:1)+/-` on the top JHL9040R. * `USB0_LSRX/DDI1_DDC_AUX_SEL` connects to `USB0_LSRX / USB0_LSTX` on the top JHL9040R. * `USB0_LSTX/DDI1_HPD` connects to `USB0_AUX- / USB0_AUX+` on the top JHL9040R. * `SS23_SDA_AUX` and `SS23_SCL_AUX+` connect to `SML0_DAT/CLK` on the top JHL9040R. * `USB_PD_I2C_DAT`, `USB_PD_I2C_CLK`, and `USB_PD_ALERT#` connect to `USB_PD_I2C_DAT/CLK/ALERT#` on the TPS65994. * `SML1_DAT`, `SML1_CLK`, and `PMCALERT#` connect to `SML1_DAT/CLK/PMCALERT#` on the TPS65994. * `USB1_AUX-` and `USB1_AUX+` connect to `USB1_AUX- / USB1_AUX+` on the bottom JHL9040R. * `USB1_LSTX/RX` connects to `USB1_LSTX / USB1_LSRX` and `FORCE_PWR` on the bottom JHL9040R. * `USB SuperSpeed SS(4:5)_TX+/-` connects to `USB4_1_SSTX(0:1)+/- / USB4_1_SSRX(0:1)+/-` on the bottom JHL9040R. * **Between Central Blocks:** * Top JHL9040R `SPI` connects to `RT01_SPI`, which goes to **8Mbit Flash** and `SPI` on the bottom JHL9040R. * Top JHL9040R `I2C` connects to `I2C3_PD-RT`, which goes to `I2C3` on the TPS65994. * Top JHL9040R `SMBUS` connects to `SML0_DAT/CLK` (blue arrow pointing left to the connector). * **I2C EEPROM** connects to the `SML0_DAT/CLK` line (green line). * TPS65994 `3.3V_LDO` (red line) connects to both TPD6S300A blocks. * TPS65994 `USB0_CCx` (purple line) connects to TPD6S300A (Top) `USB0_C_CCx` and **USB4#0** `USB0_VBUS`. * TPS65994 `USB1_CCx` (purple line) connects to TPD6S300A (Bottom) `USB1_C_CCx` and **USB4#1** `USB1_VBUS`. * **To USB4 Connectors:** * Top JHL9040R `PortB` outputs `USB0_SBU` to the top TPD6S300A and `USB0_SSTX+/-, RX+/-` to **USB4#0**. * Bottom JHL9040R `PortB` outputs `USB1_SBU` to the bottom TPD6S300A and `USB1_SSTX+/-, RX+/-` to **USB4#1**. * Top TPD6S300A outputs `USB0_C_SBU`, `USB0_C_CCx`, and `USB0_VBUS` to **USB4#0**. * Bottom TPD6S300A outputs `USB1_C_SBU`, `USB1_C_CCx`, and `USB1_VBUS` to **USB4#1**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/2e8552c28e98842802ec4041007ed2cd02dcf768cc898f67de4cc727db819d83.jpg) # 3.8. Boot SPI on Carrier The COM-HPC Base Specification V1.0 describes various boot SPI options at some length in Sections 4.3.9 and 4.3.10. The layout topology for the BOOT\_SPI bus is given in Section 6.11.1 of the COM-HPC Base Specification V1.0. Please refer to those Base document sections in addition to the materials presented here to get a bigger picture. Contemporary x86 chipsets typically have a SPI boot bus with three chip-selects: two for up to two SPI Flash devices to hold various pieces of boot firmware including the BIOS, and possibly a backup BIOS, and a 3rd chip-select dedicated to an on-Module TPM. device. The two chip-set chip-selects for boot SPI flash devices can be routed to either two on-Module SPI Flash devices, or to one on-Module SPI Flash and to one Carrier based SPI Flash device. The various possible permutations are selected by a set of three Module strap pins named BSEL0, 1, and 2. See COM-HPC Base Specification V1.0 Section 4.3.10 Table 10 for the decoding of the BSEL[0:2] pins. It is possible to have the entire boot firmware image reside in a Carrier based SPI Flash device. It is also possible of course to have the entire boot image on the module, and it is possible to split the boot image to have some parts on the Module and some on the Carrier. Some Module designs implement multiplexers to allow even more options. A typical Carrier Boot SPI Flash implementation is shown in Figure 38 below. Some points about this Figure are given on the following page. Figure 38: Boot SPI on Carrier (Example 1) ![Here is an accurate and concise description of the flowchart/block diagram: **Blocks and Components:** * **U1**: A rectangular block labeled **U1** representing a **Winbond** memory chip. Text below lists compatible parts: **W25Q64JV (64 Mbit)**, **W25Q128JV (128 Mbit)**, **W25Q256JV (256 Mbit)**. * **Pins**: 8 (**VCC**), 7 (**HOLD# / IO3**), 3 (**WP# / IO2**), 2 (**DO / IO1**), 5 (**DI / IO0**), 6 (**CLK**), 1 (**CS#**), 4 (**GND**). * **SPI MODE**: A dashed box on the far left containing a **COM** connector. * **QSPI MODE**: A dashed box next to SPI MODE containing a **COM** connector. * **Jumper Block**: A block at the bottom labeled **Jumper Block** with inputs **BSEL0**, **BSEL1**, and **BSEL2** (each labeled **COM**). * **Resistors**: **R1** (**10K**), **R2** (**10K**), **R3** (**15 ohm**), **R4** (**15 ohm**), **R5** (**15 ohm**), **R6** (**15 ohm**), **R7** (**15 ohm**). * **Capacitor**: **C1** (**100 nF**). **Connections:** * **Power Network**: The net **VCC_BOOT_SPI** connects to U1 Pin 8 (**VCC**), the top of **R1**, the top of **R2**, and the top of **C1**. The bottom of **C1** connects to ground. * **Pull-up Resistors**: The bottoms of **R1** and **R2** are connected together. This junction connects to the **BOOT_SPI_IO2** signal line. * **Signal Lines**: * **BOOT_SPI_IO3** connects through **R3** to U1 Pin 7 (**HOLD# / IO3**). * **BOOT_SPI_IO2** connects through **R4** to U1 Pin 3 (**WP# / IO2**). * **BOOT_SPI_IO1** connects through **R5** to U1 Pin 2 (**DO / IO1**). * **BOOT_SPI_IO0** connects through **R6** to U1 Pin 5 (**DI / IO0**). * **BOOT_SPI_CLK** connects through **R7** to U1 Pin 6 (**CLK**). * **BOOT_SPI_CS#** connects directly to U1 Pin 1 (**CS#**). * **Ground**: U1 Pin 4 (**GND**) and the bottom of the **Jumper Block** connect to ground.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/158cc5a78e042be4a5b77137096db86a295fb67d53a1650d26f8a4aa0b14529a.jpg) The information shown here applies to all COM-HPC versions. The COM-HPC Rev. 1.20 Specification document allows the VCC\_BOOT\_SPI power net to be either 3.3V or 1.8V. COM-HPC Mini Module vendors are likely to choose 1.8V as the SPI I/O, but this should be verified with the Module vendor. The Winbond part numbers in the Figure 38 above are 3.3V parts, not 1.8V capable. It is also wise to ask the Module vendor what specific Carrier boot SPI devices are supported – for all COM-HPC variants (Client, Server, Mini). Some of the internal register details in these boot SPI devices vary and the Module BIOS has to be aware of the device it is dealing with. # Notes on Figure 38 above: The Carrier SPI Flash device power is provided by a special COM-HPC Module pin named VCC\_BOOT\_SPI. This should be the only power source for the Carrier SPI Flash device and any related pull-ups and bypass capacitors., as shown in the Figure 38. The VCC\_BOOT\_SPI voltage level may be 3.3V or 1.8V. 。 This is Module vendor specific. ◦ It is not common or expected that a given SPI Flash device will be able to operate at both 3.3V and 1.8V. A few devices might be able to do so. ◦ The SPI Flash devices listed in the Figure above are 3.3V devices, and are not rated at 1.8V. • The VCC\_BOOT\_SPI power net may be in the S5 (suspend) or S0 (on) power domains. ◦ This is Module vendor specific. QSPI devices from Microchip / SST are shown in the Figure above. Windbond is a very popular selection for QSPI devices: W25Q16JV is a sample Winbond base part number for their 16 Mbit part. There are 16, 32, 64 and 128 Mbit offerings from Winbond. • There are many packaging options available from the QSPI vendors ◦ There are package size differences between vendors even for package names that at first glance sound the same (like SOIC8 etc) … so care must be taken. ◦ The Winbond SOIC8 packages are smaller than the Microchip devices. There are register differences between various SPI Flash vendor offerings. The Module firmware / BIOS may not be compatible with some devices. Check with the Module vendor. ◦ Carrier designers should use parts from the same SPI Flash vendor(s) and family as the Module vendor uses. ◦ There may be reasons to use different package types on the Carrier: ▪ The Module vendor likely uses the smallest possible package size. ▪ Carrier designs may want to implement a removable (socketed) SPI Flash device. Carrier designers may elect to use a SPI package that is easier to rework. Contemporary SPI Flash devices may operate in one of several modes: 。 Traditional SPI mode (noted at left side of Figure 38 above). ▪ This mode has one data line into the SPI device and one out. 。 QSPI (“Quad SPI”) mode: ▪ This mode has 4 bidirectional data lines, offering a higher net data bandwidth. The SPI Flash devices typically power up in the traditional SPI Flash mode and must be put into the QSPI mode by software. The HOLD# and WP# inputs of a traditional SPI device are disabled by pull-ups R1 and R2 in the Figure above. For QSPI mode operation, the PCB trace stubs from the QSPI data lines to these pull-ups should be minimized. ◦ If the SPI device is to immediately be put into QSPI mode, it is likely possible that R1 and R2 can be omitted. There are specific routing rules for the BOOT\_SPI\_xx nets. See Section 4.4. of this document and Section 6.11.1 of the COM-HPC Base Specification V1.0. # Removable / Reprogrammable SPI Flash Devices In some situations it is desirable or even required to have a socketed or removable Boot SPI Flash device. This is the case, for example, in some casino gaming jurisdictions, to allow the BIOS device to be removed and inspected by a regulatory technician. A socketed or removable BIOS can also be useful in product development situations, allowing easy replacement of a corrupted BIOS device. Some possible socket solutions are listed in Table 15 below: Table 15: Boot SPI Socket Suggestions
VendorVendor P/NNotes
EnplasEnplas offers a variety of sockets that accept several 8 and 16 pin SOIC sizes.Winbond and other vendors offer some of their SPI Flash devices in a 16 pin SOIC along with a variety of smaller form factors. It may be easier to find a socket for an SOIC16 device.The Carrier Boot SPI Flash device should be from the same flash vendor and family as the part used on the Module. The package details may be different.
LotesACA-SPI-004-KACA-SPI-006-T01Should be suitable for the Microchip SST26VFxxxB SOIJ8 parts.Suitable for Macronix MX77U25650F (32 MB 1.8V QSPI) or MX77L25650F (32 MB 3.3V QSPI) 16 pin 300 mil SOIC parts shown in Figure 39 below.Other Lotes socket parts may be relevant here.
GenericWinbond offers some of their Flash devices in 300 mil DIP format, for which there are many generic sockets.
Some gaming firms design their own removable BIOS assembles. These are sometimes referred to as “cartridges”. This allows the use of any SPI Flash device desired, and it can ensure easy removal and replacement of the device.. Some Carrier designers add features that multiplex signals and power to the Carrier SPI Flash device allowing the device to be used as usual in the system or cut the device off from the system and allow the device to be reprogrammed by a cable to an external piece of programming equipment. An example of such implementations (SPI device in a socket and a multiplexer to allow the SPI flash device to be programmed by an external programming tool) is shown in Figure 39 below. The programming tool in this case is from a company called Dediprog. Figure 39: Boot SPI on Carrier – Socketed Flash and Multiplexer to External Programmer ![The image displays a schematic diagram containing electronic components, connectors, and associated text labels. **Top Left:** `+V5_SBY` `R5B17` `A93549-023` `10K` `5%` `0.0625W` `RES` `0402` `+VCC_BOOT_SPI` `+VCC_BOOT_SPI_GATE` `C5B20` `A36096-112` `0.1UF` `10%` `25V` `X7R` `0402` `GND` `Q6B1` `MFET` `D45305-001` `FDN339AN` `SOT23` **Top Middle:** `+V1P8_A` `+V3P3_A` `+VCC_SPI` `R4R7` `1K` `5%` `EMPTY` `0402` `R4R8` `1K` `5%` `EMPTY` `0402` `R4R11` `10K` `5%` `EMPTY` `0402` `SPI MUX EN#` `R4R5` `10K` `5%` `EMPTY` `0402` `R4R12` `10K` `5%` `RES` `0402` `GND` **Top Right (Connector J6B1):** `DESIGN NOTE:` `TTK3 + DEDIPROG PROG CONN` `J6B1` `SCON` `HDR_2X25_K29_K30_K31 (BUB)` `1` `USB2_P4 TTK L+` `OUT` `3` `USB2_P4 TTK L-` `IN` `5` `TTK PWR BTN#` `IN` `7` `NC EC UART RTS#` `OUT` `9` `NC EC UART_RX` `OUT` `11` `TTK UART0_RX` `IN` `13` `TTK UART0_TX` `IN` `15` `TTK UART0 RTS#` `IN` `17` `PWRGOOD TTK` `IN` `19` `TTK SUS S3#` `OUT` `21` `TTK SUS S4#` `IN` `23` `TTK SUS S5#` `BI` `25` `TTK SMB CLK` `IN` `33` `SPI TPM GPIO_RST#` `IN` `35` `SPI MUX CLK TTK` `BI` `37` `SPI MUX IO3 TTK` `BI` `39` `SPI MUX IO1 TTK` `BI` `47` `TTK PLT DET` `IN` `49` `+VCC_SPI TTK R` `GND` `2` `NC EC UART TX` `IN` `4` `NC EC UART RX` `IN` `6` `NC EC UART TX` `IN` `8` `NC EC UART RX` `IN` `10` `NC EC UART_TX` `IN` `12` `V3P3 IO TTK` `IN` `14` `PORT80 SMB_CLK` `IN` `16` `PORT80 SMB_DATA` `IN` `18` `NC TTK SUS S0#` `IN` `20` `NC TTK I2C0 DAT` `IN` `22` `NC TTK I2C0 CLK` `IN` `24` `NC TTK I2C1 DAT` `IN` `26` `NC TTK I2C1 CLK` `IN` `28` `NC TTK CATERA#` `IN` `30` `SPI MUX CS0 TTK#` `IN` `32` `NC TTK CS1 TTK#` `IN` `34` `SPI MUX IO2 TTK` `BI` `36` `SPI MUX IO2 TTK` `BI` `38` `SPI MUX IO1 TTK` `BI` `40` `SPI MUX IO1 TTK` `BI` `42` `TTK PLT DET` `IN` `44` `+VCC_SPI TTK R` `GND` `46` `GND` `48` `GND` `50` `GND` `K18833-001` **Left Side (Resistors):** `CAD NOTE:` `DO NOT OVERLAP PAD. PLACE 2 RES BRANCH CLOSE TOGETHER & LOW STUB` `COM` `BOOT SPI CS#` `R7E7` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI CS0 R#` `OUT` `R3R20` `1` `2` `0402` `RES 0 0%` `2` `SPI CS0 TTK#` `OUT` `COM` `BOOT SPI I00` `R7E1` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI I00 R` `BI` `R3R27` `1` `2` `0402` `RES 0 0%` `2` `SPI I00 TTK` `BI` `COM` `BOOT SPI I01` `R7E8` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI I01 R` `BI` `R3R31` `1` `2` `0402` `RES 0 0%` `2` `SPI I01 TTK` `BI` `COM` `BOOT SPI I02` `R7E2` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI I02 R` `BI` `R4R9` `1` `2` `0402` `RES 0 0%` `2` `SPI I02 TTK` `BI` `COM` `BOOT SPI I03` `R7E6` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI I03 R` `BI` `R4R10` `1` `2` `0402` `RES 0 0%` `2` `SPI I03 TTK` `BI` `COM` `BOOT SPI CLK` `R7E9` `1` `2` `0402LF` `CHIP 16.90 1%` `2` `SPI CLK R` `OUT` `R3R26` `1` `2` `0402` `RES 0 0%` `2` `SPI CLK TTK` `OUT` **Bottom Left (Capacitors/Resistors/IC):** `+VCC_SPI` `C3R2` `1` `2` `0.1UF` `10%` `25V` `X7R` `0402` `GND` `C3R3` `1` `2` `A36096-112` `0.1UF` `10%` `25V` `X7R` `0402` `R7E5` `1` `2` `10K` `5%` `EMPTY` `0402` `R7F3` `1` `2` `10K` `5%` `EMPTY` `0402` `DESIGN NOTE:` `BOM: SPI CHIP MACRONIX` `K9I180-001 MX77L25650PMI42 (3.3V SOP16)` `M35512-001 MX77U25650PMI42 (1.8V SOP16)` `XU7E1` `SKT` `SPI_FLASH_16P` `2` `VCC` `NC` `4` `13` `WP, NISO2` `2` `8` `SO/SIO1` `DNU` `15` `SI/SIO0` `11` `CS_N` `RESET_N` `16` `SCLK` `DNU` `12` `10` `GND` `D91187-001` **Center (IC EU4R1):** `+VCC_SPI` `C4R1` `A36096-112` `0.1UF` `10%` `25V` `X7R` `0402` `GND` `CAD NOTE:` `PLACE IC NEAR SPI SOCKET` `EU4R1` `IC` `T93A27518E` `5` `VCC` `NC1` `23` `SPI MUX CS0 TTK#` `24` `NC` `NC2` `22` `SPI MUX CLK TTK` `21` `SPI CS0 TTK#` `NC3` `20` `SPI MUX IO0 TTK` `NC4` `18` `SPI I00 TTK` `16` `SPI I01 TTK` `19` `SPI MUX IO3 TTK` `NO1` `8` `NC01` `NO2` `10` `NC02` `NO3` `12` `NC03` `NO4` `14` `NC04` `NO5` `15` `NC05` `NO6` `13` `NC06` `17` `EN_IN` `21` `IN1` `25` `GND` `2` `IN2` `2` `SPI MUX IN` `25` `THPAD` `G75680-001` **Bottom Right (MOSFETs/Resistors):** `CAD NOTE:` `PLACE SPI SOCKET NEAR HPC CONN` `COM` `RSMST_OUT#` `R4R4` `1` `2` `RES` `0` `0402` `R4R2` `1` `2` `A93549-015` `10K` `0.0625W` `RES` `0402` `GND` `Q4R1` `C81974-001` `BSN138LT1G` `MFET` `SOT23` `1` `2` `RSMST_OUT R_FET` `Q4R2` `C81974-001` `BSN138LT1G` `MFET` `SOT23` `1` `2` `RSMST_OUT R_FET2` `R4R1` `1` `2` `A93549-023` `10K` `0.0625W` `RES` `0402` `+VCC_SPI` `R4R6` `1` `2` `A93549-023` `10K` `0.0625W` `RES` `0402` `R4R3` `1` `2` `0402` `RES` `0` `SPI MUX EN#` `OUT` **Right Side (Resistors):** `COM` `FLT_RST#` `R6B3` `1` `2` `RES` `0402` `TTK FLT_RST#` `OUT` `R6B25` `1` `2` `RES` `0402` `TTK RST_BTN` `OUT` `OUT` `PWR_BTN#` `R6B16` `1` `2` `RES` `0402` `PWR_BTN#` `IN` `R6B14` `1` `2` `RES` `0402` `TTK UART0_TX` `OUT` `R6B15` `1` `2` `RES` `0402` `TTK UART0_RX` `OUT` `R6B13` `1` `2` `RES` `0402` `TTK UART0_CTS#` `IN` `COM` `SUS S3#` `R6B10` `1` `2` `RES` `0402` `TTK SUS S3#` `OUT` `COM` `SUS S5#` `R6B20` `1` `2` `RES` `0402` `TTK SUS S5#` `OUT` `COM` `R6B9` `1` `2` `RES` `0402` `TTK SUS S4#` `IN` `COM` `RTC_RST_N FROM FUSA CONN` `R6B11` `1` `2` `RES` `0402` `TTK PLT_DET` `IN` `R6B12` `1` `2` `RES` `0402` `TTK CATERA#` `OUT` `COM` `GPIO9 = LVL_SFTED 3.3V CATERA# FROM MODULE` `COM` `SMB CLK` `R6B5` `1` `2` `RES` `0402` `TTK SMB_CLK` `OUT` `COM` `SMB_DATA` `R6B6` `1` `2` `RES` `0402` `TTK SMB_DATA` `OUT` `COM` `I2C0 CLK` `R6B21` `1` `2` `RES` `0402` `TTK I2C0_CLK` `BI` `COM` `I2C0 DAT` `R6B22` `1` `2` `RES` `0402` `TTK I2C0_DAT` `BI` `COM` `USB PD I2C CLK` `R6B23` `1` `2` `RES` `0402` `PORT80 SMB_CLK` `OUT` `COM` `USB PD I2C DAT` `R6B23` `1` `2` `RES` `0402` `PORT80 SMB_DAT` `BI` **Middle Right (Capacitors/Resistors):** `+V3P3_A` `R6B24` `1` `2` `10K` `0402` `RES` `A93549-023` `2` `+VCC_SPI` `C6B3` `A36096-112` `0.1UF` `10%` `25V` `X7R` `0402` `GND` `+VCC_SPI` `C6B2` `A36096-112` `0.1UF` `10%` `25V` `X7R` `0402` `GND` `R6B17` `1` `2` `RES` `0402` `10K` `0402` `GND` `R6B18` `1` `2` `RES` `0402` `0402` `GND` **Middle (Resistors):** `+VCC_SPI` `R6B1` `A93549-023` `10K` `0.0625W` `RES` `0402` `+VCC_SPI` `R6B2` `A93549-023` `10K` `0.0625W` `RES` `0402` **Middle (Resistor):** `+V3P3_A` `R6B8` `A93549-023` `10K` `0.0625W` `RES` `0402` `EMPTY` `0402` `TTK PCH_RTC_RST` **Function Table:** `Table 2. Function Table` `EN` `IN1` `IN2` `NC1/23 TO COM1/23, COM1/23 TO NC1/23` `NC4/5/6 TO COM4/5/6, COM4/5/6 TO NC4/5/6` `NO1/3 TO COM1/23, COM1/23 TO NO1/3` `NO4/5/6 TO COM4/5/6, COM4/5/6 TO NO4/5/6` `H` `X` `X` `OFF` `ON` `OFF` `OFF` `OFF` `OFF` `L` `L` `L` `ON` `OFF` `ON` `OFF` `ON` `OFF` `L` `H` `L` `ON` `OFF` `OFF` `ON` `ON` `OFF` `L` `L` `H` `ON` `OFF` `OFF` `ON` `ON` `OFF` `L` `H` `H` `OFF` `ON` `ON` `OFF` `ON` `ON`](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/8fec7714120dd022160adc2d81e7bd171aad3edca9fbd0c3ed9db7d791f3d4da.jpg) # 3.9. eSPI The COM-HPC Client and Server pinouts support an eSPI (Enhanced Serial Peripheral Interface) port. There may be up to two eSPI devices on the Module and up to two eSPI devices on the Carrier. The eSPI interface is promoted as the successor to the LPC (Low Pin Count) general x86 I/O interface. The eSPI data and clock signals run at about 50 MHz. The COM-HPC Base Specification Section 6.11.2 recommends a “balanced tree” routing topology. This is also referenced in Section 4.4. of this document. Figure 40 below illustrates a “generic” eSPI implementation example for one branch of the tree, that might apply to a Carrier Super I/O, FPGA, CPLD, eSPI to LPC bridge, or other eSPI peripheral. The COM-HPC eSPI interface is a 1.8V level interface that operates in all power states, S5 through S0. The Figure 40 shows some additional signals that are 3.3V level signals, also active in all power domains, that may be needed for some eSPI peripheral implementations. Some Carrier situations may require legacy Intel LPC (Low Pin Count) compatibility. The Microchip ECE1200 is a suitable eSPI to LPC bridge device that is referenced in some Intel literature for this task. Microchip is also a popular vendor for Carrier based management micro-controllers with an eSPI interface. Figure 40: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device ![Based on the provided schematic, here is an accurate and concise description of the flowchart/block diagram: **Main Component** * **U1:** A rectangular block labeled 'U1' representing a 'Super I/O FPGA / CPLD eSPI to LPC Bridge eSPI Peripheral'. * **Power Pins:** `VCC_1V8_S5` and `VCC_3V3_S5` are at the top. * **Ground Pin:** `GND` is at the bottom. **Power Supply Connections** * **+1.8V_A:** Connects to `VCC_1V8_S5` and a capacitor `C1` (100 nF) to ground. * **+3.3V_A:** Connects to `VCC_3V3_S5` and a capacitor `C1` (100 nF) to ground. **Signal Connections (Left to Right)** The signals originate from the left (labeled with 'COM' in a diamond) and connect to pins on U1. **1. 1.8V S5 Power Domain Signals (Top Section)** * **Annotation:** '1.8V S5 Power Domain Signals to / from COM-HPC' points to this group. * **Resistors:** These signals pass through a block labeled 'Series Damping Resistors' containing five 15-ohm resistors (R1–R5). * `eSPI_IO3` → `R1` (15 ohm) → `eSPI_IO3` * `eSPI_IO2` → `R2` (15 ohm) → `eSPI_IO2` * `eSPI_IO1` → `R3` (15 ohm) → `eSPI_IO1` * `eSPI_IO0` → `R4` (15 ohm) → `eSPI_IO0` * `eSPI_CLK` → `R5` (15 ohm) → `eSPI_CLK` **2. Option Resistors (Middle Section)** * **Annotation:** 'Option Resistors' points to the block containing R6–R9. * **Chip Select (CS):** * `eSPI_CS0#` → `R6` (0 ohm) → `eSPI_CS#` * `eSPI_CS1#` → `R7` (Open) → (Unconnected) * **Alert:** * `eSPI_ALERT0#` → `R8` (0 ohm) → `eSPI_ALERT#` * `eSPI_ALERT1#` → `R9` (Open) → (Unconnected) **3. 3.3V S5 Power Domain Signals (Bottom Section)** * **Annotation:** '3.3V S5 Power Domain signals from COM-HPC Client' points to this group. * **Direct Connections:** These signals connect directly to U1 without series resistors. * `eSPI_RST#` → `eSPI_RESET#` * `PLTRST#` → `RESET#` * `RSMRST_OUT#` → `RESUME_RESET_IN#` * `SUS_CLK` → `SUS_CLK` **Additional Notes** * Text at the bottom left states: 'For COM-HPC Mini designs, these need to be 1.8V S5 Power Domain signals ... Level translation components may be necessary depending on the particular eSPI device'.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/f8ef8928f4f3a445afea2c042b49f010193a326ece1e246dc683d5e1f62be35d.jpg) # 3.10. DisplayPort Over DDI Figure 41: DisplayPort Over DDI ![Electrical schematic diagram with component labels, pin connections, and wiring specifications for a power supply or control circuit.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/dca7d6a259ee8b4a77f1f16a9e50f15d58502fa08e571ce0f12e38d6ed7435f7.jpg) # Notes on DisplayPort over DDI: COM-HPC supports three DDI channels, designated DDI0, DDI1 and DDI2. The Figure 41 above uses DDI0 as an example. DisplayPort data pairs are capacitively coupled, near the DisplayPort cable connector, as seen in the Figure 41 above (C310 through C317). ◦ This is in contrast to HDMI data pairs which are typically DC coupled. 。 However, some HDMI buffers / level shifters / redrivers use AC coupling at the buffer inputs and DC coupling at the buffer outputs. The DisplayPort AUX channel data pair (net names DDI0\_SDA\_AUX+ and – in this example) are AC coupled on the COM-HPC Module, when the DDI channel is used in DisplayPort mode. ◦ When the DDI channel is used in HDMI mode, the DDIx\_SDA\_AUX+ and – pair (where ‘x’ is 0,1 or 2) are DC coupled on the Module, for the HDMI SDA and SCL I2C setup channel. The COM-HPC signal DDIx\_DDC\_AUX\_SEL signals are Module input signals that are used to select either DisplayPort or HDMI mode. ◦ If the signal is pulled or driven low, or left NC, then the Module invokes DisplayPort mode. ◦ If the signal is driven to a logic high, then the Module invokes HDMI mode. ◦ In this schematic example, the DDI0\_AUX\_SEL Module input signal is pulled low by R277 and ESD protected by part of ESD diode array D54. Almost all connections to the DP connector CN52 in the Figure 41 above are provided with EMI suppression components (common mode choke elements TR30 through TR34) and ESD protection arrays (D54 through D56). ◦ The EMI and ESD mitigation components used must be appropriate for the high data rates used by the DisplayPort data pairs. ▪ For the ESD diode arrays, this means selecting parts with a sufficiently low pin capacitance. For the EMI chokes, the selected parts should have a low differential impedance but a relatively high common mode impedance. ◦ It is extremely important that all the nets the DisplayPort data path be routed as differential pairs, preferably against an unbroken GND plane and without any stubs, or with minimal stubs. Note that the ESD protection arrays used in the example have 2 lands for each net being protected. This is to facilitate no-stub “flow through” routing. ▪ The ESD diode arrays should be positioned next to the DP connector pins. ▪ ESD diode array pins can be pin-swapped if needed to provide a cleaner PCB layout. ◦ DP connector pin 18 is used as a “Hot Plug Detect” signal. The external display drives this signal to a logic high to signal a display hot plug event. This signal is ESD protected by an element of D54 and buffered and level translated by U49 before being passed on to the COM-HPC module. The buffer input is pulled down by R276 in the example, ensuring that the COM-HPC HPD input signal is low if no DP display is present. Most of the information presented above for DisplayPort over DDI applies to the COM-HPC Mini as well, although the net names for the DDI related signals differ between the COM-HPC Client and the Mini and the AUX channel coupling caps are not on the Mini Module but rather on the Carrier. The DDI net name correlations between the Mini and the Client are shown in the COM-HPC Base Specification Revision 1.20 Section 10.5.3 Tables 117 and 118. The Mini AUX channel implementation with Carrier coupling caps is shown in the COM-HPC Base Specification Revision 1.20 Section 10.5.4 Figure 71. Finally the Hot Plug Detect signal level to the Mini has to be level shifted to be a 1.8V signal by altering or replacing the U49 circuit in the Figure 41 above. Some COM-HPC DisplayPort implementations may require a Carrier based redriver. A few industry offerings are listed in Table 16 below. There are of course more parts available on the market. Table 16: DisplayPort Redrivers and Retimers
VendorP/NNotes
Diodes IncPI3DPX1203B4 lane DisplayPort 1.4 redriver; up to 8.1 Gbps link rate
PI3DPX8121DisplayPort 1.4 and 2.0 compatible 2:1 mux and redriver, 2 sets of 4 lane inputs and a 4 lane output, with up to a 10 Gbps link rate.
Parade SemiconductorPS8463DisplayPort 1.4 redriver (8.1 Gbps)HDMI 2.0 redriver (6 Gbps)4 lanes
Texas InstrumentsDS160PR410This part is primarily a 4 lane PCIe Gen 4 capable redriver. However, the TI literature states that the part can be used for DisplayPort 2.0 redriver purposes, by setting a certain strap to disable the “PCIe Detect” mode. This is a very high bandwidth part and may work well with all DisplayPort modes.
There are quite a few USB Type-C and a few USB4 port multiplexers that incorporate redriver and in some cases retimer circuits. Such products come from Diodes Inc., Texas Instruments, and others. The Intel JHL9040R, also known as the “Hayden Bridge”, does DisplayPort, USB and PCIe retiming along with other USB Type-C and Thunderbolt functions. # 3.11. HDMI Over DDI Figure 42: HDMI Over DDI ![ Pin A0 A1 A4 PEN PIN_MODE DE1 DE0 V_DDD_33 V_DDD_36 --- --- --- --- --- --- --- --- --- --- A0 22 16 17 20 1 1 2 33 36 A1 16 15 15 24 27 33 33 33 33 A4 17 20 21 24 27 33 33 33 33 PEN 20 21 1 24 27 33 33 33 33 PIN_MODE 21 1 1 24 27 33 33 33 33 DE1 1 1 1 24 27 33 33 33 33 DE0 2 1 1 24 27 33 33 33 33 A0RX_+ 4 - - - - - - - - A0RX_- - - - - - - - - - A1RX_+ - - - - - - - - - A1RX_- - - - - - - - - - A2RX_+ - - - - - - - - - A2RX_- - - - - - - - - - A3RX_+ - - - - - - - - - A3RX_- - - - - - - - - - HDMI_SCL - - - - - - - - - HDMI_SDA - - - - - - - - - DDI0_BST0 - - - - - - - - - DDI0_BST1 - - - - - - - - - DDI0_BST2 - - - - - - - - - DDI0_BST3 - - - - - - - - - DDI0_VOD1 - - - - - - - - - DDI0_PS0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0S0s +3.3V_S PI3HDX1204-B *HDMI buffer has internal pull ups COM DDIO_DDC_AUX_SEL R57 R49 R48 R47 R46 R45 R44 R43 R42 R41 R40 R39 R38 R37 R36 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 R8 R7 R6 R6 R5 R4 R4 R3 R2 R1 R0 R9 K GND +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO + (sup)N(/sup)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/4be46b221dad06b6ea06ac9e0f4aca7bb9973d5036a77865ac1baaee26e9059a.jpg) ![L1 HDMI0_PAIR0+ 1 IN_1+ OUT_1+ HDMI0_PAIR0- 2 IN_1- OUT_1- HDMI0_PAIR1+ 4 IN_2+ OUT_2+ HDMI0_PAIR1- 5 IN_2- OUT_2- GND_3 GND_8 EMI8042MUTAG L2 HDMI0_PAIR2+ 1 IN_1+ OUT_1+ HDMI0_PAIR2- 2 IN_1- OUT_1- HDMI0_CLK+ 4 IN_2+ OUT_2+ HDMI0_CLK- 5 IN_2- OUT_2- GND_3 GND_8 EMI8042MUTAG J2 TMDS_DATA0+ V_+5V_POWER TMDS_DATA0- TMDS_DATA0_SHIELD TMDS_DATA1+ TMDS_DATA1- TMDS_DATA1- TMDS_DATA1_SHIELD TMDS_DATA2+ TMDS_DATA2- TMDS_DATA2- TMDS_DATA2_SHIELD TMDS_CLOCK+ TMDS_CLOCK- TMDS_CLOCK_SHIELD SCL DDC/HEC/CEC_GND SDA S1 S2 S1 HOT_PLUG_DETECT/HEC_DATA+ S2 CEC S3 S4 S4 RESERVED/HEC_DATA- FCI_10029449-001TLF GND +5.0V_S_DDIO GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/3f19fb1ba138e2b85405608e3a8511a4ce3868fc8513088cb420319f1ad8b085.jpg) ![+5.0V_S 1A1-S F1 +5.0V_S_FDDI0 2 D2 +5.0V_S_DDIO PMEG2010AE 10uF C42 0603 0603 16V 0.1uF C50 0402 0.1uF 25V 25V 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 +3.3V_S D1 1 PMEG2010AE 10uF C41 0603 0603 16V 0.1uF C43 0402 0.1uF 25V 25V 0.1uF 25V 0402 0.1uF 25V 0402 0.1uF 25V 0402 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SDDI0 +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO +3.3V_S_DDIO](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/f365b6a50135f4f6e6bec79301c07f7fb4ccc4fd12ebc267ff839adfd5c79d1c.jpg) \*Video I2C needs one buffer per port # Notes on Figure 42: HDMI Over DDI Above COM-HPC DDI signals can generally operate in DP mode or HDMI mode. COM-HPC input signal DDIx\_DDC\_AUX\_SEL (where x is 0, 1 or 2) selects between DP mode and HDMI mode. ◦ DDIx\_DDC\_AUX\_SEL left open or pulled low selects DP mode for DDIx. 。 DDIx\_DDC\_AUX\_SEL pulled or driven high to +3.3V\_S selects HDMI mode for DDIx. DP signals are AC coupled ◦ DP data pairs are AC coupled on the Carrier near the DP connectors, as can be seen in Figure 41: DisplayPort Over DDI above. DP AUX\_SEL pairs are AC coupled on the COM-HPC Module (nets DDIx\_SDA\_AUX+ and – in Figure 41). HDMI signals are generally DC coupled – at least from the HDMI / TMDS driver outputs, across the HDMI cable and on to the HDMI / TMDS receiver. DC coupling is shown for the HDMI / TMDS data pairs and the SDA / SCL setup lines in Figure 42 above. Figure 42 above a Diodes Inc / Pericom PI3HDX1204B combination HDMI level translator and redriver (U6 in the Figure 42 above). ◦ This part can be configured by resistor straps or over I2C. Both options are shown in the Figure 42 above. ◦ Components L1 and L2 are On Semiconductor EMI8042MUT offering combined ESD protection and EMI suppression. 。 Note that the +3.3V level DDIx\_SDA\_AUX+ and – HDMI setup signals are translated to a +5V level with component U8. ESD protection is included for all signals facing the outside world. There are many alternative HDMI level translators on the market. ◦ Texas Instruments, Analog Devices, Silicon Labs, Diodes Inc. and others offer HDMI level translators, redrivers and retimers. ◦ Many devices have built in ESD protection and level translation for the HDMI data pairs and the SDA / SCL setup channel. ◦ See Texas Instruments TPD12S016 for a basic HDMI level translator with integrated ESD protection. Some HDMI redrivers / retimers use AC coupling at their inputs, and DC coupling to the cable at their outputs. See, for example, Texas Instruments TDP158. There may be licensing fees involved if HDMI implementations are used, and there are strict rules about logo use. Check with the HDMI organization (www.hdmi.org). # Notes for HDMI on the COM-HPC Mini: The net names for the DDI related signals differ between the COM-HPC Client and the Mini. The correlation between the Mini “Super Speed” pairs and the DDI functions is found in the COM-HPC Base Specification Version 1.20 Section 10.5.3 Tables 117 and 118. The correlation between DDI and HDMI data pairs may be found in upper right of Figure 42 above, and in the COM-HPC Base Specification Version 1.20 Table 24. The HDMI DDC lines into the Mini need level translation from 5V (from the HDMI display) to 1.8V, and this must happen off Module. 。 This could be done by changing the supply voltage for the left side of U8 in Figure 42 above from 3.3V to 1.8V (the U8 FXMA2102 can handle this). 。 Many other I2C level translators are available. The Hot Plug Detect signal level to the Mini has to be level shifted to be a 1.8V signal into the Mini by altering or replacing the Q1 circuit in Figure 42 above. 。 One way to do this is to insert a 3.3V to 1.8V level shifter (such as Texas Instruments SN74LV1T125) in between Q1 and the COM-HPC Mini HPD pin. A 100K pull-down resistor in between the level shifter input and GND is needed, in case no HDMI display is present. The Q1 “output” (the source pin at the left side of Q1) is only approximately 3.3V depending on the FET Vgs. 1 The SN74LV1T125 will be fine with an input above 3.3V. There are HDMI buffer / re-driver parts available now which can handle the 1.8V sideband signals to and from the COM-HPC Mini directly. See, for example, the Texas Instruments TDP0604. The DDC and HPC level translations are integrated into the part, and sideband signals can be 1.8V or 3.3V. # 3.12. eDP Figure 43: eDP Schematic Example ![This image is a detailed electronic schematic diagram featuring signal routing, connectors, and power management circuits. **Top Section (Signal Routing & Connectors):** * **Connector CN42:** An I-PEX 20455-040E connector is shown on the right with pins 1 through 40. Labels include VDISP_BKLT, eDP_VDD_EN, eDPHPD, VDISP_VDD, and various EXT_EDP signal lines. * **Logic ICs:** * **U66 (74AUP1T97LX6):** A signal switch handling eDP_BKLT_CTRL. * **U52 (NC7WZ16P6X):** A dual analog switch handling eDP_HPD. * **Signal Lines:** Multiple differential pairs (eDP_TX0-3, eDP_AUX) are routed through capacitors (C1651-C1659) and inductors (TR1-TR5, labeled DLP11TB800UL2L) to the connector. **Middle Section (Cables & Notes):** * **Note Box:** Text reads: 'NOTE: To use with straight eDP cables'. * **Ribbon Cable:** A diagram shows a ribbon cable assembly labeled CN1 and CN2 (I-PEX 20453-040T-01). * **Connection Chart:** A table below the cable maps pins 1 through 40 for CN1 and CN2. **Bottom Section (Voltage Selection Circuits):** The bottom half is divided into two distinct voltage regulation sections: 1. **Left Side (Backlight):** * **Header Box:** 'PANEL BACKLIGHT VOLTAGE SELECTION / Set 1-2: 12V / Set 2-3: 5V (Default)'. * **Circuit:** Uses jumper JP12 (2211S-03G) and IC U67 (NCP45521IMNTWG-H). It includes fuse F12 (miniSMDC150F/24-2) and output capacitors C341-C345. 2. **Right Side (VDD):** * **Header Box:** 'PANEL VDD VOLTAGE SELECTION / Set 1-2: 5V / Set 2-3: 3.3V (Default)'. * **Circuit:** Uses jumper JP13 (2211S-03G) and IC U69 (NCP45521IMNTWG-H). It includes fuse F13 (microSMD150F-2) and output capacitors C346-C349.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/cdafce0175d596ca384aa53542b00e95a721619236639b2369460695c4cb75ad.jpg) NOTE: To use with straight eDP cables PANEL BACKLIGHT VOLTAGE SELECTION Set 1-2: 12V PANEL VDD VOLTAGE SELECTION Set 1-2: 5V Figure 44: eDP Connector Pin Numbering ![This diagram illustrates the pin numbering orientation for a connector, likely comparing a specific I-PEX part number against standard VESA/display vendor standards. **Blocks and Text:** * **Top Block:** A light blue rectangular box containing the text: **'I-PEX 20455-040E Pin Numbering'**. Inside the box, on the far left edge, is a black downward-pointing triangle. * **Bottom Block:** A light blue rectangular box containing the text: **'VESA and Display Vendor Pin Numbering'**. Inside the box, on the far left edge, is a black downward-pointing triangle. **Connections and Pin Layouts:** * **Top Pin Layout:** Above the top block is a row of small squares representing pins. The pin on the far left is labeled **'1'** and the pin on the far right is labeled **'40'**. * **Bottom Pin Layout:** Above the bottom block is a row of small squares representing pins. The pin on the far left is labeled **'40'** and the pin on the far right is labeled **'1'**. * **Middle Arrow:** A large black arrow pointing upwards is situated between the top and bottom blocks. Below this arrow is the text: **'Cable Entry'**. * **Bottom Arrow:** A large black arrow pointing upwards is situated below the bottom block. Below this arrow is the text: **'Cable Entry'**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/c9385f104f470f26565e858729018aefb2621413a5a88ee8661d056a312e00d9.jpg) The connector used for most eDP implementations is the I-PEX 20455-040E or equivalent. There can be some confusion about the pin numbering used in eDP systems. The connector vendor defines pin 1 at the left, as shown in the upper part of Figure 44 above. For reasons perhaps better lost to history, VESA and hence the eDP display vendors put pin 1 at the right side of the connector, as illustrated in the lower portion of the Figure, in spite of the datum mark at the left end of the connector. The eDP schematic sample in Figure 43 above uses the I-PEX pin numbering (as PCB designers generally prefer to follow the component vendor’s data sheet when making up PCB footprints). The net result here is that I-PEX pin 1 needs to map to VESA / Display pin 40, I-PEX pin 2 to VESA / Display pin 39 and so on. This happens with the straight through cable shown in Figure 43 above (which uses the I-PEX pin numbering on both ends of the cable). This cable works between a COM-HPC Carrier and a VESA eDP display (which uses the VESA pin order). Display cables for eDP typically use micro-coax wiring. The + and – conductors of an eDP data pair travel in separate but adjacent coax lines. Hence they are not electromagnetically coupled within the cable assembly, but since each conductor is completely shielded and are equal length, the differential transmission properties are preserved and this works very well even at the highest eDP data rates. The PCB traces on the Carrier and within the display assembly should be edge coupled differential pairs, as per usual. # Additional eDP Example Material An alternative eDP example implementation is presented in Section 6.2. , Appendix B: Alternative eDP Example near the end of this document. The information in this Section applies to the COM-HPC Mini as well as the Client. However, the single ended side-band signals (eDP\_BKLT\_CTRL, eDP\_HPD, eDP\_BKLT\_EN and eDP\_VDD\_EN) shown here are 3.3V signals on the COM-HPC Client Module but are 1.8V signals on the Mini. COM-HPC Carrier designs for the Mini have to accommodate this, if these lines are used. # 3.12.1. eDP / DP Conversions to Other Video Formats There are a number of video format conversion bridges available from NXP (www.nxp.com), Chrontel (www.chrontel.com) and others. These products allow conversion from eDP or DP to LVDS, analog VGA, HDMI, DVI and a host of older video formats such as CVBS, S-Video, BT656, BT1120, YPbPr etc. LVDS displays are not directly supported by COM-HPC. However conversion from an eDP or DP source (from COM-HPC) to LVDS input format displays is easily achieved using either the NXP PTN3460 (PTN3460I for the industrial temperature version) or the Chrontel CH7515. All common LVDS formats (single channel, dual channel, 16 / 18 / 24 bit color depths) are supported by these NXP and Chrontel parts. COM-Express Modules from several vendors routinely use the NXP PTN3460I behind the scenes to produce the COM-Express LVDS outputs from the chipset eDP channel. It may be wise to check with your Module vendor before selecting an eDP / DP conversion part, as the vendor may have a preference and have software / firmware support favoring a particular part. Some subtleties such as VESA EDID support, backlight control etc. may be easier using the video conversion part(s) supported by the COM-HPC Module vendor. Analog VGA support is still important in some limited markets. The NXP PTN3355 and the Chrontel CH7517 are popular parts for this task. This advice applies to COM-HPC Mini system designs as well. # 3.13. MIPI-CSI Camera Interface Figure 45: MIPI-CSI ![CN1 FPC/FFC_22 G3 21 22 20 R3 0ohm COM ) CSIO_RX0+ 19 18 16 14 12 10 8 6 4 2 G1 G2 Molex/525592253 CSIO_RX0- COM R1 0ohm CSIO_RX1+ COM R2 0ohm CSIO_CLK- COM R5 0ohm CSIO_RX2+ COM R8 0ohm CSIO_RX3- COM R9 0ohm CSIO_RST#_3V CSIO_I2C_CLK_3V +3.3V_S R13 0ohm C1 0.1uF_10V +1.8V_S C4 1uF_6.3V U2 VCCA VCCB CSIO_ENA_3V CSIO_RST# COM A1 B1 CSIO_RST#_3V COM A2 B2 CSIO_RST#_3V COM A3 B3 CSIO_I2C_CLK CSIO_I2C_DAT COM C2 1uF_6.3V U1 VCCA VCCB SCLA SCLB SDAA SDAB GND EN TCA9517ADGKR_VSSOP8 +3.3V_S R14 2.2K +-1% R15 2.2K +-1% CSIO_I2C_CLK_3V CSIO_I2C_DAT_3V CSIO_MCLK_3V +3.3V_S TXS0108EPWR_TI +3.3V_S R16 0ohm NI 2 Gnd U3 NI 74LVC1G125_SOT23-5 R18 0ohm_+-1%](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/52f288873257a88305a1547ff9b21e943e5724b9459c4a52996dedba448aef8b.jpg) A typical Carrier board MIPI-CSI implementation is shown in Figure 45 above. There is no standard connector for MIPI-CSI use. The Molex part shown in the Figure 45 above is a reasonable choice but many others are used in various situations. The example above distributes +3.3V\_S power to the camera, appropriate for many camera assemblies. However, many MIPI cameras are 1.8V devices, and the COM-HPC MIPI-CSI is defined as a 1.8V interface in the COM-HPC Base Specification document. Camera and support software selection is an important part of implementing a MIPI-CSI system. The cameras have particular data formats and non-linear data compensation requirements to account for camera characteristics. It is important to have a software driver plan that aligns with the camera choice and the Module chipset or SOC choice. There may well be NRE charges from the Module vendor to get a MIPI-CSI camera solution working, unless the vendor has a “canned” solution to offer. This information just above does NOT apply to the COM-HPC Mini. The Mini has separate FFC (Flat Foil Connector) connectors – separate from Module connector – see the Base Specification Revision 1.2 Section 10 for information on the Mini MIPI CSI implementation. # 3.14. Audio Interfaces # 3.14.1. General Discussion The COM-HPC Client Module pinout allows for up to four SoundWire audio ports and one I2S audio port. No audio support at all is offered on the COM-HPC Server Module pinout. The first two COM-HPC Client Mode SoundWire ports, numbered as 0 and 1, are free and clear and are not shared. Port 0 and Port 1 are two pins each, with CLK and DAT lines. The 3rd and 4th COM-HPC SoundWire ports, numbered as 2 and 3, are pin shared with an I2S audio port. No Intel HD Audio support at all is offered with COM-HPC revision 1.0. However it is to be offered in COM-HPC Base Specification revision 1.1 due to some delays in the industry SoundWire rollout. SoundWire is expected to be the mainstream x86 system audio interface going forward. I2S audio interfaces are also available on many contemporary x86 chipsets. I2S is the most popular audio interface on ARM designs at the time of this writing. This may shift to SoundWire over time. # 3.14.2. MIPI SoundWire Summary A 2 wire interface (CLK and DAT) is used. ◦ For most implementations there is a single Master and there may be multiple Slaves ◦ The CLK is an output from the Master 。 DAT is bidirectional signal, with data to and from Slaves The Master controls the DAT line direction, per MIPI SoundWire protocol • The SoundWire CLK and DAT lines may be run at 1.8V or 1.2V (per the MIPI specification) ◦ COM-HPC uses 1.8V SoundWire signaling ◦ This signaling should be available in all system states, S5 through S0 There may be up to 11 Slave devices on a SoundWire bus ◦ It is more common to have up to 4 Slave devices on a single SoundWire bus ◦ There is a MIPI defined enumeration process to identify the Slaves ▪ It involves a bit of trial and error but in time all Slaves are identified Some details on SoundWire clocking and signaling include: ◦ The CLK frequency used is set by the Master, and may be as high as 12.288 MHz ▪ The lowest appropriate frequency is used ◦ DDR (Double Data Rate) signaling is used (meaning that data is clocked on the rising CLK edge and the next bit on the falling CLK edge) ◦ The CLK frequency may be slowed or completely stopped by the Master, as required ▪ These clocking / data features allow lower power operation ◦ SoundWire uses a “modified” NRZI (Non Return to Zero Inverted) protocol on the data line ▪ This allows the enumeration capability and other features described in the MIPI specification ◦ Audio data may be encoded in several formats: ▪ PCM (Pulse Code Modulation) – the most common format PDM (Pulse Density Modulation) – has low hardware implementation overhead and is useful for simple devices such as digital microphones ▪ Bulk Mode – for large data blocks 。 Slaves may initiate in-band interrupts and wake events 。 I2C support for SoundWire devices is generally not needed (unlike for I2S) MIPI Slave devices may be wired together either in daisy-chain fashion or in a branched – tree topology, as shown in Figure 46 below. In either case, the SoundWire CLK and DAT lines should be routed together – not as a differential pair, but as a signal pair following approximately the same route paths, with approximate length matching all along the paths and for each branch, so that the signal flight time from Master to Slave for both the SoundWire CLK and DAT are about the same. If the balanced tree topology is used, the length of branches of the tree should be about the same. Chipset design guide examples tend to show a point to point SoundWire implementations with signal integrity measures. These include series damping resistors and snubbing capacitors, as depicted in Figure 47 below, The component values are design and layout dependent and may range from 0 to about 22 ohms for the series resistors and from 0 (i.e. not loaded) to about 22 pf for the capacitors. The MIPI Master – to Slave implementation is straightforward, as it only involves the CLK and DAT lines. There are sure to be many more CODEC or MIPI Slave device implementation details – such as filtered analog power supplies, decoupling and other component recommendations, analog layout recommendations etc., not covered here. This information is available from the CODEC and Slave device vendors. Table 17: SoundWire Audio CODECs
VendorVendor P/NNotes
Cirrus LogicCS42L42SoundWire and I2S Audio CODEC – data freely available on the web
RealtekALC711-VDSoundWire and I2S Audio CODEC – data restricted at time of this writing
There are quite a few SoundWire Slave devices available, such as microphones and amplifiers, that are simpler than full CODECs. Vendors include Analog Devices, Maxim Integrated Products, TDK, Texas Instruments and more. From a hardware compatibility view, these low end devices may be tied directly to one of the COM-HPC SoundWire ports – but be sure to check out the software support situation before putting hardware together. The reference designs from some x86 SOC and chipset vendors show SoundWire device implementations grouped into functions. For example, the first SOC or chipset SoundWire bus may host two or more output amplifiers, the second SoundWire bus an audio CODEC, and the third SoundWire bus hosts an array of SoundWire microphones. Check with your COM-HPC Module vendor to see if they have any specific SoundWire device recommendations and port mapping recommendations. # Intel SoundWire Sample Schematics and Design Guide Sample SoundWire implementations may be found in some Intel reference schematics. See, for example, NDA protected Intel document numbers 627073 and 627205. Intel NDA protected document number 627205 devotes several pages to SoundWire design They basically show a “balanced tree” with two branches of approximately equal length, and with two SoundWire loads. An alternative daisy chain arrangement with up to four loads is described as well. Also recommended are some optional series damping resistors. In the COM-HPC case, the optional damping resistors would be placed in the SoundWire clock and data lines near the COM-HPC connector. Figure 46: MIPI SoundWire Routing Topologies ![Based on the provided image, here is the accurate description of the flowchart: **Blocks:** * **COM-HPC Connector**: A large vertical block on the left containing the text 'SNDW_DMIC_DAT0', 'SNDW_DMIC_CLK0', 'SNDW_DMIC_DAT1', and 'SNDW_DMIC_CLK1'. * **SoundWire Slave**: There are six blocks labeled 'SoundWire Slave' on the right side. Each block contains the text 'SNDW_DAT' and 'SNDW_CLK'. * Four identical blocks are arranged vertically in the top section. * Two identical blocks are arranged vertically in the bottom section. **Connections and Topologies:** * **Daisy Chain Topology**: This label appears above the upper connection set. Lines originating from 'SNDW_DMIC_DAT0' and 'SNDW_DMIC_CLK0' connect to the inputs of the four 'SoundWire Slave' blocks in the top section. The lines fan out to distribute the signal to each slave. * **Balanced Tree Topology**: This label appears above the lower connection set. Lines originating from 'SNDW_DMIC_DAT1' and 'SNDW_DMIC_CLK1' connect to the inputs of the two 'SoundWire Slave' blocks in the bottom section via a branching junction.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/e597f849ab3bdf5e565f515277afc5888b4c55ff9538d94efc31e2bf730a38f6.jpg) Figure 47: MIPI SoundWire Point to Point Connection With SI Components ![The diagram depicts a circuit connecting two main blocks: **1. Left Block:** * **Label:** 'COM-HPC Connector' * **Internal Labels:** 'SNDW_DMIC_DAT0' (top) and 'SNDW_DMIC_CLK0' (bottom). **2. Right Block:** * **Label:** 'SoundWire CODEC' * **Internal Labels:** 'SNDW_DAT' (top) and 'SNDW_CLK' (bottom). * **External Icons:** To the right of this block are four icons: two speakers with musical notes and two microphones with musical notes. **Connections:** * **Top Path:** A line connects 'SNDW_DMIC_DAT0' to 'SNDW_DAT'. Along this line, a capacitor labeled '**C1**' connects to ground, followed by a resistor labeled '**R1**', then a resistor labeled '**R2**', and finally a capacitor labeled '**C2**' connects to ground. * **Bottom Path:** A line connects 'SNDW_DMIC_CLK0' to 'SNDW_CLK'. Along this line, a capacitor labeled '**C3**' connects to ground, followed by a resistor labeled '**R3**', then a resistor labeled '**R4**', and finally a capacitor labeled '**C4**' connects to ground.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/066d9becada83666374e8af60bcd9e0a0bb6d5ed01c258ee0f8ac0316bb1ddb4.jpg) # 3.14.3. I2S Implementations on COM-HPC An I2S audio implementation example specifically for COM-HPC is not available at the time of this writing. There are two I2S audio CODEC examples in the SMARC Design Guide that may be useful for reference: Cirrus Logic WM8904 Ultra Low Power CODEC Texas Instruments TLV320AIC3105 Low Power CODEC SMARC defines two I2S ports versus a single I2S port defined for COM-HPC. Apart from that, the definitions are very close: 1.8V logic level signaling. S0 power domain operation. Same signal definitions (although pin names do not quite match): ◦ An I2S clock out pin from the Module to a Carrier Slave. 。 An I2S data out pin defined. 。 An I2S data in pin defined. 。 An I2S Left – Right audio channel clock output pin defined. 。 An I2S audio master clock output defined. I2S implementations generally require a companion I2C interface to setup I2S device registers. This is evident in the SMARC sample drawings. The digital I/O levels for I2S and I2C on an I2S CODEC are generally the same. The COM-HPC I2S interface is a 1.8V interface, and hence the I2C interface used would need to be at 1.8V. The COM-HPC I2C1 interface is defined to be a 1.8V interface; the COM-HPC I2C0 is a 3.3V interface. Of course level translation can be implemented. Intel NDA protected document 616553, a schematic for an Elkhart Lake validation platform, shows an I2S CODEC implemented in a x86 based system. Elkhart Lake is an Atom class SOC and is not likely to be implemented on COM-HPC Client but may be implemented on a COM-HPC design. In any case the Intel eI2S example may be useful to designers looking to implement I2S audio on a COM-HPC Carrier. SoundWire does not require a companion I2C interface. Just the SoundWire Clock and Data lines are sufficient for both audio data and SoundWire slave register setup. The information in this Section applies to the COM-HPC Mini as well. The SGET SMARC Design guide is a useful document to find I2S CODEC and amplifier implementation examples, and many other 1.8V I/O parts. # 3.14.4. High Definition Audio (HDA) on COM-HPC Client and Mini An Intel HD Audio option was introduced to the COM-HPC Client on the COM-HPC Base Specification Rev. 1.10, due to the delayed rollout of SoundWire. The COM-HPC Mini supports HD Audio as well, as introduced in Base Specification Rev. 1.20 There are good Carrier Board HDA example designs available in the PICMG COM Express and the SGET SMARC Design Guides, although the CODECs shown are quite old. The net names between the COM-HPC Module and the target Carrier CODEC do not agree with the COM Express and SMARC Design Guides, but there are only 5 signals involved and the correlation is straight forward. # 3.15. Asynchronous Serial Port Interfaces # 3.15.1. COM-HPC UART Interfaces Two 3.3V logic level asynchronous serial ports, designated UART0 and UART1 are defined by COM-HPC. Each port has TX and RX signals for data use and RTS# and CTS# signals for optional handshake / flow control use. For logic level use, the TX and RX signals are active high and the RTS# and CTS# signals are active low. Some data sheets omit the trailing ‘#’ signal but the logic level handshake signals are active low nonetheless. The idle state, or ‘mark’ state, of the logic level TX line is high, or 3.3V in the COM-HPC case. These ports may be used directly as logic level asynchronous serial connections between COM-HPC Module and Carrier based devices, or between COM-HPC Module and Carrier based mezzanine devices such as certain Mini-PCIe or M.2 cards. Care has to be taken that the logic I/O levels match up. Note, for example, the (unused) UART connections on the left side of the M.2 E-Key card shown in Figure 14 above. The PCI-SIG M.2 specification defines the E-Key UART pins to be 1.8V signals so some non-inverting level translation would be needed in this case: 3.3V to 1.8V on the TX and RTS# lines leaving the COM-HPC Module, and 1.8V to 3.3V translation for the RX and CTS# lines coming into the COM-HPC Module. Dozens of suitable logic level translation products are available on the market. One such product is the Texas Instruments SN74LV1T125. For off-board, cabled connections, the logic level UART signals are usually translated into one of three common formats: RS-232, RS-422 or RS-485. RS-232 is a single ended format in which the ‘mark’ or ‘idle’ or ‘logic 1’ state is a negative voltage between -3V and -25V, and the ‘space’ or ‘logic 0’ state is a positive voltage between +3V and +25V. An RS-232 level translation implementation for UART0 and UART1 is shown in Figure 48 below. This example uses a pair of Maxim (Texas Instruments) MAX3243E level translators. These parts have built in capacitor based charge pumps that create RS-232 compliant voltage levels and avoid the need to distribute a negative voltage on the Carrier. Note that the signal polarities are inverted by the device. This particular Maxim device has built-in +/-15 kV air gap and +/-8 kV contact ESD discharge survivability. There are many similar devices from Texas Instruments, Analog Devices / Linear Technology, Diodes Inc. and others. The cable length that can be achieved with RS-232 interfaces depends on the data rate used. Generally, RS-232 cables lengths are limited to about 50 feet or less. RS-232 signals are most often used with D subminiature DB-9 or DB-25connectors. The RS-232 standard defines DTE (Data Terminal Equipment) and DCE (Data Communications Equipment) connector pinouts. A DTE chassis connector is a male connector, and a DCE chassis connector is female. The DTE and DCE pinouts are defined such that a straight cable (pin 1 to pin 1, pin 2 to pin2 etc. on the cable) may be used. With the straight cable, the DTE TX pin (or TX# pin if using that notation) lands on the DCE RX(or RX#) pin, and so on. For longer cable lengths, on the order of 1000 feet or more, differential signaling formats such as RS-422 or RS-485 are often used. These implementations are usually terminated in the twisted pair cable impedance at the receiving endpoints. Many suitable parts are available from Analog Devices / Linear Technology, Texas Instruments and others. These vendors offer very informative Application Notes. They also offer “multiprotocol” devices – devices that can handle RS-232, RS-422 and / or RS-485 hardware protocols. Some of these devices have switchable internal cable termination. Some products from these vendors offer galvanic isolation. The RTS# handshake line is often used in RS-485 implementations as a transceiver enable line. This of course needs appropriate software support. The COM-HPC Mini asynchronous serial ports are 1.8V level ports and the RS-232 level translators shown in the Figures below are not suitable as they are 3.3V parts. Suggestions for alternative parts are given on the page below. Figure 48: UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports ![+3.3V_S U1 C1+ V_VCC 26 27 1uF C6 16V 0402 C2+ V- 3 1uF C7 16V 0402 T1IN T1OUT 9 RS232 TX0# 10 RS232 RTS0 T2IN T2OUT 11 NC T3IN T3OUT R2OUTB 4 RS232_CTS0 5 RS232 RX0# R1OUT R1IN R2OUT R2IN R3OUT R3IN R4OUT R4IN R5OUT R5IN R5OUT R5IN R1IN 6 NC 7 NC 8 NC 20 NC 21 NC 22 NC 23 NC 24 NC 25 NC GND MAX3243E GND GND GND +3.3V_S U2 C1+ V_VCC 26 27 1uF C9 16V 0402 C2+ V- 3 1uF C10 16V 0402 T1IN T1OUT 9 RS232 TX1# 10 RS232 RTS1# T2IN T2OUT 11 NC T3IN T3OUT R2OUTB 4 RS232_CTS1 5 RS232 RX1# R1OUT R1IN R2OUT R2IN R3OUT R3IN R4OUT R4IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN R5OUT R5IN (U2) +3.3V_S U3 C4 0402 GND GND GND GND GND +3.3V_S U4 C5 0402 COM UART0_TX UART0_RTS# COM UART0_CTS# UART0_RX 10Kohms R1 0402 GND P1 P2 P3 P4 P5 P6 P7 P8 S1 S1T S2 T-S1P pinout of DB9 are configured as DTE ports. PYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins. PYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins. J1 NC 1T P1 NC 2T P2 NC 3T P3 NC 4T P4 NC 5T P5 NC 6T P6 NC 7T P7 NC 8T P8 S1 S1T S2 T-S1P pinout of DB9 are configured as DTE ports. PYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins. +3.3V_S PYCON_K42X-E9P-P-A4N * T- top pins, B- bot pins.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/98e6ff5a9b3dd6be267049cb03b0a19355647497f7cd4cc4457bf75843726fc8.jpg) The example presented just above for RS-232 level translation is NOT suitable for the COM-HPC Mini implementations as the Texas Instruments MAX3243 does not operate with a 1.8V supply voltage and chipset I/O voltage. However, there are dozens of parts available that do operate at 1.8V levels. One example is the Texas Instruments TRS3122E. There are many other possibilities from TI. Another useful vendor for these types of parts is Analog Devices. The AD LTC2802 and LTC803 are some of the many possibilities. The SGET SMARC Design Guide shows additional 1.8V I/O possibilities. # 3.15.2. Legacy Compatibility With 16C550 UART Register Set The I/O mapped UART that was the de-facto standard defined at the dawn of the personal computer age is the National Semiconductor (now Texas Instruments) 16550 or 16C550. Many BIOSes support 16C550 operations early in the BIOS boot (before USB devices are enumerated). Console redirect and Port 80 debug codes are often directed to a 16C550 compatible I/O register set. Windows, Linux and other popular operating systems used in embedded system almost universally support the 16C550 UARTs. The COM-HPC Base Specification encourages but does not require 16C550 register compatibility for the UART0 and UART1 ports. Check with your Module vendor. Once the operating system is running and drivers are loaded, 16C550 compatibility is a non-issue, but for early boot support it is valuable. # 3.15.3. Alternative / Additional Carrier Board UART Implementations If additional or perhaps higher performance UARTs beyond what the COM-HPC Module provides are needed, there are a number of excellent options available. A few of these are summarized in the Table below.. Table 18: Alternative / Additional Carrier Board UART Implementations
VendorInterfaceSample Vendor P/Ns16C550 CompatibleFeatures / Notes
FTDIUSB 2.0 FSFT232RUSBNoFuture Technology Devices IncWebwww.FTDlchip.comSeveral similar parts availableWin 10 and Linux drivers
MaxLinear (Exar)USB 2.0 FSXR21V1410XR21B1420NoWebwww.maxlinear.com
MaxLinear (Exar)PCIe x1Gen 2XR17V352XR17V354XR17V358YesWebwww.maxlinear.comDual, Quad and Octal partsVery deep FIFOs, high bit ratesNative Windows and Linux supportVendor drivers also availableRS485 support
MicrochipUSB 2.0 FSMCP2220NoWebwww.microchip.com
# 3.16. I2C / I3C Ports The COM-HPC pinout definition supports a traditional I2C port, designated I2C0, and a second port designated I2C1, targeting (optional) MIPI I3C use along with backward compatibility to traditional I2C.The I2C0 port runs at 3.3V and I2C1 at 1.8V. Both are active in suspend and full-on power states. I2C is an abbreviation for “Inter Integrated Circuit”. It was defined by Philips (and later inherited by NXP) as an easy to use two wire method for a Master device to set and read back Slave peripheral IC registers and data values. It uses, in it’s basic form, open-drain drivers and passive pull-ups. The current NXP specification document is freely available (see reference in Section 1.9. ) and defines several modes of operation, summarized in the following Table: Table 19: I2C Operating Modes
I2C ModeOperating FrequencyMax Rise TimeMax Bus CapacitanceNotes
Standard100 KHz1000 nsec400 pF
Fast400 KHz300 nsec200 pF (passive pull-up)400 pF (active pull-up)See NXP UM10204 Section 5.2
Fast Plus1 MHz120 nsec550 pF (active pull-up)
High Speed3.4 MHz3 Mbps throughputNot described in NXP UM10204Referenced in some literature including Intel
The COM-HPC Base Specification V1.0 document recommends a 2.2K ohm on-Module pull-up on the I2C0 and I2C1 Clock and Data lines. This value is sufficient for all Standard Mode (100 Khz) situations as the RC time constant is 880 nsec (= 2.2K \* 400 pF) in the worst case, under 1000 nsec. In most situations, the I2C bus capacitance is much lower than 400 pF: Typical IC pin capacitances are 6 to 8 pF • A typical PCB trace capacitance is 4 pF / inch – this varies with stackup details If, for example, there are 10 devices on the bus and there is a 20 inch total trace length, the bus capacitance would be about 160 pF (= 8 pF \* 10 + 4 pF / inch \* 20 inch) This rough calculation includes both the Module and Carrier I2C devices and trace lengths, with about 5 inches assumed on the Module. The 2.2K Module pull-up is not sufficient for the worst case Fast Mode (400 Khz) passive mode bus capacitance of 200 pF. The 2.2K value handles up to about 100 pF of bus capacitance. A 2nd, parallel set of 2.2K pull-ups on the Carrier I2C Clock and Data lines would be advisable if the bus loading is over 100 pF. The Carrier pull-ups can always be left unpopulated if they are not needed. There are various application notes on this subject available on-line. See, for example, Texas Instruments document SLVA689 titled “I2C Bus Pullup Resistor Calculation”. The Module design may include active circuitry to better support I2C Fast Mode and to support Fast Mode Plus. Check with the Module documentation or with the Module vendor. # 3.16.1. I2C Addressing I2C uses a 7 bit addressing scheme to differentiate I2C resources. The address lines are designated A6 … A0, but they are part of an 8 bit frame, in bit positions 7 through 1. Bit position 0 is used in the I2C device address to designate whether the current operation is a Read (a logic ‘1’) or a Write (a logic ‘0’). Thus I2C addresses can be described in either 7 bit or 8 bit formats. If using the 8 bit format to describe I2C addresses, the R/W bit is always assumed to be ‘0’. The 8 bit frame is transmitted MS bit first. The 4 most significant bits in the 7 bit I2C address field are used to define I2C device categories that are fixed by the I2C specification. The 3 least significant bits allow up to 8 devices within an I2C category to be identified by the I2C silicon vendor and / or the user. There are usually pin straps or specific product SKUs that define the 3 bit LS bit addresses. It is useful to put together a table of I2C devices and addresses used in a design on both the Module and the Carrier, to ensure that there are no conflicts and to provide the information to software engineers. The Module vendor should provide such a list for I2C devices on the Module that are exposed / accessible on the COM-HPC I2C0 and I2C1 buses. Two I2C memory devices for COM-HPC use, at specific I2C0 addresses, are designated in the COM-HPC Base Specification, Version 1.0, Section 5.2: • A Module EEPROM device at hexadecimal address 0x50 (7 bit I2C addressing) or 0xA0 (8 bit addressing) • A Carrier EEPROM device at hex address 0x57 (7 bit addressing) or 0xAE (8 bit addressing) The Module and Carrier EEPROM data structures and contents are described in the PICMG documents EeeP for COM-HPC (Embedded EEPROM for COM-HPC) and the PICMG COM-HPC Platform Management Interface Specification. Figure 49: I2C0 Example: Carrier EEPROM in S5 Power Domain ![COM I2C0_CLK COM I2C0_DAT COM GPIO_00 R9 DNI R1 R2 R3 R4 +3.3V_A U2 SCL VCC SDA WP A2 A1 A0 GND Microchip / Atmel AT24C32 (32 Kbit) AT24C64 (64 Kbit) +3.3V_A 8 C1 100 nF 4](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/28745fd42dcc849bb16a37458207319bac8eaed86ddf82a9e515916378bebe32.jpg) For COM-HPC Mini use, this Figure 49 needs to be adapted to 1.8V I/O levels. The parts listed for U2 above can be used with a 1.8V supply. The resistor pull-ups need to be pulled to 1.8V as well. # 3.16.1. I2C0 Example: Carrier I2C Device in S0 Power Domain The COM-HPC I2C0 port is a basic 3.3V I2C port active in all power states (S5 through S0). It is a three wire port with CLK, DAT and ALERT# pins. The ALERT# pin, if supported by the COM-HPC Module, can serve as an interrupt input to the Module. An implementation example is given in Figure 50 below. In this example, a temperature sensor that is in the S0 power domain (+3.3V\_S power net) is connected to the S5 domain COM-HPC Module I2C0 port through isolation FETs T2, T3 and T4. These FETs serve to prevent the S5 power domain I2C0 port from being dragged down when the +3.3V\_S power rail is absent. I2C0 bus pull-up resistors to the +3.3V\_A (Always on) power rail are on the COM-HPC Module. Secondary pull-ups to the +3.3V\_S (Switched) power rail are shown in the Figure 50 below. The ALERT# pin on the IC shown in the Figure is asserted by the LM75B device when a temperature threshold that had been previously set using the I2C0 interface is crossed. The I2C address of the LM75B device is set at 0x90 (8 bit addressing). The lower 3 bits of the LM75B I2C5 4 3 2 address are set by the A2, A1,A0 pin straps. Up to 7 additional devices could be deployed by setting different addresses options on these pin straps. Figure 50: I2C0 Example: Carrier Temperature Sensor in S0 Power DomainI2C Temperature Se ![+3.3V_S T4 2N7002T 1 R542 4k7 0402 I2C0_DAT_S0 +3.3V_S T2 2N7002T 1 R540 4k7 0402 I2C0_CLK_S0 +3.3V_S T3 2N7002T 1 R541 10k0 0402 I2C0_ALERT#_S0 +3.3V_S U64 SDA VCC SCL OS A2 A1 GND A0 LM75B +3.3V_S C713 100n 0402 25V I2C addr: 0x90](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/3b6dc258c9ad7e4c906ffbc8f0c3c5781617fe989793d90fecd077a7f3801c5f.jpg) Note: the COM-HPC Mini I2C0, I2C1 and I2C2 ports are defined as 1.8V ports, so the Figure 50 above, using 3.3V supplies and parts does not directly apply to the Mini. Newer parts such as the Texas Instruments TMP1075 I2C temperature sensor can operate with a 1.8V supply. N channel FETs with a lower Vgs than the 2N7002 would need to used if this circuit is used for the Mini. The Rohm RA1C030LD is one of many possibilities. This part has a Vgs ranging from 0.5V to 1.5V. Alternatively, the N FETs in the Figure 50 above may be replaced with I2C level shifters for the Mini. There are dozens of such parts. The TI / NXP PCA9306 is an example. This is addressed in Section 3.16.2. just below. The SMARC Design Guide may be a valuable resource as well for identifying 1.8V capable parts. # 3.16.2. I2C Bus Buffers / Level Translators There are a number of bus buffers and level translators that target I2C and SMBus situations. Some suggested vendors and parts to consider are listed in Table 20 below. These parts allow for power domain isolation as the I/O pins go into a high impedance mode if one or both of power rails collapse. There are many other possibilities. Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation
VendorPartNotes
Texas InstrumentsTCA9517An upgrade and replacement for the popular NXP PCA9517
On SemiconductorFXMA2102
Texas Instruments / NXPPCA9306
# 3.16.3. I2C1 (COM-HPC) and Optional I3C Support The COM-HPC Base Specification defines a second I2C port, designated I2C1. This port is a 2 wire port (clock and data; no ALERT#) that operates from the 1.8V S5 and S0 power rails. The COM-HPC specification states that this port supports I2C and optionally supports I3C operation. I3C is mostly backward compatible with I2C but there are some caveats and differences, summarized in the section just below. If the user “just” wants an additional I2C port, than the I2C / I3C differences are not important and the user may proceed with a traditional I2C implementation, bearing in mind the 1.8V operating voltage and the S5 / S0 power domain. If combined I3C / I2C operation is expected, then the material presented just below is important. # MIPI I3C Discussion The MIPI Alliance has defined a significant enhancement to traditional I2C, known as I3C, an acronym for “Improved Inter Integrated Circuit” communication. I3C is significantly faster than I2C, and has some notable feature improvements, summarized below. It is largely, but not completely, backward compatible with I2C, also noted below. Recall that I2C is a 2 wire interface (with an optional 3rd wire for an ALERT# input) that operates in most cases as a 100 KHz or 400 KHz interface, with some 1 MHz and 3.4 MHz implementations. I3C enhancements beyond I2C include: 12.5 Mbps SDR (Standard Data Rate) operation using a 12.5 MHz clock • 25 Mbps DDR (Double Data Rate) operation (12.5 MHz clock, using rising and falling clock edges) • 33.3 Mbps Ternary Encoding operation (too complicated to explain here; see the MIPI documentation) Higher bandwidth and lower power operation ◦ Active pull-ups rather than passive pull-ups increase speed and lower power consumption • In – band interrupts (ALERT# pin not needed) – 2 wire operation only Error detection Error correction, in the Ternary mode Dynamic addressing • Hot – Join operation (devices may be powered down and rejoin at power up; not same as Hot-Plug) However, there are some issues with complete backward compatibility between I3C and legacy I2C: I2C devices on an active I3C bus need “50 nsec spike filters” in series with their Clock and Data pins to prevent the legacy I2C devices from getting confused by some fast short signals (“spikes”) present in I3C traffic. ◦ The spike filters can be simple RC circuits (series resistor in front of I2C device pin, capacitor between IC pin and GND). I2C clock stretching is not allowed on an I3C bus I2C clock stretching is not allowed on an l3C bus I2C bus 10 bit addressing mode is not allowed in I3C I2C bus 10 bit addressing mode is not allowed in l3C Check with your COM-HPC Module vendor for details about their possible I3C support on the COM-HPC I2C1 port. # 3.16.4. I2C on COM-HPC Mini The COM-HPC Mini supports three general purpose I2C ports, designated I2C0, I2C1 and I2C2. This is one more general purpose I2C port than the COM-HPC Clients and Servers have. On the Client and Server Modules, I2C0 is a 3.3V interface and I2C1 is a 1.8V port. On the COM-HPC Mini, I2C0, I2C1 and I2C2 are all 1.8V ports. The I2C2 port is targeted to support SGMII PHYs in COM-HPC Mini systems. The actual net names are I2C2\_CLK/ETH\_MDIO\_CLK and I2C2\_CLK/ETH\_MDIO\_DAT. COM-HPC Mini SGMII implementation example in Section 3.25. below. It shows the I2C2 / MDIO pins used for SGMII PHY support. # 3.17. Port 80h Debug Display Over COM-HPC USB\_PD\_I2C Figure 51: Port 80h Debug Display Over COM-HPC USB\_PD\_I2C ![C701 100n 0402 25V +3.3V_A C702 100n 0402 25V U58 21 23 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 VDD(P) VDD(I2C) P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 DIG1_NU R534 100k 0402 DIG1_G DIG2_G_R R516 270R 0402 DIG2_G_R R519 270R 0402 DIG2_E_R R521 270R 0402 DIG2_E_R R523 270R 0402 DIG2_D_R R524 270R 0402 DIG2_D_R R525 270R 0402 DIG2_A_R R526 270R 0402 DIG1_A_R R527 270R 0402 DIG2_B_R R528 270R 0402 DIG1_B_R R529 270R 0402 DIG2_C_R R530 270R 0402 DIG1_C_R +3.3V_A R531 10k 0402 INT_PCD1# INT_PCD1# COM COM SDA SCL PPSS/RESET ADDR RES_PCD1# R532 10k 0402 +3.3V_A I2C Pull-Up on COM-HPC module PCA6416A 8 bit addr: 0x40](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/cd37dd0d05779c4241f17d9eafcd504a98edae1926eb669746a69d42099ea2da.jpg) ![MSB D66 CA0 CA1 3 8 +3.3V_A DIG2_A 10 DIG2_B 9 DIG2_C 7 DIG2_D 5 DIG2_E 4 DIG2_F 2 DIG2_G 1 +3.3V_A 6 a b c d e f g DP f a b g e c d DP 7SEG10CAGRN](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/bdf6ac8531103c529c2f61a9651b35835e81799c7d96f0680e3238280edb59ea.jpg) Kingbright SA39-11GWA ![LSB D67 CA0 CA1 3 8 +3.3V_A DIG1_A 10 DIG1_B 9 DIG1_C 7 DIG1_D 5 DIG1_E 4 DIG1_F 2 DIG1_G 1 +3.3V_A 6 DP 7SEG10CAGRN](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/ca319c471c3b504ca1e443a3100fe785ccccf30ee6a7fc8f33ff13bada3df816.jpg) The COM-HPC hardware specification allows for BIOS Port 80h debug codes to be serialized and transmitted over the USB Power Delivery I2C bus (COM-HPC pins USB\_PD\_I2C\_DAT and \_CLK). Figure 50 above illustrates how the codes can be de-serialized and displayed on a pair of 7-segment LED displays. This feature is optional. There are other methods for Port 80h codes to be conveyed for debug use. The Port 80h I/O writes can be picked off of the eSPI bus or even a PCIe x1 link by appropriate hardware such as a CPLD, FPGA or some Super I/O devices. Some BIOSes provide 4 digit codes as opposed to 2 digit codes. It is also possible for special debug versions of a BIOS to transmit ASCII versions of the Port 80h debug codes over one of the asynchronous serial ports … check with your Module vendor. This circuit may be used on a COM-HPC Mini system, with a small modification: the PCA6416A device can be configured for 1.8V I2C operation: U58 pin 23 and it’s bypass capacitor C702 in the Figure 50 above need to be moved off the 3.3V power rail and onto a 1.8V rail. # 3.18. Carrier BMC with IPMB Link to Module A high end Carrier BMC (Board Management Controller) using an Aspeed AST2500 / AST2520 is shown in Figures 52, 53 and 54 below. The three Figures do not show the complete implementation – the DDR4 memory devices and the Aspeed power section are omitted. What is shown are the features relevant to COM-HPC operation – the interfaces to the COM-HPC and to the user. Refer to the Aspeed documentation for complete design information. The BMC interfaces to the Module include IPMB, eSPI, UART1, I2C0 and a collection of status and control signals such as power state status, reset, power button etc. BMC operator interfaces include a USB port for keyboard and mouse use, a VGA port, and a 1000BASE-T management network interface. The primary management interface to the COM-HPC Module is over the IPMB. The Module, if it supports management functions, includes a small satellite controller known as the MMC (Module Management Controller). The MMC has at minimum an IPMB slave interface to the BMC. The design shown includes two SPI Flash devices attached to the BMC, and an eSPI interface to the COM-HPC. The COM-HPC BIOS image can reside in the BMC attached SPI Flash. This allows the BMC to manage Out of Band Flash BIOS updates, if so desired. This (just above) does not apply to the COM-HPC Mini. Figure 52: Carrier BMC with IPMB Link to Module – Sheet 14 ![The image displays a schematic diagram for an AST2500/2520 BMC (Baseboard Management Controller) chip, labeled U5A. **Top Section (PCI-Express):** - **Left:** PLTRST#, COM, R45 DNI X 100K +1%, R44 0ohm +5% PCIe_BMC_RST#, L20. - **Center:** U5A, AST2500/2520, Rev.1.5, PCI-Express. - **Right:** PERST#, PEREFCLKP, PEREFCLKN, PEREXT, PERXP, PERXN. L21 PCIE_BMC_RX_P_C, C4 0.1uF 25V, COM PCIe_BMC_RX+. L22 PCIE_BMC_RX_N_C, C5 0.1uF 25V, COM PCIe_BMC_RX-. K20 PD_P2E_BMC_PEREXT, R47 200ohm +1%. +3.3V_A. **Left Side:** - **For DDR4 Memory:** V_M_BMC_DDR4_DQ0 (W10), V_M_BMC_DDR4_DQ1 (Y10), V_M_BMC_DDR4_DQ2 (AA10), V_M_BMC_DDR4_DQ3 (U9), V_M_BMC_DDR4_DQ4 (Y9), V_M_BMC_DDR4_DQ5 (W9), V_M_BMC_DDR4_DQ6 (V9), V_M_BMC_DDR4_DQ7 (AA8), V_M_BMC_DDR4_DQ8 (Y8), V_M_BMC_DDR4_DQ9 (Y7), V_M_BMC_DDR4_DQ10 (W8), V_M_BMC_DDR4_DQ11 (AA6), V_M_BMC_DDR4_DQ12 (W7), V_M_BMC_DDR4_DQ13 (V7), V_M_BMC_DDR4_DQ14 (U7), V_M_BMC_DDR4_DQ15 (AB9), V_M_BMC_DDR4_DQS0_DP (AB7), V_M_BMC_DDR4_DQS1_DP (AB10), V_M_BMC_DDR4_DQS0_DN (AB6), V_M_BMC_DDR4_DQS1_DN (AB17), V_M_BMC_DDR4_RST_N (U16), V_M_BMC_DDR4_ALERT_N, R3512 DNI 4.7K +1%, +1.2V_A, C6 0.1uF 25V, +0.6V_A, T9, R68 240ohm +1% W11. - **eSPI:** eSPI_CLK (COM, R70 0ohm +5%, C22), eSPI_CS0# (COM, R72 0ohm +5%, F21), eSPI_CS1# (COM, R74 0ohm +5%, F22), eSPI_ALERT0# (COM, R76 0ohm +5%, G21), eSPI_ALERT1# (COM, R78 0ohm +5%, G22), eSPI_RST# (COM, R80 0ohm +5%). - **GPIO/LPC:** J20, GPIO4B_USBCK1 (H21), GPIOB5_LPCPD_LPCSMI (H22), GPIOB6_LPCPME (H20), GPIOB7, +3.3V_A, R81 10K +1% LPC_PME_N. - **SD/SDIO/I2C/GPIO:** C12, GPIOC0_SD1CLK_SCL10 (B12), GPIOC1_SD1CMD_SDA10 (D9), GPIOC2_SD1DAT0_SCL11 (D10), GPIOC3_SD1DAT1_SDA11 (E12), GPIOC4_SD1DAT2_SCL12 (C11), GPIOC5_SD1DAT3_SDA12 (B11), GPIOC6_SD1CD_SCL13 (F19), GPIOC7_SD1WP_SDA13 (E21), GPIOID0_SD2CLK (E20), GPIOID1_SD2CMD (D20), GPIOID2_SD2DAT0 (E20), GPIOID3_SD2DAT1 (E20), GPIOID4_SD2DAT2 (E20), GPIOID5_SD2DAT3 (G18), GPIOID6_SD2CD (C21), GPIOID7_SD2WP (B14), GPIOA0_MAC1LINK (D14), GPIOA1_MAC2LINK (E13), GPIO2_TIMER3_SPI1CS1, GPIOA3_TIMER4. **Center Chip (AST2500/2520):** - **Left Column Pins:** MD00, MD01, MD02, MD03, MD04, MD05, MD06, MD07, MD08, MD09, MD010, MD011, MD012, MD013, MD014, MD015, MDQS0, MDQS1, MDQS0, MDQS1, MRESET, MALERT, MVREF, MIOZ, LPC, ESPI, GPIOAC4_ESPICK_LCLK, GPIOAC5_ESPIC0_LFRAME, GPIOAC6_ESPIALT_LSIRQ, GPIOAC7_ESPIRST_LPCRST, GPIO4B_USBCK1, GPIOB5_LPCPD_LPCSMI, GPIOB6_LPCPME, GPIOB7, GPIOC0_SD1CLK_SCL10, GPIOC1_SD1CMD_SDA10, GPIOC2_SD1DAT0_SCL11, GPIOC3_SD1DAT1_SDA11, GPIOC4_SD1DAT2_SCL12, GPIOC5_SD1DAT3_SDA12, GPIOC6_SD1CD_SCL13, GPIOC7_SD1WP_SDA13, GPIOID0_SD2CLK, GPIOID1_SD2CMD, GPIOID2_SD2DAT0, GPIOID3_SD2DAT1, GPIOID4_SD2DAT2, GPIOID5_SD2DAT3, GPIOID6_SD2CD, GPIOID7_SD2WP, SD/SDIO, I2C, GPIOA0_MAC1LINK, GPIOA1_MAC2LINK, GPIO2_TIMER3_SPI1CS1, GPIOA3_TIMER4, GPIO, 1 OF 4, AST2500A2-GP. - **Right Column Pins:** PEREXT, MCK (AB11), Y11 (AB12), V11 (AB12), AA12 (AB13), W12 (AB13), Y12 (Y12), U12 (Y13), W13 (V13), MA0 (AB14), MA1 (W14), MA2 (U14), MA3 (V15), MA4 (AB16), MA5 (AA16), MA6 (Y16), MA7 (U13), MA8 (AA14), MA9 (Y14), MA10 (AB15), MA11 (Y15), MA12 (U15), MA13 (AB8), MA14_MACT (MD0), MA15 (MD1), MD0 (MD0), MD1 (MD1). - **LPC/ESPI/GPIO (Right Side):** GPIOAC0_ESPID0_LAD0, GPIOAC1_ESPID1_LAD1, GPIOAC2_ESPID2_LAD2, GPIOAC3_ESPID3_LAD3, GPIOB0 (K19), GPIOB1 (L19), GPIOB2 (L18), GPIOB3 (K18), GPIOY4_SCL1 (M18), GPIOY5_SDA1 (M19), GPIOY6_SCL2 (M20), GPIOY7_SDA2 (P20), GPIOQ0_SCL3 (A11), GPIOQ1_SDA3 (A10), GPIOQ2_SCL4 (A9), GPIOQ3_SDA4 (B9), GPIOY0_SCL5 (L3), GPIOY1_SDA5 (L4), GPIOY2_SCL6 (L1), GPIOY3_SDA6 (N2), GPIOX0_SCL7 (P1), GPIOX1_SDA7 (P2), GPIOX2_SCL8 (P2), GPIOX3_SDA8 (P1), GPIOY5_TIMER5_SCL9 (C14), GPIOY6_TIMER6_SDA9 (A13), GPIOA0_SDA14 (N21), GPIOA1_SDA15 (N22), GPIOA2_TIMER3_SPI1CS1 (B10), GPIOA3_TIMER4 (N20). **Right Side:** - **For DDR4 Memory:** V_M_BMC_DDR4_CLK_DP (MCK), V_M_BMC_DDR4_CLK_DN (Y11), V_M_BMC_DDR4_CKE (V11), V_M_BMC_DDR4_ODT (AA12), V_M_BMC_DDR4_CS_N (W12), V_M_BMC_DDR4_MA16 (Y12), V_M_BMC_DDR4_MA15 (U12), V_M_BMC_DDR4_BA0 (W13), V_M_BMC_DDR4_BA1 (Y13), V_M_BMC_DDR4_BG0 (V13), V_M_BMC_DDR4_MA0 (MA0), V_M_BMC_DDR4_MA1 (MA1), V_M_BMC_DDR4_MA2 (MA2), V_M_BMC_DDR4_MA3 (MA3), V_M_BMC_DDR4_MA4 (MA4), V_M_BMC_DDR4_MA5 (MA5), V_M_BMC_DDR4_MA6 (MA6), V_M_BMC_DDR4_MA7 (MA7), V_M_BMC_DDR4_MA8 (MA8), V_M_BMC_DDR4_MA9 (MA9), V_M_BMC_DDR4_MA10 (MA10), V_M_BMC_DDR4_MA11 (MA11), V_M_BMC_DDR4_MA12 (MA12), V_M_BMC_DDR4_MA13 (MA13), V_M_BMC_DDR4_ACT_N (MA14_MACT), V_M_BMC_DDR4_DM0 (MA15), V_M_BMC_DDR4_DM1 (MD0), MD0, MD1. - **I2C/IPMB/Thermal Sensor:** BMC_SCL1 (R48 DNI X 4.7K +1%), BMC_SDA1 (R49 X 4.7K +1%), BMC_SCL3 (R52 DNI 4.7K +1%), BMC_SDA3 (R53 X 4.7K +1%), BMC_SCL8 (R62 DNI X 4.7K +1%), BMC_SDA8 (R63 X 4.7K +1%). - **eSPI:** GPIOAC0_ESPID0_LAD0 (R73 0ohm +5%, COM eSPI_IO0), GPIOAC1_ESPID1_LAD1 (R75 0ohm +5%, COM eSPI_IO1), GPIOAC2_ESPID2_LAD2 (R77 0ohm +5%, COM eSPI_IO2), GPIOAC3_ESPID3_LAD3 (R79 0ohm +5%, COM eSPI_IO3). - **I2C:** GPIOY4_SCL1 (BMC_SCL1, R82 0ohm +5%, COM I2C0_CLK), GPIOY5_SDA1 (BMC_SDA1, R83 0ohm +5%, COM I2C0_DAT). - **IPMB:** GPIOQ0_SCL3 (BMC_SCL3, R86 0ohm +5%, COM IPMB_CLK), GPIOQ1_SDA3 (BMC_SDA3, R87 0ohm +5%, COM IPMB_DAT). - **For Thermal Sensor:** GPIOX2_SCL8 (BMC_SCL8, R96 0ohm +5%, SENSOR_SCL), GPIOX3_SDA8 (BMC_SDA8, R97 0ohm +5%, SENSOR_SDA). - **GPIO:** GPIOA3_TIMER4 (R3515 DNI 0ohm +5%), GPIOA2_TIMER3_SPI1CS1 (R3516 DNI X 4.7K +1%), +3.3V_A, COM WAKED#](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/f8f864433f752508ca02a26d944558ffcc2289c7ac01e2c516bb6eddbba771a3.jpg) Figure 53: Carrier BMC with IPMB Link to Module – Sheet 2 ![The image contains two diagrams: on the left, a schematic diagram showing a multi-pin network interface with labeled ports (e.g., R108, R107, R104, etc.) and connected to a 3.3V-A connector pinout. The right diagram shows a single module with three pins (RSST_BTN, RST_BMC_SYSRST_BTN_OUT_N) and four pins (RSST_BMC_SYSRST_BTN_OUT_N). Each pin is connected to a 3.3V-A connector pinout. The 3.3V-A connector pinout is connected to a 3.3V-A connector pinout. The 3.3V-A connector pinout is connected to a 3.3V-A connector pinout. All components are interconnected in a grid layout with labels indicating their names and functions. The diagram includes annotations such as “For BMC Console Port” and “For Management Network,” which are explicitly labeled at the bottom. The diagram includes text labels such as “For BMC Console Port” and “For Management Network,” which are embedded in the center of the circuit.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6abc0baad2c05363bec0c76b925ddef6f7396eeb3b2a6c1393c9fe5a71de9d92.jpg) Figure 54: Carrier BMC with IPMB Link to Module – Sheet 3 ![OSC2 VCC OUT 3BMC_24M ST GND 2 R160 24MH2_15p EPSON-SG210STF-24M-L 22ohm_+1% R161 C12 0.1uF_25V DIN 1 R169 BMC_SRSST_BTM_N 0ohm_+5% R165 +3.3V_A 4.7K_+1% R169 BMC_SYS_RESET_N U18 BMC_EXT_RST Y18 R170 PD_BMC_ENTEST K3 10K_+1% LGI-170Y-CT BMC_HB A K R174 330ohm_+1% BMC_FAN_TACH0 U5 U4 V5 AB4 AB3 Y4 AA4 W4 V4 W5 AA5 AB5 Y6 W6 W5 W6 W6 ADC Power Monitor C16 0.1uF_25V R193 1.43K_+1% R198 +2.5V_A 1K_+1% R198 For FAN connector For VGA connector For FAN connector For BMC KVM Keyboard/Mouse For System BIOS Flash For System BIOS AST2500/2520 Rev 1.5 DAC DACB DACG DACR GPIOJ4_VGAHS GPIOJ5_VGAVS GPIOJ6_DDCCLK GPIOJ7_DDCDAT V2 W2 BMC_FAN_PWM0 P3V3_BMC_USB2AV33_AUX FB1 120_100MH2_2A BLM18PG121SN1D C14 C15 4.7uF_6.3V C7 C7 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIW0 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GPIV8 ADC0_GIPO7_TACH15 ADC0_PWM7_VPIG7 USB2AV33 USB2AVRES USB2BVRES USB2A_DP USB2A_DN USB2B_DP USB2B_DN R2 T2 N3 N4 COM VIN_PWR_OK A19 E19 C19 CNBMC_I2C0_ALERT-L R186 0ohm_+5% COM I2C0_ALERT# BSS138LT1_200mA/50V Q53 1 COM PLTRST# COM THERMTRIP# R166 0ohm_+5% C2784 0.1uF_25V DNI SW-TACT-TS-AO2 AST2500A2-GP GPIOI4_SPIICSO_VBCS GPIOI5_SPIICK_VBCK GPIOI6_SPIIMOSI_VBMOSI GPIOI7_SPIIMISO_VBMISO System BIOS 3 OF 4 SYSTEM S PI System BIOS For BMC Reset +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.3V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A +3.6V_A + 4.7K_+1% R1013 4.7K_+1% BMC_THRMTRIP-L E17 CNBMC_I2C0_ALERT-L R186 0ohm_+5% COM I2C0_ALERT# BSS138LT1_200mA/50V Q53 1 COM PLTRST# COM THERMTRIP# R168 3.3K_+1% R171 10K_+1% C13 1uF_16V R171 10K_+1% AA17 AB18 PEICIVDD PECI NTRST TDI TMS TCK RTCK TDO GPIOG4_SGPS2CK_SALT1 GPIOG5_SGPS2LD_SALT2 GPIOG6_SGPS2IO_SGTIO GPIOG7_SGPS2IO_SGTIO GPIOG4_SGPS2CK_SALT1 GPIOG5_SGPS2LD_SALT2 GPIOG6_SGPS2IO_SGTIO GPIOG7_SGPS2IO_SGTIO GPIOG4_SGPS2IO_SGTIO GPIOG5_SGPS2IO_SGTIO GPIOG6_SGPS2IO_SGTIO GPIOG7_SGPS2IO_SGTIO GPIOG4_SGPS2IO_SGTIO GPIOG5_SGPS2IO_SGTIO GPIOG6_SGPS2IO_SGTIO GPIOG7_SGPS2IO_SGTIO GPIOG4_SGPS2IO_SGTIO GPIOG5_SGPS2IO_SGTIO GPIOG6_SGPS2IO_SGTIO GPIOG7_SGPS2IO_SGTIA S PI System BIOS 3 OF 4 SYSTEM BIOS For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS Flash For System BIOS FlashFor System BIOS Flash](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/ef1c192b9d1e8ceabddc379dbf49f2705c13f6d44227061e462994d2717f50a1.jpg) # 3.19. General Purpose SPI The COM-HPC General Purpose SPI port is, from a hardware view, an easy to use interface for Carrier peripherals that requires only four signal pins on the peripheral device (data in, data out, clock and chip select), plus an optional interrupt output. It may be used to implement a wide variety of low to medium speed (circa 4 to 20 MHz signaling rate) peripheral devices such as A/D and D/A converters, touch controllers, CPLDs, FPGAs, Flash memories and many more. The GP SPI interface is significantly faster than traditional I2C ports (400 KHz max for most I2C implementations) but much slower than PCI Express (2.5 GHz signaling and up). A SPI interface is easier to implement within a peripheral device than PCIe, resulting in lower costs. The COM-HPC pinout definitions allow for four General Purpose SPI chip selects, allowing up to four Carrier GP SPI devices. The COM-HPC GP SPI interface uses 3.3V signal levels, active in the S0 (full on) power state. Carrier GP SPI devices may be daisy-chained or routed in a branch topology with the root at the COM-HPC connector. The data in, data out and clock lines for a particular target device on the Carrier should be loosely kept together and have approximately the same length from the COM-HPC connector to the particular target device. The chip-select lines should be routed directly from the COM-HPC connector to the target device. Note: the COM-HPC Mini General Purpose SPI signals are 1.8V level signals. # 3.20. Rapid Shutdown Rapid Shutdown is a rarely used feature but one that is important to some defense industry segment customers. It’s purpose is to rapidly collapse all Module and Carrier power rails and remove all bias voltages to prevent damage to the electronics in certain extreme wartime situations. It is purely a hardware feature, without any consideration for an orderly software shutdown. It is expected that some COM-HPC Module designs will incorporate Rapid Shutdown capability, but that the feature be depopulated unless needed by certain customers. The feature is both fairly simple in concept but potentially tricky in implementation: if the Module Rapid Shutdown pin is asserted by a 5V logic level signal, all power Module and Carrier rails are collapsed by a N-channel FET and appropriately sized drain resistor on each power rail. The +12V or Wide Range power source to the system must be immediately cut as well, and isolated from any bulk capacitance that might provide hold-up power. This usually is achieved by using hotswap controller devices to gate the system power input, with the bulk hold-up capacitance located at the input side of the hot-swap controller circuitry. All power rails on the Carrier must be collapsed as well. Design drawings are not shown here. If your Module vendor supports Rapid Shutdown, then they should be able to provide implementation design support. # 3.21. Thermal Protection COM-HPC defines two pins related to thermal protection of the system: # CARRIER\_HOT# ◦ This is a 3.3V (1.8V on the Mini) level S0 power domain input signal, with an on-Module pull-up ◦ This signal may be left open, or it may be driven low by Carrier hardware if a system over-temperature situation is detected. ◦ Module support for this signal is required, per the COM-HPC Base Specification. ◦ There is no definition in the COM-HPC Base Specification as to how long CARRIER\_HOT# should stay low in a system over-temperature situation # THERMTRIP# ◦ This is a 3.3V (1.8V on the Mini) level S0 power domain output ◦ If driven low, it indicates that the CPU is in an over-temperature situation ◦ There is no definition in the COM-HPC Base Specification as to how long THERMTRIP# should stay low in an over-temperature situation ◦ Carriers may leave this signal open, or they may act on it Ideally, a Carrier circuit removes system S0 power if the situation persists and is not a short term glitch, and sets a bit in a non-volatile memory that can be read by Module firmware on the next S0 power up. ▪ A Carrier BMC may also track / process this COM-HPC output signal # 3.22. System Management Bus (SMBus) # SMBus Introduction The SMBus is primarily used to manage system peripherals on the COM-HPC Module and on the Carrier. SMBus devices such as the Serial Presence Detect (SPD) EEPROM(s) for the system RAM, thermal sensors, PCIe devices, clock buffers, Smart Battery, etc. are managed over the SMBus. Designers need to take note of several implementation issues to ensure reliable SMBus interface operation. The SMBus is derived from I2C. However, I2C devices have the potential to lock up the data line while sending information and require a power cycle to clear the fault condition. SMBus devices contain a timeout to monitor for and correct this condition. Designers are urged to use SMBus devices when possible over standard I2C devices. COM-HPC Modules are required to power SMBus devices from the suspend power rail in order to have control in all system power states. The COM-HPC Module may not function correctly or at all if Carrier SMBus devices interfere with proper Module SMBus device operation. Note: the SMBus signals on the Mini are all 1.8V level signals. # SMBus Power Domain Isolation The devices on the Carrier Board using the SMBus are usually powered by the main 3.3V (S0) power rail. To avoid current leakage between the suspend (S5) and the main (S0) power rails, the SMBus devices in the S5 power domain must be separated by a bus switch from S0 domain SMBus devices. FET devices, as shown in Figure 50 above, or I2C / SMBus isolation devices, as shown in Table 20 above may be used to achieve the S5 / S0 power domain isolation. # SMBus Addresses Since the SMBus is used by the Module and Carrier, care must be taken to ensure that Carrier based devices do not overlap the address space of Module based devices. Typical Module SMBus devices and their binary I2C / SMBus addresses include memory SPD (Serial Presence Detect) addresses 1010 000x, 1010 001x, up to 1010 111x for 8 DIMMs, programmable clock synthesizers (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor defined address). The ‘x’ in the binary addresses is the SMBus / I2C R/W bit. Contact your Module vendor for information on the SMBus addresses used on the Module. # 3.23. General Purpose Inputs / Outputs COM-HPC defines 12 General Purpose I/O pins. It is expected that the 12 pins can be individually configured as either inputs or outputs, that they be configured as inputs on power up, that they be powered by the Module 3.3V suspend (S5) power rail, that there be a 100K pull-up on the Module, and that the Module GPIO pins be able to generate interrupts to the Module CPU. As the COM-HPC GPIO may be inputs, outputs or bidirectional signals, there are a variety of ways to use and protect them. If the target I/O devices are in a different power domain from (I.e targets are in the S0 domain), that needs to be taken into account by an appropriate logic buffer or FET arrangement, similar to the S5 – S0 power domain isolation shown in this document for I2C and the SMBus. If any of the GPIO signals are exposed to the outside world and exposed to human contact and ESD events, then there needs to be appropriate ESD protection, EMI mitigation, and hardening against accidents such as short circuiting or exposure to power rails. The details of the protection implemented depend on the factors such as: What level of ESD protection is expected? What is the GPIO signal bandwidth? ◦ Low bandwidth GPIO signals may be protected with simple measures including: ▪ Dual Schottky diodes: 1st diode with anode (A) at GND and cathode (K) at the GPIO signal level • 2nd diode with anode at GPIO signal level and cathode at the GPIO VCC level Alternatives to the dual Schottky diodes proposed above may be specialty diodes or diode arrays designed for ESD mitigation such as those shown in the NBASE-T, Ethernet, USB, DP and HDMI sections of this document. ▪ A series resistor between the Schottky diode K – A node and the COM-HPC GPIO pinout ▪ Possibly a ferrite in between the COM-HPC GPIO pin and the external connector ◦ If the GPIO signal bandwidth is somewhat higher, then adjustments have to be made: ▪ The ESD diode pin capacitance needs to be lower, and appropriately sized for the bandwidth at hand ▪ The series resistor value needs to be lowered ▪ The ferrite inductance value may need adjustment • If user abuse is expected (hot plugging, sudden removal etc) then protection measures may include: 。 Some or all of the protection measures listed just above ◦ Robust buffer ICs that stand between the COM-HPC pins and the protection measures ▪ If the GPIO is to be used as a single direction input or output, then robust buffering is easy ▪ Many bidirectional buffers are available, including buffers that auto-sense the signal direction Note: the GPIO signals on the Mini are all 1.8V level signals. # 3.24. Module Type Detection and Protection There are three TYPE pins defined in the COM-HPC pinouts allowing up to eight Types to be defined. At present, four Types are defined, per Table 21 below: Table 21: COM-HPC Type Definitions
Module ConnectionsMeaning
RefTYPE2TYPE1TYPE0
7NCNCNCMini Module – Wide Range 8V to 20V input
6NCNCGNDReserved
5NCGNDNCReserved
4NCGNDGNDServer Module – Fixed 12V input
3GNDNCNCReserved
2GNDNCGNDReserved
1GNDGNDNCClient Module – Wide Range 8V to 20V input
0GNDGNDGNDClient Module – Fixed 12V input
COM-HPC Carrier hardware may optionally implement hardware to hold off the application of power to the main Carrier circuits and to the Module if the Module and Carrier Types do not match up. The COM-HPC Client and Server pinouts are different (the differences are noted in Table 2 earlier in this document) and it is not desirable to power up a system in which the Carrier and Module Types do not match. The Carrier hardware shown in Figure 55 below holds off power distribution if the Module Type is not a fixed input voltage Client or a wide-range input Client. The example uses and ATX style power supply. The 5V Standby power to the Carrier and Module is cut off by power switch U60 in the Figure 55 below. The open drain FET T1 along with pull-down resistor R539 ensure that the ATX power control line (ATX\_PSON#) is floating and not pulled low. This prevents the main ATX power rails from coming on. FET T1 should not be replaced by a logic gate as the gate’s internal ESD protection diodes might provide a path for the ATX\_PSON# signal to be pulled low unintentionally. Figure 55: Module Type Detection / Protection – ATX Power Supply and Client Type Module / Carrier ![R534 100k 0402 R535 100k 0402 C703 100n 0402 25V +5V_SBY_ATX C704 1u0 0603 16V U59 1 2 3 4 SN74LVC1G02 S BY_EN_LSW R536 100k 0402 U60 1 2 4 3 ON PAD PGND 8 7 6 5 TPS22975 C706 22u 1206 16V VCC_5V_SBY SBY_LSW_CT TYPE0 not evaluated. Carrier with ATX PSU supports 'Fixed 12V' and 'Wide Range' Modules TYPE1 COM COM TYPE2](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/f4e5ca02367186e2f18efb6d66c7c9f03257bfd688f37288d5c6e5276eec36fc.jpg) ![SUS_S3# COM R539 100k 0402 1 3 T1 2N7002A 2 ATX_PSON#](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/1e4a4494ae776f60a16b0a464f20eb94609487f4ad8cbbd0b42bfb8409aa73b5.jpg) The Carrier hardware shown in Figure 56 below holds off power distribution if the Module Type is not a Server Type Module. The example uses and AT style supply. Figure 56: Module Type Detection / Protection – AT Power Supply and Server Type Module / Carrier ![+VCC_IN U62 IN OUT 5 +3.3V_initial C707 1u0 0805 25V EN GND NC LDK320M33R C708 1u0 0402 10V +3.3V_initial R534 100k 0402 R535 100k 0402 C703 100n 0402 25V +3.3V_initial SN74LVC1G02 U59 5 C709 100n 0402 25V SN74LVC1G02 U61 5 C712 22u 1206 25V +VCC_IN U63 VIN Vout 2 VIN Vout 3 VCC OCP 9 EN PG 7 NC1 SR 6 NC5 VSS SR_VCC C711 100n 0402 25V rise time ~12ms](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/a96ecff1b17a89e83d9f69d09844afdb535b6c61517e3a0b33d70b19c85b4ae1.jpg) 5 4 3 2 1Server Modules may use either AT or ATX or other style power supplies. An AT supply is used here just as an example. The circuit example below prevents the application of power to the COM-HPC Mini if the Module and Carrier Type pins do not match up. Figure 57: Module Type Detection / Protection – COM-HPC Mini Module ![The image displays a schematic diagram divided into three sections: **Top Section:** * **U62 (LDK320M33R):** A voltage regulator. * **Pin 1 (IN)** and **Pin 3 (EN)** are connected to **+VCC_IN**. * **Pin 2 (GND)** is grounded. * **Pin 4 (NC)** is unconnected (crossed out). * **Pin 5 (OUT)** connects to **+3.3V_initial**. * **C707:** Labeled **1u0 0805 25V**, connected between +VCC_IN and ground. * **C708:** Labeled **1u0 0402 10V**, connected between +3.3V_initial and ground. **Middle Section:** * **Power Rail:** **+3.3V_initial** powers the logic circuit. * **C703:** Labeled **100n 0402 25V**, connected between +3.3V_initial and ground. * **C709:** Labeled **100n 0402 25V**, connected between +3.3V_initial and ground. * **U59 (NC7SZ08):** An AND gate. * **Pin 5 (VCC)** connected to +3.3V_initial. * **Pin 3 (GND)** grounded. * **Resistors R534** and **R535** (both **100k 0402**) are connected in parallel between +3.3V_initial and a common node. This node connects to **Pin 1 (A)** and **Pin 2 (B)** of U59. * The common node also connects to terminals **TYPE1 COM** and **TYPE0 COM**. * **Pin 4 (Y)** output connects to Pin 1 (A) of U61. * **U61 (NC7SZ08):** An AND gate. * **Pin 5 (VCC)** connected to +3.3V_initial. * **Pin 3 (GND)** grounded. * **Pin 1 (A)** connected to Pin 4 (Y) of U59. * **Resistor R537** (**100k 0402**) connects +3.3V_initial to **Pin 2 (B)**. * **Pin 2 (B)** also connects to terminal **TYPE2 COM**. * **Pin 4 (Y)** output connects to **LSW_EN**. * **Resistor R58** (**100k 0402**) connects LSW_EN to ground. **Bottom Section:** * **U63 (NCP45750):** A power management IC. * **Pin 12 (VIN)** and **Pin 13 (VIN)** connect to **+VCC_IN**. * **C712:** Labeled **22u 1206 25V**, connected between +VCC_IN and ground. * **Pin 10 (VCC)** connects to **+3.3V_initial**. * **C710:** Labeled **1u0 0402 10V**, connected between +3.3V_initial and ground. * **Pin 11 (EN)** connects to **LSW_EN**. * **Pin 1 (NC1)** and **Pin 5 (NC5)** are unconnected. * **Pin 6 (VSS)** is grounded. * **Pins 2 (Vout), 3 (Vout), 4 (Vout)** are connected together to a node labeled **VCC**. Text next to it reads 'to COM-HPC Mini module'. * **Pins 7 (SR), 8 (PG), 9 (OCP)** are connected together. This node is labeled **SR VCC**. * **C711:** Labeled **100n 0402 25V**, connected between the SR/PG/OCP node and ground. Text below reads 'rise time ~12ms'.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/b264b20752bca82caf644227b7593e07ae15ce5eef2672b65de9193a376da843.jpg) # 3.25. COM-HPC Mini SGMII Ethernet Interface Example Revision 1.20 of the COM-HPC Base Specification document allows for two SGMII port options. They are pin shared with COM-HPC Mini PCIe lanes 3 and 2. See the Base Specification document Section 10 for details. A circuit example for a 10/100/1000 TSN aware Ethernet implementation is shown here. Note that the SGMII TX and RX pairs require series coupling capacitors on the Carrier; they are not present on the COM-HPC Mini Module. The Mini also has an MDIO pin pair (essentially an I2C bus) available to set up the PHY. Figure 58: COM-HPC Mini SGMII Gbps Ethernet Example ![This image is an electronic schematic containing several integrated circuits, passive components, and a connector. **U1 (DP83867CSRGZR)** is the central component. * **Left Pins:** Connected to power rails (V_1V8_LAN, V_2V5_LAN, V_1V0_LAN), GTX_CLK, TX_EN/TX_CTRL, SGMII0_TX- (COM), SGMII0_TX+ (COM), RX_CTRL, SGMII0_RX- (COM), SGMII0_RX+ (COM), COL/GPIO1, and RBIAS (connected to a 1K resistor to ground). * **Right Pins:** Connected to MDI lines (MDI_DP0, MDI_DN0 through MDI_DP3, MDI_DN3), JTAG interface (JTAG_TDI, JTAG_TDO, JTAG_TCK, JTAG_TMS), LEDs (LED0, LED1, LED2), MDC, MDIO (with COM label, ETH_MDIO_CLK, ETH_MDIO_DAT), CLK_OUT (via 10K and 2.2K resistors to DNI and V_1V8_LAN), INT/PWDN, PHY RESET#, XI, XO, and PAD (grounded). **CN1** is a connector with pins 1 through 10. * Pins connect to MDI lines. * Includes transformers, capacitors (100n, 100n, 100pF), and a 2K resistor. * Label 'SHIELD' indicates the shield connection. **U3 (NC7SZ125M5X)** is a buffer/inverter IC. * Pins 1 (OE#), 2 (A), 3 (GND), 4 (Y), 5 (VCC). * Connected to PLTRST# (COM), PHY_RESET#, and V_1V8_LAN. * Capacitor 100n 25V connected to VCC. **U2 (74LVC3G06FT,115)** is an inverting buffer IC. * Pins 1 (1A), 3 (2A), 2 (3A), 7 (1Y), 5 (2Y), 4 (GND), 6 (VCC). * Inputs connect to LED0, LED1, LED2. * Outputs connect to LED0_G 100#, LED1_Y 1000#, LED2_G_ACT#. * LEDs D1, D2, D3 are connected to the outputs and resistors (499 ohms) to V_3V3. * Capacitor 100n 25V connected to VCC. **Y1** is a crystal oscillator. * Pins 1, 2, 3, 4. * Connected to XTAL1 and XTAL2. * Capacitors 18p connect pins 2 and 4 to ground. * Resistor R11 (1M) connects XTAL1 to ground. * Labels 50V and 25M are near the crystal. **Passive Components & Other Connections:** * **Straps:** A section labeled 'Straps' shows resistors (5.76K, 2.49K) connecting to lines labeled RX_CTRL, LED0, RX_D0, RX_D1, and DNI. * **Reset Circuit:** Resistors (2.2K, 2.2K, 100) and a capacitor (1n, 25V) form a reset circuit for PHY_RESET#. * **JTAG:** Pull-up resistors (2.2K) connect JTAG_TDI, JTAG_TDO, JTAG_TCK to V_1V8_LAN. * **FB1, FB2, FB3:** Three inductors (BLM18KG700TN1) labeled FB1, FB2, FB3. * FB1 connects V_1V8 to V_1V8_LAN. * FB2 connects V_2V5 to V_2V5_LAN. * FB3 connects V_1V0 to V_1V0_LAN. * Each is accompanied by a series of capacitors (22u, 100n, 1u, 1u) and voltage labels (6.3V, 25V, 10V).](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/eafe350d0338bd8b6a550191c7f01586b9943a972555b111a4471b43e950c3a7.jpg) Note: this schematic example is borrowed and adapted from the SGET SMARC Design Guide, with permission. # 4. PCB Design Rule Summaries # 4.1. High Speed PCB Design Information – Design Guides and Books # 4.1.1. Intel and AMD Design Guides Intel and AMD have a wealth of design guide material available, although most current materials are NDA (Non Disclosure Agreement) protected and Carrier designers must obtain their own NDAs with these vendors to access these documents. A few useful documents are listed in Table 22 below. Although these guides are centered around CPU board development there is also much general high speed design information, often in graphical format, about topics such as how to keep differential pairs length matched, about stackups, about via stubs, about voiding planes under certain components and features, and so on. There is also information about peripheral interfaces such as PCIe, USB 3 and 4 etc. Note for the COM-HPC Mini: the high speed rules shown here for USB Super Speed, PCIe, SATA etc apply to the Mini as well the COM-HPC Client and Server. The differences between the COM-HPC Client, Server and the Mini have mainly to do with the I/O voltage levels of the single ended sideband signals such as the SM buses, I2C buses etc. and the pinout choices. Table 22: Intel and AMD Design Guides
VendorDoc #Description / TitleNotes
AMD5515Socket SP3 Processor Mother Board DGSome general high speed PCB design infoFiber weave effect informationPCIe Gen 3 and 4 information
Intel576513Intel ConfidentialSome general high speed PCB design infoPCB differential pair length matching techniquesPCIe Gen 3 and 4 informationUSB 3.1Ethernet KR 10G/25G information
Intel607872Tiger Lake UP3 UP4 Platform DGFiber weave effect informationPCIe Gen 3 and 4 length matching informationUSB4 routing information
Intel618429Tiger Lake H Platform DG
Intel627205Intel ConfidentialFiber weave effect informationNo stub routing techniquesVoiding advicePCIe Gen 4 and Gen 5 advice
Intel406926Fiberweave Effect White Paper
# 4.1.2. Books on High Speed PCB Design Principles The publications listed below are much more academic than the design guides listed in Section Error: Reference source not found above. These books may be useful to designers interested in the engineering and physics details of what is going on with very fast signal propagation. The book titled High Speed Digital Design: Design Of High Speed Interconnects And Signaling is the newest and perhaps most relevant book in this list. It was written by a trio of Intel engineers and covers contemporary high speed serial interface topics quite thoroughly. Advanced Signal Integrity For High-Speed Digital Designs Stephen H.; Heck and Howard L Hall ISBN 13: 9780470192351 ISBN 10: 0470192356 © 2009 Wiley-IEEE Press High Speed Digital Design: Design Of High Speed Interconnects And Signaling Hanqiao Zhang, Steven Krooswyk and Jeffrey Ou © 2015 Morgan Kaufman, Elsevier Inc. ISBN: 978-0-12-418663-7 High-Speed Signal Propagation – Advanced Black Magic Howard Johnson and Martin Graham © 2003 Pearson Education, Prentice Hall Professional Technical Reference Right the First Time – A Practical Handbook on High Speed PCB and System Design Volumes 1 and 2 Lee W. Ritchey ©2006 Speeding Edge Signal Integrity Issues and Printed Circuit Board Design Douglas Brooks ©2003 Pearson Education, Prentice Hall Professional Technical Reference # 4.2. High Speed Serial Interfaces – General PCB Design Rules Figure 59: PCB Cross Section Terms and Notations ![Diff Pair - Surface Plane Microstrip Symmetric Stripline Asymmetric Stripline T W S W D H2 H1 or H DX Diff Pair Other Periodic Signal Dual Stripline or Dual Asymmetric Stripline](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/13c921c8180c9e2f5019e4b90dadee397576a339d4d0aa555a452dea3923b590.jpg) Some of the terms and notations in the Figure 59 above are used in the Tables and text on the following pages. The long copper colored thin rectangles represent the GND or PWR planes and the smaller rectangles, for the most part, the edge coupled differential pairs. The upper and lower signal layers within a Dual Stripline structure should be routed orthogonally to each other to minimize coupling and thereby crosstalk. Table 23: General Design Rules for High Speed Serial interfaces
RefRule / Recommendation
1High speed pairs should be routed as edge-coupled differential pairs referenced to and closely coupled to an unbroken GND plane.
2High speed pairs with Nyquist frequencies at 4 GHz or more (PCIe Gen 3,4,5, USB 3.2 Gen2, USB4 Gen 3, DisplayPort, eDP, HDMI, Ethernet KR) require the most PCB routing care.
3The preferred routing environments for high speed pairs are ranked here, from most desirable to least:1. Symmetric Stripline routing with clean GND planes above and below gives the best signal integrity, but it is often an impractical luxury. The two GND planes should be periodically tied together with stitching vias, every inch or so in both X and Y.2. Asymmetric Stripline routing with the differential pair traces close the primary reference plane, an unbroken GND plane, and further from the secondary plane. The secondary plane can be a GND plane (preferred) or a power plane, possibly with plane splits.3. Asymmetric Dual Stripline routing with high speed pairs close to the primary reference plane, a GND plane. The traces on the “other” routing layer should be as far away as possible and be routed orthogonally to the GND referenced high speed pairs. The “other” traces can be high speed pairs as well, if their primary reference plane is also GND and if the two signal layers are orthogonal. If the routes on the Asymmetric Dual Stripline routing layers are not be truly orthogonal (90 degrees) they should be angled at least 30 degrees relative to each other.4. Microstrip routing.
4Use as few vias as possible. What few vias there are should be symmetrically placed, such that the + and - lines in the pair “see” the same obstacles and impedance discontinuities.If there is a reference plane change, there must be a stitching via close to the signal via. If the planes are at the same potential (e.g. both GND), direct (DC coupled) stitching vias are used. If the reference planes are at different potentials (not desirable for high speed pairs) then a stitching capacitor is used near the signal vias. These concepts are illustrated in some of the Design Guides referenced in Table 22 above.
5The higher speed interfaces may need no-stub vias or very short stub vias. This may mean backdrilling the vias with controlled depth drills to hollow out the unused portion of the via barrel. Alternatively, via structures that are built up or are laser drilled and only transit a limited number of layers (say from Layer 1 to Layer 3, with Layer 2 being a GND plane) may be used.Another strategy to avoid via stubs is to arrange that the vias connect layers on opposite sides of the PCB. Then there is no stub (for outer layer to outer layer) or perhaps a shorter stub.Yet another strategy is to use sequential lamination PCB construction. For example, a 12 layer PCB can be built as two 6 layer PCBs and then laminated together to form a 12 layer PCB, with short vias spanning layers1-6 and layers 7-12 and longer vias spanning layers 1-12.
6If layer transitions must be done, having the high speed signals in question straddle a common GND plane is beneficial as there is no change in the reference layer. For example, if signal pairs are on Layer 1 and 3 and Layer 2 is GND, then there is no change in GND reference plane for the Layer 1 - 3 transitions.If the layer changes result in a change in GND reference planes, then there need to be GND stitching vias close to the trace vias. The stitching vias tie the GND planes together in the vicinity of the signal pair layer transition.
7It is critically important that the + and - signal lines in a differential pair are closely length matched. The matching is on the order of a few mils for the faster interfaces. This is sometimes called intra-pair length matching. In this document, this is referred to as differential pair + and - length matching. The different pairs in a group (e.g. the four TX+ and - pairs in x4 PCIe link) do not need to be matched very closely at all for many modern interfaces. This is sometimes called inter-pair length matching. In this document, it is referred to as pair to pair length matching (or similar). For some interfaces, this mismatch can be on the order of inches.
8Coupling capacitors should be discrete 0402 or 0201 package size parts. Do not use capacitor arrays as these can have internal cross coupling that can severely attenuate the differential signal.
9The plane under the coupling capacitors for the higher speed interfaces should be voided (meaning that rectangular holes about the same size as the capacitor lands, or slightly larger, should be created in the plane) - whether it is a GND or PWR plane. See the Intel Document 627205 referenced in Table 22 above for details.
10Plane layers that do NOT connect to a particular via should be voided with a circular void around the via barrel. This is done anyway so that the plated via hole does not connect to the plane, but the void should be expanded somewhat to avoid signal coupling to the plane. See the Intel Document 627205 referenced in Table 22 above for details.
11High speed traces should not be run close to the board edges, especially for long runs parallel to the edge. If they are run this way, they may be creating an EMI hazard.
12Sometimes the differential pairs are serpentine to adjust the pair length to match another pair. There is usually a “minimum distance to self”, listed in some of the Tables below.
13The fastest interfaces need to account for the “Fiberweave Effect”. This effect is due to the periodic variations in the PCB material dielectric constant caused by the fiberglass weave pattern within a PCB layer. The mitigation strategies are to either arrange that the PCB routes are not parallel (in x or y) to the glass fibers in the weave, or to use a PCB material that does not show this effect. Some of the references in Table 22 have details and illustrations on this effect.
# 4.3. PCB Design Rule Summaries – High Speed Differential Pair Serial Interfaces The COM-HPC high speed serial interfaces and two of the fastest single ended interfaces were extensively simulated by a Signal Integrity subgroup during the development of the COM-HPC specification. These efforts resulted in a set of loss budgets, maximum trace length values and other related recommendations. This is documented in Section 6 of the COM-HPC Base Specification. The loss-budget approach allows the findings to be adapted to various different PCB materials (e.g. Standard Loss, Mid Loss, Low Loss and Very Low Loss). The Base Specification recommendations as they apply to COM-HPC Carrier designs are summarized in the Sections below . Some recommendations such as trace length matching requirements are not found in the Base Specification document; rather they are compiled from industry sources. # 4.3.1. NBASE-T Design Rule Summary Table 24: NBASE-T Design Rule Summary
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist Frequency1000BASE-T: 250 Mbps / ~80 MHz10GBASE-T: 2.5 Gbps / ~450 MHz
2Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary referenceMicrostrip routing may be usedMicrostrip is necessary near connectorsQuiet unbroken well bypassed power plane may be used as a reference plane.
3Differential Trace Impedance100 ohm +/- 10%
4Single Ended Trace Impedance55 ohm +/- 15%
5Max Module Trace Length1GBASE-T STD Loss PCB Material: ≤ 3000 mils10GBASE-T STD Loss PCB Material: ≤ 1500 mils10GBASE-T MID Loss PCB Material: ≤ 1500 mils
6Max Carrier Trace Length1GBASE-T STD Loss PCB Material: ≤ 5000 mils10GBASE-T STD Loss PCB Material: ≤ 2500 mils10GBASE-T MID Loss PCB Material: ≤ 4500 mils
7Differential Pair +/- Length Matching (Carrier / Module)5 mil / 5 mil
8TX Pair to TX Pair Length Matching (Carrier / Module)500 mil / 500 mil
9RX Pair to RX Pair Length Matching (Carrier / Module)500 mil / 500 mil
10TX Pair to RX Pair Length Matching (Carrier / Module)500 mil / 500 mil
11TX Pair to RX Pair Spacing (Carrier / Module)D ≥ 5*H (Asymmetric Stripline)
12TX or RX pair Spacing to Other SignalsDX ≥ 8*H (Asymmetric Stripline)
13Max Via Stub Length80 mil
See Figure 59 above for definitions of D, DX and H. # 4.3.2. Ethernet KR Design Rule Summary Table 25: Ethernet KR Design Rule Summary
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist Frequency10G KR: 10.3125 Gtps / ~5.1 GHz25G KR: 25.78125 Gtps / ~12.9 GHz40G KR4: 10.3125 Gtps / ~5.1 GHz100G KR4: 25.78125 Gtps / ~12.9 GHz
2Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary reference
3Differential Trace Impedance93 ohm +/- 10%
4Single Ended Trace Impedance50 ohm +/- 15%
5Maximum Trace Lengths on Carrier (adapted from COM-HPC Base Specification V1.0 Tables 79, 81, 83)
PHY Down on CarrierCarrier Trace LengthsBudget(dB)Standard Loss (SL)PCB Material(inches)Mid Loss (ML)PCB Material(inches)Low Loss (LL)PCB Material(inches)Very Low Loss (VLL)PCB Material(inches)
10GBASE-KR16.013.221.027.437.3
25GBASE-KR RS-FEC20.07.912.916.523.1
25GBASE-KR BASE-RFEC16.06.310.313.218.5
25GBASE-KR No FEC12.04.77.89.913.8
Module1 MAC to Module2 MACCarrier Trace LengthsBudget(dB)Standard Loss (SL)PCB Material(inches)Mid Loss (ML)PCB Material(inches)Low Loss (LL)PCB Material(inches)Very Low Loss (VLL)PCB Material(inches)
10GBASE-KR12.09.915.720.528.0
25GBASE-KR RS-FEC12.04.77.89.913.8
25GBASE-KR BASE-RFEC8.03.25.26.69.2
25GBASE-KR No FEC3.01.21.92.53.5
SFP Connector on CarrierCarrierTrace LengthsBudget(dB)Standard Loss (SL)PCB Material(inches)Mid Loss (ML)PCB Material(inches)Low Loss (LL)PCB Material(inches)Very Low Loss (VLL)PCB Material(inches)
SFP+ Max Carrier Trace1.501.241.972.563.50
SFP28 Max Carrier Trace2.000.791.291.652.31
6Differential Pair +/- Length Matching (Carrier / Module)Note the very tight matching for 25GBASE-KRThis is actually relaxed from some Intel recommendations,per PICMG consultation with Intel2.5 mil / 2.5 mil for 10GBASE-KR1.5 mil / 1.5 mil for 25G BASE-KR
7TX Pair to Pair Length Matching (Carrier / Module)500 mil / 500 mil (KR4 only; N/A for KR)
8RX Pair to Pair Length Matching (Carrier / Module)500 mil / 500 mil (KR4 only; N/A for KR)
9TX Pair to RX Pair Length Matching (Carrier / Module)500 mil / 500 mil
10TX Pair to RX Pair Spacing (Carrier / Module)D ≥ 5*H (Asymmetric Stripline)
11TX or RX pair Spacing to Other SignalsDX ≥ 8*H (Asymmetric Stripline)
12Max Via Stub Length10 mil (KR and KR4)
# 4.3.3. SATA Design Rule Summary Table 26: SATA Design Rule Summary
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist FrequencyGen 1: 1.5 Gtps / 0.75 GHzGen 2: 3 Gtps / 1.5 GHzGen 3: 6 Gtps / 3 GHz
2Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary reference
3Differential Trace Impedance85 ohm +/- 10%
4Single Ended Trace Impedance45 ohm +/- 15%
5Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 58 and 60)
Device Up on M.2 or mSATA CardBudget dBStandard Loss (SL) PCB Material InchesMid Loss (ML) PCB Material InchesLow Loss (LL) PCB Material InchesVery Low Loss (VLL) PCB Material Inches
SATA Gen1 Carrier Trace1.14.076.888.469.17
SATA Gen2 Carrier Trace1.83.916.558.1410.11
SATA Gen3 Carrier Trace2.93.746.037.8010.21
Cabled InterfaceBudget dBStandard Loss (SL) PCB Material InchesMid Loss (ML) PCB Material InchesLow Loss (LL) PCB Material InchesVery Low Loss (VLL) PCB Material Inches
SATA Gen1 Carrier Trace0.72.594.385.385.83
SATA Gen2 Carrier Trace1.12.394.004.986.18
SATA Gen3 Carrier Trace1.82.323.744.846.34
6Differential Pair +/- Length Matching (Carrier / Module)2.5 mil / 2.5 mil to support SATA Gen 3
7TX Pair to RX Pair Length Matching (Carrier / Module)No requirement
8TX Pair to RX Pair Spacing (Carrier / Module)D ≥ 5*H (Asymmetric Stripline)
9TX or RX pair Spacing to Other SignalsDX ≥ 8*H (Asymmetric Stripline)
10Max Via Stub Length80 mil
# 4.3.4. PCIe Design Rule Summary Table 27: PCIe Design Rule Summary
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist FrequencyGen 3: 8 Gtps / 4 GHzGen 4: 16 Gtps / 8 GHzGen 5: 32 Gtps / 16 GHz
2Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary reference
3Differential Trace Impedance (PCIe data and Ref CLK pairs)85 ohm +/- 10%
4Single Ended Trace Impedance45 ohm +/- 15%
5Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 52 and 54)
Device DownBudget (dB)Standard Loss (SL)PCB Material(inches)Mid Loss (ML)PCB Material(inches)Low Loss (LL)PCB Material(inches)Very Low Loss (VLL)PCB Material(inches)
Gen 3 Max Carrier Trace11.0010.3715.6520.1626.68
Gen 4 Max Carrier Trace12.507.1110.7713.4417.64
Gen 5 Max Carrier Trace13.004.236.868.9712.65
Device UpBudget (dB)Standard Loss (SL)PCB Material(inches)Mid Loss (ML)PCB Material(inches)Low Loss (LL)PCB Material(inches)Very Low Loss (VLL)PCB Material(inches)
Gen 3 Max Carrier Trace6.506.139.2511.9115.77
Gen 4 Max Carrier Trace7.504.266.468.0610.58
Gen 5 Max Carrier Trace8.002.604.225.527.78
6Differential Pair +/- Length Matching (Carrier / Module)Gen 3, 4, 5: ≤ 2.5 mil / 2.5 mil
7TX Pair to TX Pair Length Matching (Carrier / Module)RX Pair to RX Pair Length Matching (Carrier / Module)Gen 3, 4, 5: ≤ 500 mil / 500 mil
8TX Pair to RX Pair Length Matching (Carrier / Module)No TX to RX matching required
9TX Pair to RX Pair SpacingGen 3, 4, 5: D ≥ 5H
10TX or RX pair Spacing to Other SignalsGen 3, 4, 5: DX ≥ 8H
11PCIe Data Pair Distance to SelfGen 3, 4, 5: D ≥ 3W
12PCIe RX or TX Data Pair Length relative to PCIe ReferenceClock Pair LengthNo matching required. The Reference ClockPairs should be routed as directly as possible.
13Maximum Via Stub Lengths:Gen 3: ≤ 80 milGen 4: ≤ 30 milGen 5: ≤ 10 mil
14Land Pattern and Via Voiding Recommendations:Gen 3, 4, 5: planes adjacent to component landsshould be voided. All layers that a PCIe couplingvia passes through should be voided, unless thevia connects on that layer. See the IntelDocument 627205 referenced in Table 22 abovefor illustrations on voiding and length matching.
15Fiberweave Effect MitigationSee Fiberweave Effect references in Table 22above. Alternatively, use a PCB material thatdoes not exhibit this effect.
# 4.3.5. USB 2.0 Design Rule Summary Table 28: USB 2.0 Design Rule Summary
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist Frequency480 Mbps / 240 MHz (USB 2.0 High Speed)
2PCB Routing EnvironmentAsymmetric Stripline is bestMicrostrip may be usedUnbroken GND plane primary reference is bestQuiet PWR plane may be used as a referencePlane splits should be avoidedIf plane splits are unavoidable, stitching capacitors should be used to tie the plane regions together, for AC signals
3Differential Trace Impedance (USB 2.0 data pair)90 ohm +/- 10%
4Single Ended Trace ImpedanceCirca 45 to 50 ohm
5Max Carrier Trace LengthCabled Interface: 14 inchesDevice Down on Carrier: 28 inches
6Differential Pair +/- Length Matching (Carrier / Module)20 mil / 20 mil
7Pair Spacing to other USB 2.0 Pairs (Carrier / Module)D ≥ 5*H (Asymmetric Stripline)
8TX or RX pair Spacing to Other SignalsDX ≥ 8*H (Asymmetric Stripline)
9Max Via Stub Length80 mil
# 4.3.6. USB 3.2 and USB4 Design Rule Summaries Table 29: USB 3.2 and USB4 Design Rule Summaries
RefParameter DescriptionParameter Value
1Signaling Rate / Nyquist FrequencyUSB 3.2 Gen 1: 5 Gtps / 2.5 GHzUSB 3.2 Gen 2: 10 Gtps / 5 GHzUSB4 Gen 2: 10 Gtps / 5 GHzUSB4 Gen 3: 20 Gtps / 10 GHz
2Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary reference
3Differential Trace Impedance (USB SuperSpeed Pairs)USB 3.2 Gen 1: Historically was 90 ohmGoing forward, 85 ohm is OKUSB 3.2 Gen 2: 85 ohm +/- 10%USB4 Gen 2: 85 ohm +/- 10%USB4 Gen 3: 85 ohm +/- 10%
4Single Ended Trace Impedance45 ohm +/- 15%
5Maximum Carrier Trace Lengths (from COM-HPC Base Specification V1.0 Tables 67 and 69)
USB SuperSpeed Device DownBudget (dB)Standard Loss (SL) PCB Material (Inches)Mid Loss (ML) PCB Material (Inches)Low Loss (LL) PCB Material (Inches)Very Low Loss (VLL) PCB Material (Inches)
USB 3.2 Gen 13.24.77.61012.8
USB 3.2 Gen25.54.77.69.813.4
USB4 Gen 25.54.77.69.813.4
USB4 Gen 310.55.27.610.715
USB SuperSpeed Cabled InterfaceBudget (dB)Standard Loss (SL) PCB Material (Inches)Mid Loss (ML) PCB Material (Inches)Low Loss (LL) PCB Material (Inches)Very Low Loss (VLL) PCB Material (Inches)
USB 3.2 Gen 13.24.77.61012.8
USB 3.2 Gen 25.54.77.59.813.4
USB4 Gen 25.54.77.59.813.4
USB4 Gen 310.5NANANANA
The values marked in red in the Table just above indicate that there is insufficient overall margin for a direct cabled interface with USB 3.2 Gen 2 or USB4 Gen 2 or USB4 Gen 3. Redrivers or retimers placed close to the cable connectors are advised. The Carrier maximum trace lengths in the Device Down Table above may be used for the run between the COM-HPC Module and the redrivers or retimers.
6Differential Pair +/- Length Matching (Carrier / Module)≤ 2.5 mil / 2.5 mil
7TX Pair to TX Pair Length Matching (Carrier / Module)RX Pair to RX Pair Length Matching (Carrier / Module)≤ 100 mil / 100 milApplies only to x2 configurations(2 TX pairs and 2 RX pairs)
8TX Pair to RX Pair Length Matching (Carrier / Module)≤ 100 mil / 100 mil
9TX Pair to RX Pair SpacingD ≥ 5H
10TX or RX pair Spacing to Other SignalsDX ≥ 8H
11TX or RX Data Pair Distance to Self
13Maximum Via Stub Lengths:USB 3.2 Gen 1 ≤ 80 milUSB 3.2 Gen 2 ≤ 30 milUSB4 Gen 2 ≤ 30 milUSB4 Gen 3 ≤ 10 mil
RefParameter DescriptionParameter Value
14Land Pattern and Via Voiding Recommendations:Gen 3, 4, 5: planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.
15Fiberweave Effect MitigationSee Fiberweave Effect references in Table 22 above. Alternatively, use a PCB material that does not exhibit this effect.
# 4.3.7. DisplayPort Design Rule Summary Table 30: DisplayPort Design Rule Summary
RefParameter DescriptionParameter Value
1Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary referenceMicrostrip is necessary in region near DP connector
2Differential Trace Impedance85 ohm +/- 10%
3Single Ended Trace Impedance45 ohm +/- 15%
4Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Tables 86 and 87)
DisplayPort Cabled Interfaces No Carrier RedriverBit Rate / Nyquist (per Lane) Gbps / GHzStandard Loss PCB Material inchesMid Loss PCB Material inchesLow Loss PCB Material inchesVery Low Loss PCB Material inches
DP HBR2.7 / 1.33.25.46.78.3
DP HBR25.4 / 2.72.94.66.07.8
DP HBR38.1 / 4.02.33.64.76.3
DP UHBR1010 / 5.01.652.63.44.6
DP UHBR13.513.5 / 6.71.83.03.85.3
DP UHBR2020 / 101.32.22.83.8
DisplayPort With Carrier Retimer/RedriverBit Rate / Nyquist (per Lane) Gbps / GHzStandard Loss PCB Material inchesMid Loss PCB Material inchesLow Loss PCB Material inchesVery Low Loss PCB Material inches
DP2.0 UHBR13.513.5 / 6.75810.414.4
DP2.0 UHBR2020 / 103.767.610.7
Red text in upper table above indicates that there is insufficient margin in the overall channel and that particular configuration should not be used.
5Differential Pair +/- Length Matching (Carrier / Module)≤ 2.5 mil / 2.5 mil
6Data Pair to Pair Length Matching (Carrier / Module)≤ 100 mil / 100 mil
7Pair to Pair SpacingD ≥ 5H
8TX or RX pair Spacing to Other SignalsDX ≥ 8H
9TX or RX Data Pair Distance to Self
10Maximum Via Stub Lengths:80 mil (per lane bit rate ≤ 5.4 Gtps)30 mil (per lane bit rate ≤ 13.5 Gtps)10 mil (per lane bit rate 20 Gtps)
11Land Pattern and Via Voiding Recommendations:For DP modes with bit-rate at or above 8 Gtps per lane:Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.
# 4.3.8. eDP Design Rule Summary Embedded DisplayPort signal integrity considerations were not explicitly addressed by the COM-HPC Signal Integrity subgroup. As such, it would be reasonable for COM-HPC Carrier designers to use the COM-HPC DisplayPort Design Rule Summary outlined in Section 4.3.7. for eDP layouts. For eDP panels, only the lower bit rate formats (HBR, HBR2, HBR3) are likely to come into play. Alternatively, Carrier Designers can consult some of the Intel and AMD Design Guides listed in Table 22 above for eDP guidance. The Intel Document 627205 in particular has lots of eDP advice. However, these Design Guides are targeting laptop and motherboard designs and it can be tricky to map these recommendations to the COM-HPC system case. The general rule of thumb is that about half of the motherboard or laptop board budget goes to the COM-HPC Module and half to the COM-HPC Carrier. # 4.3.9. HDMI Design Rule Summary Table 31: HDMI Design Rule Summary
RefParameter DescriptionParameter Value
1Preferred PCB Routing EnvironmentAsymmetric StriplineUnbroken GND plane primary referenceMicrostrip may necessary in the region near the HDMI connector
2Differential Trace Impedance85 ohm +/- 10% (on Carrier before HDMI buffer)100 ohm +/- 10% (after buffer)
3Single Ended Trace Impedance45 ohm +/- 15% (before buffer)55 ohm +/- 15% (after buffer)
4Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Table 88)
HDMI Buffer / Driver on Carrier near HDMI ConnectorBit Rate / Nyquist (per Lane)Gbps / GHzStandard Loss PCB Material inchesMid Loss PCB Material inchesLow Loss PCB Material inchesVery Low Loss PCB Material inches
HDMI 1.43 / 1.5
HDMI 2.16 / 3
HDMI 2.112 / 645.756.7510
5Differential Pair +/- Length Matching (Carrier / Module)≤ 2.5 mil / 2.5 mil
6Data Pair to Pair Length Matching (Carrier / Module)≤ 100 mil / 100 mil
7Pair to Pair SpacingD ≥ 5H
8TX or RX pair Spacing to Other SignalsDX ≥ 8H
9TX or RX Data Pair Distance to Self
10Maximum Via Stub Lengths:80 mil (per lane bit rate ≤ 6 Gtps)30 mil (per lane bit rate = 12 Gtps)
11Land Pattern and Via Voiding Recommendations:For HDMI modes with bit-rate at 12 Gtps per lane:Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.
# 4.4. PCB Design Rules for Single Ended (SE) Interfaces Table 32: Design Rules for Single Ended Interfaces
RefRule / Recommendation
1Most COM-HPC SE traces may be routed using a 55 ohm +/- 15%. trace impedance.The BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx nets are the exceptions and should be routed as 50 ohm +/- 15%
2SE nets may be routed as Stripline or Microstrip traces, referenced to a GND plane or to a quiet PWR plane.
3Crossing plane splits should be avoided for the faster SE interfaces (BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx). If these nets do cross a split in the reference plane, then the split should be “stitched” with a small capacitor that bridges the split for AC signals.
4SE signals with higher bit rates and faster edge rates need more routing care than slower signals. The higher bit rate SE signals include:BOOT_SPI_xxx Up to circa 100 Mhz in some cases; up to circa 50 MHz is more typicaleSPI_xxx Up to circa 50 MHzGP_SPI_xxx Up to circa 50 MHzI3C Up to circa 33 MHzSoundWire Up to circa 12 MHzVarious I2C signals Up to circa 1 MHz or 400 kHz in some cases but more typically are 100 kHz maxUART_xxx Up to circa 1 MHz in some cases – usually less – 115 kHz max is more commonCOM-HPC SE signals not listed just above are likely to be very slow, almost static in many cases.“More routing care” can mean:Signal should be GND referencedNo plane split crossingsStripline routing preferred, with primary reference to GNDSeries damping resistors for the signals listed as 50 MHz or moreBOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx have specific routing rules (see below)
5The COM-HPC BOOT_SPI_xxx signals are arranged in a “balanced tree” topology. Full details can be found in the COM-HPC Base Specification Version 1.0 Section 6.11.1.Up to 4 BOOT_SPI_xxx devices are allowed, but 3 are on the Module and only 1 (or 0) are allowed on the Carrier. The trace lengths for the BOOT_SPI Data and Clock between the COM-HPC connector balls and the Carrier device must be at least 2000 mils long and no more than 3000 mils long. This is to “balance” the on-Module and off-Module branches of the tree. The Data and Clock lines for this branch of the tree should be length matched to within 250 mil. A series damping resistor is recommended. Refer to the COM-HPC Base specification for more details and a diagram.The Chip Select line associated with the Carrier BOOT_SPI_xxx signals does not need length matching and should be routed as directly as possible.
6The COM-HPC eSPI_xxx signals are arranged in a “balanced tree” topology. Full details can be found in the COM-HPC Base Specification Version 1.0 Section 6.11.2.Up to 4 eSPI_xxx devices are allowed: up to 2 on the Module and up to 2 on the Carrier. The trace lengths for the eSPI Data and Clock lines between the COM-HPC connector balls and the Carrier device(s) must be at least 2000 mils long and no more than 3000 mils long. This is to “balance” the on-Module and off-Module branches of the tree. A series damping resistor is recommended. There should be separate branches in the tree if there are 2 Carrier devices. Refer to the COM-HPC Base specification for more details and a diagram.The Chip Select line associated with the Carrier eSPI_SPI_xxx signals does not need length matching and should be routed as directly as possible.
7GP_SPI_xxx net routing should follow the same rules as the eSPI_xxx nets. If there are 2 GP_SPI devices, there should be 2 separate tree branches.
8If any SE signals leave the Carrier and are exposed to the outside world and to potential contact with users, there should be both EMI and ESD mitigation measures implemented close to the connectors that face outside.
# 5. Mechanical Considerations # 5.1. Heat Spreader / Module / Carrier Attachment Details # 5.1.1. Heat Spreader to Module Attachment Notes The COM-HPC Base Specification calls out Module PCB mounting holes that are to align with corresponding Heat Spreader Plate, Carrier board and possibly system chassis mounting holes or features to hold the entire assembly together. However, the COM-HPC Base Specification also recommends that there be a separate set of vendor-specific holes to secure the Heat Spreader Plate (HSP), the Thermal Interface Materials (TIM) and the COM-HPC Module board together as a subsystem that can be shipped as a unit, independent of the larger system that includes the Carrier and other components (chassis, heat sinks, etc.). This is desirable as the TIM stack can be a sensitive, precision assembly that is best handled once and only once by the Module vendor. The reference to separate, design specific holes in the Module and HSP for this purpose are in the COM-HPC Base Specification V1.0 in Section 7.5.4 Table 93 Ref 5, reproduced here: The implementation specific holes / spacers / standoffs used to secure the HSP to the Module should be different from those used at the COM-HPC defined mounting hole sites. The x-y positions, the number of the vendor-specific HSP / TIM / Module attachment points and other implementation details are not defined by the COM-HPC specification document. However, a typical vertical cross section diagram of how this can be implemented is shown in Figure 60 below. Figure 60: Vendor Specific Heat Spreader to Module Attachment – Bottom Side Module PCB Access ![Pure structural diagram of a mechanical assembly with no text, numbers, or symbols](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/90b8f23ea6e2bd096922e4a0908a1b12c3d11fac625498bc56e81d7442696647.jpg) Legend: ![Seven horizontal colored bars in blue, purple, pink, orange, green, black, and yellow (no text or symbols)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/2fa203066ad601d9128f49e71bd5d20843656c0e3020b28aa5bb44a2c12a49d9.jpg) Heat Spreader Plate – Vendor Specific Implementation Details HSP to Module Spacers or Standoffs – Vendor Specific Locations and Implementation Details TIM – Vendor Specific Implementation Details – Typically, Compliant Foam or Phase Change Material CPU / SOC Die or Lid Module PCB Spacers / Standoffs at COM-HPC Defined X-Y Positions, For Module Mounting – Vendor Specific Implementation Details Module to Carrier Connectors # 5.1.2. Heat Spreader / Module Assembly Attachment to Carrier and Chassis Figures 61 through 64 illustrate a variety of hardware mechanical component and assembly options to secure the COM-HPC HSP, Module, Carrier and system chassis together, Figure 61: Heat Spreader Assembly Mounting to Carrier – Bottom Side Screw Access ![Detail B](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/c85fec796e0d456559fc468af04411887847a6af54dacd1b3511c6370a159757.jpg) ![Cross section view of Detail B Heatspreader (HSP) HSP Stand-Off (M2.5 thread) CPU Module Carrier Board Stand-Off (Ø 2.7 clearance hole) Carrier Board M2.5 Screw and Washer](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/dd3dc9ae5b95a98ee4d4d0ce441cb1b55287528bb52e5058a5000b6c136fb7a1.jpg) Figure 62: Heat Spreader Assembly Mounting to Carrier – Top Side Screw Access ![Detail A](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/0aa935c28f95019389e52c909ab6fc9fbf6b9949c489037ce6b145c8378b0d66.jpg) ![Cross section view of Detail A M2.5 Screw (flat head) HSP Stand-Off (Ø 2.7 clearance hole) Baseboard Stand-Off (M2.5 thread) Heatspreader (HSP) CPU Module Carrier Board](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/b4fbf581045394531d07a0991f5e3210fcea1e90e28f248940404a32a6a1cb27.jpg) Figure 63: Heat Spreader Assembly Mounting to Carrier With Broaching Nut – Top Side Screw Access ![Detail A](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/fa423887cc4ae076268c4171579da78abfd2ee3b7ca7088ba1fffdf97c5ac9bc.jpg) ![Cross section view of Detail A M2.5 Screw (flat head) Heatspreader Stand-Off (Ø 2.7 clearance hole) CPU Module Broaching Stand-Off (M2.5 thread) Carrier Board Heatspreader](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/c11d151dd784615f92000b88508238d300770c3b11e29aa745d4190f8324f51f.jpg) Figure 64: Heat Spreader Assembly Mounting to Carrier and Chassis – Top Side Screw Access ![Detail A](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/0d5366d291006739ed29949dd3365b50681f216d89eb3dece929717874a95324.jpg) ![Cross section view of Detail A M2.5 Screw (flat head) Heatspreader Stand-Off (Ø 2.7 clearance hole) Carrier Board Stand-Off (Ø 2.7 clearance hole) Broaching Stand-Off (M2.5 thread) Heatspreader CPU Module Carrier Board Chassis](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/2d0f5bdda5e0013f83dee031aaa66c645089fafc762e6644fe416b60adadcea2.jpg) Some useful vendors and vendor part numbers for mechanical parts that may be used in Figures 61 through 64 above are listed here: ◦ PEM TSOS-M25-1500 ▪ M2.5 threaded blind standoff for sheet metal / plate use – 15 mm overall length (for Client) PEM TSOS-M25-1800 (18 mm for Server) ▪ M2.5 threaded blind standoff for sheet metal / plate use – 18 mm overall length (for Server) ◦ www.pemnet.com ◦ Wurth 9774050951 5 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer ◦ Wurth 9774100951 10 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer ▪ May be SMT soldered to Carrier Top side as shown in the Figures 61 and 64 above 。 www.wuerth.com ◦ EFCO (Taiwan) has numerous mechanical parts for COM-HPC and other Module standards 。 www.efcotec.com ◦ Or use a search engine, look for “efcotec com accessories” # 5.2. Alternative COM-HPC Board Stack Assembly Suggestion An alternative COM-HPC board stack assembly method and set of mechanical hardware is presented just below. This material has been submitted by Samtec. These assembly mechanics make use of Samtec defined connector hardware components, known as JSOM, for “Jack Screw Stand-off – Micro”. These mechanical hardware parts are used in PC-104 and in some VITA assemblies. Samtec JSOM data sheets and drawings are readily available online. This approach defines an assembly stack allowing a COM-HPC Module and Carrier to be mounted to a metal chassis which is below the Carrier. This assembly method does not include considerations for a Heat Spreader Plate. Thermal management components such as heat sinks or HSP / heat sink combinations would be handled on separate holes. The ‘ASP’ references in some of the Figures below are Samtec designations for “Application Specific Parts”. There is an ASP summary in Figure 71 several pages below. # 5.2.1. Precision Jack Screw Standoffs Precision jack screw standoff hardware (referred to as JSOM by Samtec) can be used to help mating and unmating procedures in high-normal-force, multi-connector applications. They work like traditional stand-offs but contain an internal machined hex screw that can be turned in a counterclockwise direction to lift the Module Card from the Carrier Board. JSOM based assemblies can mitigate damage to the connector pins, components, boards, and solder joints. # Assembly / Dis-assembly Procedure Overview Before mating the Module Card to the Carrier Board, use a 1.5mm hex driver to turn the JSOM screw clockwise until the screw is fully seated in the JSOM standoff. Figure 65: JSOM (Jack Screw Standoff – Micro) Diagram and Application Cutaway ![LOCKING NUT M 2.5 JSOM SCREW JSOM STANDOFF STANDOFF (SO) SCREW M 2.5 FULL JSOM & STANDOFF ASSEMBY MODULE PCB CARRIER PCB METAL CHASSIS ASSEMBLY CUT-AWAY TO SHOW DETAILS OF JSOM & STANDOFF](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/cc0ffcacd17598836944bfae13889743e4a4b74f577055b8bc1543bd3c4b0a8f.jpg) Once all four JSOM screws are fully seated, apply even downward pressure over the J1 and J2 connector regions to mate the Module Card to the Carrier Board. Once the Module Card is fully mated secure the Module Card to the Carrier Board with four hex nuts and lock washers as shown in Figure 66 (a). Use a torque wrench to tighten the hex nuts to 3.0 (+/- 0.5) in-lbs. Tighten the nuts in an alternating diagonal pattern shown in Figure 66 (b). For detailed mating recommendations, refer to section 7.5.5 of the COM-HPC® Module Base Specification, Revision 1.0. Figure 66: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns ![This image displays a technical diagram divided into three panels labeled (a), (b), and (c), illustrating assembly instructions for a green printed circuit board (PCB). **Panel (a):** * **Title:** 'Hex Nut and Lock Washer (torque to 3.0 in-lbs)' * **Visual:** A 3D isometric view of the green PCB with black heat sinks attached. * **Labels:** An arrow points to the tops of the heat sinks labeled 'Hex Nuts'. A line points to the bottom mounting hardware labeled 'JSOM STANDOFF'. * **Bottom Label:** (a) **Panel (b):** * **Title:** 'Alternating Diagonal Pattern' * **Visual:** A top-down 2D schematic of the green PCB. * **Text:** 'Size D' is centered. * **Diagram:** Four black circles with white numbers mark corners: 1 (top-left), 4 (top-right), 3 (bottom-left), and 2 (bottom-right). Red dashed lines connect corner 1 to 2 and 3 to 4, forming an 'X' pattern. * **Bottom Label:** (b) **Panel (c):** * **Title:** 'Use Hex Key to Lift Module PCB (1/4 turns until connectors unmated)' * **Visual:** A 3D isometric view showing a tool inserted into a standoff. * **Label:** A line points to the tool labeled '1.5mm Hex Key'. * **Bottom Label:** (c)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/8829af48ecb2375fda4358f453d49f2c988171d44593372cec4d9e95e44c1e47.jpg) # Unmating the Module Card from the Carrier Board To unmate the boards remove the locking nuts and washers. Using the diagonal pattern shown in Figure 66 (b) insert the 1.5mm hex key shown in Figure 66 (c) into the JSOM screw labeled 1 and turn counterclockwise a ¼ turn. Repeat this procedure for all JSOM screws labeled 2, 3, and 4 until the connectors unmate. The Module Card can then be removed from the Carrier Board. Figure 67: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware ![The image displays three technical cross-section diagrams arranged horizontally, labeled (a), (b), and (c) at the bottom. (a) Titled **JSOM FULLY SEATED**, this diagram shows a mechanism with labels **JSOM** pointing to the upper shaft and **SO** pointing to the lower shaft. A dimension line indicates a measurement of **0.26 (.010)**. (b) Titled **JSOM PARTIAL LIFT MODULE PCB**, this diagram shows the mechanism in a lifted state. It includes labels **JSOM** and **SO**. A dimension line indicates **1.76 (.069)**. (c) Titled **JSOM FULLY LIFTED MODULE PCB CONNECTORS UNMATED**, this diagram shows the mechanism fully lifted. It includes labels **JSOM**, **SO**, **ASP-209946-01** pointing to an upper connector, and **ASP-209948-01** pointing to a lower connector. A dimension line indicates **3.26 (.128)**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/65b2ba376b74013425382f10e4569a70c36b765d7aec7fd6d556bb96a3bd85f0.jpg) # 5.3. Carrier Board Stiffener FEM (Finite Element Method) mechanical simulations were conducted to understand the amount of deflection and temporary stress that can occur in the Carrier Board as it is being mated with a Module Card. The simulations assumed that the Carrier Board was fabricated using standard 0.0625” thick FR4 material and fixed to a stiff chassis using metal stand-offs attached to the mounting holes adjacent to both the Carrier P1 and P2 connectors. As shown in Figure 68 below, a downward force was applied evenly over the length of the connector, and the amount of deflection was measured. The results confirmed that 0.0625” Carrier Boards should be supported using some type of stiffening mechanism. Figure 68: FEM Simulation Results – 0.0625” FR4 Carrier – No Stiffener ![ UY (in) Value --------- ----------- 0.024 Red 0.015 Orange 0.007 Yellow -0.002 Green -0.010 Blue -0.018 Purple -0.027 Green -0.035 Blue -0.044 Green -0.052 Blue -0.061 Green -0.069 Green -0.078 Blue ](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/ba71317591de4f4441c957156d2f5fe3100c07bb47b94bb05f67de74453cb774.jpg) Note however that the stiffness of a piece of sheet material such as a PCB is proportional to the cube of the sheet thickness. Hence using a thicker PCB may relax or obviate the need for a Carrier stiffener. PCB thickness of 0.079” (2mm), 0.092” and even 0.125” are common. However, be aware that if the Carrier uses through hole parts (typically for I/O connectors) then increasing the PCB thickness too much will result in a soldering problem as the through hole part leads need protrude beyond the PCB a bit for wave soldering. A metal simple stiffener design is shown in Figure 69 below with the corresponding keep-out regions shown in Figure 70 below. This Figure shows the Carrier PCB Top side. The Carrier stiffener keep-out regions are on the Bottom side of the Carrier board, as indicated by the dashed lines. When designing a Carrier Board stiffener there are some points to consider. The stiffener should provide uniform support directly underneath the Carrier Board connector and span the entire length of the connector region. This should be done for both the P1 and P2 Carrier connectors. ● The stiffener should be securely anchored to the chassis through mechanical mounting hardware or attached to the bottom side of the Carrier Board using an adhesive. The stiffener thickness should be as thick as the application allows. ● Care must be taken when using conductive materials such as steel or alloys. ● This stiffener concept will require a keep-out region where peripheral components cannot be placed. It may be necessary to exclude via pads from the PCB Bottom side in the in the keep-out region, or to insulate vias from a metallic stiffener. Kapton tape is the usual remedy for this situation. But such a solution may not be appropriate for high – vibration situations. A thicker, compliant foam material may also be considered. Figure 69: Mechanical Carrier Stiffener Possibility ![Isometric line drawing of a rectangular electronic component with multiple slots and circular holes (no text or symbols)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/463affe91d78f0e4fe8458125713de3a18f8c902860ef78f604f94f5428bd27d.jpg) ![Ø3.40 (4 PLCS) 18.41 14.000 6.000 0 7.00 10.000 (2 PLCS) 13.00 'A' 'A' 87.00 90.000 (2 PLCS) 93.00 100.00](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/066121a4003a65e87663f2334f8638638d900ff66dd5bdbd7921a9b81876e263.jpg) ![0.91 (TYP) 16.83 12.23 7.63 3.03 0 R0.25 3.01 2.50](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/9d538080d72d61c39dfb4a18e329296ad7e6c7b9e07a2a04d67bad72b2310eac.jpg) ![Ø3.40 REF 2.50 REF](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/d4b4ed61b55d42adf4e9cccc1c95a9c40b27f2e63a1f61c93f78c76eded76f13.jpg) Figure 70: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier) ![ Dimension Value --- --- Length 6.00 (.236) Width 10.00 (.394) Height 100.00 (.3937) (KEEP OUT) Base Width 10.00 (.394) Thickness 4.41 (.174) Keep Out Width 18.41 (.725) ](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/e96e176a43bcf27f1784a54fcf559d8b060cad31213a0cfd6215e7e80aefc386.jpg) Dimensions in the two Figures above are in mm. Figure 71: Application Specific Part Number (ASP) Reference Guide ![JSOM ASSEMBLY (ASP-222919-01) 2.50 (.098) NON-STANDARD STANDOFF REQUIRED - SEE DETAIL VIEW 10.15 (.400) 15.15 (.596) 12.65 (.498) NON-STANDARD STANDOFF REQUIRED - SEE DETAIL VIEW MODULE PCB STIFFENING CLIP (ASP-222928-01-C) CARRIER PCB STIFFENING CLIP (ASP-222927-01-C) STANDOFF ASSEMBLY (ASP-222923-01)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/fd188602f55f1b3b29545a9d0945357dedea15f9ca22bc008886b30219c952f3.jpg) ![STANDOFF ASSEMBLY ASP-222923-01 THREAD MUST BE SPECIFIED 2.5mm LONGER THAN .062 PCB THICKNESS) HEIGHT OF STANDOFF BODY MUST BE 2.5mm SHORTER THATY THAN PCB SPACING](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/1ce2d5d5e27622d4b8609b5bd4191f453ce6d23667a44a785bfa0a79babc389c.jpg) ![JSOM ASSEMBLY ASP-222919-01 6.16 (NON-STD) 6.00 (STD)](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/2d170ca49edc1d7dc76c29597b69491dd0d6821a504ed25b65aed0b6b98755ca.jpg) # Non-Metallic Stiffener Possibilities A simple but effective Carrier board stiffener option is to fabricate a simple non-metallic rectangular bar that is positioned between the Carrier PCB Bottom side and the system chassis. The stiffener bar extent shadows the Carrier connector and the adjacent mounting holes as shown by the dashed lines in Figure 70 above. Nylon is a suitable material. Metal press fit inserts at the mounting hole positions may be beneficial. # 6. Appendices # 6.1. Appendix A: Synchronous Ethernet Synchronous Ethernet, or SyncE, is an ITU-T standard that allows precision timing information to be embedded into Ethernet physical layer. This signal can be correlated to an external high precision master clock. It is important to telecom providers as the telecom infrastructure moves away from TDM based standards such as SONET and to packet based Ethernet implementations. # Introduction to SyncE Synchronous Ethernet (SyncE) distributes a frequency signal through Ethernet - Defined in ITU-T G.8261, G.8262, G.8262.1, G.8264 GbE and above always‡ sends symbols (data or idle) SyncE recovers received data rate - Ethernet requires ±100 ppm clocking - Receivers must handle up to 200 ppm clock delta - SyncE saves off a fractional rate to drive DPLL # External DPLLs External DPLLs can take in multiple clock sources - 1PPS and 10 MHz inputs–GPS/GNSS input(s) - often 1PPS as well - SyncE recovered clocks - IEEE 1588/PTP-driven clocks (also often 1PPS) - Local oscillator - Long-term oscillator (TCXO or OCXO) DPLL sets a priority of inputs • All outputs driven synchronously off selected input(s) -TX side of all PHYs and/or SoCs driven from PLL clock # SyncE on PHYs Some SoCs support SyncE on internal PHYs Some external PHYs support SyncE clock recovery Each RX port adapts to meet incoming data rate - Each RX port may be different - Fractional clock rate from selected port(s) sent to DPLL TX side driven from DPLL - All TX ports driven at same rate Driver support for SyncE with external DPLLs may vary # Implications for Modules / Pinouts • If Module SoC and Carrier Board PHY both need SyncE, need SyncE info across connectors Carrier sends recovered clock(s), 1PPS input(s) Module sends TX clock(s), 1PPS output(s) Figure 72: Synchronous Ethernet Overview ![**Blocks:** * **SoC** (Blue rectangle) * **DPLL** (Yellow rectangle) * **OCXO** * **XO** * **SMA** (Three circles) * **25 MHz** (Crystal symbol) * **DS-to-SE** (Yellow trident symbol) * **SE-to-DS** (Yellow trident symbol) * **AC Coupled** (Capacitor symbol) **Connections:** * **25 MHz** connects to **NAC_OPPS_P/N** and **NAC_CLK_SYNCED_P/N** on the SoC. * **ETH_I2C_CLK2** and **ETH_I2C_DATA2** on the SoC connect to **SDA** and **SCL** on the DPLL. * **NAC_OPPS_P/N** on the SoC connects to **DS-to-SE**, which connects to **REF0n** on the DPLL. * **NAC_CLK_SYNCED_P/N** on the SoC connects to **SyncE Clock Output from SoC** (AC Coupled), which connects to **REF1p/n** on the DPLL. * **From DPLL Out7p** connects to **SE-to-DS**, which connects to **NAC_TIME_SYNC_PN** on the SoC. * **PPS from GPS or 1588** (SMA) connects to **REF4p** on the DPLL. * **External Sync Clock** (SMA) connects to **REF3p** on the DPLL. * **OCXO** connects to **REF4n** on the DPLL. * **XO** connects to **OSC B** on the DPLL. * **OUT0p** on the DPLL connects to **PPS Output** (SMA). * **OUT1p** on the DPLL connects to **10M Sync Clock Output** (SMA). * **OUT3p/n** on the DPLL connects to **Internal PHY clock for SyncE**. * **OUT5p/n** on the DPLL connects to **1588 Time Sync Clock**. * **OUT6p** on the DPLL connects to **PLL_INT_N**. * **OUT7p** on the DPLL connects to **PPS Output To ICX-D**. * **PLL_INT_N** connects to **SRC_CLKREQ5_N_GPP_W81** on the SoC. * **Internal PHY clock for SyncE** connects to **NAC_TIME_REF_P/N** on the SoC. * **1588 Time Sync Clock** connects to **NAC_CLKIN_EREFO_P/N** on the SoC. **Notes:** 1. DS = Differential; SE = Single-ended 2. PPS from GPS and 1588 Eth can be input to DPLL 3. ESD protection needs be considered for SMA header 4. Any unused LVDS signals should be left unconnected **Legend:** * Differential Signal * Single-ended Signal](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/79c4560b5bf4f1af13536e9c497eba44f8cba13f86c1c3159ac49c8593d2173e.jpg) Figure 73: Synchronous Ethernet Example Implementation ![Based on the provided flowchart/block diagram, here is an accurate and concise description of the labeled blocks and connections: **Blocks:** * **Module:** A large grey container encompassing the internal components. * **PHY:** A green block at the top center. * **SoC:** A blue block in the center. * **DtoS:** A white block inside a dashed border, located to the right of the SoC. * **DPLL:** A yellow block at the bottom containing pins labeled **OUT0** through **OUT9**, **IN 0** through **IN 4**, and **XTAL**. * **SDP Blocks:** White blocks labeled **SDP 5**, **SDP 2 / 3**, **SDP 0 / 1**, **SDP 6**, and **SDP 7**. * **i225:** A pink block on the left. * **StoD:** A white block at the bottom left. * **XO / OCXO:** White blocks at the bottom right. * **External Inputs:** Circles labeled **SMA** (top left), **SMA** (top right), and **GPS** (top right). **Connections:** * **SMA (top left):** Connects via a dashed line labeled **1PPS** to **SDP 5**. Connects via a solid line labeled **156,25 to PV** to **PHY** and **SDP 2 / 3**. * **PHY:** Receives input from **SMA (top left)** and outputs via a solid line labeled **RCLK_A/B** to **SDP 0 / 1**. * **SDP 2 / 3:** Receives input from **SMA (top left)**. Outputs solid lines labeled **NAC_TIME_SYNC**, **INT_N**, **TIME_REF**, and **CLK_EREFO** to **SoC**. Outputs a solid line to **StoD**. * **SoC:** Receives inputs from **SDP 2 / 3**. Outputs a solid line labeled **CLK_SYNCE0** to **SDP 0 / 1**. * **SDP 0 / 1:** Receives inputs from **PHY** and **SoC**. Outputs a dashed line to **DPLL (IN 1)**. * **SDP 5:** Receives input from **SMA (top left)**. Outputs a dashed line to **i225**. * **i225:** Receives input from **SDP 5**. Outputs a solid line to **DPLL (OUT0)** and a dashed line to **DtoS**. * **DtoS:** Receives input from **i225**. Outputs a dashed line labeled **ON_PPS_OUT** to **DPLL (IN 0)**. * **StoD:** Receives input from **SDP 2 / 3**. Outputs a solid line to **DPLL (OUT5)**. * **DPLL Inputs:** * **IN 0:** Connected to **DtoS** (ON_PPS_OUT). * **IN 1:** Connected via dashed line from **SDP 0 / 1**. * **IN 2:** Crossed out with a label **No Stuff**. * **IN 3:** Connected via dashed line from **SDP 6**. * **IN 4:** Connected via dashed line from **SDP 7** and a solid line from **OCXO**. * **XTAL:** Connected via solid line from **XO**. * **SDP 6:** Receives input from **SMA (top right)** via dashed line labeled **1PPS**. * **SDP 7:** Receives input from **GPS** via dashed line labeled **1PPS**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/7516c1caa2cf7a94831bfe00722e67c2d018a28f66299c2958b9fcb057f925ba.jpg) Table 33: SDP Use in Figure 73 above
SDPMeaningDirectionNotes
0Recovered Clock AInIn (to Module)
1Recovered Clock BIn
2Output Clock (+)OutDifferential Pair on SDP2 and 3
3Output Clock (-)Out
4
51 PPS OutOut
61 PPS InIn
71 PPS In (GNSS)In
# SyncE Summary Provides physical layer synchronization signal over Ethernet ◦ Allows expensive central clock to be shared across the network Defined in ITU-T G.8261, G.8262, G.8262.1, and G.8264 specs ◦ G.8261 and G.8262 series define physical layer interface G.8264 defines messaging channel used to provide pedigree of clock sources SyncE can be used alone or in conjunction with PTP: Table 34: SyncE / PTP Matrix
AttributeSyncE OnlyPTP OnlySyncE + PTP
Frequency AccuracyYesYesYes
Phase AccuracyNoYesYes
Time of Day (ToD)NoYesYes
# 6.2. Appendix B: Alternative eDP Example The alternative eDP example presented in Figures 74 through 79 below comes, with permission, from an Intel reference schematic for a late model CORE series processor. Some parts of the example may not be directly relevant to COM-HPC embedded designs in that they dwell on eDP back-light display power supplies and on a display connector used in certain reference platforms. Nonetheless, the materials may be of interest to some readers and are included in this Appendix. Figure 74: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options – eDP and DSI ![COM EDP TX0- C7G3 1 2 EDP TX0_C- OUT COM EDP TX0+ C7G2 1 2 EDP TX0_C+ OUT COM EDP TX1- C7G1 1 2 EDP TX1_C- OUT COM EDP TX1+ C7F9 1 2 EDP TX1_C+ OUT COM EDP TX2- C7F8 1 2 EDP TX2_C- OUT COM EDP TX2+ C7F7 1 2 EDP TX2_C+ OUT COM EDP TX3- C7F6 1 2 EDP TX3_C- OUT COM EDP TX3+ C7F5 1 2 EDP TX3_C+ OUT COM EDP AUX- C7F4 1 2 EDP AUX_C- BI COM EDP AUX+ C7F3 1 2 EDP AUX_C+ BI A36096-110 0402 AC CAP SHOULD BE REPLACED WITH OR RESISTOR FOR THE MIPI-DSI DISPLAY](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/30efac12d5256958328a79189a0acc8d325ca97cb572b759670f3117084ee86d.jpg) ![H30143-001 R7F18 1 2 0 0% 0.05W RES 0201 EDP AUX MIPI_D0 L+ OUT IN EDP AUX C+ L7F1 90 EMPTY 30% SM.A J16541-001 NEED TO STUFF CMC FOR MDSI IN EDP AUX C- H30143-001 R7F19 1 2 0 0% 0201 0.05W RES EDP AUX MIPI_D0 L- OUT](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/7077fdb849d5a981186f468a2b57e402728f7d214dcdb9a2a91a70e752431d17.jpg) ![This block diagram depicts two identical signal processing stages, one for 'TX3' and one for 'TX2'. Each stage consists of a differential pair of signals passing through parallel resistor and inductor (choke) paths. **Top Stage (EDP TX3 / LANE3):** * **Positive Path:** * **Input:** An 'IN' block connects to a line labeled **EDP TX3 C+**. * **Connections:** This line splits to connect to **Pin 1** of a resistor and **Pin 3** of an inductor. * **Resistor Block:** Labeled **H30143-001**, **R7F20**. Below it reads **0 0%**, **0.05W EMPTY**, **0201**. * **Inductor Block:** Labeled **L7F2**. Below it reads **90**, **CHOKE**, **30%**, **SM A**, **JI6541-001**. The top winding connects **Pin 3** (input side) to **Pin 4** (output side). * **Output:** The resistor's **Pin 2** and the inductor's **Pin 4** connect to an 'OUT' block labeled **EDP LANE3 MIPI D3 L+**. * **Negative Path:** * **Input:** An 'IN' block connects to a line labeled **EDP TX3 C-**. * **Connections:** This line splits to connect to **Pin 1** of a resistor and **Pin 2** of the inductor (L7F2). * **Resistor Block:** Labeled **H30143-001**, **R7F21**. Below it reads **0 0%**, **0.05W EMPTY**, **0201**. * **Inductor Winding:** The bottom winding of **L7F2** connects **Pin 2** (input side) to **Pin 1** (output side). * **Output:** The resistor's **Pin 2** and the inductor's **Pin 1** connect to an 'OUT' block labeled **EDP LANE3 MIPI D3 L-**. **Bottom Stage (EDP TX2 / LANE2):** * **Positive Path:** * **Input:** An 'IN' block connects to a line labeled **EDP TX2 C+**. * **Connections:** This line splits to connect to **Pin 1** of a resistor and **Pin 3** of an inductor. * **Resistor Block:** Labeled **H30143-001**, **R7F22**. Below it reads **0 0%**, **0.05W EMPTY**, **0201**. * **Inductor Block:** Labeled **L7F3**. Below it reads **50**, **CHOKE**, **30%**, **SM A**, **JI6541-001**. The top winding connects **Pin 3** (input side) to **Pin 4** (output side). * **Output:** The resistor's **Pin 2** and the inductor's **Pin 4** connect to an 'OUT' block labeled **EDP LANE2 MIPI CLK L+**. * **Negative Path:** * **Input:** An 'IN' block connects to a line labeled **EDP TX2 C-**. * **Connections:** This line splits to connect to **Pin 1** of a resistor and **Pin 2** of the inductor (L7F3). * **Resistor Block:** Labeled **H30143-001**, **R7F23**. Below it reads **0 0%**, **0.05W EMPTY**, **0201**. * **Inductor Winding:** The bottom winding of **L7F3** connects **Pin 2** (input side) to **Pin 1** (output side). * **Output:** The resistor's **Pin 2** and the inductor's **Pin 1** connect to an 'OUT' block labeled **EDP LANE2 MIPI CLK L-**. **Additional Note:** * A box at the bottom reads: **CAD NOTE: CMC PAD SHARING WITH RESISTOR**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/20a400ed20e9ff9b4373dc39f1e875db9d20239f70450e7c553878c407695834.jpg) ![The diagram depicts a circuit with two differential signal pairs, each consisting of an input (IN) and an output (OUT) connected through parallel resistor and choke components. **Top Section (EDP_TX1 to EDP_LAN1):** * **Positive Line:** An input labeled **IN** connects to a junction. From this junction, a resistor **R7F24** (text: **H30143-001**, **0 0%**, **0.05W EMPTY**, **0201**) is connected in parallel with the top winding of a choke **L7F4** (text: **90**, **CHOKE**, **30%**, **SM_A**, **J16541-001**). The other side of both components connects to a second junction, which leads to an output labeled **EDP_LAN1_MIPI_D2_L+**. * **Negative Line:** An input labeled **IN** connects to a junction. From this junction, a resistor **R7F25** (text: **H30143-001**, **0 0%**, **0.05W EMPTY**, **0201**) is connected in parallel with the bottom winding of the choke **L7F4**. The other side connects to a second junction, leading to an output labeled **EDP_LAN1_MIPI_D2_L-**. **Bottom Section (EDP_TX0 to EDP_LAN0):** * **Positive Line:** An input labeled **IN** connects to a junction. From this junction, a resistor **R7G1** (text: **H30143-001**, **0 0%**, **0.05W EMPTY**, **0201**) is connected in parallel with the top winding of a choke **L7G1** (text: **90**, **CHOKE**, **30%**, **SM_A**, **J16541-001**). The other side connects to a second junction, leading to an output labeled **EDP_LAN0_MIPI_D1_L+**. * **Negative Line:** An input labeled **IN** connects to a junction. From this junction, a resistor **R7G2** (text: **H30143-001**, **0 0%**, **0.05W EMPTY**, **0201**) is connected in parallel with the bottom winding of the choke **L7G1**. The other side connects to a second junction, leading to an output labeled **EDP_LAN0_MIPI_D1_L-**. **Additional Note:** * A text box at the bottom reads: '**CAD NOTE:**' followed by '**CMC PAD SHARING WITH RESISTOR**'.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/08e58b6282366da85f9d700c1f7d91dc5e8c538881e798bf5524fad64e7062bb.jpg) Figure 75: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options BACKLIGHT CONTROL ![COM EDP_BKLTCTL R7F12 1 0 0402 RES R3R13 1 0 0402 EMPTY EDP_BRIGHTNESS_CONN MIPI1_PWM OUT OUT](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/4232c43169b7751c28f22b9f6ac1b614cad88756982720c25adc3a858fe60c1a.jpg) ![This diagram depicts a circuit with one input source branching into four parallel output paths. **Input Section:** * **Block:** A box labeled **COM**. * **Connection:** A line extending from COM labeled **EDP BKLt EN**. * **Split:** This line connects to a junction (black dot) that splits into four parallel branches. **Parallel Branches (Top to Bottom):** 1. **Branch 1:** * **Component:** Resistor labeled **R7F15**. * **Labels:** Above the resistor are the numbers **1** and **0**. Below the resistor is **0402** and **RES**. To the right of the resistor is the number **2**. * **Output Connection:** Labeled **EDP BKLt EN CONN**. * **Output Block:** **OUT**. 2. **Branch 2:** * **Component:** Resistor labeled **R3T6**. * **Labels:** Above the resistor are the numbers **1** and **0**. Below the resistor is **0402** and **RES**. To the right of the resistor is the number **2**. * **Output Connection:** Labeled **EDP BKLt EN R**. * **Output Block:** **OUT**. 3. **Branch 3:** * **Component:** Placeholder symbol (circle with an X) labeled **R7E4**. * **Labels:** Above the symbol are the numbers **1** and **0**. Below the symbol is **0402** and **EMPTY**. To the right of the symbol is the number **2**. * **Output Connection:** Labeled **MIPI1 BKLt EN R**. * **Output Block:** **OUT**. 4. **Branch 4:** * **Component:** Placeholder symbol (circle with an X) labeled **R3R4**. * **Labels:** Above the symbol are the numbers **1** and **0**. Below the symbol is **0402** and **EMPTY**. To the right of the symbol is the number **2**. * **Output Connection:** Labeled **MIPI1 EN**. * **Output Block:** **OUT**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/5338e1b58af0fe1652e3c7cc4002162760532ebfe9d2fe04a5b0d7f77dfb1f10.jpg) ADDITIONAL AMOLED POWER REQUIREMENTS ![J7E1 CON HDR_1X3 JA A91829-001 1 2 3 GND -V_ELVS_EDP1_AMOLED1 +VCC_EDP1_AMOLED1 C7F1 A36096-112 0.1UF 10% 25V X7R 04D2 GND +VCC_EDP1_AMOLED1 STUFF RA & RC RB & RD RA & RC](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/fa624500aba5674d94546d3c4972c96e8e8b9b9bc528652bd7a6e726d9308d36.jpg) DESIGN NOTE: THE HEADER JA SHOULD NEVER BE SHORTED WITH JUMPER SHORTING LINK ![-V_ELVS-EDP1_AMOLED1 R7E1 H11304-001 0.01 1% 0.25W EMPTY 1 2 RB -VVS_EDP1_AMOLED1 R8E1 A93552-004 0 0% 0.1w RA RES 0603 GND +VCC_EDP1_BKLT RD D71825-002 R7F5 1% 0.01 0603 0.1W RES RC 2 R7F4 2 0.01 0603 0.1W EMPTY +VCC_EDP1_BKLT_R](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/d6439f9eb52bac8b4cc304208c6fa7b31bc3cc89263f067c854e917c9da96995.jpg) ![COM EDP_VDD_EN R3T2 1 0 2 EDP1_EN_BKLT_SHDN# 0402 RES R3T1 1 0 2 MIPI1_VDD_EN_R 0402 EMPTY A93549-001 OUT OUT](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/4e406045131a6229ac5f275829c0c067e455387dbaa628abccb5020b205d2910.jpg) ![Based on the provided schematic diagram, here is the accurate description of the labeled blocks and their connections: **Labeled Blocks and Components:** * **IN**: Signal input blocks (appears three times). * **COM**: Ground/Common blocks (appears twice). * **BUF PLT RST#**: Signal label. * **R7F17**: Component (labeled '0402 EMPTY', 'A93549-001'). * **EDP_HPD**: Signal label. * **R7F16**: Resistor component (labeled '0402 RES'). * **EDP_HPD_MIPI_PNL_RST_R**: Net label. * **R7F11**: Component inside a dotted box (labeled '0402 EMPTY', 'A93549-001'). * **PANEL_MDSI_A_TE1**: Net label. * **GPIO_03**: Signal label. * **R7F10**: Component inside a dotted box (labeled '0402 EMPTY', 'A93549-001'). * **DESIGN NOTE**: Text box. * **MAKESURE COMPUTE SIDE IS 1.8V BEFORE ENABLE THIS PATH**: Text inside the design note box. **Connections:** 1. **Top Path:** An **IN** block connects to the label **BUF PLT RST#**, which connects to pin **1** of component **R7F17**. The output from pin **2** of **R7F17** connects downwards to a central junction node. 2. **Middle Path:** A **COM** block connects to the label **EDP_HPD**, which leads to the same central junction node described above. * From this junction, a line extends right through component **R7F16** (pin **1** to pin **2**). The output is labeled **EDP_HPD_MIPI_PNL_RST_R** and terminates at an **IN** block. * From the same junction, a line goes down to pin **1** of component **R7F11**. 3. **Bottom Path (Dotted Box Area):** A **COM** block connects to the label **GPIO_03**, which connects to pin **1** of component **R7F10**. * The output from pin **2** of **R7F10** (going up) and the output from pin **2** of **R7F11** (going right) meet at a junction node. * From this combined junction, a line extends right, labeled **PANEL_MDSI_A_TE1**, and terminates at an **IN** block. **Design Note:** A box labeled **DESIGN NOTE:** contains the text: **MAKESURE COMPUTE SIDE IS 1.8V BEFORE ENABLE THIS PATH**.](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/e93c8d23ea3b7cdbb2a14f0f53eb396f952e555d220d17052a36cf01d7ae7618.jpg) ![+VCC_EDP1_AMOLED1 +V5P5P_MIPI1 R7F9 0.01 1 2 EMPTY +V5P5P_MIPI1_AMOLED1 0603 0.1W 1% D71825-002 R7F8 0.01 1 2 EMPTY +V5P5N_MIPI1_AMOLED1 0603 0.1W 1% D71825-002 R7F7 0.01 1 2 EMPTY +V5P5N_MIPI1_AMOLED1 0603 0.1W 1% D71825-002 R7F6 0.01 1 2 RES 0603 0.1W 1% D71825-002](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/71bd0170645f287c805c77fc379e929f5bde00eb9ec96ac4c9aaab683296953d.jpg) Figure 76: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly ![+V3P3DX_EDP1_MIPI1 C7G6 602433-081 22UF 20% 6.3V X5R 0603 C7G4 A36096-112 0.1UF 10% 25V X7R 0402 +V3P3S C7F2 602433-081 22UF 20% 6.3V X5R 0603 C3T5 602433-081 22UF 20% 6.3V X5R 0402 +VCC_EDP1_BKLT_R C3T1 A36096-112 0.1UF 10% 25V X7R 0402 +VCC_MIPI1 C3R8 H48130-001 10UF 10% 25V X7R 0402 +VCC_MIPI1 C3R7 G21127-001 10UF 10% 50V X7R 0402 +V1P8_MIPI1 C3T2 602433-081 22UF 20% 6.3V X5R 0402 +V3P3S RF14 A93549-016 1K 5% 0.0625M EMPTY 0402 +V3P3S EDP_BKLT_EN_CONN EDP_BRIGHTNESS_CONN PANEL_MDSI_A_TE1 DESIGN NOTE: PIN 20 MDSI_A_TE1 IS 1.8V OUT +V3P3S EDP_LANEO_MIPI_D1_L- EDP_LANEO_MIPI_D1_L+ EDP_LANEE_MIPI_D2_L- EDP_LANEE_MIPI_D2_L+ EDP_LANEE_MIPI_CLK_L- EDP_LANEE_MIPI_CLK_L+ EDP_LANEE_MIPI_D3_L- EDP_LANEE_MIPI_D3_L+ EDP_AUX_MIPI_D0_L- EDP_AUX_MIPI_D0_L+ EDP_HPD_MIPI_PNL_RST_R TP_VSYNC_EDP1 +V3P3DX_EDP1_MIPI1 +V3P3S +V1P8_MIPI1 +VCC_EDP1_BKLT_R +V5P5R_MIPI1_AMOLED1 +V5PSN_MIPI1_AMOLED1 +VCC_MIPI1 A_DISPO_VLED_FB0 A_DISPO_VLED_FB1 A_DISPO_VLED_FB2 A_DISPO_VLED_FB3 A_DISPO_VLED_FB4 A_DISPO_VLED_FB5 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/37849595f775a6e7446f5dc5f5cd6bdf0f25ea3244abf60b1faffefe00c4fbe6.jpg) Figure 77: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver ![+V12_ATX C7E1 G33975-001 10UF 20% 25V X5R 0603 GND R7E3 G22026-041 10 1% 0.1W 2 RES 0603 L7E1 652666-125 10UH 20% 1.89A IND 2 +VCC_MIPI1_L SM +VCC_MIPI1_L CR7E1 A C MBRS340T3G DIO 3A SM C81983-001 R3R28 A93549-001 10 0% 0.0625W 2 EMPTY 0402 MIPI1_OVP_VOLT1 R3R30 A93549-001 10 0% 0.0625W 2 RES 0402 MIPI1_OVP_VOLT2 R3R24 A93548-412 1165K 1% 0.0625W 2 RES 0402 MIPI1_OVP_VOLT3 R3R23 A93548-222 174K 1% 0.0625W 2 RES 0402 MIP1_I_OVP_VOLT3 C3R9 G66843-002 4.7UF 10% 25V X7R 1206 GND IN MIP1I_EN IN MIP1I_PWM IN DISP BKLPWM_OUT_MDSI1 R3R16 0402 1 2 EMPTY GND R3R5 A93549-027 100K 5% 0.0625W RES 0402 GND +V12S_MIPI1_R_VIN 19 EU3R1 IC RT8532 VIN VDC 18 EN LX 15 PWM LIX 16 COMP OVP 17 MIP1 ISET 3 18 ISET MIX 12 MIPI1_OVP 4 MIPI1_MIX 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_OVP 1 2 MIP1_I_OVP 4 MIP1_I_OVP 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_OVP 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_BOP 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_COP 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_DSP 6 A DISP0_MIPI1_VLED_FB5_R_TI 7 A DISP0_MIPI1_VLED_FB4_R_TI 8 A DISP0_MIPI1_VLED_FB3_R_TI 9 A DISP0_MIPI1_VLED_FB2_R_TI 10 A DISP0_MIPI1_VLED_FB1_R_TI 11 A DISP0_MIPI1_VLED_FB0_R_TI 12 MIP1_I_DSP 6 A DISPO_MIPI1_VLED_FB5_R_TI 7 A DISPO_MIPI1_VLED_FB4_R_TI 8 A DISPO_MIPI1_VLED_FB3_R_TI 9 A DISPO_MIPI1_VLED_FB2_R_TI 10 A DISPO_MIPI1_VLED_FB1_R_TI 11 A DISPO_MIPI1_VLED_FB0_R_TI 12 MIP1_I_DSP 6 A DISPO_MIPI1_VLED_FB5_R_TI 7 A DISPO_MIPI1_VLED_FB4_R_TI 8 A DISPO_MIPI1_VLED_FB3_R_TI 9 A DISPO_MIPI1_VLED_FB2_R_TI 10 A DISPO_MIPI1_VLED_FB1_R_TI 11 A DISPO_MIPI1_VLEEDFB5_47PF_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_5V_nIEN IN MIPII_EN IN MIPII_PWM IN DISP BKLPWM_OUT_MDSI1 R3R86-0402 2 EMPTY GND IN DISP BKLPWM_OUT_MDSI1 R3R86-0402 2 EMPTY GND C3R4 A36096-112 0.1UF 10% 25V EMPTY Y402 C3R8 A93549-085 5.1K 5% 0.0625W RES 0402 MIPI I_COMP_19.6_R C3R9 A93548-450 22NF 2% 25V X7R Y402 A36096-089 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND BND FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FSEQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREV QFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQFQQFQFQFQFQFQFQQFQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFQQFDDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFFDFDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDFDDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFCFDPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCPPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPFCFPSFTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDTDFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDT DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFDTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV DFFFTV SFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFDFTDSFOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVT DOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTDOVTOOPTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUTOOTOUT OITOUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OIT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT OUT OFUT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT U NT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UNT UMTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUPTUptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt uptuptuptupt upt upt upt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt unt umt vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout v Out VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOut VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out V Out VOut](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/b202757091ef6d3bcd8aebfaa39dc0d00d18950eda2bfc2e8021c5b38cbfe6dc.jpg) Figure 78: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED ![+V3P3_ATX R8E6 0.01 1 2 +V3P3A_IN_MIPI1 EMPTY 0603 0.1W 1% D71825-002 R7E2 A93549-023 10K 5% 0.0625W RES 0402 V1P8_MIPI1_EN R8E4 1 2 0402 EMPTY 0 C8E4 A36096-125 10UF 20% 10V X5R 0402 GND IN MIPI1_BKLTEN_R C8E1 A36096-143 1UF 10% 25V X5R 0402 GND +V5MIPI1_L2 13 L8E1 G52290-004 2.2UH 0806 30% IND 1.2A +V5MIPI1_L1 15 L1 VAUX GND OUTN OUTN 2 3 MIP1_AUX 4 G84590-001 +V3P3_DUAL R3T3 1 RES 0 MIPI1_VDD_LS_VIN C3T7 A36096-112 0.1UF 10% 25V X7R 0402 GND +V3P3_DUAL C3T4 A36096-075 2.2NF 10% 50V X7R 0402 GND +V1P8_A C3T3 A36096-125 10UF 20% 10V X5R 0402 GND +V1P8_MIPI1 +V5P5P_MIPI1 R8E2 A93548-601 365K 1% 0.0625W RES 0402 R8E5 A93548-564 107K 1% 0.0625W RES 0402 R8E3 G21796-216 475K 1% 0.0625W RES 0402 +V5P5N_MIPI1 C7E3 A36096-125 10UF 20% 10V X5R 0402 GND +V3P3_DUAL U3T1 IC SLG7NT402V VDD ON CAP S GND GND +V1P8_A C3T3 A36096-125 10UF 20% 10V X5R 0402 GND +V1P8_MIPI1 +V3P3_DUAL MIP1_VDD_SR C3T4 A36096-075 2.2NF 10% 50V X7R 0402 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/6400596f193bfd480d25efe904a954b0f40a59bc28b1777fa7b2533621d63629.jpg) Figure 79: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight ![+V5_ATX R7G6 1 0 0402 RES VDD EDP1_BKLT C7G9 A36096-143 1UF 10% 25V X5R 0402 GND IN EDP_BKLT_EN_R 2 EU7G1 IC SLG55021-200010 VCC D G ON PG SHDN_N GND S THPAD GND G56246-001 +V12_ATX +VCC_EDP1_BKLT 5 7 EDP1_GATE_DRV 8 TP_EDP1_BKLT_PG 3 EDP1_EN_BKLT_SHDN# 6 IN Q7G1 MFET AON6500 J91717-001 +V3P3_ATX R7G5 1 0 0402 RES VDD EDP1_SUPPLY C7G8 A36096-112 0.1UF 10% 25V X7R 0402 GND U7G1 IC SLG5NT1458V VDD CAP 7 ON S 5 D GND 8 H10115-001 +V3P3DX_EDP1_SR_CAP C7G7 A36096-075 2.2NF 10% 50V X7R 0402 GND +V3P3DX_EDP1_MIPI1 IN EDP1_EN_BKLT_SHDN# C7G5 A36096-125 10UF 20% 10V X5R 0402 GND](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/04c2843561eafa46dfbf3a0aceeca8e8cae7f3c65d213e0b4eed04a680ac35ec.jpg) # 6.3. Appendix C: eSPI Header Example Figure 80: eSPI Header Example ![+V1P8_A +V3P3_A R9G3 1 2 EMPTY 0 0.1W 0603 A93552-004 0% R9G4 1 2 RES 0 0.1W 0603 A93552-004 0% C9G1 A36096-112 0.1UF 10% 25V X7R 0402 GND C9F2 A36096-112 0.1UF 10% 25V X7R 0402 GND J9G1 SCON HDR_2X14_K4_K21_K22 1 2 ESPI_CLK_HDR ESPI_CSO_HDR# PLTRST_1P8_ESPI# ESPI_IO3_HDR ESPI_IO0_HDR ESPI_SMB_CLK ESPI_RST_HDR# ESPI_ALERT1_HDR# ESPI_SMB_DATA ESPI_CS1_HDR# ESPI_ALERT0_HDR# ESPI_SMB_DATA ESPI_SMB_DATA ESPI_CS1_HDR# ESPI_ALERT0_HDR# ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMB_DATA ESPI_SMC_HDR# ESPI_CLK_HDR# ESPI_CSO_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# ESPI_CLK_HDR# EDesign NOTE: ALL PU AT COMPUTE MODULE SIDE IN BUF_PLT_RST 1.8# 1 2 PLTRST_1P8_ESPI# 0402 RES 0 0% 0.0625W A93549-001 R1U4 1 2 ESPI_ALERT0_HDR# ESPI_ALERT0_HDR# ESPI_ALERT1# 0402 RES 0 0% 0.0625W A93549-001 R9G6 1 2 ESPI_ALERT1_HDR# ESPI_CLSO_HDR# ESPI_CSO_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDR# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CS1_HDRL# ESPI_CSOHDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESPI_CSO_HDL# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESPI_CSO_HDR# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESIUS_LATL# R9F2 1 2 ESPI_CSO_HDR# ESIUS_LATL# R9F4 1 2 ESPI_IO3_HDR# ESIUS_LATL# R9F4 1 2 ESPI_IO3_HDR# ESIUS_LATL# R9F4 1 2 ESPI_CLK_HDR# ESIUS_LATL# R9F4 1 2 ESPI_CLK_HDR# ESIUS_LATL# R9F4 1 2 ESPI_CLK_HDR# ESIUS_LATL# R9F4 1 2 ESPI_CLK_HDR# ESIUS_LATL# R9F4 1 2 ESPI_CLK_HDR# ESIUS_LATL# R9F4 1 2 ESPI_RST_HDR# ESIUS_LATL# R9F4 1 2 ESPI_RST_HDR# ESIUS_LATL# R9F4 1 2 ESPI_RST_HDR# ESIUS_LATL# R9F4 1 2 ESPI_RST_HDR# ESIUS_LATL# R9F4 1 2 ESPI_RST_HDR# ESIUS_LATL#](.PICMG_COM-HPC_Carrier_Design_Guide_R2.2/fc5f49c458a4b609698e7b39c556bdd20833a15f5b394d830999f41e67e65771.jpg) # 6.4. Appendix D: Useful Books – General x86 Computer Topics Table 35: General Books on x86 Computer Topics
TitleAuthorNote
PCI Express System ArchitectureRavi Budruk, Don Anderson, Tom Shanleywww.mindshare.com
PCI System Architecture (4th Edition)Tom Shanley, Don Andersonwww.mindshare.com
Universal Serial Bus System ArchitectureDon Andersonwww.mindshare.com
SATA Storage TechnologyDon Andersonwww.mindshare.com
Protected Mode Software Architecture (The PC System Architecture Series)Tom Shanleywww.mindshare.com
The Unabridged Pentium 4Tom Shanleywww.mindshare.com
Building the Power-Efficient PC: A Developer's Guide to ACPI Power Management, First EditionJerzy Kolinski, Ram Chary, Andrew Henroid, and Barry PressIntel Press, 2002, ISBN 0-9702846-8-3
Hardware BibleWinn L. RoschSAMS, 1997, 0-672-30954-8
The Indispensable PC Hardware BookHans-Peter MessmerAddison-Wesley, 1994, ISBN 0-201-62424-9
The PC Handbook: For Engineers, Programmers, and Other Serious PC Users, Sixth EditionJohn P. Choisser and John O. FosterAnnabooks, 1997, ISBN 0-929392-36-1
PC Hardware in a Nutshell, 3rd EditionRobert Bruce Thompson and Barbara Fritchman ThompsonO'Reilly, 2003, ISBN 0-596-00513-X
PCI & PCI-X Hardware and Software Architecture & Design, Fifth EditionEdward Solari and George WillseAnnabooks, Intel Press, 2001, ISBN 0-929392-63-9
PCI System ArchitectureTom Shanley and Don AndersonAddison-Wesley, 2000, ISBN 0-201-30974-2
PCI Express Electrical Interconnect Design: Practical Solutions for Board-level Integration and Validation, First EditionDave Coleman, Scott Gardiner, Mo-hamad Kolberhdari, and Stephen Pe-tersIntel Press, 2005, ISBN 0-9743649-9-1
Introduction to PCI Express: A Hardware and Software Devel-oper's Guide, First EditionAdam Wilen, Justin Schade, and Ron ThornburgIntel Press, 2003, ISBN 0-9702846-9-1
Serial ATA Storage Architecture and Applications, First EditionKnut Grimsrud and Hubbert SmithIntel Press, 2003, ISBN 0-9717861-8-6
USB Design by Example, A Practical Guide to Building I/O Devices, Second EditionJohn HydeIntel Press, ISBN 0-9702846-5-9
Universal Serial Bus System Architecture, Second EditionDon Anderson and Dave DzatkoMindshare, Inc., ISBN 0-201-30975-0
Printed Circuits Handbook, Fourth EditionClyde F. Coombs Jr.McGraw-Hill, 1996, ISBN 0—07-012754-9
High Speed Signal Propagation, First EditionHoward Johnson and Martin GrahamPrentice Hall, 2003, ISBN 0-13-084408-X
High Speed Digital Design: A Handbook of Black Magic, First EditionHoward JohnsonPrentice Hall, ISBN: 0133957241
C Programmer's Guide to Serial Communications, Second Edi-tionJoe CampbellSAMS, 1987, ISBN 0-672-22584-0
The Programmer's PC Sourcebook, Second EditionThom HoganMicrosoft Press, 1991, ISBN 1-55615-321-X
The Undocumented PC, A Programmer's Guide to I/O, CPUs, and Fixed Memory AreasFrank van GilluweAddison-Wesley, 1997, ISBN 0-201-47950-8
VHDL Modeling for Digital Design SynthesisYu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu and Eric S. LinKluwer Academic Publishers, 1995, ISBN: 0-7923-9597-2
# 6.5. Appendix E: Revision History Table 36: Revision History
Release RevDateAuthorNotes / Changes
1.0Mar 17, 2021C. EderCDG preliminary version with Ethernet KR and KR4 CEI diagrams.
2.0Jan 14, 2022S. MilnorC. EderRelease Candidate for first version of complete COM-HPC CDG.
Revise Figure 35 to show a 50V capacitor for C4V20Revise Figure 41 to show a 50V capacitor for C5W7Section 3.14.1. Page 96 – insert short statement about adding HD Audio support to pending COM-HPC Base Spec Rev 1.1 due to lack of SoundWire supportRemove references to code names for unreleased Intel products ADL and ICLRevise code name references to show only Intel document numbers
Incorporate nVent Change Requests
Change Rev to RC2.0c, change date, re-issue. No other changes.
Add note to Figure 39 (USB4 ESD diodes) explaining diode positioningReplace Figures 67 and 73 (JSOM diagrams) with revised Figures that call out metric M2.5 hardware rather than 4-40 Imperial hardware
Formal PICMG release of CDG Revision 2.0
2.1Aug 10, 2023S. MilnorC. EderSection 4.3.3 SATA Design Rule SummaryDelete erroneous requirements in Ref lines 7 and 8Renumber Rev 2.0 Ref lines 9, 10, 11, 12 to Rev 2.1 Ref lines 7, 8, 9, 10Remove TX pair to RX pair length matching requirement(Ref line 9 in Rev 2.0, Ref line 7 in Rev 2.1)Section 4.3.4 PCIe Design Rule SummaryRemove TX pair to RX pair length matching requirement (Ref line 8)Add missing information on serpentine trace distance to self (Ref line 11)
Updated Figure 8 (CEI Marvel 88E1543 “Alaska” typo)Updated copyright claims to include year 2022Update Samtec patent claims in Sections 1.71 and 1.72This is per request from Samtec patent lawyer on 4/25/2022
Section 1.7.2. Page 11 Update Samtec “Unnecessary” patent claims per 3/3/2023 and 3/27/2023 input from SamtecSection 1.7.4. Page 12 Add year 2023 to Copyright claimCopyright updated to include 2023 in various other parts of the documentSection 1.8. Pages 14 and 13Correct PCI and PCIe abbreviation explanation (“Interconnect” not “Interface”)Fully expand the SATA abbreviation explanation (“Advanced Technology” instead of “AT”)Section 3.6.9. Page 57 Add two PCIe Gen 5 capable redriver parts to Table 9Section 3.10. Page 86 Correct HPD level translator IC reference from U54 to U49
Formal PICMG release of CDG Revision 2.1USB4 schematics (Figures 36 through 41) deliberately blurred to satisfy Intel NDA concerns
2.2Feb 16, 2024S. MilnorC. EderAdd numerous notes in a distinctive bold blue italic font explaining design notes for COM-HPC MiniRemove references to the Intel JHL8040R “Burnside Bridge” USB4 retimerAdd in references to the Intel JHL9040R “Hayden Bridge” USB4 retimerRemove detailed USB4 schematics (Figures 36 through 41) due to Intel NDA concernsAdd in an Intel provided Hayden Bridge USB4 block diagram for the COM-HPC Client (Figure 36)Add in an Intel provided Hayden Bridge USB4 block diagram for the COM-HPC Mini (Figure 37)Figure numbering and caption details are different between from Figure 36 on in this revision relative to Rev. 2.1Update Module Type Detection Table in Section 3.24. to include the Mini (Table 21)Add a new Figure for COM-HPC Type detection for the Mini (Figure 57 in revision 2.2)
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