## Slide 1 ![REVISION B DO NOT SCALE FROM THIS PRINT DESIGNED AND DIMENSIONED IN MILLIMETERS(INCHES) ALL DIMENSIONS REFERENCE EXCEPT AS SHOWN SOME CENTER FEATURES NOT SHOWN FOR CLARITY 68.62±0.08 (2.701±.003) C PIN D01 0.400 (.0157) D C B A 9.00±0.05 (.354±.002) 3 2 1 PIN A01 C 0.00 (.000) 0.13 (.005) 3.86 (.152) 0.74 (.029) (2 PCS) 3.66±0.08 (.144±.003) Ø29.81 (1.174) Ø8.99 (.354) C 0.635 (.0250) (TYP) (NON ACCUM) 62.87 (2.475) (99 EQ SPCS @ 0.635 (.0250)) 67.12 (2.642) 0.600 (.0236) 0.800 (.0315) 1.300 (.0512) 0.41 (.016) (TYP) Ø0.800 (.0315) 2.20 (.087) (TYP) 2.40 (.094) 6.80 (.268) C NOTES: 1. NOTE DELETED. 2. PARTS TO BE PACKAGED IN TAPE & REEL. 3. SEE SHT 2 FOR PROCESSING INFORMATION. 4. ORDERS WILL BE PACKAGED ACCORDING TO THE SAMTEC PACKAGING EFFICIENCY STANDARDS (SPES) FOUND ON WWW.SAMTEC.COM 5. ATTACH LABEL-4X2 TO EACH TAPE & REEL PACKAGE. 6. K-DOT PROVIDED AS STANDARD. 7. MEASURE BOTH OUTSIDE ROWS ONLY. PROPRIETARY NOTE THIS DOCUMENT CONTAINS CONFIDENTIAL AND PROPRIETARY INFORMATION AND ALL DESIGN, MANUFACTURING, REPRODUCTION, USE, PATENT RIGHTS AND SALES RIGHTS ARE EXPRESSLY RESERVED BY SAMTEC, INC. THIS DOCUMENT SHALL NOT BE DISCLOSED, IN WHOLE OR PART, TO ANY UNAUTHORIZED PERSON OR ENTITY NOR REPRODUCED, TRANSFERRED OR INCORPORATED IN ANY OTHER PROJECT IN ANY MANNER WITHOUT THE EXPRESS WRITTEN CONSENT OF SAMTEC, INC. DO NOT SCALE DRAWING SHEET SCALE: 4:1 MATERIAL: INSULATOR: ICP; COLOR: NATURAL CONTACT: COPPER ALLOY PLATING: CONTACT AREA: .000010' GOLD OVER .000050' NICKEL REMAINDER: .000200' REF TIN OVER .000050' NICKEL F:\DWG\MISC\MKTG\ASP-209946-01-MKT.SLDDRW samtec 520 PARK EAST BLVD., NEW ALBANY, IN 47150 PHONE: 812-944-6733 FAX: 812-948-5047 e-Mail: info@SAMTEC.com code_55322 DESCRIPTION: CUSTOM COM HPC FEMALE ASSEMBLY DWG. NO. ASP-209946-01 BY: J. BROWNING 01/16/2019 SHEET 1 OF 2](.picmg-com-hpc-carrier-design-guide-alt/slide-001.jpg) ## Slide 2 ![This slide is a technical engineering drawing containing three main sections: a PCB layout, a processing view, and a stencil layout, along with a title block. **Top Left Section: Recommended PCB Layout** * **Header:** 'REVISION B' * **Dimensions:** * Horizontal: '68.62(2.701)', '67.12(2.642)', '62.865(2.4750)' * Vertical/Horizontal details: '2.10(.083) (4 PLCS)', '0.40(.016) (2 PLCS)', '9.00(.354)' * Left side vertical: '6.80(.268)', '2.40(.094)', '2.20(.087) (TYP)', '1.300(.0512)', '0.89(.035) x 45° (2 PLCS)' * Bottom horizontal: '0.635(.0250) (TYP)' * **Labels:** 'D100', 'D01', 'A100', 'A01', '3 2 1', 'A', 'B', 'C', 'D', 'CL' (Centerline). * **Hole/Pin Specs:** 'Φ0.975±0.050(.0384±.0020) NPTH (2 PLCS)', 'Φ0.356±0.020(.0140±.0008) (TYP)' * **Note:** 'CONNECTOR OUTLINE OTHER COMPONENTS ON PCB SHALL AVOID THIS ZONE.' * **Footer:** 'RECOMMENDED PCB LAYOUT ALL DIMENSIONS SYMMETRIC ABOUT CENTERLINE' **Top Right Section: Processing View** * **Diagram:** A side profile view of the connector assembly. * **Dimension:** '9.936(.3912) (BEFORE PROCESSING HEIGHT)' * **Header:** 'PROCESSING VIEW' * **Text:** 'DIMENSION INDICATES CONNECTOR/FIXTURE HEIGHT ON PCB TO GUARANTEE ENOUGH REFLOW OVEN WORKING SPACE. DIMENSION, PCB THICKNESS, AND THE HEIGHT OF THE COMPONENTS ON THE OTHER SIDE OF THE BOARD NEED TO BE CONSIDERED.' **Bottom Section: Recommended Stencil Layout** * **Diagram:** Top-down view of solder paste stencil openings. * **Dimensions:** '62.865(2.4750)', '6.80(.268)', '2.40(.094)', '2.20(.087) (TYP)', '0.635(.0250) (TYP)', 'Φ0.356±0.020(.0140±.0008) (TYP)' * **Footer:** 'RECOMMENDED STENCIL LAYOUT ALL DIMENSIONS SYMMETRIC ABOUT CENTERLINE (STENCIL TO BE 0.125(.0050) THICK)' **Bottom Right Section: Title Block** * **Proprietary Note:** 'PROPRIETARY NOTE THIS DOCUMENT CONTAINS CONFIDENTIAL AND PROPRIETARY INFORMATION AND ALL DESIGN, MANUFACTURING, REPRODUCTION, USE, PATENT RIGHTS AND SALES RIGHTS ARE EXPRESSLY RESERVED BY SAMTEC, INC. THIS DOCUMENT SHALL NOT BE DISCLOSED, IN WHOLE OR PART, TO ANY UNAUTHORIZED PERSON OR ENTITY NOR REPRODUCED, TRANSFERRED OR INCORPORATED IN ANY OTHER PROJECT IN ANY MANNER WITHOUT THE EXPRESS WRITTEN CONSENT OF SAMTEC, INC.' * **Scale:** 'SHEET SCALE: 2:1' * **Logo/Company:** 'samtec', '520 PARK EAST BLVD. NEW ALBANY, IN 47150', 'PHONE: 812-944-6733 FAX: 812-948-5047', 'e-Mail info@SAMTEC.com code 55322' * **Description:** 'DESCRIPTION: CUSTOM COM HPC FEMALE ASSEMBLY' * **Drawing Number:** 'DWG. NO. ASP-209946-01' * **Author/Date:** 'BY: J. BROWNING 01/16/2019 SHEET 2 OF 2' * **File Path:** 'F:\DWG\MISC\MKTG\ASP-209946-01-MKT.SLDDRW'](.picmg-com-hpc-carrier-design-guide-alt/slide-002.jpg) ## Slide 3 ![The slide is a title page for a document. The content is as follows: **COM+HPC®** **COM-HPC® Carrier Design Guide** *Guidelines for Designing COM-HPC® Carrier Boards* **December 7, 2021** **Rev. RC2.0d** This Design Guide is not a specification. It provides COM-HPC® Carrier implementation information but does not replace the PICMG COM-HPC® specification. The full COM-HPC® specification is needed in conjunction with this Design Guide for signal descriptions, signal integrity information and loss budgets, Module and Carrier connector pin-outs, PCB mechanical details and more. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 1/159](.picmg-com-hpc-carrier-design-guide-alt/slide-003.jpg) ## Slide 4 ![© Copyright 2021, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG® specifications may require use of an invention covered by patent rights. PICMG® shall not be responsible for identifying patents for which a license may be required by any PICMG® specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). IMPORTANT NOTICE: This document includes references to specifications, standards or other material not created by PICMG. Such referenced materials will typically have been created by organizations that operate under IPR policies with terms that vary widely, and under process controls with varying degrees of strictness and efficacy. PICMG has not made any enquiry into the nature or effectiveness of any such policies, processes or controls, and therefore ANY USE OF REFERENCED MATERIALS IS ENTIRELY AT THE RISK OF THE USER. Users should therefore make such investigations regarding referenced materials, and the organizations that have created them, as they deem appropriate. PICMG®, COM-HPC®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COM-HPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, μTCA and ATCA logos are registered trademarks, and cPCI Serial Space™, xTCA™, IRTM™ and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 2/159](.picmg-com-hpc-carrier-design-guide-alt/slide-004.jpg) ## Slide 5 ![**Table of Contents** **1. Preface**........................................................................................................................................9 1.1. About This Document............................................................................................................9 1.2. Intended Audience...............................................................................................................9 1.3. No Special Word Usage.......................................................................................................9 1.4. No Statements of Compliance.............................................................................................9 1.5. Correctness Disclaimer.........................................................................................................9 1.6. Name and Logo Usage...........................................................................................................9 1.7. Intellectual Property............................................................................................................11 1.7.1. Necessary IPR Claims (Referring to Mandatory or Recommended Features)...........11 1.7.2. Unnecessary Claims.......................................................................................................12 1.7.3. Third Party Disclosures...................................................................................................12 1.7.4. Copyright Notice.............................................................................................................12 1.7.5. Trademarks.....................................................................................................................12 1.8. Acronyms, Abbreviations and Definitions Used.................................................................13 1.9. Applicable Documents and Standards...............................................................................16 **2. COM-HPC Interfaces**..............................................................................................................18 2.1. COM-HPC Client and Server Pinout Differences...............................................................18 **3. Reference Schematics and Block Diagrams**........................................................................22 3.1. Sources for Technical Materials..........................................................................................22 3.2. Schematic Conventions........................................................................................................22 3.3. Ethernet NBASE-T..............................................................................................................23 3.4. Ethernet KR and KR4..........................................................................................................24 3.4.1. Ethernet KR CEI Block Diagrams..................................................................................24 3.4.2. PHY Addresses..............................................................................................................32 3.5. Serial ATA............................................................................................................................33 3.5.1. Cabled SATA...................................................................................................................33 3.5.2. mSATA SSDs..................................................................................................................34 3.5.3. M.2 SATA SSDs..............................................................................................................34 3.6. PCI Express..........................................................................................................................35 3.6.1. General Notes................................................................................................................35 3.6.2. PCI Express Coupling Capacitor Locations....................................................................36 3.6.3. PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key......37 3.6.4. Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High...............42 3.6.5. PCIe x16 Slot Card Site on PCIe Group 1.....................................................................45 3.6.6. PCIe Group 2..................................................................................................................46 3.6.7. MXM-3 Graphics Card Module on Carrier....................................................................50 3.6.8. PCIe Reference Clocks....................................................................................................51 3.6.9. PCIe Redrivers and Retimers.........................................................................................56 3.7. USB........................................................................................................................................57 3.7.1. USB Terms and General Information............................................................................57 3.7.2. USB 2.0 Type-A Example..............................................................................................59 3.7.3. USB 3.2 Gen 1 and Gen 2 Type-A..................................................................................60 3.7.4. USB 3 Redrivers..............................................................................................................60 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 3/159](.picmg-com-hpc-carrier-design-guide-alt/slide-005.jpg) ## Slide 6 ![**3.7.5. USB Type-C Overview......................................................................................................................61** **3.7.6. USB Type-C Port Multiplexers............................................................................................................65** **3.7.7. USB Type-C Power Delivery Controllers............................................................................................66** **3.7.8. USB Type-C Port Protection Components..........................................................................................67** **3.7.9. USB 3.2 Gen 2x1 Type-C Basic Implementation.................................................................................68** **3.7.10. USB 3.2 Gen 2x2 Type-C Example Implementation...........................................................................70** **3.7.11. USB4..................................................................................................................................................76** **3.8. Boot SPI on Carrier.................................................................................................................................82** **3.9. eSPI.......................................................................................................................................................86** **3.10. DisplayPort Over DDI...........................................................................................................................87** **3.11. HDMI Over DDI....................................................................................................................................90** **3.12. eDP.....................................................................................................................................................92** **3.12.1. eDP / DP Conversions to Other Video Formats...............................................................................94** **3.13. MIPI-CSI Camera Interface.................................................................................................................95** **3.14. Audio Interfaces...................................................................................................................................96** **3.14.1. General Discussion........................................................................................................................96** **3.14.2. MIPI SoundWire Summary...............................................................................................................96** **3.14.3. I2S Implementations on COM-HPC..................................................................................................99** **3.15. Asynchronous Serial Port Interfaces......................................................................................................100** **3.15.1. COM-HPC UART Interfaces.............................................................................................................100** **3.15.2. Legacy Compatibility With 16C550 UART Register Set.....................................................................101** **3.15.3. Alternative / Additional Carrier Board UART Implementations..........................................................102** **3.16. I2C / I3C Ports.....................................................................................................................................103** **3.16.1. I2C Addressing................................................................................................................................104** **3.16.2. I2C0 Example: Carrier I2C Device in S0 Power Domain...................................................................105** **3.16.3. I2C Bus Buffers / Level Translators.................................................................................................105** **3.16.4. I2C1 (COM-HPC) and Optional I3C Support...................................................................................106** **3.17. Port 80h Debug Display Over COM-HPC USB_PD_I2C......................................................................107** **3.18. Carrier BMC with IPMB Link to Module..............................................................................................108** **3.19. General Purpose SPI...........................................................................................................................112** **3.20. Rapid Shutdown..................................................................................................................................112** **3.21. Thermal Protection..............................................................................................................................113** **3.22. System Management Bus (SMBus).......................................................................................................114** **3.23. General Purpose Inputs / Outputs.........................................................................................................115** **3.24. Module Type Detection and Protection..................................................................................................116** **4. PCB Design Rule Summaries...................................................................................................................118** **4.1. High Speed PCB Design Information – Design Guides and Books................................................................118** **4.1.1. Intel and AMD Design Guides.............................................................................................................118** **4.1.2. Books on High Speed PCB Design Principles.....................................................................................119** **4.2. High Speed Serial Interfaces – General PCB Design Rules......................................................................120** **4.3. PCB Design Rule Summaries - High Speed Differential Pair Serial Interfaces..........................................123** **4.3.1. NBASE-T Design Rule Summary.........................................................................................................123** **4.3.2. Ethernet KR Design Rule Summary.....................................................................................................124** **4.3.3. SATA Design Rule Summary...............................................................................................................125** **4.3.4. PCIe Design Rule Summary................................................................................................................126** **4.3.5. USB 2.0 Design Rule Summary...........................................................................................................127** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 4/159](.picmg-com-hpc-carrier-design-guide-alt/slide-006.jpg) ## Slide 7 ![4.3.6. USB 3.2 and USB4 Design Rule Summaries..................................................................................................................................128 4.3.7. DisplayPort Design Rule Summary.................................................................................................................................130 4.3.8. eDP Design Rule Summary.............................................................................................................................................131 4.3.9. HDMI Design Rule Summary..........................................................................................................................................132 4.4. PCB Design Rules for Single Ended (SE) Interfaces..........................................................................................................133 5. Mechanical Considerations......................................................................................................................................................134 5.1. Heat Spreader / Module / Carrier Attachment Details..........................................................................................................134 5.1.1. Heat Spreader to Module Attachment Notes.................................................................................................................134 5.1.2. Heat Spreader / Module Assembly Attachment to Carrier and Chassis..........................................................................135 5.2. Alternative COM-HPC Board Stack Assembly Suggestion..............................................................................................140 5.2.1. Precision Jack Screw Standoffs......................................................................................................................................140 5.3. Carrier Board Stiffener.........................................................................................................................................................142 6. Appendices................................................................................................................................................................................146 6.1. Appendix A: Synchronous Ethernet.................................................................................................................................146 6.2. Appendix B: Alternative eDP Example.........................................................................................................................150 6.3. Appendix C: eSPI Header Example...............................................................................................................................157 6.4. Appendix D: Useful Books – General x86 Computer Topics............................................................................................158 6.5. Appendix E: Revision History..........................................................................................................................................159 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 5/159](.picmg-com-hpc-carrier-design-guide-alt/slide-007.jpg) ## Slide 8 ![**Index of Tables** Table 1: Acronyms, Abbreviations and Definitions Used....................................................................................13 Table 2: Client and Server Type Pinout Difference Table....................................................................................18 Table 3: Power Net Naming...............................................................................................................................22 Table 4: MDIO Addresses for Intel POR External PHYs....................................................................................32 Table 5: mSATA Pin Mapping Relative to miniPCIe..........................................................................................34 Table 6: PCIe Maximum Allowable Clock Jitter................................................................................................51 Table 7: PCIe Clock Buffer Modes....................................................................................................................52 Table 8: PCIe Clock Buffer Vendors and Part Numbers....................................................................................53 Table 9: PCIe Redrivers and Retimers..............................................................................................................56 Table 10: USB.org Branding Term Summary....................................................................................................57 Table 11: USB Type-A Pin-Out........................................................................................................................58 Table 12: USB 3 Redrivers..................................................................................................................................60 Table 13: USB Type-C Connector Pin-out........................................................................................................62 Table 14: USB Type-C Port Multiplexers – Possible Modes............................................................................65 Table 15: Boot SPI Socket Suggestions............................................................................................................84 Table 16: DisplayPort Redrivers and Retimers..................................................................................................89 Table 17: SoundWire Audio CODECs..............................................................................................................97 Table 18: Alternative / Additional Carrier Board UART Implementations........................................................102 Table 19: I2C Operating Modes.......................................................................................................................103 Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation.......................................................105 Table 21: COM-HPC Type Definitions............................................................................................................116 Table 22: Intel and AMD Design Guides..........................................................................................................118 Table 23: General Design Rules for High Speed Serial interfaces....................................................................121 Table 24: NBASE-T Design Rule Summary......................................................................................................123 Table 25: Ethernet KR Design Rule Summary.................................................................................................124 Table 26: SATA Design Rule Summary............................................................................................................125 Table 27: PCIe Design Rule Summary.............................................................................................................126 Table 28: USB 2.0 Design Rule Summary........................................................................................................127 Table 29: USB 3.2 and USB4 Design Rule Summaries.....................................................................................128 Table 30: DisplayPort Design Rule Summary.................................................................................................130 Table 31: HDMI Design Rule Summary...........................................................................................................132 Table 32: Design Rules for Single Ended Interfaces........................................................................................133 Table 33: SDP Use in Figure Above...............................................................................................................148 Table 34: SyncE / PTP Matrix.........................................................................................................................149 Table 35: General Books on x86 Computer Topics........................................................................................158 Table 36: Revision History.............................................................................................................................159 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 6/159](.picmg-com-hpc-carrier-design-guide-alt/slide-008.jpg) ## Slide 9 ![**Table of Figures** Figure 1: Schematic Conventions...................................................................................22 Figure 2: NBASE-T...........................................................................................................23 Figure 3: Intel SoC with CEI Boundary...........................................................................25 Figure 4: Intel CEI 4x SFP28...........................................................................................26 Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827...............................................27 Figure 6: Intel CEI QSFP28 with Retimer C827/XL827...............................................28 Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4.......................................29 Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543...............................30 Figure 9: AMD SoC 4xSFP+ with CS4223 Retimer......................................................31 Figure 10: Serial ATA - Cabled..........................................................................................33 Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded)...36 Figure 12: PCIe Device Down on Carrier – PCIe Group 0 Low – PCIe Lane 0...........37 Figure 13: Mini-PCIe Site – PCIe Group 0 Low – PCIe Lane 1......................................38 Figure 14: M.2 E-Key Site – WiFi Cards – PCIe Group 0 Low – PCIe Lane 2...........39 Figure 15: M.2 B-Key Site – Cell Modem Cards – PCIe Group 0 Low – PCIe Lane 3..40 Figure 16: Clock and Reset Buffers for PCIe Group 0 Low Example Circuits.............41 Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11................................................................................................................42 Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 PCIe Lanes 12:15........43 Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High.......................................................................................................................44 Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31..................45 Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39....................46 Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43....................47 Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47....................48 Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example.............49 Figure 26: USB 2.0 Type-A Example..............................................................................59 Figure 27: USB Type-C Receptacle and Plug Images....................................................62 Figure 28: USB Type-C Receptacle Pin-Out – Looking Into Carrier Receptacle.........62 Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2...............69 Figure 30: USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A.......................................................................................................................70 Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver...........71 Figure 32: USB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD Protection...72 Figure 33: USB 3.2 Gen 2x2 Type-C (4 of 6): Port Port Mux / Redriver Coupling Capacitors.......................................................................................................................73 Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller.....74 Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection.......................................................................................................................75 Figure 36: USB4 on COM-HPC USB Port 2 (Fig 1 of 6): COM-HPC Side RX Coupling Caps.......................................................................................................................76 Figure 37: USB4 on COM-HPC USB Port 2 (Fig 2 of 6): Intel JHL8040R Thunderbolt Retimer Part 1.......................................................................................................................77 Figure 38: USB4 on COM-HPC USB Port 2 (Fig 3 of 6): Intel JHL8040R Thunderbolt Retimer Part 2.......................................................................................................................78 Figure 39: USB4 on COM-HPC USB Port 2 (Fig 4 of 6): Output Coupling and Protection.......................................................................................................................79 Figure 40: USB4 on COM-HPC USB Port 2 (Fig 5 of 6): Power Delivery Controller...80 Figure 41: USB4 on COM-HPC USB Port 2 (Fig 6 of 6): Type-C Connector and USB Port Protector.......................................................................................................................81 Figure 42: Boot SPI on Carrier (Example 1)....................................................................82 Figure 43: Boot SPI on Carrier – Socketed Flash and Multiplexer to External Programmer.......................................................................................................................85 Figure 44: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device.......................................................................................................................86 Figure 45: DisplayPort Over DDI......................................................................................87 Figure 46: HDMI Over DDI................................................................................................90 Figure 47: eDP Schematic Example..................................................................................92 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 7/159](.picmg-com-hpc-carrier-design-guide-alt/slide-009.jpg) ## Slide 10 ![Figure 48: eDP Connector Pin Numbering............................................................................................93 Figure 49: MIPI-CSI.................................................................................................................................95 Figure 50: MIPI SoundWire Routing Topologies.......................................................................................98 Figure 51: MIPI SoundWire Point to Point Connection With SI Components..........................................98 Figure 52: UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports...........................101 Figure 53: I2C0 Example: Carrier EEPROM in S5 Power Domain.........................................................104 Figure 54: I2C0 Example: Carrier Temperature Sensor in S0 Power Domain.......................................105 Figure 55: Port 80h Debug Display Over COM-HPC USB_PD_I2C......................................................107 Figure 56: Carrier BMC with IPMB Link to Module – Sheet 1............................................................109 Figure 57: Carrier BMC with IPMB Link to Module – Sheet 2............................................................110 Figure 58: Carrier BMC with IPMB Link to Module – Sheet 3............................................................111 Figure 59: Module Type Detection / Protection – ATX Power Supply and Client Type Module / Carrier....117 Figure 60: Module Type Detection / Protection – AT Power Supply and Server Type Module / Carrier....117 Figure 61: PCB Cross Section Terms and Notations............................................................................120 Figure 62: Vendor Specific Heat Spreader to Module Attachment – Bottom Side Module PCB Access...134 Figure 63: Heat Spreader Assembly Mounting to Carrier – Bottom Side Screw Access......................135 Figure 64: Heat Spreader Assembly Mounting to Carrier – Top Side Screw Access............................136 Figure 65: Heat Spreader Assembly Mounting to Carrier With Broaching Nut – Top Side Screw Access...137 Figure 66: Heat Spreader Assembly Mounting to Carrier and Chassis – Top Side Screw Access..........138 Figure 67: JSOM (Jack Screw Standoff – Micro) Diagram and Application Cutaway...........................140 Figure 68: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns...141 Figure 69: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware......................................141 Figure 70: FEM Simulation Results – 0.0625” FR4 Carrier – No Stiffener........................................142 Figure 71: Mechanical Carrier Stiffener Possibility.............................................................................143 Figure 72: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier)....................................144 Figure 73: Application Specific Part Number (ASP) Reference Guide................................................145 Figure 74: Synchronous Ethernet Overview......................................................................................147 Figure 75: Synchronous Ethernet Example Implementation................................................................148 Figure 76: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options – eDP and DSI............151 Figure 77: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options...................................152 Figure 78: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly...............153 Figure 79: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver.........................................154 Figure 80: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED.............155 Figure 81: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight..........156 Figure 82: eSPI Header Example........................................................................................................157 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 8/159](.picmg-com-hpc-carrier-design-guide-alt/slide-010.jpg) ## Slide 11 ![Preface **1. Preface** **1.1. About This Document** This document provides information for designing project specific Carrier Boards for systems using COM-HPC Modules. This document is a design guide and not a specification document. It should be used by together with the **COM-HPC Base Specification**, with other industry specifications (listed in Section 1.9 below), with silicon and component vendor’s documentation and with your COM-HPC Module vendor’s product documentation. The PICMG **COM Express Carrier Board Design Guide** is also a very useful additional source of information. The COM-HPC and COM Express pin names are not the same, but it is not hard to correlate them. The COM Express design guide document is available for free download on the public PICMG website (www.picmg.org). No membership is required to down load the design guides. **1.2. Intended Audience** This design guide is intended for electronics engineers and PCB layout engineers designing Carrier Boards for PICMG COM-HPC Modules. It may also be useful to COM-HPC Module designers for them to better understand how COM-HPC Modules are used, and to understand how some of the design rules (trace length recommendations, trace length matching recommendations etc.) are shared between Module and Carrier designs. **1.3. No Special Word Usage** Unlike a PICMG specification, which assigns special meanings to certain words such as 'shall', 'should' and 'may', there is no such usage in this document. That is because this document is not a specification; it is a non-normative design guide. **1.4. No Statements of Compliance** As this document is not a specification but a set of guidelines, there should not be any statements of compliance made with reference to this document. **1.5. Correctness Disclaimer** The schematic examples given in this document are believed to be correct but no guarantee is given. **1.6. Name and Logo Usage** The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows: Permission to use the PICMG® organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at www.picmg.org) during the period of time for which their membership dues are paid. Nonmembers may not use the PICMG® organization logo. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 9/159](.picmg-com-hpc-carrier-design-guide-alt/slide-011.jpg) ## Slide 12 ![Preface The PICMG® organization logo must be printed in black or color as shown in the files available for download from the member's side of the Web site. Logos with or without the “Open Modular Computing Specifications” banner can be used. Nothing may be added or deleted from the PICMG® logo. The use of the COM-HPC® logo is a privilege granted by the PICMG® organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and that believe their products comply with these specifications. Manufacturers’ distributors and sales representatives may use the COM-HPC® logo in promoting products sold under the name of the manufacturer. Use of the logos by either members or non-members implies such compliance. Only PICMG Executive and Associate members may use the PICMG® logo. PICMG® may revoke permission to use logos if they are misused. The COM-HPC® logo can be found on the PICMG web site, www.picmg.org. The COM-HPC® logo must be used exactly as shown in the files available for download from the PICMG® Web site. The aspect ratios of the logos must be maintained, but the sizes may be varied. Nothing may be added to or deleted from the COM-HPC® logo. The PICMG® name and logo and the COM-HPC® name and logo are registered trademarks of PICMG®. Registered trademarks must be followed by the ® symbol, and the following statement must appear in all published literature and advertising material in which the logo appears: PICMG, the COM-HPC® name and logo and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 10/159](.picmg-com-hpc-carrier-design-guide-alt/slide-012.jpg) ## Slide 13 ![Preface 1.7. Intellectual Property The PICMG Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ('IPR'). The PICMG Consortium takes no position concerning the evidence, validity or scope of this IPR. The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-Members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium. Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. The Consortium shall not be responsible for identifying any or all such IPR. No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification. This specification conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made: 1.7.1. Necessary IPR Claims (Referring to Mandatory or Recommended Features) Samtec Inc. has the following patents, which may cover some aspects of the PICMG® COM-HPC® Module and Carrier Board Connectors Contact Samtec Inc. for further information. * CN 201921051845.8 'Connector With Top and Bottom Stitched Contacts' * CN 201910602689.8 'Connector With Top and Bottom Stitched Contacts' * EP 007814686 'Connectors' * TW 108208806 'Connector With Top and Bottom Stitched Contacts' * TW 108123806 'Connector With Top and Bottom Stitched Contacts' * TW 109300856 'Connector' * US 29/709518 'Connector' * PCT/US2019/040584 * Global 29/652014 * Global 62/704031 * Global 62/704038 Samtec Inc. has the following patents, which may cover some aspects of the JSOM standoffs shown in Section 5.2.1 of this document: 'Two-Piece Unmate-Assist Standoff' * CN201480061913.2 * DE112014005338.4 (pending) * TWM505072 * US9374900 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 11/159](.picmg-com-hpc-carrier-design-guide-alt/slide-013.jpg) ## Slide 14 ![**Preface** **1.7.2. Unnecessary Claims** (Referring to optional features or non-normative elements) No disclosures in this category were made during subcommittee review. **1.7.3. Third Party Disclosures** (Note that third party IPR submissions do not contain any claim of willingness to license the IPR.) * US 10,404,014 B2, FCI USA LLC, Sep. 3, 2019, “STACKING ELECTRICAL CONNECTOR WITH REDUCED CROSS TALK” Refer to PICMG® IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage. PICMG® makes no judgment as to the validity of these claims or the licensing terms offered by the claimants. THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INFRINGEMENT IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER’S OWN RISK, AND NEITHER THE CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, SHALL HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING FROM THE USE OF THIS SPECIFICATION. Compliance with this specification does not absolve manufacturers of COM-HPC® equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG®, CompactPCI®, AdvancedTCA®, ATCA®, AdvancedMC®, CompactPCI® Express, COM Express®, COM-HPC®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and xTCA™ and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. **1.7.4. Copyright Notice** © 2021 PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from PICMG. PICMG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”. **1.7.5. Trademarks** Intel is a registered trademark of Intel Corporation. PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). COM-HPC® is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registered trademark of NXP Semiconductors. Samtec is a registered trademark of Samtec Inc. All product names and logos referenced in this document are property of their owners. Thunderbolt is a registered trademark of the Intel corporation. Accelerate is a trademark of Samtec Inc. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 12/159](.picmg-com-hpc-carrier-design-guide-alt/slide-014.jpg) ## Slide 15 ![**Preface** **1.8. Acronyms, Abbreviations and Definitions Used** **Table 1: Acronyms, Abbreviations and Definitions Used** Term Definition :--- :--- **10GBASE-KR** 10 Gbps internal copper interface. Operates over a single lane and uses the same physical layer coding (defined in IEEE 802.3 Clause 49) as 10GBASE-LR (Single Mode Fiber 1310 nm ) / ER (Single Mode Fiber 1550 nm )/SR (Multi Mode Fiber 850 nm) **25GBASE-KR** 25 Gb/s internal copper interface using 25GBASE-R encoding over one lane in each direction **AC Coupled** This term means that series capacitors are inserted in the differential pair lines. This allows the transmit and receive lines to have their own, possibly separate DC common mode voltages. **ACPI** Advanced Configuration Power Interface **AMOLED** Active Matrix Organic (semiconductor) Light Emitting Diode (a flat panel display technology) **ARM** Advanced RISC Machine – a low power alternative CPU architecture widely used in mobile and embedded systems **ATX** Advanced Technology Extended – Industry standard PC Motherboard form factor and power supply definitions **BIDIR** Bidirectional (in reference to electrical signals) **BIOS** Basic Input Output System **BMC** Baseboard Management Controller or Board Management Controller – located on Carrier for COM-HPC, if implemented **Carrier Board** An application specific circuit board that accepts a COM-HPC Module **CCC** Current Carrying Capability **DDI** Digital Display Interface – an interface that can serve DisplayPort and HDMI/DVI, **DIMM** Dual In-line Memory Module – larger format SDRAM memory module used in desk top systems and server PCs **DisplayPort DP** DisplayPort is a digital display interface standard put forth by the Video Electronics Standards Association (VESA). It defines a new license free, royalty free, digital audio/video interconnect, intended to be used primarily between a computer and its display monitor. **DPLL** Digital Phase Locked Loop **DRAM** Dynamic Random Access Memory **DVI** Digital Visual Interface - a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digital and analog video signals. The digital signals use TMDS. **EAPI** Embedded Application Programming Interface **EC** Embedded Controller **ECN** Engineering Change Notice **EEPROM** Electrically Erasable Programmable Read-Only Memory **Embedded DisplayPort eDP** Embedded DisplayPort (eDP) is a digital display interface standard defined by the Video Electronics Standards Association (VESA) for digital interconnect of Audio and Video within a closed system such as a laptop computer or a piece of laboratory instrumentation. **ESD** Electro Static Discharge **eSPI** Enhanced Serial Peripheral Interface **FAE** Field Application Engineer **Flash** EEPROM memory used for code storage. It can be updated in place (“flashed”). **FPGA** Field Programmable Gate Array **FR4** A type of fiber-glass laminate commonly used for printed circuit boards. **Gb** Gigabit **GbE** Gigabit Ethernet **Gbps** Gigabits per second **GPI** General Purpose Input **GPS** Global Positioning System **GPIO** General Purpose Input Output **GPO** General Purpose Output **GPU** Graphics Processing Unit PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 13/159](.picmg-com-hpc-carrier-design-guide-alt/slide-015.jpg) ## Slide 16 ![**Preface** Term Definition :--- :--- **Gtps, GT/sec** Giga Transfers per Second **HDA** Intel High Definition Audio (HD Audio) refers to the specification released by Intel in 2004 for delivering high definition audio. **HDMI** High Definition Multimedia Interface – digital display interface widely used in consumer electronics such as digital TVs **I2C** Inter Integrated Circuit – 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to read and load register values. **I2S** Inter IC Sound – a 5 wire serial data interface, used primarily for transmitting and receiving digital audio data **I3C** Improved Inter Integrated Circuit – builds on I2C and offers higher speeds and in-band interrupts **IPMB** Intelligent Platform Management Bus **IPMI** Intelligent Platform Management Interface **IPR** Intellectual Property Rights **LAN** Local Area Network **Legacy Device** Relics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial ports, parallel printer ports, PS-2 keyboards, and mice. Definitions vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device. **LPC** Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC. **LS** Least Significant **M.2** A small form factor add in card, for storage, WiFi, Cell Modems, etc. Interface options include PCIe x1, x2 or x4, SATA, USB and asynchronous serial. The standard is maintained by the PCI-SIG. **MAC** Media Access Control – in this document, MAC refers to to the physical hardware bridge device between a CPU interface such as PCIe, and a network interface such as MDI or 10GBASE-KR or many others. A PHY is needed between the MAC and the Ethernet physical layer **MAFS** Term for Master Attached Flash Sharing where the Flash component is attached to the processor interface. **MDI** Media Dependent Interface between a Ethernet PHY and the system magnetics and copper twisted pairs **MDIO** Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used to manage PHYs or physical layer devices in media access controllers (MACs). **ME** Management Engine – Intel term for a management microcontroller embedded into the chipset silicon. It is active before the main x86 CPU boots. **MIPI** Industry trade group that sets standards for mobile devices **MMC** Module Management Controller – a small microcontroller on the Module that works in conjunction with a Carrier BMC to implement IPMI functions. Implementation is optional. **MS** Most Significant **NA or N/A** Not Available, Not Applicable **NBASE-KR** Ethernet back plane signaling on PCB differential pairs. ‘N’ signifies the speed – 25Gbps or 10Gbps **NBASE-T** Ethernet physical layer signaling on twisted pairs. ‘N’ signifies the speed – 10Gbps, 5Gbps, 2.5Gbps, 1Gbps, 100Mbps or 10Mbps **NC** No Connect **NDA** Non-Disclosure Agreement **Nyquist Frequency** The critical frequency, sometimes called the “folding frequency”, for a digital sampling system. It is (usually) ½ of the maximum data rate for the system. **NVME** Non Volatile Memory Express - non volatile memory with a PCIe interface – x1, x2 or x4 – often in an M.2 card form factor **OCXO** Oven Controlled Xtal (crystal) Oscillator **OEM** Original Equipment Manufacturer **OTP** One Time Programmable – an option offered by some silicon vendors to change IC parameters by programming or blowing device fuses once, before shipment. **PC-AT** “Personal Computer – Advanced Technology” – an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s **PCB** Printed Circuit Board **PCI** Peripheral Component Interface **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 14/159](.picmg-com-hpc-carrier-design-guide-alt/slide-016.jpg) ## Slide 17 ![**Preface** **Term** **Definition** --- --- **PCI Express PCIe** Peripheral Component Interface Express – serialized point-to-point version of PCI **PEG** PCI Express Graphics **PHY** Physical layer device, usually used in the context of **Pin-out Type** A reference to one of eight COM Express® or COM-HPC definitions for the signals that appear on the COM Express® Module connector pins. **PMD** Physical Medium Dependent – the physical layer of computer network protocols **POR** Plan of Record **PPS** Pulse Per Second (for Ethernet) **PTP** Precision Time Protocol (for Ethernet) **PU PD** Pull Up A connection between a signal and a specified power rail, through a resistor Pull Down **Ra** Roughness Average – a measure of surface roughness, expressed in units of length. **ROM** Read Only Memory – a legacy term – often the device referred to as a ROM can actually be written to, in a special mode. Such writable ROMs are sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM. **RSVD** Reserved. If a pin is marked RSVD, nothing should be connected to it **RTC** Real Time Clock – battery backed circuit in PC-AT systems that keeps system time and date **S0, S1, S2, S3, S4, S5** System states describing the power and activity level S0 Full power, all devices powered S1 CPU powered, CPU and bus clocks off, not in common use S2 S3 Suspend to RAM System context stored in RAM; RAM is in standby S4 Suspend to Disk System context stored on disk S5 Soft Off Main power rail off, only standby power rail present **SAFS** Term for Slave Attached Flash Sharing where the Flash component is attached behind a BMC component. **SATA** Serial AT Attachment: serial-interface standard for hard disks **SDP** Software Definable Pin **SKU** Stock Control Unit (a part number for a specific stockable item) **SGMII** Serial Gigabit Media Independent Interface **SMA** Sub Miniature type A – a small form factor circular connector used for miniature coax cables, for WiFi, GPS and Cell Modem antennas **SMBus** System Management Bus – a 3 wire bus – clock, data and alert – based in I2C – for system management **SOC** System On Chip **SO-DIMM** Small Outline Dual In-line Memory Module – small form factor SDRAM module **SPD** Serial Presence Detect – refers to serial EEPROM on DRAMs that has DRAM Module configuration information **SPI** Serial Peripheral Interface **Super I/O** An integrated circuit, typically interfaced via the LPC or eSPI bus that provides legacy PC I/O functions including PS2 keyboard and mouse ports, serial and parallel port(s) and a floppy interface. **TFT** Thin Film Transistor – refers to technology used in active matrix flat-panel displays, in which there is one thin film transistor per display pixel. **TMDS** Transition Minimized Differential Signaling - a digital signaling protocol between the graphics subsystem and display. TMDS is used for the DVI digital signals. **TPM** Trusted Platform Module, chip to enhance the security features of a computer system. **USB** Universal Serial Bus **WDT** Watch Dog Timer. **XAUI** 10 Gbps Attachment Unit Interface. **XGMII** 10 Gbps Media Independent Interface **XO** Xtal (crystal) Oscillator PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 15/159](.picmg-com-hpc-carrier-design-guide-alt/slide-017.jpg) ## Slide 18 ![**Preface** **1.9. Applicable Documents and Standards** The list below is a partial list of documents and standards applicable to COM-HPC®. Many of the standards groups listed below (MIPI, PCI-SIG, USB, VESA etc.) have much more additional information available – ECNs, supplemental documents, test specifications, SI masks etc. These are too numerous to list here. Please explore the links below for additional documents that may be relevant. * Advanced Configuration and Power Interface (ACPI) Specification Version 6.3, January 2019, Copyright © 2018, Unified Extensible Firmware Interface (UEFI) Forum, Inc. All rights reserved. https://uefi.org/specifications * ATX Specification Version 2.2 © Intel Corp. 2004 * ATX12V Power Supply Design Guide, Version 2.2, March 2005 © Intel Corp. * eSPI Enhanced Serial Peripheral Interface, Interface Base Specification Revision 1.0, Copyright © 2016, Intel Corporation. January 2016 https://downloadcenter.intel.com/download/27055/ * HDMI (High Definition Multimedia Interface) specifications. http://www.hdmi.org * High-Definition Multimedia Interface specification versions 1.3, 1.4b, 2.1 * HDMI Alt Mode USB Type-C * I2C Specification * NXP UM10204 “I2C-bus specification and user manual” * Rev 7 October 1, 2021 * http://www.nxp.com use NXP site search tool to locate UM10204 * IEEE standards http://www.ieee.org * IEEE Std 802.3™-2018 (Revision of IEEE Std 802.3-2015), IEEE Standard for Information technology, Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements – Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications * IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, July 24, 2008, Copyright 2016 * Intelligent Platform Management Interface Specification Second Generation, v2.0, Document Revision 1.1, October 1, 2013 (c) Intel, Hewlett-Packard, NEC, Dell * An E7 red-line markup version of this document, dated April 21 2015, is available – see https://www.intel.com/content/www/us/en/servers/ipmi/ipmi-technical-resources.html * Intel Low Pin Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright © 2002 Intel Corporation. All rights reserved. https://www.intel.com/content/www/us/en/design/technologies-and-topics/low-pin-count-interface-specification.html * MIPI Alliance specifications https://www.mipi.org * MIPI CSI-2 Camera Serial Interface * MIPI-CSI-3 Camera Serial Interface * MIPI DSI Display Serial Interface * MIPI DSI-2 Display Serial Interface * MIPI C-PHY Physical layer spec for CSI-2 and DSI-2 (alternative) * MIPI D-PHY Physical layer spec for CSI-2 and DSI-2 * MIPI M-PHY Physical layer spec for CSI-3 * MIPI Soundwire Serialized audio interface * MIPI I3C Two wire serial data interface, successor to I2C * MXM Graphics Module Mobile PCI Express Module Electromechanical Specification Version 3.0 Revision 1.1 (c) 2009 Nvidia Corporation Note: this document is not publicly available at the time of this writing but it does exist * NC-SI Network Controller Sideband Interface Specification http://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.0.0.pdf PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 16/159](.picmg-com-hpc-carrier-design-guide-alt/slide-018.jpg) ## Slide 19 ![Preface Document Number: DSP0222, Jul 21, 2009, Version: 1.0.0 Copyright© 2009 Distributed Management Task Force, Inc. (DMTF). * NEBS (Network Equipment – Building Systems) This is a collection of documents describing reliability criteria for telecom equipment. The NEBs docu- ments are maintained by Telcordia / Ericsson https://telecom-info.telcordia.com * PCI-SIG (Peripheral Component Interconnect Special Interest Group) specifications https://www.pcisig.- com * PCI Express Base Specification Revision 5.0 * PCI Express Card Electromechanical Specification Revision 4.0 * PCI Express Mini Card Electromechanical Specification Revision 2.1 * Add USB 3.0 to the Mini Card * PCI Express M.2 Specification Revision 4.0 V1.0 * PCI Local Bus Specification Revisions 3,4 and 5. * PICMG (PCI Industrial Computer Manufacturing Group) documents http://www.picmg.org/ * PICMG COM.0 COM Express Module Base Specification Revision 3.0 * PICMG EAPI Embedded Application Software Interface Specification Revision 1.0 * PICMG EEEP Embedded EEPROM Specification Revision 1.0 (for COM-Express) * PICMG COM-HPC EEEP Embedded EEPROM Specification Revision 1.0 * PICMG COM-HPC Carrier Design Guide Revision 1.0 * PICMG COM Express Carrier Design Guide Revision 2.0 * PICMG COM-HPC Platform Management Interface Specification Revision 1.0 * PICMG Policies and Procedures for Specification Development, Revision 2.0 * Serial ATA Revision 3.5a Specification (March 2021) http://www.sata-io.org/ * SFP+, SFF-8083 Rev 3.1, SFF-8083 Specification for SFP+ 1X 10 Gb/s Pluggable Transceiver Solution (SFP10) Rev 3.1, Sep. 13, 2014 ftp://ftp.seagate.com/sff/SFF-8083.PDF * SGET (Standardization Group for Embedded Technologies) standards and documents (www.sget.org) * SMARC Hardware Specification Revision 2.1.1 (Smart Mobility ARChitecture) * SMARC Design Guide Revision 2.1.1 * SPI, Serial Peripheral Interface Bus See http://elm-chan.org/docs/spi_e.html for some general information on SPI * System Management Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright © 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technol- ogy Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. All rights reserved. http://www.sm- bus.org * Trusted Computing Group Specifications https://www.trustedcomputinggroup.org Trusted Platform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007 TPM 2.0 Library Specification * Underwriters Laboratories UL 1642 Standard for Safety for Lithium Batteries * USB Specifications https://www.usb.org/ * USB 2.0 * USB 3.0, 3.1, 3.2 * USB4 also known as “Thunderbolt 4” * USB Type-C Connector and Power Delivery specifications * VESA (Video Electronics Standards Association) https://www.vesa.org * DisplayPort Interoperability Guideline Version 1.1a, February 5, 2009 http://www.vesa.org/vesa-standards/free-standards/ * DisplayPort Standard Version 1.4 * DisplayPort Standard Version 2.0 * Embedded DisplayPort (eDP) Specification Rev. 1.4b, Oct 10, 2015 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 17/159](.picmg-com-hpc-carrier-design-guide-alt/slide-019.jpg) ## Slide 20 ![**Header:** COM-HPC Interfaces **2. COM-HPC Interfaces** **2.1. COM-HPC Client and Server Pinout Differences** The complete listings of signal descriptions and connector pin assignments for the COM-HPC Client and Server pinout types are found in the PICMG COM-HPC Module Base Specification and are not repeated here. Table 2 below details the Module connector pin assignments that differ between the Client and Server types. **Table 2: Client and Server Type Pinout Difference Table** Pin Row Client Server :--- :--- :--- :--- 20 A DDI1_SDA_AUX- ETH4_RX- 21 A DDI1_SCL_AUX+ ETH4_RX+ 23 A DDI1_PAIR0- ETH5_RX- 24 A DDI1_PAIR0+ ETH5_RX+ 26 A DDI1_PAIR1- ETH6_RX- 27 A DDI1_PAIR1+ ETH6_RX+ 29 A DDI1_PAIR2- ETH7_RX- 30 A DDI1_PAIR2+ ETH7_RX+ 32 A DDI1_PAIR3- RSVD 33 A DDI1_PAIR3+ RSVD 35 A eDP_AUX- ETH4_TX- 36 A eDP_AUX+ ETH4_TX+ 38 A eDP_TX0- ETH5_TX- 39 A eDP_TX0+ ETH5_TX+ 41 A eDP_TX1- ETH6_TX- 42 A eDP_TX1+ ETH6_TX+ 44 A eDP_TX2- ETH7_TX- 45 A eDP_TX2+ ETH7_TX+ 47 A eDP_TX3- USB1_AUX- 48 A eDP_TX3+ USB1_AUX+ 19 B I2S_LRCLK/SNDW_CLK3 RSVD 20 B I2S_DOUT/SNDW_DAT3 RSVD 21 B I2S_MCLK RSVD 22 B I2S_DIN/SNDW_DAT2 RSVD 23 B I2S_CLK/SNDW_CLK2 RSVD 45 B LID# RSVD 46 B SLEEP# RSVD 20 C SNDW_DMIC_CLK1 ETH0_TX- 21 C SNDW_DMIC_DAT1 ETH0_TX+ 23 C SNDW_DMIC_CLK0 ETH1_TX- 24 C SNDW_DMIC_DAT0 ETH1_TX+ 26 C DDI0_DDC_AUX_SEL ETH2_TX- 27 C DDI1_DDC_AUX_SEL ETH2_TX+ 28 C DDI0_HPD GND 29 C DDI1_HPD ETH3_TX- 30 C eDP_HPD ETH3_TX+ 31 C eDP_VDD_EN GND 32 C eDP_BKLT_EN USB3_SSRX- 33 C eDP_BKLTCTL USB3_SSRX+ 35 C USB1_AUX- USB2_SSRX- 36 C USB1_AUX+ USB2_SSRX+ 19 D DDI0_SDA_AUX- ETH0_RX- 20 D DDI0_SCL_AUX+ ETH0_RX+ 22 D DDI0_PAIR0- ETH1_RX- 23 D DDI0_PAIR0+ ETH1_RX+ 25 D DDI0_PAIR1- ETH2_RX- 26 D DDI0_PAIR1+ ETH2_RX+ **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 18/159](.picmg-com-hpc-carrier-design-guide-alt/slide-020.jpg) ## Slide 21 ![**Header:** COM-HPC Interfaces **Table Content:** Pin Row Client Server :--- :--- :--- :--- 28 D DDI0_PAIR2- ETH3_RX- 29 D DDI0_PAIR2+ ETH3_RX+ 31 D DDI0_PAIR3- USB3_SSTX- 32 D DDI0_PAIR3+ USB3_SSTX+ 34 D AC_PRESENT USB2_SSTX- 35 D RSVD USB2_SSTX+ 3 E DDI2_SDA_AUX- RSVD 4 E DDI2_SCL_AUX+ RSVD 6 E DDI2_PAIR0- RSVD 7 E DDI2_PAIR0+ RSVD 9 E DDI2_PAIR1- RSVD 10 E DDI2_PAIR1+ RSVD 12 E DDI2_PAIR2- RSVD 13 E DDI2_PAIR2+ RSVD 15 E DDI2_PAIR3- RSVD 16 E DDI2_PAIR3+ RSVD 18 E DDI2_DDC_AUX_SEL RSVD 19 E DDI2_HPD RSVD 69 E RSVD PCIe48_TX- 70 E RSVD PCIe48_TX+ 71 E RSVD GND 72 E RSVD PCIe49_TX- 73 E RSVD PCIe49_TX+ 74 E RSVD GND 75 E RSVD PCIe50_TX- 76 E RSVD PCIe50_TX+ 77 E RSVD GND 78 E NBASET1_CREF PCIe51_TX- 79 E NBASET1_SDP PCIe51_TX+ 80 E NBASET1_LINK_MID# GND 81 E NBASET1_LINK_ACT# PCIe52_TX- 82 E NBASET1_LINK_MAX# PCIe52_TX+ 84 E RSVD PCIe53_TX- 85 E RSVD PCIe53_TX+ 87 E ETH0_RX- PCIe54_TX- 88 E ETH0_RX+ PCIe54_TX+ 90 E ETH1_RX- PCIe55_TX- 91 E ETH1_RX+ PCIe55_TX+ 1 F RSVD ETH2_SDP 2 F RSVD ETH3_SDP 3 F RSVD ETH4_SDP 4 F RSVD ETH5_SDP 5 F RSVD ETH6_SDP 6 F RSVD ETH7_SDP 7 F RSVD ETH4-7_I2C_CLK 8 F RSVD ETH4-7_I2C_DAT 9 F RSVD ETH4-7_INT# 10 F RSVD ETH4-7_MDIO_CLK 11 F RSVD ETH4-7_MDIO_DAT 12 F RSVD ETH4-7_PHY_INT# 13 F RSVD ETH4-7_PHY_RST# 14 F RSVD ETH4-7_PRSNT# 68 F RSVD PCIe48_RX- 69 F RSVD PCIe48_RX+ 71 F NBASET1_MDIO- PCIe49_RX- 72 F NBASET1_MDIO+ PCIe49_RX+ 74 F NBASET1_MD1- PCIe50_RX- 75 F NBASET1_MD1+ PCIe50_RX+ 77 F NBASET1_MD2- PCIe51_RX- 78 F NBASET1_MD2+ PCIe51_RX+ **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 19/159](.picmg-com-hpc-carrier-design-guide-alt/slide-021.jpg) ## Slide 22 ![**Header:** COM-HPC Interfaces **Table:** Pin Row Client Server 80 F NBASE1_MDI3- PCIe52_RX- 81 F NBASE1_MDI3+ PCIe52_RX+ 83 F RSVD PCIe53_RX- 84 F RSVD PCIe53_RX+ 86 F ETH0_TX- PCIe54_RX- 87 F ETH0_TX+ PCIe54_RX+ 88 F ETH1_TX- PCIe55_RX- 90 F ETH1_TX+ PCIe55_RX+ 95 F RSVD PCIe_CLKREQ3# 96 F ETH0-1_PRSNT# ETH0-3_PRSNT# 97 F ETH0-1_PHY_RST# ETH0-3_PHY_RST# 2 G GND RSVD 3 G USB2_SSRX0- RSVD 4 G USB2_SSRX0+ RSVD 5 G GND RSVD 6 G USB2_SSRX1- RSVD 7 G USB2_SSRX1+ RSVD 8 G GND RSVD 9 G USB3_SSRX0- RSVD 10 G USB3_SSRX0+ RSVD 11 G GND RSVD 12 G USB3_SSRX1- RSVD 13 G USB3_SSRX1+ RSVD 15 G USB3_LSRX RSVD 16 G USB3_LSTX RSVD 17 G USB2_LSRX RSVD 18 G USB2_LSTX RSVD 19 G PEG_LANE_REV# RSVD 69 G RSVD PCIe56_RX- 70 G RSVD PCIe56_RX+ 72 G CSI0_RX0- PCIe57_RX- 73 G CSI0_RX0+ PCIe57_RX+ 75 G CSI0_RX1- PCIe58_RX- 76 G CSI0_RX1+ PCIe58_RX+ 78 G CSI0_RX2- PCIe59_RX- 79 G CSI0_RX2+ PCIe59_RX+ 81 G CSI0_RX3- PCIe60_RX- 82 G CSI0_RX3+ PCIe60_RX+ 84 G CSI0_CLK- PCIe61_RX- 85 G CSI0_CLK+ PCIe61_RX+ 87 G CSI0_I2C_CLK PCIe62_RX- 88 G CSI0_I2C_DAT PCIe62_RX+ 89 G CSI0_MCLK GND 90 G CSI0_RST# PCIe63_RX- 91 G CSI0_ENA PCIe63_RX+ 93 G RSVD PCIe_REFCLK3- 94 G RSVD PCIe_REFCLK3+ 96 G ETH0-1_I2C_CLK ETH0-3_I2C_CLK 97 G ETH0-1_I2C_DAT ETH0-3_I2C_DAT 98 G ETH0-1_PHY_INT# ETH0-3_PHY_INT# 99 G ETH0-1_INT# ETH0-3_INT# 1 H GND RSVD 2 H USB2_SSTX0- RSVD 3 H USB2_SSTX0+ RSVD 4 H GND RSVD 5 H USB2_SSTX1- RSVD 6 H USB2_SSTX1+ RSVD 7 H GND RSVD 8 H USB3_SSTX0- RSVD 9 H USB3_SSTX0+ RSVD **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 20/159](.picmg-com-hpc-carrier-design-guide-alt/slide-022.jpg) ## Slide 23 ![The slide is titled 'COM-HPC Interfaces' at the top right. It features a table with four columns: 'Pin', 'Row', 'Client', and 'Server'. **Table Content:** * **Pin 10:** Row H, Client GND, Server RSVD * **Pin 11:** Row H, Client USB3_SSTX1-, Server RSVD * **Pin 12:** Row H, Client USB3_SSTX1+, Server RSVD * **Pin 13:** Row H, Client GND, Server RSVD * **Pin 14:** Row H, Client USB2_AUX-, Server RSVD * **Pin 15:** Row H, Client USB2_AUX+, Server RSVD * **Pin 16:** Row H, Client GND, Server RSVD * **Pin 17:** Row H, Client USB3_AUX-, Server RSVD * **Pin 18:** Row H, Client USB3_AUX+, Server RSVD * **Pin 68:** Row H, Client RSVD, Server PCIe56_TX- * **Pin 69:** Row H, Client RSVD, Server PCIe56_TX+ * **Pin 71:** Row H, Client CSI1_RX0-, Server PCIe57_TX- * **Pin 72:** Row H, Client CSI1_RX0+, Server PCIe57_TX+ * **Pin 74:** Row H, Client CSI1_RX1-, Server PCIe58_TX- * **Pin 75:** Row H, Client CSI1_RX1+, Server PCIe58_TX+ * **Pin 77:** Row H, Client CSI1_RX2-, Server PCIe59_TX- * **Pin 78:** Row H, Client CSI1_RX2+, Server PCIe59_TX+ * **Pin 80:** Row H, Client CSI1_RX3-, Server PCIe60_TX- * **Pin 81:** Row H, Client CSI1_RX3+, Server PCIe60_TX+ * **Pin 83:** Row H, Client CSI1_CLK-, Server PCIe61_TX- * **Pin 84:** Row H, Client CSI1_CLK+, Server PCIe61_TX+ * **Pin 86:** Row H, Client CSI1_I2C_CLK, Server PCIe62_TX- * **Pin 87:** Row H, Client CSI1_I2C_DAT, Server PCIe62_TX+ * **Pin 88:** Row H, Client CSI1_MCLK, Server GND * **Pin 89:** Row H, Client CSI1_RST#, Server PCIe63_TX- * **Pin 90:** Row H, Client CSI1_ENA, Server PCIe63_TX+ * **Pin 98:** Row H, Client ETH0-1_MDIO_CLK, Server ETH0-3_MDIO_CLK * **Pin 99:** Row H, Client ETH0-1_MDIO_DAT, Server ETH0-3_MDIO_DAT **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 21/159](.picmg-com-hpc-carrier-design-guide-alt/slide-023.jpg) ## Slide 24 ![**Header:** Reference Schematics and Block Diagrams **3. Reference Schematics and Block Diagrams** **3.1. Sources for Technical Materials** The schematic diagrams, block diagrams and mechanical diagrams in this document were contributed by several companies and organizations, including Adlink, Advantech, Avnet Integrated, Bielefeld University, congatec, Intel, Kontron, Samtec and SECO. Hence the graphic styles vary a bit. An effort has been made to provide part numbers in the drawings that can be located in a web search (except for small generic parts). **3.2. Schematic Conventions** Schematic examples are drawn with signal directions shown per the Figure below. Signals that connect directly to the COM-HPC connector are flagged with the text “COM” in the off-page connect symbol, as shown in Figure 1 below. Nets that connect to the COM-HPC Module are named per the PICMG COM-HPC specification in almost all cases. **Figure 1: Schematic Conventions** (Diagram of an IC with connections) * **Center Box:** IC * **Left Side Labels:** Output from IC, Input to IC, Bidir Signal, Output from IC to Module (with 'COM' in red box), Input to IC from Module (with 'COM' in red box), Bidir Signal to / from Module (with 'COM' in red box). * **Right Side Labels:** Output from IC, Input to IC, Bidir Signal, Output from IC to Module (with 'COM' in red box), Input to IC from Module (with 'COM' in red box), Bidir Signal to / from Module (with 'COM' in red box). Power nets shown in the sample schematics and drawings are labeled, for the most part, per the Table below. The power rail behavior under the various system power states is shown in the Table. **Table 3: Power Net Naming** Power Net S0 On S3 Suspend to RAM S4 Suspend to Disk S5 Soft Off G3 Mechanical Off :--- :--- :--- :--- :--- :--- +12V_S 12V off off off off +5V_S 5V off off off off +3.3V_S 3.3V off off off off +1.5V_S 1.5V off off off off +2.5V_S 2.5V off off off off +5V_A 5V 5V 5V 5V off +3.3V_A 3.3V 3.3V 3.3V 3.3V off VCC_RTC 3.0V 3.0V 3.0V 3.0V 3.0V **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 22/159](.picmg-com-hpc-carrier-design-guide-alt/slide-024.jpg) ## Slide 25 ![**Reference Schematics and Block Diagrams** **3.3. Ethernet NBASE-T** A typical NBASE-T implementation is shown in Figure 2 below. The “N” refers to the link speed, and may be 10 Mbps, 100 Mbps, 1 Gbps, 2.5 Gbps, 5 Gbps or 10 Gbps. However not all speeds may be available on all Module designs. All COM-HPC Modules are required to support at least the 1 Gbps rate. This example shows a “Mag-Jack” (an 8 pin RJ45 jack with integrated isolation magnetics) from Würth Electronics, p/n 7499611420. This part is claimed by Würth to support 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps data rates. There are many similar parts from Würth and from vendors such as Bel-Fuse, Pulse Electronics and others. It may be advisable to check with your Module vendor on the suitability of chosen parts. Ethernet RJ45 jacks (including Mag-Jacks and jacks that require external magnetics) come in “tab-up” and “tab-down” versions. The Würth part shown here is “tab-up”. If a “tab-down” part is used then the PCB layout is impacted as the pin orientation is effectively flipped 180 degrees. Implementing magnetics that are external to the jack is of course possible but it is trickier. It may be necessary in certain situations that require a higher than normal isolation between the Ethernet magnetics primary and secondary sides. This can be the case in safety critical designs such as medical equipment. The colors and meanings of the colors used for NBASE-T LEDs are not standardized in the industry. The scheme shown in the diagram below is suggested for COM-HPC but not required. The diagram below shows ESD protection diode arrays (Texas Instruments TPD4E02B04) protecting the NBASE-T differential pairs. Many similar parts are available from other vendors. Make sure the selected part has a suitably low pin capacitance. It is very important that the parts (D43 and D44 in the figure) are placed close to the connector and are routed in a “no stub” fashion. For example the net NBASET0+ in the figure should hit D43 pin 6 and continue under the D43 package to catch pin 5 and then on to the RJ45 connector. Pins may be swapped for easier routing, as long as the pairs are kept together and the no-stub routing is followed. **Figure 2: NBASE-T** (Shows a schematic diagram including connector X37, LEDs, resistors, capacitors, ESD protection diodes D43 and D44, and connector X36). **Note:** Connection of Center Tap should be adjusted depending on Phy used on COM-HPC module. Schematic shown here should offer stuffing options for all common architectures (separated caps at center tap, individual center taps shorted, adjustable CT capacitor values) **PICMG® COM-HPC® Carrier Design Guide** **Rev. RC2.0d / Dec 7, 2021** **23/159**](.picmg-com-hpc-carrier-design-guide-alt/slide-025.jpg) ## Slide 26 ![**Header:** Reference Schematics and Block Diagrams **3.4. Ethernet KR and KR4** The Ethernet KR interfaces consist of a single TX pair and single RX pair. These pairs are capacitively coupled off of the COM-HPC Module – either on the Carrier board (for Module to PHY or Module to Module situations) or within the SFP assemblies. Ethernet KR4 interfaces are comprised of four TX pairs and four RX pairs, capacitively coupled off of the COM-HPC Module, as per the KR interfaces. In order to save pins, the side band signals for the 10G / 25G / 40G / 100G Ethernet KR interfaces are serialized on the Module silicon per an Intel convention known as CEI. This is an acronym for “Common Electrical Interface”. The serialized CEI signals need to be deserialized on the Carrier Board. The block diagrams in this section describe which components are needed and what the functions of the deserialized nets are. The Ethernet KR LED information is carried on one I2C bus per four Ethernet KR channels, known as a Quad. The I2C buses are named ETH0-3_I2C* (where the * indicates the final characters of the net name in that signal group) and ETH4-7_I2C* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1_I2C*. There is one MDIO bus per Quad available to configure the PHYs on the Carrier Board. The MDIOs are named ETH0-3_MDIO* and ETH4-7_MDIO* for the Server type. As the Client only supports 2 Ethernet channels, the group is named ETH0-1_MDIO*. The Reset and Interrupt signals also follow the same naming convention. The SDP signals are more critical in timing and are available directly. **3.4.1. Ethernet KR CEI Block Diagrams** Ethernet KR CEI concepts are illustrated in block diagram format in Figures 3 through 9 on the following pages. Many of the details of these implementations are vendor NDA protected. Some references to vendor document numbers for confidential material are listed after each Figure, if material is available. Designers interested in these materials need to contact the silicon vendors directly and work out the necessary NDAs. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 24/159](.picmg-com-hpc-carrier-design-guide-alt/slide-026.jpg) ## Slide 27 ![Reference Schematics and Block Diagrams Figure 3: Intel SoC with CEI Boundary **Left Column:** Intel SoC New ETH(0..3) ETH0-3_MDIO ETH_I2C_0 ETH_TIMESYNC0 ETH_TIMESYNC1 ETH_TIMESYNC2 ETH_TIMESYNC3 ETH_LED11 ETH_LED9 ETH_LED10 ETH(4..7) ETH4-7_MDIO ETH_I2C_1 ETH_TIMESYNC4 ETH_TIMESYNC5 ETH_TIMESYNC6 ETH_TIMESYNC7 ETH_GPIO5 ETH_GPIO3 ETH_GPIO4 **Middle Column:** Connector COM-HPC Server ETH(0:3) ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT# ETH(4:7) ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP ETH4-7_PRSNT# ETH4-7_PHY_RST# ETH4-7_INT# ETH4-7_PHY_INT# **Right Column:** CEI0 Boundary CEI_PMD_L(0:3) CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# CEI1 Boundary CEI_PMD_L(4:7) CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# For further details on this configuration, refer to NDA protected Intel documents 620640 and 631178. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 25/159](.picmg-com-hpc-carrier-design-guide-alt/slide-027.jpg) ## Slide 28 ![Reference Schematics and Block Diagrams Figure 4: Intel CEI 4x SFP28 The slide displays a block diagram illustrating connections between a server connector and four SFP28 ports. **Left Column (Connector):** Label: 'Connector COM-HPC Server' Signals listed include: ETH(0:3) ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT# ETH(4:7) ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP ETH4-7_PRSNT# ETH4-7_PHY_RST# ETH4-7_INT# ETH4-7_PHY_INT# **Middle Columns (Boundaries & ICs):** Two boxes labeled 'CEI0 Boundary' and 'CEI1 Boundary' contain signals such as CEI_PMD_L(0:3), CEI_MDIO, CEI_I2C, and address configurations (e.g., CEI_ADDR0=0). Four integrated circuit blocks connect the boundaries to the SFPs: * **PCA9546A MUX**: Addr = 0xE0/0xE1 (I2C, I2C0, I2C1, I2C2, I2C3, ResetN) * **PCA9575 I/O**: Addr = 0x40/0x41 (I2C, ResetN, IntN, P0.0 through P1.7) * **EEPROM**: Addr = 0xA8/0xA9 (I2C, WP) * **PCA9685 LED**: Addr = 0x80/0x81 (I2C, EXTCLK, OE n, LED0 through LED15) **Right Column (SFP Connectors & LEDs):** Four boxes labeled 'PMD SFP_0' through 'PMD SFP_3'. Each box lists pins: I2C, RX_Loss, ModPresN, RS. Below the LED controller, a list of LED outputs is shown: P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED **Footer:** 'This configuration is not supported by additional Intel documentation at the time of this writing.' 'PICMG® COM-HPC® Carrier Design Guide' 'Rev. RC2.0d / Dec 7, 2021' '26/159'](.picmg-com-hpc-carrier-design-guide-alt/slide-028.jpg) ## Slide 29 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 5: Intel CEI 4x SFP28 with Retimer C827/XL827 **Diagram Content (Left to Right):** * **Connector COM-HPC Server:** * ETH(0:3) * ETH0-3_MDIO * ETH0-3_I2C * ETH0_SDP, ETH1_SDP, ETH2_SDP, ETH3_SDP * ETH0-3_PRSNT# * ETH0-3_PHY_RST# * ETH0-3_INT# * ETH0-3_PHY_INT# * ETH4-7_MDIO * ETH4-7_I2C * ETH4_SDP, ETH5_SDP, ETH6_SDP, ETH7_SDP * ETH4-7_PRSNT# * ETH4-7_PHY_RST# * ETH4-7_INT# * ETH4-7_PHY_INT# * **CEI0 Boundary:** * CEI_PMD_L(0:3) * CEI_ADDR0=0 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_I2C * CEI_PRSNT# * CEI_RESET# * CEI_INT# * **CEI1 Boundary:** * ETH(4:7) * CEI_PMD_L(4:7) * CEI_ADDR0=1 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_I2C * CEI_PRSNT# * CEI_RESET# * CEI_INT# * **PCA9546A MUX:** * I2C, I2C0, I2C1, I2C2, I2C3 * Addr = 0xE0/0xE1 * ResetN * **C827/XL827 Parkvale:** * PMD(0..3), PMD0, PMD1, PMD2, PMD3 * Addr0, Addr1, Addr2, Addr3, Addr4=0 * MDIO * ResetN * IntN * **PCA9575 I/O:** * I2C * ResetN, IntN * P0.0 through P0.7 * P1.0 through P1.7 * Addr = 0x40/0x41 * **EEPROM:** * I2C, WP * Addr = 0xA8/0xA9 * **PCA9685 LED:** * I2C * EXTCLK, OEn * LED0 through LED15 * Addr = 0x80/0x81 * **Right Side Blocks (SFP Modules):** * **PMD SFP_0:** I2C, RX_Loss, ModPresN, RS * **PMD SFP_1:** I2C, RX_Loss, ModPresN, RS * **PMD SFP_2:** I2C, RX_Loss, ModPresN, RS * **PMD SFP_3:** I2C, RX_Loss, ModPresN, RS * **LED Labels (Color Coded):** * P0_SPD_A_LED * P0_SPD_B_LED * P0_ACT_LED * P1_SPD_A_LED * P1_SPD_B_LED * P1_ACT_LED * P2_SPD_A_LED * P2_SPD_B_LED * P2_ACT_LED * P3_SPD_A_LED * P3_SPD_B_LED * P3_ACT_LED * P0_DISABLE * P1_DISABLE * P2_DISABLE * P3_DISABLE **Footer Text:** For further details on this configuration, refer to NDA Intel document 636564. **Page Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 27/159](.picmg-com-hpc-carrier-design-guide-alt/slide-029.jpg) ## Slide 30 ![**Header** Reference Schematics and Block Diagrams Figure 6: Intel CEI QSFP28 with Retimer C827/XL827 **Connector Block (Left)** Connector COM-HPC Server ETH(0:3) ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT# ETH(4:7) ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP ETH4-7_PRSNT# ETH4-7_PHY_RST# ETH4-7_INT# ETH4-7_PHY_INT# **CEI0 Boundary Block (Center-Left)** CEI0 Boundary CEI_PMD_L(0:3) CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# **C827/XL827 Block (Top-Right)** C827/XL827 PMD(0..3) Parkvale PMD(0..3) Addr0 Addr1 Addr2 Addr3 Addr4=0 MDIO ResetN IntN **QSFP Block (Far Right)** QSFP PMD(0..3) I2C ResetN IntN PresentN LPMode **PCA9575 I/O Block (Center-Right)** PCA9575 I/O I2C ResetN IntN P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Addr = 0x40/0x41 **EEPROM Block (Center-Lower)** EEPROM I2C WP Addr = 0xA8/0xA9 **CEI1 Boundary Block (Center-Lower-Left)** CEI1 Boundary CEI_PMD_L(4:7) CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# **PCA9685 LED Block (Bottom-Right)** PCA9685 LED I2C EXTCLK OEn LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 Addr = 0x80/0x81 P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE **Footer** For further details on this configuration, refer to NDA Intel document 636566. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 28/159](.picmg-com-hpc-carrier-design-guide-alt/slide-030.jpg) ## Slide 31 ![Reference Schematics and Block Diagrams **Figure 7: Intel CEI 4x 10GBASE-T Copper PHY X557-AT4** **Connector** COM-HPC Server ETH(0:3) ETH0-3_MDIO ETH0-3_I2C ETH0_SDP ETH1_SDP ETH2_SDP ETH3_SDP ETH0-3_PRSNT# ETH0-3_PHY_RST# ETH0-3_INT# ETH0-3_PHY_INT# ETH(4:7) ETH4-7_MDIO ETH4-7_I2C ETH4_SDP ETH5_SDP ETH6_SDP ETH7_SDP ETH4-7_PRSNT# ETH4-7_PHY_RST# ETH4-7_INT# ETH4-7_PHY_INT# **CEI0 Boundary** CEI_PMD_L(0:3) CEI_ADDR0=0 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# **CEI1 Boundary** CEI_PMD_L(4:7) CEI_ADDR0=1 CEI_ADDR1=1 CEI_ADDR2=0 CEI_MDIO CEI_I2C CEI_PRSNT# CEI_RESET# CEI_INT# **X557-AT4 Copper** PMD(0..3) MDI0_(0:3) LED_P0 Addr0 = 0 MDI1_(0:3) LED_P1 Addr1 = 0 MDI2_(0:3) LED_P2 Addr2 MDI3_(0:3) LED_P3 Addr3 MDIO Addr4 ResetN IntN **4x RJ-45** 10GBASE-T MDI0 LED_P0 MDI1_(0:3) LED_P1 MDI2_(0:3) LED_P2 MDI3_(0:3) LED_P3 **PCA9575 I/O** I2C ResetN IntN P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Addr = 0x40/0x41 **EEPROM** I2C Addr = 0xA8/0xA9 WP **PCA9685 LED** I2C EXTCLK OEn LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 Addr = 0x80/0x81 P0_SPD_A_LED P0_SPD_B_LED P0_ACT_LED P1_SPD_A_LED P1_SPD_B_LED P1_ACT_LED P2_SPD_A_LED P2_SPD_B_LED P2_ACT_LED P3_SPD_A_LED P3_SPD_B_LED P3_ACT_LED P0_DISABLE P1_DISABLE P2_DISABLE P3_DISABLE For further details on this configuration, refer to NDA Intel document 613899. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 29/159](.picmg-com-hpc-carrier-design-guide-alt/slide-031.jpg) ## Slide 32 ![**Header:** Reference Schematics and Block Diagrams **Figure Title:** Figure 8: Intel CEI 4x 1GBASE-T Copper PHY Marvell 88E1543 **Diagram Content (Left to Right):** **Connector Block:** * Connector * COM-HPC Server * ETH(0:3) * ETH0-3_MDIO * ETH0-3_I2C * ETH0_SDP * ETH1_SDP * ETH2_SDP * ETH3_SDP * ETH0-3_PRSNT# * ETH0-3_PHY_RST# * ETH0-3_INT# * ETH0-3_PHY_INT# * ETH(4:7) * ETH4-7_MDIO * ETH4-7_I2C * ETH4_SDP * ETH5_SDP * ETH6_SDP * ETH7_SDP * ETH4-7_PRSNT# * ETH4-7_PHY_RST# * ETH4-7_INT# * ETH4-7_PHY_INT# **CEI Boundary Blocks:** * CEI0 Boundary * CEI_PMD_L(0:3) * CEI_ADDR0=0 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_I2C * CEI_PRSNT# * CEI_RESET# * CEI_INT# * CEI1 Boundary * CEI_PMD_L(4:7) * CEI_ADDR0=1 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_I2C * CEI_PRSNT# * CEI_RESET# * CEI_INT# **88E1543 Block:** * 88E1543 * Aaska * PMD(0..3) * MDI0_(0:3) * MDI1_(0:3) * MDI2_(0:3) * MDIO * ResetN * IntN * MDI3_(0:3) **4x RJ-45 Block:** * 4x RJ-45 * 1GBASE-T * MDI0_(0:3) * MDI1_(0:3) * MDI2_(0:3) * MDI3_(0:3) **PCA9575 I/O Block:** * PCA9575 I/O * I2C * ResetN * IntN * P0.0 * P0.1 * P0.2 * P0.3 * P0.4 * P0.5 * P0.6 * P0.7 * P1.0 * P1.1 * P1.2 * P1.3 * P1.4 * P1.5 * P1.6 * P1.7 * Addr = * 0x40/0x41 **EEPROM Block:** * EEPROM * I2C * WP * Addr = * 0xA8/0xA9 **PCA9685 LED Block:** * PCA9685 LED * I2C * EXTCLK * OEn * LED0 * LED1 * LED2 * LED3 * LED4 * LED5 * LED6 * LED7 * LED8 * LED9 * LED10 * LED11 * LED12 * LED13 * LED14 * LED15 * P0_SPD_A_LED * P0_SPD_B_LED * P0_ACT_LED * P1_SPD_A_LED * P1_SPD_B_LED * P2_SPD_A_LED * P2_SPD_B_LED * P2_ACT_LED * P3_SPD_A_LED * P3_SPD_B_LED * P3_ACT_LED * P0_DISABLE * P1_DISABLE * P2_DISABLE * P3_DISABLE * Addr = * 0x80/0x81 **Footer Text:** For further details on this configuration, refer to NDA Intel document 613900. **Document Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 30/159](.picmg-com-hpc-carrier-design-guide-alt/slide-032.jpg) ## Slide 33 ![**Header:** Reference Schematics and Block Diagrams **Figure 9:** AMD SoC 4xSFP+ with CS4223 Retimer **Main Diagram Blocks (Left to Right):** **1. AMD SoC EPYC3000** * ETH(0:3) * SMBus * INTy# * PLRST# * INTx# **2. Connector COM-HPC Server** * ETH(0:3) * ETH0-3_MDIO * ETH0-3_I2C * ETH0_SDP * ETH1_SDP * ETH2_SDP * ETH3_SDP * ETH0-3_PRSNT# * ETH0-3_PHY_INT# * ETH0-3_PHY_RST# * ETH0-3_INT# * ETH(4:7) * ETH4-7_MDIO * ETH4-7_I2C * ETH4_SDP * ETH5_SDP * ETH6_SDP * ETH7_SDP * ETH4-7_PRSNT# * ETH4-7_PHY_RST# * ETH4-7_INT# * ETH4-7_PHY_INT# **3. CEI0 Boundary** * CEI_PMD_L_(0:3) * CEI_ADDR0=0 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_PRSNT# * CEI_RESET# * CEI_INT# **4. CEI1 Boundary** * CEI_PMD_L_(4:7) * CEI_ADDR0=1 * CEI_ADDR1=1 * CEI_ADDR2=0 * CEI_MDIO * CEI_PRSNT# * CEI_RESET# **5. CS4223** * PMD(0..3) * Addr0 * Addr1 * Addr2 * Addr3 * Addr4=0 * I2C * ResetN * IntN * PMD0 * PMD1 * PMD2 * PMD3 **6. PCA9545A MUX** * I2C * Addr = 0xE0/0xE1 * ResetN * I2C0 * I2C1 * I2C2 * I2C3 **7. PCA9555 I/O** * I2C * IntN * P1.7 * P1.6 * P1.5 * P1.4 * P1.3 * P1.2 * P1.1 * P1.0 * P0.7 * P0.6 * P0.5 * P0.4 * P0.3 * P0.2 * P0.1 * P0.0 * Addr = 0x40/0x41 **8. PMD SFP_0** * I2C * TX_Disable * TX_Fault * RX_Loss * ModPresN **9. PMD SFP_1** * I2C * TX_Disable * TX_Fault * RX_Loss * ModPresN **10. PMD SFP_2** * I2C * TX_Disable * TX_Fault * RX_Loss * ModPresN **11. PMD SFP_3** * I2C * TX_Disable * TX_Fault * RX_Loss * ModPresN **Footer Text:** For further details on this configuration, contact AMD. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 31/159](.picmg-com-hpc-carrier-design-guide-alt/slide-033.jpg) ## Slide 34 ![Reference Schematics and Block Diagrams 3.4.2. PHY Addresses Table 4: MDIO Addresses for Intel POR External PHYs PHY MDIO Address (Decimal) Ethernet Quad / Port :--- :--- :--- Intel “Parkvale” 2 Quad0 3 Quad1 Intel “Copperville” 8 Quad0 Port0 9 Quad0 Port1 10 Quad0 Port2 11 Quad0 Port3 Marvell offers a similar Phy 12 Quad1 Port0 13 Quad1 Port1 14 Quad1 Port2 15 Quad1 Port3 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 32/159](.picmg-com-hpc-carrier-design-guide-alt/slide-034.jpg) ## Slide 35 ![**Text Content:** Reference Schematics and Block Diagrams 3.5. Serial ATA 3.5.1. Cabled SATA The COM-HPC pin-outs offer up to two SATA ports, designated SATA0 and SATA1. The implementation for a cabled interface is straightforward, as illustrated in Figure 10 below. No Carrier coupling capacitors are needed as they are specified to be present on the Module. The connections between the Module and the SATA connector are simple differential pairs. Some routing rules may be found in Section 4 below. Two common connector styles used for cabled SATA implementations are shown in the Figure. The upper image shows a 7 pin data-only connector. Power to the SATA drive is handled separately in this case. The lower image in the Figure shows a 22 pin connector that handles SATA data and power. There are three power rails defined on this connector, but all three are not necessarily used. Smaller format drives tend to use just one or two of these rails, Check the drive specifications. Figure 10 below shows two typical COM-HPC cabled SATA0 implementations. SATA1 is handled in the same way. Note how the data pair polarity order flips along the connector pins: TX+ TX- GND RX- RX+ ... this is not a mistake, but is part of the SATA specification. Figure 10: Serial ATA - Cabled PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 33/159 **Visual Description:** The slide features two schematic diagrams under 'Figure 10.' The top diagram illustrates a 7-pin 'SATA1' connector (LOTES_ABA-SAT-010-K21) connecting SATA0 differential pairs (TX+/TX-, RX+/RX-) to pins 1 through 7. The bottom diagram illustrates a larger 22-pin 'SATA1' connector (MOLEX_47018-4001) that combines power rails (+12V_S, +5V_S, +3.3V_S) with the SATA data signals (SATA0_TX+, SATA0_TX-, SATA0_RX+, SATA0_RX-) across multiple pins.](.picmg-com-hpc-carrier-design-guide-alt/slide-035.jpg) ## Slide 36 ![**Header:** Reference Schematics and Block Diagrams **3.5.2. mSATA SSDs** The SATA specification defines a small form factor card for SATA SSDs that is almost identical in mechanical and electrical definition to the PCI-SIG miniPCIe format. The same card connector and mounting holes are used. Both half size and full size cards are in use. Sometimes dual mini-PCIe / mSATA implementations are executed. This involves multiplexing four signals per the following Table: **Table 5: mSATA Pin Mapping Relative to miniPCIe** MiniPCIe Card Pin Name MiniPCIe / mSATA Card Pin Number PCIE Signal Relative to COM-HPC Module SATA Signal Relative to COM-HPC Module :--- :--- :--- :--- PETP0 33 PCIe TX+ SATA TX+ PETN0 31 PCIe TX- SATA TX- PERP0 25 PCIe RX+ SATA RX- PERN0 23 PCIe RX- SATA RX+ The SATA_RX- mapping to miniPCIe PERP0 and SATA_RX+ to PERN0 is intentional per the SATA specification. The signals do not have to be multiplexed if a mSATA only or miniPCIe only implementation is desired. SSD implementations are largely moving away from the miniPCIe format and to M.2 formats. In the M.2 formats, there are PCIe interfaces defined (x1, x2 and x4) and a SATA interface defined, similar to the miniPCIe / mSATA pin sharing format shown in the Table above. The M.2 PCIe x 4 format, sometimes referred to as NVMe, offer a much higher interface bandwidth than mSATA. **3.5.3. M.2 SATA SSDs** The PCI Express M.2 Specification defines several M.2 format SATA SSD options that may be used in COM-HPC systems. These include (but are not limited to): * Socket 2 B-M Key (Table 3-23 in the PCI-SIG Version 4.0 M.2 document) * Socket 3 M Key (Table 3-28) These are not diagrammed here as SATA SSD implementations seem to be losing ground to PCIe based SSD implementations. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 34/159](.picmg-com-hpc-carrier-design-guide-alt/slide-036.jpg) ## Slide 37 ![Reference Schematics and Block Diagrams **3.6. PCI Express** **3.6.1. General Notes** The COM-HPC PCIe resources are divided into 5 Groups: * Group 0 Low (8 lanes) * Generally used for smaller links (x1, x2, x4) and slower PCIe link speeds (PCIe Gen 1,2,3). * Group 0 High (8 lanes) * Recommended for use with one or two PCIe x4 NVME SSD instances * The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group * Group 1 (16 lanes) * Recommended for PEG use * The COM-HPC specification recommends that higher bandwidth PCIe links be steered to this Group * Group 2 (16 lanes) * General purpose links – x16 or combinations of x8 and / or x4 * Group 3 (16 lanes) * Available on the Server pinout only Each PCIe Group listed above has it's own 100 MHz PCIe Reference Clock pair from the COM-HPC Module. Additionally, there is a CLKREQ# (Clock Request) input to the Module for each PCIe Group. There is one additional PCIe link available on both the Client and Server pinouts. This is a x1 link for use with a Carrier BMC (Board Management Controller). The BMC PCIe link makes use of the Group 0 PCIe Reference Clock pair. If only a single PCIe link (of any link width – x1, x2, x4, x8 or x16) is used from a PCIe Group, then the COM-HPC PCIe Reference Clock pair may be used directly with the link target. If a Group uses more than one link (i.e. 2 or more links) then a Carrier Board PCIe Reference Clock buffer is needed for that Group. Many PCIe clock buffer products are available on the market. Buffers with 2,4,6 or 8 and more output pairs are available. The buffer must be appropriate for the fastest PCIe link in the Group (PCIe Gen 3, 4 or 5). Several examples are shown in the schematics below. If the link's PCIe target is located on a slot card or a mezzanine board such as an M.2 site, the connector involved must be rated for the fastest PCIe link in use for that target. At the time of this writing, most such connectors are PCIe Gen 3 capable. Gen 4 and Gen 5 capable connectors are becoming available, most visibly from Amphenol FCI. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 35/159](.picmg-com-hpc-carrier-design-guide-alt/slide-037.jpg) ## Slide 38 ![**Reference Schematics and Block Diagrams** **3.6.2. PCI Express Coupling Capacitor Locations** The proper positions for PCIe data pair coupling capacitors is shown in Figure 11 below. * COM-HPC Module TX pair coupling caps are on the COM-HPC Module. * COM-HPC Module RX pair coupling caps are NOT on the COM-HPC Module. * For **most** Device Up mezzanine card implementations (Slot card, Mini-PCle, and M.2 card) the coupling caps are up on the mezzanine card, close to the mezzanine target device TX pins. * The exception to this rule is with MXM-3 graphics cards: there are no PCIe coupling caps at all on a MXM-3 graphics card. The COM-HPC Module TX lines are AC coupled on the COM-HPC Module. The COM-HPC Module RX lines are AC coupled on the Carrier, near the MXM-3 Module TX pins. * For Device Down implementations, the coupling caps are down on the Carrier board, close to the target device TX pins. **Figure 11: PCIe Data Line Coupling Capacitor Positions (MXM-3 Cards Excluded)** (Diagram Description) The diagram is a block schematic showing connections between a 'COM-HPC Module' on the left, a central 'Connector,' and two device configurations on the right. * **COM-HPC Module:** A box containing a smaller box with pins labeled TX+, TX-, RX+, RX-. Coupling capacitors (parallel lines) are located on the TX+ and TX- lines. * **Device Up:** A top box on the right labeled 'Device Up' containing a 'PCIe Add-in Device' box with pins RX+, RX-, TX+, TX-. Coupling capacitors are located on the TX+ and TX- lines (near the device TX pins). * **Device Down:** A bottom box on the right labeled 'Device Down' containing a 'PCIe Add-in Device' box with pins RX+, RX-, TX+, TX-. Coupling capacitors are located on the TX+ and TX- lines (near the device TX pins). This section is labeled 'Carrier Board' at the bottom. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 36/159](.picmg-com-hpc-carrier-design-guide-alt/slide-038.jpg) ## Slide 39 ![**Header:** Reference Schematics and Block Diagrams **Section Title:** 3.6.3. PCIe Group 0 Low Examples: Device Down, mini-PCIe, M.2 E-Key, M.2 B-Key **Figure Title:** Figure 12: PCIe Device Down on Carrier – PCIe Group 0 Low – PCIe Lane 0 **Schematic Diagram Text:** * **Component:** U9 * **Vertical Label:** SECTION 1 OF 4 * **Top Left Connections:** * COM PCIe0_TX+ (Pin 24) * COM PCIe0_TX- (Pin 23) * 5 PCIe_CLK_GOL_0+ (Pin 26) * 5 PCIe_CLK_GOL_0- (Pin 25) * WAKE0# -) 0ohms -) R55 -) 1% -) 0402 -) 5 * PCIe RESET GOL 0# (Pin 17) * WAKE_GOL 1# (Pin 16) * LAN1 SMB_SCL (Pin 34) * LAN1 SMB_SDA (Pin 36) * LAN1 SMB_ALERT# (Pin 35) * 5.1Kohms R64 * 5.1Kohms R65 * 5.1Kohms R66 * 3.3V 60 * **U9 Chip Pins (Left Column):** PE_R+, PE_R-, PECLK+, PECLK-, PE_RST#, PE_WAKE#, SMB_CLK, SMB_DATA, SMB_ALERT# * **U9 Chip Pins (Right Column):** PE_T+, PE_T-, NC_SI_CLK_IN, NC_SI_CR5_DV, NC_SI_TX_EN, NC_SI_ARB_IN, NC_SI_ARB_OUT, NC_SI_TXD0, NC_SI_TXD1, NC_SI_RXD0, NC_SI_RXD1 * **Bottom Label:** i210 * **Note:** 'This reference sheet does not show the full Intel WGI210T device but only shows the PCIe, Wake, and Clocking interfaces' * **Top Right Connections:** * 21 PE_I210_GOL_RX+ -) 0.22uF -) C44 -) 10V -) 0402 -) PCIe0_RX+ -) COM * 20 PE_I210_GOL_RX- -) 0.22uF -) C45 -) 10V -) 0402 -) PCIe0_RX- -) COM * **Right Side Signals:** * 2 NCSIO_LAN_CLK * 3 NCSIO_LAN_CR5_DV * 7 NCSIO_LAN_TXEN * 43 NCSIO_LAN_ARB_IN * 44 NCSIO_LAN_ARB_OUT -) To i210 Strapping Resistors * 9 NCSIO_LAN_TXD(0) * 8 NCSIO_LAN_TXD(1) * 6 NCSIO_LAN_RXD(0) * 5 NCSIO_LAN_RXD(1) **Body Text:** 'This figure shows a portion of an Intel i210 Gigabit Ethernet implementation, the portion that is relevant to the COM-HPC Module interface. This figure shows the interface to the COM-HPC and to some Carrier board circuit elements such as an appropriate PCIe Clock buffer, shown later in this section.' 'The key point of this Figure is that coupling caps (C44 and C45 in the Figure) are needed on the Carrier, for the Carrier target device TX pair pins. These are the PCIe RX lines for the Module. These Carrier coupling caps are to be placed close to the i210 device, in a symmetric manner consistent with high speed PCB design practices.' 'Coupling caps for COM-HPC PCIe TX lines are on the Module, and are never needed on a COM-HPC Carrier.' 'If the PCIe target device is a slot or mezzanine card, the coupling caps for the target device are on the slot or mezzanine card and not on the Carrier. - except for MXM graphics card implementations. This case is discussed in Section 3.6.7 below.' **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 37/159](.picmg-com-hpc-carrier-design-guide-alt/slide-039.jpg) ## Slide 40 ![**Reference Schematics and Block Diagrams** **Figure 13: Mini-PCIe Site – PCIe Group 0 Low – PCIe Lane 1** The slide displays a detailed electronic schematic diagram. The top section features a connection diagram for a Mini-PCIe connector (labeled **J3**), showing signal lines for PCIe, USB, SMB, and power rails (such as **+3.3V_S** and **+1.5V_S_GOL**), along with associated resistors, capacitors, and inductors. Below this, a middle section shows connector labels (**HW1**, **HW2**, **HW6**, **HW7**). The bottom section illustrates a voltage regulator circuit utilizing component **U5** (labeled **AP7173**) with input/output connections and a specification box indicating **+1.5V_S**. **PICMG® COM-HPC® Carrier Design Guide** **Rev. RC2.0d / Dec 7, 2021** **38/159**](.picmg-com-hpc-carrier-design-guide-alt/slide-040.jpg) ## Slide 41 ![The slide displays a technical schematic under the header **'Reference Schematics and Block Diagrams'**. The main title is **'Figure 14: M.2 E-Key Site – WiFi Cards – PCIe Group 0 Low – PCIe Lane 2'**. The central diagram shows the pinout for connector **J4** (labeled **TE-Connectivity_1-2199230**), detailing connections for various signals including PCIe, UART, SDIO, and power rails across pins 1 through 77. Two smaller circuit sections are at the bottom: * **Bottom Left:** Labeled **'Mounting hole for M.2 EXPANSION'**. It lists **'MM_DS_M2.5x0.45x2.5MM'** and component **'ZNL1'**, with the note **'Move solderpaste layer of HW5 to top side.'** * **Bottom Right:** A power circuit section featuring the label **'2.5A'** and components labeled with values like **'0805'** and **'50mR'**. The footer reads: **'PICMG® COM-HPC® Carrier Design Guide'** **'Rev. RC2.0d / Dec 7, 2021'** **'39/159'**](.picmg-com-hpc-carrier-design-guide-alt/slide-041.jpg) ## Slide 42 ![Reference Schematics and Block Diagrams Figure 15: M.2 B-Key Site – Cell Modem Cards – PCIe Group 0 Low – PCIe Lane 3 +3.3V_S_3V7_3V3 74 V_3V3_74 72 V_3V3_72 70 V_3V3_70 68 SUSCLK 66 SIM_DETECT 64 COEX1 62 COEX2 60 COEX3 58 NC_56 54 PEWAKE# 52 CLKREQ# 50 PERS#1# 48 UIM_RST_G0L_BU 46 GPIO_3 44 UIM_DATA_G0L_BU 42 GPIO_0/SMB_CLK 40 DEVSLP 38 UIM_PWR 36 UIM_DATA 34 UIM_CLK 32 UIM_RESET 30 GPIO_8 28 GPIO_10 26 GPIO_7 24 GPIO_6 22 GPIO_5 20 CONNECTOR-KEY_18 18 CONNECTOR-KEY_16 16 CONNECTOR-KEY_14 14 CONNECTOR-KEY_12 12 GPIO_9/ASUS5SRL1# 8 W_DISABLE# 6 FULL_CARD_POWER_OFF# 4 MODEM_PWR_EN 2 V_3V3_2 0 M_77 75 CONFIG_2 73 GND_73 71 GND_71 69 RESET# 67 PCI_RESET_G0L_3A# 65 ANTCTL3 63 ANTCTL2 61 ANTCTL1 59 ANTCTL0 57 MOD1_V_3V7_3V3_SEL_G0L 55 REFCLKP 53 REFCLKN 51 PCIe_TX+ 49 PCIe_TX- 47 PCIe_RX+ 45 PCIe_RX- 43 USB0_SSTX+ 41 USB0_SSTX- 39 USB0_SSRX+ 37 USB0_SSRX- 35 M2_DPR_G0L_B 33 GND_33 31 USB0_D- 29 USB0_D+ 27 USB0_VBUS 25 GND_25 23 CONFIG_0 21 CONNECTOR-KEY_19 19 CONNECTOR-KEY_17 17 CONNECTOR-KEY_15 15 CONNECTOR-KEY_13 13 GND_11 11 USB_D- 9 USB_D+ 7 USB0_VBUS 5 GND_3 3 CONFIG_3 1 M_76 WAKE# R53 0ohms WAKE_G0L_2# PCIe_CLKREQ_G0L_3# PCIe_RESET_G0L_3A# UIM VCC_G0L_BU UIM CLK_G0L_BU GPIO External Buff G0L_M2_1_WIFI_DIS_2# G0L_M2_1_WIFI_DIS_1# GPIO R11 10kOhms R12 10kOhms R13 10kOhms R9 10kOhms R10 10kOhms R14 10kOhms Pinout based on using a Sierra Wireless EM7455 +3.3V_S_3V7_3V3 C12 0.1uF C10 0.1uF C13 0.1uF C1 0.1uF C2 0.1uF C4 0.1uF C6 0.1uF C8 0.1uF C10 0.1uF C12 0.1uF C14 0.1uF M.2 Retention Hardware HW3 M2_5x2_9MM Dual SIM card socket J1 U8 U7 U6 7-U IO_7-U 6-U CLK_3-U 5-U RST_2-U 4-U GND_5-U 3-U UPPER CARD 2-U LOWER CARD 1-U IO_7-L 0-U CLK_3-L 9-U RST_2-L 8-U GND_5-L 1-U V_UIM_VCC_G0L_BU 0-U V_UIM_VPP_G0L_BU 6-U V_UIM_VCC_G0L_BU 5-U V_UIM_VPP_G0L_BU 4-L V_UIM_VCC_G0L_BL 3-L V_UIM_VPP_G0L_BL 2-L VCC_G0L_T1 1-L GND VCC_G0L_T3 UIM_DATA_G0L_BU UIM_CLK_G0L_BU UIM_RST_G0L_BU VCC_G0L_T2 UIM_DATA_G0L_BL UIM_CLK_G0L_BL UIM_RST_G0L_BL VCC_G0L_T1 R51 0ohms R52 0ohms S1 S2 S3 S4 CH_GND PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 40/159](.picmg-com-hpc-carrier-design-guide-alt/slide-042.jpg) ## Slide 43 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 16: Clock and Reset Buffers for PCIe Group 0 Low Example Circuits **Top Circuitry (Power Filters):** * **Components:** FB1 (600, 0805), FB3 (600, 0803), FB2 (600, 0803) * **Capacitors:** C15 (1uF, 10V, 0603), C40 (10uF, 0.1uF, 0603), C6 (0.1uF, 25V, 0402); C16 (1uF, 10V, 0603), C38 (10uF, 0.1uF, 0603), C7 (0.1uF, 25V, 0402); C17 (1uF, 10V, 0603), C39 (10uF, 0.1uF, 0603), C42 (0.1uF, 25V, 0402) * **Rails:** +3.3V S, +3.3V_S VDD, +3.3V_S VDDR, +3.3V_S_VDDA **Main IC (U1):** * **Pins/Signals:** BW_MODE_GOL, PWRGD_PD_GOL#, SADR_GOL, PCIe_CLK_SDA (0ohms, 1%, 0402), PCIe_CLK_SCL (0ohms, 1%, 0402), PCIe_CLKREQ_GOL_0#, OE2#, OE3#, CLK_IN+, CLK_IN-, FB_DNC+, FB_DNC-, GND_DIG, GND_TAB, HIBW_BYPM_LOBW#, V_3V3_DIG, V_3V3_VDDR, V_3V3_VDDA, SDATA_3V3, SCLK_3V3, DIF0- through DIF3+, NC_7, NC_16, NC_20, NC_28, NC_30, PCIe_CLK_GOL_0- through PCIe_CLK_GOL_3+. * **Note:** 90BL0452 (bottom left). **Left Signals:** * PCIe_CLKREQ_GOL_1#, PCIe_CLKREQ_GOL_2#, PCIe_CLKREQ_GOL_3#, PCIe_REFCLK0_LO+, PCIe_REFCLK0_LO- **Middle Connections & Resistors:** * **Signal:** PCIe_CLKCLK_GOL_0# (0ohms, 0402, GND) * **Note:** COM-HPC external PCIe Clock always requested due to CI10 chip down * **Resistors R15-R28:** 100k ohm, 1%, 0402 (repeated) * **Connected Signals:** PCIe_CLKREQ_GOL_3#, PCIe_CLKREQ_GOL_2#, PCIe_CLKREQ_GOL_1#, PCIe_CLKREQ_GOL_0#, SADR_GOL, PWRGD_PD_GOL#, BW_MODE_GOL **Configuration Tables:** * **SADR: SMBUS ADDR:** 0 0x6B (7-bit), M 0x6C (7-bit), 1 0x6D (7-bit) (Default) * **BW_MODE:** 0 LOW BW_MODE, M BYPASS_MODE (Default), 1 HIGH BW_MODE **Lower Circuitry (U2, U3, U4):** * **Resistor R11:** 2.86kohm, 1%, 0402 * **Capacitor C10:** 0.1uF, 25V, 0402 * **Signals:** PCle_CLK_SCL, PCle_CLK_SDA * **IC U2 (FXMA2102):** V_VCCB, V_VCCA, B0, B1, GND, OE, A0, A1, SMB_CLK, SMB_DAT (COM) * **Note:** *Only on buffer per board needed * **IC U3 (74LVC1G125):** PLTRST#, 1, 2, 3, 4, 5, VCC, GND. Capacitor C9 (0.1uF, 25V, 0402). * **Outputs U3:** PCI_RESET_GOL_0#, PCI_RESET_GOL_1#, PCI_RESET_GOL_2# (via resistors R31, R32, R33: 22ohms, 1%, 0402) * **IC U4 (74LVC1G125):** 1, 2, 3, 4, 5, VCC, GND. Capacitor C11 (0.1uF, 25V, 0402). * **Outputs U4:** PCI_RESET_GOL_3A#, PCI_RESET_GOL_3B# (via resistors R35, R36: 22ohms, 1%, 0402) **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 41/159](.picmg-com-hpc-carrier-design-guide-alt/slide-043.jpg) ## Slide 44 ![**Reference Schematics and Block Diagrams** **3.6.4. Dual PCIe x4 M.2 M Key NVME SSDs Examples on PCIe Group 0 High** The following three figures illustrate a dual PCIe x4 M.2 M Key deployment for NVME SSDs. The COM-HPC specification recommends that PCIe Group 0 High be used for this purpose. **Figure 17: M.2 M-Key Site for NVME SSD Card #1 in Group 0 High PCIe Lanes 8:11** **Schematic Text and Labels:** * **Top Annotation:** 22x80mm M-type, 4.2mm connector height * **Connector J2 (Left Pins/Labels):** +3.3V_S, V_3V3_74, V_3V3_72, V_3V3_70, SURCLK, CONNECTOR_KEY_68, CONNECTOR_KEY_66, CONNECTOR_KEY_64, CONNECTOR_KEY_62, CONNECTOR_KEY_60, NC_58, NC_56, PEWAKE#, CLKREQ#, PERST#, NC_48, NC_46, ALERT#, SMB_DATA, SMB_CLK, DEVSLP, NC_40, NC_38, NC_36, NC_34, NC_32, NC_30, NC_28, NC_26, NC_24, NC_22, NC_20, V_3V3_18, V_3V3_16, V_3V3_14, V_3V3_12, DAS/SSLED1#, NC_8, NC_6, V_3V3_4, V_3V3_2, MTG_77 * **Connector J2 (Right Pins/Labels):** GND_75, GND_73, GND_71, PEDET, NC_69, CONNECTOR_KEY_65, CONNECTOR_KEY_63, CONNECTOR_KEY_61, CONNECTOR_KEY_59, NC_57, REFCLK+, REFCLK-, GND_51, PER0/SATA-A+, PER0/SATA-A-, PER0/SATA-B+, PER0/SATA-B-, GND_39, PET+, PET1+, PET1-, PET2+, PET2-, PET3+, PET3-, GND_9, PER0+, PER0-, GND_1, MTG_76 * **Connector J2 (Network Connections - Right):** PCI_0_CLK_G0H_1+, PCI_0_CLK_G0H_1-, PCI_0_TX+, PCI_0_TX-, PCI_0_RX+, PCI_0_RX-, PCI_8_TX+, PCI_8_TX-, PCI_8_RX+, PCI_8_RX-, PCI_9_TX+, PCI_9_TX-, PCI_9_RX+, PCI_9_RX-, PCI_10_TX+, PCI_10_TX-, PCI_10_RX+, PCI_10_RX-, PCI_11_TX+, PCI_11_TX-, PCI_11_RX+, PCI_11_RX- * **Connector J2 (Network Connections - Left):** PCI_CLKREQ_G0H_1#, PCI_RESET_G0H_1#, SMB_DAT_G0H_1, M2_G0H_1.DEVSLEEP, +3.3V_S, +1.8V_G0H, M2_G0H_1.SSD_ACT# * **Annotations:** * REV 1.1 * Not connecting SMBus on connectors to COM-HPC main SMBus due to the inability to guarantee unique SMBus addresses * M.2 Retention Hardware * M2.5x2 SMM * Staggered spin-up isn't disabled by default. From SATA specification, DAS pullup voltage is Vth = 1.8V to 2.1V max. It must be buffered to drive a LED. * M2_G0H_1.SSD_ACT_D# * M2_G0H_1.SSD_ACT# * Q3 MMBT3904 SOT23 * Q4 MMBT3904 SOT23 * 80 to 180mA @ 20mA, 25C * 22 to 45mA @ 5mA, 25C * Vi @ 20mA = 1.9V typ, 2.0V typ, 2.4V max * Vi @ 5mA = 1.85V typ. * @0.58A max * U2 (IC Labels): IN_1, IN_2, EN, PG, BIAS, OUT_9, OUT_10, FB, 1V8_FB, SS, 1V8_SS, GND, TH_PAD * AP1773 * 1.4kohms * VOUT = 0.91*(1+R1/R2) 1.782V (typ) **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 42/159](.picmg-com-hpc-carrier-design-guide-alt/slide-044.jpg) ## Slide 45 ![**Reference Schematics and Block Diagrams** **Figure 18: M.2 M -Key Site for NVME SSD #2 in Group 0 PCIe Lanes 12:15** **Schematic Text:** * 22x80mm M-type * 4.2mm connector height * +3.3V_S * PCIe_CLKREQ_G0H_2# * PCIe_RESET_2# * Not connecting SMBus on connectors to COM-HRD main SMBus due to the inability to guarantee unique SMBus addresses * SMB_DAT_G0H_2 * SMB_CLK_G0H_2 * M2_G0H_1_DEVSLP * M2_G0H_2_ACT# * Stagered spin-up isn't disabled by default. From SATA specification, DAS pullup voltage is 1.8V to 1.9V max. It must be buffered to drive a LED. * J1 Pin Names: GND_75, GND_73, GND_71, PEDET, NC_67, CONNECTOR_KEY_65, CONNECTOR_KEY_63, CONNECTOR_KEY_61, CONNECTOR_KEY_59, NC_58, NC_56, PEWAKE#, CLKREQ#, PERST#, NC_48, NC_46, ALERT#, SMB_DATA, SMB_CLK, DEVSLP#, NC_38, NC_34, NC_32, NC_30, NC_28, NC_26, NC_24, NC_22, NC_20, V_3V3_18, V_3V3_16, V_3V3_14, V_3V3_12, DAS/DSS/LED1#, NC_8, NC_6, V_3V3_4, V_3V3_2, MTG_77, TE-Connectivity_1-2199230_CARD, MTG_76. * Right Side Connections: PCIe CLK_G0H 2+, PCIe CLK_G0H 2-, PCIe12 TX+, PCIe12 TX-, PCIe12 RX+, PCIe12 RX-, PCIe13 TX+, PCIe13 TX-, PCIe13 RX+, PCIe13 RX-, PCIe14 TX+, PCIe14 TX-, PCIe14 RX+, PCIe14 RX-, PCIe15 TX+, PCIe15 TX-, PCIe15 RX+, PCIe15 RX-. * M.2 Retention Hardware * M.2 5x2.5MM * SSD Activity LED * 270ohms * M2_G0H_2_SSD_ACT_D# * M2_G0H_2_SSD_ACT_G# * 90 to 180mcd @ 20mA, 25C * 22 to 45mcd @ 6mA, 25C * Vf @ 20mA = 1.9V min, 2.0V typ, 2.4V max * Vf @ 6mA = 1.85V typ. * Q1 MMBT3904 SOT23 * Q2 MMBT3904 SOT23 **Text Below Schematic:** The M.2 M-Key connector used must have a PCIe 'speed rating' at least as high as the link speed being used (PCIe Gen 3, 4 or 5). PCIe Gen 3 capable M.2 connectors are common. At the time of this writing, PCIe Gen 4 and 5 capable M.2 connectors are not common. PCIe Gen 4 capable M.2 connectors are available from Amphenol FCI. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 43/159](.picmg-com-hpc-carrier-design-guide-alt/slide-045.jpg) ## Slide 46 ![**Header:** Reference Schematics and Block Diagrams Figure 19: Clock Buffer and Reset for PCIe Dual M.2 NVME SSD PCIe Group 0 High **Schematic Annotations (Blue Boxes):** SADR: SMBUS ADDR 0 0x6B (7-bit) M 0x6C (7-bit) 1 0x6D (7-bit) (Default) BW_MODE 0 LOW BW MODE M BYPASS MODE (DEFAULT) 1 HIGH BW MODE **Schematic Components & Signals:** U1: 74LVC1G08 U3: 74LVC1G125 U4: 9DBL0252 Signals/Labels visible in the diagram include: +3.3V_S_G0H_VDD, +3.3V_S_G0H_VDDR, +3.3V_S_G0H_VDDA, SMB DAT, SMB CLK, PCIe_CLKREQ_G0H_1#, PCIe_CLKREQ_G0H_2#, PCIe_REFCLK0_H+, PCIe_REFCLK0_H-, COM, CLK_BUFF_SMB_DATA, CLK_BUFF_SMB_CLK, PLTRST#, PCI_RESET#, G0H_PCI_RESET_1#, G0H_PCI_RESET_2#, DIF0, DIF1, DIF0+, DIF1+, etc. **Descriptive Text:** A dual channel clock buffer is used as there are two PCIe x4 links implemented in this PCIe Group 0 High example. The COM-HPC PCIe_CLKREQ0_HI# signal is driven by logic gate U1 in the Figure just above, resulting in a clock request if either one or both of the NVMe cards are present. Alternatively, U1 could be removed and the COM-HPC Group 0 High clock request line held low by R34, in which case the Group 0 High PCIe clock pair would always run. The clock buffer shown is the 9DBL0252 from Renesas / IDT. It is PCIe Gen 1,2,3,4 and 5 capable. The PLTRST# buffer shown, U3, is a 74LVC1G125 device that tolerates a signal input between 0 and 5.5V even in the absence of the VCC to the device. The PLTRST# signal is in the S5 power domain; the VCC applied to U3 is in the S0 domain. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 44/159](.picmg-com-hpc-carrier-design-guide-alt/slide-046.jpg) ## Slide 47 ![**Header:** Reference Schematics and Block Diagrams **Section Title:** 3.6.5. PCIe x16 Slot Card Site on PCIe Group 1 **Figure Caption:** Figure 20: PCIe x16 Slot Card Site on PCIe Group 1 PCIe Lanes 16:31 **Diagram Description:** The slide features a detailed schematic showing the pinout for connector J1. It maps out PCIe differential pairs (TX/RX) for lanes 16 through 31, power rails (+12V, +3.3V), clock signals, and reset lines. A smaller inset diagram labeled 'Optional' shows a buffer circuit (U1, 74LVC100) and a reset circuit (U2, 74LVC10125). **Body Text:** No PCIe clock buffer is needed as there is only one PCIe link in this example. The COM-HPC Group 1 PCIe clock pair is used directly. If the group is split into two or more links, then a PCIe clock buffer would be required. The slot connector used must be rated and qualified for the PCIe link speed expected. Slot connectors rated for PCIe Gen 3 and below are common. Connectors rated for PCIe Gen 4 and Gen 5 are at the time of this writing are still new. Such parts are available from Amphenol FCI and others. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 45/159](.picmg-com-hpc-carrier-design-guide-alt/slide-047.jpg) ## Slide 48 ![**Reference Schematics and Block Diagrams** **3.6.6. PCIe Group 2** Figures 21 through 24 below illustrate the implementation of 3 PCIe slots on COM-HPC PCIe Group 2, along with a PCIe clock buffer appropriate for use with PCIe Gen 4 and below. The slot RESET# signals come from a buffer in Figure 24. Additional notes are provided after the last Figure in this series. **Figure 21: PCIe x8 Slot Card Site on PCIe Group 2 PCIe Lanes 32:39** **Schematic J1 Content:** * **Top Left/Center:** ICT11 A5, ICT12 A6, ICT13 A7, ICT14 A8, ICT15 B9, JTAG2_TCK, JTAG2_TDI, JTAG2_TDO, JTAG5_TMS, JTAG1_TRST#, PCIe_CLK_G2_1+ A13, REFCLK+, PCIe_CLK_G2_1- A14, REFCLK-, PCIe32_TX+ B14, PET0+, PCIe32_TX- B15, PET0-, PCIe33_TX+ B19, PET1+, PCIe33_TX- B20, PET1-, PCIe34_TX+ B23, PET2+, PCIe34_TX- B24, PET2-, PCIe35_TX+ B27, PET3+, PCIe35_TX- B28, PET3-, PCIe36_TX+ B33, PET4+, PCIe36_TX- B34, PET4-, PCIe37_TX+ B38, PET5+, PCIe37_TX- B39, PET5-, PCIe38_TX+ B42, PET6+, PCIe38_TX- B43, PET6-, PCIe39_TX+ B45, PET7+, PCIe39_TX- B46, PET7- * **Top Right:** +12V_S A2, V_12V0_A2 A3, V_3V3_A9 B1, V_12V0_B1 B2, V_12V0_B3 B3, +3.3V_S A9, V_3V3_B8 B8, +3.3V_A B10, V_12V0_B2, PERST# A11, PCI_RESET_G2_1#, PER0+ A16, PCIe32_RX+, PER0- A17, PCIe33_RX+, PER1+ A21, PCIe33_RX-, PER1- A22, PCIe34_RX+, PER2+ A25, PCIe34_RX-, PER2- A26, PCIe35_RX+, PER3+ A29, PCIe35_RX-, PER3- A30, PCIe36_RX+, PER4+ A35, PCIe36_RX-, PER4- A36, PCIe37_RX+, PER5+ A39, PCIe37_RX-, PER5- A40, PCIe38_RX+, PER6+ A43, PCIe38_RX-, PER6- A44, PCIe39_RX+, PER7+ A47, PCIe39_RX-, PER7- A48 * **Middle Left:** WAKE0# R28 0ohms 0402 1% WAKE0_G2_1# B11, PCIe_CLK_SCL R33 0ohms 0402 UNI 1% B5, SMCLK, PCIe_CLK_DAT R34 0ohms 0402 UNI 1% B6, SMDAT, EPRBRK_G2_1# B30 * **Middle/Bottom Right:** PRSNT1# A1, PRSNT2#_B17 B17, PRSNT2#_B31 B31, PRSNT2#_B48 B48, PCIe_CLKREQ_G2_1#, GND_B4 B4, GND_B7 B7, GND_B13 B13, GND_B16 B16, GND_B18 B18, GND_B21 B21, GND_B22 B22, GND_B25 B25, GND_B26 B26, GND_B29 B29, GND_B32 B32, GND_B35 B35, GND_B36 B36, GND_B39 B39, GND_B40 B40, GND_B43 B43, GND_B44 B44, GND_B47 B47, GND_B49 B49 * **Bottom Left Pins:** A4, A12, A15, A18, A20, A23, A24, A27, A28, A31, A34, A37, A38, A41, A42, A45, A46, A49 * **Bottom Left Grounds:** GND_A4, GND_A12, GND_A15, GND_A18, GND_A20, GND_A23, GND_A24, GND_A27, GND_A28, GND_A31, GND_A34, GND_A37, GND_A38, GND_A41, GND_A42, GND_A45, GND_A46, GND_A49 * **Internal/Other:** RSVD_A19, RSVD_A32, RSVD_A33, RSVD_B12, RSVD_B30, PCI_10141523-122Y, M1, M2 **Annotations:** * COM (repeated next to TX/RX lines) * Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to guarantee unique SMBus addresses * Signal can also be used as a present **Optional Box:** * Optional * U5 * +3.3V_S * NC, 1 * VCC, 5 * 4 * 3 * GND * 74LVC1G07 * EPRBRK_G2_1# * Open Drain Signal * GPIO_EPRBRK_G2_1# * Driven from any source os GPIO logic * R17 0.402 1% 10KOhms **Components:** * C42 0.1uF 35V 0402 * C43 100uF 16V P7A X5S * C10 100uF 16V X6S * C11 10uF 16V X6S **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 46/159](.picmg-com-hpc-carrier-design-guide-alt/slide-048.jpg) ## Slide 49 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 22: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 40:43 **Schematic Top Left:** +12V_S, +3.3V_S, +3.3V_A, +12V_S C1, 100uF, 16V, X54-31, GND C4, 100uF, 16V, X5S, GND C9, 10uF, 16V, 0603, GND ICT2, ICT3, ICT4, ICT5 **Schematic J2 Left Pins:** J2 A1 PRSNT1#, A2 V_12V0_A2, A3 V_12V0_B3, A4 GND_A4 A5 JTAG2_TCK, A6 JTAG3_TDI, A7 JTAG4_TDO, A8 JTAG5_TMS A9 V_3V3_A9, A10 V_3V3_A10, A11 PERST#, A12 PCI_RESET_G2_2# A13 PCIe_CLK_G2_2+, A14 PCIe_CLK_G2_2-, A15 PCIe40_RX+, A16 PCIe40_RX- A17 PER0+, A18 PRSNT2#_B17, A19 GND_A18, A20 RSVD_A19 A21 GND_A20, A22 PER1+, A23 GND_B21, A24 PER1- A25 GND_A23, A26 PER2+, A27 GND_B22, A28 PER2- A29 GND_A25, A30 PER3+, A31 GND_B29, A32 PER3- MTG1, GND, CASE1 FCL_10141523-121Y **Schematic J2 Right Pins:** B1 V_12V0_B1, B2 V_12V0_B2, B3 V_12V0_B3, B4 GND_B4 B5 SMCLK, B6 SMDAT, B7 GND_B7, B8 V_3V3_B8 B9 JT1G1_TRST#, B10 V_3V3_AUX_B10, B11 WAKE#, B12 RSVD_B12 B13 GND_B13, B14 REFCLK+, B15 PET0+, B16 PET0- B17 GND_B16, B18 PRSNT2#_B17, B19 GND_B18, B20 PET1+ B21 PET1-, B22 GND_B21, B23 PET2+, B24 PET2- B25 GND_B25, B26 PET3+, B27 PET3-, B28 GND_B29 B29 PET3+, B30 RSVD_B30, B31 PRSNT2#_B31, B32 GND_B32 MTG2, GND, CASE2 **Schematic Top Right:** +12V_S, +3.3V_S, +3.3V_A 0ohms, 1%, DNI, R31, 0402, PCIe_CLK_SCL, COM 0ohms, 1%, DNI, R32, 0402, PCIe_CLK_DAT, COM Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to guarantee unique SMBus addresses WAKE0_G2_2#, 0ohms, 1%, R27, 0402, WAKE0#, COM **Schematic Middle Right:** PCIe40_TX+, COM, PCIe40_TX-, COM PCIe41_TX+, COM, PCIe41_TX-, COM PCIe42_TX+, COM, PCIe42_TX-, COM PCIe43_TX+, COM, PCIe43_TX-, COM **Schematic Bottom Right:** EPRBRK_G2_2#, PCIe_CLKREQ_G2_2# Signal can also be used as a present **Optional Circuit:** +3.3V_S, R13, 0402, 10Kohms, 1% C12, 0402, 0.1uF Optional, U3, 74LVC1G07 VCC, NC, 1, 2, 3, GND, 5, 4 GPIO_EPRBRK_G2_2#, Driven from any source or GPIO logic R12, 0402, 10Kohms, 1% EPRBRK_G2_2#, Open Drain Output Signal **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 47/159](.picmg-com-hpc-carrier-design-guide-alt/slide-049.jpg) ## Slide 50 ![**Reference Schematics and Block Diagrams** **Figure 23: PCIe x4 Slot Card Site on PCIe Group 2 PCIe Lanes 44:47** The slide displays a schematic diagram featuring a connector **J3** (labeled **FCI_10141523-121Y**). **Left Side:** * **Power Rails:** **+12V_S**, **+3.3V_S**, **+3.3V_A** * **Components:** Capacitors **C2** (100uF, 25V, 7343-31, PTA), **C5** (100uF, 10V, X6S), **C10** (0.1uF, 16V, X6S). * **Test Points:** **ICT7**, **ICT8**, **ICT9**, **ICT10**. * **Signals:** **PCI_RESET_G2_3#**, **PCIe_CLK_G2_3+**, **PCIe_CLK_G2_3-**, **PCIe44_RX+**, **PCIe44_RX-**, **PCIe45_RX+**, **PCIe45_RX-**, **PCIe46_RX+**, **PCIe46_RX-**, **PCIe47_RX+**, **PCIe47_RX-**. **Connector J3 Pins:** * **Side A (A1-A32):** Includes labels such as **PRSNT1#**, **V_12V0_A2**, **JT2G2_TCK**, **JT4G3_TDI**, **JT4G4_TDO**, **JT4G5_TMS**, **PERST#**, **REFCLK+**, **REFCLK-**, **PER0+**, **PER1+**, **PER2+**, **PER3+**, **RSVD_A19**, **MTG1**, **CASE1**. * **Side B (B1-B32):** Includes labels such as **V_12V0_B1**, **SMCLK**, **SMDAT**, **JTAG1_TRST#**, **WAKE#**, **PET0+**, **PRSNT2#_B17**, **PET1+**, **PET2+**, **PET3+**, **RSVD_B12**, **MTG2**, **CASE2**. **Right Side:** * **Power Rails:** **+12V_S**, **+3.3V_S** * **Components:** Resistors **R29** (0ohms, DNI, 0402, 1%), **R30** (0ohms, DNI, 0402, 1%), **R26** (0ohms, 0402, 1%). * **Signals:** **PCIe_CLK_SCL**, **PCIe_CLK_DAT**, **WAKE0_G2_3#**, **WAKE0#**, **PCIe44_TX+**, **PCIe44_TX-**, **PCIe45_TX+**, **PCIe45_TX-**, **PCIe46_TX+**, **PCIe46_TX-**, **PCIe47_TX+**, **PCIe47_TX-**, **EPRBRK_G2_3#**, **PCIe_CLKREQ_G2_3#**. * **Red Text Note:** 'Not connecting SMBus on connectors to COM-HPD main SMBus due to the inability to garantee unique SMBus addresses'. * **Red Text Note:** 'Signal can also be used as a present'. **Optional Section (Dashed Box):** * **Text:** **Optional** * **Components:** **U4** (74LVC1G07), **R25** (10Kohms, 1%, 0402), **C13** (25V, 0.1uF), **R15** (10Kohms, 1%, 0402). * **Text:** **VCC**, **NC**, **1**, **2**, **GND**, **3**. * **Text:** **EPRBRK_G2_3#**, **Open Drain Output Signal**, **+3.3V_S**. * **Text:** **GPIO_EPRBRK_G2_3#**, **Driven from any source os GPIO logic**. **Footer:** **PICMG® COM-HPC® Carrier Design Guide** **Rev. RC2.0d / Dec 7, 2021** **48/159**](.picmg-com-hpc-carrier-design-guide-alt/slide-050.jpg) ## Slide 51 ![This slide presents a technical circuit diagram titled **'Figure 24: PCIe Clock Buffer and Reset Buffer for PCIe Group 2 Example'**. The image displays a complex schematic involving logic buffers (U22, U2, U1, U7), resistors, and capacitors, illustrating the wiring for PCIe clock and reset signals. Key text elements on the slide include: **Header:** * 'Reference Schematics and Block Diagrams' **Configuration Tables (Right Side):** * **SADR: SMBUS ADDR** * '0 0x6B (7-bit)' * 'M 0x6C (7-bit)' * '1 0x6D (7-bit)' * **BW_SEL_TRI** * '0 LOW BW MODE' * 'M BYPASS MODE (Default)' * '1 HIGH BW MODE' **Footer Notes (Red Text):** * '*Max 4 outputs per buffer' * '*Push/Pull design use LVC07 wih PU resistor for OC designs' **Footer:** * 'PICMG® COM-HPC® Carrier Design Guide' * 'Rev. RC2.0d / Dec 7, 2021' * '49/159'](.picmg-com-hpc-carrier-design-guide-alt/slide-051.jpg) ## Slide 52 ![**Reference Schematics and Block Diagrams** **3.6.7. MXM-3 Graphics Card Module on Carrier** The **COM Express Carrier Design Guide** Rev 2.0 Section 2.6 has a good schematic example of a MXM-3 graphics card implementation on COM Express Carriers. The net names used are not the same as the COM-HPC net names, but the correlation is straightforward. MXM-3 cards use a 16 lane PCI Express interface. Most MXM cards also allow x8 implementations (and all PCIe devices must work in x1 configurations per the PCI-SIG specification). COM-HPC recommends but does not require that COM-HPC PCIe Group 1 be used for PEG (PCI Express Graphics). No Carrier PCIe clock buffer is needed for the MXM card (assuming that the MXM card is only PCIe device used in the COM-HPC PCIe Group). The COM-HPC PCIe reference clock that goes with the COM-HPC PCIe group can be used directly with the MXM card. Coupling capacitors for the COM-HPC Module PCIe RX pairs (MXM card PCIe TX pairs) must be present on the Carrier, preferably close to the MXM connector. Use discrete 0402 or 0201 package size parts. The MXM-3 specification document is currently hard to find. The document was created and is owned by Nvidia but is not publicly available. Information found in the **COM Express Carrier Design Guide**, from the MXM-3 connector vendors (Aces, Amphenol / FCI, Foxconn, JAE, Yamaichi), from the MXM GPU card vendors and from the COM-HPC Module vendor should be sufficient to carry out a design. The Amphenol / FCI MXM-3 connector part number 10151114-001TLF supports all PCIe signal rates up to and including Gen 5. Note that MXM cards operate in the S0 power domain only. Any signals that are active in the S5 (suspend) power state must be isolated, in the S5 power state, from the MXM card. Note also that MXM-3 connectors have 314 individual pins, but the MXM-3 specification gangs multiple connector pins together for power delivery. The 314 individual connector pins are grouped together in the NVIDIA MXM-3 specification into PWR and GND blocks labeled E1, E2, E3 and E4, and then the pins left over are numbered 1 through 281. The MXM-3 connector drawings from the connector vendors usually illustrate this. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 50/159](.picmg-com-hpc-carrier-design-guide-alt/slide-052.jpg) ## Slide 53 ![Reference Schematics and Block Diagrams **3.6.8. PCIe Reference Clocks** COM-HPC, like COM Express and like most commercial and embedded PCI Express implementations, uses the “Common Clock” architecture defined in the PCI-SIG PCI Express Base Specification, Revisions 1 through 5. In this arrangement, there is a common 100 MHz reference clock source that feeds the PCIe Root complex and copies are fed to each PCIe Target device serviced by that Root. The maximum skew allowed between any two PCIe reference clocks, at their destinations, is 10 ns for PCIe Gen 1 and 12 ns for Gen 2 through 5. In most cases, the 100 MHz reference source is integrated into the SOC or chipset and the reference clock routing to the Root is internal to the SOC or chipset. In some cases, a clock generator IC that is external to the SOC or chipset is used. In any case, the 100 MHz reference source for a COM-HPC Root device is on the COM-HPC Module, either internal or external to the SOC or chipset. The SOC or chipset may provide one or multiple copies of the PCIe reference clock. If the SOC, chipset or Module does not provide enough copies of the reference clock for the Carrier PCIe targets then one or more PCIe clock buffers are used, on and / or off Module, depending on the situation. The PCIe targets use the 100 MHz reference clock copy, along with the clocking information embedded into the PCIe data stream to quickly form a local copy of the appropriate high frequency clock (2.5 GHz for Gen1, 5 GHz for Gen 2, and so on) needed to correctly interpret the incoming PCIe data stream, and to correctly time and encode the target’s outgoing data stream. Table 6 below lists the maximum clock jitter allowed for each PCIe generation, per the PCI-SIG source specifications, for the Common Clock architecture. Note the ever shrinking jitter allowance as the generations advance. For example, the Gen 5 jitter allowance is only 15% of the Gen 3 allowance. However, PCIe Gen 5 uses a different filtering transfer function than Gen 3 and Gen 4, so the comparison is more nuanced than indicated here. **Table 6: PCIe Maximum Allowable Clock Jitter** PCIe Generation Signaling Rate Reference Clock Max Jitter Allowed Notes :--- :--- :--- :--- 1 2.5 Gbps 86 ps PTP PTP is Peak to Peak 2 5.0 Gbps 3.1 ps RMS RMS is Root Mean Square 3 8.0 Gbps 1.0 ps RMS 4 16.0 Gbps 0.5 ps RMS 5 32.0 Gbps 0.15 ps RMS 6 64.0 Gbps 0.10 ps RMS Table 7 on the following page defines some PCIe Clock Buffer mode terminology. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 51/159](.picmg-com-hpc-carrier-design-guide-alt/slide-053.jpg) ## Slide 54 ![**Reference Schematics and Block Diagrams** **Table 7: PCIe Clock Buffer Modes** Mode Description Pros and Cons :--- :--- :--- Zero Delay A Clock Buffer PLL keeps the output clock copies in phase with the input clock.(br)(br)Also known as ZDB (Zero Delay Buffer) mode or as PLL mode.(br)(br)Some clock buffers have High Bandwidth and Low Bandwidth PLL modes. **Pro:** Zero delay makes it easier to meet the maximum skew of 12 ns between any two clocks, especially if the PCIe traces are very long, or if buffers are cascaded(br)(br)The PLL tends average out the jitter contribution from the source clock (see jitter discussion later in this document section, following Table 8)(br)(br)**Con:** PLLs buffers may have trouble with a Spread Spectrum source (see discussion following Table 8) Fan Out or PLL Bypass No PLL used. The output clock copies are an exact frequency copy of the input but are not in phase with the input. **Pro:** lower jitter from the buffer itself, in most cases (but the source clock jitter must be added to the that of the fan out buffer, per discussion following Table 8)(br)(br)Fan out buffers track a Spread-Spectrum clock source easily(br)(br)**Con:** may be harder to meet 12 ns max clock skew(br)(br)Although the fan out buffer jitter itself is low, the source clock jitter adds to the fan out buffer jitter **Timing Delay Discussion For Various PCIe Clock Buffer Scenarios** Regarding the max PCIe Reference Clock skew of 12 ns (or 10 ns for PCIe Gen 1) and the use of Fan Out (non – PLL) based clock buffers: a modern Fan Out buffer will have a worst case skew of well under 5 ns (several vendors claim 3 ns max, and at least one claims 1.5 ns max). Signals propagate at about 6 inches per ns, so a system with a 5 ns buffer delay and about 12 inches of PCB trace (2 ns delay) would have a worst case skew of 7 ns which is comfortably within the 12 ns Gen 2 through Gen 5 skew limit. Very long PCIe trace situations might need the Zero Delay Buffer – be aware of the possible issues with spread spectrum sources. However .. if there is a clock buffer on the COM-HPC Module in-between the Root complex PCIe reference clock and the clock(s) going out to the COM-HPC pins, then there will likely be an additional delay time that factors into the analysis in the previous paragraph. Check with your Module vendor on that. As: “what is the skew between the PCIe Reference Clock to the CPU or SOC Root Complex, and the COM-HPC PCIe Clock Reference pins” … it could be anywhere from 0 ns to 5 ns, depending on Module design details. Also: “what is the jitter contribution of a Module PCIe clock buffer” - if there is one. **PICMG® COM-HPC® Carrier Design Guide** **Rev. RC2.0d / Dec 7, 2021** **52/159**](.picmg-com-hpc-carrier-design-guide-alt/slide-054.jpg) ## Slide 55 ![Reference Schematics and Block Diagrams **PCIe Clock Buffer Options – Keep Them Open** A PCIe Clock Buffer IC usually has pin-strap(s) and / or SMBus options allowing the Clock Buffer operational modes to be set. It is best to keep access to these options open as sometimes issues can be resolved late in the design cycle (i.e. during regulatory and compliance testing) by changing the operational mode of the PCIe Clock Buffer. For example, Spread Spectrum PCIe reference clock operation may work with some but not all of the Clock Buffer modes. Additionally, some PCIe Clock Buffer devices have mechanisms (such as SMBus registers or OTP ordering options) to change parameters such as output clock slew rate, signal amplitude and / or the output termination values. **Sample PCIe Clock Buffer List** A sample collection of PCIe Clock Buffers is given in Table 8 below. Of course this is just a snapshot of what is available and appropriate at the time of this writing. Fan Out Mode jitter is additive (meaning the Module source jitter needs to be added together with the Fan Out buffer jitter). PLL Mode jitter is not additive, hence is marked as Total in the Table. The Module source jitter tends to get averaged out in the PLL. This is described in more detail on the page following Table 8. **Table 8: PCIe Clock Buffer Vendors and Part Numbers** Vendor Part Numbers Notes RMS Jitter (picoseconds) :--- :--- :--- :--- Diodes Inc. (Pericom) PI6CB18200 (dual, no internal term)(br)PI6CB18401 (quad, internal term)(br)PI6CB18601 (hex, internal term)(br)PI6CB18801 (octal, internal term)(br)A internal termination value for 100 ohm differential traces is implied in the data sheet but not explicitly stated. PCIe Gen 4 capable(br)1.8V supplies(br)OE# on each output(br)SMBus configuration option(br)Pin strap configuration option(br)Zero Delay Buffer modes(br)High BW PLL(br)Low BW PLL(br)PLL Bypass (aka Fan Out) Mode **PLL Mode (Total)**(br)Gen 1 5.0(br)Gen 2 0.3(br)Gen 3 0.1(br)Gen 4 0.05(br)(br)**Fan Out Mode**(br)Values not shown in public data sheet Diodes Inc. (Pericom) PI6CB33202 (dual, 85 ohm internal term)(br)PI6CB33402 (quad, 85 ohm internal term)(br)PI6CB33602 (hex, 85 ohm internal term)(br)PI6CB33802 (octal, 85 ohm internal term)(br)PI6CB33201 (dual, 100 ohm internal term)(br)PI6CB33401 (quad, 100 ohm internal term)(br)PI6CB33601 (hex, 100 ohm internal term)(br)PI6CB33801 (octal, 100 ohm internal term) PCIe Gen 5 capable(br)3.3V power supply(br)OE# on each output(br)SMBus configuration option(br)Pin strap configuration option(br)Zero Delay Buffer modes(br)High BW PLL(br)Low BW PLL(br)PLL Bypass (aka Fan Out) Mode **PLL Mode (Total)**(br)Gen 1 0.05(br)Gen 2 0.05(br)Gen 3 0.05(br)Gen 4 0.05(br)Gen 5 0.05 Diodes Inc. (Pericom) PI6CB332001A (20 outputs, 85 ohm internal term) PCIe Gen 5 capable(br)3.3V power supply(br)OE# for 8 outputs(br)SMBus, Side-Band interface support(br)20 HCSL outputs with On-chip Termination **Fan Out (Additive)**(br)Gen 1 0.03(br)Gen 2 0.03(br)Gen 3 0.03(br)Gen 4 0.03(br)Gen 5 0.12 Renesas (IDT) 9DBL0252 (dual, 85 ohm internal term)(br)9DBL0452 (quad, 85 ohm internal term)(br)9DBL0651 (hex, 85 ohm internal term)(br)9DBL0851 (octal, 85 ohm internal term)(br)9DBL0242 (dual, 100 ohm internal term)(br)9DBL0442 (quad, 100 ohm internal term)(br)9DBL0641 (hex, 100 ohm internal term)(br)9DBL0841 (octal, 100 ohm internal term) PCIe Gen 5 capable(br)3.3V power supplies(br)OE# on each output(br)SMBus configuration option(br)Pin strap configuration option(br)Zero Delay Buffer modes(br)High BW PLL(br)Low BW PLL(br)PLL Bypass (aka Fan Out) Mode **Fan Out (Additive)**(br)Gen 1 5.0(br)Gen 2 0.428(br)Gen 3 0.149(br)Gen 4 0.156(br)Gen 5 0.05(br)(br)**PLL Mode (Total)**(br)Gen 1 33(br)Gen 2 1.9(br)Gen 3 0.53(br)Gen 4 0.48(br)Gen 5 0.149 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 53/159](.picmg-com-hpc-carrier-design-guide-alt/slide-055.jpg) ## Slide 56 ![Reference Schematics and Block Diagrams Vendor Part Numbers Notes RMS Jitter (picoseconds) :--- :--- :--- :--- Renesas (IDT) 9DBL0255 (dual, 85 ohm internal term)(br)9DBL0455 (quad, 85 ohm internal term) Ultra low jitter(br)PCIe Gen 5 capable(br)100 ohm option with ext resistors(br)3.3V power supplies(br)OE# for each output Fan Out (Additive)(br)Gen 3 0.033(br)Gen 4 0.033(br)Gen 5 0.012 Renesas (IDT) 9ZXL0451E (quad, 85 ohm internal term)(br)9ZXL0651E (hex , 85 ohm internal term)(br)9ZXL0851E (octal, 85 ohm internal term)(br)9ZXL1251E (12 out, 85 ohm internal term) PCIe Gen 5 capable(br)3.3V power supplies(br)OE# on each output(br)SMBus configuration option(br)Zero Delay Buffer modes(br)High BW PLL(br)Low BW PLL(br)PLL Bypass (aka Fan Out) Mode Fan Out (Additive)(br)Gen 1 1.9(br)Gen 2 0.126(br)Gen 3 0.062(br)Gen 4 0.062(br)Gen 5 0.024(br)(br)Low BW PLL Mode (Total Jitter)(br)Gen 1 6.8(br)Gen 2 0.12(br)Gen 3 0.07(br)Gen 4 0.07(br)Gen 5 0.018 Skyworks (Silicon Labs) Si53204-A02 (quad, 85 ohm internal term)(br)Si53208-A02 (octal, 85 ohm internal term)(br)Si53212-A02 (12 out, 85 ohm internal term)(br)(br)Si53204-A01 (quad, 100 ohm internal term)(br)Si53208-A01 (octal, 100 ohm internal term)(br)Si53212-A01 (12 out, 100 ohm internal term)(br)(br)Silicon Labs has many other PCIe Clock Buffers, too numerous to list here. PCIe Gen 5 capable(br)1.8V power supplies(br)OE# on each output(br)SMBus configuration option(br)Fan Out Mode only (no PLL) Fan Out (Additive)(br)Gen 1 17 (PTP)(br)Gen 2 0.2(br)Gen 3 0.06(br)Gen 4 0.06(br)Gen 5 0.021 Texas Instruments LMK00334 (quad output, external term) PCIe Gen 4 capable(br)3.3V and 2.5V supplies(br)Single OE#(br)Fan Out Mode only Fan Out (Additive)(br)Gen 3 0.15(br)Gen 4 0.05 Texas Instruments LMK00338 (octal output, external term) PCIe Gen 3 capable(br)3.3V and 2.5V supplies(br)Single OE#(br)Fan Out Mode only Fan Out (Additive)(br)Gen 3 0.15 Texas Instruments CDCB2000 (20 outputs, 85 ohm int term) PCIe Gen 5 capable(br)3.3V supplies(br)OE# for 8 outputs(br)SMBus configuration option(br)Side Band Interface config option PLL Mode (Total)(br)Gen 1 5.0(br)Gen 2 0.2(br)Gen 3 0.15(br)Gen 4 0.08(br)Gen 5 0.03 Texas Instruments CDCDB800 (octal output, 85 or 100ohm software selectable term) PCIe Gen 5 capable(br)3.3V supplies(br)OE# on each output(br)SMBus configuration options(br)Fan Out Mode only(br)Propagation delay 0.5 ns typically(br)3 ns max Fan Out (Additive)(br)Gen 3 0.1(br)Gen 4 0.1(br)Gen 5 0.025 There may be more subtleties in the jitter numbers than is immediately apparent here. For example, some buffers allow the clock output slew rate to be adjusted, but the slew rate may in turn affect the jitter values. Check the vendor data sheets and make use of the vendor application engineers. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 54/159](.picmg-com-hpc-carrier-design-guide-alt/slide-056.jpg) ## Slide 57 ![Reference Schematics and Block Diagrams **Note on the Additive and Total Jitter values in Table 8 Above:** These values are taken from silicon vendor data sheets and are meant here as a rough guide. The jitter values for all operational modes (e.g. high PLL BW, low PLL BW etc) of the clock buffer devices may not be shown here. The values in the Table for Fan Out buffers are the “Maximum Additive Jitter” values listed in the vendor data sheets. For PLL buffers, the typical values are usually much lower, often less than half, of the maximum values. Jitter analysis can be tricky. Designers should consult the actual vendor data sheets and vendor application notes before making design decisions. **Note on Fan – Out Buffer Jitter vs. PLL or Zero Delay Buffers** If a Fan-Out mode PCIe clock buffer is used, then the clock jitter at the target is the square root of the sum of the squares of the COM-HPC Module clock source and of the Fan-Out buffer jitter, per the expression shown here: \$\$ \sqrt{J^2_{source} + J^2_{buffer}} \$\$ For PLL or Zero – Delay mode buffers, the clock jitter at the target is simply the jitter of the PLL buffer as listed in the vendor data sheet. The PLL buffer tends to average out the source clock jitter, unless it is extreme. In other words, with regard to the jitter values shown in Table 8 above, the Fan-Out buffer jitter values are not the full story, as the clock generator source jitter values need to be factored in per the equation above. The source clock generator jitter values need to be obtained from the Module vendor or the SOC vendor data sheets. **Note on the Internal Termination Impedances in Table 8 Above:** PCIe Clock Buffer internal output termination values suitable for both 85 ohm and 100 ohm differential traces are shown as being available in Table 8 above. The COM-HPC Base Specification recommends an 85 ohm differential impedance for the PCIe Reference Clocks coming off the Module, and hence into the Carrier Clock Buffer. Designers are free to choose either 85 ohms or 100 ohm differential impedances for their Clock Buffer output distribution. The phrasing “85 ohm internal term” in the Table above means that the device internal termination is appropriate for 85 ohm differential pairs, and similarly for “100 ohm internal term”. **Spread Spectrum Clock (SSC) Operation** SSC profiles for different PCIe generations are different, so a PLL based buffer with support for SSC needs to have an appropriate loop bandwidth for the PFD (Phase Frequency Detector) within the PLL. Therefore, it is advisable to check whether a PLL based buffer supports SSC for the PCIe generation it is to be used with. Some clock buffer vendors recommend against using a Spread Spectrum Clock source with their PLL mode parts and recommend the use of a Fan Out buffer instead. Check with your clock buffer vendor and allow for a PLL bypass mode (Fan Out Mode) option if possible. **COM-HPC Reference Clocks vs COM Express / Use of Clock Buffers** COM Express Rev 3.0 defines a single PCIe Reference Clock in it’s pinout. COM-HPC Rev 1.0 allows up to five PCIe Reference Clock pairs – there is one COM-HPC Module PCIe Reference Clock pair for each of the five COM-HPC PCIe groups, as outlined in Section 3.6.1 above. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 55/159](.picmg-com-hpc-carrier-design-guide-alt/slide-057.jpg) ## Slide 58 ![Reference Schematics and Block Diagrams 3.6.9. PCIe Redrivers and Retimers PCIe maximum trace length guidelines are given in Section 4.3.4 below and are presented along with loss budgets and more context in the COM-HPC Base Specification. However, PCIe Gen 3, 4, and 5 implementations may well need a redriver or retimer on the Carrier to make up for signal degradation. A redriver is an analog circuit that reshapes the PCIe signal using sophisticated analog techniques. A nearly closed PCIe signal eye can become a compliant open eye with a redriver. Redrivers may have a digital section in the form of I2C accessible registers or strap pins to set redriver parameters. A retimer is a digital and analog circuit that clocks in the PCIe signal using the PCIe 100 MHz reference clock and an on-chip PLL and reissues the reclocked signal in pristine form. Two popular vendors for PCIe redriver and retimer products are Diodes Inc. (formerly Pericom) (www.diodes.com) and Texas Instruments (www.ti.com). A retimer may possibly yield better results than a redriver, at a cost. Table 9: PCIe Redrivers and Retimers Vendor P/N Notes :--- :--- :--- Diodes Inc PI3EQX16904GL PCIe Gen 4 capable quad lane redriver (4 lanes in one direction) PI3EQX16908GL PCIe Gen 4 capable octal lane redriver (8 lanes in one direction) Texas Instruments DS160PR410 PCIe Gen 4 capable quad lane redriver (4 lanes in one direction) DS160PR810 PCIe Gen 4 capable octal lane redriver (8 lanes in one direction) DS160PT801 PCIe Gen 4 capable 16 lane retimer (8 lanes TX and 8 lanes RX) The items shown in Table 9 above represent only a small sample of parts available on the market. Texas Instruments, for example, has quite a few additional redriver and retimer parts not listed here. Some of the unlisted parts incorporate redriver or retimer functions along with analog multiplexer and cross-point switch functions. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 56/159](.picmg-com-hpc-carrier-design-guide-alt/slide-058.jpg) ## Slide 59 ![Reference Schematics and Block Diagrams **3.7. USB** **3.7.1. USB Terms and General Information** **Table 10: USB.org Branding Term Summary** USB.org Current Branding Nominal Bit Rates Notes USB.org Former Branding :--- :--- :--- :--- USB 2.0 480 Mbps (High Speed mode) Single half duplex DC coupled pair Also supports slower USB 1.1 and 1.0 legacy modes USB 2.0 USB 3.2 Gen 1 5 Gbps Dual simplex AC coupled transmit pair and a receive pair. Also requires a specific USB 2.0 link, on a separate set of conductors. USB 3.0 USB 3.1 Gen 1 USB 3.2 Gen 2 10 Gbps Dual simplex AC coupled transmit pair and a receive pair. Also requires a specific USB 2.0 link, on a separate set of conductors. USB 3.1 USB 3.1 Gen 2 USB 3.2 Gen 2x2 10 Gbps (per lane) 20 Gbps (two lanes) Two AC coupled transmit pairs and two receive pairs allowing 20 Gbps operation in each direction. Also requires a specific USB 2.0 link, on a separate set of conductors. USB4 Gen 2x2 10 Gbps (per lane) 20 Gbps (two lanes) Incorporates USB 3.2 Gen 2x2 and USB 2.0 features, along with additional features such as DisplayPort operation, USB Type-C (reversible) connector, and Thunderbolt 4 support. USB4 Gen 3x2 20 Gbps (per lane) 40 Gbps (two lanes) Features 20 Gbps bit rate per lane and uses 2 lanes TX and 2 lanes RX. Also includes USB 2.0 features, along with additional features such as DisplayPort operation, USB Type-C (reversible) connector, and Thunderbolt 4 support. USB SuperSpeed USB SuperSpeed+ 5 Gbps 10 or 20 Gbps The high speed interface used in USB 3.2 Gen 1, Gen 2, Gen 2x2 and USB4 is referred to as the SuperSpeed or SuperSpeed+ interface. A USB 3.2 Gen 1, Gen 2, Gen 2x2 or USB4 implementation require both SuperSpeed / SuperSpeed+ support and USB 2.0 support. The SuperSpeed / SuperSpeed+ interface is implemented on a separate set of pins from the USB 2.0 interface. However, every SuperSpeed implementation needs a specific companion USB 2.0 interface. Actual payload data rates are lower than what is implied by the “Nominal Bit Rates” in the chart above, due to the encoding methods used in the serialized data stream. The most common connector for USB host ports is the Type-A connector. Figure 25 below is a view looking into a USB 3 Type-A host receptacle (the Carrier connector is receptacle, the cable connector is the plug). Some points about this illustration: * A USB 2.0 Type-A connector only has pins 1 through 4 present. Pin-out details are in Table 11 below. * A USB 3 Type-A connector has 9 pins: * Pins 1 through 4 from the USB 2.0 definition are used for power, GND and a USB 2.0 data pair. * Pins 5 through 9 are used for SuperSpeed or SuperSpeed+ TX and RX pairs and a GND. * A USB 2.0 cable plug may be used with a USB 3 receptacle, but only the USB 2.0 link will function. * A USB 3 cable plug may be used with a USB 2.0 receptacle, but only the USB 2.0 link will function. * The USB 3 pins 5 through 9 are cleverly positioned so that they are invisible to the USB 2.0 plug. * USB 2.0 target devices are allowed to consume up to 500 mA at 5V on a Type-A connector. * USB 3 target devices are allowed to consume up to 900 mA at 5V on a Type-A connector. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 57/159](.picmg-com-hpc-carrier-design-guide-alt/slide-059.jpg) ## Slide 60 ![**Reference Schematics and Block Diagrams** **Figure 25: USB 3 Type-A Connector Receptacle – Looking Into the Receptacle** (Diagram showing a connector with pins numbered 1, 2, 3, 4 on the bottom row and 5, 6, 7, 8, 9 on the top row) **Table 11: USB Type-A Pin-Out** Pin Signal Signal Description Notes :--- :--- :--- :--- 1 VBUS 5V current limited USB target power 500mA (USB 2) or 900mA (USB 3) 2 D- USB 2.0 differential signal (-) 3 D+ USB 2.0 differential signal (+) 4 GND GND for USB 2.0 pair and power 5 SSRX- USB SuperSpeed RX(-) Not used / not present on USB 2.0 6 SSRX+ USB SuperSpeed RX(+) Not used / not present on USB 2.0 7 GND GND for SuperSpeed RX and TX cable drain wire Not used / not present on USB 2.0 8 SSTX- USB SuperSpeed TX(-) Not used / not present on USB 2.0 9 SSTX+ USB SuperSpeed TX(+) Not used / not present on USB 2.0 **Type-A Connector Electrical Distinctions** There are three general categories of USB Type-A connectors: * **USB 2.0** 480 Mbps USB 2.0 signaling (no USB 3) – 4 pin connector * **USB 3.2 Gen 1** 5 Gbps SuperSpeed signaling (along with USB 2.0) – 9 pin connector * **USB 3.2 Gen 2** 10 Gbps SuperSpeed+ signaling (along with USB 2.0) – 9 pin connector For USB 2.0 and USB 3.2 Gen 1 Type-A connectors, there are many vendors and styles (R/A, vertical, single, dual, quad combinations, combinations with other standards such as GbE etc). For USB 3.2 Gen 2 (10 Gbps pair signaling), there are not many Type-A connector parts available as of this writing. Amphenol FCI is a connector vendor that has several 10 Gbps capable Type-A connectors available. Amphenol FCI GSB4111312HR, for example is a single R/A version of such a part. Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5 through 3.7.11 below. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 58/159](.picmg-com-hpc-carrier-design-guide-alt/slide-060.jpg) ## Slide 61 ![Reference Schematics and Block Diagrams 3.7.2. USB 2.0 Type-A Example Figure 26: USB 2.0 Type-A Example Figure 26 above illustrates a typical USB 2.0 implementation on a Carrier. * The USB 2.0 data lines must be routed as differential pairs, in a no-stub fashion. * Components T9 and T10 are common-mode chokes that are an EMI mitigation measure. * Component D33 is a ESD protection diode array. Pins 1,3,4,6 may be exchanged if needed to provide the easiest no-stub routing. * Components U32 and U33 are USB power switches and current limiters. For USB 2.0, the current delivered to a USB target device is to be limited to about 500 mA. * The power switch / current limiter shown is from Richtek. There are many similar parts available from Texas Instruments, Micrel, Microchip and others. * The current limiter IC FAULT# pins are tied to the COM Module USB port 4 and 5 over-current input. There are 4 such inputs (for USB 0,1 and USB 2,3 and USB 4,5 and USB 6,7). * The 5V power traces involved between the USB power switches, through FB7 and FB8 and on to connector CN20 must be sized to carry the 1A current (and this should be increased to 1.5 or 2 A to allow for a safety factor). * The power switches are enabled by the COM-HPC RSMRST_OUT# signal. This signal going high indicates that the +5V_A power rail is stable. USB 2.0 Allocation Note The COM-HPC Client and Server pin-outs allow up to eight USB 2.0 ports each. Note however that the first four USB 2.0 ports (COM-HPC USB0+/- through USB3+/-) are paired with the corresponding USB Super-Speed ports (COM-HPC USB0_SSTX0+/- and USB0_SSRX0+/- through USB3_SSTX0+/- and USB3RX0+/-). A USB SuperSpeed port needs a specific companion USB 2.0 pair for certain setup functions. Thus ... if the Carrier needs one or more USB 2.0 only ports (no SuperSpeed) in addition to the four Super-Speed capable ports, the above pairings need to be considered. COM-HPC USB4+/- through USB7+/- are USB 2.0 only ports. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 59/159](.picmg-com-hpc-carrier-design-guide-alt/slide-061.jpg) ## Slide 62 ![Reference Schematics and Block Diagrams 3.7.3. USB 3.2 Gen 1 and Gen 2 Type-A A USB 3.2 Gen 1 example on a Type-A connector is given in the COM Express Carrier Design Guide Rev 2.0 Section 2.9. At the time that the COMe Design Guide was written, USB 3.2 Gen 1 (single SuperSpeed TX pair and single RX pair, 5 Gbps signaling, plus a USB 2.0 pair) was referred to as USB 3.0. A USB 3.2 Gen 2 Type-A connector implementation (single SuperSpeed+ TX pair and single RX pair, 10 Mbps signaling) is basically the same as a Gen 1 implementation, except that the components involved may need an upgrade for the 10 Gbps signaling: lower capacitance ESD diodes, different common mode choke choices and a connector receptacle appropriate for 10 Gbps signaling. An additional consideration is that there may be a greater need for a redriver. Most USB 3.2 Gen 2 implementations use a Type-C connector rather than Type-A. Type-C implementations are covered in Sections 3.7.5 through 3.7.11 below. No USB 3 redriver is shown in the COM Express Carrier Design Guide example. If the traces from the COM-HPC Module connector to the Type-A host receptacle are more than a few inches, then a Carrier redriver may be advisable. 3.7.4. USB 3 Redrivers Table 12: USB 3 Redrivers Vendor P/N Notes --- --- --- Diodes Inc PI3EQX7841 USB 3.1 Gen 1 capable single port redriver (1 TX pair and 1 RX pair) 5 Gbps per pair PI3EQX1004E USB 3.1 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs ) 10 Gbps per pair Texas Instruments TUSB522P USB 3.2 Gen 1 capable single port redriver (1 TX pair and 1 RX pair) 5 Gbps per pair TUSB1002A USB 3.2 Gen 2 capable single port redriver (1 TX pair and 1 RX pair) 10 Gbps per pair TUSB1004 USB 3.2 Gen 2 capable dual port redriver (2 TX pairs and 2 RX pairs ) 10 Gbps per pair May be used to support two USB 3.2 Gen 2 ports The items shown in Table 12 above represent only a small sample of such parts available on the market. USB Type-C Port Multiplexers, which may include redriver and retimer capabilities, are listed in Table 14 below. USB Type-C implementations are covered in Sections 3.7.5 through 3.7.10 below, and USB4 in Section 3.7.11. USB Hubs – May Serve as Retimers USB 2 and USB 3 hubs are plentiful and may be considered as a form of a USB retimer: they clock the USB 2 and 3 signals in, process them and clock them out in fresh form. Of course the downstream bandwidth is shared, if more than one downstream hub port is used. Microchip Technologies (www.microchip.com) seems to be the dominant USB hub supplier and has dozens of offerings. Granted, there may be some software subtleties concerning the use of USB hubs versus true USB retimers (a true retimer should be invisible to software apart from possible setup; a hub has to be enumerated by the operating system, etc.). PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 60/159](.picmg-com-hpc-carrier-design-guide-alt/slide-062.jpg) ## Slide 63 ![Reference Schematics and Block Diagrams **3.7.5. USB Type-C Overview** USB Type-C refers to a small form factor reversible connector definition (reversible cable plug, no polarity, can be inserted with either orientation), and to the USB and other data and negotiated power delivery formats that it supports. Some highlights include: * **Polarity free operation** * Cable plug can be used in either orientation * **USB 2.0** ( 480 Mbps signaling) * **USB 3.2 Gen 1 x1 and Gen 2 x 1** ( 5 Gbps, 10 Gbps signaling) (single lane) * **USB 3.2 Gen 1 x2 and Gen 2 x 2** ( 10 Gbps, 20 Gbps signaling) (2 lanes) * **“Alternate Modes” including** * DisplayPort (2 lanes) + USB 3.2 * DisplayPort (4 lanes) * HDMI * Intel Thunderbolt * Other vendor specific Alternate Modes * **USB4**, described Section 3.7.11 below. * **USB Power Delivery (PD) protocol and implementation** * Allows negotiated power delivery, from 5V up to 20V and up to 100W. * **Active cable support** (electronics within the USB cable assembly) For an excellent explanation of USB Type-C features, capabilities and details on how they work, see the Microchip Technologies Application Note **AN1953 Introduction to USB Type-C**. Much of the information in this section has been adapted from this note. A typical Type-C receptacle is shown in Figure 27 below, at the left. A typical cable plug is shown at the right. The connector is fairly small, with an overall width less than 9mm and body height just under 3mm. These dimensions are similar but slightly larger than the Apple Computer “Lightening” connectors that are popular on consumer cell phones. The USB Type-C connector system has more capabilities than the “Lightening” system. The receptacle and corresponding cable plugs are mechanically symmetrical and the cable plug can be used in either orientation. The connector pin-out, presented on the following page, is almost completely symmetrical. There are some locking versions of the USB Type-C connector available. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 61/159](.picmg-com-hpc-carrier-design-guide-alt/slide-063.jpg) ## Slide 64 ![**Header:** Reference Schematics and Block Diagrams **Figure 27:** USB Type-C Receptacle and Plug Images * *Visuals:* Images of a USB Type-C receptacle (metal housing) and a USB Type-C plug cable (black cable). **Figure 28:** USB Type-C Receptacle Pin-Out – Looking Into Carrier Receptacle * *Diagram:* A horizontal oval representing the connector with two rows of colored blocks indicating pin signals. * **Top Row Labels (Left to Right):** A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12. * **Top Row Signals:** GND, TX1+, TX1-, VBUS, CC1, D+, D-, SBU1, VBUS, RX2-, RX2+, GND. * **Bottom Row Labels (Right to Left):** B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1. * **Bottom Row Signals:** GND, RX1+, RX1-, VBUS, SBU2, D-, D+, CC2, VBUS, TX2-, TX2+, GND. **Note:** 'Note that the Type-C receptacle connector pin-out is mostly symmetrical with respect to flipping the plug connector. If the connector plug is inserted 'right side up' (plug A1 to receptacle A1 etc.), all plug and receptacle signals match. If the connector plug is inserted 'upside down' (plug A1 to receptacle B1 etc) then a few things must be sorted out by Carrier hardware, as explained on the following pages.' **Table 13:** USB Type-C Connector Pin-out * **Left Column (A Pins):** * A1 GND * A2 TX1+ SuperSpeed TX1+ * A3 TX1- SuperSpeed TX1- * A4 VBUS Bus Power to Peripheral USB device * A5 CC1 Configuration Channel 1 or VCONN * A6 D+ USB 2.0 D+ * A7 D- USB 2.0 D- * A8 SBU1 Side Band Use 1 * A9 VBUS Bus Power to Peripheral USB device * A10 RX2- SuperSpeed RX2- * A11 RX2+ SuperSpeed RX2+ * A12 GND * **Right Column (B Pins):** * B12 GND * B11 RX1+ SuperSpeed RX1+ * B10 RX1- SuperSpeed RX1- * B9 VBUS Bus Power to Peripheral USB device * B8 SBU2 Side Band Use 2 * B7 D- USB 2.0 D- * B6 D+ USB 2.0 D+ * B5 CC2 Configuration Channel 2 or VCONN * B4 VBUS Bus Power to Peripheral USB device * B3 RX1- SuperSpeed TX2- * B2 RX1+ SuperSpeed TX2+ * B1 GND **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 62/159](.picmg-com-hpc-carrier-design-guide-alt/slide-064.jpg) ## Slide 65 ![Reference Schematics and Block Diagrams For the yellow shaded cells in the Table above, the ‘A’ and ‘B’ signals have complete symmetry and nothing at all needs to be done to sort them out if the cable plug is “upside down”. The non-shaded signals need some help in the “upside down” case – to get the plug signals to the correct Carrier destinations. Multiplexers are involved, and, to reduce stubs and preserve signal integrity, the “right side up” signals are usually routed through multiplexers along with the “upside down”. signals. **USB 2.0 D+ and D-** The USB 2.0 D+ and D- differential pair data lines are arranged in a symmetrical block in the USB Type-C pin-out definition. This arrangement has the result that no signal multiplexing is needed for “right side up” and “upside down” cable plug insertions. However, as a consequence of this arrangement, there are some short signal stubs. Since the USB 2.0 signaling rate is relatively low (480 Mbps), this is not a problem. **VBUS** VBUS is the power source provided by the host system (the COM-HPC Carrier in this case) to the attached downstream port. It can be the traditional fixed 5V current limited supply per USB 2.0 or USB 3.x, or it can be a higher voltage supply, up to 20V, and up to 100W, as negotiated by implementations following the USB Type-C Power Delivery Specification. The Power Delivery (PD) negotiation and implementation capability is optional, but necessary for higher powered peripherals. The PD negotiation happens over one of the two CC lines. Note that there are four VBUS pins and four GND pins. All eight pins should be used, to handle the possibly high power and current levels. **VCONN** VCONN is 5V nominal 1W max power source for active USB cables. Active cables have internal electronics that boost the signals carried, allowing longer cable assembles. The electronics in an Active cable may take their power from VCONN or VBUS. VCONN is routed to the receptacle CC2 pin if the plug is “right side up” or to the receptacle CC1 pin if the plug is “upside down”. **CC1 and CC2 Configuration Channel Signals** The CC1 and CC2 signals serve several purposes in USB Type-C implementations: * The CC1 and CC2 pins are used by the host system to identify whether the cable plug is inserted “right side up” or “upside down”, through an analog detection process, relying on certain resistor values on the host side and on the downstream port side. * The CC1 and CC2 signals are also used to identify the basic host power delivery requirements to the downstream peripheral. A resistor scheme and analog measurements are used to identify 5V 500 mA. 1.5A and 3A possibilities. * The receptacle CC1 pin (if the plug connector is “rightside up”) or the receptacle CC2 pin (plug connector is “upside down”) may be used to negotiate the USB Type-C Power Delivery using a one – wire protocol defined in the USB Power Delivery Specification. This is optional but necessary if the peripheral needs a VBUS voltage over 5V. * VCONN power is distributed to the “unused” CC pin (CC2 for plug “rightside up” and CC1 for plug “upside down”). * The Microchip application note AN1953 explains the CC1 and CC2 operational details very well. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 63/159](.picmg-com-hpc-carrier-design-guide-alt/slide-065.jpg) ## Slide 66 ![**Header:** Reference Schematics and Block Diagrams **SuperSpeed TX1+, TX1-, RX1+, RX1-** * If the cable plug is “rightside up” then these pins are used for the USB 3.2 Gen 1 and Gen 2 single lane SuperSpeed signals, or for the first lane of a two lane implementation. * If the cable plug is “upside down” then the cable TX1+, TX1-, RX1+ and RX1- signals land on the receptacle TX2+, TX2-, RX2+ and RX2- pins. In this case, Carrier hardware has to route these signals to the proper TX1+, TX1-, RX1+ and RX1- destinations on the Carrier board. * In practice, a Carrier Board multiplexer is used to route the receptacle TX1 and RX1 pairs to the proper Carrier destination, as the signals are high speed and stubs must be avoided. * In some cases, the TX1 and RX1 high speed pairs are used for “Alternate Mode” purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol. **SuperSpeed TX2+, TX2-, RX2+, RX2-** * If the cable plug is “rightside up” then these pins may be used for the second lane set of a USB 3.2 Gen 1x2 or Gen 2x2 implementation. * If the cable plug is “upside down” then the cable TX2+. TX2-, RX2+ and RX2- signals land on the receptacle TX1+, TX1-, RX1+ and RX1- pins. In this case, Carrier hardware has to route these signals to the proper TX2+. TX2-, RX2+ and RX2- destinations on the Carrier board. * In practice, a Carrier Board multiplexer is used to route the receptacle TX2 and RX2 pairs to the proper Carrier destination. * In some cases, the TX2 and RX2 high speed pairs are used for “Alternate Mode” purposes. Alternate Mode use is negotiated as part of the USB Power Delivery protocol. * A common Alternate Mode usage of these pairs is for a DisplayPort implementation. **SBU1 and SBU2** * SBU is an acronym for Side Band Use. * These are optional signals, not needed for USB only implementations. * For the DisplayPort Alternate Mode, these signals are used for the DisplayPort Aux Channel pair. * For an HDMI Port Alternate Mode, these signals are used for the HDMI I2C channel. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 64/159](.picmg-com-hpc-carrier-design-guide-alt/slide-066.jpg) ## Slide 67 ![**Reference Schematics and Block Diagrams** **3.7.6. USB Type-C Port Multiplexers** Selecting a USB Type-C Port Multiplexer can be tricky. It is important to understand what it does, and does not do, and what software support is available. Tables 14 lays out some of the possibilities. It is best to work with the silicon vendor and Module vendor FAEs on the details. It’s pretty difficult, but not impossible, to cover all the possible USB Type-C modes in a single design. All the USB Type-C Port Multiplexers listed in this Table incorporate redriver or retimer functions, reducing part count. **Table 14: USB Type-C Port Multiplexers – Possible Modes** Ref Mode Notes Possible Part(s) Part Notes :--- :--- :--- :--- :--- 1 USB 3.2 Gen 1x1 5 Gbps signaling single SuperSpeed TX pair and single RX pair used TUSB542 TUSB1042 TUSB1104 TUSB1142 TUSB1146 Intel JHL8040R TUSB542 is 5 Gbps Others are 10 Gbps capable 2 USB 3.2 Gen 2x1 10 Gbps signaling single SuperSpeed+ TX pair and single RX pair used TUSB1042 TUSB1044 TUSB1046 TUSB1104 TUSB1142 TUSB1146 Intel JHL8040R 10 Gbps capable parts TUSB1104 is pre release 3 USB 3.2 Gen 1x2 5 Gbps signaling per pair dual SuperSpeed TX pairs and dual RX pairs used 10 Gbps net TX speed, 10 Gbps net RX speed TUSB1104 TUSB1104 is pre release 4 USB 3.2 Gen 2x2 10 Gbps signaling per pair dual SuperSpeed+ TX pairs and dual RX pairs used 20 Gbps net TX speed, 20 Gbps net RX speed TUSB1104 TUSB1104 is pre release 5 DisplayPort Alternate Mode 2 DP lanes + USB 3 Separate DP Source USB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1 Two DP pairs on TX2 / RX2 (RX2 used as DP TX pair) DP sourced externally, from GPU pins TUSB546A-DCI TUSB1044 TUSB1046 TUSB1046A-DCI TUSB1146 TUSB546A-DCI is 5 Gbps Others are 10 Gbps capable 6 DisplayPort Alternate Mode 4 DP lanes Separate DP Source No USB 3 at all (USB 2 remains) Four DisplayPort pairs on TX1,RX1,TX2,RX2 DP sourced externally, from GPU pins TUSB546A-DCI TUSB1046A-DCI TUSB1046 TUSB1146 TUSB546A-DCI is 5 Gbps Others are 10 Gbps capable 7 DisplayPort Alternate Mode 2 DP lanes + USB 3 USB 3.2 Gen 1x1 or Gen 2x1 on TX1 / RX1 Two DP pairs on TX2 / RX2 (RX2 used as DP TX pair) DP multiplexed with USB 3 within chip-set TUSB544 TUSB1044 Intel JHL8040R 8 DisplayPort Alternate Mode 4 DP lanes No USB 3 at all (USB 2 remains) Four DisplayPort pairs on TX1,RX1,TX2,RX2 DP multiplexed with USB 3 within chip-set TUSB544 TUSB1044 Intel JHL8040R 9 HDMI Alternate Modes Similar to DP Alternate Modes TUSB546 10 USB4: 20 Gbps only All USB3 modes USB4: 20 Gbps signaling using 2 lanes DP Alternate Modes Intel JHL8040R 11 Thunderbolt Modes All USB 3 modes USB4: 20 Gbps signaling, 40 Gbps using 2 lanes DP Alternate Modes PCIe Alternate Mode Intel JHL8040R PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 65/159](.picmg-com-hpc-carrier-design-guide-alt/slide-067.jpg) ## Slide 68 ![**Reference Schematics and Block Diagrams** **Notes on Table 14:** * All the “TUSB” prefixed parts listed above are from Texas Instruments * The TUSB1104 part is, as of this writing, a pre release TI part, referenced with permission, and optimized for USB 3.2 Gen 2x2 Type-C use. * The Intel JHL8040R is a USB4 retimer part, formerly known as the “Burnside Bridge”. **3.7.7. USB Type-C Power Delivery Controllers** The USB Type-C specification is an ambitious specification with many features. For Power Delivery, the specification allows up to 100W of power, over a voltage range from 5V to 20V, to be delivered either out of the device in question or accepted into the device. For example, a laptop computer might want to provide power to an external display or printer in some situations. In a different situation, the same laptop may want to accept power from an external charger for battery recharging. The Power Delivery options are negotiated over the USB Type-C CC lines. If there is no negotiation, than a simple old style USB 3.0 or USB 2.0 Type-A power delivery out of the COM-HPC host is assumed Sections 3.7.10 and 3.7.11 below, and more specifically in Figures 34 and 40 below show a USB Type-C Power Delivery solution that allows 15W max power at 5V, out of the COM-HPC carrier to an external device. The Texas Instruments TPS65994 Power Delivery controller is shown. This is actually a dual part that could support two USB Type-C ports. Only one port is used in the Section 3.7.10 USB 3.2 Gen 2x2 example, and similarly for the Section 3.7.11 USB4 port example. Higher power levels (up to 100W, voltages over 5V to 20V range), either out or into the COM-HPC Carrier are possible with other PD controllers. For example, the Texas Instruments TPS65987D device allows up to 100W power delivery, over a 5V to 20V range, out of or into the system, using integrated power FETs. The voltage level, the current level and the current direction are negotiated over the CC lines before power is applied to, or accepted from, the USB Type-C VBUS. The TPS65994 device used in the USB 3,2 Gen 2x2 and USB4 design examples below has a provision, using external power FETs, for up to 100W to come in to the design, but this capability is not used in these examples. There are many additional USB Type-C Power Delivery controllers available from Cypress Semiconductor (now part of Infineon), Microchip Technologies, NXP, On Semiconductor, Texas Instruments and others. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 66/159](.picmg-com-hpc-carrier-design-guide-alt/slide-068.jpg) ## Slide 69 ![Reference Schematics and Block Diagrams 3.7.8. USB Type-C Port Protection Components It is important to protect USB Type-C port pins against accidental exposure to 20V VBUS contact, and against ESD events. The USB 3.2 Gen 2x2 and USB4 schematic examples (Sections 3.7.10 and 3.7.11 below) illustrate this. The examples here use a Texas Instruments TPD6S300 USB Type-C Port Protector to protect the Type-C CC lines (2 pins), SBU lines (2 pins) and the USB 2.0 lines (4 pins, in the Type-C implementation). This is shown in Figures 35 and 41 below. Note: since these examples were created, Texas Instruments has upgraded their Type-C Port Protector to the TPD6S300A and that should be used for new designs. The high speed data pairs (2 TX pairs and 2 RX pairs, for USB, DP, HDMI etc) are protected separately in these schematic examples, using discrete low capacitance ESD diodes. This is shown in Figures 32 and 39 below. There are many other possible USB Type-C Port Protection components, from Texas Instruments, Microchip Technologies, On Semiconductor, NXP and others. If the COM-HPC is implementing a battery powered option, then there are battery charging and dead battery concerns to consider. Refer to the Texas Instruments and Microchip Technologies data sheets and application notes for more technical information on this. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 67/159](.picmg-com-hpc-carrier-design-guide-alt/slide-069.jpg) ## Slide 70 ![This document page, numbered 68/159, features a header at the top right reading 'Reference Schematics and Block Diagrams.' The main body begins with the bolded section title: '3.7.9. USB 3.2 Gen 2x1 Type-C Basic Implementation.' The text below this title consists of six paragraphs: 1. 'A basic USB Type-C implementation that supports USB 2.0, USB 3.2 Gen 1 x1 and USB 3.2 Gen 2x1 is straightforward. An example is presented in Figure 29 on the following page. Although this example is in block diagram format and does not include the many passive components needed for a complete design, it only requires two small ICs. This Type-C example is hardly any more complex than a traditional USB 3 Type A , design, especially if a redriver is included in the Type A design.' 2. 'The example in Figure 29 includes a USB Type-C port multiplexer and USB 3 redriver in a single IC package that can be placed close to the Type-C connector receptacle to best launch the signal over the USB cable. Note that TX line coupling capacitors are needed on the redriver output pins.' 3. 'The example also includes a USB Type-C Power Source controller that performs cable detection, provides cable orientation information, provides VBUS power and VCONN power and current limiting for both, along with fault detection. This part does not implement the full USB Power Delivery protocol – this is not necessary here as the VBUS power is limited to traditional USB 3 values of 5V nominal, 1A operational and 1.5A fault current.' 4. 'An implementation that allows the full USB Type-C Power Delivery gamut (5V to 20V, up to 100W) requires a more complex Power Source or Delivery part, that implements the one-wire negotiation on the CC1 or CC2 lines (depending on cable plug insertion polarity).' 5. 'There are many useful parts for USB Type-C support available from Texas Instruments, Microchip Technol- ogy, Diodes Inc. and other vendors.' 6. 'Figure 29 below uses the COM-HPC USB0 port as an example (for USB 2.0 and USB 3.2 signals). Any of the first four COM-HPC USB ports (USB0 through USB3) may be used. Remember that COM-HPC USB 2 and USB 3 ports are paired together. See the notes on this in the COM-HPC Base Specification V1.0 Table 15.' The footer displays 'PICMG® COM-HPC® Carrier Design Guide' on the left and 'Rev. RC2.0d / Dec 7, 2021' with the page number '68/159' on the right.](.picmg-com-hpc-carrier-design-guide-alt/slide-070.jpg) ## Slide 71 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 29: USB Type-C Basic Implementation: USB 3.2 Gen 1 and Gen 2 **Diagram Content:** * **Top Left Inputs:** COM, USB0+, COM, USB0- * **Center Block (Top):** * **Text:** USB Type-C Mux and Redriver, USB 3.1 Gen 2 Capable (10 Gbps), Texas Inst TUSB1142 or TUSB1042 * **Sub-block 1:** TX PAIR MUX * **Inputs:** COM, USB0_SSTX0+, COM, USB0_SSTX0- * **Outputs:** TX1+, TX1-, TX2+, TX2- * **Sub-block 2:** RX PAIR MUX * **Outputs:** RX1+, RX1-, RX2+, RX2- * **Inputs:** COM, USB0_SSRX0+, COM, USB0_SSRX0- * **Control Signals:** FLIP, CTL0 * **Right Vertical Block:** USB Type-C Receptacle * **Bottom Block:** * **Connections/Labels:** 5V BUS POWER, IN, OUT, VBUS, CC1, CC or VCONN, CC2, CC or VCONN, POL#, SINK#, FAULT#, COM, USB01_OC# * **Text:** Texas Inst TPS25820, USB Type-C Power Source Controller **Footer:** * PICMG® COM-HPC® Carrier Design Guide * Rev. RC2.0d / Dec 7, 2021 * 69/159](.picmg-com-hpc-carrier-design-guide-alt/slide-071.jpg) ## Slide 72 ![**Header:** Reference Schematics and Block Diagrams **Section 3.7.10:** USB 3.2 Gen 2x2 Type-C Example Implementation **Text Content:** A detailed schematic example of a USB 3.2 Gen 2x2 implementation (meaning two USB SuperSpeed TX pairs and two RX pairs, each pair capable of 10 Gbps signaling) is shown in Figures 30 through 35 below. The net TX signaling over two pairs is 20 Gbps, and the net RX signaling over two pairs is 20 Gbps This is delivered over a Type-C reversible connector. The Type-C port multiplexer shown in Figure 31 below, Texas Instruments (TI) TUSB1104, is the optimal part for this application but it is a non-released part as of this writing. It is shown here with permission from TI. The TI TUSB1044 is a similar part that is released and may be used for context but may not be totally suitable here. A single TX and RX SuperSpeed pair Type-A connector option is implied by some resistor stuffing options in Figure 30 below (R5W6 through R5W9, not populated) but the Type-A connector details are not shown in this Figure set. The Type-A implementation is discussed in Section 3.7.3 above. This example includes a USB Power Delivery controller, Texas Instruments TPS65994, in Figure 34 below. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7 above more some discussion on Power Delivery controllers. **Figure 30:** USB 3.2 Gen 2x2 Type-C (1 of 6): Option Resistors for Type-C or Type-A **Schematic Description:** The diagram shows connections labeled 'FROM COM-HPC CONN' branching into resistor networks (labeled 'TRI-PAD OPTION') for USB0 and USB2 signals. These connect to 'OUT' and 'IN' blocks. Specific nets include USB0_SSTX0, USB0_SSRX0, and USB2_P0_TCP. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 70/159](.picmg-com-hpc-carrier-design-guide-alt/slide-072.jpg) ## Slide 73 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 31: USB 3.2 Gen 2x2 Type-C (2 of 6): Port Multiplexer and Redriver **Schematic Text and Components:** * **Top Left:** +V3P3_A, R4W9 (10K 5% EMPTY 0.0625W 0402), R5W19 (10K 5% EMPTY 0402), EJ5W2 TUSB1104 * **Top Right:** +V3P3_A, CSW9 (10uF 10V 25V X7R 0402), CSW10 (0.1uF 10V 25V X7R 0402), CW14 (0.1uF 10V 25V X7R 0402), CW4 (0.1uF 10V 25V X7R 0402), CW47 (0.1uF 10V 25V X7R 0402), GND * **Central IC (TUSB1104):** * **Pins:** 1, 2, 3, 4, 5, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41. * **Pin Labels:** EN, SLP_SD_N, VCC, SBTX2_DP, SBTX2_DN, SRRX2_DP, SRRX2_DN, SBTX1_DP, SBTX1_DN, SRRX1_DP, SRRX1_DN, SBTX0_DP, SBTX0_DN, SRRX0_DP, SRRX0_DN, TESTOUT2, TESTOUT1, TEST1, MODE, FLIP/SCL, AECN/SDA, CEQ1, VIO_SEL, AEGCFG, TP_TP0, NC. * **Signal Labels:** USB0_RVR_EN, USB0_RVR_SLPS, USB0_SBTX1_DP, USB0_SBTX1_DN, USB0_SRRX1_DP, USB0_SRRX1_DN, USB0_SBTX0_DP, USB0_SBTX0_DN, USB0_SRRX0_DP, USB0_SRRX0_DN, USB0_RVR_A1_SBD1, USB0_RVR_A0_SBD0, USB0_RVR_MODE, USB0_RVR_FLIP, USB0_RVR_SDA, USB0_RVR_AEQENC, USB0_RVR_CEQ1, USB0_RVR_VIO_SEL, USB0_RVR_AEGCFG. * **Resistors/Caps:** R4W54, R5W12, R5W13, R5W14, R5W10, R5W11, C4W1, C4W2, R4W28, R4W32, R4W34. * **Bottom Left Resistor Array:** +V3P3_A, R5W27 (1K 5% EMPTY 0402), R5J2 (1K 5% EMPTY 0402), R4W22 (1K 5% EMPTY 0402), R4W59 (1K 5% EMPTY 0402), R5J1 (1K 5% EMPTY 0402), R5W15 (1K 5% EMPTY 0402), R4W5 (1K 5% EMPTY 0402), R5W28 (1K 5% EMPTY 0402), R5J5 (1K 5% RES 0402), R4W20 (1K 5% EMPTY 0402), R4W61 (1K 5% EMPTY 0402), R5J4 (1K 5% EMPTY 0402), R5W16 (1K 5% EMPTY 0402), R4W62 (1K 5% EMPTY 0402), R5W21 (1K 5% EMPTY 0402), GND. * **Bottom Center Resistor:** +V3P3_A, R4W24 (1K 5% EMPTY 0402), R4W36 (1K 5% EMPTY 0402), R4W40 (1K 5% EMPTY 0402), GND. * **CAD NOTE:** 'PLACE RESISTORS THAT CONNECT TO PIN 21/22 CLOSE TO IC' **Right Side Text:** * **PIN STRAP** * MODE = F (I2C MODE) * VIO_SEL = F (3.3V I2C) * AI = F * I2C ADR = 0x10 (7BIT) * AEQENC = SDA * AEGCFG = CTRL BY FULLAEQ_UPPER_EQ_REGISTER * **Table 8-1. 4-Level Control Pin Settings** * **LEVEL:** 0, R, F, 1 * **SETTINGS:** * Option 1: Tie 1-kΩ 5% to GND. Option 2: Tie directly to GND. * Tie 20-kΩ 5% to GND. * Float (leave pin open) * Option 1: Tie 1-kΩ 5% to VCC. Option 2: Tie directly to VCC. **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 71/159](.picmg-com-hpc-carrier-design-guide-alt/slide-073.jpg) ## Slide 74 ![**Header:** Reference Schematics and Block Diagrams **Figure Title:** Figure 32: USB 3.2 Gen 2x2 Type-C (3 of 6): EMI Mitigation and ESD Protection **Left Column Schematic Content:** * **Top Section:** * IN USB0 SSTX0_RX0- connects to R4Y6 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * Below R4Y6 is L4Y3 (Text: 1 2, J16541-001, CHOK, 100mA, SM_A 90 30%). * OUT USB0 SSTX0_L- * IN USB0 SSTX0_RX0+ connects to R4Y5 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * OUT USB0 SSTX0_L+ * **Middle Section:** * IN USB0 SSTX1_RX0+ connects to R4Y12 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * Below R4Y12 is L4Y5 (Text: 1 2, J16541-001, CHOK, 100mA, SM_A 90 30%). * OUT USB0 SSTX1_L+ * IN USB0 SSTX1_RX0- connects to R4Y11 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * OUT USB0 SSTX1_L- * **Bottom Section:** * OUT USB0 SSBX0_RX0- connects to R4Y18 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * Below R4Y18 is L4Y7 (Text: 1 2, J16541-001, CHOK, 100mA, SM_A 90 30%). * IN USB0 SSBX0_L- * OUT USB0 SSBX0_RX0+ connects to R4Y21 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * IN USB0 SSBX0_L+ * OUT USB0 SSBX1_RX0+ connects to R4Y8 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * Below R4Y8 is L4Y4 (Text: 1 2, J16541-001, CHOK, 100mA, SM_A 90 30%). * IN USB0 SSBX1_L+ * OUT USB0 SSBX1_RX0- connects to R4Y7 (Text: 1 2, 0.20W EMPTY, 0.05W 0 0%). * IN USB0 SSBX1_L- **Right Column Schematic Content:** * **Top ESD Protection Section:** * Lines: USB0 SSTX1_L-, USB0 SSTX1_L+, USB0 SSTX0_L+ * Components: CR4Y13, CR4Y12, CR4Y8, CR4Y7 * Text under diodes: 2, 20KV, ESD, SM * Text next to CR4Y7: K74755-001, PESIOXV321MSF * Connection to GND * **Middle ESD Protection Section:** * CAD NOTE: PLACE ESD CLOSE TO CONNECTOR * Lines: USB0 SSBX0_L+, USB0 SSBX0_L-, USB0 SSBX1_L- * Components: CR4Y6, CR4Y5, CR4Y14, CR4Y16 * Text under diodes: 2, 20KV, ESD, SM * Text next to CR4Y16: K74755-001, PESIOXV321MSF * Connection to GND * **Bottom Auxiliary/USB2 Section:** * Lines: USB0 AUX-, USB0 AUX+ * Components: C4V10 A36096-112, 0.1UF 10%, 25V EMPTY. C4V9 A36096-112, 0.1UF 10%, 25V EMPTY. * DESIGN NOTE: USB0 RECEIVER NOT SUPPORT DP MODE, AUX PATH DEFAULT DISCONNECTED * Resistor R4V28 (Text: A93549-027, 100K, 0.0625W, EMPTY, 0402) connected to +V3P3. * Resistor R4V27 (Text: A93549-027, 100K, 0.0625W, EMPTY, 0402) connected to GND. * Bottom Block: * R6K6 (Text: 1 2, 0402, EMPTY, 0.0625W, 0, 0%) * L6K3 (Text: 3, 752402-015, 9u, 25%, 0.4A, IND) * R6K5 (Text: 1 2, 0402, EMPTY, 0.0625W, 0, 0%) * Text: A93549-001 * Lines: USB2_P0_TPC-, USB2_P0_TPC+ **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 72/159](.picmg-com-hpc-carrier-design-guide-alt/slide-074.jpg) ## Slide 75 ![Reference Schematics and Block Diagrams Figure 33: USB 3.2 Gen 2x2 Type-C (4 of 6): Port Port Mux / Redriver Coupling Capacitors IN USB0_SSTX0 L- C4Y6 1 2 x5R 220NF USB0_SSTX0 C- OUT 0201 10% 25V IN USB0_SSTX0 L+ C4Y5 1 2 x5R 220NF USB0_SSTX0 C+ OUT 0201 10% 25V IN USB0_SSTX1 L- C4Y9 1 2 x5R 220NF USB0_SSTX1 C- OUT 0201 10% 25V IN USB0_SSTX1 L+ C4Y10 1 2 x5R 220NF J95198-001 USB0_SSTX1 C+ OUT 0201 10% 25V RC SHORT PROTECTION OUT USB0_SSRX0 L- C4Y17 J96611-001 330NF 10% 25V X5R 1 2 0201 USB0_SSRX0 C- IN OUT USB0_SSRX0 L+ C4Y19 J96611-001 330NF 10% 25V X5R 1 2 0201 USB0_SSRX0 C+ IN OUT USB0_SSRX1 L- C4Y7 J96611-001 330NF 10% 25V X5R 1 2 0201 USB0_SSRX1 C- IN OUT USB0_SSRX1 L+ C4Y8 J96611-001 330NF 10% 25V X5R 1 2 0201 USB0_SSRX1 C+ IN R4Y17 220K 1% RES 0201 R4Y22 220K 1% RES 0201 R4Y14 220K 1% RES 0201 R4Y13 220K 1% RES 0201 G13778-001 2 RES 0201 GND PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 73/159](.picmg-com-hpc-carrier-design-guide-alt/slide-075.jpg) ## Slide 76 ![This slide presents 'Figure 34: USB 3.2 Gen 2x2 Type-C (5 of 6): Type-C Power Delivery Controller' under the header 'Reference Schematics and Block Diagrams.' The main content is a detailed electronic circuit schematic centered around an IC labeled 'EJUV1 IC TP965994.' Key text elements found within the schematic include: * **Design Note:** 'DESIGN NOTE: TARGET I2C ADDRESS ADDR FROM PD CTRL USB0_RDRV = 0X12 (7BIT) USB1_RDRV = 0X12 (7BIT) EEPROM = 0X50 (7BIT)' * **Design Note:** 'DESIGN NOTE: I2C_EC_ADDR (7BIT) PORT 0 0X20 PORT 1 0X24 FUSE MODE DISABLED' * **Header Label:** 'USBC PD CTRL EEPROM PROGRAMMING HEADER' * **Component Label:** 'U4W1 IC 24AA256' and 'ADDR = 0X50 (7BIT)' In the bottom right corner, a table outlines 'ADCIN1 decoded value,' 'ADCIN2 decoded value,' 'I2C address Index,' and 'Dead Battery Configuration.' The entry for Index #1 includes the text: 'SafeMode: The device does not enable the sink path. USB PD is disabled until configuration is loaded. Note that the configuration could put the device into a source-only mode. This is recommended when the application loads the patch from EEPROM.' The footer reads: 'PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 74/159'.](.picmg-com-hpc-carrier-design-guide-alt/slide-076.jpg) ## Slide 77 ![This slide displays a schematic diagram titled '**Figure 35: USB 3.2 Gen 2x2 Type-C (6 of 6): Type-C Connector and Port Protection**'. The header reads '**Reference Schematics and Block Diagrams**'. The diagram illustrates the electrical connections for a USB Type-C port, featuring: * A connector labeled **JSK4** (J40583-001) with various pin assignments (e.g., USB0_SSD0_C+, CC1). * Protection components including a Zener diode (**CRSY2**) and capacitors (**CSY16**, **CSY17**, **CSY13**, **CSY14**). * A design note box stating '**DESIGN NOTE: SUPPORT USB MODE ONLY**'. * A lower section showing a power supply IC (**U4V1**, TPS6300) connected to resistors (**RV13**, **RV17**) and capacitors (**C4V20**, **C4V12**). * Additional circuitry on the right including resistors (**C4V18**, **C4V17**, **R4V24**, **R4V25**) and ESD diodes (**CR8K3**, **CR8K4**). The footer contains the text '**PICMG® COM-HPC® Carrier Board Design Guide Draft**' and '**Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021**', along with the page number '**75/159**'.](.picmg-com-hpc-carrier-design-guide-alt/slide-077.jpg) ## Slide 78 ![Reference Schematics and Block Diagrams **3.7.11. USB4** An example COM-HPC USB4 implementation, that supports all USB modes up to USB4 Gen 3x2 and the USB Type-C Alternate Modes is shown in Figures 36 through 41 below. Of course this support requires that the COM-HPC Module used supports these modes as well. See Table 10 above for a summary of all the USB modes. This example includes a USB Power Delivery controller, Texas Instruments TPS65994, in Figure 40 below. In this example, the power delivery is out of the COM-HPC Carrier, at 5V and at up to 3A. See Section 3.7.7 above more some discussion on Power Delivery controllers. **Figure 36: USB4 on COM-HPC USB Port 2 (Fig 1 of 6): COM-HPC Side RX Coupling Caps** (COM) USB2_SSTX0- R5J8 1 2 USB2_SSTX0_C- (OUT) 0201 RES H30143-001 0.05W 0 0% (COM) USB2_SSTX0+ R5J7 1 2 USB2_SSTX0_C+ (OUT) 0201 RES H30143-001 0.05W 0 0% (COM) USB2_SSTX1- R5J10 1 2 USB2_SSTX1_C- (OUT) 0201 RES H30143-001 0.05W 0 0% (COM) USB2_SSTX1+ R5J9 1 2 USB2_SSTX1_C+ (OUT) 0201 RES H30143-001 0.05W 0 0% (COM) USB2_SSRX0- C5J2 X5R 1 2 220NF USB2_SSRX0_C- (BI) 0201 25V 10% J95198-001 (COM) USB2_SSRX0+ C5J1 X5R 1 2 220NF USB2_SSRX0_C+ (BI) 0201 25V 10% J95198-001 (COM) USB2_SSRX1- C5J4 X5R 1 2 220NF USB2_SSRX1_C- (BI) 0201 25V 10% J95198-001 (COM) USB2_SSRX1+ C5J3 X5R 1 2 220NF USB2_SSRX1_C+ (BI) 0201 25V 10% J95198-001 (COM) USB2_AUX- R5J26 1 2 USB2_AUX_R- (BI) 0402 RES A93549-001 0.0625W 0 0% (COM) USB2_AUX+ R5J24 1 2 USB2_AUX_R+ (BI) 0402 RES A93549-001 0.0625W 0 0% (COM) USB2_LSTX R6W24 1 2 USB2_R_LSTX (OUT) 0402 RES A93549-001 0.0625W 0 0% (COM) USB2_LSRX R5W29 1 2 USB2_R_LSRX (IN) 0402 RES A93549-001 0.0625W 0 0% PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 76/159](.picmg-com-hpc-carrier-design-guide-alt/slide-078.jpg) ## Slide 79 ![**Header and Footer:** * **Top Right:** Reference Schematics and Block Diagrams * **Title:** Figure 37: USB4 on COM-HPC USB Port 2 (Fig 2 of 6): Intel JHL8040R Thunderbolt Retimer Part 1 * **Bottom Left:** PICMG® COM-HPC® Carrier Board Design Guide Draft * **Bottom Center:** Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 * **Bottom Right:** 77/159 **Design Note Box:** * DESIGN NOTE: * - FORCE_PWR : 0 = DEFAULT ; 1 = FOR DEBUG ONLY / FW UPDATE * - FLASH_SHARE_EN : 0 = FLASH IS NOT SHARED * - FLASH_MASTER_SLAVE(MS) : 1 = SET BB TO BE MASTER ON SHARED FLASH SPI **Schematic Components and Labels:** * **IC US1 (JHL8040R) - Left Block:** * Pins: J1, C3, C2, E2, E1, M7, M8, L8 * Labels: BB_TCPI2_FLASH_CS, BB_TCPI2_FLASH_DI, BB_TCPI2_FLASH_DO, BB_TCPI2_FLASH_WP, BB_TCPI2_FLASH_HOLD#, PA_LSTK_SRU#, PA_LSR0_SBU#, PA_AUX_P, PA_AUX_N * **IC US1 (JHL8040R) - Right Block:** * Pins: C7, B7, A3, B6, C6, M11 * Labels: BB_TCPI2_FLASH_CLK, BB_TCPI2_FLASH_DO, BB_TCPI2_FLASH_DI, BB_TCPI2_SMB, BB_TCPI2_TDO, TDP_TSK0_TSK0A, I2C_SDA, I2C_SCL, I2C_INF_N, FORCE_PWR, FLASH_BUSY_N, POC_GPIO_5, POC_GPIO_6, POC_GPIO_7, SMBUS_SCL, SMBUS_SDA, POC_GPIO_10, POC_GPIO_11, POC_GPIO_12, RESET_N, TEST_EN, MONDC_N2, MONDC_SVR, TEST_PWR_GOOD, ATEST_P, ATEST_N, THERMDA * **IC Y5K1:** * Pins: 1, 2, 3, 4 * Labels: XTAL, GND * **Resistors R917, R918, R919, R920:** TCPI2_RT_TSK0+, TCPI2_RT_TSK0-, TCPI2_RT_TSK1+, TCPI2_RT_TSK1- * **Resistors R923, R924, R925, R926:** SMG_CLK, SMG_DAT, BB_TCPI2_FLASH_BUSY#, BB_TCPI2_FLASH_WP# * **Resistors R910, R906:** SUS_G4_RST#, BB_TCPI2_RESET# * **Resistors R904, R903, R911, R912:** TCPI2_RETIMER_PERS#_N, TCPI2_RETIMER_POWR_PIN, +V3P3_A * **Resistors R905, R906:** BB_TCPI2_FLASH_BUSY#, BB_TCPI2_TEST_PWR_GOOD * **Resistors R901, R902:** BB_TCPI2_GPIO_5, BB_TCPI2_GPIO_6 * **Resistors R913, R915:** BB_TCPI2_FLASH_SHARE_EN, BB_TCPI2_FLASH_MODE_RAV * **Resistors R907, R908:** BB_TCPI2_GPIO_12 * **IC UBW1:** * Pins: 8, 1, 6 * Labels: VCC, CS_N, CLK * Connections: BB_TCPI2_FLASH_CS#, BB_TCPI2_FLASH_DI#, BB_TCPI2_FLASH_DO#, BB_TCPI2_FLASH_WP#, BB_TCPI2_FLASH_HOLD# * **IC XLBW1 (mx25l12835f_ppg):** * Pins: 1, 8, 4 * Labels: VCC, RESET_N, GND * Connections: BB_TCPI2_FLASH_CS#, BB_TCPI2_FLASH_DI#, BB_TCPI2_FLASH_DO#, BB_TCPI2_FLASH_WP#, BB_TCPI2_FLASH_HOLD# **CAD Notes:** * CAD NOTE: MAKE SURE CLEARANCE AROUND SPI CHIP FOR PROGRAMMING CLIP * CAD NOTE: SPI CLIP PGZ, OVERLAP SYMBOL WITH SPI FLASH IC](.picmg-com-hpc-carrier-design-guide-alt/slide-079.jpg) ## Slide 80 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 38: USB4 on COM-HPC USB Port 2 (Fig 3 of 6): Intel JHL8040R Thunderbolt Retimer Part 2 **Schematic Content:** * **IC U5J1 (Top Left):** JHL8040R. Pins: SVR_VSS_1, SVR_VSS_2, VCCIP_ANA, VCCIP1_LC, SVR_IND_2, VCCIP9_SVR_ANA_1, VCCIP9_SVR_ANA_2, VCCIP9_SVR, VCCIP9_SVR_PS_ANA, VCCIP9_SVR_PE_ANA, VCCIP9_LC. Labels: L3, NC, J6, NC, J6, 4 OF 4. * **Capacitors (Top Left):** C5W11, C5W16, C5W15, C5W17 (1 2.2UF 10% 10V X5R 0402). C5W18 (1 47UF 20% 6.3V X5R 0603). * **Net Labels (Top Left):** +VCC3P3_LC_TCP2, +VCCIP9_SVR_TCP2_PHASE, +VCCIP9_SVR_TCP2, +VCCIP9_LVR_TCP2. * **IC U5J1 (Top Right):** JHL8040R. Pins: B1, B12, D1, D11, D12, D2, F1, F2, F9, F11, F12, H1, H12, H11, K1, K2, K11, K12, G1, G2, F5, F3, G5. Labels: NC, J6, NC, J6, 3 OF 4. * **Net Labels (Top Right):** VSS_ANA, VSS. * **Top Right Components:** C5J7 (1 47UF 20% 6.3V X5R 0603). C5J8, C5J9, C5W19, C5Y3 (1 2.2UF 10% 10V X5R 0402). R5W32 (1 0.0425W 5% RES 0402). C5Y5 (1 10UF 5% 50V C0G 0402). C5Y4 (1 2.2UF 10% 10V X5R 0402). * **Net Labels (Top Right):** +VCC3P3_SX_TCP2, +VCC3V3A_S0_TCP2, +VCC3V3_SX_TCP2, +VCC3P3_LC_TCP2. * **Inductor L5J1 (Bottom Left):** IC, IND, 0.68UH, J79658-001, 1 2016M. * **Bottom Left Capacitors:** C5J5 (1 47UF 20% 6.3V X5R 0603). C4J13 (1 47UF 20% 10V X5R 0603). C5W12, C5W13, CSY1, CSY2 (1 2.2UF 10% 10V X5R 0402). CSY6, CSY (1 2.2UF 10% EMPTY 0402). CSW14 (1 18PF 5% 50V C0G 0402). * **IC U5Y1 (Bottom Left):** IC, SLGSNT1458V. Pins: VDD, CAP, ON, GND, 5, 8, 2, 3, D, GND. * **Bottom Left Resistors/Caps:** R5Y1, R5Y2 (1 0.0425W 5% RES 0402). CSY7 (1 0.1UF 10% 25V X7R 0402). CSY8 (1 10UF 10% 25V X5R 0402). * **Net Labels (Bottom Left):** +V3P3_A, +V5_A, +V3.3DQ_RT_TCP2_SR_CAP, +V3.3DQ_RT_TCP23, +VCC3P3_SX_TCP2, TCP23_LS_EN, USB_RT_ENA, +V3P3_A, +V3.3DQ_RT_TCP2_EN. * **IC FBBY1 (Bottom Middle):** 693286-057, 330 25% 1.5A FB. * **Bottom Middle Capacitors:** CSY9, CSY10 (1 10UF 20% 10V X5R 0402). CSY11 (1 2.2NF 10% 50V X7R 0402). * **IC J1J1 (Bottom Right):** ICON HDR_2X3, E54876-001. * **Bottom Right Resistors:** R1J2, R1J5, R1J3, R1J4 (1 0.0425W 5% RES 0402). * **Signal Labels (Bottom Right):** IN, OUT, BB_TCP2 TDI, BB_TCP2 TCR, BB_TCP2 TMO R, BB_TCP2 TMO L. **Notes:** * CAD NOTE: LVR_Sense routing should be from the load * CAD NOTE: Put 0-ohm res near to retimer. Put 2x3 HDR at board edge extended debug porch **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 78/159](.picmg-com-hpc-carrier-design-guide-alt/slide-080.jpg) ## Slide 81 ![**Header:** Reference Schematics and Block Diagrams **Title:** Figure 39: USB4 on COM-HPC USB Port 2 (Fig 4 of 6): Output Coupling and Protection **Left Side Components (ESD Protection Diodes):** * CR5K5 (J96837-001, 4.5A, DIO) * CR5K6 (J96837-001, 4.5A, DIO) * CR5K8 (J96837-001, 4.5A, DIO) * CR5K7 (J96837-001, 4.5A, DIO) * CR5K1 (J96837-001, 4.5A, DIO) * CR5K2 (J96837-001, 4.5A, DIO) * CR5K4 (J96837-001, 4.5A, DIO) * CR5K3 (J96837-001, 4.5A, DIO) **Bottom Left Components:** * FROM COM-HPC CONN * LSK1 (752402-015, 00, 0.4A, IND) * RSK14 (A93549-001, EMPTY, 0.0625W, 0 0%) * RSK13 (A93549-001, EMPTY, 0.0625W, 0 0%) **Right Side Components (Coupling Caps & Protection):** * **ACTUAL CAP VALUE PENDING SI RECOMMENDATION** * CSK3 (J95198-001, 220nF, 10%, 25V, X5R) * CSK4 (J95198-001, 220nF, 10%, 25V, X5R) * CSK5 (J95198-001, 220nF, 10%, 25V, X5R) * CSK6 (J95198-001, 220nF, 10%, 25V, X5R) * CSK7 (J96611-001, 330nF, 10%, 25V, X5R) * CSK8 (J96611-001, 330nF, 10%, 25V, X5R) * CSK9 (J96611-001, 330nF, 10%, 25V, X5R) * CSK10 (J96611-001, 330nF, 10%, 25V, X5R) * **RC SHORT PROTECTION** * RSK23 (220K, 1%, RES) * RSK24 (220K, 1%, RES) * RSK25 (013778-001, 220K, 1%, RES) * RSK26 (220K, 1%, RES) **Note:** * **Note:** The ESD protection diodes shown at the upper left of this page are isolated from the USB4 Type- C connector (J5K3 shown in Fig 6 of 6 of this series) by the coupling caps shown just above, to prevent accidental exposure to potential hazards during connector insertion. Traditionally, the ESD protection diodes are placed right at the external connector pins, and some designers may choose to do so. **Footer:** * PICMG® COM-HPC® Carrier Board Design Guide Draft * Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 * 79/159](.picmg-com-hpc-carrier-design-guide-alt/slide-081.jpg) ## Slide 82 ![Reference Schematics and Block Diagrams Figure 40: USB4 on COM-HPC USB Port 2 (Fig 5 of 6): Power Delivery Controller (Left Section) R5V8, 10K, 1%, RES, 0402 R5V16, A39349-023, 10K, 5%, RES, 0402 SBL_TCP2_RESET#, SBL_TCP1_RESET#, DBPTV, DBPTV +V3P3_PD2_LDO R5V20, A39349-016, 1K, 5%, RES, 0402 R5V23, 1K, 5%, RES, 0402 R5V19, A39349-023, 10K, 5%, RES, 0402 FD2_I2C3_INT# FD2_I2C3_SDA FD2_I2C3_SCL R5V24, 1, 10K, 2 RES, 0402, FD2_I2C3_SCL R5V25, 1, 10K, 2 RES, 0402, FD2_I2C3_SDA R5V18, 1, 10K, 2 RES, 0402, FD2_I2C3_INT# J51, HDR_1X3, 1, 2, 3, FD2_I2C3_SCL, FD2_I2C3_SDA, GND (Bottom Left) USBC PD CTRL EEPROM PROGRAMMING HEADER R5V03, 5%, 10k, 1%, RES, 0402 R5V04, 5%, 10k, 1%, RES, 0402 R5V05, 5%, 10k, 1%, RES, 0402 R5V06, 5%, 10k, 1%, RES, 0402 USW1 IC, 24AA256 A2, VCC, 8 A1, A0, 1 SCL, SDA, 5 WP, VS, 4 FD2_FLASH_A2, FD2_FLASH_A1, FD2_FLASH_A0, FD2_I2C3_SCL, FD2_FLASH_WP +V3P3_PD2_LDO R5V25, 20K, 1%, DBPTV, 0402, A39348-181 24AA256 (K67554-001) ADDR = 0X50 (7BIT) (Center Component) EUW1 IC, TPS65994 GPIO9, 32, VIN_3V3 GPIO8, 10 GPIO7, 27 GPIO6, 29 GPIO5, 46 GPIO4, 2 GPIO3, 28 GPIO2, 19 GPIO1, 38, BB_TCP1_RESET# BB_TCP2_RESET#, 45 USB_EP_12C_CLK, R5V12, 1, 10K, 2 RES, 0402, FD2_I2C3_CLK, 42 USB_EP_12C_RX, R5V10, 1, 10K, 2 RES, 0402, FD2_EC_CLK, 40 USB_EP_ALERT#, R5V13, 1, 10K, 2 RES, 0402, FD2_EC_ALERT#, 43 SML_CLK, R5V11, 1, 10K, 2 RES, 0402, FD2_SML_CLK, 41 SML_I2C, R5V14, 1, 10K, 2 RES, 0402, FD2_SML_I2C, 44 FD2_I2C3_SCL, 1, FD2_I2C3_SDA, 48, FD2_I2C3_INT#, 47, FD2_24AA256#, 39 PB_CC2, 7, +VTCPC1_CC2 PB_CC1, 6, +VTCPC2_CC2 PA_CC2, 30, +VTCPC2_CC1 PA_CC1, 31 PB_GATE_VSYS, 18 PB_GATE_VBUS, 4, 5, TP_FD2B_GATE_VSYS, TP_FD2B_GATE_VBUS PA_GATE_VSYS, 19, TP_FD2A_GATE_VSYS, TP_FD2A_GATE_VBUS VSYS, 3, FD2_VSYS GND, 36 THPAD, 48 (Right Section) +V3P3_A_SEV CSV5, G33975-001, 10uF, 20%, 25V, 2 X5R, 0603 +V5_A CSV14, H14975-001, 1, 47uF, 20%, 10V, 2 X5R, 0805 CSV13, H14975-001, 1, 47uF, 20%, 10V, 2 X5R, 0805 CSV11, A36096-125, 1, 10uF, 20%, 10V, 2 X5R, 0402 CSV10, A36096-125, 1, 10uF, 20%, 10V, 2 X5R, 0402 CSV8, A36096-143, 1, 10uF, 20%, 25V, 2 X5R, 0402 +V_TCPC1_VBUS_CONN +V_TCPC2_VBUS_CONN CSV12, 1, 47uF, 20%, 10V, X5R, 0402 CSV9, 1, 47uF, 20%, 10V, X5R, 0402 +V1P5_PD2_LDO CSV6, A36096-121, 1, 2,2uF, 10%, 10V, 2 X5R, 0402 CSV7, A36096-134, 1, 4,7uF, 10%, 10V, 2 X5R, 0402 +V3P3_PD2_LDO CSV4, A36096-125, 1, 10uF, 20%, 10V, 2 X5R, 0402 R5V22, A39349-001, 1, 0, 0,0472M, 2 RES, 0402 (Bottom Right Resistors) R5V21, 1, 1K, 5%, RES, 0402 R5V15, 1, 1K, 5%, RES, 0402 R5V5, 1, 1K, 5%, RES, 0402 R5W2, 1, 1K, 5%, RES, 0402 RSW1, A39349-016, 1K, 5%, 0,0625W, RES, 0402 I2C_ADDR (7BIT) PORT 2 0X21 PORT 3 0X25 SINK MODE DISABLED R5V7, 10K, 1%, 0,0625W, EMPTY, 0402 R5V3, 10K, 1%, 0,0625W, EMPTY, 0402 FD2_ADCIN1, FD2_ADCIN2 R5V2, 1, 0%, RES, 0402 R5V4, 1, 0%, RES, 0402 (Table) ADCIN1 decoded value (2) ADCIN2 decoded value (2) I2C address Index (1) Dead Battery Configuration 7 0 #1 SafeMode: The device does not enable the sink path. USB PD is disabled until configuration is loaded. Note that the configuration could put the device into a source-only mode. This is recommended when the application loads the patch from EEPROM. 0 0 #2 6 0 #3 5 7 #4 PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 80/159](.picmg-com-hpc-carrier-design-guide-alt/slide-082.jpg) ## Slide 83 ![Reference Schematics and Block Diagrams Figure 41: USB4 on COM-HPC USB Port 2 (Fig 6 of 6): Type-C Connector and USB Port Protector +V_TCP_C2_VBUS_CONN CR5Y1 J58608-001 NSR20P30NXT5G 2A DIO SM C A GND J5K3 SCON USB3_C_SHLD_24P_6M J40583-001 A2 TCP2_RT_TXD0_C+ IN A3 TCP2_RT_TXD0_C- IN A4 +VTCPC2_CCI_CONN IN A5 USB2_F2_L- IN A6 USB2_F2_L+ IN A7 TCP2_SBU1_CONN IN A8 TCP2_RT_TXK1_C- IN A9 TCP2_RT_TXK1_C+ IN A10 M-1 A11 M-2 A12 M-3 M-4 M-5 M-6 GND B12 GND_B2 B11 RX1_DP B10 RX1_DN B9 VBUS_B6 B8 CC2 B7 D_B_DN B6 D_B_DP B5 VBUS_B1 B4 TX2_DN B3 TX2_DP B2 GND_B1 B1 TCP2_RT_RXD0_C+ TCP2_RT_RXD0_C+ IN TCP2_RT_RXD0_C- IN TCP2_SBU2_CONN IN USB2_F2_L- IN USB2_F2_L+ IN +VTCPC2_CC2_CONN IN TCP2_RT_TX1_C- IN TCP2_RT_TX1_C+ IN C5Y18 1 0.1UF 10% 10V 2 X5R 0402 GND C5Y19 1 0.1UF 10% 10V 2 X5R 0402 GND C5Y15 1 0.1UF 10% 10V 2 X5R 0402 GND C5Y12 A36096-043 1 0.1UF 10% 10V 2 X5R 0402 GND +V3P3_BD2_LDO R5W14 A93549-027 100R 3% 0.0625W RES 0402 EUSW1 TFPD6300 IC 3 VBIAS 10 VPMR 1 C_SBU1 2 C_SBU2 4 C_CCI1 5 C_CCI2 12 CCI1 11 CCI2 8 GND_1 13 GND_1 18 GND_3 21 GND_TP1 20 D1 19 D2 16 NC1 17 NC2 15 SBU1 14 SBU2 +V3P3_BD2_LDO +VBIAS_TCP2 C5W7 602433-020 0.1UF 10% 50V 2 X7R 0603 GND C5W1 A36096-088 2.2UF 20% 6.3V 2 X5R 0402 GND +VTCPC2_CC2_CONN R5W17.1 0402 6 0 RES 0402 TCP2_RPD_G2 +VTCPC2_CCI_CONN R5W18.1 0402 7 2 RES 0402 TCP2_RPD_G1 +VTCPC2_CC2_CONN TCP2_SBU1_CONN SBU1 TCP2_SBU2_CONN SBU2 +VTCPC2_CC2_CONN C5W6 1 220PF 10% 50V 2 X7R 0402 GND C5W5 A36096-050 1 220PF 10% 50V 2 X7R 0402 GND TCP2_SBU2_CONN R5W22 A93548-209 1M 1% 0.0625W RES 0402 GND TCP2_SBU1_CONN R5W23 A93548-209 1M 1% 0.0625W RES 0402 GND USB2_F2_L+ SM DIO 3.5A BSD131-B1-W0201 J76907-001 CR5K9 2 1 GND USB2_F2_L- SM DIO 3.5A BSD131-B1-W0201 J76907-001 CR5K10 2 1 GND PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 81/159](.picmg-com-hpc-carrier-design-guide-alt/slide-083.jpg) ## Slide 84 ![**3.8. Boot SPI on Carrier** The COM-HPC Base Specification V1.0 describes various boot SPI options at some length in Sections 4.3.9 and 4.3.10. The layout topology for the BOOT_SPI bus is given in Section 6.11.1 of the COM-HPC Base Specification V1.0. Please refer to those Base document sections in addition to the materials presented here to get a bigger picture. Contemporary x86 chipsets typically have a SPI boot bus with three chip-selects: two for up to two SPI Flash devices to hold various pieces of boot firmware including the BIOS, and possibly a backup BIOS, and a 3rd chip-select dedicated to an on-Module TPM. device. The two chip-set chip-selects for boot SPI flash devices can be routed to either two on-Module SPI Flash devices, or to one on-Module SPI Flash and to one Carrier based SPI Flash device. The various possible permutations are selected by a set of three Module strap pins named BSEL0, 1, and 2. See COM-HPC Base Specification V1.0 Section 4.3.10 Table 10 for the decoding of the BSEL(0:2) pins. It is possible to have the entire boot firmware image reside in a Carrier based SPI Flash device. It is also possible of course to have the entire boot image on the module, and it is possible to split the boot image to have some parts on the Module and some on the Carrier. Some Module designs implement multiplexers to allow even more options. A typical Carrier Boot SPI Flash implementation is shown in Figure 42 below.. Some points about this Figure are given on the following page. **Figure 42: Boot SPI on Carrier (Example 1)** **Schematic Description:** * **Left Side:** Columns for 'SPI MODE' and 'QSPI MODE' with 'COM' pins. * **Top Rail:** 'VCC_BOOT_SPI' connects to Pin 8 (VCC) of chip U1. Pull-up resistors R1 (10K) and R2 (10K) and capacitor C1 (100 nF) are connected to this rail. * **Data Lines (via 15 ohm resistors R3-R6):** * BOOT_SPI_IO3 (R3) connects to Pin 7 (HOLD# / IO3). * BOOT_SPI_IO2 (R4) connects to Pin 3 (WP# / IO2). * BOOT_SPI_IO1 (R5) connects to Pin 2 (DO / IO1). * BOOT_SPI_I00 (R6) connects to Pin 5 (DI / IO0). * **Control Lines:** * BOOT_SPI_CLK (R7) connects to Pin 6 (CLK). * BOOT_SPI_CS# connects to Pin 1 (CS#). * **Ground:** Pin 4 (GND) is grounded. * **Jumper Block:** Connected to pins labeled BSEL0, BSEL1, and BSEL2. * **Chip U1:** Labeled 'Winbond' with options W25Q64JV (64 Mbit), W25Q128JV (128 Mbit), and W25Q256JV (256 Mbit). **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 82/159](.picmg-com-hpc-carrier-design-guide-alt/slide-084.jpg) ## Slide 85 ![Reference Schematics and Block Diagrams * **Notes on Figure 42 above:** * The Carrier SPI Flash device power is provided by a special COM-HPC Module pin named VCC_BOOT_SPI. This should be the only power source for the Carrier SPI Flash device and any related pull-ups and bypass capacitors., as shown in the Figure. * The VCC_BOOT_SPI voltage level may be 3.3V or 1.8V. * This is Module vendor specific. * It is not common or expected that a given SPI Flash device will be able to operate at both 3.3V and 1.8V. A few devices might be able to do so. * The SPI Flash devices listed in the Figure above are 3.3V devices, and are not rated at 1.8V. * The VCC_BOOT_SPI power net may be in the S5 (suspend) or S0 (on) power domains. * This is Module vendor specific. * QSPI devices from Microchip / SST are shown in the Figure above. * Windbond is a very popular selection for QSPI devices: W25Q16JV is a sample Winbond base part number for their 16 Mbit part. There are 16, 32, 64 and 128 Mbit offerings from Winbond. * There are many packaging options available from the QSPI vendors * There are package size differences between vendors even for package names that at first glance sound the same (like SOIC8 etc) ... so care must be taken. * The Winbond SOIC8 packages are smaller than the Microchip devices. * There are register differences between various SPI Flash vendor offerings. The Module firmware / BIOS may not be compatible with some devices. Check with the Module vendor. * Carrier designers should use parts from the same SPI Flash vendor(s) and family as the Module vendor uses. * There may be reasons to use different package types on the Carrier: * The Module vendor likely uses the smallest possible package size. * Carrier designs may want to implement a removable (socketed) SPI Flash device. * Carrier designers may elect to use a SPI package that is easier to rework. * Contemporary SPI Flash devices may operate in one of several modes: * Traditional SPI mode (noted at left side of Figure 42 above). * This mode has one data line into the SPI device and one out. * QSPI (“Quad SPI”) mode: * This mode has 4 bidirectional data lines, offering a higher net data bandwidth. * The SPI Flash devices typically power up in the traditional SPI Flash mode and must be put into the QSPI mode by software. * The HOLD# and WP# inputs of a traditional SPI device are disabled by pull-ups R1 and R2 in the Figure above. For QSPI mode operation, the PCB trace stubs from the QSPI data lines to these pull-ups should be minimized. * If the SPI device is to immediately be put into QSPI mode, it is likely possible that R1 and R2 can be omitted. * There are specific routing rules for the BOOT_SPI_xx nets. See Section 4.4 of this document and Section 6.11.1 of the COM-HPC Base Specification V1.0. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 83/159](.picmg-com-hpc-carrier-design-guide-alt/slide-085.jpg) ## Slide 86 ![Reference Schematics and Block Diagrams Removable / Reprogrammable SPI Flash Devices In some situations it is desirable or even required to have a socketed or removable Boot SPI Flash device. This is the case, for example, in some casino gaming jurisdictions, to allow the BIOS device to be removed and inspected by a regulatory technician. A socketed or removable BIOS can also be useful in product development situations, allowing easy replacement of a corrupted BIOS device. Some possible socket solutions are listed in Table 15 below: Table 15: Boot SPI Socket Suggestions Vendor Vendor P/N Notes :--- :--- :--- Enplas Enplas offers a variety of sockets that accept several 8 and 16 pin SOIC sizes. Winbond and other vendors offer some of their SPI Flash devices in a 16 pin SOIC along with a variety of smaller form factors. It may be easier to find a socket for an SOIC16 device. The Carrier Boot SPI Flash device should be from the same flash vendor and family as the part used on the Module. The package details may be different. Lotes ACA-SPI-004-K Should be suitable for the Microchip SST26VFxxxB SOIJ8 parts. ACA-SPI-006-T01 Suitable for Macronix MX77U25650F (32 MB 1.8V QSPI) or MX77L25650F (32 MB 3.3V QSPI) 16 pin 300 mil SOIC parts shown in Figure 43 below. Other Lotes socket parts may be relevant here. Generic Winbond offers some of their Flash devices in 300 mil DIP format, for which there are many generic sockets. Some gaming firms design their own removable BIOS assembles. These are sometimes referred to as “cartridges”. This allows the use of any SPI Flash device desired, and it can ensure easy removal and replacement of the device.. Some Carrier designers add features that multiplex signals and power to the Carrier SPI Flash device allowing the device to be used as usual in the system or cut the device off from the system and allow the device to be reprogrammed by a cable to an external piece of programming equipment. An example of such implementations (SPI device in a socket and a multiplexer to allow the SPI flash device to be programmed by an external programming tool) is shown in Figure 43 below. The programming tool in this case is from a company called Dediprog. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 84/159](.picmg-com-hpc-carrier-design-guide-alt/slide-086.jpg) ## Slide 87 ![Reference Schematics and Block Diagrams Figure 43: Boot SPI on Carrier – Socketed Flash and Multiplexer to External Programmer +V5_BOOT R6B17 C5B20 Q6B1 +V1P8_A R4R7 R4R8 R4R11 R4R5 R4R12 +V3P3 R6B11 R6B4 J6B1 HDB_2521... E30 K11 (RUB) DESIGN NOTE: TTK3 + DIEDIPROG PROG CONN +V3P3_A CAD NOTE: DO NOT OVERLAP PAD, PLACE 2 RES BRANCH CLOSE TOGETHER & LOW STUB BOOT SPI C5# R27E R29D R2F1 R2F27 R2F21 R2F2 R2F10 R2F30 SPI_100_B SPI_100_TTK SPI_101_B SPI_101_TTK SPI_102_B SPI_102_TTK SPI_103_B SPI_103_TTK SPI_CLK_B SPI_CLK_TTK CAD NOTE: PLACE IC NEAR SPI SOCKET EU4R1 753A275182 Table 2 Function Table EN IN1 IN2 NC103 TO COM103 COM103 TO NC103 NC102 TO COM102 COM102 TO NC102 NC101 TO COM101 COM101 TO NC101 NC100 TO COM100 COM100 TO NC100 H X X OFF OFF OFF OFF L L L ON ON OFF OFF L H L OFF ON OFF ON L H H OFF ON OFF ON +V3P3_A C4R1 BOOT_SPI_100 SPI_100_TTK SPI_101_B SPI_101_TTK SPI_102_B SPI_102_TTK SPI_103_B SPI_103_TTK SPI_CLK_B SPI_CLK_TTK RTC_RST# R4B6 TTK_RI_RST# U3A00 TX R4B14 TTK_U3A00 TX U3A00 RX R4B13 TTK_U3A00 RX U3A00 CTS# R4B15 TTK_U3A00 CTS# SPI_100_B R4B10 TTK_SPI_100_B SPI_101_B R4B11 TTK_SPI_101_B SPI_102_B R4B12 TTK_SPI_102_B SPI_103_B R4B16 TTK_SPI_103_B RTC_RST_N_FROM_PUMA_C53B GPIO9 = LVL_SPTRD 3.3V CARRIER FROM MODULE C3R2 C3R3 R7E5 R7F3 DESIGN NOTE: BO#1: SPI CHIP MACRONIX K51180-001 M277L25650RN142 (3.3V SOP16) K55121-001 M277L25650RN142 (1.8V SOP16) BOARD 50 BOARD G3, TTK POWERED XLP1 SPI_FLASH_16P CAD NOTE: PLACE SPI_SOCKET NEAR HPC CONN R4R4 R4R2 Q4R1 R4R6 R4R3 Q4R2 PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 85/159](.picmg-com-hpc-carrier-design-guide-alt/slide-087.jpg) ## Slide 88 ![Reference Schematics and Block Diagrams **3.9. eSPI** The COM-HPC Client and Server pin-outs support an eSPI (Enhanced Serial Peripheral Interface) port. There may be up to two eSPI devices on the Module and up to two eSPI devices on the Carrier. The eSPI interface is promoted as the successor to to the LPC (Low Pin Count) general x86 I/O interface. The eSPI data and clock signals run at about 50 MHz. The COM-HPC Base Specification Section 6.11.2 recommends a “balanced tree” routing topology. This is also referenced in Section 4.4 of this document. Figure 44 below illustrates a “generic” eSPI implementation example for one branch of the tree, that might apply to a Carrier Super I/O, FPGA, CPLD, eSPI to LPC bridge, or other eSPI peripheral. The COM-HPC eSPI interface is a 1.8V level interface that operates in all power states, S5 through S0. The Figure shows some additional signals that are 3.3V level signals, also active in all power domains, that may be needed for some eSPI peripheral implementations. Some Carrier situations may require legacy Intel LPC (Low Pin Count) compatibility. The Microchip ECE1200 is a suitable eSPI to LPC bridge device that is referenced in some Intel literature for this task. Microchip is also a popular vendor for Carrier based management micro-controllers with an eSPI interface. **Figure 44: eSPI Generic Interface Example: SIO, FPGA, LPC Bridge, or Other Peripheral eSPI Device** (Diagram Text) 1.8V S5 Power Domain Signals to / from COM-HPC +1.8V_A C1 100 nF U1 VCC_1V8_S5 VCC_3V3_S5 +3.3V_A C1 100 nF COM eSPI_IO3 COM eSPI_IO2 COM eSPI_IO1 COM eSPI_IO0 COM eSPI_CLK COM eSPI_CS0# COM eSPI_CS1# COM eSPI_ALERT0# COM eSPI_ALERT1# COM eSPI_RST# COM PLRST# COM RSMRST_OUT# COM SUS_CLK R1 15 ohm R2 15 ohm R3 15 ohm R4 15 ohm R5 15 ohm R6 0 ohm R7 Open R8 0 ohm R9 Open Series Damping Resistors Opt on Resistors eSPI_IO3 eSPI_IO2 eSPI_IO1 eSPI_IO0 eSPI_CLK eSPI_CS# eSPI_ALERT# eSPI_RESET# RESET# RESUME_RESET_IN# SUS_CLK GND Super I/O FPGA / CPLD eSPI to LPC Bridge eSPI Peripheral 3.3V S5 Power Domain Signals from COM-HPC PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 86/159](.picmg-com-hpc-carrier-design-guide-alt/slide-088.jpg) ## Slide 89 ![**Header** Reference Schematics and Block Diagrams **Title** 3.10. DisplayPort Over DDI **Figure Caption** Figure 45: DisplayPort Over DDI **Schematic Content** * **Top Section:** * Top right: Resistor 'R?', '0', '0603' connected to ground. Ground labeled 'SHIELD'. * Connector 'CN52' (part number 'WDPE-20F5L1BU3') with pins 1-20 labeled (e.g., GND, D0+, D0-, D1+, D1-, AUX+, AUX-, HPD, PWR, CAI/GND, CEC/GND). * Signal lines on the left: 'DDI0_PAIR0+', 'DDI0_PAIR0-', 'DDI0_PAIR1+', 'DDI0_PAIR1-', 'DDI0_PAIR2+', 'DDI0_PAIR2-', 'DDI0_PAIR3+', 'DDI0_PAIR3-', 'DDI0_DDC_AUX_SEL', 'DDI0_SDA_AUX+', 'DDI0_SDA_AUX-'. Several are marked 'COM'. * Components 'C310' through 'C317' with note '8x 0402 25V 100n'. * Inductors labeled 'DLP11TB800UL2L' (TR31, TR30, TR32, TR33, TR34). * Signal lines connected to inductors: 'DP0_TXP0', 'DP0_TXN0', 'DP0_TXP1', 'DP0_TXN1', 'DP0_TXP2', 'DP0_TXN2', 'DP0_TXP3', 'DP0_TXN3', 'DP0_CEC', 'DP0_AUXP', 'DP0_AUXN', 'DP0_HPD'. * **Middle Left Section:** * Power rail '+3.3V_S' connected to fuse 'F7' (NANOSMDC075F). * Diode 'D57'. * Switch 'SDM2U40CSP-7B' (Q30) with pins 1, 2, 3. * MOSFET 'SI2312CDS-T1-GE3' with pins 1, 2, 3. * Resistor 'R278' (1K, 0402) connected to '+5V_S'. * Resistor 'R279' (100K, 0402) connected to ground. * Inductor 'L28' (BLM18PG121SN1J). * Capacitor 'C319' (100n, 25V, 0402). * Diode 'D58' (ESD9X3.3ST5G). * Label '3.3V_DP0'. * Ground labeled 'SHIELD'. * Resistors 'R200' (0, 0603) connected to ground. * **Bottom Left Section:** * Resistors: 'R275' (5.1M, 0402), 'R276' (100K, 0402), 'R277' (1M, 0402) connected to ground. * Signals: 'DP0_CEC', 'DP0_HPD', 'DDI0_DDC_AUX_SEL'. * IC 'U49' (NC7WZ16P6X). Pins: Y1, A1, VCC, GND, Y2, A2. * Signal 'DDI0_HPD' connected to 'COM' and pin 6 (Y1). * '+3.3V_S' connected to pin 5 (VCC). * Capacitor 'C318' (100n, 25V, 0402) connected to pin 4 (GND). * Signal 'DP0_HPD' connected to pin 1 (A1). * **Bottom Right Section (ESD Protection):** * IC 'D54' (AOZ8809ADI-05). Pins 1-6. Signals: 'DP0_AUXN', 'DP0_AUXP', 'DP0_HPD', 'DDI0_DDC_AUX_SEL'. * IC 'D55' (AOZ8809ADI-05). Pins 1-10. Signals: 'DP0_TXN1', 'DP0_TXP1', 'DP0_TXN0', 'DP0_TXP0'. * IC 'D56' (AOZ8809ADI-05). Pins 1-10. Signals: 'DP0_TXN3', 'DP0_TXP3', 'DP0_TXN2', 'DP0_TXP2'. **Footer** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 87/159](.picmg-com-hpc-carrier-design-guide-alt/slide-089.jpg) ## Slide 90 ![Reference Schematics and Block Diagrams Notes on DisplayPort over DDI: * COM-HPC supports three DDI channels, designated DDI0, DDI1 and DDI2. The Figure above uses DDI0 as an example. * DisplayPort data pairs are capacitively coupled, near the DisplayPort cable connector, as seen in the Figure above (C310 through C317). * This is in contrast to HDMI data pairs which are typically DC coupled. * However, some HDMI buffers / level shifters / redrivers use AC coupling at the buffer inputs and DC coupling at the buffer outputs. * The DisplayPort AUX channel data pair (net names DDI0_SDA_AUX+ and – in this example) are AC coupled on the COM-HPC Module, when the DDI channel is used in DisplayPort mode. * When the DDI channel is used in HDMI mode, the DDlx_SDA_AUX+ and – pair (where ‘x’ is 0,1 or 2) are DC coupled on the Module, for the HDMI SDA and SCL I2C setup channel. * The COM-HPC signal DDlx_DDC_AUX_SEL signals are Module input signals that are used to select either DisplayPort or HDMI mode. * If the signal is pulled or driven low, or left NC, then the Module invokes DisplayPort mode. * If the signal is driven to a logic high, then the Module invokes HDMI mode. * In this schematic example, the DDI0_AUX_SEL Module input signal is pulled low by R277 and ESD protected by part of ESD diode array D54. * Almost all connections to the DP connector CN52 in the Figure are provided with EMI suppression components (common mode choke elements TR30 through TR34) and ESD protection arrays (D54 through D56). * The EMI and ESD mitigation components used must be appropriate for the high data rates used by the DisplayPort data pairs. * For the ESD diode arrays, this means selecting parts with a sufficiently low pin capacitance. * For the EMI chokes, the selected parts should have a low differential impedance but a relatively high common mode impedance. * It is extremely important that all the nets the DisplayPort data path be routed as differential pairs, preferably against an unbroken GND plane and without any stubs, or with minimal stubs. * Note that the ESD protection arrays used in the example have 2 lands for each net being protected. This is to facilitate no-stub “flow through” routing. * The ESD diode arrays should be positioned next to the DP connector pins. * ESD diode array pins can be pin-swapped if needed to provide a cleaner PCB layout. * DP connector pin 18 is used as a “Hot Plug Detect” signal. The external display drives this signal to a logic high to signal a display hot plug event. This signal is ESD protected by an element of D54 and buffered and level translated by U54 before being passed on to the COM-HPC module. The buffer input is pulled down by R276 in the example, ensuring that the COM-HPC HPD input signal is low if no DP display is present. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 88/159](.picmg-com-hpc-carrier-design-guide-alt/slide-090.jpg) ## Slide 91 ![**Header:** Reference Schematics and Block Diagrams **Body Text:** Some COM-HPC DisplayPort implementations may require a Carrier based redriver. A few industry offerings are listed in Table 16 below. There are of course more parts available on the market. **Table 16: DisplayPort Redrivers and Retimers** Vendor P/N Notes :--- :--- :--- Diodes Inc PI3DPX1203B 4 lane DisplayPort 1.4 redriver; up to 8.1 Gbps link rate PI3DPX8121 DisplayPort 1.4 and 2.0 compatible 2:1 mux and redriver, 2 sets of 4 lane inputs and a 4 lane output, with up to a 10 Gbps link rate. Parade Semiconductor PS8463 DisplayPort 1.4 redriver (8.1 Gbps) HDMI 2.0 redriver (6 Gbps) 4 lanes Texas Instruments DS160PR410 This part is primarily a 4 lane PCIe Gen 4 capable redriver. However, the TI literature states that the part can be used for DisplayPort 2.0 redriver purposes, by setting a certain strap to disable the “PCIe Detect” mode. This is a very high bandwidth part and may work well with all DisplayPort modes. **Body Text (Continued):** There are quite a few USB Type-C and a few USB4 port multiplexers that incorporate redriver and in some cases retimer circuits. Such products come from Diodes Inc., Texas Instruments, and others. The Intel JHL8040R, also known as the “Burnside Bridge”, does DisplayPort, USB and PCIe retiming along with other USB Type-C and Thunderbolt functions. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 89/159](.picmg-com-hpc-carrier-design-guide-alt/slide-091.jpg) ## Slide 92 ![The slide is a schematic diagram titled 'Figure 46: HDMI Over DDI' from section '3.11. HDMI Over DDI' of the 'PICMG® COM-HPC® Carrier Design Guide'. **Header Text:** * 'Reference Schematics and Block Diagrams' * '3.11. HDMI Over DDI' * 'Figure 46: HDMI Over DDI' **Resistor Network (Top Left):** * 'I2C addr = 0x70' * 'R38 0ohms 1% DDIO_A0' * 'R39 0ohms 1% DDIO_A1' * 'R40 0ohms 1% DDIO_A4' * 'R41 0ohms 1% DDIO_PM' * 'R42 0ohms 1% DDIO_DE0' * 'R43 0ohms 1% DDIO_DE1' * 'R45 0ohms 1% DDIO_BST0' * 'R46 0ohms 1% DDIO_BST1' * 'R47 0ohms 1% DDIO_BST2' * 'R48 0ohms 1% DDIO_BST3' * 'R49 0ohms 1%' * 'R50 0ohms 1% DDIO_VOD1' * 'R51 0ohms 1% DDIO_PS0' * 'R52 0ohms 1% DDIO_PS1' * '*HDMI buffer has internal pull ups' **IC U6 (Top Center):** * 'U6' * 'DDIO_A0 22 A0 V_VDD_3 3 +3.3V_S_DDIO' * 'DDIO_A1 18 A1 V_VDD_9 9' * 'DDIO_A4 17 A4 V_VDD_15 15' * 'DDIO_PM 21 PEN V_VDD_24 24' * 'DDIO_DE0 1 DE1 V_VDD_27 27' * 'DDIO_DE1 2 DE0 V_VDD_36 36' * 'DDIO_PAIR0+ 4 A0RX_ 35 HDMI0_PAIR0+' * 'DDIO_PAIR0- 5 A0TX_ 34 HDMI0_PAIR0-' * 'DDIO_PAIR1+ 7 A1RX_ 32 HDMI0_PAIR1+' * 'DDIO_PAIR1- 8 A1RX_ 31 HDMI0_PAIR1-' * 'DDIO_PAIR2+ 10 A2RX_ 29 HDMI0_PAIR2+' * 'DDIO_PAIR2- 11 A2RX_ 28 HDMI0_PAIR2-' * 'DDIO_PAIR3+ 13 A3RX_ 26 HDMI0_CLK+' * 'DDIO_PAIR3- 14 A3RX_ 25 HDMI0_CLK-' * 'HDMI_SCL 19 SCL' * 'HDMI_SDA 18 SDA' * 'DDIO_BST0 39 BST0' * 'DDIO_BST1 40 BST1' * 'DDIO_BST2 41 BST2' * 'DDIO_BST3 42 BST3' * 'DDIO_VOD1 23 VOD1' * 'DDIO_PS0 37 PS0' * 'DDIO_PS1 38 PS1' * 'GND_6 6' * 'GND_12 12' * 'GND_30 30' * 'THMPAD_43 43' * 'PI3IOX1204-B' * '0402' '1%' 'COM' **IC L1 (Middle Left):** * 'L1' * 'HDMI0_PAIR0+ 1 IN_1+ 10 HDMI0_DATA0+ 7' * 'HDMI0_PAIR0- 2 IN_1- 9 HDMI0_DATA0- 8' * 'HDMI0_PAIR1+ 4 IN_2+' * 'HDMI0_PAIR1- 5 IN_2-' * 'HDMI0_PAIR2+ 2 IN_1+' * 'HDMI0_PAIR2- 3 IN_1-' * 'HDMI0_CLK+ 4 IN_2+' * 'HDMI0_CLK- 5 IN_2-' * 'OUT_1+' 'OUT_1-' 'OUT_2+' 'OUT_2-' 'OUT_3+' 'OUT_3-' * 'GND_3' 'GND_8' * 'EMI0402MU1AG' **IC J2 (Middle Right):** * 'J2' * 'TMDS_DATA0+' 'TMDS_DATA0-' 'TMDS_DATA0_SHIELD' 'TMDS_DATA1+' 'TMDS_DATA1-' 'TMDS_DATA1_SHIELD' 'TMDS_DATA2+' 'TMDS_DATA2-' 'TMDS_DATA2_SHIELD' 'TMDS_CLOCK+' 'TMDS_CLOCK-' 'TMDS_CLOCK_SHIELD' 'SCL' 'SDA' 'HOT_PLUG_DETECT/HEC_DATA+' 'CEC' 'RESERVED/HEC_DATA-' 'S1' 'S2' 'S3' 'S4' * 'PCI_10029449-0011CF' * 'V_+5V_POWER 18' * 'DDC0/HEC_GND 17' * '+5.0V_S_DDIO' **Power Supply Section:** * '1812' 'F1' * 'D2' 'PMEG2010AE' * '+5.0V_S' '5.0V_S_FDDIO' '+5.0V_S_DDIO' * 'D1' '+3.3V_S' '+3.3V_S_DDIO' 'PMEG2010AE' * '10uF' '0.1uF' '0.402' '0.16V' '100uF' '16V' '0.1uF' '100V' '0.1uF' '16V' '0.402' '0.16V' '0.402' '0.402' '0.16V' '0.402' '0.16V' '0.402' '0.402' '0.16V' **Bottom Section (I2C Control):** * '*Optional HDMI I2C configuration control' * 'U7' 'XMA2102' * 'V_VCCA' 'V_VCCB' 'A0' 'A1' 'OE' 'GND' 'B0' 'B1' * 'I2C0_CLK' 'I2C0_DAT' '+3.3V_S' '+3.3V_S_DDIO' 'HDMI_SCL' 'HDMI_SDA' 'To Buffer' * 'DDIO_HPD' 'D1' '5' '3' 'D4' 'MMBZ26VB' 'To connector' * 'U8' 'XMA2102' * 'V_VCCA' 'V_VCCB' 'A0' 'A1' 'OE' 'GND' 'B0' 'B1' * 'DDIO_SCL_AUX+' 'DDIO_SDA_AUX-' '+3.3V_S' '+3.3V_S_DDIO' 'HDMI0_SCL' 'HDMI0_SDA' 'To connector' * '0.1uF' '0.402' '1%' '2.86ohms' '1%' '2.86ohms' '10uF' '0.402' '1%' '2.86ohms' '1%' '2.86ohms' * '*Video I2C needs one buffer per port' **Footer:** * 'PICMG® COM-HPC® Carrier Design Guide' * 'Rev. RC2.0d / Dec 7, 2021' * '90/159'](.picmg-com-hpc-carrier-design-guide-alt/slide-092.jpg) ## Slide 93 ![**Reference Schematics and Block Diagrams** **Notes on Figure 46: HDMI Over DDI Above** * COM-HPC DDI signals can generally operate in DP mode or HDMI mode. * COM-HPC input signal DDIx_DDC_AUX_SEL (where x is 0, 1 or 2) selects between DP mode and HDMI mode. * DDIx_DDC_AUX_SEL left open or pulled low selects DP mode for DDIx. * DDIx_DDC_AUX_SEL pulldown driven high to +3.3V_S selects HDMI mode for DDIx. * DP signals are AC coupled * DP data pairs are AC coupled on the Carrier near the DP connectors, as can be seen in Figure 45: DisplayPort Over DDI above. * DP AUX_SEL pairs are AC coupled on the COM-HPC Module (nets DDIx_SDA_AUX+ and – in Figure 45). * HDMI signals are generally DC coupled – at least from the HDMI / TMDS driver outputs, across the HDMI cable and on to the HDMI / TMDS receiver. DC coupling is shown for the HDMI / TMDS data pairs and the SDA / SCL setup lines in Figure 46 above. * Figure 46 uses a Diodes Inc / Pericom PI3HDX1204B combination HDMI level translator and redriver (U6 in the Figure). * This part can be configured by resistor straps or over I2C. Both options are shown in the Figure. * Components L1 and L2 are On Semiconductor EMI8042MUT offering combined ESD protection and EMI suppression. * Note that the +3.3V level DDIx_SDA_AUX+ and – HDMI setup signals are translated to a +5V level with component U8. ESD protection is included for all signals facing the outside world. * There are many alternative HDMI level translators on the market. * Texas Instruments, Analog Devices, Silicon Labs, Diodes Inc. and others offer HDMI level translators, redrivers and retimers. * Many devices have built in ESD protection and level translation for the HDMI data pairs and the SDA / SCL setup channel. * See Texas Instruments TPD12S016 for a basic HDMI level translator with integrated ESD protection. * Some HDMI redrivers / retimers use AC coupling at their inputs, and DC coupling to the cable at their outputs. See, for example, Texas Instruments TDP158. * There may be licensing fees involved if HDMI implementations are used, and strict rules about logo use. Check with the HDMI organization (www.hdmi.org). PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 91/159](.picmg-com-hpc-carrier-design-guide-alt/slide-093.jpg) ## Slide 94 ![**Header & Title:** Reference Schematics and Block Diagrams 3.12. eDP Figure 47: eDP Schematic Example **Top Schematic Section:** * **Top Right Connector:** CN42, L-PEX 20455-040E. Pin numbers 1-40 are visible. Signal labels include VDISP_BKLT, eDP_VDD_EN, EDPHPD, VDISP_VDD. * **Component U66:** 74AUP1T97L6X. Pins: 3 (COM), 4 (A/B), 5 (VCC/Y), 1 (A/B), 2 (GND). Connected to +3.3V_S and BKLT_CTRL. Capacitor C664 (100n 25V 0402), Resistor R566 (100K 0402). Signal: eDP_BKLT_CTRL. * **Component U52:** NC7WZ16P6X. Pins: 6 (Y1/A1), 5 (VCC), 4 (Y2/A2), 3 (GND), 2 (GND), 1 (GND). Connected to +3.3V_S. Capacitor C361 (25V 100n 0402), Resistor R291 (0402 100K). Signal: eDP_HPD. * **Left Side Signals (eDP Signals):** eDP_AUX-, eDP_AUX+, eDP_TX0-, eDP_TX0+, eDP_TX1-, eDP_TX1+, eDP_TX2-, eDP_TX2+, eDP_TX3-, eDP_TX3+. * **Left Side Components:** Capacitors C1654, C1655, C1651, C1650, C1653, C1652, C1657, C1656, C1659, C1658. Text: '10x 0402 25V 100n'. * **Middle Traces:** EXT_EDP_AUX_DN, EXT_EDP_AUX_DP, EXT_EDP_TXP0, EXT_EDP_TXN0, EXT_EDP_TXP1, EXT_EDP_TXN1, EXT_EDP_TXP2, EXT_EDP_TXN2, EXT_EDP_TXP3, EXT_EDP_TXN3. * **Inductors/TRs:** DLP11TB800UL2L TR1, TR2, TR3, TR4, TR5. * **Right Side Filtered Signals:** EXT_EDP_AUX_DN_Filt, EXT_EDP_AUX_DP_Filt, EXT_EDP_TXP0_Filt, EXT_EDP_TXN0_Filt, EXT_EDP_TXP1_Filt, EXT_EDP_TXN1_Filt, EXT_EDP_TXP2_Filt, EXT_EDP_TXN2_Filt, EXT_EDP_TXP3_Filt, EXT_EDP_TXN3_Filt. * **Bottom Right:** R300 0 0603, C4, G3. * **Connector Diagram:** Labeled 'PIN 1'. **Middle Section:** * **Note Box:** 'NOTE:', 'To use with straight eDP cables'. * **Connector Diagram:** CN1:L-PEX 20453-040T-G1, CN2:L-PEX 20453-040T-G1. * **Connection Chart:** Table with headers CN1 and CN2, columns 1-40. **Bottom Schematic Section:** * **Panel Backlight Voltage Selection:** 'PANEL BACKLIGHT VOLTAGE SELECTION', 'Set 1-2: 12V', 'Set 2-3: 5V (Default)'. * Component JP12 (2211S-03G): Pins 1 (+12V_S), 2 (V_BKLT), 3. * Component P12 (228CG). * Component U67 (NCP45521MNTWG-H): Pins 1 (VIN), 9 (VIN), 7 (VOUT), 8 (VOUT), 5 (BLEED), 4 (GND), 6 (PG/SR), 2 (EN), VCC. * Signals: +3.3V_A, VDISP_BKLT, eDP_BKLT_EN. * Components: C666 (100n 0402 25V), C668 (100n 25V 0402), R568 (100K 0402), R567 (1K 0402), C669 (100n 25V 0402), F12 (0402 50V C670 minSMDC150F/24-2). * VDISP_BKLT Capacitors: C341, C342, C343, C344, C345 (22u 25V 0805, 100n 25V 0402). * **Panel VDD Voltage Selection:** 'PANEL VDD VOLTAGE SELECTION', 'Set 1-2: 5V', 'Set 2-3: 3.3V (Default)'. * Component JP13 (2211S-03G): Pins 1 (+5V_S), 2 (V_VDD), 3 (+3.3V_S). * Component P13 (228CG). * Component U69 (NCP45521MNTWG-H): Pins 1 (VIN), 9 (VIN), 7 (VOUT), 8 (VOUT), 5 (BLEED), 4 (GND), 6 (PG/SR), 2 (EN), VCC. * Signals: +3.3V_A, VDISP_VDD, eDP_VDD_EN. * Components: C674 (100n 0402 25V), C678 (100n 25V 0402), C680 (100n 25V 0402), R570 (100K 0402), R569 (403 0402), C677 (100n 25V 0402), F13 (0402 50V C678 microSMD150F-2). * VDISP_VDD Capacitors: C346, C347, C350, C348, C349 (22u 25V 0805, 100n 25V 0402). **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 92/159](.picmg-com-hpc-carrier-design-guide-alt/slide-094.jpg) ## Slide 95 ![**Header:** Reference Schematics and Block Diagrams **Figure 48:** eDP Connector Pin Numbering **Top Diagram:** A row of pins numbered 1 to 40. Text inside the box reads: 'I-PEX 20455-040E Pin Numbering'. An arrow pointing upward is labeled 'Cable Entry'. **Bottom Diagram:** A row of pins numbered 40 to 1. Text inside the box reads: 'VESA and Display Vendor Pin Numbering'. An arrow pointing upward is labeled 'Cable Entry'. **Body Text:** The connector used for most eDP implementations is the I-PEX 20455-040E or equivalent. There can be some confusion about the pin numbering used in eDP systems. The connector vendor defines pin 1 at the left, as shown in the upper part of Figure 48 above. For reasons perhaps better lost to history, VESA and hence the eDP display vendors put pin 1 at the right side of the connector, as illustrated in the lower portion of the Figure, in spite of the datum mark at the left end of the connector. The eDP schematic sample in Figure 47 above uses the I-PEX pin numbering (as PCB designers generally prefer to follow the component vendor’s data sheet when making up PCB footprints). The net result here is that I-PEX pin 1 needs to map to VESA / Display pin 40, I-PEX pin 2 to VESA / Display pin 39 and so on. This happens with the straight through cable shown in Figure 47 above (which uses the I-PEX pin numbering on both ends of the cable). This cable works between a COM-HPC Carrier and a VESA eDP display (which uses the VESA pin order). Display cables for eDP typically use micro-coax wiring. The + and – conductors of an eDP data pair travel in separate but adjacent coax lines. Hence they are not electromagnetically coupled within the cable assembly, but since each conductor is completely shielded and are equal length, the differential transmission properties are preserved and this works very well even at the highest eDP data rates. The PCB traces on the Carrier and within the display assembly should be edge coupled differential pairs, as per usual. **Section Header:** Additional eDP Example Material **Final Paragraph:** An alternative eDP example implementation is presented in Section 6.2, Appendix B: Alternative eDP Exam-ple near the end of this document. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 93/159](.picmg-com-hpc-carrier-design-guide-alt/slide-095.jpg) ## Slide 96 ![Reference Schematics and Block Diagrams 3.12.1. eDP / DP Conversions to Other Video Formats There are a number of video format conversion bridges available from NXP (www.nxp.com), Chrontel (www.chrontel.com) and others. These products allow conversion from eDP or DP to LVDS, analog VGA , HDMI, DVI and a host of older video formats such as CVBS, S-Video, BT656, BT1120, YPbPr etc. LVDS displays are not directly supported by COM-HPC. However conversion from an eDP or DP source (from COM-HPC) to LVDS input format displays is easily achieved using either the NXP PTN3460 (PT-N3460I for the industrial temperature version) or the Chrontel CH7515. All common LVDS formats (single channel, dual channel, 16 / 18 / 24 bit color depths) are supported by these NXP and Chrontel parts. COM-Express Modules from several vendors routinely use the NXP PTN3460I behind the scenes to produce the COM-Express LVDS outputs from the chipset eDP channel. It may be wise to check with your Module vendor before selecting an eDP / DP conversion part, as the vendor may have a preference and have software / firmware support favoring a particular part. Some subtleties such as VESA EDID support, backlight control etc. may be easier using the video conversion part(s) supported by the COM-HPC Module vendor. Analog VGA support is still important in some limited markets. The NXP PTN3355 and the Chrontel CH7517 are popular parts for this task. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 94/159](.picmg-com-hpc-carrier-design-guide-alt/slide-096.jpg) ## Slide 97 ![**Header and Titles:** Reference Schematics and Block Diagrams 3.13. MIPI-CSI Camera Interface Figure 49: MIPI-CSI **Schematic Content:** * **Connector (Top):** CN1, FPC/FFC_22, Molex/525592253. Pins labeled 1-22. * **Left Side Signals/Components:** CSIO_RX0-, COM, R1 0ohm, CSIO_RX1+, COM, R2 0ohm, CSIO_CLK-, COM, R5 0ohm, CSIO_RX2+, COM, R8 0ohm, CSIO_RX3-, COM, R9 0ohm, CSIO_RST#_3V, R12 0ohm, CSIO_I2C_CLK_3V, +3.3V_S, R13 0ohm, C1 0.1uF_10V, G3, G1. * **Right Side Signals/Components:** R3 0ohm, CSIO_RX0+, COM, R4 0ohm, CSIO_RX1-, R6 0ohm, CSIO_CLK+, COM, R7 0ohm, CSIO_RX2-, R10 0ohm, CSIO_RX3+, COM, R11 0ohm, CSIO_ENA_3V, CSIO_MCLK_3V, CSIO_I2C_DAT_3V, G4, G2. * **Logic/Conversion (Middle/Bottom):** * **U2:** TXS0108EPWR_TI. Pins: VCCA, VCCB, A1-A8, B1-B8, OE, GND. Signals: +1.8V_S, +3.3V_S, CSIO_ENA, CSIO_RST#, CSIO_I2C_CLK, CSIO_I2C_DAT. Capacitors: C4 1uF_6.3V, C5 1uF_6.3V. * **U1:** TCA9517ADGKR_VSSOP8. Pins: VCCA, VCCB, SCL_A, SCL_B, SDA_A, SDA_B, GND, EN. Components: C2 1uF_6.3V, C3 1uF_6.3V, +1.8V_S, +3.3V_S, R14 2.2K +1%, R15 2.2K +1%. * **U3:** 74LVC1G125_SOT23-5. Pins: OE, A, Y, Gnd. Signals: CSIO_MCLK, COM, R16 0ohm, NI, R1 1k NI, CSIO_MCLK_3V, R18 0ohm_+-1%. Capacitor: +3.3V_S. **Body Text:** A typical Carrier board MIPI-CSI implementation is shown in Figure 49 above. There is no standard connector for MIPI-CSI use. The Molex part shown in the Figure above is a reasonable choice but many others are used in various situations. The example above distributes +3.3V_S power to the camera, appropriate for many camera assemblies. However, many MIPI cameras are 1.8V devices, and the COM-HPC MIPI-CSI is defined as a 1.8V interface in the COM-HPC Base Specification document. Camera and support software selection is an important part of implementing a MIPI-CSI system. The cameras have particular data formats and non-linear data compensation requirements to account for camera characteristics. It is important to have a software driver plan that aligns with the camera choice and the Module chipset or SOC choice. There may well be NRE charges from the Module vendor to get a MIPI-CSI camera solution working, unless the vendor has a “canned” solution to offer. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 95/159](.picmg-com-hpc-carrier-design-guide-alt/slide-097.jpg) ## Slide 98 ![Reference Schematics and Block Diagrams **3.14. Audio Interfaces** **3.14.1. General Discussion** The COM-HPC Client Module pin-out allows for up to four SoundWire audio ports and one I2S audio port. No audio support at all is offered on the COM-HPC Server Module pin-out. The first two COM-HPC Client Mode SoundWire ports, numbered as 0 and 1, are free and clear and are not shared. Port 0 and Port 1 are two pins each, with CLK and DAT lines. The 3rd and 4th COM-HPC SoundWire ports, numbered as 2 and 3, are pin shared with an I2S audio port. No Intel HD Audio support at all is offered with COM-HPC revision 1.0. However it is to be offered in COM-HPC Base Specification revision 1.1 due to some delays in the industry SoundWire rollout. SoundWire is expected to be the mainstream x86 system audio interface going forward. I2S audio interfaces are also available on many contemporary x86 chipsets. I2S is the most popular audio interface on ARM designs at the time of this writing. This may shift to SoundWire over time. **3.14.2. MIPI SoundWire Summary** * A 2 wire interface (CLK and DAT) is used. * For most implementations there is a single Master and there may be multiple Slaves * The CLK is an output from the Master * DAT is bidirectional signal, with data to and from Slaves * The Master controls the DAT line direction, per MIPI SoundWire protocol * The SoundWire CLK and DAT lines may be run at 1.8V or 1.2V (per the MIPI specification) * COM-HPC uses 1.8V SoundWire signaling * This signaling should be available in all system states, S5 through S0 * There may be up to 11 Slave devices on a SoundWire bus * It is more common to have up to 4 Slave devices on a single SoundWire bus * There is a MIPI defined enumeration process to identify the Slaves * It involves a bit of trial and error but in time all Slaves are identified * Some details on SoundWire clocking and signaling include: * The CLK frequency used is set by the Master, and may be as high as 12.288 MHz * The lowest appropriate frequency is used * DDR (Double Data Rate) signaling is used (meaning that data is clocked on the rising CLK edge and the next bit on the falling CLK edge) * The CLK frequency may be slowed or completely stopped by the Master, as required * These clocking / data features allow lower power operation * SoundWire uses a “modified” NRZI (Non Return to Zero Inverted) protocol on the data line * This allows the enumeration capability and other features described in the MIPI specification * Audio data may be encoded in several formats: * PCM (Pulse Code Modulation) – the most common format * PDM (Pulse Density Modulation) – has low hardware implementation overhead and is useful for simple devices such as digital microphones * Bulk Mode – for large data blocks * Slaves may initiate in-band interrupts and wake events * I2C support for SoundWire devices is generally not needed (unlike for I2S) PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 96/159](.picmg-com-hpc-carrier-design-guide-alt/slide-098.jpg) ## Slide 99 ![Reference Schematics and Block Diagrams MIPI Slave devices may be wired together either in daisy-chain fashion or in a branched – tree topology, as shown in Figure 50 on the next page. In either case, the SoundWire CLK and DAT lines should be routed together – not as a differential pair, but as a signal pair following approximately the same route paths, with approximate length matching all along the paths and for each branch, so that the signal flight time from Master to Slave for both the SoundWire CLK and DAT are about the same. If the balanced tree topology is used, the length of branches of the tree should be about the same. Chipset design guide examples tend to show point to point SoundWire implementations with signal integrity measures. These include series damping resistors and snubbing capacitors, as depicted in Figure 51 below, The component values are design and layout dependent and may range from 0 to about 22 ohms for the series resistors and from 0 (i.e. not loaded) to about 22 pf for the capacitors. The MIPI Master – to Slave implementation is straightforward, as it only involves the CLK and DAT lines. There are sure to be many more CODEC or MIPI Slave device implementation details – such as filtered analog power supplies, decoupling and other component recommendations, analog layout recommendations etc., not covered here. This information is available from the CODEC and Slave device vendors. Table 17: SoundWire Audio CODECs Vendor Vendor P/N Notes :--- :--- :--- Cirrus Logic CS42L42 SoundWire and I2S Audio CODEC – data freely available on the web Realtek ALC711-VD SoundWire and I2S Audio CODEC – data restricted at time of this writing There are quite a few SoundWire Slave devices available, such as microphones and amplifiers, that are simpler than full CODECs. Vendors include Analog Devices, Maxim Integrated Products, TDK, Texas Instruments and more. From a hardware compatibility view, these low end devices may be tied directly to one of the COM-HPC SoundWire ports – but be sure to check out the software support situation before putting hardware together. The reference designs from some x86 SOC and chipset vendors show SoundWire device implementations grouped into functions. For example, the first SOC or chipset SoundWire bus may host two or more output amplifiers, the second SoundWire bus an audio CODEC, and the third Soundwire bus hosts an array of SoundWire microphones. Check with your COM-HPC Module vendor to see if they have any specific SoundWire device recommendations and port mapping recommendations. **Intel SoundWire Sample Schematics and Design Guide** Sample SoundWire implementations may be found in some Intel reference schematics. See, for example, NDA protected Intel document numbers 627073 and 627205. Intel NDA protected document number 627205 devotes several pages to SoundWire design They basically show a “balanced tree” with two branches of approximately equal length, and with two SoundWire loads. An alternative daisy chain arrangement with up to four loads is described as well. Also recommended are some optional series damping resistors. In the COM-HPC case, the optional damping resistors would be placed in the SoundWire clock and data lines near the COM-HPC connector. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 97/159](.picmg-com-hpc-carrier-design-guide-alt/slide-099.jpg) ## Slide 100 ![**Header:** Reference Schematics and Block Diagrams **Figure 50: MIPI SoundWire Routing Topologies** * **Top Section (Daisy Chain Topology):** A 'COM-HPC Connector' labeled with 'SNDW_DMIC_DAT0' and 'SNDW_DMIC_CLK0' connects via lines labeled 'Daisy Chain Topology' to four stacked blocks labeled 'SoundWire Slave.' Each slave block contains 'SNDW_DAT' and 'SNDW_CLK' and is accompanied by a speaker and musical note icon. * **Bottom Section (Balanced Tree Topology):** The same 'COM-HPC Connector' block continues with labels 'SNDW_DMIC_DAT1' and 'SNDW_DMIC_CLK1.' Lines labeled 'Balanced Tree Topology' connect to two stacked blocks labeled 'SoundWire Slave,' each containing 'SNDW_DAT' and 'SNDW_CLK' and accompanied by speaker and musical note icons. **Figure 51: MIPI SoundWire Point to Point Connection With SI Components** * A 'COM-HPC Connector' on the left lists 'SNDW_DMIC_DAT0' and 'SNDW_DMIC_CLK0.' * A 'SoundWire CODEC' on the right lists 'SNDW_DAT' and 'SNDW_CLK' and is accompanied by speaker and musical note icons. * **Connections:** * The top line connects 'SNDW_DMIC_DAT0' to 'SNDW_DAT' via capacitors 'C1' and 'C2' (grounded) and resistors 'R1' and 'R2' (series). * The bottom line connects 'SNDW_DMIC_CLK0' to 'SNDW_CLK' via capacitors 'C3' and 'C4' (grounded) and resistors 'R3' and 'R4' (series). **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 98/159](.picmg-com-hpc-carrier-design-guide-alt/slide-100.jpg) ## Slide 101 ![**Header:** Reference Schematics and Block Diagrams **Title:** 3.14.3. I2S Implementations on COM-HPC **Content:** * **Availability & References:** No specific COM-HPC I2S audio example is available yet. References the **SMARC Design Guide** for two CODEC examples: * Cirrus Logic WM8904 Ultra Low Power CODEC * Texas Instruments TLV320AIC3105 Low Power CODEC * **SMARC vs. COM-HPC:** SMARC defines two I2S ports versus COM-HPC's single port. Definitions are similar: * '1.8V logic level signaling.' * 'S0 power domain operation.' * Same signal definitions (despite pin name mismatches): * 'An I2S clock out pin from the Module to a Carrier Slave.' * 'An I2S data out pin defined.' * 'An I2S data in pin defined.' * 'An I2S Left – Right audio channel clock output pin defined.' * 'An I2S audio master clock output defined.' * **I2C Interface Requirements:** I2S implementations generally need a 'companion I2C interface'. The COM-HPC I2S interface is '1.8V', requiring a matching 1.8V I2C interface. * 'The COM-HPC I2C1 interface is defined to be a 1.8V interface; the COM-HPC I2C0 is a 3.3V interface.' * 'Of course level translation can be implemented.' * **Intel Reference:** 'Intel NDA protected document 616553' shows an 'Elkhart Lake' (an 'Atom class SOC') schematic. While unlikely for COM-HPC, it is useful for designers. * **SoundWire Alternative:** 'SoundWire does not require a companion I2C interface. Just the SoundWire Clock and Data lines are sufficient for both audio data and SoundWire slave register setup.' **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 99/159](.picmg-com-hpc-carrier-design-guide-alt/slide-101.jpg) ## Slide 102 ![Reference Schematics and Block Diagrams **3.15. Asynchronous Serial Port Interfaces** **3.15.1. COM-HPC UART Interfaces** Two 3.3V logic level asynchronous serial ports, designated UART0 and UART1 are defined by COM-HPC. Each port has TX and RX signals for data use and RTS# and CTS# signals for optional handshake / flow control use. For logic level use, the TX and RX signals are active high and the RTS# and CTS# signals are active low. Some data sheets omit the trailing '#' signal but the logic level handshake signals are active low nonetheless. The idle state, or 'mark' state, of the logic level TX line is high, or 3.3V in the COM-HPC case. These ports may be used directly as logic level asynchronous serial connections between COM-HPC Module and Carrier based devices, or between COM-HPC Module and Carrier based mezzanine devices such as certain Mini-PCIe or M.2 cards. Care has to be taken that the logic I/O levels match up. Note, for example, the (unused) UART connections on the left side of the M.2 E-Key card shown in Figure 14 above. The PCI-SIG M.2 specification defines the E-Key UART pins to be 1.8V signals so some non-inverting level translation would be needed in this case: 3.3V to 1.8V on the TX and RTS# lines leaving the COM-HPC Module, and 1.8V to 3.3V translation for the RX and CTS# lines coming into the COM-HPC Module. Dozens of suitable logic level translation products are available on the market. One such product is the Texas Instruments SN74LV1T125. For off-board, cabled connections, the logic level UART signals are usually translated into one of three common formats: RS-232, RS-422 or RS-485. RS-232 is a single ended format in which the 'mark' or 'idle' or 'logic 1' state is a negative voltage between -3V and -25V, and the 'space' or 'logic 0' state is a positive voltage between +3V and +25V. An RS-232 level translation implementation for UART0 and UART1 is shown in Figure 52 below. This example uses a pair of Maxim (Texas Instruments) MAX3243E level translators. These parts have built in capacitor based charge pumps that create RS-232 compliant voltage levels and avoid the need to distribute a negative voltage on the Carrier. Note that the signal polarities are inverted by the device. This particular Maxim device has built-in +/-15 kV air gap and +/-8 kV contact ESD discharge survivability. There are many similar devices from Texas Instruments, Analog Devices / Linear Technology, Diodes Inc. and others. The cable length that can be achieved with RS-232 interfaces depends on the data rate used. Generally, RS-232 cables lengths are limited to about 50 feet or less. RS-232 signals are most often used with D subminiature DB-9 or DB-25connectors. The RS-232 standard defines DTE (Data Terminal Equipment) and DCE (Data Communications Equipment) connector pin-outs. A DTE chassis connector is a male connector, and a DCE chassis connector is female. The DTE and DCE pinouts are defined such that a straight cable (pin 1 to pin 1, pin 2 to pin2 etc. on the cable) may be used. With the straight cable, the DTE TX pin (or TX# pin if using that notation) lands on the DCE RX(or RX#) pin, and so on. For longer cable lengths, on the order of 1000 feet or more , differential signaling formats such as RS-422 or RS-485 are often used. These implementations are usually terminated in the twisted pair cable impedance at the receiving endpoints. Many suitable parts are available from Analog Devices / Linear Technology, Texas Instruments and others. These vendors offer very informative Application Notes. They also offer “multi-protocol” devices – devices that can handle RS-232, RS-422 and / or RS-485 hardware protocols. Some of these devices have switchable internal cable termination. Some products from these vendors offer galvanic isolation. The RTS# handshake line is often used in RS-485 implementations as a transceiver enable line. This of course needs appropriate software support. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 100/159](.picmg-com-hpc-carrier-design-guide-alt/slide-102.jpg) ## Slide 103 ![This slide from the 'PICMG® COM-HPC® Carrier Design Guide' (Rev. RC2.0d / Dec 7, 2021) contains a schematic diagram and text regarding UART compatibility. **Figure 52:** 'UART0 and UART1 RS-232 Level Translated Asynchronous Serial Ports' The schematic displays two MAX3243E chips (U1 and U2) used for translating UART signals to RS-232 levels. * **Top Section (UART0):** Shows connections for UART0_TX, UART0_RTS#, UART0_CTS#, and UART0_RX. These connect to a KYCON_K42X-E9P-P-A4N connector (J1). * **Bottom Section (UART1):** Shows similar connections for UART1_TX, UART1_RTS#, UART1_CTS#, and UART1_RX. These also connect to a KYCON_K42X-E9P-P-A4N connector (J1). * **Annotation:** Red text states, 'Pinouts of DB9 are configured as DTE ports'. **3.15.2. Legacy Compatibility With 16C550 UART Register Set** The text explains that the National Semiconductor (now Texas Instruments) 16550 or 16C550 UART is the 'defacto standard defined at the dawn of the personal computer age.' * It notes that many BIOSes support 16C550 operations for early boot functions like console redirect and Port 80 debug codes. * It states: 'The COM-HPC Base Specification encourages but does not require 16C550 register compatibility for the UART0 and UART1 ports. Check with your Module vendor.' * The final sentence reads: 'Once the operating system is running and drivers are loaded, 16C550 compatibility is a non-issue, but for early boot support it is valuable.'](.picmg-com-hpc-carrier-design-guide-alt/slide-103.jpg) ## Slide 104 ![Reference Schematics and Block Diagrams **3.15.3. Alternative / Additional Carrier Board UART Implementations** If additional or perhaps higher performance UARTs beyond what the COM-HPC Module provides are needed, there are a number of excellent options available. A few of these are summarized in the Table below.. **Table 18: Alternative / Additional Carrier Board UART Implementations** Vendor Interface Sample Vendor P/Ns 16C550 Compatible ? Features / Notes :--- :--- :--- :--- :--- FTDI USB 2.0 FS FT232RUSB No Future Technology Devices Inc Web www.FTDIchip.com Several similar parts available Win 10 and Linux drivers MaxLinear (Exar) USB 2.0 FS XR21V1410 XR21B1420 No Web www.maxlinear.com MaxLinear (Exar) PCIe x1 Gen 2 XR17V352 XR17V354 XR17V358 Yes Web www.maxlinear.com Dual, Quad and Octal parts Very deep FIFOs, high bit rates Native Windows and Linux support Vendor drivers also available RS485 support Microchip USB 2.0 FS MCP2220 No Web www.microchip.com PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 102/159](.picmg-com-hpc-carrier-design-guide-alt/slide-104.jpg) ## Slide 105 ![Reference Schematics and Block Diagrams **3.16. I2C / I3C Ports** The COM-HPC pin-out definition supports a traditional I2C port, designated I2C0, and a second port designated I2C1, targeting (optional) MIPI I3C use along with with backward compatibility to traditional I2C.The I2C0 port runs at 3.3V and I2C1 at 1.8V. Both are active in suspend and full-on power states. I2C is an abbreviation for 'Inter Integrated Circuit'. It was defined by Philips (and later inherited by NXP) as an easy to use two wire method for a Master device to set and read back Slave peripheral IC registers and data values. It uses, in it's basic form, open-drain drivers and passive pull-ups. The current NXP specification document is freely available (see reference in Section 1.9) and defines several modes of operation, summarized in the following Table: **Table 19: I2C Operating Modes** I2C Mode Operating Frequency Max Rise Time Max Bus Capacitance Notes :--- :--- :--- :--- :--- Standard 100 KHz 1000 nsec 400 pF Fast 400 KHz 300 nsec 200 pF (passive pull-up) 400 pF (active pull-up) See NXP UM10204 Section 5.2 Fast Plus 1 MHz 120 nsec 550 pF (active pull-up) High Speed 3.4 MHz 3 Mbps throughput Not described in NXP UM10204 Referenced in some literature including Intel The COM-HPC Base Specification V1.0 document recommends a 2.2K ohm on-Module pull-up on the I2C0 and I2C1 Clock and Data lines. This value is sufficient for all Standard Mode (100 Khz) situations as the RC time constant is 880 nsec (= 2.2K * 400 pF) in the worst case, under 1000 nsec. In most situations, the I2C bus capacitance is much lower than 400 pF: * Typical IC pin capacitances are 6 to 8 pF * A typical PCB trace capacitance is 4 pF / inch – this varies with stackup details * If, for example, there are 10 devices on the bus and there is a 20 inch total trace length, the bus capacitance would be about 160 pF (= 8 pF * 10 + 4 pF / inch * 20 inch) * This rough calculation includes both the Module and Carrier I2C devices and trace lengths, with about 5 inches assumed on the Module. The 2.2K Module pull-up is not sufficient for the worst case Fast Mode (400 Khz) passive mode bus capacitance of 200 pF. The 2.2K value handles up to about 100 pF of bus capacitance. A 2nd, parallel set of 2.2K pull-ups on the Carrier I2C Clock and Data lines would be advisable if the bus loading is over 100 pF. The Carrier pull-ups can always be left unpopulated if they are not needed. There are various application notes on this subject available on-line. See, for example, Texas Instruments document SLVA689 titled “I2C Bus Pullup Resistor Calculation”. The Module design may include active circuitry to better support I2C Fast Mode and to support Fast Mode Plus. Check with the Module documentation or with the Module vendor. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 103/159](.picmg-com-hpc-carrier-design-guide-alt/slide-105.jpg) ## Slide 106 ![**Reference Schematics and Block Diagrams** **3.16.1. I2C Addressing** I2C uses a 7 bit addressing scheme to differentiate I2C resources. The address lines are designated A6 ... A0, but they are part of an 8 bit frame, in bit positions 7 through 1. Bit position 0 is used in the I2C device address to designate whether the current operation is a Read (a logic '1') or a Write (a logic '0'). Thus I2C addresses can be described in either 7 bit or 8 bit formats. If using the 8 bit format to describe I2C addresses, the R/W bit is always assumed to be '0'. The 8 bit frame is transmitted MS bit first. The 4 most significant bits in the 7 bit I2C address field are used to define I2C device categories that are fixed by the I2C specification. The 3 least significant bits allow up to 8 devices within an I2C category to be identified by the I2C silicon vendor and / or the user. There are usually pin straps or specific product SKUs that define the 3 bit LS bit addresses. It is useful to put together a table of I2C devices and addresses used in a design on both the Module and the Carrier, to ensure that there are no conflicts and to provide the information to software engineers. The Module vendor should provide such a list for I2C devices on the Module that are exposed / accessible on the COM-HPC I2C0 and I2C1 buses. Two I2C memory devices for COM-HPC use, at specific I2C0 addresses, are designated in the COM-HPC Base Specification, Version 1.0, Section 5.2 : * A Module EEPROM device at hexadecimal address 0x50 (7 bit I2C addressing) or 0xA0 (8 bit addressing) * A Carrier EEPROM device at hex address 0x57 (7 bit addressing) or 0xAE (8 bit addressing) The Module and Carrier EEPROM data structures and contents are described in the PICMG documents *EeEP for COM-HPC (Embedded EEPROM for COM-HPC)* and the *PICMG COM-HPC Platform Management Interface Specification*. **Figure 53: I2C0 Example: Carrier EEPROM in S5 Power Domain** (Diagram Labels) * +3.3V_A * DNI (appearing 4 times vertically) * R1, R2, R3, R4 * I2C0_CLK * COM (box) * I2C0_DAT * COM (box) * GPIO_00 * COM (box) * R9 * DNI * U2 * SCL (pin 6) * SDA (pin 5) * WP (pin 7) * A2 (pin 3) * A1 (pin 2) * A0 (pin 1) * VCC (pin 8) * +3.3V_A * C1 100 nF * GND (pin 4) * Microchip / Atmel AT24C32 (32 Kbit) AT24C64 (64 Kbit) * R5, 4.7K * R6, 4.7K * R7, 4.7K * R8, 4.7K **Footer** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 104/159](.picmg-com-hpc-carrier-design-guide-alt/slide-106.jpg) ## Slide 107 ![**Reference Schematics and Block Diagrams** **3.16.2. I2C0 Example: Carrier I2C Device in S0 Power Domain** The COM-HPC I2C0 port is a basic 3.3V I2C port active in all power states (S5 through S0). It is a three wire port with CLK, DAT and ALERT# pins. The ALERT# pin, if supported by the COM-HPC Module, can serve as an interrupt input to the Module. An implementation example is given in Figure 54 below. In this example, a temperature sensor that is in the S0 power domain (+3.3V_S power net) is connected to the S5 domain COM-HPC Module I2C0 port through isolation FETs T2, T3 and T4. These FETs serve to prevent the S5 power domain I2C0 port from being dragged down when the +3.3V_S power rail is absent. I2C0 bus pull-up resistors to the +3.3V_A (Always on) power rail are on the COM-HPC Module. Secondary pull-ups to the +3.3V_S (Switched) power rail are shown in the Figure below. The ALERT# pin on the IC shown in the Figure is asserted by the LM75B device when a temperature threshold that had been previously set using the I2C0 interface is crossed. The I2C address of the LM75B device is set at 0x90 (8 bit addressing). The lower 3 bits of the LM75B I2C address are set by the A2, A1, A0 pin straps. Up to 7 additional devices could be deployed by setting different addresses options on these pin straps. **Figure 54: I2C0 Example: Carrier Temperature Sensor in S0 Power Domain** (Diagram Text) +3.3V_S T4 2N7002T R542 4k7 0402 I2C0_DAT COM 3 2 I2C0_DAT_S0 +3.3V_S T2 2N7002T R540 4k7 0402 I2C0_CLK COM 3 2 I2C0_CLK_S0 +3.3V_S T3 2N7002T R541 10k0 0402 I2C0_ALERT# COM 3 2 I2C0_ALERT#_S0 U64 1 SDA 2 SCL 3 OS 5 A2 6 A1 7 A0 8 VCC 4 GND LM75B I2C addr: 0x90 +3.3V_S C713 100n 0402 25V **3.16.3. I2C Bus Buffers / Level Translators** There are a number of bus buffers and level translators that target I2C and SMBus situations. Some suggested vendors and parts to consider are listed in Table 20 below. These parts allow for power domain isolation as the I/O pins go into a high impedance mode if one or both of power rails collapse. **Table 20: I2C Bus Buffers / Level Translators / Power Domain Isolation** Vendor Part Notes --- --- --- Texas Instruments TCA9517 An upgrade and replacement for the popular NXP PCA9517 On Semiconductor FXMA2102 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 105/159](.picmg-com-hpc-carrier-design-guide-alt/slide-107.jpg) ## Slide 108 ![Reference Schematics and Block Diagrams **3.16.4. I2C1 (COM-HPC) and Optional I3C Support** The COM-HPC Base Specification defines a second I2C port, designated I2C1. This port is a 2 wire port (clock and data; no ALERT#) that operates from the 1.8V S5 and S0 power rails. The COM-HPC specification states that this port supports I2C and optionally supports I3C operation. I3C is mostly backward compatible with I2C but there are some caveats and differences, summarized in the section just below. If the user “just” wants an additional I2C port, than the I2C / I3C differences are not important and the user may proceed with a traditional I2C implementation, bearing in mind the 1.8V operating voltage and the S5 / S0 power domain. If combined I3C / I2C operation is expected, then the material presented just below is important. **MIPI I3C Discussion** The MIPI Alliance has defined a significant enhancement to traditional I2C, known as I3C, an acronym for “Improved Inter Integrated Circuit” communication. I3C is significantly faster than I2C, and has some notable feature improvements, summarized below. It is largely, but not completely, backward compatible with I2C, also noted below. Recall that I2C is a 2 wire interface (with an optional 3rd wire for an ALERT# input) that operates in most cases as a 100 KHz or 400 KHz interface, with some 1 MHz and 3.4 MHz implementations. I3C enhancements beyond I2C include: * 12.5 Mbps SDR (Standard Data Rate) operation using a 12.5 MHz clock * 25 Mbps DDR (Double Data Rate) operation (12.5 MHz clock, using rising and falling clock edges) * 33.3 Mbps Ternary Encoding operation (too complicated to explain here; see the MIPI documentation) * Higher bandwidth and lower power operation * Active pull-ups rather than passive pull-ups increase speed and lower power consumption * In – band interrupts (ALERT# pin not needed) – 2 wire operation only * Error detection * Error correction, in the Ternary mode * Dynamic addressing * Hot – Join operation (devices may be powered down and rejoin at power up; not same as Hot-Plug) However, there are some issues with complete backward compatibility between I3C and legacy I2C: * I2C devices on an active I3C bus need “50 nsec spike filters” in series with their Clock and Data pins to prevent the legacy I2C devices from getting confused by some fast short signals (“spikes”) present in I3C traffic. * The spike filters can be simple RC circuits (series resistor in front of I2C device pin, capacitor between IC pin and GND). * I2C clock stretching is not allowed on an I3C bus * I2C bus 10 bit addressing mode is not allowed in I3C Check with your COM-HPC Module vendor for details about their possible I3C support on the COM-HPC I2C1 port. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 106/159](.picmg-com-hpc-carrier-design-guide-alt/slide-108.jpg) ## Slide 109 ![**Header:** Reference Schematics and Block Diagrams **Title:** 3.17. Port 80h Debug Display Over COM-HPC USB_PD_I2C **Figure Caption:** Figure 55: Port 80h Debug Display Over COM-HPC USB_PD_I2C **Schematic Text & Labels:** +3.3V_A C701 100n 0402 25V C702 100n 0402 25V R533 100k 0402 DIG2_G R516 270R 0402 DIG2_F R519 270R 0402 DIG2_E R521 270R 0402 DIG2_D R523 270R 0402 DIG2_A R525 270R 0402 DIG2_B R527 270R 0402 DIG2_C R529 270R 0402 DIG2_C R U58 PCA6416A P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 INT SDA SCL TP VDD(P) VDD(I2C) ADDR VRESET P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DIG1_G DIG1_F DIG1_E DIG1_D DIG1_A DIG1_B DIG1_C R534 100k 0402 R518 270R 0402 R520 270R 0402 R522 270R 0402 R524 270R 0402 R526 270R 0402 R528 270R 0402 R530 270R 0402 +3.3V_A R531 10k 0402 INT_PCD1# USB_PD_I2C_DAT COM USB_PD_I2C_CLK COM I2C Pull-Up on COM-HPC module RES_PCD1# R532 10k 0402 +3.3V_A 8 bit addr: 0x40 MSB D66 CA0 CA1 +3.3V_A DIG2_A DIG2_B DIG2_C DIG2_D DIG2_E DIG2_F DIG2_G +3.3V_A DP 7SEG10CAGRN Kingbright SA39-11GWA LSB D67 CA0 CA1 +3.3V_A DIG1_A DIG1_B DIG1_C DIG1_D DIG1_E DIG1_F DIG1_G +3.3V_A DP 7SEG10CAGRN **Body Text:** The COM-HPC hardware specification allows for BIOS Port 80h debug codes to be serialized and transmitted over the USB Power Delivery I2C bus (COM-HPC pins USB_PD_I2C_DAT and _CLK). Figure 55 above illustrates how the codes can be de-serialized and displayed on a pair of 7-segment LED displays. This feature is optional. There are other methods for Port 80h codes to be conveyed for debug use. The Port 80h I/O writes can be picked off of the eSPI bus or even a PCIe x1 link by appropriate hardware such as a CPLD, FPGA or some Super I/O devices. Some BIOSes provide 4 digit codes as opposed to 2 digit codes. It is also possible for special debug versions of a BIOS to transmit ASCII versions of the Port 80h debug codes over one of the asynchronous serial ports ... check with your Module vendor. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 107/159](.picmg-com-hpc-carrier-design-guide-alt/slide-109.jpg) ## Slide 110 ![Reference Schematics and Block Diagrams **3.18. Carrier BMC with IPMB Link to Module** A high end Carrier BMC (Board Management Controller) using an Aspeed AST2500 / AST2520 is shown in Figures 56, 57 and 58 below. The three Figures do not show the complete implementation – the DDR4 memory devices and the Aspeed power section are omitted. What is shown are the features relevant to COM-HPC operation – the interfaces to the COM-HPC and to the user. Refer to the Aspeed documentation for complete design information. The BMC interfaces to the Module include IPMB, eSPI, UART1, I2C0 and a collection of status and control signals such as power state status, reset, power button etc. BMC operator interfaces include a USB port for keyboard and mouse use, a VGA port, and a 1000BASE-T management network interface. The primary management interface to the COM-HPC Module is over the IPMB. The Module, if it supports management functions, includes a small satellite controller known as the MMC (Module Management Controller). The MMC has at minimum an IPMB slave interface to the BMC. The design shown includes two SPI Flash devices attached to the BMC, and an eSPI interface to the COM-HPC. The COM-HPC BIOS image can reside in the BMC attached SPI Flash. This allows the BMC to manage Out of Band Flash BIOS updates, if so desired. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 108/159](.picmg-com-hpc-carrier-design-guide-alt/slide-110.jpg) ## Slide 111 ![Reference Schematics and Block Diagrams Figure 56: Carrier BMC with IPMB Link to Module – Sheet 1 U5A AST2500/2520 Rev:1.5 PCI-Express DDR3/DDR4 LPC ESPI SD/SDIO I2C GPIO AST2500A2-GP 1 OF 4 PLTRST# PCIe_REFCLK0_LO+ PCIe_REFCLK0_LO- PCIe_BMC_TX+ PCIe_BMC_TX- For DDR4 Memory V_M_BMC_DDR4_D00 V_M_BMC_DDR4_D01 V_M_BMC_DDR4_D02 V_M_BMC_DDR4_D03 V_M_BMC_DDR4_D04 V_M_BMC_DDR4_D05 V_M_BMC_DDR4_D06 V_M_BMC_DDR4_D07 V_M_BMC_DDR4_D08 V_M_BMC_DDR4_D09 V_M_BMC_DDR4_DQ10 V_M_BMC_DDR4_DQ11 V_M_BMC_DDR4_DQ12 V_M_BMC_DDR4_DQ13 V_M_BMC_DDR4_DQ14 V_M_BMC_DDR4_DQ15 V_M_BMC_DDR4_DQS0_DP V_M_BMC_DDR4_DQS1_DP V_M_BMC_DDR4_DQS0_DN V_M_BMC_DDR4_DQS1_DN V_M_BMC_DDR4_RST_N V_M_BMC_DDR4_ALERT_N +1.2V_A +0.6V_A C6 0.1uF 25V R68 240ohm +1% eSPI_CLK eSPI_CS0# eSPI_CS1# eSPI_ALERT0# eSPI_ALERT1# eSPI_RST# R70 0ohm +5% R72 0ohm +5% R74 0ohm +5% R76 0ohm +5% R78 0ohm +5% R80 0ohm +5% +3.3V_A R81 10K +1% LPC_PME_N L21 PCIe_BMC_RX_P_C C4 0.1uF 25V PCIe_BMC_RX+ L22 PCIe_BMC_RX_N_C C5 0.1uF 25V PCIe_BMC_RX- PD_P2E_BMC_PEREXT R47 200ohm +1% +3.3V_A For DDR4 Memory BMC_SCL1 R48 4.7K +1% BMC_SDA1 R49 4.7K +1% BMC_SCL3 R52 4.7K +1% BMC_SDA3 R53 4.7K +1% BMC_SCL8 R62 4.7K +1% BMC_SDA8 R63 4.7K +1% eSPI_I00 R73 0ohm +5% eSPI_I01 R75 0ohm +5% eSPI_I02 R77 0ohm +5% eSPI_I03 R79 0ohm +5% eSPI I2C0 BMC_SCL1 R82 0ohm +5% I2C0_CLK BMC_SDA1 R83 0ohm +5% I2C0_DAT IPMB BMC_SCL3 R86 0ohm +5% IPMB_CLK BMC_SDA3 R87 0ohm +5% IPMB_DAT For Thermal Sensor SENSOR_SCL BMC_SCL8 R96 0ohm +5% SENSOR_SDA BMC_SDA8 R97 0ohm +5% PERST PERECLKP PERECLKN PERXP PERXN MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ00 MDQ01 MDQ02 MDQ03 MDQ04 MDQ05 MDQ06 MDQ07 MDQ08 MDQ09 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MRESET MALERT MREF MIOZ GPIOAC4_ESPID0_LCAD0 GPIOAC5_ESPID1_LFRAME GPIOAC1_ESPID1_LADD1 GPIOAC2_ESPID2_LADD2 GPIOAC3_ESPID3_LADD3 GPIOIO4_USBCN GPIOIO5_LPCPD_LPCSMI GPIOIO6_LPCPME GPIOIO7 GPIOIO0_SDA1 GPIOIO1_SDA0 GPIOIO2_SDA10 GPIOIO3_SDA11 GPIOIO4_SDA12 GPIOIO5_SDA13 GPIOIO6_SDA14 GPIOIO7_SDA15 GPIOIO0_SDA2 GPIOIO1_SDA20 GPIOIO2_SDA21 GPIOIO3_SDA22 GPIOIO4_SDA23 GPIOIO5_SDA24 GPIOIO6_SDA25 GPIOIO7_SDA26 GPIOIO0_SDA3 GPIOIO1_SDA30 GPIOIO2_SDA31 GPIOIO3_SDA32 GPIOIO4_SDA33 GPIOIO5_SDA34 GPIOIO6_SDA35 GPIOIO7_SDA36 GPIOIO0_SDA4 GPIOIO1_SDA40 GPIOIO2_SDA41 GPIOIO3_SDA42 GPIOIO4_SDA43 GPIOIO5_SDA44 GPIOIO6_SDA45 GPIOIO7_SDA46 GPIOIO0_SDA5 GPIOIO1_SDA50 GPIOIO2_SDA51 GPIOIO3_SDA52 GPIOIO4_SDA53 GPIOIO5_SDA54 GPIOIO6_SDA55 GPIOIO7_SDA56 GPIOIO0_SDA6 GPIOIO1_SDA60 GPIOIO2_SDA61 GPIOIO3_SDA62 GPIOIO4_SDA63 GPIOIO5_SDA64 GPIOIO6_SDA65 GPIOIO7_SDA66 GPIOIO0_SDA7 GPIOIO1_SDA70 GPIOIO2_SDA71 GPIOIO3_SDA72 GPIOIO4_SDA73 GPIOIO5_SDA74 GPIOIO6_SDA75 GPIOIO7_SDA76 AB11 AB12 Y11 V11 W12 AB13 Y12 U12 Y13 W13 V13 MA1 W14 U14 W15 V15 MA5 AB16 AA16 W16 Y16 MA8 W18 MA10 AA14 MA11 Y14 AB15 Y15 U15 MA15 MA14 AB8 MDM0 MDM1 GPIOIO0_MACLINK GPIOIO1_MACLINK GPIOIO2_TIMER3_SPIICS1 GPIOIO3_TIMER4 GPIOIO4_SDA14 GPIOIO6_OSCCLK GPIOIO7_PEWAKE R3516 0ohm +5% R3515 4.7K +1% +3.3V_A WAKED# PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 109/159](.picmg-com-hpc-carrier-design-guide-alt/slide-111.jpg) ## Slide 112 ![Reference Schematics and Block Diagrams Figure 57: Carrier BMC with IPMB Link to Module – Sheet 2 **Top Left (EEPROM 0):** +3.3V_A EEPROM 0 R102 4.7K +1% BMC_SPI0_CS0 R105 22ohm +1% BMC_SPI0_MOSI R105 R108 22ohm +1% BMC_SPI0_MISO BMC_SPI0_CS EEPROM 0 VCC 1, CS 2, CLK 3, SI/SI00 4, SO/SI0POT 5, WP/SI02 6, HOLD/03 7, NC 8, GND 9 +3.3V_A R110 4.7K +1% BMC_SPI1_WP_N R111 4.7K +1% BMC_SPI1_HOLD# +3.3V_A C7 0.1uF_25V SPI_FLASH_SKT_16 SSKT_LOTES_ACA-SPI-006-K01 **Top Right (EEPROM 1):** EEPROM 1 R103 4.7K +1% BMC_SPI1_CS1 R106 22ohm +1% BMC_SPI1_MOSI R106 R109 22ohm +1% BMC_SPI1_MISO BMC_SPI1_CS EEPROM 1 VCC 1, CS 2, CLK 3, SI/SI00 4, SO/SI0POT 5, WP/SI02 6, HOLD/03 7, NC 8, GND 9 +3.3V_A R112 4.7K +1% BMC_SPI2_WP_N R114 4.7K +1% BMC_SPI2_HOLD# +3.3V_A C8 0.1uF_25V SPI_FLASH_SKT_16 SSKT_LOTES_ACA-SPI-006-K01 **Center (AST2500/2520):** BMC_SPI0_CS1 R118 22ohm +1% BMC_SPI0_CS_R CARRIER_HOT# COM R124 22ohm +1% BMC_SPI1_CS1 R116 22ohm +1% BMC_SPI1_CS_R AST2500/2520 Rev.1.5 BMC SPI BMC SPI2 ACPI Digital Video Output Left Pins: T1 GPIO0_NCT51 T2 GPIO1_NDCR1 T3 GPIO2_NIR0 T4 GPIO3_NTR0 T5 GPIO4_NTR1 T6 GPIO5_NTR2 T7 GPIO6_NTR3 T8 GPIO7_NTR4 T9 GPIO8_NTR5 T10 GPIO9_NTR6 T11 GPIO10_NTR7 T12 GPIO11_NTR8 T13 GPIO12_NTR9 T14 GPIO13_NTR10 T15 GPIO14_NTR11 T16 GPIO15_NTR12 T17 GPIO16_NTR13 T18 GPIO17_NTR14 T19 GPIO18_NTR15 T20 GPIO19_NTR16 T21 GPIO20_NTR17 T22 GPIO21_NTR18 T23 GPIO22_NTR19 T24 GPIO23_NTR20 T25 GPIO24_NTR21 T26 GPIO25_NTR22 T27 GPIO26_NTR23 T28 GPIO27_NTR24 T29 GPIO28_NTR25 T30 GPIO29_NTR26 T31 GPIO30_NTR27 T32 GPIO31_NTR28 T33 GPIO32_NTR29 T34 GPIO33_NTR30 T35 GPIO34_NTR31 T36 GPIO35_NTR32 T37 GPIO36_NTR33 T38 GPIO37_NTR34 T39 GPIO38_NTR35 T40 GPIO39_NTR36 T41 GPIO40_NTR37 T42 GPIO41_NTR38 T43 GPIO42_NTR39 T44 GPIO43_NTR40 T45 GPIO44_NTR41 T46 GPIO45_NTR42 T47 GPIO46_NTR43 T48 GPIO47_NTR44 T49 GPIO48_NTR45 T50 GPIO49_NTR46 T51 GPIO50_NTR47 T52 GPIO51_NTR48 T53 GPIO52_NTR49 T54 GPIO53_NTR50 T55 GPIO54_NTR51 T56 GPIO55_NTR52 T57 GPIO56_NTR53 T58 GPIO57_NTR54 T59 GPIO58_NTR55 T60 GPIO59_NTR56 T61 GPIO60_NTR57 T62 GPIO61_NTR58 T63 GPIO62_NTR59 T64 GPIO63_NTR60 T65 GPIO64_NTR61 T66 GPIO65_NTR62 Right Pins: T1 GPIO0_NCT52 T2 GPIO1_NDCR2 T3 GPIO2_NIR1 T4 GPIO3_NTR1 T5 GPIO4_NTR2 T6 GPIO5_NTR3 T7 GPIO6_NTR4 T8 GPIO7_NTR5 T9 GPIO8_NTR6 T10 GPIO9_NTR7 T11 GPIO10_NTR8 T12 GPIO11_NTR9 T13 GPIO12_NTR10 T14 GPIO13_NTR11 T15 GPIO14_NTR12 T16 GPIO15_NTR13 T17 GPIO16_NTR14 T18 GPIO17_NTR15 T19 GPIO18_NTR16 T20 GPIO19_NTR17 T21 GPIO20_NTR18 T22 GPIO21_NTR19 T23 GPIO22_NTR20 T24 GPIO23_NTR21 T25 GPIO24_NTR22 T26 GPIO25_NTR23 T27 GPIO26_NTR24 T28 GPIO27_NTR25 T29 GPIO28_NTR26 T30 GPIO29_NTR27 T31 GPIO30_NTR28 T32 GPIO31_NTR29 T33 GPIO32_NTR30 T34 GPIO33_NTR31 T35 GPIO34_NTR32 T36 GPIO35_NTR33 T37 GPIO36_NTR34 T38 GPIO37_NTR35 T39 GPIO38_NTR36 T40 GPIO39_NTR37 T41 GPIO40_NTR38 T42 GPIO41_NTR39 T43 GPIO42_NTR40 T44 GPIO43_NTR41 T45 GPIO44_NTR42 T46 GPIO45_NTR43 T47 GPIO46_NTR44 T48 GPIO47_NTR45 T49 GPIO48_NTR46 T50 GPIO49_NTR47 T51 GPIO50_NTR48 T52 GPIO51_NTR49 T53 GPIO52_NTR50 T54 GPIO53_NTR51 T55 GPIO54_NTR52 T56 GPIO55_NTR53 T57 GPIO56_NTR54 T58 GPIO57_NTR55 T59 GPIO58_NTR56 T60 GPIO59_NTR57 T61 GPIO60_NTR58 T62 GPIO61_NTR59 T63 GPIO62_NTR60 T64 GPIO63_NTR61 T65 GPIO64_NTR62 T66 GPIO65_NTR63 **Right Side Components:** CARRIER_HOT# R120 4.7K +1% R123 10K +1% CARRIER_HOT# R129 10K +1% R122 0ohm +5% SUS_SSR# R121 0ohm +5% SUS_5SR COM +3.3V_A +3.3V_A +3.3V_A R204 4.7K +1% FM_BMC_PWRBTN_OUT_N U44 SN74LVCGT08DR_SOT26-6 R1548 0ohm +5% COM PWRBTN# SW_TACT-T5-A02 C150 0.1uF_25V R131 0ohm +5% UART1 UART1_CTS# UART1_RTS# UART1_RX UART1_TX SW_TACT-T5-A02 C782 0.1uF_25V R132 0ohm +5% R133 0ohm +5% **Bottom Left:** R3549 0ohm +5%NC7823 SW_TACT-T5-A02 C110 0.1uF_25V +3.3V_A +3.3V_A R3520 4.7K +1% R3521 4.7K +1% RST_BMC_SYSRST_BTN_OUT_N RST_TCK# U49 SN74LVCGT08DR_SOT26-6 For BMC Console Port BMC_UART_TX0 BMC_UART_RX0 BMC_RMII1_50M_CLK BMC_RMII1_TX0 BMC_RMII1_RX0 BMC_RMII1_CRS_DV R136 0ohm +5% RMII1_REF_CLK R137 10K +1% R138 0ohm +5% RMII1_TX0 R139 0ohm +5% RMII1_RX0 R140 0ohm +5% RMII1_CRS_DV R155 10K +1% RMII1_REF_CLK R156 10K +1% RMII1_TX0 R157 10K +1% RMII1_RX0 R158 10K +1% RMII1_CRS_DV **Bottom Right:** For Management Network MAC1 MAC2 BMC_RMII1_TX_EN BMC_RMII1_TX0 BMC_RMII1_TX1 OSC1 SG2150SM-STF-L-4005 L1 120_100MHz_2A C9 0.1uF_25V C10 0.1uF_25V CLK_SOM R145 33ohm +1% BMC_RMII1_50M_CLK **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 110/159](.picmg-com-hpc-carrier-design-guide-alt/slide-112.jpg) ## Slide 113 ![**Header:** Reference Schemas and Block Diagrams **Title:** Figure 58: Carrier BMC with IPMB Link to Module – Sheet 3 **Top Left Section (Oscillator & Reset):** +3.3V_A OSC2 4 VCC OUT ST GND 3 BMC_24M R160 22ohm +-1% BMC_24M_R R161 X_10K_+1% C12 0.1uF_25V BMC_SRST_BTM_N 0ohm +-5% 185 BMC_SYS_RESET_N +3.3V_A 4.7K +-1% R169 BMC_EXT_RST 189 BMC_HB_LED +3.3V_A R174 330ohm +-1% LG-170Y-CT BMC_FAN_TACH0 U5 R170 10K +-1% PD_BMC_ENTEST For FAN connector **Center Chip (Top Half - AST2500/2520):** U5C AST2500/2520 Rev.1.5 W18 CLKIN U18 SRST EXTRST MISC DAC V18 HBLED ENTEST K3 U5 GPIO00_TACH0_VPIG8 GPIO10_PWM0 GPIO01_TACH1_VPIG9 GPIO11_PWM1 GPIO02_TACH2 GPIO2_PWM2_VPIG2 GPIO03_TACH3_VPIG3 GPIO3_PWM3_VPIG3 GPIO04_TACH4_VPIR2 GPIO4_PWM4_VPIG4 GPIO05_TACH5_VPIR3 GPIO5_PWM5_VPIG5 GPIO06_TACH6_VPIR4 GPIO6_PWM6_VPIG6 GPIO07_TACH7_VPIR5 GPIO7_PWM7_VPIG7 GPIO08_TACH8_VPIR6 GPIO09_TACH9_VPIR7 GPIO10_TACH10_VPIR8 GPIO11_TACH11_VPIR9 GPIO12_TACH12 GPIO13_TACH13 GPIO14_TACH14 GPIO15_TACH15 FAN **Top Right Section (VGA & Fan Connectors):** J2 DACB J3 DACG J4 DACR N5 GPIOJ4_VGAHS R4 GPIOJ5_VGAVS R3 GPIOJ6_DDCCLK T3 GPIOJ7_DDCDAT V2 GPIOV2 Y3 GPIOY3 W3 GPIOV3 A3 GPIOV4 T4 GPIOV5 For VGA connector VGA_BLU VGA_GRN VGA_RED VGA_HSYNC VGA_VSYNC VGA_I2C_CLK VGA_I2C_DAT V2 BMC_FAN_PWM0 For FAN connector **Right Middle Section (USB):** +3.3V_A P3V3_BMC_USB2AV33_AUX FB1 120_100MHz_2A BLM18PG121SN1D C14 0.01uF_50V C15 4.7uF_6.3V C7 B8 PD_BMC_USB2A_VREF B7 PD_BMC_USB2B_VREF C17 33pF_50V R175 8.2K +-1% R176 8.2K +-1% A7 USB2AV33 USB2AVRES USB2BVRES A8 USB2A_DP USB2A_DN R3536 0ohm +-5% USB2B_DP USB2B_DN R3537 0ohm +-5% COM USB2B_ For BMC KVM Keyboard/Mouse **Left Middle Section (ADC Power Monitor):** ADC Power Monitor C16 0.1uF_25V +2.5V_A BMC_ADC0 1.43K +-1% R193 1K +-1% R198 **Center Chip (Lower Half - ADC/PECI/JTAG/SGPIO):** F4 ADC0_GPIW0 F2 ADC1_GPIW1 E1 ADC2_GPIW2 F3 ADC3_GPIW3 E3 ADC4_GPIW4 G5 ADC5_GPIW5 G4 ADC6_GPIW6 F2 ADC7_GPIW7 G3 ADC8_GPIX0 G2 ADC9_GPIX1 F1 ADC10_GPIX2 H5 ADC11_GPIX3 G1 ADC12_GPIX4 H2 ADC13_GPIX5 G5 ADC14_GPIX6 H4 ADC15_GPIX7 ADC USB PECI SGPIO JTAGIC AN17 PECIVDD PECI AB18 E11 NTRST D12 TDI C8 TMS C9 TCK D11 TDO C18 GPIO14_SGP52C_SALT1 E15 GPIO00_SGPS1C B16 GPIO01_SGPS1D C15 GPIO02_SGPSID A19 GPIO03_SGPSI1 D18 GPIO04_SGP52K_SALT1 E17 GPIO05_SGP52LD_SALT2 D18 GPIO06_SGP520_SALT3 E14 GPIO07_SGP521_SALT4 **Bottom Center Section (System SPI & BIOS Flash):** B15 CNBMC_I2C_ALERT-L R186 0ohm +-5% COM I2C_ALERT# R188 22ohm +-1% C15 BMC_SPI1_CS0_N A14 BMC_SPI1_CLK A15 BMC_SPI1_MOSI A15 BMC_SPI1_MISO For System BIOS Flash AST2500A2_GP 3 of 4 System BIOS **Bottom Left Section (BMC Reset):** For BMC Reset +1.15V_A R168 3.3K +-1% C13 1uF_16V R171 10K +-1% +3.3V_A R163 10K +-1% Q2 PMBT3904_200mA/40V U7 74AHC1G14_SOT23-5 4 BMC_SRST_BTM_N BMC_BTN SW-TACT-TS-A02 C2784 0.1uF_25V R166 0ohm +-5% DNI **Bottom Right Section (Power/Thermal):** +3.3V_A R1013 4.7K +-1% Q53 BSS138LT1_200mA/50V 1 PLTRST# THERMTRIP# +3.3V 4.7K +-1% R126 10K +-1% R127 VIN_PWR_OK COM **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 111/159](.picmg-com-hpc-carrier-design-guide-alt/slide-113.jpg) ## Slide 114 ![**Reference Schematics and Block Diagrams** **3.19. General Purpose SPI** The COM-HPC General Purpose SPI port is described as an easy-to-use hardware interface for Carrier peripherals requiring four signal pins (data in, data out, clock, chip select) plus an optional interrupt output. It supports low-to-medium speed devices (circa 4 to 20 MHz) like A/D and D/A converters, touch controllers, and Flash memories. The text notes it is faster than traditional I2C ports (400 KHz) but slower than PCI Express, offering lower implementation costs. The section details pinout definitions allowing four chip selects for up to four Carrier GP SPI devices using 3.3V signal levels in the S0 power state. Devices may be daisy-chained or routed in a branch topology. Routing instructions specify keeping data, output, and clock lines loosely together with approximately the same length, while chip-select lines should route directly from the connector. **3.20. Rapid Shutdown** Rapid Shutdown is a rarely used hardware feature important for defense industry customers, designed to rapidly collapse all Module and Carrier power rails and remove bias voltages to prevent damage in extreme situations. It operates without software consideration. Implementation details state that the feature may be depopulated if not needed. If asserted by a 5V logic level signal, all power Module and Carrier rails are collapsed using N-channel FETs and drain resistors. The +12V or Wide Range power source must be immediately cut and isolated from bulk capacitance, often using hot-swap controller devices. All Carrier power rails must also be collapsed. The text concludes that design drawings are not shown and Module vendors should provide support. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 112/159](.picmg-com-hpc-carrier-design-guide-alt/slide-114.jpg) ## Slide 115 ![Reference Schematics and Block Diagrams **3.21. Thermal Protection** COM-HPC defines two pins related to thermal protection of the system: * **CARRIER_HOT#** * This is a 3.3V level S0 power domain input signal, with an on-Module pull-up * This signal may be left open, or it may be driven low by Carrier hardware if a system over-temperature situation is detected. * Module support for this signal is required, per the **COM-HPC Base Specification**. * There is no definition in the COM-HPC Base Specification as to how long CARRIER_HOT# should stay low in an system over-temperature situation * **THERMTRIP#** * This is a 3.3V level S0 power domain output * If driven low, it indicates that the CPU is in an over-temperature situation * There is no definition in the COM-HPC Base Specification as to how long THERMTRIP# should stay low in an over-temperature situation * Carriers may leave this signal open, or they may act on it * Ideally, a Carrier circuit removes system S0 power if the situation persists and is not a short term glitch, and sets a bit in a non-volatile memory that can be read by Module firmware on the next S0 power up. * A Carrier BMC may also track / process this COM-HPC output signal PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 113/159](.picmg-com-hpc-carrier-design-guide-alt/slide-115.jpg) ## Slide 116 ![Reference Schematics and Block Diagrams 3.22. System Management Bus (SMBus) SMBus Introduction The SMBus is primarily used to manage system peripherals on the COM-HPC Module and on the Carrier. SMBus devices such as the Serial Presence Detect (SPD) EEPROM(s) for the system RAM, thermal sensors, PCIe devices, clock buffers, Smart Battery, etc. are managed over the SMBus. Designers need to take note of several implementation issues to ensure reliable SMBus interface operation. The SMBus is derived from I2C. However, I2C devices have the potential to lock up the data line while sending information and require a power cycle to clear the fault condition. SMBus devices contain a timeout to monitor for and correct this condition. Designers are urged to use SMBus devices when possible over standard I2C devices. COM-HPC Modules are required to power SMBus devices from the suspend power rail in order to have control in all system power states. The COM-HPC Module may not function correctly or at all if Carrier SMBus devices interfere with proper Module SMBus device operation. SMBus Power Domain Isolation The devices on the Carrier Board using the SMBus are usually powered by the main 3.3V (S0) power rail. To avoid current leakage between the suspend (S5) and the main (S0) power rails, the SMBus devices in the S5 power domain must be separated by a bus switch from S0 domain SMBus devices. FET devices, as shown in Figure 54 above, or I2C / SMBus isolation devices, as shown in Table 20 above may be used to achieve the S5 / S0 power domain isolation. SMBus Addresses Since the SMBus is used by the Module and Carrier, care must be taken to ensure that Carrier based devices do not overlap the address space of Module based devices. Typical Module SMBus devices and their binary I2C / SMBus addresses include memory SPD (Serial Presence Detect) addresses 1010 000x, 1010 001x, up to 1010 111x for 8 DIMMs, programmable clock synthesizers (1101 001x), clock buffers (1101 110x), thermal sensors (1001 000x), and management controllers (vendor defined address). The 'x' in the binary addresses is the SMBus / I2C R/W bit. Contact your Module vendor for information on the SMBus addresses used on the Module. PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 114/159](.picmg-com-hpc-carrier-design-guide-alt/slide-116.jpg) ## Slide 117 ![**Header:** Reference Schematics and Block Diagrams **3.23. General Purpose Inputs / Outputs** COM-HPC defines 12 General Purpose I/O pins. It is expected that the 12 pins can be individually configured as either inputs or outputs, that they be configured as inputs on power up, that they be powered by the Module 3.3V suspend (S5) power rail, that there be a 100K pull-up on the Module, and that the Module GPIO pins be able to generate interrupts to the Module CPU. As the COM-HPC GPIO may be inputs, outputs or bidirectional signals, there are a variety of ways to use and protect them. If the target I/O devices are in a different power domain from (I.e targets are in the S0 domain), that needs to be taken into account by an appropriate logic buffer or FET arrangement, similar to the S5 – S0 power domain isolation shown in this document for I2C and the SMBus. If any of the GPIO signals are exposed to the outside world and exposed to human contact and ESD events, then there needs to be appropriate ESD protection, EMI mitigation, and hardening against accidents such as short circuiting or exposure to power rails. The details of the protection implemented depend on the factors such as: * What level of ESD protection is expected ? * What is the GPIO signal bandwidth ? * Low bandwidth GPIO signals may be protected with simple measures including: * Dual Schottky diodes: * 1st diode with anode (A) at GND and cathode (K) at the GPIO signal level * 2nd diode with anode at GPIO signal level and cathode at the GPIO VCC level * Alternatives to the dual Schottky diodes proposed above may be specialty diodes or diode arrays designed for ESD mitigation such as those shown in the NBASE-T, Ethernet, USB, DP and HDMI sections of this document. * A series resistor between the Schottky diode K – A node and the COM-HPC GPIO pin-out * Possibly a ferrite in between the COM-HPC GPIO pin and the external connector * If the GPIO signal bandwidth is somewhat higher, then adjustments have to be made: * The ESD diode pin capacitance needs to be lower, and appropriately sized for the bandwidth at hand * The series resistor value needs to be lowered * The ferrite inductance value may need adjustment * If user abuse is expected (hot plugging, sudden removal etc) then protection measures may include: * Some or all of the protection measures listed just above * Robust buffer ICs that stand between the COM-HPC pins and the protection measures * If the GPIO is to be used as a single direction input or output, then robust buffering is easy * Many bidirectional buffers are available, including buffers that auto-sense the signal direction **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 115/159](.picmg-com-hpc-carrier-design-guide-alt/slide-117.jpg) ## Slide 118 ![**Header** Reference Schematics and Block Diagrams **Section Title** 3.24. Module Type Detection and Protection **Introductory Text** There are three TYPE pins defined in the COM-HPC pin-outs allowing up to eight Types to be defined. At present, three Types are defined, per Table 21 below: **Table 21: COM-HPC Type Definitions** Ref Module Connections (TYPE2) (TYPE1) (TYPE0) Meaning :--- :--- :--- :--- :--- 7 NC NC NC Reserved 6 NC NC GND Reserved 5 NC GND NC Reserved 4 NC GND GND Server Module – Fixed 12V input 3 GND NC NC Reserved 2 GND NC GND Reserved 1 GND GND NC Client Module - Wide Range 8V to 20V input 0 GND GND GND Client Module – Fixed 12V input **Paragraph 1** COM-HPC Carrier hardware may optionally implement hardware to hold off the application of power to the main Carrier circuits and to the Module if the Module and Carrier Types do not match up. The COM-HPC Client and Server pin-outs are different (the differences are noted in Table 2 earlier in this document) and it is not desirable to power up a system in which the Carrier and Module Types do not match. **Paragraph 2** The Carrier hardware shown in Figure 59 below holds off power distribution if the Module Type is not a fixed input voltage Client or a wide-range input Client. The example uses and ATX style power supply. The 5V Standby power to the Carrier and Module is cut off by power switch U60 in the Figure. The open drain FET T1 along with pull-down resistor R539 ensure that the ATX power control line (ATX_PSON#) is floating and not pulled low. This prevents the main ATX power rails from coming on. FET T1 should not be replaced by a logic gate as the gate's internal ESD protection diodes might provide a path for the ATX_PSON# signal to be pulled low unintentionally. **Footer** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 116/159](.picmg-com-hpc-carrier-design-guide-alt/slide-118.jpg) ## Slide 119 ![**Reference Schematics and Block Diagrams** **Figure 59 Section** * **Title:** Figure 59: Module Type Detection / Protection – ATX Power Supply and Client Type Module / Carrier * **Schematic Text:** * +5V_SBY_ATX * C703 100n 0402 25V * R534 100k 0402 * R535 100k 0402 * U59 SN74LVC1G02 * SBY_EN_LSW * C704 1u0 0603 16V * U60 TPS22975 * VCC_5V_SBY * C706 22u 1206 16V * SBY_LSW_CT * C705 4n7 0402 25V Rise time ~8ms * TYPE2 COM * TYPE1 COM * TYPE0 not evaluated. Carrier with ATX PSU supports 'Fixed 12V' and 'Wide Range' Modules * SUS_S3# COM * R539 100k 0402 * T1 2N7002A * ATX_PSON# **Middle Text** The Carrier hardware shown in Figure 60 below holds off power distribution if the Module Type is not a Server Type Module. The example uses and AT style supply. **Figure 60 Section** * **Title:** Figure 60: Module Type Detection / Protection – AT Power Supply and Server Type Module / Carrier * **Schematic Text:** * +VCC_IN * U62 LDK320M33R * +3.3V_initial * C707 1u0 0805 25V * C708 1u0 0402 10V * R534 100k 0402 * R535 100k 0402 * C709 100n 0402 25V * TYPE1 COM * TYPE0 COM * U59 SN74LVC1G02 * +3.3V_initial * R537 100k 0402 * TYPE2 COM * U61 NC7SZ08 * LSW_EN * R538 100k 0402 * +VCC_IN * C712 22u 1206 25V * +3.3V_initial * C710 1u0 0402 10V * U63 NCP45750 * VCC to COM-HPC module * LSW_EN * SR_VCC * C711 100n 0402 25V rise time ~12ms **Bottom Text** Server Modules may use either AT or ATX or other style power supplies. An AT supply is used here just as an example. **Footer** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 117/159](.picmg-com-hpc-carrier-design-guide-alt/slide-119.jpg) ## Slide 120 ![PCB Design Rule Summaries 4. PCB Design Rule Summaries 4.1. High Speed PCB Design Information – Design Guides and Books 4.1.1. Intel and AMD Design Guides Intel and AMD have a wealth of design guide material available, although most current materials are NDA (Non Disclosure Agreement) protected and Carrier designers must obtain their own NDAs with these vendors to access these documents. A few useful documents are listed in Table 22 below. Although these guides are centered around CPU board development there is also much general high speed design information, often in graphical format, about topics such as how to keep differential pairs length matched, about stackups, about via stubs, about voiding planes under certain components and features, and so on. There is also information about peripheral interfaces such as PCIe, USB 3 and 4 etc. Table 22: Intel and AMD Design Guides Vendor Doc # Description / Title Notes :--- :--- :--- :--- AMD 5515 Socket SP3 Processor Mother Board DG Some general high speed PCB design info(br)Fiber weave effect information(br)PCIe Gen 3 and 4 information Intel 576513 Intel Confidential Some general high speed PCB design info(br)PCB differential pair length matching techniques(br)PCIe Gen 3 and 4 information(br)USB 3.1(br)Ethernet KR 10G/25G information Intel 607872 Tiger Lake UP3 UP4 Platform DG Fiber weave effect information(br)PCIe Gen 3 and 4 length matching information(br)USB4 routing information Intel 618429 Tiger Lake H Platform DG Intel 627205 Intel Confidential Fiber weave effect information(br)No stub routing techniques(br)Voiding advice(br)PCIe Gen 4 and Gen 5 advice Intel 406926 Fiberweave Effect White Paper PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 118/159](.picmg-com-hpc-carrier-design-guide-alt/slide-120.jpg) ## Slide 121 ![**PCB Design Rule Summaries** **4.1.2. Books on High Speed PCB Design Principles** The publications listed below are much more academic than the design guides listed in Section Error: Reference source not found above. These books may be useful to designers interested in the engineering and physics details of what is going on with very fast signal propagation. The book titled *High Speed Digital Design: Design Of High Speed Interconnects And Signaling* is the newest and perhaps most relevant book in this list. It was written by a trio of Intel engineers and covers contemporary high speed serial interface topics quite thoroughly. * **Advanced Signal Integrity For High-Speed Digital Designs** Stephen H.; Heck and Howard L Hall ISBN 13: 9780470192351 ISBN 10: 0470192356 © 2009 Wiley-IEEE Press * **High Speed Digital Design: Design Of High Speed Interconnects And Signaling** Hanqiao Zhang, Steven Krooswyk and Jeffrey Ou © 2015 Morgan Kaufman, Elsevier Inc. ISBN: 978-0-12-418663-7 * **High-Speed Signal Propagation - Advanced Black Magic** Howard Johnson and Martin Graham © 2003 Pearson Education, Prentice Hall Professional Technical Reference * **Right the First Time - A Practical Handbook on High Speed PCB and System Design Volumes 1 and 2** Lee W. Ritchey ©2006 Speeding Edge * Signal Integrity Issues and Printed Circuit Board Design Douglas Brooks ©2003 Pearson Education, Prentice Hall Professional Technical Reference PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 119/159](.picmg-com-hpc-carrier-design-guide-alt/slide-121.jpg) ## Slide 122 ![**Header:** PCB Design Rule Summaries **Title:** 4.2. High Speed Serial Interfaces – General PCB Design Rules **Figure Title:** Figure 61: PCB Cross Section Terms and Notations **Diagram Labels (Top to Bottom):** * **Microstrip Diagram:** Diff Pair - Surface, Plane, Microstrip * **Symmetric Stripline Diagram:** Symmetric Stripline * **Asymmetric Stripline Diagram:** Asymmetric Stripline, T, D, W, S, W, D, H2, H1 or H * **Dual Stripline Diagram:** Dual Stripline or Dual Asymmetric Stripline, DX, Diff Pair, Other Periodic Signal **Bottom Text:** Some of the terms and notations in the Figure above are used in the Tables and text on the following pages. The long copper colored thin rectangles represent the GND or PWR planes and the smaller rectangles, for the most part, the edge coupled differential pairs. The upper and lower signal layers within a Dual Stripline structure should be routed orthogonally to each other to minimize coupling and thereby crosstalk. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 120/159](.picmg-com-hpc-carrier-design-guide-alt/slide-122.jpg) ## Slide 123 ![**Table 23: General Design Rules for High Speed Serial interfaces** Ref Rule / Recommendation :--- :--- 1 High speed pairs should be routed as edge-coupled differential pairs referenced to and closely coupled to an unbroken GND plane. 2 High speed pairs with Nyquist frequencies at 4 GHz or more (PCIe Gen 3,4,5, USB 3.2 Gen2, USB4 Gen 3, DisplayPort, eDP, HDMI, Ethernet KR) require the most PCB routing care. 3 The preferred routing environments for high speed pairs are ranked here, from most desirable to least: (br)1. Symmetric Stripline routing with clean GND planes above and below gives the best signal integrity, but it is often an impractical luxury. The two GND planes should be periodically tied together with stitching vias, every inch or so in both X and Y. (br)2. Asymmetric Stripline routing with the differential pair traces close the primary reference plane, an unbroken GND plane, and further from the secondary plane. The secondary plane can be a GND plane (preferred) or a power plane, possibly with plane splits. (br)3. Asymmetric Dual Stripline routing with high speed pairs close to the primary reference plane, a GND plane. The traces on the “other” routing layer should be as far away as possible and be routed orthogonally to the GND referenced high speed pairs. The “other” traces can be high speed pairs as well, if their primary reference plane is also GND and if the two signal layers are orthogonal. If the routes on the Asymmetric Dual Stripline routing layers are not truly orthogonal (90 degrees) they should be angled at at least 30 degrees relative to each other. (br)4. Microstrip routing. 4 Use as few vias as possible. What few vias there are should be symmetrically placed, such that the + and – lines in the pair “see” the same obstacles and impedance discontinuities. If there is a reference plane change, there must be a stitching via close to the signal via. If the planes are at the same potential (e.g. both GND), direct (DC coupled) stitching vias are used. If the reference planes are at different potentials (not desirable for high speed pairs) then a stitching capacitor is used near the signal vias. These concepts are illustrated in some of the Design Guides referenced in Table 22 above. 5 The higher speed interfaces may need no-stub vias or very short stub vias. This may mean backdrilling the vias with controlled depth drills to hollow out the unused portion of the via barrel. Alternatively, via structures that are built up or are laser drilled and only transit a limited number of layers (say from Layer 1 to Layer 3, with Layer 2 being a GND plane) may be used. Another strategy to avoid via stubs is to arrange that the vias connect layers on opposite sides of the PCB. Then there is no stub (for outer layer to outer layer) or perhaps a shorter stub. Yet another strategy is to use sequential lamination PCB construction. For example, a 12 layer PCB can be built as two 6 layer PCBs and then laminated together to form a 12 layer PCB, with short vias spanning layers1-6 and layers 7-12 and longer vias spanning layers 1-12. 6 If layer transitions must be done, having the high speed signals in question straddle a common GND plane is beneficial as there is no change in the reference layer. For example, if signal pairs are on Layer 1 and 3 and Layer 2 is GND, then there is no change in GND reference plane for the Layer 1 – 3 transitions. If the layer changes result in a change in GND reference planes, then there need to be GND stitching vias close to the trace vias. The stitching vias tie the GND planes together in the vicinity of the signal pair layer transition. 7 It is critically important that the + and – signal lines in a differential pair are closely length matched. The matching is on the order of a few mils for the faster interfaces. This is sometimes called intra-pair length matching. In this document, this is referred to as differential pair + and – length matching. The different pairs in a group (e.g. the four TX+ and – pairs in x4 PCIe link) do not need to be matched very closely at all for many modern interfaces. This is sometimes called inter-pair length matching. In this document, it is referred to as pair to pair length matching (or similar). For some interfaces, this mismatch can be on the order of inches. 8 Coupling capacitors should be discrete 0402 or 0201 package size parts. Do not use capacitor arrays as these can have internal cross coupling that can severely attenuate the differential signal. 9 The plane under the coupling capacitors for the higher speed interfaces should be voided (meaning that rectangular holes about the same size as the capacitor lands, or slightly larger, should be created in the plane) – whether it is a GND or PWR plane. See the Intel Document 627205 referenced in Table 22 above for details. 10 Plane layers that do NOT connect to a particular via should be voided with a circular void around the via barrel. This is done anyway so that the plated via hole does not connect to the plane, but the void should be expanded somewhat to avoid signal coupling to the plane. See the Intel Document 627205 referenced in Table 22 above for details. 11 High speed traces should not be run close to the board edges, especially for long runs parallel to the edge. If they are run this way, they may be creating an EMI hazard. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 121/159](.picmg-com-hpc-carrier-design-guide-alt/slide-123.jpg) ## Slide 124 ![The slide is titled 'PCB Design Rule Summaries' and contains a table with headers 'Ref' and 'Rule / Recommendation'. The table lists two rules: * **12:** 'Sometimes the differential pairs are serpented to adjust the pair length to match another pair. There is usually a “minimum distance to self”, listed in some of the Tables below.' * **13:** 'The fastest interfaces need to account for the “Fiberweave Effect”. This effect is due to the periodic variations in the PCB material dielectric constant caused by the fiberglass weave pattern within a PCB layer. The mitigation strategies are to either arrange that the PCB routes are not parallel (in x or y) to the glass fibers in the weave, or to use a PCB material that does not show this effect. Some of the references in Table 22 have details and illustrations on this effect.' The footer reads 'PICMG® COM-HPC® Carrier Design Guide' on the left and 'Rev. RC2.0d / Dec 7, 2021' followed by '122/159' on the right.](.picmg-com-hpc-carrier-design-guide-alt/slide-124.jpg) ## Slide 125 ![**Header:** PCB Design Rule Summaries **Section 4.3:** PCB Design Rule Summaries - High Speed Differential Pair Serial Interfaces The COM-HPC high speed serial interfaces and two of the fastest single ended interfaces were extensively simulated by a Signal Integrity subgroup during the development of the COM-HPC specification. These efforts resulted in a set of loss budgets, maximum trace length values and other related recommendations. This is documented in Section 6 of the COM-HPC Base Specification. The loss-budget approach allows the findings to be adapted to various different PCB materials (e.g. Standard Loss, Mid Loss, Low Loss and Very Low Loss). The Base Specification recommendations as they apply to COM-HPC Carrier designs are summarized in the Sections below . Some recommendations such as trace length matching requirements are not found in the Base Specification document; rather they are compiled from industry sources. **Section 4.3.1:** NBASE-T Design Rule Summary **Table 24:** NBASE-T Design Rule Summary Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency 1000BASE-T: 250 Mbps / ~80 MHz(br)10GBASE-T: 2.5 Gbps / ~450 MHz 2 Preferred PCB Routing Environment Asymmetric Stripline(br)Unbroken GND plane primary reference(br)(br)Microstrip routing may be used(br)Microstrip is necessary near connectors(br)(br)Quiet unbroken well bypassed power plane may be used as a reference plane. 3 Differential Trace Impedance 100 ohm +/- 10% 4 Single Ended Trace Impedance 55 ohm +/- 15% 5 Max Module Trace Length 1GBASE-T STD Loss PCB Material: ≤ 3000 mils(br)10GBASE-T STD Loss PCB Material: ≤ 1500 mils(br)10GBASE-T MID Loss PCB Material: ≤ 1500 mils 6 Max Carrier Trace Length 1GBASE-T STD Loss PCB Material: ≤ 5000 mils(br)10GBASE-T STD Loss PCB Material: ≤ 2500 mils(br)10GBASE-T MID Loss PCB Material: ≤ 4500 mils 7 Differential Pair +/- Length Matching (Carrier / Module) 5 mil / 5 mil 8 TX Pair to TX Pair Length Matching (Carrier / Module) 500 mil / 500 mil 9 RX Pair to RX Pair Length Matching (Carrier / Module) 500 mil / 500 mil 10 TX Pair to RX Pair Length Matching (Carrier / Module) 500 mil / 500 mil 11 TX Pair to RX Pair Spacing (Carrier / Module) D ≥ 5*H (Asymmetric Stripline) 12 TX or RX pair Spacing to Other Signals DX ≥ 8*H (Asymmetric Stripline) 13 Max Via Stub Length 80 mil See Figure 61 above for definitions of D, DX and H. **Footer Left:** PICMG® COM-HPC® Carrier Design Guide **Footer Right:** Rev. RC2.0d / Dec 7, 2021 123/159](.picmg-com-hpc-carrier-design-guide-alt/slide-125.jpg) ## Slide 126 ![PCB Design Rule Summaries 4.3.2. Ethernet KR Design Rule Summary Table 25: Ethernet KR Design Rule Summary Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency 10G KR: 10.3125 Gtps / ~5.1 GHz(br)25G KR: 25.78125 Gtps / ~12.9 GHz(br)40G KR4: 10.3125 Gtps / ~5.1 GHz(br)100G KR4: 25.78125 Gtps / ~12.9 GHz 2 Preferred PCB Routing Environment Asymmetric Stripline(br)Unbroken GND plane primary reference 3 Differential Trace Impedance 93 ohm +/- 10% 4 Single Ended Trace Impedance 50 ohm +/- 15% 5 Maximum Trace Lengths on Carrier (adapted from COM-HPC Base Specification V1.0 Tables 79, 81, 83) **PHY Down on Carrier**(br)Carrier Trace Lengths Budget (dB) Standard Loss (SL) PCB Material (inches) Mid Loss (ML) PCB Material (inches) Low Loss (LL) PCB Material (inches) Very Low Loss (VLL) PCB Material (inches) 10GBASE-KR 16.0 13.2 21.0 27.4 37.3 25GBASE-KR RS-FEC 20.0 7.9 12.9 16.5 23.1 25GBASE-KR BASE-R FEC 16.0 6.3 10.3 13.2 18.5 25GBASE-KR No FEC 12.0 4.7 7.8 9.9 13.8 **Module1 MAC to Module2 MAC**(br)Carrier Trace Lengths Budget (dB) Standard Loss (SL) PCB Material (inches) Mid Loss (ML) PCB Material (inches) Low Loss (LL) PCB Material (inches) Very Low Loss (VLL) PCB Material (inches) 10GBASE-KR 12.0 9.9 15.7 20.5 28.0 25GBASE-KR RS-FEC 12.0 4.7 7.8 9.9 13.8 25GBASE-KR BASE-R FEC 8.0 3.2 5.2 6.6 9.2 25GBASE-KR No FEC 3.0 1.2 1.9 2.5 3.5 **SFP Connector on Carrier**(br)Carrier Trace Lengths Budget (dB) Standard Loss (SL) PCB Material (inches) Mid Loss (ML) PCB Material (inches) Low Loss (LL) PCB Material (inches) Very Low Loss (VLL) PCB Material (inches) SFP+ Max Carrier Trace 1.50 1.24 1.97 2.56 3.50 SFP28 Max Carrier Trace 2.00 0.79 1.29 1.65 2.31 6 Differential Pair +/- Length Matching (Carrier / Module)(br)Note the very tight matching for 25GBASE-KR(br)This is actually relaxed from some Intel recommendations, per PICMGM consultation with Intel 2.5 mil / 2.5 mil for 10GBASE-KR(br)1.5 mil / 1.5 mil for 25G BASE-KR 7 TX Pair to Pair Length Matching (Carrier / Module) 500 mil / 500 mil (KR4 only; N/A for KR) 8 RX Pair to Pair Length Matching (Carrier / Module) 500 mil / 500 mil (KR4 only; N/A for KR) 9 TX Pair to RX Pair Length Matching (Carrier / Module) 500 mil / 500 mil 10 TX Pair to RX Pair Spacing (Carrier / Module) D ≥ 5*H (Asymmetric Stripline) 11 TX or RX pair Spacing to Other Signals DX ≥ 8*H (Asymmetric Stripline) 12 Max Via Stub Length 10 mil (KR and KR4) PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 124/159](.picmg-com-hpc-carrier-design-guide-alt/slide-126.jpg) ## Slide 127 ![**PCB Design Rule Summaries** **4.3.3. SATA Design Rule Summary** **Table 26: SATA Design Rule Summary** Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency Gen 1: 1.5 Gtps / 0.75 GHz(br)Gen 2: 3 Gtps / 1.5 GHz(br)Gen 3: 6 Gtps / 3 GHz 2 Preferred PCB Routing Environment Asymmetric Stripline(br)Unbroken GND plane primary reference 3 Differential Trace Impedance 85 ohm +/- 10% 4 Single Ended Trace Impedance 45 ohm +/- 15% 5 Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 58 and 60 ) **Device Up on M.2 or mSATA Card**(br) Budget dB Standard Loss (SL) PCB Material Inches Mid Loss (ML) PCB Material Inches Low Loss (LL) PCB Material Inches Very Low Loss (VLL) PCB Material Inches (br) --- --- --- --- --- (br) SATA Gen1 Carrier Trace 1.1 4.07 6.88 8.46 9.17 (br) SATA Gen2 Carrier Trace 1.8 3.91 6.55 8.14 10.11 (br) SATA Gen3 Carrier Trace 2.9 3.74 6.03 7.80 10.21 (br)(br)**Cabled Interface**(br) Budget dB Standard Loss (SL) PCB Material Inches Mid Loss (ML) PCB Material Inches Low Loss (LL) PCB Material Inches Very Low Loss (VLL) PCB Material Inches (br) --- --- --- --- --- (br) SATA Gen1 Carrier Trace 0.7 2.59 4.38 5.38 5.83 (br) SATA Gen2 Carrier Trace 1.1 2.39 4.00 4.98 6.18 (br) SATA Gen3 Carrier Trace 1.8 2.32 3.74 4.84 6.34 6 Differential Pair +/- Length Matching (Carrier / Module) 2.5 mil / 2.5 mil to support SATA Gen 3 7 TX Pair to Pair Length Matching (Carrier / Module) 500 mil / 500 mil 8 RX Pair to Pair Length Matching (Carrier / Module) 500 mil / 500 mil 9 TX Pair to RX Pair Length Matching (Carrier / Module) 500 mil / 500 mil 10 TX Pair to RX Pair Spacing (Carrier / Module) D ≥ 5*H (Asymmetric Stripline) 11 TX or RX pair Spacing to Other Signals DX ≥ 8*H (Asymmetric Stripline) 12 Max Via Stub Length 80 mil **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 125/159](.picmg-com-hpc-carrier-design-guide-alt/slide-127.jpg) ## Slide 128 ![**PCB Design Rule Summaries** **4.3.4. PCIe Design Rule Summary** **Table 27: PCIe Design Rule Summary** Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency Gen 3: 8 Gtps / 4 GHz(br)Gen 4: 16 Gtps / 8 GHz(br)Gen 5: 32 Gtps / 16 GHz 2 Preferred PCB Routing Environment Asymmetric Stripline(br)Unbroken GND plane primary reference 3 Differential Trace Impedance (PCIe data and Ref CLK pairs) 85 ohm +/- 10% 4 Single Ended Trace Impedance 45 ohm +/- 15% 5 Maximum Trace Lengths (from COM-HPC Base Specification V1.0 Tables 52 and 54) **Device Down**(br)Device Down Budget (dB) Standard Loss (SL) PCB Material (inches) Mid Loss (ML) PCB Material (inches) Low Loss (LL) PCB Material (inches) Very Low Loss (VLL) PCB Material (inches) (br)Gen 3 Max Carrier Trace 11.00 10.37 15.65 20.16 26.68(br)Gen 4 Max Carrier Trace 12.50 7.11 10.77 13.44 17.64(br)Gen 5 Max Carrier Trace 13.00 4.23 6.86 8.97 12.65(br)(br)**Device Up**(br)Device Up Budget (dB) Standard Loss (SL) PCB Material (inches) Mid Loss (ML) PCB Material (inches) Low Loss (LL) PCB Material (inches) Very Low Loss (VLL) PCB Material (inches) (br)Gen 3 Max Carrier Trace 6.50 6.13 9.25 11.91 15.77(br)Gen 4 Max Carrier Trace 7.50 4.26 6.46 8.06 10.58(br)Gen 5 Max Carrier Trace 8.00 2.60 4.22 5.52 7.78 6 Differential Pair +/- Length Matching (Carrier / Module) Gen 3, 4, 5: ≤ 2.5 mil / 2.5 mil 7 TX Pair to TX Pair Length Matching (Carrier / Module) RX Pair to RX Pair Length Matching (Carrier / Module) Gen 3, 4, 5: ≤ 500 mil / 500 mil 8 TX Pair to RX Pair Length Matching (Carrier / Module) Gen 3, 4, 5: ≤ 500 mil / 500 mil 9 TX Pair to RX Pair Spacing Gen 3, 4, 5: D ≥ 5H 10 TX or RX pair Spacing to Other Signals Gen 3, 4, 5: DX ≥ 8H 11 PCIe Data Pair Distance to Self 12 PCIe RX or TX Data Pair Length relative to PCIe Reference Clock Pair Length No matching required. The Reference Clock Pairs should be routed as directly as possible. 13 Maximum Via Stub Lengths: Gen 3: ≤ 80 mil(br)Gen 4: ≤ 30 mil(br)Gen 5: ≤ 10 mil 14 Land Pattern and Via Voiding Recommendations: Gen 3, 4, 5: planes adjacent to component lands should be voided. All layers that a PCIe coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching. 15 Fiberweave Effect Mitigation See Fiberweave Effect references in Table 22 above.. Alternatively, use a PCB material that does not exhibit this effect. **PICMG® COM-HPC® Carrier Design Guide** Rev. RC2.0d / Dec 7, 2021 126/159](.picmg-com-hpc-carrier-design-guide-alt/slide-128.jpg) ## Slide 129 ![**Header:** PCB Design Rule Summaries **Section:** 4.3.5. USB 2.0 Design Rule Summary **Table:** Table 28: USB 2.0 Design Rule Summary Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency 480 Mbps / 240 MHz (USB 2.0 High Speed) 2 PCB Routing Environment Asymmetric Stripline is best(br)Microstrip may be used(br)(br)Unbroken GND plane primary reference is best(br)Quiet PWR plane may be used as a reference(br)(br)Plane splits should be avoided(br)If plane splits are unavoidable, stitching capacitors should be used to tie the plane regions together, for AC signals 3 Differential Trace Impedance (USB 2.0 data pair) 90 ohm +/- 10% 4 Single Ended Trace Impedance Circa 45 to 50 ohm 5 Max Carrier Trace Length Cabled Interface: 14 inches(br)Device Down on Carrier: 28 inches 6 Differential Pair +/- Length Matching (Carrier / Module) 20 mil / 20 mil 7 Pair Spacing to other USB 2.0 Pairs (Carrier / Module) D ≥ 5*H (Asymmetric Stripline) 8 TX or RX pair Spacing to Other Signals DX ≥ 8*H (Asymmetric Stripline) 9 Max Via Stub Length 80 mil **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 127/159](.picmg-com-hpc-carrier-design-guide-alt/slide-129.jpg) ## Slide 130 ![PCB Design Rule Summaries 4.3.6. USB 3.2 and USB4 Design Rule Summaries Table 29: USB 3.2 and USB4 Design Rule Summaries Ref Parameter Description Parameter Value :--- :--- :--- 1 Signaling Rate / Nyquist Frequency USB 3.2 Gen 1: 5 Gtps / 2.5 GHz(br)USB 3.2 Gen 2: 10 Gtps / 5 GHz(br)USB4 Gen 2: 10 Gtps / 5 GHz(br)USB4 Gen 3: 20 Gtps / 10 GHz 2 Preferred PCB Routing Environment Asymmetric Stripline(br)Unbroken GND plane primary reference 3 Differential Trace Impedance (USB SuperSpeed Pairs) USB 3.2 Gen 1: Historically was 90 ohm(br)Going forward, 85 ohm is OK(br)USB 3.2 Gen 2: 85 ohm +/- 10%(br)USB4 Gen 2: 85 ohm +/- 10%(br)USB4 Gen 3: 85 ohm +/- 10% 4 Single Ended Trace Impedance 45 ohm +/- 15% 5 Maximum Carrier Trace Lengths (from COM-HPC Base Specification V1.0 Tables 67 and 69 ) **USB SuperSpeed Device Down**(br)(br) Budget (dB) Standard Loss (SL) PCB Material (Inches) Mid Loss (ML) PCB Material (Inches) Low Loss (LL) PCB Material (Inches) Very Low Loss (VLL) PCB Material (Inches) :--- :--- :--- :--- :--- :--- USB 3.2 Gen 1 3.2 4.7 7.6 10 12.8 USB 3.2 Gen2 5.5 4.7 7.6 9.8 13.4 USB4 Gen 2 5.5 4.7 7.6 9.8 13.4 USB4 Gen 3 10.5 5.2 7.6 10.7 15 **USB SuperSpeed Cabled Interface** Budget (dB) Standard Loss (SL) PCB Material (Inches) Mid Loss (ML) PCB Material (Inches) Low Loss (LL) PCB Material (Inches) Very Low Loss (VLL) PCB Material (Inches) :--- :--- :--- :--- :--- :--- USB 3.2 Gen 1 3.2 4.7 7.6 10 12.8 USB 3.2 Gen 2 5.5 4.7 7.5 9.8 13.4 USB4 Gen 2 5.5 4.7 7.5 9.8 13.4 USB4 Gen 3 10.5 NA NA NA NA The values marked in red in the Table just above indicate that there is insufficient overall margin for a direct cabled interface with USB 3.2 Gen 2 or USB4 Gen 2 or USB4 Gen 3. Redrivers or retimers placed close to the cable connectors are advised. The Carrier maximum trace lengths in the Device Down Table above may be used for the run between the COM-HPC Module and the redrivers or retimers. 6 Differential Pair +/- Length Matching (Carrier / Module) ≤ 2.5 mil / 2.5 mil 7 TX Pair to TX Pair Length Matching (Carrier / Module)(br)RX Pair to RX Pair Length Matching (Carrier / Module) ≤ 100 mil / 100 mil(br)Applies only to x2 configurations(br)(2 TX pairs and 2 RX pairs) 8 TX Pair to RX Pair Length Matching (Carrier / Module) ≤ 100 mil / 100 mil 9 TX Pair to RX Pair Spacing D ≥ 5H 10 TX or RX pair Spacing to Other Signals DX ≥ 8H 11 TX or RX Data Pair Distance to Self 13 Maximum Via Stub Lengths: USB 3.2 Gen 1 ≤ 80 mil(br)USB 3.2 Gen 2 ≤ 30 mil(br)USB4 Gen 2 ≤ 30 mil(br)USB4 Gen 3 ≤ 10 mil PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 128/159](.picmg-com-hpc-carrier-design-guide-alt/slide-130.jpg) ## Slide 131 ![The slide is titled 'PCB Design Rule Summaries' and contains a table with three columns: Ref, Parameter Description, and Parameter Value. **Row 1:** * **Ref:** 14 * **Parameter Description:** Land Pattern and Via Voiding Recommendations: * **Parameter Value:** Gen 3, 4, 5: planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching. **Row 2:** * **Ref:** 15 * **Parameter Description:** Fiberweave Effect Mitigation * **Parameter Value:** See Fiberweave Effect references in Table 22 above. Alternatively, use a PCB material that does not exhibit this effect. **Footer:** * Left: PICMG® COM-HPC® Carrier Design Guide * Right: Rev. RC2.0d / Dec 7, 2021 129/159](.picmg-com-hpc-carrier-design-guide-alt/slide-131.jpg) ## Slide 132 ![**Header:** PCB Design Rule Summaries **Title:** 4.3.7. DisplayPort Design Rule Summary **Table Title:** Table 30: DisplayPort Design Rule Summary **Table Content:** * **1 Preferred PCB Routing Environment:** Asymmetric Stripline Unbroken GND plane primary reference Microstrip is necessary in region near DP connector * **2 Differential Trace Impedance:** 85 ohm +/- 10% * **3 Single Ended Trace Impedance:** 45 ohm +/- 15% * **4 Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Tables 86 and 87 ):** * **Upper Nested Table:** * **Headers:** DisplayPort Cabled Interfaces No Carrier Redriver Bit Rate / Nyquist (per Lane) Gbps / GHz Standard Loss PCB Material inches Mid Loss PCB Material inches Low Loss PCB Material inches Very Low Loss PCB Material inches * **Rows:** * DP HBR: 2.7 / 1.3 3.2 5.4 6.7 8.3 * DP HBR2: 5.4 / 2.7 2.9 4.6 6.0 7.8 * DP HBR3: 8.1 / 4.0 **2.3** (Red) 3.6 4.7 6.3 * DP UHBR10: 10 / 5.0 **1.65** (Red) 2.6 3.4 4.6 * DP UHBR13.5: 13.5 / 6.7 **1.8** (Red) 3.0 3.8 5.3 * DP UHBR20: 20 / 10 **1.3** (Red) **2.2** (Red) **2.8** (Red) 3.8 * **Lower Nested Table:** * **Headers:** DisplayPort With Carrier Retimer/Redriver Bit Rate / Nyquist (per Lane) Gbps / GHz Standard Loss PCB Material inches Mid Loss PCB Material inches Low Loss PCB Material inches Very Low Loss PCB Material inches * **Rows:** * DP2.0 UHBR13.5: 13.5 / 6.7 5 8 10.4 14.4 * DP2.0 UHBR20: 20 / 10 3.7 6 7.6 10.7 * **Note:** Red text in upper table above indicates that there is insufficient margin in the overall channel and that that particular configuration should not be used. * **5 Differential Pair +/- Length Matching (Carrier / Module):** ≤ 2.5 mil / 2.5 mil * **6 Data Pair to Pair Length Matching (Carrier / Module):** ≤ 100 mil / 100 mil * **7 Pair to Pair Spacing:** D ≥ 5H * **8 TX or RX pair Spacing to Other Signals:** DX ≥ 8H * **9 TX or RX Data Pair Distance to Self:** (Empty) * **10 Maximum Via Stub Lengths:** 80 mil (per lane bit rate ≤ 5.4 Gtps) 30 mil (per lane bit rate ≤ 13.5 Gtps) 10 mil (per lane bit rate 20 Gtps) * **11 Land Pattern and Via Voiding Recommendations:** For DP modes with bit-rate at or above 8 Gtps per lane: Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 130/159](.picmg-com-hpc-carrier-design-guide-alt/slide-132.jpg) ## Slide 133 ![**Header:** PCB Design Rule Summaries **Section Title:** 4.3.8. eDP Design Rule Summary **Body Text:** Embedded DisplayPort signal integrity considerations were not explicitly addressed by the COM-HPC Signal Integrity subgroup. As such, it would be reasonable for COM-HPC Carrier designers to use the COM-HPC DisplayPort Design Rule Summary outlined in Section 4.3.7 for eDP layouts. For eDP panels, only the lower bit rate formats (HBR, HBR2, HBR3) are likely to come into play. Alternatively, Carrier Designers can consult some of the Intel and AMD Design Guides listed in Table 22 above for eDP guidance. The Intel Document 627205 in particular has lots of eDP advice. However, these Design Guides are targeting laptop and motherboard designs and it can be tricky to map these recommendations to the COM-HPC system case. The general rule of thumb is that about half of the motherboard or laptop board budget goes to the COM-HPC Module and half to the COM-HPC Carrier. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 131/159](.picmg-com-hpc-carrier-design-guide-alt/slide-133.jpg) ## Slide 134 ![This slide presents a 'PCB Design Rule Summary' specifically for HDMI design rules, titled '4.3.9. HDMI Design Rule Summary'. It features a large table labeled 'Table 31: HDMI Design Rule Summary' which lists various parameters and their corresponding values. **Table Content:** * **Header:** Ref Parameter Description Parameter Value * **Row 1:** Ref 1, 'Preferred PCB Routing Environment', 'Asymmetric Stripline Unbroken GND plane primary reference Microstrip may necessary in the region near the HDMI connector' * **Row 2:** Ref 2, 'Differential Trace Impedance', '85 ohm +/- 10% (on Carrier before HDMI buffer) 100 ohm +/- 10% (after buffer)' * **Row 3:** Ref 3, 'Single Ended Trace Impedance', '45 ohm +/- 15% (before buffer) 55 ohm +/- 15% (after buffer)' * **Row 4:** Ref 4, 'Maximum Carrier Trace Lengths (adapted from COM-HPC Base Specification V1.0 Table 88 )'. This row contains a nested table with headers: 'HDMI Buffer / Driver on Carrier near HDMI Connector', 'Bit Rate / Nyquist (per Lane) Gbps / GHz', 'Standard Loss PCB Material inches', 'Mid Loss PCB Material inches', 'Low Loss PCB Material inches', and 'Very Low Loss PCB Material inches'. * Row 4a: HDMI 1.4 3 / 1.5 (Empty) (Empty) (Empty) (Empty) * Row 4b: HDMI 2.1 6 / 3 (Empty) (Empty) (Empty) (Empty) * Row 4c: HDMI 2.1 12 / 6 4 5.75 6.75 10 * **Row 5:** Ref 5, 'Differential Pair +/- Length Matching (Carrier / Module)', '≤ 2.5 mil / 2.5 mil' * **Row 6:** Ref 6, 'Data Pair to Pair Length Matching (Carrier / Module)', '≤ 100 mil / 100 mil' * **Row 7:** Ref 7, 'Pair to Pair Spacing', 'D ≥ 5H' * **Row 8:** Ref 8, 'TX or RX pair Spacing to Other Signals', 'DX ≥ 8H' * **Row 9:** Ref 9, 'TX or RX Data Pair Distance to Self', (Empty) * **Row 10:** Ref 10, 'Maximum Via Stub Lengths:', '80 mil (per lane bit rate ≤ 6 Gtps) 30 mil (per lane bit rate = 12 Gtps)' * **Row 11:** Ref 11, 'Land Pattern and Via Voiding Recommendations:', 'For HDMI modes with bit-rate at 12 Gtps per lane: Planes adjacent to component lands should be voided. All layers that a coupling via passes through should be voided, unless the via connects on that layer. See the Intel Document 627205 referenced in Table 22 above for illustrations on voiding and length matching.' **Footer:** PICMG® COM-HPC® Carrier Design Guide (Left) Rev. RC2.0d / Dec 7, 2021 132/159 (Right)](.picmg-com-hpc-carrier-design-guide-alt/slide-134.jpg) ## Slide 135 ![**Header:** PCB Design Rule Summaries **Section Title:** 4.4. PCB Design Rules for Single Ended (SE) Interfaces **Table Title:** Table 32: Design Rules for Single Ended Interfaces **Table Content:** Ref Rule / Recommendation :--- :--- 1 Most COM-HPC SE traces may be routed using a 55 ohm +/- 15 %. trace impedance. The BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx nets are the exceptions and should be routed as 50 ohm +/- 15% 2 SE nets may be routed as Stripline or Microstrip traces, referenced to a GND plane or to a quiet PWR plane. 3 Crossing plane splits should be avoided for the faster SE interfaces (BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx). If these nets do cross a split in the reference plane, then the split should be “stitched” with a small capacitor that bridges the split for AC signals. 4 SE signals with higher bit rates and faster edge rates need more routing care than slower signals. The higher bit rate SE signals include: (br) • BOOT_SPI_xxx Up to circa 100 Mhz in some cases; up to circa 50 MHz is more typical (br) • eSPI_xxx Up to circa 50 MHz (br) • GP_SPI_xxx Up to circa 50 MHz (br) • I3C Up to circa 33 MHz (br) • Soundwire Up to circa 12 MHz (br) • Various I2C signals Up to circa 1 MHz or 400 kHz in some cases but more typically are 100 kHz max (br) • UART_xxx Up to circa 1 MHz in some cases – usually less – 115 kHz max is more common (br) COM-HPC SE signals not listed just above are likely to be very slow, almost static in many cases. (br) “More routing care” can mean: (br) • Signal should be GND referenced (br) • No plane split crossings (br) • Stripline routing preferred, with primary reference to GND (br) • Series damping resistors for the signals listed as 50 MHz or more (br) • BOOT_SPI_xxx, eSPI_xxx and GP_SPI_xxx have specific routing rules (see below) 5 The COM-HPC BOOT_SPI_xxx signals are arranged in a “balanced tree” topology. Full details can be found in the COM-HPC Base Specification Version 1.0 Section 6.11.1. (br) Up to 4 BOOT_SPI_xxx devices are allowed, but 3 are on the Module and only 1 (or 0) are allowed on the Carrier. The trace lengths for the BOOT_SPI Data and Clock between the COM-HPC connector balls and the Carrier device must be at least 2000 mils long and no more than 3000 mils long. This is to “balance” the on-Module and off-Module branches of the tree. The Data and Clock lines for this branch of the tree should be length matched to within 250 mil. A series damping resistor is recommended. Refer to the COM-HPC Base specification for more details and a diagram. (br) The Chip Select line associated with the Carrier BOOT_SPI_xxx signals does not need length matching and should be routed as directly as possible. 6 The COM-HPC eSPI_xxx signals are arranged in a “balanced tree” topology. Full details can be found in the COM-HPC Base Specification Version 1.0 Section 6.11.2. (br) Up to 4 eSPI_xxx devices are allowed: up to 2 on the Module and up to 2 on the Carrier. The trace lengths for the eSPI Data and Clock lines between the COM-HPC connector balls and the Carrier device(s) must be at least 2000 mils long and no more than 3000 mils long. This is to “balance” the on-Module and off-Module branches of the tree. A series damping resistor is recommended. There should be separate branches in the tree if there are 2 Carrier devices. Refer to the COM-HPC Base specification for more details and a diagram. (br) The Chip Select line associated with the Carrier eSPI_SPI_xxx signals does not need length matching and should be routed as directly as possible. 7 GP_SPI_xxx net routing should follow the same rules as the eSPI_xxx nets. If there are 2 GP_SPI devices, there should be 2 separate tree branches. 8 If any SE signals leave the Carrier and are exposed to the outside world and to potential contact with users, there should be both EMI and ESD mitigation measures implemented close to the connectors that face outside. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 133/159](.picmg-com-hpc-carrier-design-guide-alt/slide-135.jpg) ## Slide 136 ![**Header:** Mechanical Considerations **5. Mechanical Considerations** **5.1. Heat Spreader / Module / Carrier Attachment Details** **5.1.1. Heat Spreader to Module Attachment Notes** The COM-HPC Base Specification calls out Module PCB mounting holes that are are to align with corresponding Heat Spreader Plate, Carrier board and possibly system chassis mounting holes or features to hold the entire assembly together. However, the COM-HPC Base Specification also recommends that there be a separate set of vendor-specific holes to secure the Heat Spreader Plate (HSP), the Thermal Interface Materials (TIM) and the COM-HPC Module board together as a subsystem that can be shipped as a unit, independent of the larger system that includes the Carrier and other components (chassis, heat sinks, etc.). This is desirable as the TIM stack can be a sensitive, precision assembly that is best handled once and only once by the Module vendor. The reference to separate, design specific holes in the Module and HSP for this purpose are in the COM-HPC Base Specification V1.0 in Section 7.5.4 Table 93 Ref 5, reproduced here: The implementation specific holes / spacers / standoffs used to secure the HSP to the Module should be different from those used at the COM-HPC defined mounting hole sites. The x-y positions, the number of the vendor-specific HSP / TIM / Module attachment points and other implementation details are not defined by the COM-HPC specification document. However, a typical vertical cross section diagram of how this can be implemented is shown in Figure 62 below. **Figure 62: Vendor Specific Heat Spreader to Module Attachment – Bottom Side Module PCB Access** (Diagram Description: A vertical cross-section diagram showing a blue rectangular plate on top, held down by purple vertical standoffs. Below the plate is a pink layer, followed by an orange block in the center. Below that is a green rectangular board. Black vertical standoffs are positioned at the far left and right edges. Yellow rectangular connectors are at the very bottom left and right.) **Legend:** * **(Blue Box)** Heat Spreader Plate – Vendor Specific Implementation Details * **(Purple Box)** HSP to Module Spacers or Standoffs – Vendor Specific Locations and Implementation Details * **(Pink Box)** TIM – Vendor Specific Implementation Details – Typically, Compliant Foam or Phase Change Material * **(Orange Box)** CPU / SOC Die or Lid * **(Green Box)** Module PCB * **(Black Box)** Spacers / Standoffs at COM-HPC Defined X-Y Positions, For Module Mounting – Vendor Specific Implementation Details * **(Yellow Box)** Module to Carrier Connectors **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 134/159](.picmg-com-hpc-carrier-design-guide-alt/slide-136.jpg) ## Slide 137 ![Mechanical Considerations 5.1.2. Heat Spreader / Module Assembly Attachment to Carrier and Chassis Figures 63 through 66 illustrate a variety of hardware mechanical component and assembly options to secure the COM-HPC HSP, Module, Carrier and system chassis together, Figure 63: Heat Spreader Assembly Mounting to Carrier – Bottom Side Screw Access Detail B Cross section view of Detail B Heatspreader (HSP) CPU Module Carrier Board M2.5 Screw and Washer Carrier Board Stand-Off (Ø 2.7 clearance hole) HSP Stand-Off (M2.5 thread) PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 135/159](.picmg-com-hpc-carrier-design-guide-alt/slide-137.jpg) ## Slide 138 ![The slide is titled 'Figure 64: Heat Spreader Assembly Mounting to Carrier – Top Side Screw Access' under the header 'Mechanical Considerations.' It displays a top diagram showing stacked layers with a circle labeled 'Detail A,' followed by a 'Cross section view of Detail A.' This detailed view labels the following components with arrows: 'M2.5 Screw (flat head),' 'HSP Stand-Off (ø 2.7 clearance hole),' 'Baseboard Stand-Off (M2.5 thread),' 'Heatspreader (HSP),' 'CPU Module,' and 'Carrier Board.' The footer reads 'PICMG® COM-HPC® Carrier Design Guide' on the left and 'Rev. RC2.0d / Dec 7, 2021' with page number '136/159' on the right.](.picmg-com-hpc-carrier-design-guide-alt/slide-138.jpg) ## Slide 139 ![**Header:** Mechanical Considerations **Title:** Figure 65: Heat Spreader Assembly Mounting to Carrier With Broaching Nut – Top Side Screw Access **Diagram Labels:** * Detail A * Cross section view of Detail A * M2.5 Screw (flat head) * Heatspreader Stand-Off (Ø 2.7 clearance hole) * Broaching Stand-Off (M2.5 thread) * Heatspreader * CPU Module * Carrier Board **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 137/159](.picmg-com-hpc-carrier-design-guide-alt/slide-139.jpg) ## Slide 140 ![Mechanical Considerations Figure 66: Heat Spreader Assembly Mounting to Carrier and Chassis – Top Side Screw Access Detail A Cross section view of Detail A M2.5 Screw (flat head) Heatspreader Stand-Off (Ø 2.7 clearance hole) Carrier Board Stand-Off (Ø 2.7 clearance hole) Broaching Stand-Off (M2.5 thread) Heatspreader CPU Module Carrier Board Chassis PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 138/159](.picmg-com-hpc-carrier-design-guide-alt/slide-140.jpg) ## Slide 141 ![Mechanical Considerations Some useful vendors and vendor part numbers for mechanical parts that may be used in Figures 63 through 66 above are listed here: * PEM TSOS-M25-1500 * M2.5 threaded blind standoff for sheet metal / plate use - 15 mm overall length (for Client) * PEM TSOS-M25-1800 (18 mm for Server) * M2.5 threaded blind standoff for sheet metal / plate use - 18 mm overall length (for Server) * www.pemnet.com * Würth 9774050951 5 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer * Würth 9774100951 10 mm Length x 5.1 mm OD x 2.7 mm ID SS SMT Clearance Hole Spacer * May be SMT soldered to Carrier Top side as shown in the Figures 63 and 66 above * www.wuerth.com * EFCO (Taiwan) has numerous mechanical parts for COM-HPC and other Module standards * www.efcotec.com * Or use a search engine, look for “ efcotec com accessories ” PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 139/159](.picmg-com-hpc-carrier-design-guide-alt/slide-141.jpg) ## Slide 142 ![**Header:** Mechanical Considerations **5.2. Alternative COM-HPC Board Stack Assembly Suggestion** An alternative COM-HPC board stack assembly method and set of mechanical hardware is presented just below. This material has been submitted by Samtec. These assembly mechanics make use of Samtec defined connector hardware components, known as JSOM, for “Jack Screw Stand-off – Micro”. These mechanical hardware parts are used in PC-104 and in some VITA assemblies. Samtec JSOM data sheets and drawings are readily available online. This approach defines an assembly stack allowing a COM-HPC Module and Carrier to be mounted to a metal chassis which is below the Carrier. This assembly method does not include considerations for a Heat Spreader Plate. Thermal management components such as heat sinks or HSP / heat sink combinations would be handled on separate holes. The ‘ASP’ references in some of the Figures below are Samtec designations for “Application Specific Parts”. There is an ASP summary in Figure 73 several pages below. **5.2.1. Precision Jack Screw Standoffs** Precision jack screw standoff hardware (referred to as JSOM by Samtec) can be used to help mating and unmatting procedures in high-normal-force, multi-connector applications. They work like traditional stand-offs but contain an internal machined hex screw that can be turned in a counterclockwise direction to lift the Module Card from the Carrier Board. JSOM based assemblies can mitigate damage to the connector pins, components, boards, and solder joints. **Assembly / Dis-assembly Procedure Overview** Before mating the Module Card to the Carrier Board, use a 1.5mm hex driver to turn the JSOM screw clockwise until the screw is fully seated in the JSOM standoff. **Figure 67:** JSOM (Jack Screw Standoff – Micro) Diagram and Application Cutaway **Diagram Labels:** * LOCKING NUT M 2.5 * FULL JSOM & STANDOFF ASSEMBLY * JSOM SCREW * JSOM STANDOFF * STANDOFF (SO) * SCREW M 2.5 * ASSEMBLY CUT-AWAY TO SHOW DETAILS OF JSOM & STANDOFF * MODULE PCB * CARRIER PCB * METAL CHASSIS **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 140/159](.picmg-com-hpc-carrier-design-guide-alt/slide-142.jpg) ## Slide 143 ![Mechanical Considerations Once all four JSOM screws are fully seated, apply even downward pressure over the J1 and J2 connector regions to mate the Module Card to the Carrier Board. Once the Module Card is fully mated secure the Module Card to the Carrier Board with four hex nuts and lock washers as shown in Figure 68 (a). Use a torque wrench to tighten the hex nuts to 3.0 (+/- 0.5) in-lbs. Tighten the nuts in an alternating diagonal pattern shown in Figure 68 (b). For detailed mating recommendations, refer to section 7.5.5 of the COM-HPC® Module Base Specification, Revision 1.0. Figure 68: (a) Hex Nuts to Torque (b) Diagonal Torque Application / De-application (c) Hex Screw Turns Hex Nut and Lock Washer (torque to 3.0 in-lbs) Hex Nuts JSOM STANDOFF (a) Alternating Diagonal Pattern 1 4 Size D 3 2 (b) Use Hex Key to Lift Module PCB (1/4 turns until connectors unmated) 1.5mm Hex Key (c) Figure 3. (a) Hex nut torque, (b) diagonal unmated pattern, (c) hex screw turning ratio Unmating the Module Card from the Carrier Board To unmated the boards remove the locking nuts and washers. Using the diagonal pattern shown in Figure 68 (b) insert the 1.5mm hex key shown in Figure 68 (c) into the JSOM screw labeled 1 and turn counterclockwise a ¼ turn. Repeat this procedure for all JSOM screws labeled 2, 3, and 4 until the connectors unmated. The Module Card can then be removed from the Carrier Board. Figure 69: COM-HPC Stack Dis-assembly Procedure Using JSOM Hardware JSOM FULLY SEATED JSOM 0.26 (.010) SO (a) JSOM PARTIAL LIFT MODULE PCB JSOM 1.76 (.069) SO (b) JSOM FULLY LIFTED MODULE PCB CONNECTORS UNMATED JSOM 3.26 (.128) ASP-209946-01 ASP-209948-01 SO (c) PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 141/159](.picmg-com-hpc-carrier-design-guide-alt/slide-143.jpg) ## Slide 144 ![**Header:** Mechanical Considerations **5.3. Carrier Board Stiffener** FEM (Finite Element Method) mechanical simulations were conducted to understand the amount of deflection and temporary stress that can occur in the Carrier Board as it is being mated with a Module Card. The simulations assumed that the Carrier Board was fabricated using standard 0.0625' thick FR4 material and fixed to a stiff chassis using metal stand-offs attached to the mounting holes adjacent to both the Carrier P1 and P2 connectors. As shown in Figure 70, a downward force was applied evenly over the length of the connector, and the amount of deflection was measured. The results confirmed that 0.0625' Carrier Boards should be supported using some type of stiffening mechanism. **Figure 70: FEM Simulation Results – 0.0625' FR4 Carrier – No Stiffener** (Image Description: A 3D model of a rectangular board supported by two yellow pillars, colored with a gradient map indicating deflection (red to blue) with purple arrows showing downward force. A legend on the right lists 'UY (in)' values.) **Legend Values:** UY (in) 0.024 0.015 0.007 -0.002 -0.010 -0.018 -0.027 -0.035 -0.044 -0.052 -0.061 -0.069 -0.078 **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 142/159](.picmg-com-hpc-carrier-design-guide-alt/slide-144.jpg) ## Slide 145 ![**Mechanical Considerations** Note however that the stiffness of a piece of sheet material such as a PCB is proportional to the **cube** of the sheet thickness. Hence using a thicker PCB may relax or obviate the need for a Carrier stiffener. PCB thickness of 0.079' (2mm), 0.092' and even 0.125' are common. However, be aware that if the Carrier uses through hole parts (typically for I/O connectors) then increasing the PCB thickness too much will result in a soldering problem as the through hole part leads need protrude beyond the PCB a bit for wave soldering. A metal simple stiffener design is shown in Figure 71 below with the corresponding keep-out regions shown in Figure 72. This Figure shows the Carrier PCB Top side. The Carrier stiffener keep-out regions are on the Bottom side of the Carrier board, as indicated by the dashed lines. When designing a Carrier Board stiffener there are some points to consider. * The stiffener should provide uniform support directly underneath the Carrier Board connector and span the entire length of the connector region. This should be done for both the P1 and P2 Carrier connectors. * The stiffener should be securely anchored to the chassis through mechanical mounting hardware or attached to the bottom side of the Carrier Board using an adhesive. * The stiffener thickness should be as thick as the application allows. * Care must be taken when using conductive materials such as steel or alloys. * This stiffener concept will require a keep-out region where peripheral components cannot be placed. * It may be necessary to exclude via pads from the PCB Bottom side in the in the keep-out region, or to insulate vias from a metallic stiffener. Kapton tape is the usual remedy for this situation. But such a solution may not be appropriate for high – vibration situations. A thicker, compliant foam material may also be considered. **Figure 71: Mechanical Carrier Stiffener Possibility** The slide displays three technical diagrams of the stiffener: 1. **Top Image:** An isometric view of a long, rectangular metal plate featuring parallel ribs running along its length and mounting holes at both ends. 2. **Bottom Left Diagram:** A 2D top-down technical drawing with dimensions including 'Ø 3.40 (4 PLS)', vertical measurements (18.41, 14.000, 6.000, 0), and horizontal measurements (7.00, 10.000 (2 PLS), 13.00, 87.00 (2 PLS), 90.000 (2 PLS), 93.00, 100.00). 3. **Bottom Right Diagram:** A side-view cross-section showing dimensions such as '0.91 (TYP)', '16.83', '12.23', '7.63', '3.03', '0', 'R0.25', '3.01', and '2.50'. A small detail view to the far right shows a hatched cross-section labeled 'Ø 3.40 REF' and '2.50 REF'. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 143/159](.picmg-com-hpc-carrier-design-guide-alt/slide-145.jpg) ## Slide 146 ![**Header:** Mechanical Considerations **Title:** Figure 72: Carrier Board Stiffener Keep-Out Region (Seen Through Carrier) **Diagram Description:** A large green rectangle representing a board. Near the top edge, there is a horizontal rectangular slot (connector) surrounded by a dashed box with two mounting holes. Near the bottom edge, there is a similar horizontal rectangular slot surrounded by a dashed box with two mounting holes. **Dimensions (Verbatim):** * **Left side:** 6.00 (.236) * **Right side:** 4.41 (.174) * **Bottom Left:** 10.00 (.394) * **Bottom Right:** 10.00 (.394) * **Bottom Center:** 100.00 (3.937) (KEEP OUT) * **Right Vertical:** 18.41 (.725) (KEEP OUT) **Note:** Dimensions in the two Figures above are in mm. **Footer:** * **Left:** PICMG® COM-HPC® Carrier Design Guide * **Right:** Rev. RC2.0d / Dec 7, 2021 * **Right (below rev):** 144/159](.picmg-com-hpc-carrier-design-guide-alt/slide-146.jpg) ## Slide 147 ![**Header:** Mechanical Considerations **Figure Title:** Figure 73: Application Specific Part Number (ASP) Reference Guide **Diagram Labels & Dimensions:** * JSOM ASSEMBLY (ASP-222919-01) * MODULE PCB STIFFENING CLIP (ASP-222928-01-C) * CARRIER PCB STIFFENING CLIP (ASP-222927-01-C) * STANDOFF ASSEMBLY (ASP-222923-01) * 2.50 (.098) NON-STANDARD STANDOFF REQUIRED - SEE DETAIL VIEW * 10.15 (.400) * 15.15 (.596) * 12.65 (.498) NON-STANDARD STANDOFF REQUIRED - SEE DETAIL VIEW **Detail Views:** * **STANDOFF ASSEMBLY ASP-222923-01** * THREAD MUST BE SPECIFIED 2.5mm LONGER THAN .062 PCB THICKNESS) * HEIGHT OF STANDOFF BODY MUST BE 2.5mm SHORTER THAN PCB SPACING * **JSOM ASSEMBLY ASP-222919-01** * 6.16 (NON-STD) * 6.00 (STD) **Text Section:** **Non-Metallic Stiffener Possibilities** A simple but effective Carrier board stiffener option is to fabricate a simple non-metallic rectangular bar that is positioned between the Carrier PCB Bottom side and the system chassis. The stiffener bar extent shadows the Carrier connector and the adjacent mounting holes as shown by the dashed lines in Figure 72 above. Nylon is a suitable material. Metal press fit inserts at the mounting hole positions may be beneficial. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 145/159](.picmg-com-hpc-carrier-design-guide-alt/slide-147.jpg) ## Slide 148 ![**Appendices** **6. Appendices** **6.1. Appendix A: Synchronous Ethernet** Synchronous Ethernet, or SyncE, is an ITU-T standard that allows precision timing information to be embedded into Ethernet physical layer. This signal can be correlated to an external high precision master clock. It is important to telecom providers as the telecom infrastructure moves away from TDM based standards such as SONET and to packet based Ethernet implementations. **Introduction to SyncE** * Synchronous Ethernet (SyncE) distributes a frequency signal through Ethernet * - Defined in ITU-T G.8261, G.8262, G.8262.1, G.8264 * GbE and above always§ sends symbols (data or idle) * SyncE recovers received data rate * - Ethernet requires ±100 ppm clocking * - Receivers must handle up to 200 ppm clock delta * - SyncE saves off a fractional rate to drive DPLL **External DPLLs** * External DPLLs can take in multiple clock sources * - 1PPS and 10 MHz inputs–GPS/GNSS input(s) * - often 1PPS as well * - SyncE recovered clocks * - IEEE 1588/PTP-driven clocks (also often 1PPS) * - Local oscillator * - Long-term oscillator (TCXO or OCXO) * DPLL sets a priority of inputs * All outputs driven synchronously off selected input(s) * -TX side of all PHYs and/or SoCs driven from PLL clock **SyncE on PHYs** * Some SoCs support SyncE on internal PHYs * Some external PHYs support SyncE clock recovery * Each RX port adapts to meet incoming data rate * - Each RX port may be different * - Fractional clock rate from selected port(s) sent to DPLL * Tx side driven from DPLL * - All TX ports driven at same rate * Driver support for SyncE with external DPLLs may vary **Implications for Modules / Pin-outs** * If Module SoC and Carrier Board PHY both need SyncE, need SyncE info across connectors * Carrier sends recovered clock(s), 1PPS input(s) * Module sends TX clock(s), 1PPS output(s) PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 146/159](.picmg-com-hpc-carrier-design-guide-alt/slide-148.jpg) ## Slide 149 ![**Header:** Appendices **Title:** Figure 74: Synchronous Ethernet Overview **Diagram Content:** The diagram displays a block diagram connecting an 'SoC' (blue box) and a 'DPLL' (yellow box) with various external signals and components. **SoC Block (Blue Box):** * '25 MHz' (connected to a crystal symbol) * 'From DPLL Out7p' (connected to an 'SE-to-DS' converter) * 'NAC_OPPS_P/N' * 'NAC_CLK_SYNCED_P/N' * 'ETH_I2C_CLK2' * 'ETH_I2C_DATA2' * 'NAC_TIME_SYNC_P/N' * 'SoC' * 'SRC_CLKREQ5_N_GPP_W81' * 'NAC_TIME_REF_P/N' * 'NAC_CLKIN_EREF0_P/N' **DPLL Block (Yellow Box):** * 'SDA' * 'SCL' * 'OUT0p' * 'OUT1p' * 'REF4p' * 'REF0n' * 'REF3p' * 'REF1p/n' * 'OUT3p/n' * 'OUT5p/n' * 'OUT6p' * 'OUT7p' * 'DPLL' * 'REF4n' * 'OSCB' **External Connections & Labels:** * 'PPS Output' pointing to an 'SMA' circle * '10M Sync Clock Output' pointing to an 'SMA' circle * 'Internal PHY clock for SyncE' * '1588 Time Sync Clock' * 'PLL_INT_N' * 'PPS Output To ICX-D' * 'PPS from GPS or 1588' pointing to an 'SMA' circle * 'DS-to-SE' (next to a splitter symbol) * 'External Sync Clock' pointing to an 'SMA' circle * 'SyncE Clock Output from SoC' (connected via an 'AC Coupled' symbol) * 'OCXO' box pointing to 'REF4n' * 'XO' box pointing to 'OSCB' **Notes Section:** Notes: 1. DS = Differential; SE = Single-ended 2. PPS from GPS and 1588 Eth can be input to DPLL 3. ESD protection needs be considered for SMA header 4. Any unused LVDS signals should be left unconnected **Legend:** * 'Differential Signal' (next to a double line) * 'Single-ended Signal' (next to a single line) **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 147/159](.picmg-com-hpc-carrier-design-guide-alt/slide-149.jpg) ## Slide 150 ![**Appendices** **Figure 75: Synchronous Ethernet Example Implementation** **Diagram Components and Labels:** * **Top Left:** Circle labeled 'SMA' with '1PPS' below it. Line labeled '156,25 to PV' connects to a green box labeled 'PHY'. * **Top Right:** Line labeled 'RCLK_A/B' connects to 'SDP 0/1'. Two circles: 'SMA' with '1PPS' below, and 'GPS' with '1PPS' below. Boxes labeled 'SDP 6' and 'SDP 7'. * **Inside Grey 'Module' Area:** * **Left:** Box 'SDP 5' (connected to SMA 1PPS and 'i225'). Box 'SDP 2/3'. Box 'StoD'. Box 'i225'. * **Center:** Blue box 'SoC' connected to lines 'NAC_TIME_SYNC', 'INT_N', 'TIME_REF', 'CLK_EREF0'. To its right, a white box 'DtoS' connected to 'CLK_SYNCE0' and 'ON_PPS_OUT'. * **Bottom Center:** Yellow box 'DPLL'. Contains columns of pins: 'OUT0' through 'OUT9' and 'IN 0' through 'IN 4'. Also 'XTAL'. * **Right:** White boxes 'XO' and 'OCXO'. Small text 'No Stuff' near 'IN 2' and 'IN 3'. **Table 33: SDP Use in Figure Above** SDP Meaning Direction Notes :--- :--- :--- :--- 0 Recovered Clock A In In (to Module) 1 Recovered Clock B In 2 Output Clock (+) Out Differential Pair on SDP2 and 3 3 Output Clock (-) Out 4 5 1 PPS Out Out 6 1 PPS In In 7 1 PPS In (GNSS) In **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 148/159](.picmg-com-hpc-carrier-design-guide-alt/slide-150.jpg) ## Slide 151 ![**Appendices** **SyncE Summary** * Provides physical layer synchronization signal over Ethernet * Allows expensive central clock to be shared across the network * Defined in ITU-T G.8261, G.8262, G.8262.1, and G.8264 specs * G.8261 and G.8262 series define physical layer interface * G.8264 defines messaging channel used to provide pedigree of clock sources SyncE can be used alone or in conjunction with PTP: **Table 34: SyncE / PTP Matrix** Attribute SyncE Only PTP Only SyncE + PTP :--- :--- :--- :--- Frequency Accuracy Yes Yes Yes Phase Accuracy No Yes Yes Time of Day (ToD) No Yes Yes **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 149/159](.picmg-com-hpc-carrier-design-guide-alt/slide-151.jpg) ## Slide 152 ![**Header:** Appendices **Title:** 6.2. Appendix B: Alternative eDP Example **Body Text:** The alternative eDP example presented in Figures 76 through 81 below comes, with permission, from an Intel reference schematic for a late model CORE series processor. Some parts of the example may not be directly relevant to COM-HPC embedded designs in that they dwell on eDP back-light display power supplies and on a display connector used in certain reference platforms. Nonetheless, the materials may be of interest to some readers and are included in this Appendix. **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 150/159](.picmg-com-hpc-carrier-design-guide-alt/slide-152.jpg) ## Slide 153 ![**Header:** Appendices **Title:** Figure 76: Alternative eDP Example (Sheet 1 of 6): Passive Stuffing Options – eDP and DSI **Top Left Diagram (Dashed Box):** IN EDP_TXD- C7G3 1 2 EDP_TXD_C- OUT IN EDP_TXD+ C7G2 1 2 EDP_TXD_C+ OUT IN EDP_TX1- C7G1 1 2 EDP_TX1_C- OUT IN EDP_TX1+ C7G0 1 2 EDP_TX1_C+ OUT IN EDP_TX2- C7G8 1 2 EDP_TX2_C- OUT IN EDP_TX2+ C7G7 1 2 EDP_TX2_C+ OUT IN EDP_TX3- C7G6 1 2 EDP_TX3_C- OUT IN EDP_TX3+ C7G5 1 2 EDP_TX3_C+ OUT IN EDP_AUX- C7E4 1 2 EDP_AUX_C- OUT IN EDP_AUX+ C7E3 1 2 EDP_AUX_C+ OUT 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR 0.1uF XTR A36096-110 0402 AC CAP SHOULD BE REPLACED WITH OR RESISTOR FOR THE MIPI-DSI DISPLAY **Top Right Diagram:** H30143-001 R7F18 1 2 0.05W EMPTY 0201 0 % 0.05W RES 0201 L7F1 0.0 CHOKE 30N SM A J1E541-001 NEED TO STUFF CMC FOR MDSI H30143-001 R7F19 1 2 0.05W EMPTY 0201 0 % 0.05W RES 0201 IN EDP_AUX_C+ OUT EDP_AUX_MIPI_D0_L+ IN EDP_AUX_C- OUT EDP_AUX_MIPI_D0_L- **Bottom Left Diagram:** H30143-001 R7F20 1 2 0.05W EMPTY 0201 0 % L7F2 0.0 CHOKE 30N SM A J1E541-001 H30143-001 R7F21 1 2 0.05W EMPTY 0201 0 % 0.05W EMPTY 0201 IN EDP_TX3_C+ OUT EDP_LAN3_MIPI_D3_L+ IN EDP_TX3_C- OUT EDP_LAN3_MIPI_D3_L- H30143-001 R7F22 1 2 0.05W EMPTY 0201 0 % L7F3 0.0 CHOKE 30N SM A J1E541-001 H30143-001 R7F23 1 2 0.05W EMPTY 0201 0 % IN EDP_TX2_C+ OUT EDP_LAN2_MIPI_CLK_L+ IN EDP_TX2_C- OUT EDP_LAN2_MIPI_CLK_L- CAD NOTE: CMC PAD SHARING WITH RESISTOR **Bottom Right Diagram:** H30143-001 R7F24 1 2 0.05W EMPTY 0201 0 % L7F4 0.0 CHOKE 30N SM A J1E541-001 H30143-001 R7F25 1 2 0.05W EMPTY 0201 0 % 0.05W EMPTY 0201 IN EDP_TX1_C+ OUT EDP_LAN1_MIPI_D2_L+ IN EDP_TX1_C- OUT EDP_LAN1_MIPI_D2_L- H30143-001 R7G1 1 2 0.05W EMPTY 0201 0 % L7G1 0.0 CHOKE 30N SM A J1E541-001 H30143-001 R7G2 1 2 0.05W EMPTY 0201 0 % IN EDP_TX0_C+ OUT EDP_LAN0_MIPI_D1_L+ IN EDP_TX0_C- OUT EDP_LAN0_MIPI_D1_L- CAD NOTE: CMC PAD SHARING WITH RESISTOR **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 151/159](.picmg-com-hpc-carrier-design-guide-alt/slide-153.jpg) ## Slide 154 ![**Figure 77: Alternative eDP Example (Sheet 2 of 6): Backlight Control Options** **Appendices** **BACKLIGHT CONTROL** * COM * EDP_BRIGHT * R7E12 1 0 2 0402 RES * EDP_BRIGHTNESS_CONN OUT * R2D13 1 0 2 0402 RES * MIP11_PWM OUT * COM * EDP_BLT_EN * R7E15 1 0 2 0402 RES * EDP_BLT_EN_CONN OUT * R3T8 1 0 2 0402 RES * EDP_BLT_EN_R OUT * R7E4 1 0 2 0402 RES * MIP11_BRIGHTEN_R OUT * R2D4 1 0 2 0402 RES * MIP11_EN OUT **ADDITIONAL AMOLED POWER REQUIREMENTS** * J7E1 HDR_1X3 * 1 -V_ELVSS_EDP1_AMOLED1 * JA A91529-001 * 1 +VCC_EDP1_AMOLED1 * 2 +VCC_EDP1_AMOLED1 * C7F1 A35096-112 0.1uF 10V 25V X7R 0402 * NORMAL eDP PANEL * AMOLED EDP PANEL * STUFF UNSTUFF * RA & RC RB & RD * RA & RC * DESIGN NOTE: * THE HEADER JA SHOULD NEVER BE SHORTED WITH JUMPER SHORTING LINK * -V_ELVSS_EDP1_AMOLED1 * R7E1 H11304-001 0.01 1% 0.25W EMPTY * -VSS_EDP1_AMOLED1 * RBE1 A93552-004 0% 0.25W RES 0603 * RB RC RA * GND * +VCC_EDP1_AMOLED1 * +VCC_EDP1_BLIT * +VCC_EDP1_BLIT_R * RD 071625-002 0.01 0.1W RES 0603 * R7F5 0.01 0.1W RES 0603 * RC 071625-002 0.01 0.1W RES 0603 * R7F4 0.01 0.1W RES EMPTY 0603 **(Bottom Left Section)** * COM EDP_VDD_EN * R3T2 0402 RES * EDP1_EN_BLT_SHUT OUT * R3T1 0402 RES * MIP11_VDD_EN_R OUT * IN EDP_PIT_RST# * R7E17 0402 RES EMPTY A93549-001 * COM EDP_HPD * R7E16 0402 RES * EDP_HPD_MIP11_PNG_RST_R IN * COM GPIO_03 * R7E11 0402 RES EMPTY A93549-001 * PANEL_MESA_A_TEL IN * R7E10 0402 RES EMPTY A93549-001 * DESIGN NOTE: * MAXIMUM COMPUTE SIDE IS 1.8V BEFORE ENABLE THIS PATH **(Bottom Right Section)** * +VCC_EDP1_AMOLED1 * +V5PSH_MIP11 * R7F9 0.01 0.1W 1% EMPTY 0603 * +V5PSH_MIP11_AMOLED1 * +V5PSH_MIP11 * R7F8 0.01 0.1W 1% EMPTY 0603 * +V5PSH_MIP11_AMOLED1 * +V5PSH_MIP11 * R7F7 0.01 0.1W 1% EMPTY 0603 * +V5PSH_MIP11_AMOLED1 * -VSS_EDP1_AMOLED1 * R7F6 0.01 0.1W 1% RES 0603 D71625-002 * -VSS_EDP1_AMOLED1 **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 152/159](.picmg-com-hpc-carrier-design-guide-alt/slide-154.jpg) ## Slide 155 ![**Header:** Appendices Figure 78: Alternative eDP Example (Sheet 3 of 6): Connector to Display Panel Assembly **Connector JF1 Block:** JF1 SON CON_1X60_27EM (Pin 1) IO1 (Pin 2) IO2 EDP_LANE0_MIPI_D1_L- (Pin 3) IO4 EDP_LANE0_MIPI_D1_L+ (Pin 4) IO6 EDP_LANE1_MIPI_D2_L- (Pin 5) IO8 EDP_LANE1_MIPI_D2_L+ (Pin 6) IO8 EDP_LANE2_MIPI_CLK_L- (Pin 7) IO8 EDP_LANE2_MIPI_CLK_L+ (Pin 8) IO10 EDP_LANE3_MIPI_D3_L- (Pin 9) IO12 EDP_LANE3_MIPI_D3_L+ (Pin 10) IO14 EDP_AUX_MIPI_DO_L- (Pin 11) IO15 EDP_AUX_MIPI_DO_L+ (Pin 12) IO16 EDP_HPD_MIPI_RST_R (Pin 13) OUT EDP_BKLT_EN_CONN (Pin 14) EDP_BRIGHTNESS_CONN (Pin 15) PANEL_MOD1_A_TEL (Pin 16) (Pin 17) (Pin 18) (Pin 19) (Pin 20) DESIGN NOTE: PIN 20 MDSI_A_TEL IS 1.8V (Pin 21) IO21 (Pin 22) IO22 (Pin 23) IO23 (Pin 24) IO24 (Pin 25) IO25 (Pin 26) IO26 (Pin 27) IO27 (Pin 28) IO28 (Pin 29) IO29 (Pin 30) IO30 (Pin 31) IO31 (Pin 32) IO32 (Pin 33) IO33 (Pin 34) IO34 (Pin 35) IO35 (Pin 36) IO36 (Pin 37) IO37 (Pin 38) IO38 (Pin 39) IO39 (Pin 40) IO40 (Pin 41) IO41 (Pin 42) IO42 (Pin 43) IO43 (Pin 44) IO44 (Pin 45) IO45 (Pin 46) IO46 (Pin 47) IO47 (Pin 48) IO48 (Pin 49) IO49 (Pin 50) IO50 (Pin 51) IO51 (Pin 52) IO52 (Pin 53) IO53 (Pin 54) IO54 (Pin 55) IO55 (Pin 56) IO56 (Pin 57) IO57 (Pin 58) IO58 (Pin 59) IO59 (Pin 60) IO60 MH1 MH1 MH2 MH2 MH3 MH3 MH4 MH4 MH5 MH5 MH6 MH6 MH7 MH7 MH8 MH8 MH9 MH9 MH10 MH10 MH11 MH11 MH12 MH12 MH13 MH13 MH14 MH14 MH15 MH15 MH16 MH16 MH17 MH17 MH18 MH18 MH19 MH19 MH20 MH20 MH21 MH21 MH22 MH22 MH23 MH23 MH24 MH24 MH25 MH25 MH26 MH26 MH27 MH27 Z22036-001 **Connected Signals (Top/Left):** +V3P3S R014 A36096-014 1K 25V EMPTY 0402 R013 A36096-014 1K 25V EMPTY 0402 +V3P3X_EDP1_MIPI1 C7Q6 602433-081 22UF 20% 6.3V X5R 0603 C7G4 A36096-112 0.1UF 10% 25V X7R 0402 OUT DISP_BKL_PWM_OUT_MES11 **Connected Signals (Middle/Bottom):** TP_VSYNC_EDP1 +V3P3X_EDP1_MIPI1 +V1P8_MIPI1 +VCC_EDP1_BKLT_R +VCC_MIPI1 +V5PSV_MIPI1_AMLE1 +V5PSV_MIPI1_AMLE1 A_DISP0_VLED_FB0 A_DISP0_VLED_FB1 A_DISP0_VLED_FB2 A_DISP0_VLED_FB3 A_DISP0_VLED_FB4 A_DISP0_VLED_FB5 **Components (Bottom Left):** +V3P3S C7F2 602433-081 22UF 20% 6.3V X5R 0603 C3T5 602433-081 22UF 20% 6.3V X5R 0603 C3T6 A36096-112 0.1UF 10% 25V X7R 0402 +VCC_EDP1_BKLT_R C3T1 A36096-112 0.1UF 10% 25V X7R 0402 +VCC_MIPI1 C3R8 H48130-001 100UF 10% 25V EMPTY 0803 C3R7 G21127-001 0.1UF 10% 50V X7R 0402 +V1P8_MIPI1 C3T2 602433-081 22UF 20% 6.3V X5R 0603 **Footer:** PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 153/159](.picmg-com-hpc-carrier-design-guide-alt/slide-155.jpg) ## Slide 156 ![**Appendices** **Figure 79: Alternative eDP Example (Sheet 4 of 6): Backlight LED Driver** **Top Section Components & Labels:** * +V12_ATX * C7E1 G33975-001 1.0UF 20% 25V X5R 0603 * L7E1 652666-125 10UH 20% 1.89A IND 1 2 SM * +VCC_MIPI1_L * CR7E1 MIQS34073G D10 3A SM CS1983-001 A C * +VCC_MIPI1 * VOUT_OVP = 21V * C3P9 G66843-002 4.7UF 10% 25V X7R 1206 * R3R28 A93549-001 0% 0.0625W EMPTY 0402 (Label below: MIPI1_OVP_VOLT1) * R3R30 A93549-001 1 0 0.0625W RES 0402 (Label below: MIPI1_OVP_VOLT2) * R3R29 A93549-001 1 0 0.0625W 0402 (Label below: MIPI1_OVP_VOLT3) * R3R22 A93548-219 154K 1% 0.0625W RES 0402 * R3R24 A93548-412 163K 1% 0.0625W RES 0402 * R3R23 A93548-222 174K 1% 0.0625W RES 0402 * Formula: VOUT_OVP = VOUT x (1 + R_OVP2 / R_OVP1) * V_OVP = 1.2V **Middle/Left Section:** * IN MIPI1_EN * IN MIPI1_PWM * IN DISP_BKLPMN_OUT_MES11 * R3R5 A93549-0027 100K 5% 0.0625W RES 0402 * C7E2 A36096-112 0.1UF 10% 25V X7R 0402 * C3R6 A36096-112 0.1UF 10% 25V X7R 0402 (Top center capacitor) **IC Section (EU8R1):** * EU8R1 RT8532 IC * G55311-001 * +V12S_MIPI1_R VIN 19 * EN 1 * PWM 17 * MIPI1_CCOMP 20 * ISET 3 * MIPI1_FREQ 2 * AGND 13 * PGND 14 * GND 21 * VDC 18 * LX 15 * OVP 16 * MIPI1_OVP 12 * MIPI1_MIX 4 * LED6 6 A DISPO MIPI1 VLED FB5 R TI * LED5 7 A DISPO MIPI1 VLED FB4 R TI * LED4 8 A DISPO MIPI1 VLED FB3 R TI * LED3 9 A DISPO MIPI1 VLED FB2 R TI * LED2 10 A DISPO MIPI1 VLED FB1 R TI * LED1 11 A DISPO MIPI1 VLED FB0 R TI **Bottom Left Components:** * C3R4 A36096-112 0.1UF 10% 25V X7R 0402 * EMPTY 0402 * C3R1 A36096-089 22NF 10% 25V X7R 0402 * R3R8 A93549-085 5.1K 5% 0.0625W RES 0402 * MIPI1_CCOMP_19.6_R * R3R2 A93548-450 12K 1% 0.0625W RES 0402 * R3R3 G64084-106 22K 1% 0.0625W RES 0402 **Right Section Components:** * R3R1 A93549-023 10K 5% 0.0625W RES 0402 * R3R21 A93548-034 47PF 1% 50V C0G 0402 * C3R6 A36095-025 1 5% 50V C0G 0402 2 (Note: Duplicate reference designator C3R6) **Bottom Right Resistors:** * R3R7 0 0402 RES * R3R10 0 0402 RES * R3R12 0 0402 EMPTY * R3R15 0 0402 EMPTY * R3R18 0 0402 EMPTY * R3R19 0 0402 A93549-001 **Connectors/Outputs (Far Right):** * R3R6 0402 1 2 EMPTY A DISPO VLED FB5 * R3R9 0402 1 2 EMPTY A DISPO VLED FB4 * R3R11 0402 1 2 EMPTY A DISPO VLED FB3 * R3R14 0402 1 2 EMPTY A DISPO VLED FB2 * R3R17 0402 1 2 EMPTY A DISPO VLED FB1 * R3R20 0402 1 2 EMPTY A DISPO VLED FB0 * OUT (Repeated 5 times) **CAD Note:** * CAD NOTE: 3 PAD **Footer:** * PICMG® COM-HPC® Carrier Board Design Guide Draft * Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 * 154/159](.picmg-com-hpc-carrier-design-guide-alt/slide-156.jpg) ## Slide 157 ![Appendices Figure 80: Alternative eDP Example (Sheet 5 of 6): Split Rail (Pos / Neg) PS for AMOLED +V3P3_ATX +V1P8_MIPI1 R7E2 A30549-023 120 5% 0.0625W RES 0402 R8E6 EMPTY 0.01 1 EMPTY 0.1W 1 D71823-002 +V3P3A_IN_MIPI1 C8E4 A36096-125 10UF 20% 10V X5R 0402 EU81 IC TP665L35 1 VIN 8 EN 9 OUTP 10 OUTP 13 L2 14 L2 15 L1 16 L1 4 VAUX 2 OUTN 3 OUTN 5 GND 12 PGND 17 THPAD +V5_MIPI1_L2 L8E1 QS2290-004 2.2UH 0806 30% IND 1.2A +V5P5P_MIPI1_FB R8E5 A30548-564 107K 1% 0.0625W RES 0402 +V5P5P_MIPI1_FRG R8E3 G21796-216 475K 1% 0.0625W RES 0402 +V5P5N_MIPI1 R8E2 A93548-601 365K 1% 0.0625W RES 0402 C7E3 A36096-125 10UF 20% 10V X5R 0402 C8E1 A36096-143 1UF 10% 25V X5R 0402 C8E2 A36096-112 0.1UF 10% 25V X7R 0402 IN MIPI1_BKLTEN_R +V3P3_DUAL R3T1 0402 RES 0 C3T7 A36096-112 0.1UF 10% 25V X7R 0402 U3T1 IC SLG7NT402V 1 VDD 2 ON 3 D 5 S 7 CAP 8 GND G54192-001 +V1P8_A C3T3 A36096-125 10UF 20% 10V X5R 0402 +V1P8_MIPI1 C3T4 A36096-075 2.2NF 10% 50V X7R 0402 PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 155/159](.picmg-com-hpc-carrier-design-guide-alt/slide-157.jpg) ## Slide 158 ![Appendices Figure 81: Alternative eDP Example (Sheet 6 of 6): High Side Gate Driver for eDP Backlight +V5_ATX R7G6 1 0 2 0402 RES C7G9 A36096-143 10uF 25V X5R 0402 1 2 GND VDD_EDP1_BKLT EU7G1 IC SLG55021-200010 1 VCC D 5 7 EDP1_GATE_DRV 2 ON PG 8 TP_EDP1_BKLT_PG 4 GND SHDN_N 3 EDP1_EN_BKLT_SHDN# 9 THPAD S 6 G56246-001 IN EDP_BKLT_EN_R +V12_ATX Q7G1 MFET AON6500 J91717-001 5 D 4 G 1 2 3 S IN +VCC_EDP1_BKLT +V3P3_ATX R7G5 1 0 2 0402 RES C7G8 A36096-112 0.1uF 10% 25V X7R 0402 1 2 GND VDD_EDP1_SUPPLY U7G1 IC SLG5NT1458V 1 VDD CAP 7 2 ON S 5 3 D GND 8 H10115-001 IN EDP1_EN_BKLT_SHDN# V3P3DX_EDP1_SR_CAP C7G7 A36096-075 2.2nF 10% 50V X7R 0402 1 2 GND +V3P3DX_EDP1_MIPI1 +V3P3_ATX C7G5 A36096-125 100uF 20% 10V X5R 0402 1 2 GND PICMG® COM-HPC® Carrier Board Design Guide Draft Rev. RC2.0d / (c) Copyright 2021 PICMG December 7, 2021 156/159](.picmg-com-hpc-carrier-design-guide-alt/slide-158.jpg) ## Slide 159 ![**Header** * **Appendices** (Top Right) * **6.3. Appendix C: eSPI Header Example** * **Figure 82: eSPI Header Example** **Top Left Schematic** * +V1P8_A * +V3P3_A * R9G3 1 2 PMOTY 0 0.1W 0603 A93552-004 0% * R9G4 1 2 RES 0 0.1W 0603 A93552-004 0% * C9G1 A36096-112 0.1UF 10% XTR 0402 * +V3P3_A_V1P8A_ESPI **Top Right Schematic** * +V3P3_A * C9F2 A36096-112 0.1UF 10% XTR 0402 * +V5S * C9F1 A36096-112 0.1UF 10% XTR 0402 * J9G1 SCON HDR_2X14_K4 K21 K22 H46981-001 * **Pin Labels (Left Side):** * IN ESPI CLK HDR * IN ESPI CS0 HDR# * IN ESPI CS1 HDR# * BI ESPI IO3 HDR * BI ESPI IO0 HDR * IN ESPI SMB CLK * IN ESPI SMB DATA * BI ESPI CS1 HDR# * IN ESPI RST HDR# * OUT ESPI ALERT1 HDR# * **Pin Labels (Right Side):** * ESPI CLK HDR * ESPI CS0 HDR# * ESPI CS1 HDR# * ESPI IO2 HDR * ESPI IO1 HDR * ESPI IO0 HDR * ESPI SMB DATA * ESPI CS1 HDR# * ESPI CS1 HDR# * OUT ESPI ALERT0 HDR# **Bottom Left Section** * **DESIGN NOTE:** * ALL PU AT COMPUTE MODULE SIDE * IN BUF FLT RST 1.8# R9F3 1 2 PLTRST 1P8_ESPI# OUT * COM ESPI ALERT0# R1U4 1 2 ESPI ALERT0 HDR# IN * COM ESPI ALERT1# R9G6 1 2 ESPI ALERT1 HDR# IN * COM ESPI CS0# R9F2 1 2 ESPI CS0 HDR# OUT * COM ESPI CS1# R1U3 1 2 ESPI CS1 HDR# OUT * COM ESPI IO0 R9G1 1 2 ESPI IO0 HDR BI * COM ESPI IO1 R1U1 1 2 ESPI IO1 HDR BI * COM ESPI IO2 R1T1 1 2 ESPI IO2 HDR BI * COM ESPI IO3 R9F4 1 2 ESPI IO3 HDR BI * COM ESPI CLK R9F1 1 2 ESPI CLK HDR OUT * COM ESPI_RST# R9G5 1 2 ESPI_RST_HDR# OUT **Bottom Right Section** * IN PCIE X4 G0_SMB_CLK R9G2 1 2 ESPI SMB CLK OUT * BI PCIE X4 G0_SMB_DATA R1U2 1 2 ESPI SMB DATA BI **Footer** * PICMG® COM-HPC® Carrier Design Guide * Rev. RC2.0d / Dec 7, 2021 * 157/159](.picmg-com-hpc-carrier-design-guide-alt/slide-159.jpg) ## Slide 160 ![Appendices 6.4. Appendix D: Useful Books – General x86 Computer Topics Table 35: General Books on x86 Computer Topics Title Author Note :--- :--- :--- PCI Express System Architecture Ravi Budruk, Don Anderson, Tom Shanley www.mindshare.com PCI System Architecture (4th Edition) Tom Shanley, Don Anderson www.mindshare.com Universal Serial Bus System Architecture Don Anderson www.mindshare.com SATA Storage Technology Don Anderson www.mindshare.com Protected Mode Software Architecture (The PC System Architecture Series) Tom Shanley www.mindshare.com The Unabridged Pentium 4 Tom Shanley www.mindshare.com Building the Power-Efficient PC: A Developer's Guide to ACPI Power Management, First Edition Jerzy Kolinski, Ram Chary, Andrew Henroid, and Barry Press Intel Press, 2002, ISBN 0-9702846-8-3 Hardware Bible Winn L. Rosch SAMS, 1997, 0-672-30954-8 The Indispensable PC Hardware Book Hans-Peter Messmer Addison-Wesley, 1994, ISBN 0-201-62424-9 The PC Handbook: For Engineers, Programmers, and Other Serious PC Users, Sixth Edition John P. Choisser and John O. Foster Annabooks, 1997, ISBN 0-929392-36-1 PC Hardware in a Nutshell, 3rd Edition Robert Bruce Thompson and Barbara Fritchman Thompson O'Reilly, 2003, ISBN 0-596-00513-X PCI & PCI-X Hardware and Software Architecture & Design, Fifth Edition Edward Solari and George Willse Annabooks, Intel Press, 2001, ISBN 0-929392-63-9 PCI System Architecture Tom Shanley and Don Anderson Addison-Wesley, 2000, ISBN 0-201-30974-2 PCI Express Electrical Interconnect Design: Practical Solutions for Board-level Integration and Validation, First Edition Dave Coleman, Scott Gardiner, Mohamad Kolberhdari, and Stephen Peters Intel Press, 2005, ISBN 0-9743649-9-1 Introduction to PCI Express: A Hardware and Software Developer's Guide, First Edition Adam Wilen, Justin Schade, and Ron Thornburg Intel Press, 2003, ISBN 0-9702846-9-1 Serial ATA Storage Architecture and Applications, First Edition Knut Grimsrud and Hubbert Smith Intel Press, 2003, ISBN 0-9717861-8-6 USB Design by Example, A Practical Guide to Building I/O Devices, Second Edition John Hyde Intel Press, ISBN 0-9702846-5-9 Universal Serial Bus System Architecture, Second Edition Don Anderson and Dave Dzatko Mindshare, Inc., ISBN 0-201-30975-0 Printed Circuits Handbook, Fourth Edition Clyde F. Coombs Jr. McGraw-Hill, 1996, ISBN 0—07-012754-9 High Speed Signal Propagation, First Edition Howard Johnson and Martin Graham Prentice Hall, 2003, ISBN 0-13-084408-X High Speed Digital Design: A Handbook of Black Magic, First Edition Howard Johnson Prentice Hall, ISBN: 0133957241 C Programmer's Guide to Serial Communications, Second Edition Joe Campbell SAMS, 1987, ISBN 0-672-22584-0 The Programmer's PC Sourcebook, Second Edition Thom Hogan Microsoft Press, 1991, ISBN 1-55615-321-X The Undocumented PC, A Programmer's Guide to I/O, CPUs, and Fixed Memory Areas Frank van Gilluwe Addison-Wesley, 1997, ISBN 0-201-47950-8 VHDL Modeling for Digital Design Synthesis Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu and Eric S. Lin Kluwer Academic Publishers, 1995, ISBN: 0-7923-9597-2 PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 158/159](.picmg-com-hpc-carrier-design-guide-alt/slide-160.jpg) ## Slide 161 ![This slide is titled '6.5. Appendix E: Revision History' and contains 'Table 36: Revision History'. **Table 36: Revision History** Revision Date Author Notes / Changes :--- :--- :--- :--- 1.0 March17, 2021 C. Eder CDG preliminary version with Ethernet KR and KR4 CEI diagrams. RC2.0 October 2, 2021 S. Milnor(br)C. Eder Release Candidate for first version of complete COM-HPC CDG. RC2.0a November 14, 2021 S. Milnor(br)C. Eder Revise Figure 35 to show a 50V capacitor for C4V20(br)Revise Figure 41 to show a 50V capacitor for C5W7(br)Section 3.14.1 Page 96 – insert short statement about adding HD Audio support to pending COM-HPC Base Spec Rev 1.1 due to lack of Soundwire support(br)Remove references to code names for unreleased Intel products ADL and ICL(br)Revise code name references to show only Intel document numbers RC2.0b November 17, 2021 S. Milnor Incorporate nVent Change Requests RC2.0c December 6, 2021 S. Milnor Change Rev to RC2.0c, change date, re-issue. No other changes. RC2.0d December 7, 2021 S. Milnor Add note to Figure 39 (USB4 ESD diodes) explaining diode positioning(br)Replace Figures 67 and 73 (JSOM diagrams) with revised Figures that call out metric M2.5 hardware rather than 4-40 Imperial hardware **Footer:** PICMG® COM-HPC® Carrier Design Guide Rev. RC2.0d / Dec 7, 2021 159/159 **Top Right Header:** Appendices](.picmg-com-hpc-carrier-design-guide-alt/slide-161.jpg) [🔗 Link to the original document](.picmg-com-hpc-carrier-design-guide-alt/picmg-com-hpc-carrier-design-guide-alt.pdf) [🔗 Link to the original document](.picmg-com-hpc-carrier-design-guide-alt/picmg-com-hpc-carrier-design-guide-alt.md)