# ETX® 3.0

# Long Term Support

# ETX® Specification

Document Revision 3.02

# Contents

# 1. USER INFORMATION......3

1.1 Objective 3
1.2 Target Audience 3
1.3 Assumptions.... 3
1.4 Scope....3
1.5 Disclaimer....3
1.6 ETX $^{\textregistered}$ – an exclusive Trademark for Members of the ETX $^{\textregistered}$ Industrial Group (ETX $^{\textregistered}$ -IG) . 4
1.7 Technical Support....5

# 2. INTRODUCTION 6

2.1 ETX Benefits 6
2.2 ETX $^{®}$ Documentation 7

# 3. CONNECTOR PINOUT......8

3.1 Connector X1 8
3.1.1 PCI Bus, USB, Audio 8
3.2 Connector X2 9
3.2.1 ISA Bus....9
3.3 Connector X3 10
3.3.1 VGA, LCD, Video, COM1, COM2, LPT/Floppy, IrDA, Mouse, Keyboard......10
3.4 Connector X4 12
3.4.1 IDE 1, IDE 2, Ethernet, Miscellaneous ....12

# 4. SIGNAL DESCRIPTIONS 13

4.1 Power....13
4.1.1 GND 13
4.1.2 VCC....13
4.1.3 3V....13
4.2 Reserved....13
4.3 Connector X1 14
4.3.1 PCI Signals - General 14
4.3.2 USB Signals....16
4.3.3 Audio Signals....17
4.3.4 Miscellaneous....17
4.4 Connector X2 18
4.4.1 ISA Signals....18
4.5 Connector X3 22
4.5.1 VGA Signals....22
4.5.2 LVDS Flat-Panel Interface Signals 23
4.5.3 Digital Flat-Panel Interface Signals 25
4.5.4 Television Output Signals 26

4.5.5 Serial Port Signals 27
4.5.6 PS/2 Keyboard, PS/2 Mouse Signals 28
4.5.7 IRDA (SIR) Signals 28
4.6 Parallel Port Signals....29
4.6.1 Floppy Signals 30
4.7 Connector X4 32
4.7.1 IDE Signals....32
4.7.2 Ethernet Signals....33
4.7.3 Power Control Signals....35
4.7.4 Power-Management Signals....36
4.7.5 Miscellaneous Signals....37

# 5. MECHANICAL CHARACTERISTICS 39

5.1 Dimensions of ETX....39
5.2 Heat Spreader and Heat-sink Considerations....40
5.3 Specifications Baseboard Connector and Standoffs....41
5.4 PCB Footprint of Receptacle FX8-100S 42
5.5 Backplane Layout 43

# 6. OPTIONAL INTERFACE SATA 44

6.1 Functionality....44
6.2 Connector Area 44
6.3 Requirements 45
6.4 SATA Signals....45

# 7. APPENDIX A: PC ARCHITECTURE INFORMATION 46

7.1 General PC Architecture 46
7.2 Buses....46
7.2.1 ISA, Standard PS/2 – Connectors 46
7.2.2 PC/104 and PCI 46
7.3 Ports....47
7.3.1 RS-232 Serial....47
7.3.2 Serial ATA 47
7.3.3 USB 47
7.4 Programming....48

# 8. APPENDIX B: DOCUMENT-REVISION HISTORY 49

# 1. User Information

# 1.1 Objective

This document is the defining specification for ETX $^{®}$ computer modules. It specifies common mechanical and electrical characteristics for all ETX module designs to ensure physical interchangeability and electrical compatibility between modules.

# 1.2 Target Audience

This guide is intended for hardware engineers who design ETX computer modules or system baseboards for ETX computer modules.

# 1.3 Assumptions

The reader is assumed to have a hardware engineering background as well as experience with personal computer buses and peripheral interfaces. A working knowledge of practices for designs of multi-layer, printed circuit boards is assumed. Appendix A: PC Architecture Information contains suggested references for readers desiring a more extensive presentation of topics such as PCI and ISA buses and the IDE (ATAPI) interface.

# 1.4 Scope

This specification should be regarded as a supplement to industry standards that define computer buses and interfaces used on ETX modules. This specification does not include detailed information on protocols, timing, and logic levels. Please refer to the relevant industry standards for this detailed information.

ETX modules typically contain basic signal termination components such as pullup resistors. In some applications it will be necessary to place additional components on the baseboard to meet application-specific ESD, EMI, or safety requirements. These requirements vary among applications and are outside the scope of this document.

# 1.5 Disclaimer

Although the information presented in this document was carefully reviewed and is believed to be accurate, it is not guaranteed. The reader assumes all liability for the use of the information herein.

# 1.6 ETX $^{®}$ – an exclusive Trademark for Members of the ETX $^{®}$ Industrial Group (ETX $^{®}$ -IG)

Kontron Embedded Modules GmbH and Advantech Co., Ltd. are founding member of the ETX $^{®}$ Industrial Group the purpose of which is the definition, marketing and promotion of the Embedded Technology eXtended (ETX $^{®}$ ) Industrial Standard. Kontron Embedded Modules GmbH has significantly contributed to the development and promotion of the ETX $^{®}$ Industrial Standard and administrates the ETX $^{®}$ Industrial Group's website (www.etx-ig.com). Kontron Embedded Modules GmbH is the owner of the ETX $^{®}$ trademark which is protected as a registered trademark under various jurisdictions worldwide.

Kontron Embedded Modules GmbH has licensed the ETX $^{\textregistered}$ trademark to all members of the ETX $^{\textregistered}$ Industrial Group. All members of the ETX $^{\textregistered}$ Industrial Group have committed themselves to fulfilment of the current specifications of the ETX $^{\textregistered}$ Industrial Standard which can be downloaded from the ETX $^{\textregistered}$ IG's website.

Companies that are not a member of the ETX $^{\textregistered}$ Industrial Group are not authorized to use the trademark ETX $^{\textregistered}$ for their products. Neither the ETX $^{\textregistered}$ Industrial Group nor its members can monitor the compliance of third parties with the ETX $^{\textregistered}$ Industrial Standard's specifications.

More information on how to become a member of the ETX $^{®}$ Industrial Group as well as on the terms of use of the trademark ETX $^{®}$ can be downloaded from the website of the ETX $^{®}$ Industrial Group (www.etx-ig.com).

# 1.7 Technical Support

Technicians and engineers from ETX industrial Group Members are available for technical support. We are committed to making our product easy to use and will help you use our products in your systems.

http://www.etx-ig.com/members/members.php

Before contacting ETX Industrial Group Members technical support, please consult our Web site at http://www.etx-ig.com for the latest product documentation, utilities, and drivers. If the information does not help solve the problem, contact us by email.

http://www.etx-ig.com/contact/contact.php

# 2. Introduction

# 2.1 ETX® Benefits

Embedded Technology extended (ETX) modules are very compact ( $\sim$ 100mm square, 12mm thick), highly integrated computers. All ETX modules have a standardized form factor and a standardized connector layout that carry a specified set of signals. This standardization allows designers to create a single system “baseboard” that can accept present and future ETX modules.

ETX modules include common personal computer (PC) peripheral functions such as graphics, USB, serial, and parallel ports, keyboard/mouse, Ethernet, and IDE. The baseboard designer can optimize exactly how each of these functions is physically implemented. Connectors can be placed precisely where needed on a baseboard designed to optimally fit system packaging.

Peripheral PCI or ISA devices can be implemented directly on the baseboard rather than on mechanically unwieldy expansion cards. The ability to build a system on a single baseboard, using the computer as one “plug-in” component, simplifies packaging, eliminates cabling, and reduces system-level cost.

A single baseboard design may be used with a range of ETX modules. This flexibility can differentiate products at various price/performance points, or to design systems that have a built-in upgrade path. The modularity of an ETX solution also ensures against obsolescence as computer technology evolves. A properly designed ETX baseboard can be used with successive generations of ETX modules.

An ETX baseboard design has many of the advantages of a custom computer-board design but delivers better obsolescence protection, greatly reduces engineering effort, and achieves faster time to market.

The baseboard designer can optimize exactly how each of these functions implements physically. Designers can place connectors precisely where needed for the application on a baseboard designed to optimally fit a system's packaging.

# 2.2 ETX® Documentation

This ETX $^{®}$ Specification, which you should read first, is one of three principal references for an ETX $^{®}$ design. The other two references, which are available from the ETX Industrial Group Web site, include:

The ETX $^{®}$ Design Guide, which is a general guide for baseboard design, with a focus on maximum flexibility to accommodate all ETX modules.

http://www.etx-ig.com/specs/specs.php

Product manuals for specific ETX $^{®}$ modules document specifications and features of each ETX $^{®}$ module.

http://www.etx-ig.com/members/members.php

# 3. Connector Pinout

# 3.1 Connector X1

# 3.1.1 PCI Bus, USB, Audio

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td><td rowspan="25"></td><td>51</td><td>VCC</td><td>52</td><td>VCC</td></tr><tr><td>3</td><td>PCICLK3</td><td>4</td><td>PCICLK4</td><td>53</td><td>PAR</td><td>54</td><td>SERR#</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td><td>55</td><td>GPERR#</td><td>56</td><td>RESERVED</td></tr><tr><td>7</td><td>PCICLK1</td><td>8</td><td>PCICLK2</td><td>57</td><td>PME#</td><td>58</td><td>USB2-</td></tr><tr><td>9</td><td>REQ3#</td><td>10</td><td>GNT3#</td><td>59</td><td>LOCK#</td><td>60</td><td>DEVSEL#</td></tr><tr><td>11</td><td>GNT2#</td><td>12</td><td>3V</td><td>61</td><td>TRDY#</td><td>62</td><td>USB3-</td></tr><tr><td>13</td><td>REQ2#</td><td>14</td><td>GNT1#</td><td>63</td><td>IRDY#</td><td>64</td><td>STOP#</td></tr><tr><td>15</td><td>REQ1#</td><td>16</td><td>3V</td><td>65</td><td>FRAME#</td><td>66</td><td>USB2+</td></tr><tr><td>17</td><td>GNT0#</td><td>18</td><td>RESERVED</td><td>67</td><td>GND</td><td>68</td><td>GND</td></tr><tr><td>19</td><td>VCC</td><td>20</td><td>VCC</td><td>69</td><td>AD16</td><td>70</td><td>CBE2#</td></tr><tr><td>21</td><td>SERIRQ</td><td>22</td><td>REQ0#</td><td>71</td><td>AD17</td><td>72</td><td>USB3+</td></tr><tr><td>23</td><td>AD0</td><td>24</td><td>3V</td><td>73</td><td>AD19</td><td>74</td><td>AD18</td></tr><tr><td>25</td><td>AD1</td><td>26</td><td>AD2</td><td>75</td><td>AD20</td><td>76</td><td>USB0-</td></tr><tr><td>27</td><td>AD4</td><td>28</td><td>AD3</td><td>77</td><td>AD22</td><td>78</td><td>AD21</td></tr><tr><td>29</td><td>AD6</td><td>30</td><td>AD5</td><td>79</td><td>AD23</td><td>80</td><td>USB1-</td></tr><tr><td>31</td><td>CBE0#</td><td>32</td><td>AD7</td><td>81</td><td>AD24</td><td>82</td><td>CBE3#</td></tr><tr><td>33</td><td>AD8</td><td>34</td><td>AD9</td><td>83</td><td>VCC</td><td>84</td><td>VCC</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>GND</td><td>85</td><td>AD25</td><td>86</td><td>AD26</td></tr><tr><td>37</td><td>AD10</td><td>38</td><td>AUXAL</td><td>87</td><td>AD28</td><td>88</td><td>USB0+</td></tr><tr><td>39</td><td>AD11</td><td>40</td><td>MIC</td><td>89</td><td>AD27</td><td>90</td><td>AD29</td></tr><tr><td>41</td><td>AD12</td><td>42</td><td>AUXAR</td><td>91</td><td>AD30</td><td>92</td><td>USB1</td></tr><tr><td>43</td><td>AD13</td><td>44</td><td>ASVCC</td><td>93</td><td>PCIRST#</td><td>94</td><td>AD31</td></tr><tr><td>45</td><td>AD14</td><td>46</td><td>SNDL</td><td>95</td><td>INTC#</td><td>96</td><td>INTD#</td></tr><tr><td>47</td><td>AD15</td><td>48</td><td>ASGND</td><td>97</td><td>INTA#</td><td>98</td><td>INTB#</td></tr><tr><td>49</td><td>CBE1#</td><td>50</td><td>SNDR</td><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

# 3.2 Connector X2

# 3.2.1 ISA Bus

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td><td rowspan="25"></td><td>51</td><td>VCC</td><td>52</td><td>VCC</td></tr><tr><td>3</td><td>SD14</td><td>4</td><td>SD15</td><td>53</td><td>SA6</td><td>54</td><td>IRQ5</td></tr><tr><td>5</td><td>SD13</td><td>6</td><td>MASTER#</td><td>55</td><td>SA7</td><td>56</td><td>IRQ6</td></tr><tr><td>7</td><td>SD12</td><td>8</td><td>DREQ7</td><td>57</td><td>SA8</td><td>58</td><td>IRQ7</td></tr><tr><td>9</td><td>SD11</td><td>10</td><td>DACK7#</td><td>59</td><td>SA9</td><td>60</td><td>SYSCLK</td></tr><tr><td>11</td><td>SD10</td><td>12</td><td>DREQ6</td><td>61</td><td>SA10</td><td>62</td><td>REFSH#</td></tr><tr><td>13</td><td>SD9</td><td>14</td><td>DACK6#</td><td>63</td><td>SA11</td><td>64</td><td>DREQ1</td></tr><tr><td>15</td><td>SD8</td><td>16</td><td>DREQ5</td><td>65</td><td>SA12</td><td>66</td><td>DACK1#</td></tr><tr><td>17</td><td>MEMW#</td><td>18</td><td>DACK5#</td><td>67</td><td>GND</td><td>68</td><td>GND</td></tr><tr><td>19</td><td>MEMR#</td><td>20</td><td>DREQ0</td><td>69</td><td>SA13</td><td>70</td><td>DREQ3</td></tr><tr><td>21</td><td>LA17</td><td>22</td><td>DACK0#</td><td>71</td><td>SA14</td><td>72</td><td>DACK3#</td></tr><tr><td>23</td><td>LA18</td><td>24</td><td>IRQ14</td><td>73</td><td>SA15</td><td>74</td><td>IOR#</td></tr><tr><td>25</td><td>LA19</td><td>26</td><td>IRQ15</td><td>75</td><td>SA16</td><td>76</td><td>IOW#</td></tr><tr><td>27</td><td>LA20</td><td>28</td><td>IRQ12</td><td>77</td><td>SA18</td><td>78</td><td>SA17</td></tr><tr><td>29</td><td>LA21</td><td>30</td><td>IRQ11</td><td>79</td><td>SA19</td><td>80</td><td>SMEMR#</td></tr><tr><td>31</td><td>LA22</td><td>32</td><td>IRQ10</td><td>81</td><td>IOCHRDY</td><td>82</td><td>AEN</td></tr><tr><td>33</td><td>LA23</td><td>34</td><td>IO16#</td><td>83</td><td>VCC</td><td>84</td><td>VCC</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>GND</td><td>85</td><td>SD0</td><td>86</td><td>SMEMW#</td></tr><tr><td>37</td><td>SBHE#</td><td>38</td><td>M16#</td><td>87</td><td>SD2</td><td>88</td><td>SD1</td></tr><tr><td>39</td><td>SA0</td><td>40</td><td>OSC</td><td>89</td><td>SD3</td><td>90</td><td>NOWS#</td></tr><tr><td>41</td><td>SA1</td><td>42</td><td>BALE</td><td>91</td><td>DREQ2</td><td>92</td><td>SD4</td></tr><tr><td>43</td><td>SA2</td><td>44</td><td>TC</td><td>93</td><td>SD5</td><td>94</td><td>IRQ9</td></tr><tr><td>45</td><td>SA3</td><td>46</td><td>DACK2#</td><td>95</td><td>SD6</td><td>96</td><td>SD7</td></tr><tr><td>47</td><td>SA4</td><td>48</td><td>IRQ3</td><td>97</td><td>IOCHK#</td><td>98</td><td>RSTDRV</td></tr><tr><td>49</td><td>SA5</td><td>50</td><td>IRQ4</td><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

# 3.3 Connector X3

# 3.3.1 VGA, LCD, Video, COM1, COM2, LPT/Floppy, IrDA, Mouse, Keyboard

# Flat-panel Interfaces

ETX modules may implement an LVDS flat-panel interface or a parallel, digital flat-panel interface. Please refer the board manual and specific design guide for details of this option.

Pin functions for the shaded pins differ between the two flat-panel interfaces. The unshaded pins have identical functions regardless of interface type.

<table><tr><td colspan="4">LVDS Interface Pinout</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>R</td><td>4</td><td>B</td></tr><tr><td>5</td><td>HSY</td><td>6</td><td>G</td></tr><tr><td>7</td><td>VSY</td><td>8</td><td>DDCK</td></tr><tr><td>9</td><td>DETECT#</td><td>10</td><td>DDDA</td></tr><tr><td>11</td><td>LCDDO16</td><td>12</td><td>LCDDO18</td></tr><tr><td>13</td><td>LCDDO17</td><td>14</td><td>LCDDO19</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>LCDDO13</td><td>18</td><td>LCDDO15</td></tr><tr><td>19</td><td>LCDDO12</td><td>20</td><td>LCDDO14</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>LCDDO8</td><td>24</td><td>LCDDO11</td></tr><tr><td>25</td><td>LCDDO9</td><td>26</td><td>LCDDO10</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>GND</td></tr><tr><td>29</td><td>LCDDO4</td><td>30</td><td>LCDDO7</td></tr><tr><td>31</td><td>LCDDO5</td><td>32</td><td>LCDDO6</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>LCDDO1</td><td>36</td><td>LCDDO3</td></tr><tr><td>37</td><td>LCDDO0</td><td>38</td><td>LCDDO2</td></tr><tr><td>39</td><td>VCC</td><td>40</td><td>VCC</td></tr><tr><td>41</td><td>JILI_DAT</td><td>42</td><td>LTGIO0</td></tr><tr><td>43</td><td>JILI_CLK</td><td>44</td><td>BLON#</td></tr><tr><td>45</td><td>BIASON</td><td>46</td><td>DIGON</td></tr><tr><td>47</td><td>COMP</td><td>48</td><td>Y</td></tr><tr><td>49</td><td>SYNC</td><td>50</td><td>C</td></tr></table>

# Parallel Port / Floppy Interfaces

ETX $^{®}$ parallel-port interfaces can be configured either as conventional PC parallel ports or as an interface for floppy-disk drives. The operating mode can be selected by BIOS settings or by a select pin for a specific hardware mode.

If Pin X3-51 (LPT/FLPY#) is grounded at boot time, the floppy-support mode is selected. If this pin is left floating or is held high, parallel-port mode is selected.

The mode selection is determined only at boot time. It cannot be changed until the next boot cycle.

The functions of the shaded pins differ between the parallel-port mode and the floppy-support mode. The unshaded pins are not part of the parallel port / floppy interface. These pins have identical functions regardless of the operating mode of the interface.

<table><tr><td colspan="4">Parallel Port Mode Pinout</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>LPT/FLPY#</td><td>52</td><td>RESERVED</td></tr><tr><td>53</td><td>VCC</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>STB#</td><td>56</td><td>AFD#</td></tr><tr><td>57</td><td>RESERVED</td><td>58</td><td>PD7</td></tr><tr><td>59</td><td>IRRX</td><td>60</td><td>ERR#</td></tr><tr><td>61</td><td>IRTX</td><td>62</td><td>PD6</td></tr><tr><td>63</td><td>RXD2</td><td>64</td><td>INIT#</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>RTS2#</td><td>68</td><td>PD5</td></tr><tr><td>69</td><td>DTR2#</td><td>70</td><td>SLIN#</td></tr><tr><td>71</td><td>DCD2#</td><td>72</td><td>PD4</td></tr><tr><td>73</td><td>DSR2#</td><td>74</td><td>PD3</td></tr><tr><td>75</td><td>CTS2#</td><td>76</td><td>PD2</td></tr><tr><td>77</td><td>TXD2</td><td>78</td><td>PD1</td></tr><tr><td>79</td><td>RI2#</td><td>80</td><td>PDO</td></tr><tr><td>81</td><td>VCC</td><td>82</td><td>VCC</td></tr><tr><td>83</td><td>RXD1</td><td>84</td><td>ACK#</td></tr><tr><td>85</td><td>RTS1#</td><td>86</td><td>BUSY</td></tr><tr><td>87</td><td>DTR1#</td><td>88</td><td>PE</td></tr><tr><td>89</td><td>DCD1#</td><td>90</td><td>SLCT#</td></tr><tr><td>91</td><td>DSR1#</td><td>92</td><td>MSCLK</td></tr><tr><td>93</td><td>CTS1#</td><td>94</td><td>MSDAT</td></tr><tr><td>95</td><td>TXD1</td><td>96</td><td>KBCLK</td></tr><tr><td>97</td><td>RI1#</td><td>98</td><td>KBDAT</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

<table><tr><td colspan="4">Floppy Support Mode Pinout</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>LPT/FLPY#</td><td>52</td><td>RESERVED</td></tr><tr><td>53</td><td>VCC</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>RESERVED</td><td>56</td><td>DENSEL</td></tr><tr><td>57</td><td>RESERVED</td><td>58</td><td>RESERVED</td></tr><tr><td>59</td><td>IRRX</td><td>60</td><td>HDSEL#</td></tr><tr><td>61</td><td>IRTX</td><td>62</td><td>RESERVED</td></tr><tr><td>63</td><td>RXD2</td><td>64</td><td>DIR#</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>RTS2#</td><td>68</td><td>RESERVED</td></tr><tr><td>69</td><td>DTR2#</td><td>70</td><td>STEP#</td></tr><tr><td>71</td><td>DCD2#</td><td>72</td><td>DSKCHG#</td></tr><tr><td>73</td><td>DSR2#</td><td>74</td><td>RDATA#</td></tr><tr><td>75</td><td>CTS2#</td><td>76</td><td>WP#</td></tr><tr><td>77</td><td>TXD2</td><td>78</td><td>TRKO#</td></tr><tr><td>79</td><td>RI2#</td><td>80</td><td>INDEX#</td></tr><tr><td>81</td><td>VCC</td><td>82</td><td>VCC</td></tr><tr><td>83</td><td>RXD1</td><td>84</td><td>DRV#</td></tr><tr><td>85</td><td>RTS1#</td><td>86</td><td>MOT#</td></tr><tr><td>87</td><td>DTR1#</td><td>88</td><td>WDATA#</td></tr><tr><td>89</td><td>DCD1#</td><td>90</td><td>WGATE#</td></tr><tr><td>91</td><td>DSR1#</td><td>92</td><td>MSCLK</td></tr><tr><td>93</td><td>CTS1#</td><td>94</td><td>MSDAT</td></tr><tr><td>95</td><td>TXD1</td><td>96</td><td>KBCLK</td></tr><tr><td>97</td><td>RI1#</td><td>98</td><td>KBDAT</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

# 3.4 Connector X4

# 3.4.1 IDE 1, IDE 2, Ethernet, Miscellaneous

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>5V_SB</td><td>4</td><td>PWGIN</td></tr><tr><td>5</td><td>PS_ON#</td><td>6</td><td>SPEAKER</td></tr><tr><td>7</td><td>PWRBTN#</td><td>8</td><td>BATT</td></tr><tr><td>9</td><td>KBINH#</td><td>10</td><td>LILED#</td></tr><tr><td>11</td><td>RSMRST#</td><td>12</td><td>ACTLED#</td></tr><tr><td>13</td><td>ROMKBCS#</td><td>14</td><td>SPEEDLED#</td></tr><tr><td>15</td><td>EXT_PRG</td><td>16</td><td>I2CLK</td></tr><tr><td>17</td><td>VCC</td><td>18</td><td>VCC</td></tr><tr><td>19</td><td>OVCR#</td><td>20</td><td>GPCS#</td></tr><tr><td>21</td><td>EXTSMI#</td><td>22</td><td>I2DAT</td></tr><tr><td>23</td><td>SMBCLK</td><td>24</td><td>SMBDATA</td></tr><tr><td>25</td><td>SIDE_CS3#</td><td>26</td><td>SMBALRT#</td></tr><tr><td>27</td><td>SIDE_CS1#</td><td>28</td><td>DASP_S</td></tr><tr><td>29</td><td>SIDE_A2</td><td>30</td><td>PIDE_CS3#</td></tr><tr><td>31</td><td>SIDE_A0</td><td>32</td><td>PIDE_CS1#</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>PDIAG_S</td><td>36</td><td>PIDE_A2</td></tr><tr><td>37</td><td>SIDE_A1</td><td>38</td><td>PIDE_A0</td></tr><tr><td>39</td><td>SIDE_INTRQ</td><td>40</td><td>PIDE_A1</td></tr><tr><td>41</td><td>BATLOW#</td><td>42</td><td>GPE1#</td></tr><tr><td>43</td><td>SIDE_AK#</td><td>44</td><td>PIDE_INTRQ</td></tr><tr><td>45</td><td>SIDE_RDY</td><td>46</td><td>PIDE_AK#</td></tr><tr><td>47</td><td>SIDE_IOR#</td><td>48</td><td>PIDE_RDY</td></tr><tr><td>49</td><td>VCC</td><td>50</td><td>VCC</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>SIDE_IOW#</td><td>52</td><td>PIDE_IOR#</td></tr><tr><td>53</td><td>SIDE_DRQ</td><td>54</td><td>PIDE_IOW#</td></tr><tr><td>55</td><td>SIDE_D15</td><td>56</td><td>PIDE_DRQ</td></tr><tr><td>57</td><td>SIDE_D0</td><td>58</td><td>PIDE_D15</td></tr><tr><td>59</td><td>SIDE_D14</td><td>60</td><td>PIDE_D0</td></tr><tr><td>61</td><td>SIDE_D1</td><td>62</td><td>PIDE_D14</td></tr><tr><td>63</td><td>SIDE_D13</td><td>64</td><td>PIDE_D1</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>SIDE_D2</td><td>68</td><td>PIDE_D13</td></tr><tr><td>69</td><td>SIDE_D12</td><td>70</td><td>PIDE_D2</td></tr><tr><td>71</td><td>SIDE_D3</td><td>72</td><td>PIDE_D12</td></tr><tr><td>73</td><td>SIDE_D11</td><td>74</td><td>PIDE_D3</td></tr><tr><td>75</td><td>SIDE_D4</td><td>76</td><td>PIDE_D11</td></tr><tr><td>77</td><td>SIDE_D10</td><td>78</td><td>PIDE_D4</td></tr><tr><td>79</td><td>SIDE_D5</td><td>80</td><td>PIDE_D10</td></tr><tr><td>81</td><td>VCC</td><td>82</td><td>VCC</td></tr><tr><td>83</td><td>SIDE_D9</td><td>84</td><td>PIDE_D5</td></tr><tr><td>85</td><td>SIDE_D6</td><td>86</td><td>PIDE_D9</td></tr><tr><td>87</td><td>SIDE_D8</td><td>88</td><td>PIDE_D6</td></tr><tr><td>89</td><td>GPE2#</td><td>90</td><td>CBLID_P</td></tr><tr><td>91</td><td>RXD-</td><td>92</td><td>PIDE_D8</td></tr><tr><td>93</td><td>RXD+</td><td>94</td><td>SIDE_D7</td></tr><tr><td>95</td><td>TXD-</td><td>96</td><td>PIDE_D7</td></tr><tr><td>97</td><td>TXD+</td><td>98</td><td>HDRST#</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

# 4. Signal Descriptions

# 4.1 Power

# 4.1.1 GND

Ground. All 41 GND pins on an ETX $^{®}$ module should be connected to the ground plane of the baseboard.

# 4.1.2 VCC

The baseboard provides the +5V ±5% power supply. All 21 VCC pins on an ETX $^{®}$ module should be connected to the baseboard's +5V plane.

# 4.1.3 3V

The +3.3V ±5% supply voltage is generated onboard an ETX $^{®}$ module. These three pins may be used as a power supply for external devices. The maximum allowed external load is 500mA.

WARNING: Do not connect 3.3V pins to an external 3.3V supply.

# 4.2 Reserved

These pins are reserved for future use or for manufacturing and test purposes. Do not connect external signals to these pins.

# 4.3 Connector X1

# 4.3.1 PCI Signals - General

All signals are 3.3V level PCI signals. All PCI signal pullups are integrated on the ETX $^{®}$ board and are either a 3.3V or 5V supply. For compatibility with all ETX $^{®}$ modules, external PCI devices should have 3.3V-signal levels and be 5V tolerant. No pull-ups should be implemented externally on the PCI bus.

NOTE: For further description of PCI signals refer to Appendix A: PC Architecture Information. Refer to the ETX® Design Guide for routing guidelines.

# PCICLK1..4

PCI clock outputs for up to 4 external PCI slots or devices.

The baseboard designer should route these clocks for 1300pS total delay from the ETX connector pin to the clock pin of the PCI device. See the ETX $^{®}$ Design Guide for typical route length calculations.

# REQ[0..3]#

Bus Request signals for up to 4 external bus mastering PCI devices. When asserted, a PCI device is requesting PCI bus ownership from the arbiter.

ETX modules support varying numbers of REQ/GNT pairs. Refer to the product manual for the specific ETX module to determine how many REQ/GNT pairs are available.

# GNT[0..3]#

Grant signals to PCI Masters. When asserted by the arbiter, the PCI master has been granted ownership of the PCI bus.

# AD[0..31]

PCI Address and Data Bus Lines. These lines carry the address and data information for PCI transactions.

# CBE[0..3]#

PCI Bus Command and Byte Enables. Bus command and byte enables are multiplexed in these lines for address and data phases, respectively.

# PAR

Parity bit for the PCI bus. Generated as even parity across AD[31:0] and CBE[3:0]#.

# SERR#

System Error. Asserted for hardware-error conditions such as parity errors detected in DRAM.

# GPERR#

Parity Error. For PCI operation per exception granted by PCI 2.1 Specification.

# PME#

Power-management event.

# LOCK#

Lock Resource Signal. This signal indicates that either the PCI master or the bridge intends to run exclusive transfers.

# DEVSEL#

Device Select. When the target device has decoded the address as its own cycle, it will assert DEVSEL#.

# TRDY#

Target Ready. This signal indicates that the target is ready to complete the current data phase of a transaction.

# IRDY#

Initiator Ready. This signal indicates that the initiator is ready to complete the current data phase of a transaction.

# STOP#

Stop. This signal indicates that the target is requesting that the master stop the current transaction.

# FRAME#

Cycle Frame of PCI Buses. This signal indicates the beginning and duration of a PCI access. The access will be either an output driven by the north bridge on behalf of the CPU, or an input during PCI master access.

# PCIRST#

PCI Bus Reset. This output signal resets the entire PCI Bus. This signal is asserted during system reset.

# INTA#, INTB#, INTC#, INTD#

PCI interrupts. These interrupts are sharable and are typically wired in rotation to PCI slots or devices. See the ETX $^{®}$ Design Guide for details.

# IDSEL

This pin is not present on the ETX module connector, but it is present on each PCI slot connector or device. IDSEL is an input to the device and is used to set a device's configuration address for PCI configuration cycles. The IDSEL pin of each device is typically connected to one of the AD lines to set a unique configuration address.

In ETX $^{®}$ systems, the four external bus slots or devices are assumed to use AD[19..22] for IDSEL connections. See the ETX $^{®}$ Design Guide for details.

# 4.3.2 USB Signals

USB signal-termination components are integrated on the ETX $^{®}$ board.

In applications using external USB devices, baseboard designers will typically add USB- protection components on the baseboard, including power-supply-current limiting or fusing components.

Rout USB data signals as differential pairs. See the ETX $^{®}$ Design Guide for details.

NOTE: For further description of USB signals, refer to Appendix A: PC Architecture Information. For information regarding over-current detection on the USB, refer to signal OVCR#

USBO +, USBO -

Universal Serial Bus Port 0. These are the serial data pairs for USB Port 0.

USB1 +, USB1 -

Universal Serial Bus Port 1. These are the serial data pairs for USB Port 1.

USB1 – positive signal. USB1# – negative signal.

USB2 +, USB2 -

Universal Serial Bus Port 2. These are the serial data pairs for USB Port 2.

USB2 – positive signal. USB2# – negative signal.

USB3 +, USB3 -

Universal Serial Bus Port 3. These are the serial data pairs for USB Port 3.

USB3 – positive signal. USB3# – negative signal.

# 4.3.3 Audio Signals

# SNDL/ SNDR

Line-level stereo output left/ right. These outputs have a nominal level of 1 volt RMS into a 10K-impedance load. These outputs cannot drive low-impedance speakers directly. See the ETX® Design Guide for typical amplifier circuits.

# AUXAL/ AUXAR

Auxiliary A input left/ right. This signal connects to an internal or external CD-ROM analog output or a similar line-level audio source. Minimum input impedance is 5KOhm. Nominal input level is 1 volt RMS.

# MIC

Microphone input. Minimum input impedance is 5KOhm, max. input voltage is 0.15 V $_{p-p}$ .

# ASGND

Analog ground for sound controller. Use this signal ground for an external amplifier to achieve lowest audio-noise levels.

# ASVCC

Analog supply voltage for sound controller. This output is used only for production test. Do not make external connections to this pin.

# 4.3.4 Miscellaneous

# SERIRQ

Serial interrupt request. This pin supports the serial-interrupt protocol.

NOTE: Refer to the ETX $^{®}$ product manual for information on the support of this signal.

# 4.4 Connector X2

# 4.4.1 ISA Signals

All required signal pullups are integrated into the ETX $^{®}$ module. In some applications, it may be desirable to add additional signal-termination components to the baseboard.

NOTE: For further description of ISA signals, refer to the Appendix A: PC Architecture Information.

# SD[0..15]

These signals provide data bus bits 0 to 15 for peripheral devices. All 8-bit devices use SD0[0..7] for data transfers. All 16-bit devices use SD[0..15].

To support 8-bit devices, the data on SD[8..15] is gated to SD[0..7] during 8-bit transfers to these devices. All 16-bit CPU cycles automatically convert to two, 8-bit cycles for 8-bit peripherals.

# SA[0..19]

Address bits 0 through 15 are used to address I/O devices. Address bits 0 through 19 are used to address memory within the system. These 20 address lines, in addition to LA[17..23], allow access of up to 16MB of memory. SA[0..19] are gated on the ISA bus when BALE is high and latched on to the falling edge of BALE.

# SBHE#

Bus High Enable indicates a data transfer on the upper byte of the data bus SD[8..15]. All 16-bit I/O devices use SBHE# to enable data-bus buffers on SD[8..15].

# BALE

BALE is an active-high pulse generated at the beginning of a bus cycle initiated by a CPU module. It indicates when the SA[0..19], LA17.23, AEN, and SBHE# signals are valid.

# AEN

AEN is an active-high output that indicates a DMA transfer cycle. Only resources with a active DACK# signal should respond to the command lines when AEN is high.

# MEMR#

MEMR# instructs memory devices to drive data onto the data bus. MEMR# is active for all memory-read cycles.

# SMEMR#

SMEMR# instructs memory devices to drive data onto the data bus. SMEMR# is active for memory-read cycles to addresses below 1MB.

# MEMW#

MEMW# instructs memory devices to store the data present on the data bus. MEMW# is active for all memory-write cycles.

# SMEMW#

SMEMW# instructs memory devices to store the data present on the data bus. SMEMW# is active for all memory-write cycles to address below 1MB.

# IOR#

I/O read instructs an I/O device to drive its data onto the data bus. It may be driven by the CPU or by the DMA controller. IOR# is inactive (high) during refresh cycles.

# IOW#

I/O write instructs an I/O device to store the data present on the data bus. It may be driven by the CPU or by the DMA controller. IOW# is inactive (high) during refresh cycles.

# IOCHK#

IOCHK# is an active-low input signal that indicates that an error has occurred on the module bus. If I/O checking is enabled on the CPU module, an IOCHK# assertion by a peripheral device sends a NMI to the processor.

# IOCHRDY

The I/O Channel Ready is pulled low to extend the read or write cycles of any bus access when required. The CPU, DMA controllers or refresh controller can initiate the cycle. A peripheral that cannot present read data or strobe in write data within this amount of time uses IOCHRDY to extend these cycles.

This signal should not be held low for more than 2.5 $\mu$ s for normal operation. Any extension to more than 2.5 $\mu$ s does not guarantee proper DRAM memory content because memory refresh is disabled when IOCHRDY is low.

# M16#

The M16# signal determines when a 16-bit to 8-bit conversion is needed for memory bus cycles. A conversion is done any time the CPU module requests a 16-bit memory cycle while the M16# line is high. If M16# is high, 16-bit CPU cycles are automatically converted on the bus into two 8-bit cycles. If M16# is low, an access to peripherals is done 16-bits wide.

# I016#

The I016# signal determines when a 16-bit to 8-bit conversion is needed for I/O bus cycles. A conversion is done any time the CPU module requests a 16-bit I/O cycle while the I016# line is high. If I016# is high, 16-bit CPU cycles are automatically converted on the bus into two 8-bit cycles. If I016# is low, an access to peripherals is done at 16-bit width.

# REFSH#

REFSH# is pulled low whenever a refresh cycle is initiated. A refresh cycle is activated every 15.6 us to prevent loss of DRAM data.

# NOWS#

The Zero wait-state signal tells the CPU to complete the current bus cycle without inserting the default wait states. By default, the CPU inserts 4 wait states for 8-bit transfers and 1 wait state for 16-bit transfers.

# MASTER#

This signal is used with a DRQ line to gain control of the system bus. A processor or a DMA controller on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DACK#. Upon receiving the DACK#, a bus master may pull MASTER# low, which will allow it to control the system address, data, and control lines. After MASTER# is low, the bus master must wait one system clock period before driving the address and data lines and two clock periods before issuing a read or write command. If this signal is held low for more than 15 us, system memory may be lost as memory refresh is disabled during this process.

# SYSCLK

SYSCLK is supplied by the CPU module and has a nominal frequency of about 8 MHz with a duty cycle of 40-60 percent. The frequency supplied by different CPU modules may vary. This signal is supplied at all times except when the CPU module is in sleep mode.

# OSC

The CPU module supplies OSC. It has a nominal frequency of 14.31818 MHz and a duty cycle of 40-60 percent. This signal is supplied at all times except when the CPU module is in sleep mode.

# RESETDRV

This active-high output is system reset generated from CPU modules. It is responsible for resetting external devices.

# DREQ[0, 1, 2, 3, 5, 6, 7]

The asynchronous DMA request inputs are used by external devices to indicate when they need service from the CPU module's DAM controllers. DREQ0..3 are used for transfers between 8-bit I/O adapters and system memory. DREQ5..7 are used for transfers between 16-bit I/O adapters and system memory. DRQ4 is not available externally. All DRQ pins have pullup resistors on CPU modules.

# DACK[0, 1, 2, 3, 5, 6, 7]#

DMA acknowledge 0..3 and 5.7 acknowledge DMA requests. They are active-low.

# TC

The active-high output TC indicates that one of the DMA channels has transferred all data.

# IRQ[3..7, 9,15]

These are the asynchronous interrupt request lines. IRQ0, 1, 2 and 8 are not available as external interrupts because they are used internally on the CPU module. All IRQ signals are inactive-high. The interrupt requests are prioritized. IRQ9 through IRQ12 and IRQ14 through IRQ15 have the highest priority (IRQ9 is the highest). IRQ3 through IRQ7 have the lowest priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from low to high. The line must be held high until the CPU acknowledges the interrupt request (interrupt-service routine).

# 4.5 Connector X3

# 4.5.1 VGA Signals

External termination components are required on the VGA analog video outputs. See the ETX $^{®}$ Design Guide for details.

NOTE: For further description of VGA signals, refer to Appendix A: PC Architecture Information.

# HSY

Horizontal Sync: This output supplies the horizontal synchronization pulse to the CRT monitor.

# VSY

Vertical Sync: This output supplies the vertical synchronization pulse to the CRT monitor.

# R, G, B

Red, green and blue analog video output signals for CRT monitors. These lines should be terminated with 75 ohms to ground at the video connector.

# DDCK, DDDA

These two pins can be used for a DDC interface between the graphics-controller chip and the CRT monitor.

# 4.5.2 LVDS Flat-Panel Interface Signals

NOTE: ETX modules may implement either this LVDS flat-panel interface or the digital interface described in section 4.5.3. Refer to the specific ETX module product manual for additional information.

# LCDDO[0..19]

LCD data output pins for LVDS support. These signals are differential and should be routed as differential pairs. See the ETX $^{®}$ Design Guide for more information.

An ETX module that supports LVDS output must implement at least LCDDO[0..7]. These four signal pairs can support a single channel TFT interface of 18 bits or less.

The implementation of LCDDO[8..19] is optional. Refer to the specific ETX product manual for information about the implementation of these signals.

Single channel LVDS links use the first channel only. Dual channel links, which are commonly used to transmit high data rates, will use both the first and second channels.

The Txout3+ and Txout3- signals are used only for 24-bit LCD panels. ETX modules that do not support 24-bit panels will not implement LCDDO[8..9] or LCCDO[18..19].

<table><tr><td>Pin Name</td><td>LVDS Signal</td><td>Channel</td></tr><tr><td>LCDD00</td><td>Txout0-</td><td>first</td></tr><tr><td>LCDD01</td><td>Txout0+</td><td>first</td></tr><tr><td>LCDD02</td><td>Txout1-</td><td>first</td></tr><tr><td>LCDD03</td><td>Txout1+</td><td>first</td></tr><tr><td>LCDD04</td><td>Txout2-</td><td>first</td></tr><tr><td>LCDD05</td><td>Txout2+</td><td>first</td></tr><tr><td>LCDD06</td><td>Txclk-</td><td>first</td></tr><tr><td>LCDD07</td><td>Txclk+</td><td>first</td></tr><tr><td>LCDD08</td><td>Txout3-</td><td>first</td></tr><tr><td>LCDD09</td><td>Txout3+</td><td>first</td></tr><tr><td>LCDD010</td><td>Txout0-</td><td>second</td></tr><tr><td>LCDD011</td><td>Txout0+</td><td>second</td></tr><tr><td>LCDD012</td><td>Txout1-</td><td>second</td></tr><tr><td>LCDD013</td><td>Txout1+</td><td>second</td></tr><tr><td>LCDD014</td><td>Txout2-</td><td>second</td></tr><tr><td>LCDD015</td><td>Txout2+</td><td>second</td></tr><tr><td>LCDD016</td><td>Txclk-</td><td>second</td></tr><tr><td>LCDD017</td><td>Txclk+</td><td>second</td></tr><tr><td>LCDD018</td><td>Txout3-</td><td>second</td></tr><tr><td>LCDD019</td><td>Txout3+</td><td>second</td></tr></table>

# BIASON

Controls contrast voltage to the panel.

# DIGON

Controls digital power to the panel.

# BLON#

Controls backlight power to the panel.

# LTGI00

General purpose I/O pin; it is not used by the JILI interface.

# JILI\_CLK, JILI\_DAT

I $^{2}$ C interface for panel parameter EEPROM. This EEPROM is mounted on JILI adapter. The data in the EEPROM allows the ETX module to automatically set the proper timing parameters for a specific LCD panel. These lines are pulled up to 3.3 volts on the ETX module. Power the EEPROM with 3.3 volts.

# DETECT#

Panel hot-plug detection. Implementation of this pin is optional. See the specific ETX module product manual for details.

# 4.5.3 Digital Flat-Panel Interface Signals

NOTE: ETX modules may implement either a parallel interface or the LVDS flat-panel interface described in section 4.5.2. Refer to the specific ETX module product manual and special design guide for additional information regarding parallel display interface.

# 4.5.4 Television Output Signals

External termination components are required on analog television outputs. See the ETX® Design Guide for details.

NOTE: Television output is not a standard ETX feature. Refer to your ETX product manual for additional information.

# SYNC

Composite Sync for RGB Video (SCART).

# Y

Analog Output: outputs either Y (Luminance) for S-Video, or Red for RGB Video (SCART).

# C

Analog Output: outputs either C (Color/Chrominance) for S-Video, or Green for RGB Video.

# COMP

Analog Output: outputs either Composite Video, or Blue for RGB Video.

# 4.5.5 Serial Port Signals

Signals for serial ports on the ETX module connectors are logic-level signals. External transceiver devices are necessary for the conversion of the logic-level signals to the desired physical interface such as RS232, RS422, or RS485. See the ETX® Design Guide for details.

# DTR1#, DTR2#

Active-low data terminal ready outputs for the serial port. The handshake output signal notifies the modem that the UART is ready to establish a data-communication link.

# RI1#, RI2#

Active-low input is for the serial port. Handshake signals notify the UART when a telephone-ring signal is detected by the modem.

# TXD1, TXD2

Transmitter serial-data output from serial port.

# RXD1, RXD2

Receiver serial-data input.

# CTS1#, CTS2#

Active-low input for serial ports. Handshake signals notify the UART when the modem is ready to receive data.

# RTS1#, RTS2#

Active-low output for serial port. Handshake signals notify the modem when the UART is ready to transmit data.

# DCD1#, DCD2#

Active-low input for serial port. Handshake signals notify the UART when a carrier signal is detected by the modem.

# DSR1#, DSR2#

This active-low input is for serial port. Handshake signals are use to notify the UART that the modem is ready to establish the communication link.

# 4.5.6 PS/2 Keyboard, PS/2 Mouse Signals

# KBDAT

Bi-directional keyboard-data signal.

# KBCLK

Keyboard-clock signal.

# MSDAT

Bi-directional mouse-data signal.

# MSCLK

Mouse-clock signal.

# 4.5.7 IRDA (SIR) Signals

# IRTX, IRRX

Infrared transmit and receive pins.

# 4.6 Parallel Port Signals

Signals for the parallel port require external termination components. See the ETX® Design Guide for details.

The parallel port has two alternative operating modes: parallel port and floppy disk. If the parallel port is used in parallel-port mode, floppy-disk support is not available via the parallel port. The LPT/FLPY# pin, which switches the parallel-port modes, is sensed only at boot and cannot be changed dynamically.

If simultaneous floppy drive and parallel support is needed, an external floppy controller may be incorporated into the baseboard design.

# LPT/FLPY#

This ETX input signal selects whether parallel-port pins will implement parallel port or floppy support functionality. There is an internal pullup on this signal. If this signal is high or unconnected, the following parallel-port pin functions are in effect:

# STB#

This active-low signal strobes the printer data into the printer.

# AFD#

This active-low output tells the printer to automatically feed the next single line after each preceding line has been printed.

# PD[0..7]

This bi-directional parallel data bus transfers information between the CPU and peripherals.

# ERR#

This active-low signal indicates an error has occurred with the printer.

# INIT#

This active-low signal initiates the printer when low.

# SLIN#

This active-low signal selects the printer.

# ACK#

This active-low output from the printer indicates that it has received the previous data and that it is ready to receive new data.

# BUSY

This signal indicates that the printer is busy and not ready to receive new data.

# PE

This signal indicates that the printer is out of paper.

# SLCT#

This active-high output from the printer indicates that its power is on.

# 4.6.1 Floppy Signals

ETX modules support only a single floppy drive over the parallel-port interface. When operating in floppy-disk mode, the parallel port is not available.

# LPT/FLPY#

This ETX input signal selects whether the parallel-port pins will implement parallel port or floppy-support functionality. There is an internal pullup on this signal. If this signal is low, the following floppy-support functions are supported over the parallel-port pins.

# DENSEL

Indicates whether a low (250/300Kb/s) or high (500/1000Kbs) data rate has been selected.

# INDEX#

This active-low Schmitt Trigger input signal is asserted by the disk drive when the diskette index hole is sensed.

# TRKO#

This active-low Schmitt Trigger input signal is asserted by the disk drive when the head is positioned over the outermost track.

# WP#

This active-low Schmitt Trigger input signal is asserted by the disk drive when a disk is write-protected.

# RDATA#

The active-low, raw-data read signal from the disk drive. Each falling edge represents a flux transition of the encoded data.

# DSKCHG#

This active-low input signal is asserted by the disk drive when the drive door has been opened.

# DRV#

This signal selects the floppy drive.

# MOT#

This active-low output activates the disk-drive motor.

# HDSEL#

This active-low output determines which disk-drive head is active.

Low = Head 0. High (open) = Head 1.

# DIR#

This active-low output determines the direction of head movement.

Low = step-in. High (open) = step-out.

# STEP#

This active-low output signal is pulsed at a software-programmable rate to move the head during a seek operation.

# WDATA#

This active-low output is a write precompensated serial-data stream to be written onto the selected disk drive. Each falling edge causes a flux change on the media.

# WGATE#

This active-low output enables the write circuitry of the selected disk drive.

# 4.7 Connector X4

# 4.7.1 IDE Signals

IDE signals are duplicated for primary and secondary IDE channels. For each signal, the first signal name is for the primary channel and the second signal name is for the secondary channel.

PIDE\_DO..15/ SIDE\_DO..15

IDE Data Bus.

PIDE\_A[0..2]/SIDE\_A[0..2]

IDE Address Bus.

PIDE\_CS1#/SIDE\_CS1#

IDE Chip Select 1. This is the Chip Select 1 command output pin that enables the IDE device to watch the Read/Write Command.

PIDE\_CS3#/SIDE\_CS3#

IDE Chip Select 3. This is the Chip Select 3 command output pin that enables the IDE device to watch the Read/Write Command.

PIDE\_DRQ/ SIDE\_DRQ

IDE DMA Request for IDE Master. This signal is asserted by an IDE device. It will be active-high in DMA or Ultra-33 mode and always be inactive-low in PIO mode.

PIDED\_AK#/SIDED\_AK#

IDE DACK# for IDE Master. This signal grants the IDE DMA request to begin the IDE Master Transfer in DMA or Ultra-33 mode.

PIDE\_RDY/ SIDE\_RDY

IDE Ready. This is the input pin from the IDE Channel. It indicates that the IDE device is ready to terminate the IDE command in PIO mode. The IDE device can de-assert this input to expand the IDE command if the device is not ready. In Ultra-33 mode, this pin has different functions. See the references for details.

PIDE\_IOR#/SIDE\_IOR#

IDE IOR# Command. This IOR# command output pin tells the IDE device to assert the Read Data in PIO and DMA mode. In Ultra-33 mode, this pin has different functions.

# PIDE\_IOW#/SIDE\_IOW#

IDE IOW# Command. This IOW# command output pin notifies the IDE device that the available Write Data is already asserted by the IDE Busmaster in PIO and DMA mode. In Ultra-33 mode, this pin has different functions.

# PIDE\_INTRQ/ SIDE\_INTRQ

Interrupt-request signal from the IDE device.

# HDRST#

Low-active hardware reset (RSTDRV inverted).

# DASP\_S

Time-multiplexed, open-collector output that indicates that a drive is active. It is also used for Master/Slave negotiation on the secondary IDE channel.

If an IDE device such as a Flash Disk exists onboard the ETX module, this signal must be connected to the DASP\_S pin of any other device connected to the secondary IDE channel.

NOTE: Refer to your ETX module product manual for additional information.

# PDIAG\_S

The signal is used for Master/Slave negotiation on the secondary IDE channel. It is asserted by the Slave to indicate to a master that the slave has passed its internal diagnostic command.

If an IDE device such as a Flash Disk exists onboard the ETX module, this signal must be connected to the PDIAG\_S pin of any other device connected to the secondary IDE channel.

On ETX modules that support DMA66 or DMA100, this pin may also detect the presence of the 80-conductor IDE cable that is needed to support these modes.

NOTE: Refer to your ETX module product manual for additional information.

# CBLID\_P

On ETX $^{®}$ modules that support DMA66 or DMA100, this pin may be used to detect the presence of an 80-conductor IDE cable on the primary IDE channel. This allows BIOS or system software to determine whether to enable high-speed transfer modes.

NOTE: Refer to your ETX $^{®}$ module product manual for additional information.

# 4.7.2 Ethernet Signals

The ETX $^{®}$ Ethernet interface is designed for use with an external 1:1/ 1:1 transformer. See the transformer specification below.

NOTE: Refer to the ETX $^{®}$ Design Guide for more information on the Ethernet interface and for routing guidelines for Ethernet signals.

# TXD-, TXD+ (Analog Twisted Pair)

Ethernet Transmit Differential Pair. These pins transmit the serial-bit stream on the Unshielded Twisted Pair (UTP) cable. The current-driven differential driver can be two-level (10BASE-T) or three-level (100BASE-TX) signals, depending on the mode of operation. These signals interface to the Ethernet cable through an isolation transformer.

# RXD-, RXD+ (Analog Twisted Pair)

Ethernet Receive Differential Pair. These pins receive the serial-bit stream from the isolation transformer. The bit stream can be transmitted in either two-level (10BASE-T) or three-level (100BASE-TX) signals, depending on the mode of operation. These signals interface to the Ethernet cable through an isolation transformer.

# ACTLED#

The Activity LED pin indicates either transmitted or received data activity on the Ethernet port. This pin is asserted low when activity is detected. It can sink 5mA to ground through an external LED and a limiting resistor to a 3.3V source.

# LILED#

The Link Integrity LED pin indicates link integrity. This pin is asserted low when the link is valid. It can sink 5mA to ground through an external LED and a limiting resistor to a 3.3V source.

# SPEEDLED#

The Speed LED pin indicates high-speed operation. This LED is not supported by all ETX boards. This pin is asserted low when a 100Mbps link is detected and is not asserted for a 10Mbps link. It can sink 5mA to ground through an external LED and a limiting resistor to a 3.3V source.

<table><tr><td colspan="2">Ethernet Transformer Specification</td></tr><tr><td>Turns ratio transmit:</td><td>1:1 +/- 5%</td></tr><tr><td>Turns ratio receive:</td><td>1:1 +/- 5%</td></tr><tr><td>Insertion Loss 1 to 60 MHz:</td><td>max. 1 dB</td></tr><tr><td>Return Loss 1 to 80 MHz:</td><td>max. 10 dB</td></tr><tr><td colspan="2">Common Mode Rejection</td></tr><tr><td>30 to 100 MHz:</td><td>max. 30 dB</td></tr><tr><td>100 to 500 MHz:</td><td>max. 20 dB</td></tr><tr><td>Cross Talk 1 to 80 MHz:</td><td>max. 35 dB</td></tr><tr><td>Hi-Pot (Pri-Sec):</td><td>min. 1500VRMS</td></tr></table>

<table><tr><td>Supported Ethernet Transformer Examples</td></tr><tr><td>Pulse H0002</td></tr><tr><td>Pulse H1012T</td></tr><tr><td>Valor MD6301NDS1</td></tr><tr><td>Valor ST6118T</td></tr><tr><td>Bel Fuse S558-5999-46</td></tr><tr><td>Delta Electronics LF8200M</td></tr></table>

# 4.7.3 Power Control Signals

# PWGIN

An active-high input to the ETX from an external power supply indicates that the power is good and that the ETX can begin booting. Use of this signal is not required because the ETX module contains its own power-good logic.

The PWGIN signal also can be used as an active-low reset input to the ETX module.

# 5V\_SB

Power input for the internal suspend and power-control circuitry. Connect to a 5V, 400mA stand-by power source available. This can be a no-connect if a standby supply is unavailable.

# PS\_ON#

Active-low output from ETX module. It can be connected to the PS\_ON# input of an ATX power supply to switch the main output. For this pin to function, 5V\_SB must be supplied to the ETX module.

# PWRBTN#

Power Button Input. Connect to GND with momentary-contact switch or open-collector driver to implement ATX power-button control of PS\_ON. For this pin to function, 5V\_SB must be supplied to the ETX module.

# 4.7.4 Power-Management Signals

NOTE: Support of these signals is not required by the ETX specification. Refer to the specific ETX product manual for information about supported power management signals.

For these pins to function while VCC is powered down, 5V\_SB must be supplied to the ETX module.

Rthese signals generally have pullup resistors to the suspend power supply inside the ETX module. Care must be taken in interfacing these signals to logic that is powered down when 5V\_SB is active.

# RSMRST#

Resume Reset input. This input may be driven low by external circuitry to reset the power-management logic on the ETX module.

# SMBALRT#

System Management Bus Alert input. This signal may be driven low by SMB devices to signal an event on the SM Bus.

# BATLOW#

Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.

# GPE1#

General-purpose, power-management event input 1. This may be driven low by external circuitry to signal an external power-management event. Within the ETX module, this pin is commonly connected to the chipset's LID# input.

# GPE2#

General-purpose, power-management event input 2. This may be driven low by external circuitry to signal an external power-management event. Within the ETX module, this pin is commonly connected to the chipset's RING# input.

# EXTSMI#

System-management-interrupt input. This may be driven low by external circuitry to initiate an SMI.

# 4.7.5 Miscellaneous Signals

# SPEAKER

PC speaker output signal. This logic-level signal can be connected to an external transistor to drive a piezoelectric or dynamic speaker.

NOTE: Refer to the ETX® Design Guide for more information.

# BATT

This is a 3V-backup-cell input. BATT is typically connected to a 3V-lithium-backup cell for RTC operation and CMOS register non-volatility in the absence of system power.

When RTC operation is not required by the application, some ETX modules can back up CMOS contents to EEPROM without using a battery.

NOTE: Refer to your ETX module product manual for RTC current requirements.

# I $^{2}$ CLK, I $^{2}$ DAT

These clock and data lines implement an I²C-bus, which supports external slave devices only. Data rate is approximate 1-10kHz. This interface supports EEPROMs and other simple I/O-devices

NOTE: Refer to your ETX product manual for additional information.

# SMBDATA, SMBCLK

System Management Bus clock and data lines. This may be used to support external SMBUS devices such as temperature and battery monitoring chips. The addresses of external SMBUS devices must be chosen so they do not conflict with addresses used internally on the ETX module. Implementation of these pins is optional. See the specific ETX module product manual for details

NOTE: Refer to your ETX product manual for additional information.

# KBINH#

Keyboard Inhibit. Asserting this pin disables data input from the keyboard. This is not supported on all ETX modules.

# OVCR#

Over-current detect input. This signal monitors the USB power over-current. Pull with open collector to GND if over-current is detected.

# ROMKBCS#, EXT\_PRG

Reserved. Do not connect to this pin.

# GPCS#

Reserved. Some modules may use this pin as an active-low programmable chip select signal or for some other module-specific functions. See product manual for documentation.

# 5. Mechanical Characteristics

# 5.1 Dimensions of ETX

![This technical drawing features a 'top view' and a 'side view' of a mechanical assembly.  **Top View:** The top section displays a rectangular outline with various dimension lines. - **Dimensions:**     - Top horizontal: **111.6**     - Top left horizontal offset: **2.4**     - Left vertical: **95 +0 -0.2** (stacked) and **92.5**     - Bottom left vertical offset: **2.5**     - Bottom left horizontal offset: **3**     - Bottom horizontal: **111** and **114**     - Right side vertical stack: **87.5**, **53.3**, **45.9**, **41.7**, **11.7**, **7.5** - **Annotations:**     - Text pointing to a corner hole: **Mounting hole Ø2.7**     - Dashed rectangles labeled **X4**, **X3**, **X2**, and **X1**.     - Circled numbers **①** and **②** indicate specific peg locations. - **Legend:**     - **①: Location peg Ø1mm +0.075mm / -0.025mm**     - **②: Location peg Ø0.7mm +0.075mm / -0.025mm** - **Title:** **top view**  **Side View:** The bottom section shows a cross-section profile. - **Visuals:** A blue rectangular block sits atop a grey structural component with small protrusions. - **Labels & Dimensions:**     - Pointer to the blue block: **heatspreader**     - Top right vertical dimension: **9.6 ± 0.4mm**     - Bottom left vertical dimension: **2mm ±0.3mm**     - Bottom right vertical dimension: **2.8mm ± 0.2mm** - **Title:** **side view** - **Subtitle:** **without heatsink**](.ETX_Specification_v3.02/91f9ca7495cc42d0f7720a75dee3c44bdaa23df4e051fb17e7c7abdfda688686.jpg)
①: Location peg ∅1mm +0.075mm / -0.025mm
②: Location peg ∅0.7mm +0.075mm / -0.025mm
side view
without heatsink

# CAUTION: DO NOT USE THIS DRAWING FOR BASEBOARD LAYOUT. (SEE SECTION 5.5).

Notes: The height (Y) dimension is 100mm (instead of 95mm) on some ETX. This does not change the relative location of the connectors and mounting holes. The 100mm height modules are interchangeable with 95mm modules.

Headers X1 to X4 (FX8-100P-SV) on ETX are 2.8mm high and connect to the corresponding receptacles on the baseboard. See Section 5.3 for baseboard-receptacle specifications.

# 5.2 Heat Spreader and Heat-sink Considerations

The heat-spreader is an Aluminium plate with variable thickness. It provides a thermal-interface surface for heat removal from the ETX module. Because of the thickness of the plate, components, which must fit under the plate, are limited to a height of 6mm unless clearance holes are provided.

Clearance holes in the heat-spreader plate are permitted for user access such as SODIMM removal or to allow the use of high-profile components up to 8mm high. All hole locations and sizes should be carefully considered so that the mechanical integrity of the heat-spreader is maintained.

The heat-spreader is thermally coupled to the CPU die or package surface, and it may also be coupled to other heat-generating devices on the module. The heat-spreader is the thermal-interface surface for most of the heat generated within the module. The heat spreader is not intended as a heat sink, although it may be suitable for this purpose on low-power modules operating under benign conditions. Higher power modules or higher temperature conditions will require heat-removal devices (such as heat sinks with fans and heat pipes) to be attached to the heat-spreader, or they may need to be thermally coupled to a chassis.

Thermal dissipation varies considerably among ETX modules and proper heat removal from the heat-spreader plate is an essential consideration for any ETX design. For maximum flexibility, ETX cooling methods should couple to as much of the heat-spreader plate area as possible because the location of the CPU varies with each ETX module design.

NOTE: Refer to your ETX module product manual for the exact definition of the heat-spreader and cooling requirements and operating temperature limits for that module

# 5.3 Specifications Baseboard Connector and Standoffs

To achieve various stacking heights, the receptacles for ETX baseboards are available in two heights.

<table><tr><td>Manufacturer</td><td>Order number</td><td>Resulting Height H between Backplane and ETX Board</td><td>Standoff Specification</td></tr><tr><td>HIROSE</td><td>FX8-100S-SV</td><td>3.0mm</td><td>3.0mm ±0.2mm</td></tr><tr><td></td><td>FX8C-100S-SV5</td><td>9.5mm</td><td>9.5mm+0.0 -0.1mm</td></tr></table>

<table><tr><td>Parameter</td><td>Hirose FX8 Series</td></tr><tr><td>Current Capacity</td><td>0.4A per pin</td></tr><tr><td>Rated voltage</td><td>100V AC</td></tr><tr><td>Insulation resistance</td><td>100MΩ or greater @ 250V DC</td></tr><tr><td>Withstand voltage</td><td>300V AC r.m.s.</td></tr><tr><td>Contact resistance</td><td>45mΩ or less @ 100mA DC</td></tr><tr><td>Insulation</td><td>PPS resin (Light brown, UL94V-0)</td></tr><tr><td>Contacts</td><td>Phosphor bronze (Contacts and leads-gold plating)</td></tr></table>

![ETX-Board H Receptacle Backplane](.ETX_Specification_v3.02/1015d1c0f3a6ea245b016fe57f6a00bbe1a8aa33d0f770e7ed881a08bef38702.jpg)

![Pure electrical connector pinout diagram without any text or symbols](.ETX_Specification_v3.02/068529dbad584857068e99e3485510e40466b608a9bfad2897f0a83261d56133.jpg)

The FX8 and FX8C connectors from HIROSE are especially designed for board-to-board connections such as on the ETX $^{®}$ form factor products. To achieve several stacking heights, different contact lengths are utilized while maintaining the same mating faces. For ETX $^{®}$ module mating only FX8 or FX8C connectors should be used. They have been fully qualified through laboratory tests and on many ETX $^{®}$ applications. All mechanical stability and PCB interference have been verified as acceptable when secured with screws or bolts. Furthermore, all dimensions and tolerances of the stand-offs are designed to match the ETX $^{®}$ Specification.

Use of the FX8C type connector requires that the baseboard designer pay special attention to the impedance level that corresponds to the different contacts lengths of the FX8C type connector.

# 5.4 PCB Footprint of Receptacle FX8-100S

![36.6±0.3 34.2±0.05 2.4±0.03 29.4±0.05 2.4±0.03 Pin 1 Ø1+.075/-.025 Pin 99 Ø0.7+.075/-.025 7.4MIN 4±0.05 1.8±0.05 Pin 2 Pin 100 1.8±0.05](.ETX_Specification_v3.02/8b83dc5219c7601d502d72f89d951bcfed2b119c369f5b4bb640199844ab8216.jpg)

![Pad Detail 1.7±0.05 0.35±0.03 0.6±0.05](.ETX_Specification_v3.02/d2ab44b820a472167ddf82fb88d3ce7f6225d429e28af2e4d1eba1fd75a94896.jpg)

# 5.5 Backplane Layout

![111.9 2.1 Mounting hole Ø2.7 ① X4 X2 ② 87.5 92.5 ① ② X3 X1 41.7 45.9 53.3 2.5 3 7.5 11.7 Reference 0,0 111 All dimensions without tolerance ±0.2mm](.ETX_Specification_v3.02/5f9ce31f2bb7cff48410435aaa11efc003fbe680f809fb1bf18e5518c089ebcb.jpg)

①: Location peg ∅1mm +0.075mm / -0.025mm
②: Location peg ∅0.7mm +0.075mm / -0.025mm

The outline shown here is for modules with a Y dimension of 95mm. To accommodate both 95mm and 100mm ETX modules, the 95mm outline shown here should be expanded by 2.5mm on the top and 2.5mm on the bottom.

The relative mounting hole and connector locations on the 95mm and 100mm modules are the same, only the Y envelope dimension varies. A given baseboard design can accommodate both 95mm and 100mm modules provided sufficient clearance is allowed for the 100mm module.

# 6. Optional Interface SATA

# 6.1 Functionality

This chapter defines a connector area to supply Serial ATA to peripheral devices.

# 6.2 Connector Area

![0.95.0 44 (mm) 114 (mm) 114.0,95.0 X4 17 (mm) X2 44 (mm) 17 (mm) 95 (mm) X3 X1 0.0 L14.0,0](.ETX_Specification_v3.02/2c1049c029a60540641f5887f8e3debcf8969d7160de27a08001211461bb6975.jpg)

Top View

# 6.3 Requirements

All the additional connectors must be compliant to the mechanical specification defined in chapter 5. It is recommended to use state of the art PC technology connectors, example :

![The image displays a black-and-white line drawing of a rectangular mechanical component, likely an electrical connector or bracket. It features two parallel slots running lengthwise along the top surface. The object has protruding tabs or flanges on its left and right sides, along with small mounting feet or holes at the bottom corners. The central area shows a ribbed or slotted detail. The drawing is presented in an isometric view. There is no text visible in the image.](.ETX_Specification_v3.02/7b6f232633eb69ac7b0d595e49974ce534d57e28df62df1154a418460cc59b52.jpg)
MOLEX 47080-4005

# 6.4 SATA Signals

There are total of 7 pins in the signal segment. The pin definitions are shown in Table below.

Table – Device plug connector pin definition

<table><tr><td rowspan="7">Signal segment</td><td>S1</td><td>Gnd</td><td> $2^{nd}$  mate</td></tr><tr><td>S2</td><td>SATA TxDx+</td><td rowspan="2">Differential signal pair A from Phy</td></tr><tr><td>S3</td><td>SATA TxDx-</td></tr><tr><td>S4</td><td>Gnd</td><td> $2^{nd}$  mate</td></tr><tr><td>S5</td><td>SATA RxDx-</td><td rowspan="2">Differential signal pair B from Phy</td></tr><tr><td>S6</td><td>SATA RxDx+</td></tr><tr><td>S7</td><td>Gnd</td><td> $2^{nd}$  mate</td></tr></table>

![SATA TxD+ SATA TxD- SATA RxD- SATA RxD+ 1 2 3 4 5 6 7 SATA](.ETX_Specification_v3.02/99676bd7975a6406ab9cb704ee4d46c30b89e765380a51c28a3aa5fbb0040522.jpg)

# 7. Appendix A: PC Architecture Information

The following sources of information can help you better understand PC architecture.

# 7.1 General PC Architecture

Embedded PCs, Markt&Technik GmbH, ISBN 3-8272-5314-4 (German)
Hardware Bible, Winn L. Rosch, SAMS, 1997, 0-672-30954-8
Interfacing to the IBM Personal Computer, Second Edition, Lewis C. Eggebrecht, SAMS, 1990, ISBN 0-672-22722-3
The Indispensable PC Hardware Book, Hans-Peter Messmer, Addison-Wesley, 1994, ISBN 0-201-62424-9
The PC Handbook: For Engineers, Programmers, and Other Serious PC Users, Sixth Edition, John P. Choisser and John O. Foster, Annabooks, 1997, ISBN 0-929392-36-1

# 7.2 Buses

# 7.2.1 ISA, Standard PS/2 – Connectors

AT Bus Design: Eight and Sixteen-Bit ISA, E-ISA and EISA Design, Edward Solari, Annabooks, 1990, ISBN 0-929392-08-6
AT IBM Technical Reference Vol 1&2, 1985
ISA & EISA Theory and Operation, Edward Solari, Annabooks, 1992, ISBN 0929392159
ISA Bus Specifications and Application Notes, Jan. 30, 1990, Intel
ISA System Architecture, Third Edition, Tom Shanley and Don Anderson, Addison-Wesley Publishing Company, 1995, ISBN 0-201-40996-8
Personal Computer Bus Standard P996, Draft D2.00, Jan. 18, 1990, IEEE Inc
Technical Reference Guide, Extended Industry Standard Architecture Expansion Bus, Compaq 1989

# 7.2.2 PC/104 and PCI

Embedded PC/104 Consortium
The consortium provides information about PC/104 and PC/104-Plus technology. You can search for information about the consortium on the Web.

PCI SIG
The PCI-SIG provides a forum for its \~900 member companies, who develop PCI products based on the specifications that are created by the PCI-SIG. You can search for information about the SIG on the Web.
PCI & PCI-X Hardware and Software Architecture & Design, Fifth Edition, Edward Solari and George Willse, Annabooks, 2001, ISBN 0-929392-63-9.
PCI System Architecture, Tom Shanley and Don Anderson, Addison-Wesley, 2000, ISBN 0-201-30974-2.

# 7.3 Ports

# 7.3.1 RS-232 Serial

EIA-232-E standard
The EIA-232-E standard specifies the interface between (for example) a modem and a computer so that they can exchange data. The computer can then send data to the modem, which then sends the data over a telephone line. The data that the modem receives from the telephone line can then be sent to the computer. You can search for information about the standard on the Web.
RS-232 Made Easy: Connecting Computers, Printers, Terminals, and Modems, Martin D. Seyer, Prentice Hall, 1991, ISBN 0-13-749854-3
National Semiconductor
The Interface Data Book includes application notes. Type “232” as search criteria to obtain a list of application notes. You can search for information about the data book on National Semiconductor’s Web site.

# 7.3.2 Serial ATA

Serial AT Attachment (ATA) Working Group

This X3T10 standard defines an integrated bus interface between disk drives and host processors. It provides a common point of attachment for systems manufacturers and the system. You can search for information about the working group on the Web.

We recommend you also search the Web for information on 4.2 I/O cable, if you use hard disks in a DMA3 or PIO4 mode.

# 7.3.3 USB

USB Specification

USB Implementers Forum, Inc. is a non-profit corporation founded by the group of companies that developed the Universal Serial Bus specification. The USB-IF was formed to provide a support organization and forum for the advancement and

adoption of Universal Serial Bus technology. You can search for information about the standard on the Web.

# 7.4 Programming

C Programmer's Guide to Serial Communications, Second Edition, Joe Campbell, SAMS, 1987, ISBN 0-672-22584-0
Programmer's Guide to the EGA, VGA, and Super VGA Cards, Third Edition, Richard Ferraro, Addison-Wesley, 1990, ISBN 0-201-57025-4
The Programmer's PC Sourcebook, Second Edition, Thom Hogan, Microsoft Press, 1991, ISBN 1-55615-321-X
Undocumented PC, A Programmer's Guide to I/O, CPUs, and Fixed Memory Areas, Frank van Gilluwe, Second Edition, Addison-Wesley, 1997, ISBN 0-201-47950-8

# 8. APPENDIX B: DOCUMENT-REVISION HISTORY

<table><tr><td>Revision</td><td>Date</td><td>Edited by</td><td>Changes</td></tr><tr><td>ETX-CPU Specification.DOC</td><td>02/08/01</td><td>C. Cooper</td><td>Made global changes to replace j with #, updated drawings, applied new template, removed sections: LCD LVDS interface, serial ports, IRDA, parallel port, FDC, IDE, &amp; audio specification.</td></tr><tr><td>ETX Specification</td><td>02/22/01</td><td>C. Cooper</td><td>Changed document title to ETX Component SBC. Updated signal names. Removed Electrical Characteristic chapter.</td></tr><tr><td>ETX Specification</td><td>03/01/01</td><td>R. Van ScoyS. Milnor</td><td>Revised some signal descriptions, added thermal management information and general editing to simplify text.</td></tr><tr><td>ETX Specification V2.5</td><td>3/22/01</td><td>B. Boyer</td><td>Formatting changes.</td></tr><tr><td>ETX Specification V2.6</td><td>5/09/01</td><td>R. Van Scoy</td><td>Revised pinout tables for X3 and X4, revised sections 4.3.2 and 4.3.3, added power management signal descriptions in 4.4.4.</td></tr><tr><td>ETX Specification V2.7</td><td>07/16/04</td><td>J. LowellD. Gunter</td><td>Revised the following chapters:3.3.2 (removed # after BUSY for Pin 86 BUSY entry in Parallel Port Mode Pinout table and deleted # sign from Pin 77 in Parallel-Port Mode Pinout and Floppy-Support Mode Pinout tables)3.4 (added # to Pin 9 KBINH, Pin 10 LILED#, Pin 12 ACTLED#, and Pin 14 SPEEDLED# in Connector X4 table)4.1.1 (changed wording in PCI Signals [General])4.3.2 (changed wording in JILI_CLK, JILI_DAT)4.3.8 (removed # from BUSY entry in signal-description section)4.4.2 (added # to Pin 10 LILED#, Pin 12 ACTLED#, and Pin 14 SPEEDLED# in signal-description section)4.4.5 (added text to GPCS# signal description)5.1 (changed mounting-hole and location-peg dimensions in Dimensions of ETX Component SBC drawing)5.3 (changed table headings)5.3.2 (deleted "Dimensions of Receptacle FX8-100S" drawing, changed location-peg dimensions and added outside dimensions in "PCB Footprint" drawing)5.4 (changed mounting-hole and location-peg dimensions in "Backplane Layout" drawing. Editing and formatting changes throughout manual.</td></tr><tr><td>ETX Specification V2.8</td><td>03/01/2006</td><td>M. Ciolacu</td><td>Changed Corporate Offices and Web Addresses</td></tr><tr><td>ETX Specification V3.0</td><td>03/22/2006</td><td>G. Vogl, M. Ciolacu</td><td>Add new chapter 6.0 Optional Interface SATA</td></tr><tr><td>ETX Specification V3.01</td><td>09/20/2006</td><td>U. Geisler, G. Vogl, M. Ciolacu</td><td>Changed to new Kontron Layout.Revised the following chapter:4.5.3 removed digital interface to option</td></tr><tr><td>ETX Specification V3.02</td><td>01/22/2007</td><td>G. Vogl, M. Ciolacu, M. Unverdorben</td><td>Changed document title to ETX Specification.Removed ETX Product Photo.Create an official neutral technical document.Remove Kontron Logo.Revised the following chapters:1.6 (changed Copyright Notice and Trademarks)1.7 Technical Support neutral document2.2 ETX Documentation neutral document3.1.1 and 4.3.2 (renamed the signals USB# and USB to USB- and USB+) and (removed text USB - positive signal. USB# - negative signal.)3.3.1 and 4.6.1 (added # to Pin 84 DRV and Pin 86 MOT)3.4.1, 4.7.2 and 4.7.3 (added # to Pin 5 PS_ON, added + to Pin 93 RXD and Pin 97 TXD, added - to Pin 91 RXD# and Pin 95 TXD#)4.5.2 LVDS Flat Panel Interface Signals. Replace “#” by “-” and add “+” after other signal without “#”4.7.3 Power Control Signals: 5V_SB changed the current from 100mA to 400mA4.7.4 (added # to EXTSMI )5.1 (changed tolerance for PCB thickness to -0.2/+0.4)5.1 Dimension of ETX&gt;&gt; removed: an ETX module, including the heat-spreader plate, has a maximum thickness of approximately 12mm. The top components are up to 8mm high, and the bottom components are up to 2mm high.5.2 Heat Spreader and Heat-Sink Considerations removed heat-spreader thickness.5.3 (added FX8 and FX8C statement)7.2.2 (renamed chapter to PC/104 and PCI)</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>
[🔗 Link to the original document](.ETX_Specification_v3.02/ETX_Specification_v3.02.pdf)