| Task | (VITA 46) or Custom COTS Approach | Typical OpenVPX Savings | Comments |
| RFP generation for System elements | Custom effortInteroperability holesNo clear way to specify system requirements | 25-50% time | OpenVPX assures common language and definitionsCommunications improved on requirements creation team |
| System design | Custom effortSignificant error-prone backplane /chassis /module investigationsDifficulty in getting agreement on needed design implementation | 50% time | OpenVPX establishes well-defined choicesSystem issues addressedPinouts, placements, protocols defined in OpenVPX specification |
| Development system readiness for integration | Significant iterations with vendors before lock downRoom for interpretation | 33% time or 50-60% time savings, if standard development chassis chosen | OpenVPX assures common language and definitionsEstablished ecosystem of standard backplane and chassis |
| Multi-vendor hardware/system integration | Rework cyclesFinger pointingCost, schedule, performance hits due to interoperability issues | 50% time | OpenVPX published common language and specifications quickly resolves conflicts |
| Risk to demonstrate readiness for initial fight-test | HighReduced qualityTechnical, management, customer, team frustration | 50%+ risk reduction for integrated system goals with a clean architecture maintained | OpenVPX reduces errors early in processOverall quality improvesOverall QRC improves |
topologies. OpenVPX supports Centralized Switching, Distributed Switching, and Master/Slave Topologies.
\- Centralized Switching: Uses dedicated switch modules in multiple types of switched configurations (e.g. Dual Star).
\- Distributed Switching: Full or partial mesh switching. May require switch logic on each card for larger slot count chassis (e.g. 5 slot sRIO mesh).
\- Master-Slave: Generally Master host SBC with Slave I/O cards connected by PCIe fabric. (e.g. SBC root complex connected to I/O cards via PCIe fabric.)
Using the OpenVPX specification taxonomy and the architectural building block language of connectivity, a system engineer or architect can now leverage the specification's content and rules for their unique application.
# OpenVPX Specification Decision Tree
The OpenVPX Specification (available now via ANSI and www.vita.com) can be used in developing open architecture, high-performance, embedded hardware solutions. OpenVPX-compliant solutions provide a compatible hardware platform for open embedded OS and middleware layering. As a result, as the target application is developed, the OpenVPX specification can provide a performance migration path to using open middleware capabilities at the module, chassis and intra-chassis levels.
Here is a simple, high level “recipe” for using the OpenVPX specification for application development:
1. Establish application requirements to determine technology choice.
2. Decide on VPX technology — 3U or 6U form factor for SWaP requirements.
3. Is integrated multi-module, perhaps multi-vendor and /or system management enabled chassis solution required?
a. No — (standalone module only) Use VITA 46 specification(s) if desired.
b. Yes — Use OpenVPX specification.
If yes, select slot and module payload profiles and, if switched architecture, switch module profiles that will allow assets to achieve (processing, throughput, management) application requirements.
Once this step in the solution development process has been reached, you have essentially constructed the architecture and topology of your development solution for application integration. You now have a clear template for design or for approaching suppliers for module, backplane and or chassis outsourcing from an ever-growing ecosystem and cadre of OpenVPX suppliers.
# Achieving Significant Results and Benefits
The OpenVPX Open Systems architecture specification gives developers the tools to create complex OpenVPX technology applications for mitigating risk to Quick Response Capabilities (QRC) development programs and, ultimately, deployment. The above table identifies a typical set of tasks that may
be considered for a QRC VPX technology development program, noting estimated benefits anticipated from using the OpenVPX systems specification as a clear decision making guide to development. As an early thought leader and major contributor to the OpenVPX specification content, Mercury Computer was able to use these concepts to create and deploy a major prime QRC program using OpenVPX-compliant architectures in just 10 months. When systems developers with domain expertise and proposal writers become proficient with using the specification, similar types of risk reduction and development efficiencies may be expected.
# The Journey Continues
A path to OpenVPX V1.1 is being developed to create an efficient method to augment the specification with new profiles in support of technology and market changes. Also, recommendations for user-defined pins are in discussion, which hopefully will result in further VITA 65 specification definition, but still allow for innovation. As a result, the team is already looking forward to ensuring that OpenVPX will stay current and relevant as the world of fast-moving technology continues to evolve.
This article was written by Bob Grochmal, Director, OpenVPX Program, Mercury Computer Systems, Inc. (Chelmsford, MA). For more information, contact Mr. Grochmal at rgrochmal@mc.com, or visit http://info.hotims.com/28057-450.
# Stroke of Genius Introducing the NEW Cobalt Series of Virtex-6 Modules!
Unleash your inner genius with Pentek's new 71620 Cobalt™ Virtex-6 XMC module. Built to optimize high-performance, wideband, communications, SIGINT, radar, beamforming and telemetry applications, this high-speed module includes:
• Three 200 MHz 16-bit A/Ds
• Dual 800 MHz 16-bit D/As
• Intelligent chaining DMA engines
• High dynamic range
- PCI Express x8
• Dedicated memory for each I/O stream
• Secondary x8 XMC for gigabit serial I/O
- Advanced gating and triggering modes optimized for radar applications
- Multi-channel, multi-board synchronization
- GateFlow® FPGA Design Kit
- VPX, XMC, PCI, PCIe, VME/VXS, cPCI, conduction-cooled XMC
With extensive resources and new enhancements in DSP engines, block RAM, logic and clocking technology, the Virtex-6 family represents the industry's most advanced FPGAs.
Call 201-818-5900 or go to www.pentek.com/go/v6vpx for your FREE Putting FPGAs to Work in Software Radio Handbook, technical datasheets and price quotations.
PENTEK
Setting the Standard for Digital Signal Processing
# Transitioning to OpenVPX for Next-Generation C4ISR Systems
VPX systems offer tremendous performance for the Mil/Aero market, including naval, airborne, and ground-based computing systems. The architecture provides an unprecedented combination of bandwidth, user IO, and rugged design, in both a 3U and 6U Eurocard format. The new OpenVPX initiative has opened up new definitions for VPX system interoperability, including defined module profiles, slot profiles, backplane & chassis configurations, secondary expansion fabrics and control planes, and higher speed fabric options.
# Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR)
C4ISR embedded computing systems have certain general needs, both today and continuing into the future. These include:
- Mission-critical reliability – For Mil/Aero applications, system failures can cost lives.
- Higher bandwidth – Weapon and intelligence gathering platforms are using more intensive digital signal processing for gathering, relaying, and processing data.
- Rugged design – Platforms need to survive the shock, vibration, and effects in aircraft, ground, and sea
based applications.
- Stable architecture, less risk – Platforms need to last many years, even decades. Vendor support is also critical.
- Performance density – As space restrictions get tighter, the system needs options for small form factors while retaining high performance.
VPX, and later OpenVPX, were collaboratively created within VITA (VME International Trade Association) by dozens of experts in the military/aerospace community. Based on the rugged Eurocard format like VME and CompactPCI, VPX comes in both 3U and 6U standard board sizes with typically 1.0" pitch (0.80" and 1.2" pitch are also possible). VPX uses a high-speed Multi-Gig connector and offers plenty of IO in a rugged, open standard architecture. With dozens of vendors and some backwards compatibility options to VME, the architecture is stable and will be supported for years to come.
# OpenVPX for System Interoperability
If there is any fault with VPX, it was made to be very flexible. This flexibility was beneficial for customized solutions, particularly for how high-speed IO is transported throughout the system. However, it was difficult, if not impossible, to be assured that a board from one vendor would work with one from
Figure 1. Figure 1a shows a standard 6U 5-slot VPX backplane and 1b shows a simple side-view diagram of how the J0-J6 connectors are used.
another vendor, along with a backplane from yet another party. Therefore, the OpenVPX initiative commenced in early 2009 with a goal of providing interoperability definitions for the VPX specification. The initiative was rolled into VITA as the VITA 65 specification, which was approved by ANSI in June 2010.
In short, OpenVPX provides definitions for backplane configurations, which are comprised of slot profiles into which various module profiles can be plugged. The module and slot profiles ensure that a vendor's VPX boards (modules) have pinouts that are interoperable within the VPX backplane slots. The backplane configuration tells the user which slot profiles are utilized, including information on the data rate, routing topology, and fabric used.
When it comes to backplane functionality, there is very little change. The new standard simply redefined two reserved P0/J0 signals Aux\_Clk (+/-) and added one P1/J1 single ended Utility signal of Maskable Reset and redefined the Res\_Bus signal to GDiscrete. The Aux\_Clk and GDiscrete pins were already bussed anyway, so the change is minimal. Also, the SysCon signal is now configurable.
Let's take a look at a standard 6U VPX 5-slot Mesh backplane and compare it to an OpenVPX version. Figure 1a shows a 6U 5-slot VPX backplane and 1b shows a side-view of how the J0-J6 connectors are used.
The standard VPX version has pinout charts for P0 and P1 sections with the P2-P6 as “undefined”. Although the P0 and P1 sections have defined pinouts, there are no details in VPX as to the kind of signals such as thin pipes, fat pipes, or ultra thin pipes. Also, the details of the utility plane are not as clear.
In the OpenVPX version of the same backplane, Figure 2 shows the payload slot profile. It provides more information for the data plane section (in yellow), which in this case defines 4 fat pipe lanes. Also, the utility plane sections are clearer. Although this backplane does not have a control plane, if it had one we'd also see this in the payload slot profile, along with the type of signal (thin pipes are commonly used for the control plane).
The Slot Profile that is referenced in Figure 2 gives us some details on the card plugging into the slot. For example, the slot profile number SLT6 says it's a 6U slot
# GE Intelligent Platforms
# It's an open specification.
So it's only fitting that our 136-page reference guide is free.
Think of this reference book as Cliffs Notes for VPX and OpenVPX. It's that comprehensive and easy to read. It covers all the key topics, including the VITA 46 (VPX) specification, VITA 48 (VPX REDI), and VITA 65 (OpenVPX). It covers the history and rationale for VPX, its underlying principles and features, describes in detail important technical information, and illustrates the content with over 50 diagrams, charts and photos. Ordering one is a no-brainer.
Order your free copy at www.ge-ip.com/vpx
imagination at work
OpenVPX
© 2010 GE Intelligent Platforms, Inc. All rights reserved. All other brands or names are property of their respective holders.
Free Info at http://info.hotims.com/28057-844 profile (a 6U board), the PER says it's a peripheral slot, 4F means it has 4 fat pipes and the 10.3.1 is where you can find details on this slot profile in the VITA 65 specification. For OpenVPX, fat pipes have 4 links (4 Tx pairs + 4 Rx pairs), thin pipes have 2 links, and ultra thin pipes have one link. The wider bands, like fat pipes, are typically used in the data plane, while the control plane will often have the thin pipe or ultra thin-pipe signals. Slot types are comprised of peripheral slots, payload slots, switch slots, or bridge slots.
Figure 2. A Slot Profile of an OpenVPX (VITA 65 compliant) version of the 6U 5-slot backplane. The profile provides more details on the data signals, utility plane, and more.
The backplane profile of the backplane also provides more information. For example, this 6U 5-slot's profile is
BKP6-DIS05-11.2.16-1. The BKP6 tells us it's a 6U backplane profile. DIS05 means it's a distributed (like a mesh or ring) architecture and has 5 slots. The 11.2.16 is the section of the specification where you can find details on this backplane profile. The “-1” tells us the data rate is 3.125 Gbps (-2 means 5 Gbps and -3 means 6.250 Gbps).
The backplane profile chart in Figure 3 shows the profile name, the pitch, the corresponding slot profile for the backplane, the control plane data rate (if applicable) and the data rate of the backplane.
The slot type (like DIS05) section of the profile name is an important part of