# Open Standard Module

# Hardware Specification

![Abstract graphic with three colored rounded rectangles (pink, black, yellow) on a white background, no text or symbols present.](.osm-specification-v1-0/e464c176e4da478c36e333cb0ece39e7d3c354944e5d9a2c490d601cf10771c5.jpg)

# OPEN STANDARD MODULE TM

OSM\_V1.0.docx

Dec 09, 2020

![SGeT](.osm-specification-v1-0/ebe063619689dce1453979cf67293998d25dd477db79361aa6a48ccdb7c166fd.jpg)

STANDARDIZATION

EMBEDDED

TECHNOLOGIES

# 1 INTRODUCTION

# 1.1 Legal

# 1.1.1 Copyright

© Copyright 2020, SGET Standardization Group for Embedded Technology e.V.

All Open Standard Modules™ shall be published and licensed under Creative Commons Plus (CC+) Dual License. This allows an open license model, like Creative Commons Attribution-ShareAlike License (CC BY-SA 4.0) for a defined set of materials, components and software as well as for a commercial license for everything that is not included in this set. For example, block diagrams, Altium libraries and BOM might be included in the set, but not Altium design files. Thus, it is possible to license services or custom developments under a commercial license without violating the open-source idea.

# 1.1.2 Intellectual Property

This SGET document conforms to the current SGET® Intellectual Property Rights Policy as incorporated in the “Agreement on Intellectual Property Rights (IPR) on work results from the working groups of the registered association SGET (SGET)” which supplements the SGET Statutes and the SGET Standards Development Team (SDT) procedures.

Accordingly, it has to be noted that patent rights and other intellectual property rights not held by SGET may legally protect some content of this SGET document. SGET is not obligated to identify the parts of this specification that require licensing or other legitimization. The contents of this SGET document are advisory only. Users of SGET documents are responsible for protecting themselves against liability for infringement of patents. This SGET document does not contain any intellectual property known to the Standards Development Team (SDT) of this document which might be relevant for the specification defined herein, other than the intellectual property identified below. Please contact the respective patentee for further information. SGET makes no judgment as to the validity of these claims or the licensing terms offered by the claimants.

A) Intellectual property available for licensing under reasonable and non-discriminatory terms.

DE patent application 10 2019 115 189.9 (iesy GmbH & Co. KG) This patent application covers certain aspects of the Open Standard Module™ specification. iesy GmbH & Co. KG has assured SGET that it is willing to provide a non-exclusive, free license of DE patent application 10 2019 115 189.9 and all intellectual property rights evolving from this patent application to those licensees (Members and non-Members alike) desiring to implement this specification.

B) Intellectual property with undetermined licensing availability: US patent US 9,510,461 (Samsung Electro-Mechanics Co., Ltd.), including patent family members KR 101548799 and

CN patent CN 104241256

These patents relate to insulation of soldered joints between base boards and module boards/spacers by means of hot-melt tape, thermal bonding tape or thermosetting bonding tape The SDT believes that these patents do not directly impact the Open Standard Module™ specification which does not define such insulation. They might, however, be relevant for implementations, which seek to use additional insulation.

# 1.2 Disclaimers

SGET provides no warranty with regard to this SGET document or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. SGET assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and this SGET document. In no event shall SGET be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this SGET document or any other information contained herein or the use thereof.

Compliance with this specification does not absolve manufacturers of Open Standard Module™ equipment from the requirements of safety and regulatory agencies (EN, UL, CSA, FCC, IEC, etc.).

All content and information within this document are subject to change without prior notice.

# 1.3 Revision History

<table><tr><td>Rev</td><td>Date</td><td>Originator</td><td>Notes</td></tr><tr><td>1.0</td><td>Nov 09, 2020</td><td>M. Unverdorben</td><td>Initial Release of OSM specification</td></tr></table>

Table 1: Revision History

# 1.4 Table of Contents

# Introduction ...

1.1 Legal .... 2

1.1.1 Copyright...... .2

1.1.2 Intellectual Property .... 2

1.2 Disclaimers ..... 3

1.3 Revision History .... . 3

1.4 Table of Contents . 4

1.5 List of Figures .. . 5

1.6 List of Tables... . 6

1.7 General Introduction ... . 8

1.8 Purpose of This Document .. . 8

1.9 Document and Standards References ... . 8

# 2 TECHNICAL SPECIFICATON .......... ............... 10

2.1 General Module Features .... . 10

2.1.1 Module Size Overview . ..10

2.1.2 Module Outline Overview .............. .....10

2.1.3 Outline Dimensions... ..11

2.1.4 Interface Overview ... ..16

2.1.5 Required and Optional Feature Table ............ ....17

2.1.6 Footprint Grid ...... ....20

2.1.7 Contacts Characteristics . ..21

2.2 Module Height Specification ........ . 23

2.2.1 Standard Height F.. .23

2.2.2 Extended Height E ..... ...24

2.2.3 RF Antenna Connector Area. ..28

2.2.4 Standard Metal Shielding.... .29

2.2.5 Breakout Area and Tolerances ..30

2.3 Electrical Interfaces .... .. 32

2.3.1 Contact Grid.. ..32

2.3.2 Contact Overview... ..33

2.3.3 Size-0 – Basic Functions.. ..34

2.3.4 Size-S – ADDITIONAL Functions ............ .....36

2.3.5 Size-M – ADDITIONAL Functions ............ .....38

2.3.6 Size-L – ADDITIONAL Functions ............ ......40

2.4 Contact Tables.. . 43

2.4.1 Signal Descriptions .. ...43

2.4.2 Size-0 Basic Functionality ... ..45

2.4.3 Size-S – Additional Functionality.. ..65

2.4.4 Size-M – Additional Functionality . ..76

2.4.5 Size-L – Additional Functionality .. ..87

2.5 Module Designation .... ... 96

2.6 Packing and Production Technologies .. .. 97

2.6.1 Packing Method ........ ....97

2.6.2 Handling Instruction .. ..99

# 3 Software..... . 101

3.1 Bootloader... . 101
3.2 Operating System ........ . 101
3.3 APIs . . 101
3.4 Others ... . 101
4 Accessories... .. 102
4.1 Evaluation Carrier Board . .. 102
4.2 Cooling solution ..... . 102
5 Certification / Compliance ..... .. 103
6 Appendix... .. 104
6.1 Abbreviations . 104

# 1.5 List of Figures

Figure 1: Overview (view from top, through the module) . .... 10
Figure 2: Sizes (view from top, through the module)... .... 11
Figure 3: Size-0 Dimension and Footprint (view from top, through the module). .. 12
Figure 4: Size-S Dimension and Footprint (view from top, through the module) . .... 13
Figure 5: Size-M Dimension and Footprint (view from top, through the module).. .. 14
Figure 6: Size-L Dimension and Footprint (view from top, through the module). .... 15
Figure 7: Footprint Grid Dimensions, Size-S upper left corner (view from top, through the module) .............. 20
Figure 8: Fused Tin Grid Array bottom view.... .. 21
Figure 9: ENIG LGA package (bottom side)...... .. 22
Figure 10: BGA package (bottom side) ...... .. 22
Figure 11: Sectional view on Standard Height F (“Flat” module) ... .. 23
Figure 12: Sectional view on Standard Height E ("Extended" module)..... .. 24
Figure 13: Schematic illustration of the Spacer PCB for Extended Height E (Size-S).... .. 25
Figure 14: Placement Area (left) and Cut-Out Area (right) - Size S (view from bottom) .. .. 26
Figure 15: Placement Area (left) and Cut-Out Area (right) - Size M (view from bottom) . .. 27
Figure 16: Placement Area (left) and Cut-Out Area (right) - Size L (view from bottom) ..... .. 27
Figure 17: RF Antenna Connector Area (all sizes) (view from top, through the module) . .28
Figure 18: PCB RF Metal shielding (example) .. .. 29
Figure 19: Breakout Areas (all sizes) (view from top, through the module) ..... .. 30
Figure 20: Tolerances Breakout Areas (all sizes) . .... 31
Figure 21: Contact Grid (all sizes) (view from top, through the module) .. .. 32
Figure 22: Contact Overview (all sizes) ...... .... 33
Figure 23: Size-0 - detailed contact overview ....... .... 35
Figure 24: Size-S detailed Contact Overview........ ... 37
Figure 25: Size-M detailed Contact Overview .............. .... 39
Figure 26: Size-L Detailed Contact Overview ........ ... 42
Figure 27: JEDEC Tray....... .... 97
Figure 28: Reel ...... ..... 98

# 1.6 List of Tables

Table 1: Revision History... . 3
Table 2: Interface Overview for each size ... ... 16
Table 3: Required and Optional Features ... ... 19
Table 4: Size-0 – Function Table.. .. 34
Table 5: Size-S Changes to Size-0 ... .. 36
Table 6: Size-S Additional Functionality / Interfaces ... .. 36
Table 7: Size-M Changes to Size-0... .. 38
Table 8: Size-M Additional Functionality / Interfaces .. 38
Table 9: Size-L Changes to Size-0.. ... 40
Table 10: Size-L Additional Functionality / Interfaces ......... ...... 40
Table 11: Contact Types...... .... 43
Table 12: Buffer Types ... .. 44
Table 13: Size-0 Power ........... ...... 46
Table 14: Size-0 JTAG .... ... 47
Table 15: Size-0 UART..... .... 48
Table 16: Size-0 UART Console . ... 49
Table 17: Size-0 Ethernet... .... 51
Table 18: Size-0 GPIO... ... 52
Table 19: Size-0 SDIO... .. 54
Table 20: Size-0 PWM.. .. 55
Table 21: Size-0 Analog Signals . ... 55
Table 22: Size-0 SPI.... .... 56
Table 23: Size-0 I2S . .. 57
Table 24: Size-0 CAN.. .... 57
Table 25: Size-0 USB .. .. 58
Table 26: I2C ... .... 59
Table 27: Size-0 Communication Area - Wireless Mode... .... 61
Table 28: Size-0 Communication Area - Fieldbus Mode..... ... 63
Table 29: Size-0 Reserved Contacts..... ... 64
Table 30: Size-S Power + Ground.. ... 65
Table 31: Size-S: Ethernet...... .... 66
Table 32: Size-S GPIO ... ... 67
Table 33: Size-S MIPI DSI.. .... 68
Table 34: Size-S MIPI CSI.. .... 70
Table 35: Size-S Parallel RGB Display ... .. 72
Table 36: Size-S UFS.... .... 73
Table 37: Size-S PCIe ....... .... 74
Table 38: Size-S Reserved Contacts ... ... 75
Table 39: Size-S Vendor Defined Contacts... ... 75
Table 40: Size-M Power + Ground . .... 76
Table 41: Size-M Ethernet.. .. 77
Table 42: Size-M GPIO...... ..... 78
Table 43: Size-M SPI.... ..... 79
Table 44: Size-M UFS . .. 80
Table 45: Size-M USB . .. 81

Table 46: Size-M PCIe... ... 82
Table 47: Size-M eDP.. .. 85
Table 48: Size-M Reserved Contacts............ ..... 86
Table 49: Size-M Vendor Defined Contacts ... .. 86
Table 50: Size-L Power + Ground .. .. 87
Table 51: Size-L Ethernet ....... ..... 89
Table 52: Size-L GPIO.. .. 90
Table 53: Size-L LVDS .. .. ... 92
Table 54: Size-L PCIe x4........ .... 94
Table 55: Size-L Reserved Contacts..... .... 95
Table 56: Vendor Defined Contacts .. . 95
Table 57: Abbreviations .......... ............. 104

# 1.7 General Introduction

The idea of all Open Standard Modules™ is to create a new, future proof and versatile standard for smallsize, low-cost embedded computer modules, combining the following key characteristics:

Completely machine processible during soldering, assembly and testing

Pre-tinned LGA package for direct PCB soldering without connector

Pre-defined soft- and hardware interfaces

Open-Source in soft- and hardware

The Open Standard Module™ specification allows developing, producing and distributing embedded modules for the most popular MCU32, ARM and x86 architectures. For a growing number of IoT applications this standard helps to combine the advantages of modular embedded computing with increasing requirements regarding costs, space and interfaces.

# 1.8 Purpose of This Document

This document defines the Module mechanical, electrical, signal and thermal parameters at a level of detail sufficient to provide a framework for OSM Module and Carrier Board designs.

# 1.9 Document and Standards References

BT.656 (“Recommendation ITU-R BT.656-5 Interface for digital component video signals in 525-line and 625-line television systems operating at the 4:2:2 level of Recommendation ITU-R BT.601”), International Telecommunications Union, December 2007 (www.itu.int)
 CAN (“Controller Area Network”) Bus Standards – ISO 11898, ISO 11992, SAE J2411
CSI-2 (Camera Serial Interface version 2) The CSI-2 standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)
CSI-3 (Camera Serial Interface version 3) The CSI-2 standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)
COM Express – the formal title for the COM Express specification is “PICMG® COM.0 COM Express Module Base Specification”, Revision 2.0, August 8, 2010. This standard is owned and maintained by the PICMG (“PCI Industrial Computer Manufacturer’s Group”) (www.picmg.org)
DisplayPort and Embedded DisplayPort These standards are owned and maintained by VESA (“Video Electronics Standards Association”) (www.vesa.org)
D-PHY CSI-2 physical layer standard – owned and maintained by the MIPI Alliance (www.mipi.org)
DSI (Display Serial Interface) The DSI standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)
eMMC (“Embedded Multi-Media Card”) The eMMC electrical standard is defined by JEDEC JESD84- B45 and the mechanical standard by JESD84-C44 (www.jedec.org)
eSPI (“Enhanced Serial Peripheral Interface”) The eSPI Interface Base Specification is defined by Intel (https://downloadcenter.intel.com/de/download/22112)
Fieldbus - this term refers to a number of network protocols used for real – time industrial control. Refer to the following web sites: www.profibus.com/downloads and www.canopen.org
GBE MDI (“Gigabit Ethernet Medium Dependent Interface”) This is defined by IEEE 802.3. The 1000Base-T operation over copper twisted pair cabling is defined by IEEE 802.3ab (www.ieee.org)
 I2C Specification, Version 2.1, January 2000, Philips Semiconductor (now NXP) (www.nxp.com)
 I2S Bus Specification, Feb. 1986 and Revised June 5, 1996, Philips Semiconductor (now NXP) ()
IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (http://standards.ieee.org/findstds/standard/1588-2008.html)

JTAG (“Joint Test Action Group”) This is defined by IEEE 1149.1-2001 - IEEE Standard Test Access Port and Boundary Scan Architecture (www.ieee.org )
MXM3 Graphics Module Mobile PCI Express Module Electromechanical Specification, Version 3.0, Revision 1.1, © 2009 NVidia Corporation (www.mxm-sig.org)
 PICMG® EEEP Embedded EEPROM Specification, Rev. 1.0, August 2010 (www.picmg.org)
 PCI Express Specifications (www.pci-sig.org)
Serial ATA Revision 3.1, July 18, 2011, Gold Revision, © Serial ATA International Organization (www.sata-io.org)
SD Specifications Part 1 Physical Layer Simplified Specification, Version 3.01, May 18, 2010, © 2010 SD Group and SD Card Association (“Secure Digital”) (www.sdcard.org)
SPI Bus – “Serial Peripheral Interface” – de-facto serial interface standard defined by Motorola. A good description may be found on Wikipedia (http://en.wikipedia.org/wiki/Serial\_Peripheral\_Interface\_Bus )
USB Specifications (www.usb.org)

# 2 TECHNICAL SPECIFICATON

# 2.1 General Module Features

# 2.1.1 Module Size Overview

The Open Standard Module™ is made up of four different sizes that build upon each other:

Size-0 – “Zero”: 30 mm x 15 mm / with 188 contacts →
Size-S – “Small”: 30 mm x 30 mm / with 332 contacts →
Size-M – “Medium”: 30 mm x 45 mm / with 476 contacts→
Size-L – “Large”: 45 mm x 45 mm / with 662 contacts →
shown below with red outlines
shown below with blue outlines
shown below with orange outlines
shown below with green outlines

# 2.1.2 Module Outline Overview

![Pure geometric pattern with repeating circular and rectangular blocks (no text or symbols)](.osm-specification-v1-0/4ea16b316f6af8c09f90e9c9f87827a212c6be4d3763aafabd4555590fda940a.jpg)

Figure 1: Overview (view from top, through the module)

# 2.1.3 Outline Dimensions

The Open Standard Module™ is made up of four different sizes that build upon each other:

Size-0 – “Zero”: 30 mm x 15 mm
 Size-S – “Small”: 30 mm x 30 mm
 $\mathsf { S i z e - M - } \mathsf { \ " { M e d i u m } } \mathsf { : } 3 0 \mathsf { m m } \mathsf { \times } 4 5 \mathsf { m m }$
Size-L – “Large”: 45 mm x 45 mm

![30 mm 45 mm 45 mm 30 mm 15 mm](.osm-specification-v1-0/9917d8346c36abc37595618042e9f64506786d38333176cb22a2f05e6105681b.jpg)

Figure 2: Sizes (view from top, through the module)

# 2.1.3.1 Size-0

![  Dimension   Value         ---------   ---------     Top Width   30 mm         Bottom Width   15 mm     ](.osm-specification-v1-0/708fcd8a8769eaa1c4665a5a53158253c52532b3972f5fba9c290550ef535c75.jpg)

Figure 3: Size-0 Dimension and Footprint (view from top, through the module)

# 2.1.3.2 Size-S

![  Dimension   Value     ---------   -----     Total Height   30 mm     Top Width   30 mm     Bottom Width   30 mm  ](.osm-specification-v1-0/91b6982594da43a2bfcc3658e3a286ecfcb9acf4e34e23e26365ee41e2d113ef.jpg)

Figure 4: Size-S Dimension and Footprint (view from top, through the module)

# 2.1.3.3 Size-M

![  Row   Height (mm)    ----- -------------    1     30              2     30              3     30              4     30              5     30              6     30              7     30              8     30              9     30              10    30              11    30              12    30              13    30              14    30              15    30              16    30              17    30              18    30              19    30              20    30              21    30              22    30              23    30              24    30              25    30              26    30              27    30              28    30              29    30              30    30              31    30              32    30              33    30              34    30              35    30              36    30              37    30              38    30              39    30              40    30              41    30              42    30              43    30              44    30              45    30           ](.osm-specification-v1-0/5bc33a23e8f37b30d447f63202ae49f8e5e61efa993af51db56fb7b206d1f995.jpg)

Figure 5: Size-M Dimension and Footprint (view from top, through the module)

# 2.1.3.4 Size-L

![  Row   Height (mm)    ----- -------------    1     45              2     45              3     45              4     45              5     45              6     45              7     45              8     45              9     45              10    45              11    45              12    45              13    45              14    45              15    45              16    45              17    45              18    45              19    45              20    45              21    45              22    45              23    45              24    45              25    45              26    45              27    45              28    45              29    45              30    45              31    45              32    45              33    45              34    45              35    45              36    45              37    45              38    45              39    45              40    45              41    45              42    45              43    45              44    45              45    45              46    45              47    45              48    45              49    45              50    45              51    45              52    45              53    45              54    45              55    45              56    45              57    45              58    45              59    45              60    45              Note: The actual values for each row are not provided in the code. The numbers inside the cells are estimated based on the visual data and the number of rows in the cells. There is only one data series in this case. The values for the last row are estimated based on the visual data and the number of rows in the cells.](.osm-specification-v1-0/9655a5a31f822317ca68b829faac1a05740a91d12eff9675ac4c3132bf33042f.jpg)

Figure 6: Size-L Dimension and Footprint (view from top, through the module)

# 2.1.4 Interface Overview

<table><tr><td>Feature</td><td>Sub Feature</td><td>Size-0</td><td>Size-S</td><td>Size-M</td><td>Size-L</td></tr><tr><td>01</td><td>Ethernet / LAN (Q)(S)(R)(G)MII</td><td>0 ... 1</td><td>0 ... 2</td><td>0 ... 3</td><td>0 ... 5</td></tr><tr><td>02</td><td>USB 2.0</td><td>0 ... 2</td><td>1 ... 3</td><td>1 ... 4</td><td>1 ... 4</td></tr><tr><td>03</td><td>USB 3.0 (w/o USB 2.0)</td><td>-</td><td>0 ... 1</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>04</td><td>UART Console</td><td>1</td><td>1</td><td>1</td><td>1</td></tr><tr><td>05</td><td>UART (Rx/Tx only, 2 x with RTS/CTS)</td><td>0 ... 4</td><td>0 ... 4</td><td>0 ... 4</td><td>0 ... 4</td></tr><tr><td>06</td><td>- Communication Area- Wireless (Antenna Signals)- Wired (Fieldbus Signals)</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>07</td><td>GPIO contacts</td><td>0 ... 15</td><td>0 ... 23</td><td>0 ... 31</td><td>0 ... 39</td></tr><tr><td>08</td><td>SPI (1 x Quad SPI optional)</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 3</td><td>0 ... 3</td></tr><tr><td>09</td><td>I2C (general purpose, besides Display, etc.)</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>10</td><td>I2S / PDM</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>11</td><td>SDIO (with 4 lane + 8 lane interface)</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>12</td><td>UFS</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>13</td><td>CAN</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>14</td><td>JTAG</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>15</td><td>Analog Input contacts</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>16</td><td>PWM signals</td><td>0 ... 6</td><td>0 ... 6</td><td>0 ... 6</td><td>0 ... 6</td></tr><tr><td>17</td><td>Power Supply via 3.3V contacts</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>18</td><td>Power Supply via 5V contacts</td><td>0 ... 1</td><td>5</td><td>9</td><td>17</td></tr><tr><td>19</td><td>Vendor Defined Contacts (up to)</td><td>3</td><td>7</td><td>13</td><td>19</td></tr><tr><td>20</td><td>Reserved Contacts (up to)</td><td>9</td><td>11</td><td>27</td><td>58</td></tr><tr><td>21</td><td>Parallel Display Interface (RGB with 18 bit)</td><td>-</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>22</td><td>Display Serial Interface (DSI with 4 channels)</td><td>-</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>23</td><td>Camera Serial Interface (CSI with 4 channels)</td><td>-</td><td>0 ... 1</td><td>0 ... 1</td><td>0 ... 1</td></tr><tr><td>24</td><td>PCIe x1</td><td>-</td><td>0 ... 1</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>25</td><td>PCIe x4 (configurable as PCIe x1 / PCIe x2)</td><td>-</td><td>-</td><td>-</td><td>0 ... 2</td></tr><tr><td>26</td><td>Embedded DisplayPort (eDP/eDP++)</td><td>-</td><td>-</td><td>0 ... 2</td><td>0 ... 2</td></tr><tr><td>27</td><td>LVDS Display Interface</td><td>-</td><td>-</td><td>-</td><td>0 ... 1</td></tr></table>

Table 2: Interface Overview for each size\*

# 2.1.5 Required and Optional Feature Table

Required and optional features for an OSM are summarized in the table below.

“Shall” indicates a mandatory requirement

“Should” indicates a recommended but not mandatory requirement

“May” indicates a lesser used optional interface

$" 6 1 \pmb { \mathbb { A } } ^ { 5 }$ indicates an optional interface, which is not allowed to be implement

$^ { 6 6 } - ^ { 5 9 }$ indicates an interface, that is not available in this size

<table><tr><td>Feature</td><td>Sub Feature</td><td>Size 0</td><td>Size S</td><td>Size M</td><td>Size L</td></tr><tr><td>Ethernet</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Ethernet A (Q)(S)(R)(G)MII</td><td>Should</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td></td><td>Ethernet B (Q)(S)(R)(G)MII</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>Ethernet C (Q)(S)(R)(G)MII</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>Ethernet D (Q)(S)(R)(G)MII</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>Ethernet E (Q)(S)(R)(G)MII</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td>USB</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>USB A</td><td>Should</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td></td><td>USB A as Dual Role</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>USB A as host</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>USB B as host</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>USB C as USB 2.0 host</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>USB C as USB 3.0 host</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>USB C as USB 2.0 Dual Role</td><td>-</td><td>NA</td><td>NA</td><td>NA</td></tr><tr><td></td><td>USB C as USB 3.0 Dual Role</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>USB D as USB 2.0 host</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>USB D as USB 3.0 host</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>USB D as USB 2.0 Dual Role</td><td>-</td><td>-</td><td>NA</td><td>NA</td></tr><tr><td></td><td>USB D as USB 3.0 Dual Role</td><td>-</td><td>-</td><td>NA</td><td>NA</td></tr><tr><td>Serial Ports</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>UART Console</td><td>Shall</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td></td><td>UART A</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>UART A Handshake Support</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>UART B</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>UART B Handshake Support</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>UART C</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>UART D</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td>Communication Area</td><td></td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>Wireless Mode</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>Fieldbus Mode</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td>GPIO</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>GPIO[0:15]</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>GPIO[0:15] interrupt capability</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>GPIO[16:23]</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>GPIO[16:23] interrupt capability</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>GPIO[24:31]</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>GPIO[24:31] interrupt capability</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td>SPI</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>SPI A</td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td></td><td>SPI B</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>SPI C</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td>I2C</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>I2C A</td><td>Should</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td></td><td>I2C B</td><td>May</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td>Audio</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>I2S A</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>I2S B</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td>RTC</td><td></td><td>Shall</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td>JTAG</td><td></td><td>Should</td><td>Should</td><td>Should</td><td>Should</td></tr><tr><td>UFS</td><td></td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td>CAN</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>CAN A</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>CAN B</td><td>May</td><td>May</td><td>May</td><td>May</td></tr></table>

<table><tr><td>PWM</td><td>PWM[0:5]</td><td>May</td><td>May</td><td>May</td><td>May</td></tr><tr><td>Power</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>VCC supply via 3.3V</td><td>Should</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>VCC supply via 5V</td><td>May</td><td>Shall</td><td>Shall</td><td>Shall</td></tr><tr><td></td><td>Flexible IO voltage (controlled by module)</td><td>May</td><td>NA</td><td>NA</td><td>NA</td></tr><tr><td>Display Interfaces</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Parallel Display Interface (RGB with 18 bit)</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>Display Serial Interface (DSI with 4 channels)</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>Embedded DisplayPort (eDP)</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>LVDS Display Interface</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td>Camera Interface</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>CSI – 2 lane support</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>CSI – 4 lane support</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td>PCIe</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>PCIe A</td><td>-</td><td>May</td><td>May</td><td>May</td></tr><tr><td></td><td>PCIe B</td><td>-</td><td>-</td><td>May</td><td>May</td></tr><tr><td></td><td>PCIe C 4 x x1 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>PCIe C 2 x x2 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>PCIe C 1 x x4 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>PCIe D 4 x x1 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>PCIe D 2 x x2 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr><tr><td></td><td>PCIe D 1 x x4 lanes</td><td>-</td><td>-</td><td>-</td><td>May</td></tr></table>

Table 3: Required and Optional Features

# 2.1.6 Footprint Grid

The Contact Grid for the Open Standard Module™ Specification is symmetrically and defines the following dimensions:

Contact Diameter: 0.8 mm
Contact Grid: 1.25 mm
Contact-to-Contact: 0.45 mm
Contact-to-Edge: 0.85 mm

![  Dimension   Value         ---------   ---------     Width       0.85 mm       Height      1.25 mm       Width       0.45 mm       Height      0.8 mm     ](.osm-specification-v1-0/5c7d2e8b99da0509d5730016fa777d9cfdbec715aa67c4bacd319476623876c0.jpg)

Figure 7: Footprint Grid Dimensions, Size-S upper left corner (view from top, through the module)

# 2.1.7 Contacts Characteristics

All Open Standard Modules™ use a symmetric LGA package for connecting the module PCB to the baseboard PCB. The manufacturer may decide and specify the use of one the following, recommended contact technologies:

 Fused Tin Grid Array (FTGA):

see Figure 8: Fused Tin Grid Array bottom view below

ENIG LGA:

see Figure 9: ENIG LGA package (bottom side) below

1 BGA:

see Figure 10: BGA package (bottom side) below

![Close-up of metallic oval-shaped indentations arranged in a regular pattern on a green metal surface (no text or symbols)](.osm-specification-v1-0/77554cb469d86b7d4c32af5bdb453a0eabf40783952fb46fcb11351d89c48293.jpg)

Figure 8: Fused Tin Grid Array bottom view

![Close-up of a green printed circuit board with evenly spaced circular holes, placed on a textured black surface (no text or symbols visible)](.osm-specification-v1-0/03350d01aad0521ea8c9048421013e72c8cbf415b10a1781dc9a90915774ba61.jpg)

Figure 9: ENIG LGA package (bottom side)
![Close-up of metallic spherical particles on a green surface (no text or symbols visible)](.osm-specification-v1-0/ebff9fb3e868b653f434f09a7b60367d1fe712594db6b86634f268e3dbb4d632.jpg)

Figure 10: BGA package (bottom side)

# 2.2 Module Height Specification

The Open Standard Module™ Specification allows different heights to adopt the module to different technical requirements:

Standard Height F – “Flat:” The Module PCB height is NOT extended via a “PCB Spacer” and has to be soldered directly on the Open Standard Module™ Carrier Board
Extended Height E – “Extended”: The Module PCB height is extended via a “PCB Spacer”. The “PCB Spacer” extends the total height of the Open Standard Module™ and is pre-soldered on the bottom side of the Open Standard Module™.

# 2.2.1 Standard Height F

Standard Height Open Standard Modules™ will be directly soldered on the PCB base board.

![Electronic Component on PBC top side Module PCB Base Board PCB](.osm-specification-v1-0/b5e8c9b2aaa9778eb34d5094f8f6485b953c0516fbf9ba77cba50a0385a85923.jpg)

Figure 11: Sectional view on Standard Height F (“Flat” module)

# 2.2.2 Extended Height E

Extended Height Open Standard Modules™ have an increased module height from additional “Spacer PCB Layers” between module and base board PCB. The “Spacer PCB Layers” need to be pressed or grouted directly on the bottom of the module PCB - most likely before the electronic components have been populated or assembled. The “Spacer PCB Layer” might help to facilitate the placement of components on the bottom of the Open Standard Module™

![Electronic Component on PBC top side Module PCB Spacer PCB Layer Electronic Component on PBC bottom side Base Board PCB](.osm-specification-v1-0/33c240e7176ec019ae32271b556d4fa17d8350aa796e172e9797a4945276f762.jpg)

Figure 12: Sectional view on Standard Height E ("Extended" module)

# 2.2.2.1 Schematic Illustration

The following illustration shows the structure and assembly of an exemplary Open Standard Module™ with Spacer PCB and Size “Small” and Height “Extended”.

![3D rendering of a green printed circuit board with two black rectangular components (no text or symbols visible)](.osm-specification-v1-0/d3ca4ec483baab8aa31ae4523b4fe937792491d3e3556ecca8ba629c24a55635.jpg)

![3D rendering of a green perforated plate with a central grid structure (no text or symbols)](.osm-specification-v1-0/4220b84308bb38017c1e881a2f4a8dc0943c7607b4bb6e7dfc584e28f4de10be.jpg)

![3D illustration of a green integrated circuit board with two black components and a grid pattern (no text or symbols)](.osm-specification-v1-0/f42d2d11cb6cd2aba478ce12ff7ceb0524f4e1cd38b35b142e742088368b6030.jpg)

![3D rendering of a green circuit board with multiple holes and a central component (no text or symbols visible)](.osm-specification-v1-0/e257ae7dfcc0343a469ad71334cef8464b5133b895db7727f007b22cf0ea4d73.jpg)

Figure 13: Schematic illustration of the Spacer PCB for Extended Height E (Size-S)

# 2.2.2.2 Possible Cut-out and Placement Areas (bottom side)

All modules adhering to the Open Standard Module™ Specification are meant to be soldering modules. Therefore, the definition of placement areas on bottom side of the module is necessary to allow placement of electronic components on the opposite of some main components like CPU, RAM, etc. Predefined placement areas will need to be taken into account for baseboard designs for recesses or cut-out areas. Otherwise, the module PCB itself could be increased with a Spacer PCB layer considering the placement areas on module bottom side.

Optional Placement Area #1: 10.25 mm width x 16.5 mm height
Optional Placement Area #2: 10.25 mm width x 16.5 mm height
Optional Placement Area #3: 31.5 mm width x 7.75 mm height

Additionally, to the placement area, also the area for the cut-out either on the spacer PCB or the carrier board needs to be defined.

![13.00 6.75 R1 30.00 16.50 10.25 30.00](.osm-specification-v1-0/2523ab0d12f5d6301bee6579d31dd5d1ac9ae9bfb9a9cbcebf65ea9ba94bb560.jpg)

![12.50 6.25 R1 30.00 17.50 11.25 30.00](.osm-specification-v1-0/ad2abc87b5249a76791d3c120c5831e2d805850a32cfe2b6590ce4fea6b6cb6b.jpg)

Figure 14: Placement Area (left) and Cut-Out Area (right) - Size S (view from bottom)

![28.00 6.75 R1 R1 6.75 30.00 16.50 16.50 10.25 10.25 45.00](.osm-specification-v1-0/4083c684817857ce5332d7be64314ca31f2de2d6c213aceb1a6894dd5c658561.jpg)

![  Dimension   Value     ---------   -----     Width       27.50     Height      6.25      Top Margin   6.25      Bottom Margin   17.50     Total Width   30.00     Top Thickness   11.25     Bottom Thickness   45.00     Top Thickness   R7       Bottom Thickness   R1       Total Thickness   17.50  ](.osm-specification-v1-0/cd21b4b40b6a6ba7825134ddc5408a2f0ea2e4b9ba0f6cf4a0258a092229db70.jpg)

Figure 15: Placement Area (left) and Cut-Out Area (right) - Size M (view from bottom)

![  Dimension   Value       ---------   -------     Total Length   45.00     Total Height   31.50     Total Width   6.75     Total Height (Top)   10.25     Total Height (Bottom)   6.75     Total Height (Bottom)   16.50     Total Height (Top)   28.00     Total Height (Top)   10.25     Total Height (Top)   6.75     Total Height (Top)   16.50     Total Height (Top)   30.50     Total Height (Top)   6.75     Total Height (Top)   10.25     Total Height (Top)   16.50     Total Height (Top)   31.50     Total Height (Top)   45.00     R1 (Top)     6.75        R1 (Top)     10.25       R1 (Top)     16.50       R1 (Top)     28.00       R1 (Top)     31.50       R1 (Top)     45.00       R1 (Top)     6.75        R1 (Top)     10.25       R1 (Top)     16.50       R1 (Top)     28.00       R1 (Top)     31.50       R1 (Top)     45.00       R1'         6.75        R1'         10.25       R1'         16.50       R1'         28.00       R1'         31.50       R1'         45.00       R1'         6.75        R1'         10.25       R1'         16.50       R1'         28.00       R1'         31.50       R1'         45.00       R1'         5.75        R1'         9.25        R1'         13.75       R1'         18.25       R1'         22.75       R1'         27.25       R1'         32.75       R1'         37.25       R1'         42.75       R1'         47.25       R1'         52.75       R1'         57.25       R1'         62.75       R1'         67.25       R1'         72.75       R1'         77.25       R1'         82.75       R1'         87.25       R1'         92.75       R1'         97.25       R1'         102.75      R1'         107.25      R1'         112.75      R1'         117.25      R1'         122.75      R1'         127.25      R1'         132.75      R1'         137.25      R1'         142.75      R1'         147.25      R1'         152.75      R1'         157.25      R1'         162.75      R1'         167.25      R1'         172.75      R1'         177.25      R1'         182.75      R1'         187.25      R1'         192.75      R1'         197.25      R1'         202.75      R1'         207.25      R1'         212.75      R1'         217.25      R1'         222.75      R1'         227.25      R1'         232.75      R1'         237.25      R1'         242.75      R1'         247.25      R1'         252.75      R1'         257.25      R1'         262.75      R1'         267.25      R1'         272.75      R1'         277.25      R1'         282.75      R1'         287.25      R1'         292.75      R1'         297.25      R1'         302.75      R1'         307.25      R1'         312.75      R1'         317.25      R1'         322.75      R1'         327.25      R1'         332.75      R1'         337.25      R1'         342.75      R1'         347.25      R1'         352.75      R1'         357.25      R1'         362.75      R1'         367.25      R1'         372.75      R1'         377.25      R1'         382.75      R1'         387.25      R1'         392.75      R1'         397.25      R1'         402.75      R1'         407.25      R1'         412.75      R1'         417.25      R1'         422.75      R1'         427.25      R1'         432.75      R1'         437.25      R1'         442.75      R1'         447.25,  R₁       ](.osm-specification-v1-0/6771527eabbcb48a5adf1fc99c82506f56e36887b29ec39d77fa54eb762ea4e0.jpg)

![  Dimension   Value     ---------   -----     Total Length   45.00     Height   30.00     Top Width   6.25     Bottom Width   8.75     Top Center   11.25     Bottom Center   32.50     Top Center (Right)   11.25     Bottom Center (Right)   6.25     Top Center (Left)   6.25     Bottom Center (Left)   32.50     Top Center (Center)   17.50     Bottom Center (Center)   6.25     Top Center (Center)   17.50     Bottom Center (Center)   6.25     Top Center (Center)   27.50   The chart displays a schematic layout with dimension labels for each component.](.osm-specification-v1-0/8a8a9aadbea1e2b3b77104b05ed36434d76566723a566c7fa22cffe18876cb81.jpg)

Figure 16: Placement Area (left) and Cut-Out Area (right) - Size L (view from bottom)

# 2.2.3 RF Antenna Connector Area

All modules adhering to the Open Standard Module™ Specification may provide one specific areas for potential RF antenna connectors. This area might be used for other electrical components as well, no matter if RF antenna connectors are provided or not.

![  Dimension   Value     ---------   -----     Width       4.5       Height      15     ](.osm-specification-v1-0/e1d580f8c9b26af92523ced8c03a143cef1b4cc4fb76751d5d2b7c1febf260bc.jpg)

Figure 17: RF Antenna Connector Area (all sizes) (view from top, through the module)

# 2.2.4 Standard Metal Shielding

All modules adhering to the Open Standard Module™ Specification may be able to carry a standardized RF Metal Shielding. This shielding helps to improve the EMC characteristics and reduce EMC emissions.

![Two views of a metallic electronic component with internal cutouts, placed on a textured surface (no text or symbols visible)](.osm-specification-v1-0/99856585defb76c8c12bc739b20892bb35545c463a2996888a1039d24e4840c4.jpg)

Figure 18: PCB RF Metal shielding (example)

# 2.2.5 Breakout Area and Tolerances

All modules adhering to the Open Standard Module™ Specification may have predefined panel breakout areas. Within these breakout areas the outline and texture of the module PCB might vary.

The definition of breakout areas might facilitate the production of the modules as well as testing equipment and shall reduce potential mechanical intolerances and conflicts on the baseboard.

Therefore, the red areas (below) border the maximum tolerances to be considered during production and assembly. The usage of those breakout areas is not a mandatory requirement.

![Two identical rectangular panels with circular patterns and red corner markers, no text or symbols present.](.osm-specification-v1-0/faeb4cb932072e43349fbbba9e88223132c942ecff83733f58178a3201b1a390.jpg)

![Pure geometric diagram with grid pattern and red corner markers (no text or symbols)](.osm-specification-v1-0/9a6373251f04eefcfff0b226025ac656549a54c677bf6c57b742691a3d2b99f7.jpg)

![Pure geometric diagram of a square grid with red corner markers and gray dots, no text or symbols present.](.osm-specification-v1-0/559372810f998f52422d42b56e6fa21924699307c8052faff20b9029a3117433.jpg)

Figure 19: Breakout Areas (all sizes) (view from top, through the module)

![2.0 mm 3.0 mm 1.0 mm 2.0 mm](.osm-specification-v1-0/48fcf9c13c8ff68b631695bdb77faff2e39f7483dde4d97d76320fde4b3e7a98.jpg)

Figure 20: Tolerances Breakout Areas (all sizes)

# 2.3 Electrical Interfaces

# 2.3.1 Contact Grid

Modules adhering to the Open Standard Module™ Specification shall use the following contact grid and the regarding designation:

![  Row   Column   Value    --- --- ---    1   A   2     1   B   4     1   C   6     1   D   8     1   E   10     1   F   12     1   G   14     1   H   16     1   I   18     1   J   20     1   K   22     1   L   24     1   M   26     1   N   28     1   O   30     1   P   32     1   R   34     1   T   35     1   U   33     1   V   31     1   W   29     1   Y   27     1   AA   25     1   AB   23     1   AC   21     1   AD   19     1   AE   17     1   AF   15     1   AG   13     1   AH   11     1   AJ   9     1   AK   7     1   AL   5     1   AM   3     1   AN   1     1   AP   -2     1   AR   -4   The chart displays a grid of circular cells (O) that are positioned within a rectangular grid. The top row contains the absolute numbers (e.g., '2' for position '2') and the bottom row contains the corresponding row numbers (e.g., '35') above each row. There is no additional data series or trends visible in the image.](.osm-specification-v1-0/35a16e0fe4c743d56af1fa855ac3b945933e60c117d6d408367661b051b5591c.jpg)

Figure 21: Contact Grid (all sizes) (view from top, through the module)

# 2.3.2 Contact Overview

![The image displays a grid map with row labels (A through AR) on the left and right sides, and column labels (1 through 35) on the top and bottom. The grid contains colored blocks with text indicating signal names or functions.  **Top Section (Rows A-C):** *   **Row A:** 4(GND), 8(GND), 10(USB), 11(GND), 14-23(COM ARPA), 25(GND), 26(USB), 27(GND), 31(GND) *   **Row B:** 3(GND), 6(GND), 9(GND), 14(VEN DEF), 17(TEST), 23(VEN DEF), 25(GND), 26(TEST), 27(GND), 31(GND) *   **Row C:** 4(GND), 5(ETH), 6(GND), 7(TEST), 8(VEN DEF), 9(GND), 11(USB), 12(GND), 14(UART), 15(VEN DEF), 17(TEST), 20(SDIO), 22(CONSOLE), 25(GND), 26(SPI), 27(GND), 30(eDP)  **Middle Section (Rows D-N):** *   **Row D:** 1(GND), 2(ETH), 3(GND), 4(GND), 15(GND), 16(ETH), 18(GND), 20(SDIO), 31(GND) *   **Row E:** 2(GND), 15(GND), 17(GPIO), 18(PWM), 19(GPIO), 20(SDIO), 31(GND) *   **Row F:** 15(GND), 19(GND), 31(GND) *   **Row G:** 1(GND), 2(GND), 15(ETH), 18(GND), 20(SDIO), 31(GND) *   **Row H:** 1(GND), 2(GND), 15(GND), 18(GND), 31(GND) *   **Row J:** 1(ETH), 2(RGB/TTL), 16(TEST), 17(ADC), 18(TEST), 19(GND), 31(GND) *   **Row K:** 15(VEN DEF), 16(JTAG), 17(GND), 18(JTAG), 19(GND), 31(GND) *   **Row L:** 1(GND), 2(GND), 18(SDIO), 31(GND) *   **Row M:** 1(GND), 18(RSVD), 31(GND) *   **Row N:** 2(RSVD), 17(SPI), 18(GND), 20(PWR), 31(GND)  **Lower Middle Section (Rows P-AD):** *   **Row P:** 1(GND), 2(GND), 18(I2S), 31(GND) *   **Row R:** 1(GND), 2(RGB/TTL), 14(RSVD), 16(TEST), 17(GND), 18(PWR), 19(TEST), 20(SPI), 31(GND) *   **Row T:** 1(PCle), 2(GND), 14(GND), 15(I2C), 16(GND), 17(VBAT), 18(GND), 19(I2C), 20(GND), 31(GND) *   **Row U:** 1(GND), 2(GND), 31(PCle) *   **Row V:** 1(GND), 2(PCle), 3(GND), 14(USB), 16(CAN), 17(DEBUG), 18(CAN), 19(USB), 31(ETH) *   **Row W:** 1(GND), 2(TEST), 3(RGB/TTL), 4(PWR), 14(GND), 15(I2C), 16(GND), 17(VBAT), 18(GND), 19(I2C), 20(GND) *   **Row Y:** 14(GND), 15(I2C), 16(GND), 17(VBAT), 18(GND), 19(I2C), 20(GND), 31(GPIO) *   **Row AA:** 1(GND), 2(RSVD), 3(DSI), 4(GND), 5(GND), 6(PWR), 7(GND), 14(GND), 15(I2C), 16(GND), 17(VBAT), 18(GND), 19(I2C), 20(GND), 31(GND), 32(TEST) *   **Row AB:** 1(PCle), 2(GND), 3(DSI), 4(GND), 5(DSI), 6(GND), 14(USB), 16(CAN), 17(DEBUG), 18(CAN), 19(USB), 31(GND), 32(UFS) *   **Row AC:** 2(GND), 3(GND), 14(USB), 16(CAN), 17(DEBUG), 18(CAN), 19(USB), 31(UFS), 32(GND), 33(UFS), 34(GND), 35(ETH)  **Bottom Section (Rows AE-AR):** *   **Row AE:** 1(GND), 3(PWR), 31(PCle), 32(GND) *   **Row AF:** 2(GND), 31(PCle), 32(GND) *   **Row AG:** 1(GND), 31(PCle), 32(GND) *   **Row AH:** 2(GND), 31(GPIO) *   **Row AJ:** 1(ETH), 31(PCle) *   **Row AK:** 2(GND), 31(PCle) *   **Row AL:** 1(GND), 31(VEN DEF) *   **Row AM:** 1(RSVD), 2(GND), 11(RESERVED), 31(PCle) *   **Row AN:** 1(RSVD), 2(GND), 3-10(GND), 11(RESERVED), 14(LVDS), 15(GND), 16(LVDS), 17(GND), 18(LVDS), 19(GND), 20(LVDS), 21(GND), 22(LVDS), 23(GND), 24(GND), 25(LVDS), 26(GND), 27(LVDS), 28(GND), 29(LVDS), 30(GND), 31(PCle), 32(GND), 33(PCle), 34(GND), 35(PCle) *   **Row AP:** 1(GND), 2(GND), 4(GND), 6(GND), 8(GND), 10(GND), 11(RESERVED), 14(GND), 15(GND), 16(GND), 17(GND), 18(GND), 19(GND), 20(GND), 21(GND), 22(GND), 23(GND), 24(GND), 25(PCle), 26(GND), 27(PCle), 28(GND), 29(PCle), 30(GND), 31(PCle), 32(GND), 33(PCle), 34(GND), 35(PCle) *   **Row AR:** 1-10(GND), 11(RESERVED), 14(GND), 15(LVDS), 16(GND), 17(PCle), 18(GND), 19(PCle), 20(GND), 21(PCle), 22(GND), 23(PCle), 24(GND), 25(PCle), 26(GND), 27(PCle), 28(GND), 29(PCle), 30(GND), 31(PCle), 32(GND), 33(PCle), 34(GND), 35(PCle)](.osm-specification-v1-0/2cbab57d87aba5a32917ece2b2cf5c987ad6dc18df4736c614f476d1e0bef9d9.jpg)
Figure 22: Contact Overview (all sizes)

# 2.3.3 Size-0 – Basic Functions

# 2.3.3.1 Size-0 – Function Table

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of Interfaces</td><td>No. of Contacts</td><td>Mandatory Interface</td><td>Color Code</td></tr><tr><td>Ethernet / LAN</td><td>(Q)(S)(R)(G)MII, 100/1000 Mbit</td><td>0 ... 1</td><td>18</td><td>No</td><td></td></tr><tr><td>USB</td><td>USB 2.0</td><td>0 ... 2</td><td>12</td><td>No</td><td></td></tr><tr><td>UART Console</td><td>Rx, Tx only</td><td>1 ... 2</td><td>2</td><td>Yes</td><td></td></tr><tr><td>UART</td><td>Rx, Tx, 2xRTS, 2xCTS</td><td>0 ... 4</td><td>12</td><td>No</td><td></td></tr><tr><td>Power Supply</td><td>5 / 3.3 V-DC, Battery, System Reset, Control signals</td><td>1</td><td>8</td><td>Yes</td><td></td></tr><tr><td>Ground</td><td>Main Power GND</td><td>1</td><td>22</td><td>Yes</td><td></td></tr><tr><td>JTAG</td><td></td><td>1</td><td>6</td><td>Yes</td><td></td></tr><tr><td>GPIO</td><td>General Purpose Input Output</td><td>0 ... 16</td><td>16</td><td>No</td><td></td></tr><tr><td>Testing</td><td>VCC_Test_0 ... 3, SWIM, etc.</td><td>0 ... 6</td><td>6</td><td>No</td><td></td></tr><tr><td>Vendor Defined</td><td>Defined by module manufacturer</td><td>0 ... 3</td><td>3</td><td>No</td><td></td></tr><tr><td>Reserved</td><td>TBD / for future use</td><td>0 ... 8</td><td>8</td><td>No</td><td></td></tr><tr><td>Communication Area</td><td>Either in Wireless Mode or in Fieldbus Mode</td><td>0 ... 1</td><td>18</td><td>No</td><td></td></tr><tr><td>SPI</td><td>Host or Slave, 1 x Quad SPI optional</td><td>0 ... 2</td><td>10</td><td>No</td><td></td></tr><tr><td>I2C</td><td></td><td>0 ... 2</td><td>4</td><td>No</td><td></td></tr><tr><td>I2S / PDM</td><td>one channel</td><td>0 ... 2</td><td>7</td><td>No</td><td></td></tr><tr><td>SDIO</td><td>4 Lanes + 8 Lanes</td><td>0 ... 2</td><td>24</td><td>No</td><td></td></tr><tr><td>CAN</td><td></td><td>0 ... 2</td><td>4</td><td>No</td><td></td></tr><tr><td>Analog Input</td><td></td><td>0 ... 2</td><td>2</td><td>No</td><td></td></tr><tr><td>PWM</td><td>PWM_0 ...5</td><td>0 ... 6</td><td>6</td><td>No</td><td></td></tr><tr><td colspan="3">Amount of Contacts</td><td colspan="2">188</td><td></td></tr></table>

Table 4: Size-0 – Function Table

# 2.3.3.2 Size-0 – Detailed Contact Overview

![The image displays a pinout table for a connector, organized by rows labeled A through AC and columns labeled 13 through 23.  **Row A:** 14: UART_A_RX, 15: ANT_GND, 16: ANT_MAIN, 17: ANT_GND, 18: ANT_GND, 19: ANT_GND, 20: ANT_AUX, 21: ANT_GND, 22: UART_C_RX **Row B:** 13: UART_A_TX, 15: ANT_GND, 16: ANT_GND, 17: ANT_GND, 18: ANT_GND, 19: ANT_GND, 20: ANT_GND, 21: ANT_GND, 22: Vendor Defined, 23: UART_C_TX **Row C:** 13: UART_A RTS, 14: UART_A CTS, 15: ANT_ MAIN TEST, 16: Vendor Defined, 17: ANT_B MAIN TEST, 18: TEST GENERIC, 19: ANT_B AUX TEST, 20: SDIO_A VSEL, 21: ANT AUX TEST, 22: UART_D RX, 23: UART_D TX **Row D:** 13: UART_B_TX, 14: UART_B_RX, 15: UART_B RTS, 16: UART_B CTS, 17: GPIO_A 0, 18: GND, 19: GPIO_B 0, 20: SDIO_A WP, 21: SDIO_A PWR_EN, 22: UART_CON_RX, 23: UART_CON_TX **Row E:** 14: GND, 15: ETH_A (R)(G)MII CRS, 16: GPIO_A 1, 17: PWM 0, 18: GPIO_B 1, 19: SDIO_A CMD, 20: GND **Row F:** 14: ETH_A (R)(G)MII COL, 15: GND, 16: GPIO_A 2, 17: PWM 1, 18: GPIO_B 2, 19: GND, 20: SDIO_A CLK **Row G:** 14: ETH_A (S)(R)(G)MII_TXD1, 15: ETH_A (R)(G)MII_TXD3, 16: GPIO_A 3, 17: PWM 2, 18: GPIO_B 3, 19: SDIO_A D0, 20: SDIO_A D1 **Row H:** 14: ETH_A (S)(R)(G)MII_TXD0, 15: ETH_A (R)(G)MII_TXD2, 16: GPIO_A 4, 17: PWM 3, 18: GPIO_B 4, 19: SDIO_A D2, 20: SDIO_A D3 **Row J:** 14: ETH_A (R)(G)MII_TX_CLK, 15: GND, 16: GPIO_A 5, 17: PWM 4, 18: GPIO_B 5, 19: GND, 20: SDIO_A CD# **Row K:** 14: ETH_A (S)(R)(G)MII_RXD0, 15: ETH_A (R)(G)MII_TX_EN_ER, 16: GPIO_A 6, 17: PWM 5, 18: GPIO_B 6, 19: SDIO_B CLK, 20: SDIO_B CMD **Row L:** 14: ETH_A (S)(R)(G)MII_RXD1, 15: ETH_A (R)(G)MII_RX_ER, 16: GPIO_A 7, 17: GND, 18: GPIO_B 7, 19: SDIO_B D0, 20: SDIO_B D1 **Row M:** 14: ETH_A (R)(G)MII_RX_DV_ER, 15: GND, 16: VCC_1_TEST, 17: ADC_1, 18: VCC_2_TEST, 19: GND, 20: SDIO_B D2 **Row N:** 14: ETH_A (R)(G)MII_RXD2, 15: ETH_A SDP, 16: JTAG_TCK(SWCLK), 17: ADC_0, 18: JTAG_TMS(SWIO), 19: SDIO_B D3, 20: SDIO_B D4 **Row P:** 14: ETH_A (R)(G)MII_RXD3, 15: Vendor Defined, 16: JTAG_TDI, 17: GND, 18: JTAG_RTCK, 19: SDIO_B D5, 20: SDIO_B D6 **Row R:** 14: ETH_A (R)(G)MII_RX_CLK, 15: GND, 16: JTAG_TDO(SWO), 17: RESERVED, 18: JTAG_nTRST, 19: GND, 20: SDIO_B D7 **Row T:** 14: ETH_MDIO, 15: ETH_MDC, 16: RESERVED, 17: RESERVED, 18: RESERVED, 19: SDIO_B VSEL, 20: SDIO_B CD# **Row U:** 14: SPI_A_SDI(IO0), 15: SPI_A_SCK, 16: SYS_RST#, 17: RESERVED, 18: RESERVED, 19: SDIO_B WP, 20: SDIO_B PWR_EN **Row V:** 14: SPI_A_SDO(IO1), 15: GND, 16: Carrier_PWR_EN, 17: I2S_MCLK, 18: I2S_B_DATA_IN, 19: GND, 20: I2S_A_DATA_IN **Row W:** 14: SPI_A_HOLD(IO3), 15: SPI_A_WP(IO2), 16: RTC_PWR, 17: I2S_LRCLK, 18: I2S_B_DATA_OUT, 19: I2S_BITCLK, 20: I2S_A_DATA_OUT **Row Y:** 13: RESERVED, 14: RESERVED, 15: SPI_A_CS#, 16: VCC_3_TEST, 17: VCC_IN_5V, 18: GND, 19: VCC_IN_3V3, 20: VCC_A_TEST, 21: SPI_B_SCK, 22: SPI_B_SDI, 23: SPI_B_SDO **Row AA:** 13: RESERVED, 14: GND, 15: I2C_A_SCL, 16: I2C_A_SDA, 17: GND, 18: VBAT, 19: GND, 20: I2C_B_SCL, 21: I2C_B_SDA, 22: GND, 23: SPI_B_CS# **Row AB:** 13: USB_A_D_N, 14: USB_A_ID, 15: GND, 16: USB_A_VBUS, 17: CAN_A_RX, 18: VBAT, 19: CAN_B_RX, 20: USB_B_VBUS, 21: GND, 22: USB_B_ID, 23: USB_B_D_N **Row AC:** 13: USB_A_D_P, 14: USB_A_OC#, 15: USB_A_EN, 16: CAN_A_TX, 17: DEBUG_EN, 18: CAN_B_TX, 19: USB_B_EN, 20: USB_B_OC#, 21: USB_B_D_P](.osm-specification-v1-0/2fe1bf9efe5d3c232617975b65a59a5fb2291750b5bcccd240f5448cdfbb43a4.jpg)
Figure 23: Size-0 - detailed contact overview

# 2.3.4 Size-S – ADDITIONAL Functions

# 2.3.4.1 Size-S – Function Table

Size-S’s functionality on column 13 to 23 is identical to Size-0. There is only one change in the necessity of USB interfaces according to following table:

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of Interfaces</td><td>No. of Contacts</td><td>Mandatory Interface</td></tr><tr><td>USB</td><td>USB 2.0</td><td>1 ... 2</td><td>12</td><td>1x Yes</td></tr><tr><td>I2C</td><td>I2C</td><td>1 ... 2</td><td>4</td><td>1x Yes</td></tr></table>

Table 5: Size-S Changes to Size-0

The following table describes the additional functions on column 1 to 11.

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of additional Interfaces</td><td>No. of additional Contacts</td><td>Mandatory Interface</td><td>Color code</td></tr><tr><td>Power Supply</td><td>5 V-DC, Power Button</td><td>1</td><td>5</td><td>Yes</td><td></td></tr><tr><td>Ground</td><td>Main Power GND</td><td>1</td><td>36</td><td>Yes</td><td></td></tr><tr><td>GPIO</td><td>General Purpose Input Output</td><td>0 ... 8</td><td>8</td><td>No</td><td></td></tr><tr><td>Reserved</td><td>TBD / for future use</td><td>0 ... 2</td><td>2</td><td>No</td><td></td></tr><tr><td>Vendor Defined</td><td>Defined by module manufacturer</td><td>0 ... 4</td><td>4</td><td>No</td><td></td></tr><tr><td>Ethernet / LAN</td><td>(Q)(S)(R)(G)MII, 100/1000 Mbit</td><td>0 ... 1</td><td>16</td><td>No</td><td></td></tr><tr><td>USB</td><td>USB 2.0 with 3.0 option, with Dual Role option</td><td>0 ... 1</td><td>10</td><td>No</td><td></td></tr><tr><td>MIPI Interfaces</td><td>DSI, CSI</td><td>0 ... 3</td><td>24</td><td>No</td><td></td></tr><tr><td>RGB</td><td>Parallel Display</td><td>0 ... 1</td><td>25</td><td>No</td><td></td></tr><tr><td>Testing</td><td>VCC_Test_5 ... 6</td><td>0 ... 2</td><td>2</td><td>No</td><td></td></tr><tr><td>PCIe x1</td><td>With WAKE and SMBus signal</td><td>0 ... 1</td><td>12</td><td>No</td><td></td></tr><tr><td colspan="3">Amount of Contacts</td><td colspan="2">144</td><td></td></tr></table>

Table 6: Size-S Additional Functionality / Interfaces

# 2.3.4.2 Size-S – Detailed Contact Overview

![](.osm-specification-v1-0/3a0cb5a3ce8e0412049e6d66e698da236f1f22507b1f545910e087b6f56bd387.jpg)
Figure 24: Size-S detailed Contact Overview

# 2.3.5 Size-M – ADDITIONAL Functions

# 2.3.5.1 Size-M – Function Table

Size-M’s functionality on column 13 to 23 is identical to Size-0. There is only one change in the necessity of USB interfaces according to following table:

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of Interfaces</td><td>No. of Contacts</td><td>Mandatory Interface</td></tr><tr><td>USB</td><td>USB 2.0</td><td>1 ... 2</td><td>12</td><td>1x Yes</td></tr><tr><td>I2C</td><td>I2C</td><td>1 ... 2</td><td>4</td><td>1x Yes</td></tr></table>

Table 7: Size-M Changes to Size-0

The following table describes the additional functions on column 24 to 35.

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of additional Interfaces</td><td>No. of additional Contacts</td><td>Mandatory Interface</td><td>Color code</td></tr><tr><td>Power Supply</td><td>5 V-DC</td><td>1</td><td>4</td><td>Yes</td><td></td></tr><tr><td>Ground</td><td>Main Power GND</td><td>1</td><td>34</td><td>Yes</td><td></td></tr><tr><td>GPIO</td><td>General Purpose Input Output</td><td>0 ... 8</td><td>8</td><td>No</td><td></td></tr><tr><td>Reserved</td><td>TBD / for future use</td><td>0 ... 16</td><td>16</td><td>No</td><td></td></tr><tr><td>Vendor Defined</td><td>Defined by module manufacturer</td><td>0 ... 6</td><td>6</td><td>No</td><td></td></tr><tr><td>Ethernet / LAN</td><td>(Q)(S)(R)(G)MII, 100/1000 Mbit</td><td>0 ... 1</td><td>16</td><td>No</td><td></td></tr><tr><td>USB</td><td>USB 2.0 with 3.0 option</td><td>0 ... 1</td><td>10</td><td>No</td><td></td></tr><tr><td>Display Interface</td><td>eDP_A, eDP_B</td><td>0 ... 2</td><td>28</td><td>No</td><td></td></tr><tr><td>PCIe x1</td><td></td><td>0 ... 1</td><td>6</td><td>No</td><td></td></tr><tr><td>Testing</td><td>VCC_Test_5 ... 6</td><td>0 ... 2</td><td>2</td><td>No</td><td></td></tr><tr><td>UFS</td><td></td><td>0 ... 1</td><td>10</td><td>No</td><td></td></tr><tr><td>SPI</td><td>Host or Slave</td><td>0 ... 1</td><td>4</td><td>No</td><td></td></tr><tr><td colspan="3">Amount of Contacts</td><td colspan="2">144</td><td></td></tr></table>

Table 8: Size-M Additional Functionality / Interfaces

# 2.3.5.2 Size-M – Detailed Contact Overview

![The image displays a pinout diagram for a connector, with rows labeled A through AC and columns labeled 25 through 35. The content of each cell is as follows:  **Row A:** 26: GND, 27: USB_D_SSTX_P, 28: USB_D_SSTX_N, 29: GND, 30: eDP_A_LANE0_P, 31: eDP_A_LANE0_N, 32: GND, 33: eDP_A_LANE2_P, 34: eDP_A_LANE2_N **Row B:** 25: USB_D_SSRX_P, 26: USB_D_SSRX_N, 27: GND, 28: GND, 29: VCC_8_TEST, 30: GND, 31: eDP_A_LANE1_P, 32: eDP_A_LANE1_N, 33: GND, 34: eDP_A_LANE3_P, 35: eDP_A_LANE3_N **Row C:** 25: GND, 26: USB_D_EN, 27: USB_D_VBUS, 28: USB_D_OC#, 29: SPI_C_SDI, 30: SPI_C_CS#, 31: eDP_A_BL_PWM, 32: GND, 33: eDP_A_AUX_P, 34: eDP_A_AUX_N, 35: GND **Row D:** 25: USB_D_D_P, 26: USB_D_D_N, 27: USB_D_ID, 28: GND, 29: SPI_C_SCK, 30: SPI_C_SDO, 31: eDP_A_BL_EN, 32: eDP_A_AUX_SEL, 33: eDP_A_HPD, 34: GND, 35: eDP_B_LANE0_P **Row E:** 32: eDP_B_BL_EN, 33: eDP_B_BL_PWM, 34: eDP_B_LANE1_P, 35: eDP_B_LANE0_N **Row F:** 32: eDP_B_AUX_SEL, 33: GND, 34: eDP_B_LANE1_N, 35: GND **Row G:** 32: eDP_B_HPD, 33: eDP_B_AUX_P, 34: GND, 35: eDP_B_LANE2_P **Row H:** 32: GND, 33: eDP_B_AUX_N, 34: eDP_B_LANE3_P, 35: eDP_B_LANE2_N **Row J:** 32: RESERVED, 33: GND, 34: eDP_B_LANE3_N, 35: GND **Row K:** 32: RESERVED, 33: PCIe_B_PRSNT#, 34: GND, 35: PCIe_B_HS00_P **Row L:** 32: RESERVED, 33: PCIe_B_PERST#, 34: PCIe_B_HS10_P, 35: PCIe_B_HS00_N **Row M:** 32: RESERVED, 33: RESERVED, 34: PCIe_B_HS10_N, 35: GND **Row N:** 32: RESERVED, 33: RESERVED, 34: GND, 35: ETH_C_(R)(G)MII_TX_CLK **Row P:** 32: RESERVED, 33: RESERVED, 34: RESERVED, 35: ETH_C_(R)(G)MII_RXD3 **Row R:** 32: RESERVED, 33: RESERVED, 34: ETH_C_SDP, 35: ETH_C_(R)(G)MII_RXD2 **Row T:** 32: RESERVED, 33: RESERVED, 34: GND, 35: ETH_C_(R)(G)MII_RX_DV_ER **Row U:** 32: GPIO_D_0, 33: GPIO_D_1, 34: ETH_C_(R)MII_RX_ER, 35: ETH_C_(S)(R)(G)MII_RXD1 **Row V:** 32: GPIO_D_2, 33: GPIO_D_3, 34: ETH_C_(R)(G)MII_TX_EN, 35: ETH_C_(S)(R)(G)MII_RXD0 **Row W:** 32: GPIO_D_4, 33: GPIO_D_5, 34: GND, 35: ETH_C_(R)(G)MII_RX_CLK **Row Y:** 25: VCC_IN_5V, 26: VCC_IN_5V, 27: VCC_IN_5V, 28: VCC_IN_5V, 29: Vendor Defined, 30: Vendor Defined, 31: Vendor Defined, 32: GPIO_D_6, 33: GPIO_D_7, 34: ETH_C_(R)(G)MII_TXD2, 35: ETH_C_(S)(R)(G)MII_TXD0 **Row AA:** 25: GND, 26: GND, 27: GND, 28: GND, 29: Vendor Defined, 30: Vendor Defined, 31: Vendor Defined, 32: GND, 33: VCC_7_TEST, 34: ETH_C_(R)(G)MII_TXD3, 35: ETH_C_(S)(R)(G)MII_TXD1 **Row AB:** 25: RESERVED, 26: RESERVED, 27: UFS_RESET#, 28: GND, 29: UFS_TX1_P, 30: UFS_TX1_N, 31: GND, 32: UFS_RX1_P, 33: UFS_RX1_N, 34: GND, 35: ETH_C_(R)(G)MII_COL **Row AC:** 26: UFS_CLK, 27: GND, 28: UFS_TX0_P, 29: UFS_TX0_N, 30: GND, 31: UFS_RX0_P, 32: UFS_RX0_N, 33: GND, 34: ETH_C_(R)(G)MII_CRS](.osm-specification-v1-0/073786abcd7e37bf3015e2dd283267e339fc76edde1d6dd237304d98e1616a4d.jpg)
Figure 25: Size-M detailed Contact Overview

# 2.3.6 Size-L – ADDITIONAL Functions

# 2.3.6.1 Size-L – Function Table

Size-L’s functionality on column 13 to 23 is identical to Size-0. There is only one change in the necessity of USB interfaces according to following table:

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of Interfaces</td><td>No. of Contacts</td><td>Mandatory Interface</td></tr><tr><td>USB</td><td>USB 2.0</td><td>1 ... 2</td><td>12</td><td>1x Yes</td></tr><tr><td>I2C</td><td>I2C</td><td>1 ... 2</td><td>4</td><td>1x Yes</td></tr></table>

Table 9: Size-L Changes to Size-0

The following table describes the additional functions on line AE to AP

<table><tr><td>Functionality</td><td>Description</td><td>Quantity of additional Interfaces</td><td>No. of additional Contacts</td><td>Mandatory Interface</td><td>Color Code</td></tr><tr><td>Power Supply</td><td>5 V-DC</td><td>1</td><td>8</td><td>Yes</td><td></td></tr><tr><td>Ground</td><td>Main Power GND</td><td>1</td><td>40</td><td>Yes</td><td></td></tr><tr><td>GPIO</td><td>General Purpose Input Output</td><td>0 ... 8</td><td>8</td><td>No</td><td></td></tr><tr><td>Reserved</td><td>TBD / for future use</td><td>0 ... 37</td><td>31</td><td>No</td><td></td></tr><tr><td>Vendor Defined</td><td>Defined by module manufacturer</td><td>0 ... 6</td><td>6</td><td>No</td><td></td></tr><tr><td>Ethernet / LAN</td><td>(Q)(S)(R)(G)MII, 100/1000 Mbit</td><td>0 ... 2</td><td>32</td><td>No</td><td></td></tr><tr><td>Display Interface</td><td>LVDS</td><td>0 ... 1</td><td>25</td><td>No</td><td></td></tr><tr><td>PCIe x4</td><td>x1 option</td><td>0 ... 2</td><td>36</td><td>No</td><td></td></tr><tr><td colspan="3">Amount of Contacts</td><td colspan="2">186</td><td></td></tr></table>

Table 10: Size-L Additional Functionality / Interfaces

# 2.3.6.2 Size-L – Detailed Contact Overview

<table><tr><td></td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td><td>9</td><td>10</td><td>11</td><td>12</td></tr><tr><td>AE</td><td></td><td>GND</td><td>ETH_D_(R)(G)MII_CRS</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AF</td><td>ETH_D_(S)(R)(G)MII_TXD0</td><td>ETH_D_(R)(G)MII_TXD3</td><td>ETH_D_(R)(G)MII_COL</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AG</td><td>ETH_D_(S)(R)(G)MII_TXD1</td><td>ETH_D_(R)(G)MII_TXD2</td><td>GND</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AH</td><td>ETH_D_(R)(G)MII_TX_CLK</td><td>GND</td><td>VCC_IN_5V</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AJ</td><td>ETH_D_(S)(R)(G)MII_RXD0</td><td>ETH_D_(R)(G)MII_TX_EN(ER)</td><td>VCC_IN_5V</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AK</td><td>ETH_D_(S)(R)(G)MII_RXD1</td><td>ETH_D_(R)MII_RX_ER</td><td>GND</td><td>VCC_IN_5V</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AL</td><td>ETH_D_(R)(G)MII_RX_DV(ER)</td><td>GND</td><td>RESERVED</td><td>RESERVED</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>AM</td><td>ETH_D_(R)(G)MII_RXD2</td><td>ETH_B_SDP</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>RESERVED</td><td>LVDS_I2C_CLK</td><td>LVDS_I2C_DAT</td></tr><tr><td>AN</td><td>ETH_D_(R)(G)MII_RXD3</td><td>RESERVED</td><td>GND</td><td>ETH_E_(R)(G)MII_CRS</td><td>RESERVED</td><td>GND</td><td>RESERVED</td><td>RESERVED</td><td>GND</td><td>ETH_E_(R)(G)MII_RX_CLK</td><td>GND</td><td>LVDS_A_CLK_N</td></tr><tr><td>AP</td><td>ETH_D_(R)(G)MII_RX_CLK</td><td>GND</td><td>ETH_E_(R)(G)MII_TXD2</td><td>ETH_E_(R)(G)MII_TXD3</td><td>GND</td><td>ETH_E_(R)(G)MII_TX_EN(EN)</td><td>ETH_E_(R)MII_RX_ER</td><td>GND</td><td>ETH_E_SDP</td><td>RESERVED</td><td>LVDS_A_LANE3_N</td><td>LVDS_A_LANE3_P</td></tr><tr><td>AR</td><td></td><td>ETH_E_(R)(G)MII_COL</td><td>ETH_E_(S)(R)(G)MII_TXD0</td><td>ETH_E_(S)(R)(G)MII_TXD1</td><td>ETH_E_(R)(G)MII_TX_CLK</td><td>ETH_E_(S)(R)(G)MII_RXD0</td><td>ETH_E_(S)(R)(G)MII_RXD1</td><td>ETH_E_(R)(G)MII_RX_DV(ER)</td><td>ETH_E_(R)(G)MII_RXD2</td><td>ETH_E_(R)(G)MII_RXD3</td><td></td><td></td></tr></table>

![The image displays a pinout grid or connector layout with rows labeled AE through AR and columns numbered 13 through 35. The grid is divided into two main sections: a top section (columns 13-23) and a bottom section (columns 24-35). The cells are color-coded (purple/blue for ground/GPIO, cyan/light blue for signals, teal for reserved).  **Top Section (Columns 13-23)** *   **Row AM:** 13=GND, 14=LVDS_B_LANE3_N, 15=LVDS_B_LANE3_P, 16=GND, 17=LVDS_B_Lane2_N, 18=LVDS_B_Lane2_P, 19=GND, 20=LVDS_B_LANE0_N, 21=LVDS_B_LANE0_P, 22=GND, 23=RESERVED *   **Row AN:** 13=LVDS_A_CLK_P, 14=LVDS_VDD_EN, 15=GND, 16=LVDS_B_CLK_N, 17=LVDS_B_CLK_P, 18=GND, 19=LVDS_B_LANE1_N, 20=LVDS_B_LANE1_P, 21=GND, 22=LVDS_BL_PWM, 23=LVDS_BL_EN *   **Row AP:** 13=GND, 14=LVDS_A_LANE2_N, 15=LVDS_A_LANE2_P, 16=GND, 17=LVDS_A_LANE0_N, 18=LVDS_A_LANE0_P, 19=GND, 20=PCIe_D_HS00_N, 21=PCIe_D_HS00_P, 22=GND, 23=PCIe_D_HS01_N *   **Row AR:** 14=GND, 15=LVDS_A_LANE1_N, 16=LVDS_A_LANE1_P, 17=GND, 18=PCIe_D_HS10_N, 19=PCIe_D_HS10_P, 20=GND, 21=PCIe_D_HS11_N, 22=PCIe_D_HS11_P (Columns 13 and 23 are empty)  **Bottom Section (Columns 24-35)** *   **Row AE:** 32=PCIe_C_PRSNT#, 33=PCIe_C_PERST#, 34=GND (Columns 24-31 and 35 are empty) *   **Row AF:** 32=GPIO_E_0, 33=GPIO_E_1, 34=PCIe_C_HS03_P, 35=GND (Columns 24-31 are empty) *   **Row AG:** 32=GPIO_E_2, 33=GPIO_E_3, 34=PCIe_C_HS03_N, 35=PCIe_C_HS13_P (Columns 24-31 are empty) *   **Row AH:** 32=GPIO_E_4, 33=GPIO_E_5, 34=GND, 35=PCIe_C_HS13_N (Columns 24-31 are empty) *   **Row AJ:** 32=GPIO_E_6, 33=GPIO_E_7, 34=PCIe_C_HS02_P, 35=GND (Columns 24-31 are empty) *   **Row AK:** 32=Vendor Defined, 33=Vendor Defined, 34=PCIe_C_HS02_N, 35=PCIe_C_HS12_P (Columns 24-31 are empty) *   **Row AL:** 32=Vendor Defined, 33=Vendor Defined, 34=GND, 35=PCIe_C_HS12_N (Columns 24-31 are empty) *   **Row AM:** 24-31=RESERVED (x8), 32=Vendor Defined, 33=Vendor Defined, 34=PCIe_C_HS01_P, 35=GND *   **Row AN:** 24-31=RESERVED (x8), 32=PCIe_D_PRSNT#, 33=PCIe_D_PERST#, 34=GND, 35=PCIe_C_HS01_N, (Extra Cell) PCIe_C_HS11_P *   **Row AP:** 24=PCIe_D_HS01_P, 25=GND, 26=PCIe_D_HS12_N, 27=PCIe_D_HS12_P, 28=GND, 29=PCIe_D_HS13_N, 30=PCIe_D_HS13_P, 31=GND, 32=PCIe_C_HS10_N, 33=PCIe_C_HS10_P, 34=GND, 35=PCIe_C_HS11_N *   **Row AR:** 25=GND, 26=PCIe_D_HS02_N, 27=PCIe_D_HS02_P, 28=GND, 29=PCIe_D_HS03_N, 30=PCIe_D_HS03_P, 31=GND, 33=PCIe_C_HS00_N, 34=PCIe_C_HS00_P (Columns 24, 32, and 35 are empty)](.osm-specification-v1-0/9b9ff2af063d0aee4164775a215799668f6a100282b9279448121167c256bad9.jpg)
Figure 26: Size-L Detailed Contact Overview

# 2.4 Contact Tables

All data in the contacts tables refer to the associated module, i.e. any mentioned PU/PD should be placed on the module, not on the carrier.

# 2.4.1 Signal Descriptions

# 2.4.1.1 Signal Naming Convention

Active-low signals are indicated by a trailing ‘#’ sign: REQ# Differential pairs are indicated by trailing ‘\_P’ and ‘\_N‘ signs: TX\_P, TX\_N

# 2.4.1.2 I/O Types

The I/O Type defines Contact Type and Buffer Type according following Tables

<table><tr><td>Contact Type</td><td>Description</td><td>Comments</td></tr><tr><td>I</td><td>Input to the Module</td><td></td></tr><tr><td>O</td><td>Output from the Module</td><td></td></tr><tr><td>I/O</td><td>Bi-directional Input / Output signal</td><td></td></tr><tr><td>OD</td><td>Open Drain Output</td><td></td></tr><tr><td>I OD</td><td>Input to the module, where an OD output on the carrier is expected</td><td></td></tr></table>

Table 11: Contact Types

<table><tr><td>Buffer Type</td><td>Description</td><td>Comments</td></tr><tr><td>P</td><td>Power to the module or Power source from the module</td><td></td></tr><tr><td>Analog</td><td>Analog signal between defined voltage</td><td></td></tr><tr><td>CMOS</td><td>Logic input or output.</td><td>Please check the noise margins for your logic levels.</td></tr><tr><td>USB</td><td>USB compatible differential signal. Please refer to the USB Specification for details.</td><td></td></tr><tr><td>USB SS</td><td>USB SuperSpeed signal. Please refer to the USB 3.x specification for details.</td><td></td></tr><tr><td>MDI</td><td>Media Dependent Interface, differential signal.</td><td></td></tr><tr><td>LVDS D-PHY</td><td>MIPI-DSI/CSI differential signal. Please refer to the MIPI D-PHY specification</td><td></td></tr><tr><td>LVDS M-PHY</td><td>MIPI-DSI/CSI differential signal. Please refer to the MIPI M-PHY specification</td><td></td></tr><tr><td>LVDS PCIE</td><td>PCI Express compatible differential signal. Please refer to the PCI Express Specification for details.</td><td></td></tr><tr><td>LVDS UFS</td><td>UFS compatible differential signal. Please refer to the UFS specification by JEDEC.</td><td></td></tr><tr><td>LVDS DP</td><td>DisplayPort compatible differential signal. Please refer to the DisplayPort specification for details.</td><td></td></tr><tr><td>LVDS LCD</td><td>Low Voltage Differential signals for connecting an LCD. Please refer to the LDI/OLDI specification for details.</td><td></td></tr></table>

Table 12: Buffer Types

# 2.4.2 Size-0 Basic Functionality

# 2.4.2.1 Power Supply + Ground

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VCC_1_TEST</td><td>M17</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_2_TEST</td><td>M19</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_3_TEST</td><td>Y16</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_4_TEST</td><td>Y20</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_IN_5V</td><td>Y17</td><td>Module power input voltage of 5V – Primary voltage rail for size S, M and L modules</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_IN_3V3</td><td>Y19</td><td>Module power input voltage of 3.3V – Primary voltage rail for 0 size modules</td><td>P</td><td></td><td></td><td></td></tr><tr><td>V_BAT</td><td>AA18,AB18</td><td>Module power input battery voltage</td><td>P</td><td></td><td></td><td></td></tr><tr><td>GND</td><td>D18, E15, E21, F16, F20, J16, J20, L18, M16, M20, P18, R16, R20, V16, V20, Y18, AA14, AA17, AA19, AA22, AB15, AB21</td><td>Module Signal and power return and GND reference</td><td>P</td><td></td><td></td><td></td></tr><tr><td>SYS_RST#</td><td>U17</td><td>Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10K</td><td></td></tr><tr><td>CARRIER_PWR_EN</td><td>V17</td><td>Carrier board circuits should not be powered up until the module asserts the CARRIER_PWR_EN signal</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

<table><tr><td>VCC_OUT_IO</td><td>U18</td><td>Can provide IO voltage level for several interfaces to connect</td><td>P</td><td>1.8V/3.3V</td><td></td><td>Only applicable in size 0 – minimum current: 100mA; All other sizes or feature not used: NC</td></tr><tr><td>RTC_PWR</td><td>W17</td><td>Low current RTC circuit backup power – 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P</td><td></td><td></td><td></td></tr><tr><td>BOOT_SEL#</td><td>U19</td><td>If low on carrier board it has to boot from carrier boot medium (SD/USB/SPI)</td><td>I OD CMOS</td><td>1.8V</td><td>PU 10k</td><td>The boot medium is the choice of the module vendor.</td></tr></table>

Table 13: Size-0 Power

# 2.4.2.2 JTAG

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>JTAG_TCK(SWCLK)</td><td>N17</td><td>Test Clock</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>JTAG_TMS(SWDIO)</td><td>N19</td><td>Test Mode Select</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>JTAG_TDI</td><td>P17</td><td>Test Data Input</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>JTAG_RTCK</td><td>P19</td><td>Returned Test Clock</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>JTAG_TDO(SWO)</td><td>R17</td><td>Test Data Output</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>JTAG_nTRST</td><td>R19</td><td>Test Reset, Active Low</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>DEBUG_EN</td><td>AC18</td><td>Enables JTAG function</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>TEST_GENERIC</td><td>C18</td><td>General purpose for testing</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 14: Size-0 JTAG

# 2.4.2.3 UART

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>UART_A_RX</td><td>A14</td><td>Asynchronous serial data input port A</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_A_TX</td><td>B13</td><td>Asynchronous serial data output port A</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_A_RTS</td><td>C13</td><td>&quot;Request to Send&quot; handshake line for port A</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_A_CTS</td><td>C14</td><td>&quot;Clear to Send&quot; handshake line for port A</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_B_RX</td><td>D14</td><td>Asynchronous serial data input port B</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_B_TX</td><td>D13</td><td>Asynchronous serial data output port B</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_B_RTS</td><td>D15</td><td>&quot;Request to Send&quot; handshake line for port B</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_B_CTS</td><td>D16</td><td>&quot;Clear to Send&quot; handshake line for port B</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_C_RX</td><td>A22</td><td>Asynchronous serial data input port C</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_C_TX</td><td>B23</td><td>Asynchronous serial data output port C</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_D_RX</td><td>C22</td><td>Asynchronous serial data input port D</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_D_TX</td><td>C23</td><td>Asynchronous serial data output port D</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 15: Size-0 UART

# 2.4.2.4 UART Console

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>UART_CON_RX</td><td>D22</td><td>Asynchronous serial data input port console</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>UART_CON_TX</td><td>D23</td><td>Asynchronous serial data output port console</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 16: Size-0 UART Console

# 2.4.2.5 Ethernet

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_A_(R)(G)MII_CRS</td><td>E16</td><td>Carrier Sense port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_COL</td><td>F15</td><td>Collision detect (half speed only) port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD0</td><td>H15</td><td>Transmit data bit 0 (transmitted first) port A</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_TXD1</td><td>G15</td><td>Transmit data bit 1 port A</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_A_(R)(G)MII_TXD2</td><td>H16</td><td>Transmit data bit 2 port A</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_TXD3</td><td>G16</td><td>Transmit data bit 3 port A</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_TX_EN(ER)</td><td>K16</td><td>Transmit enable (Error) port A</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_TX_CLK</td><td>J15</td><td>Transmit clock port A</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD0</td><td>K15</td><td>Receive data bit 0 (received first) port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_A_(S)(R)(G)MII_RXD1</td><td>L15</td><td>Receive data bit 1 port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_A_(R)(G)MII_RXD2</td><td>N15</td><td>Receive data bit 2 port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RXD3</td><td>P15</td><td>Receive data bit 3 port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RX_ER</td><td>L16</td><td>Receive error port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RX_DV(ER)</td><td>M15</td><td>Receive data valid port A</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_(R)(G)MII_RX_CLK</td><td>R15</td><td>Receive clock port A</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_A_SDP</td><td>N16</td><td>Ethernet port A System Defined Contact</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

<table><tr><td>ETH_MDIO</td><td>T15</td><td>Management data</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_MDC</td><td>T16</td><td>Management data clock</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

Table 17: Size-0 Ethernet

# 2.4.2.6 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO_A_0</td><td>D17</td><td>General purpose I/O Contact A0</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_1</td><td>E17</td><td>General purpose I/O Contact A1</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_2</td><td>F17</td><td>General purpose I/O Contact A2</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_3</td><td>G17</td><td>General purpose I/O Contact A3</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_4</td><td>H17</td><td>General purpose I/O Contact A4</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_5</td><td>J17</td><td>General purpose I/O Contact A5</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_6</td><td>K17</td><td>General purpose I/O Contact A6</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_A_7</td><td>L17</td><td>General purpose I/O Contact A7</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_0</td><td>D19</td><td>General purpose I/O Contact B0</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_1</td><td>E19</td><td>General purpose I/O Contact B1</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_2</td><td>F19</td><td>General purpose I/O Contact B2</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_3</td><td>G19</td><td>General purpose I/O Contact B3</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_4</td><td>H19</td><td>General purpose I/O Contact B4</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_5</td><td>J19</td><td>General purpose I/O Contact B5</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_6</td><td>K19</td><td>General purpose I/O Contact B6</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_B_7</td><td>L19</td><td>General purpose I/O Contact B7</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 18: Size-0 GPIO

# 2.4.2.7 SDIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SDIO_A_CMD</td><td>E20</td><td>SDIO A Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_CLK</td><td>F21</td><td>SDIO A Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D0</td><td>G20</td><td>SDIO A Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D1</td><td>G21</td><td>SDIO A Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D2</td><td>H20</td><td>SDIO A Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_D3</td><td>H21</td><td>SDIO A Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_CD#</td><td>J21</td><td>SDIO A Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td></td></tr><tr><td>SDIO_A_WP</td><td>D20</td><td>SDIO A Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td>Tie to GND on carrier, if not used</td></tr><tr><td>SDIO_A_PWR_EN</td><td>D21</td><td>SDIO A Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_A_IOPWR</td><td>C20</td><td>SDIO A Voltage. It is used to provide the IO Voltage Level</td><td>P</td><td>1.8V or 3.3V</td><td></td><td>Minimum current: 100mA</td></tr><tr><td>SDIO_B_CLK</td><td>K20</td><td>SDIO B Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_CMD</td><td>K21</td><td>SDIO B Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr></table>

<table><tr><td>SDIO_B_D0</td><td>L20</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D1</td><td>L21</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D2</td><td>M21</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D3</td><td>N20</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D4</td><td>N21</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D5</td><td>P20</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D6</td><td>P21</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_D7</td><td>R21</td><td>SDIO B Data lines. These signals operate in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_CD#</td><td>T21</td><td>SDIO B Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td></td></tr><tr><td>SDIO_B_WP</td><td>U20</td><td>SDIO B Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>1.8V or 3.3V</td><td>PU 10k</td><td>Tie to GND on carrier, if not used</td></tr><tr><td>SDIO_B_PWR_EN</td><td>U21</td><td>SDIO B Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td></td><td></td></tr><tr><td>SDIO_B_IOPWR</td><td>T20</td><td>SDIO B Voltage. It is used to provide the IO Voltage Level</td><td>P</td><td>1.8V or 3.3V</td><td></td><td>Minimum current: 100mA</td></tr></table>

Table 19: Size-0 SDIO

# 2.4.2.8 PWM

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PWM_0</td><td>E18</td><td>Pulse width modulation 0</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>PWM_1</td><td>F18</td><td>Pulse width modulation 1</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>PWM_2</td><td>G18</td><td>Pulse width modulation 2</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>PWM_3</td><td>H18</td><td>Pulse width modulation 3</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>PWM_4</td><td>J18</td><td>Pulse width modulation 4</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>PWM_5</td><td>K18</td><td>Pulse width modulation 5</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 20: Size-0 PWM

# 2.4.2.9 Analog Signals

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ADC_0</td><td>M18</td><td>Analog Digital Converter 0</td><td>Analog</td><td>0V – 1.8V</td><td></td><td></td></tr><tr><td>ADC_1</td><td>N18</td><td>Analog Digital Converter 1</td><td>Analog</td><td>0V – 1.8V</td><td></td><td></td></tr></table>

Table 21: Size-0 Analog Signals

# 2.4.2.10 SPI

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI_A_SDI_(IO0)</td><td>U15</td><td>SPI A Serial Data Input</td><td>IO CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Alternate use: QuadSPI IO0</td></tr><tr><td>SPI_A_SDO_(IO1)</td><td>V15</td><td>SPI A Serial Data Output</td><td>IO CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Alternate use: QuadSPI IO1</td></tr><tr><td>SPI_A_/WP_(IO2)</td><td>W16</td><td>SPI A Write Protect</td><td>IO CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Alternate use: QuadSPI IO2</td></tr><tr><td>SPI_A_/HOLD_(IO3)</td><td>W15</td><td>SPI A Suspend Serial Input</td><td>IO CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Alternate use: QuadSPI IO3</td></tr><tr><td>SPI_A_CS#</td><td>Y15</td><td>SPI A Master Chip Select</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_A_SCK</td><td>U16</td><td>SPI A Serial Data Clock</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_SDI</td><td>Y22</td><td>SPI B Serial Data Input</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_SDO</td><td>Y23</td><td>SPI B Serial Data Output</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_CS#</td><td>AA23</td><td>SPI B Master Chip Select</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_B_SCK</td><td>Y21</td><td>SPI B Serial Data Clock</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 22: Size-0 SPI

# 2.4.2.11 I2S

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>I2S_A_DATA_IN</td><td>V21</td><td>I2S A Digital audio Input</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2S_A_DATA_OUT</td><td>W21</td><td>I2S A Digital audio Output</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2S_B_DATA_IN</td><td>V19</td><td>I2S B Digital audio Input</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2S_B_DATA_OUT</td><td>W19</td><td>I2S B Digital audio Output</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2S_MCLK</td><td>V18</td><td>Master clock output to I2S codec(s)</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2S_LRCLK</td><td>W18</td><td>I2S Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td>I2S_BITCLK</td><td>W20</td><td>I2S Digital audio clock</td><td>I/O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr></table>

Table 23: Size-0 I2S

# 2.4.2.12 CAN

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CAN_A_TX</td><td>AC17</td><td>CAN port A Transmit output</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_A_RX</td><td>AB17</td><td>CAN port A Receive input</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_B_TX</td><td>AC19</td><td>CAN port B Transmit output</td><td>O CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr><tr><td>CAN_B_RX</td><td>AB19</td><td>CAN port B Receive input</td><td>I CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td></td><td></td></tr></table>

Table 24: Size-0 CAN

# 2.4.2.13 USB

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB_A_D_N</td><td>AB13</td><td>USB differential data pairs for port A</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_A_D_P</td><td>AC14</td><td>USB differential data pairs for port A</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_A_ID</td><td>AB14</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_A_OC#</td><td>AC15</td><td>USB over-current for port A</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>USB_A_VBUS</td><td>AB16</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td></td><td></td></tr><tr><td>USB_A_EN</td><td>AC16</td><td>Power enable for usb VBUS voltage</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_B_D_N</td><td>AB23</td><td>USB differential data pairs for port B</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_B_D_P</td><td>AC22</td><td>USB differential data pairs for port B</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_B_ID</td><td>AB22</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_B_OC#</td><td>AC21</td><td>USB over-current for port B</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>USB_B_VBUS</td><td>AB20</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td></td><td></td></tr><tr><td>USB_B_EN</td><td>AC20</td><td>Power enable for usb VBUS voltage</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr></table>

Table 25: Size-0 USB

# 2.4.2.14 I2C

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level (Size-0 only, optional)</td><td>I/O Level (&gt;Size-0)</td><td>PU / PD</td><td>Comments</td></tr><tr><td>I2C_A_SCL</td><td>AA15</td><td>I2C Port A Clock Signal</td><td>I/O OD CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_A_SDA</td><td>AA16</td><td>I2C Port A Data Signal</td><td>I/O OD CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_B_SCL</td><td>AA20</td><td>I2C Port B Clock Signal</td><td>I/O OD CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_B_SDA</td><td>AA21</td><td>I2C Port B Data Signal</td><td>I/O OD CMOS</td><td>V_OUT_IO</td><td>1.8V</td><td>PU 2k2</td><td></td></tr></table>

Table 26: I2C

# 2.4.2.15 Communication Area

The Communication Area can have two different modes, which can be used exclusively either/or and are defined by the module manufacturer.

2.4.2.15.1 Communication Area in Wireless Mode

<table><tr><td>Contact Name</td><td>Contact Name in Wireless Mode</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>COM_AREA_01</td><td>ANT_GND</td><td>A15</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_02</td><td>ANT_MAIN</td><td>A16</td><td>Main Antenna</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_03</td><td>ANT_GND</td><td>A17</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_04</td><td>ANT_GND</td><td>A18</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_05</td><td>ANT_GND</td><td>A19</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_06</td><td>ANT_AUX</td><td>A20</td><td>Antenna Auxiliary Signal</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_07</td><td>ANT_GND</td><td>A21</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_08</td><td>ANT_GND</td><td>B15</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_09</td><td>ANT_GND</td><td>B16</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_10</td><td>ANT_GND</td><td>B17</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_11</td><td>ANT_GND</td><td>B18</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_12</td><td>ANT_GND</td><td>B19</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_13</td><td>ANT_GND</td><td>B20</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_14</td><td>ANT_GND</td><td>B21</td><td>Antenna Ground</td><td></td><td></td><td></td><td></td></tr></table>

<table><tr><td>COM_AREA_15</td><td>ANT_MAIN_TEST</td><td>C15</td><td>Main antenna test point</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_16</td><td>ANT_B_MAIN_TEST</td><td>C17</td><td>Main antenna test point</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_17</td><td>ANT_B_AUX_TEST</td><td>C19</td><td>Auxiliary antenna test point</td><td></td><td></td><td></td><td></td></tr><tr><td>COM_AREA_18</td><td>ANT_AUX_TEST</td><td>C21</td><td>Auxiliary antenna test point</td><td></td><td></td><td></td><td></td></tr></table>

Table 27: Size-0 Communication Area - Wireless Mode

2.4.2.15.2 Communication Area in Fieldbus Mode

<table><tr><td>Contact Name</td><td>Contact Name in Fieldbus Mode</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>COM_AREA_01</td><td>CH1_RX_N</td><td>A15</td><td>MDI Channel 1</td><td>I MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_02</td><td>CH1_LINK</td><td>A16</td><td>LINK LED Channel 0</td><td>O OD CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_03</td><td>CH1_TX_N</td><td>A17</td><td>MDI Channel 1</td><td>O MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_04</td><td>CHO_SYNC_TRIGGER</td><td>A18</td><td>SYNC Trigger Signal Channel 0</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_05</td><td>CHO_RX_N</td><td>A19</td><td>MDI Channel 0</td><td>I MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_06</td><td>CHO_LINK</td><td>A20</td><td>LINK LED Channel 0</td><td>O OD CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_07</td><td>CHO_TX_N</td><td>A21</td><td>MDI Channel 0</td><td>O MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_08</td><td>CH1_RX_P</td><td>B15</td><td>MDI Channel 1</td><td>I MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_09</td><td>CH1_ACT</td><td>B16</td><td>ACT LED Channel 1</td><td>O OD CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_10</td><td>CH1_TX_P</td><td>B17</td><td>MDI Channel 1</td><td>O MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_11</td><td>CH1_SYNC_TRIGGER</td><td>B18</td><td>SYNC Trigger Signal Channel 1</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_12</td><td>CHO_RX_P</td><td>B19</td><td>MDI Channel 0</td><td>I MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_13</td><td>CHO_ACT</td><td>B20</td><td>ACT LED Channel 0</td><td>O OD CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_14</td><td>CHO_TX_P</td><td>B21</td><td>MDI Channel 0</td><td>O MDI</td><td></td><td></td><td>Auto-MDIX capable</td></tr><tr><td>COM_AREA_15</td><td>CH1_RXC</td><td>C15</td><td>MDI Channel 1</td><td>Analog</td><td>0 to 3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_16</td><td>CH1_TXC</td><td>C17</td><td>MDI Channel 1</td><td>Analog</td><td>0 to 3.3V</td><td></td><td></td></tr><tr><td>COM_AREA_17</td><td>CHO_RXC</td><td>C19</td><td>MDI Channel 0</td><td>Analog</td><td>0 to 3.3V</td><td></td><td></td></tr></table>

<table><tr><td>COM_AREA_18</td><td>CHO_TXC</td><td>C21</td><td>MDI Channel 0</td><td>Analog</td><td>0 to 3.3V</td><td></td><td></td></tr></table>

Table 28: Size-0 Communication Area - Fieldbus Mode

# 2.4.2.16 Reserved

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>RESERVED</td><td>R18, T17, T18, T19, Y13, Y14, AA13</td><td>Reserved for future use</td><td></td><td></td><td></td><td></td></tr></table>

Table 29: Size-0 Reserved Contacts

2.4.2.17 Vendor Defined Contacts

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>Vendor Defined</td><td>B22, C16, P16</td><td>Defined by module manufacturer</td><td></td><td></td><td></td><td></td></tr></table>

# 2.4.3 Size-S – Additional Functionality

# 2.4.3.1 Power Supply + Ground

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VCC_5_TEST</td><td>Y3</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_6_TEST</td><td>C5</td><td>Module power voltage test point</td><td>P</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VCC_IN_5V</td><td>Y8, Y9, Y10, Y11</td><td>Module power input voltage of 5V</td><td>P</td><td></td><td></td><td></td></tr><tr><td>GND</td><td>A4, A7, A10, B2, B5, B8, B9, C11, D1, D5, D8, E2, H2, H4, L2, L4, P2, P4, R1, U2, U4, V1, W3, Y2, AA1, AA4, AA7, AA8, AA10, AA11, AB3, AB6, AB9, AC4, AC7, AC10</td><td>Module Signal and power return and GND reference</td><td>P</td><td></td><td></td><td></td></tr><tr><td>PWR_BTN#</td><td>AA9</td><td>Power-button input from Carrier board. Carrier to float the line in in-active state.Active low, level sensitive. Should be de-bounced on the Module.</td><td>I OD CMOS</td><td>1.8 to 5V</td><td>PU 10K</td><td></td></tr></table>

Table 30: Size-S Power + Ground

# 2.4.3.2 Ethernet / LAN

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_B_(R)(G)MII_CRS</td><td>D2</td><td>Carrier Sense port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_COL</td><td>E1</td><td>Collision detect (half speed only) port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD0</td><td>G1</td><td>Transmit data bit 0 (transmitted first) port B</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_TXD1</td><td>F1</td><td>Transmit data bit 1 port B</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_B_(R)(G)MII_TXD2</td><td>G2</td><td>Transmit data bit 2 port B</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_TXD3</td><td>F2</td><td>Transmit data bit 3 port B</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_TX_EN(_ER)</td><td>J2</td><td>Transmit enable (Error) port B</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_TX_CLK</td><td>H1</td><td>Transmit clock port B</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(S)(R)(G)MII_RXD0</td><td>J1</td><td>Receive data bit 0 (received first) port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_B_(S)(R)(G)MII_RXD1</td><td>K1</td><td>Receive data bit 1 port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_B_(R)(G)MII_RXD2</td><td>M1</td><td>Receive data bit 2 port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RXD3</td><td>N1</td><td>Receive data bit 3 port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RX_ER</td><td>K2</td><td>Receive error port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RX_DV(_ER)</td><td>L1</td><td>Receive data valid (Error) port B</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_(R)(G)MII_RX_CLK</td><td>P1</td><td>Receive clock port B</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_B_SDP</td><td>M2</td><td>Ethernet port B System Defined Contact</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

Table 31 Size-S: Ethernet

# 2.4.3.3 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO_C_0</td><td>D3</td><td>General purpose I/O Contact C0</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_1</td><td>D4</td><td>General purpose I/O Contact C1</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_2</td><td>E3</td><td>General purpose I/O Contact C2</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_3</td><td>E4</td><td>General purpose I/O Contact C3</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_4</td><td>F3</td><td>General purpose I/O Contact C4</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_5</td><td>F4</td><td>General purpose I/O Contact C5</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_C_6</td><td>G3</td><td>General purpose I/O Contact C6</td><td>I/O CMOS</td><td>1.8V</td><td></td><td>Dual function: CAM_PWR</td></tr><tr><td>GPIO_C_7</td><td>G4</td><td>General purpose I/O Contact C7</td><td>I/O CMOS</td><td>1.8V</td><td></td><td>Dual function: CAM_RST#</td></tr></table>

Table 32: Size-S GPIO

# 2.4.3.4 MIPI DSI

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>DSI_DATA0_N</td><td>AB11</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA0_P</td><td>AB10</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA1_N</td><td>AC9</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA1_P</td><td>AC8</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA2_N</td><td>AC6</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA2_P</td><td>AC5</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA3_N</td><td>AB5</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_DATA3_P</td><td>AB4</td><td>DSI differential output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_CLOCK_N</td><td>AB8</td><td>DSI differential clock output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_CLOCK_P</td><td>AB7</td><td>DSI differential clock output (point to point)</td><td>O LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>DSI_TE</td><td>AA3</td><td>DSI panel tearing effect signal</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 33: Size-S MIPI DSI

# 2.4.3.5 MIPI CSI

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI_DATA0_N</td><td>C1</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY/ I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA0_P</td><td>B1</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA1_N</td><td>A2</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA1_P</td><td>A3</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA2_N</td><td>A5</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA2_P</td><td>A6</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA3_N</td><td>B6</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_DATA3_P</td><td>B7</td><td>CSI differential input (point to point)</td><td>I LVDS D-PHY / I LVDS M-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_CLOCK_N</td><td>B3</td><td>CSI differential clock input (point to point)</td><td>I LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>CSI_CLOCK_P</td><td>B4</td><td>CSI differential clock input (point to point)</td><td>I LVDS D-PHY</td><td></td><td></td><td></td></tr><tr><td>CAM_MCK</td><td>C2</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>I2C_CAM_SDA / CSI_TX_N</td><td>C3</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM_SDA MIPI-CSI 3.0 mode uses CSI_TX_N</td></tr><tr><td>I2C_CAM_SCL / CSI_TX_P</td><td>C4</td><td>I2C clock for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 mode uses I2C_CAM_SCL MIPI-CSI 3.0 mode uses CSI_TX_P</td></tr><tr><td>CAM_PWR / GPIO_C_6</td><td>G3</td><td>Camera 0 Power Enable, active high output.</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

<table><tr><td>CAM_RST# / GPIO_C_7</td><td>G4</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 34: Size-S MIPI CSI

2.4.3.6 Parallel RGB Display

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>RGB_R0</td><td>Y7</td><td>Red data bit 0</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_R1</td><td>AA6</td><td>Red data bit 1</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_R2</td><td>Y6</td><td>Red data bit 2</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_R3</td><td>AA5</td><td>Red data bit 3</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_R4</td><td>Y5</td><td>Red data bit 4</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_R5</td><td>Y4</td><td>Red data bit 5</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G0</td><td>W4</td><td>Green data bit 0</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G1</td><td>V3</td><td>Green data bit 1</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G2</td><td>V4</td><td>Green data bit 2</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G3</td><td>U3</td><td>Green data bit 3</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G4</td><td>T3</td><td>Green data bit 4</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_G5</td><td>T4</td><td>Green data bit 5</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B0</td><td>R4</td><td>Blue data bit 0</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B1</td><td>R3</td><td>Blue data bit 1</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B2</td><td>P3</td><td>Blue data bit 2</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B3</td><td>N3</td><td>Blue data bit 3</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B4</td><td>N4</td><td>Blue data bit 4</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_B5</td><td>M3</td><td>Blue data bit 5</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr></table>

<table><tr><td>RGB_(PIXEL)CLK</td><td>M4</td><td>Pixel clock signal</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_VSYNC</td><td>L3</td><td>Vertical synch</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_HSYNC</td><td>K3</td><td>horizontal synch</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_DISP</td><td>K4</td><td>Display ON/OFF</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_DE</td><td>J4</td><td>Data Enable</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_RESET#</td><td>J3</td><td>Global Reset</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>RGB_CS#</td><td>H3</td><td>Chip select</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr></table>

Table 35: Size-S Parallel RGB Display

# 2.4.3.7 USB

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB_C_D_N</td><td>D11</td><td>USB differential data pairs for port C</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_C_D_P</td><td>D10</td><td>USB differential data pairs for port C</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_C_ID</td><td>D9</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_C_OC#</td><td>C8</td><td>USB over-current for port C</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>USB_C_VBUS</td><td>C9</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td></td><td></td></tr><tr><td>USB_C_EN</td><td>C10</td><td>Power enable for usb VBUS voltage</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_C_SSTX_N</td><td>A9</td><td>Transmit signal differential pairs for SuperSpeed on port C</td><td>O USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_C_SSTX_P</td><td>A8</td><td>Transmit signal differential pairs for SuperSpeed on port C</td><td>O USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_C_SSRX_N</td><td>B11</td><td>Receive signal differential pairs for SuperSpeed on port C</td><td>I USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_C_SSRX_P</td><td>B10</td><td>Receive signal differential pairs for SuperSpeed on port C</td><td>I USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr></table>

Table 36: Size-S UFS

# 2.4.3.8 PCIe

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIe_A_HSIO_P</td><td>AB1</td><td>Differential PCIe link A receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_A_HSIO_N</td><td>AB2</td><td>Differential PCIe link A receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_A_HSO0_P</td><td>AC2</td><td>Differential PCIe link A transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_A_HSO0_N</td><td>AC3</td><td>Differential PCIe link A transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_A_PRSNT#</td><td>W2</td><td>PCIe Port A present input</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>PCIe_A_PERST#</td><td>V2</td><td>PCIe Port A reset output</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>PCIe_REFCLK_P</td><td>W1</td><td>Differential PCIe reference clock output</td><td>O LVDS PCIE</td><td></td><td></td><td></td></tr><tr><td>PCIe_REFCLK_N</td><td>Y1</td><td>Differential PCIe reference clock output</td><td>O LVDS PCIE</td><td></td><td></td><td></td></tr><tr><td>PCIe_WAKE#</td><td>T2</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>PCIe_SMDAT</td><td>U1</td><td>System management I2C bus DATA</td><td>I/O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>PCIe_SMCLK</td><td>T1</td><td>System management I2C bus CLK</td><td>O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>PCIe_SM_ALERT#</td><td>R2</td><td>SMBus Alert# (interrupt) signal</td><td>I OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr></table>

Table 37: Size-S PCIe

# 2.4.3.9 Reserved

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>RESERVED</td><td>N2, AA2</td><td>Reserved for future use</td><td></td><td></td><td></td><td></td></tr></table>

Table 38: Size-S Reserved Contacts

# 2.4.3.10 Vendor Defined Contacts

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>Vendor Defined</td><td>C6, C7, D6, D7</td><td>Defined by module manufacturer</td><td></td><td></td><td></td><td></td></tr></table>

Table 39: Size-S Vendor Defined Contacts

# 2.4.4 Size-M – Additional Functionality

# 2.4.4.1 Power Supply + Ground

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VCC_7_TEST</td><td>AA33</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td>VCC_8_TEST</td><td>B29</td><td>Module power voltage testpoint</td><td>P</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>VCC_IN_5V</td><td>Y25, Y26, Y27, Y28</td><td>Module power input voltage of 5V</td><td>P</td><td></td><td></td><td></td></tr><tr><td>GND</td><td>A26, A29, A32, B27, B28, B30, B33, C25, C32, C35, D28, D34, F33, F35, G34, H32, J33, J35, K34, M35, N34, T34, W34, AA25, AA26, AA27, AA28, AA32, AB28, AB31, AB34, AC27, AC30, AC33</td><td>Module Signal and power return and GND reference</td><td>P</td><td></td><td></td><td></td></tr></table>

Table 40: Size-M Power + Ground

# 2.4.4.2 Ethernet / LAN

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_C_(R)(G)MII_CRS</td><td>AC34</td><td>Carrier Sense port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_COL</td><td>AB35</td><td>Collision detect (half speed only) port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(S)(R)(G)MII_TXD0</td><td>Y35</td><td>Transmit data bit 0 (transmitted first) port C</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_C_(S)(R)(G)MII_TXD1</td><td>AA35</td><td>Transmit data bit 1 port C</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_C_(R)(G)MII_TXD2</td><td>Y34</td><td>Transmit data bit 2 port C</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_TXD3</td><td>AA34</td><td>Transmit data bit 3 port C</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_TX_EN(_ER)</td><td>V34</td><td>Transmit enable (Error) port C</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_TX_CLK</td><td>N35</td><td>Transmit clock port C</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(S)(R)(G)MII_RXD0</td><td>V35</td><td>Receive data bit 0 (received first) port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_C_(S)(R)(G)MII_RXD1</td><td>U35</td><td>Receive data bit 1 port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_C_(R)(G)MII_RXD2</td><td>R35</td><td>Receive data bit 2 port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_RXD3</td><td>P35</td><td>Receive data bit 3 port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_RX_ER</td><td>U34</td><td>Receive error port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_RX_DV(_ER)</td><td>T35</td><td>Receive data valid (Error) port C</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_(R)(G)MII_RX_CLK</td><td>W35</td><td>Receive clock port C</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_C_SDP</td><td>R34</td><td>Ethernet port C System Defined Contact</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

Table 41: Size-M Ethernet

# 2.4.4.3 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO_D_0</td><td>U32</td><td>General purpose I/O Contact D0</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_1</td><td>U33</td><td>General purpose I/O Contact D1</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_2</td><td>V32</td><td>General purpose I/O Contact D2</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_3</td><td>V33</td><td>General purpose I/O Contact D3</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_4</td><td>W32</td><td>General purpose I/O Contact D4</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_5</td><td>W33</td><td>General purpose I/O Contact D5</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_6</td><td>Y32</td><td>General purpose I/O Contact D6</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_D_7</td><td>Y33</td><td>General purpose I/O Contact D7</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 42: Size-M GPIO

# 2.4.4.4 SPI

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI_C_SDI</td><td>C29</td><td>SPI C Serial Data Input</td><td>I CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_SDO</td><td>D30</td><td>SPI C Serial Data Output</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_CS#</td><td>C30</td><td>SPI C Master Chip Select</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>SPI_C_SCK</td><td>D29</td><td>SPI C Serial Data Clock</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 43: Size-M SPI

# 2.4.4.5 UFS

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>UFS_TX0_N</td><td>AC29</td><td>UFS differential output (point to point)</td><td>O LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_TX0_P</td><td>AC28</td><td>UFS differential output (point to point)</td><td>O LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_RX0_N</td><td>AC32</td><td>UFS differential input (point to point)</td><td>I LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_RX0_P</td><td>AC31</td><td>UFS differential input (point to point)</td><td>I LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_TX1_N</td><td>AB30</td><td>UFS differential output (point to point)</td><td>O LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_TX1_P</td><td>AB29</td><td>UFS differential output (point to point)</td><td>O LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_RX1_N</td><td>AB33</td><td>UFS differential input (point to point)</td><td>I LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_RX1_P</td><td>AB32</td><td>UFS differential input (point to point)</td><td>I LVDS UFS</td><td></td><td></td><td></td></tr><tr><td>UFS_RESET#</td><td>AB27</td><td>UFS reset output</td><td>O CMOS</td><td>1.8V / 1.2V</td><td></td><td>USF 3.0 need 1.2V I/O level</td></tr><tr><td>UFS_CLK</td><td>AC26</td><td>UFS reference clock output</td><td>O CMOS</td><td>1.8V / 1.2 V</td><td></td><td>USF 3.0 need 1.2V I/O level</td></tr></table>

Table 44: Size-M UFS

# 2.4.4.6 USB

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB_D_D_N</td><td>D26</td><td>USB differential data pairs for port D</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_D_D_P</td><td>D25</td><td>USB differential data pairs for port D</td><td>I/O USB</td><td>USB</td><td></td><td></td></tr><tr><td>USB_D_ID</td><td>D27</td><td>Input Contact to announce OTG device insertion on USB 2.0 port</td><td>I CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_D_OC#</td><td>C28</td><td>USB over-current for port D</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>USB_D_VBUS</td><td>C27</td><td>USB port 0 port power detection</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td></td><td></td></tr><tr><td>USB_D_EN</td><td>C26</td><td>Power enable for usb VBUS voltage</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>USB_D_SSTX_N</td><td>A28</td><td>Transmit signal differential pairs for SuperSpeed on port D</td><td>O USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_D_SSTX_P</td><td>A27</td><td>Transmit signal differential pairs for SuperSpeed on port D</td><td>O USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_D_SSRX_N</td><td>B26</td><td>Receive signal differential pairs for SuperSpeed on port D</td><td>I USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_D_SSRX_P</td><td>B25</td><td>Receive signal differential pairs for SuperSpeed on port D</td><td>I USB SS</td><td>USB SS</td><td></td><td>AC coupled off module</td></tr></table>

Table 45: Size-M USB

# 2.4.4.7 PCIe

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIe_B_HSI0_P</td><td>L34</td><td>Differential PCIe link B receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_B_HSI0_N</td><td>M34</td><td>Differential PCIe link B receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_B_HSO0_P</td><td>K35</td><td>Differential PCIe link B transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_B_HSO0_N</td><td>L35</td><td>Differential PCIe link B transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_B_PRSNT#</td><td>K33</td><td>PCIe Port B present input</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>PCIe_B_PERST#</td><td>L33</td><td>PCIe Port B reset output</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr></table>

Table 46: Size-M PCIe

2.4.4.8 eDP/eDP++

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>eDP_A_LANE0_P</td><td>A30</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE0_N</td><td>A31</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE1_P</td><td>B31</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE1_N</td><td>B32</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE2_P</td><td>A33</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE2_N</td><td>A34</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE3_P</td><td>B34</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_LANE3_N</td><td>B35</td><td>Primary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_A_AUX_P</td><td>C33</td><td>Primary bidirectional channel used for link management and device control</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>AC coupled off module</td></tr><tr><td>eDP_A_AUX_N</td><td>C34</td><td>Primary bidirectional channel used for link management and device control</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>AC coupled off module</td></tr><tr><td>eDP_A_AUX_SEL</td><td>D32</td><td>Strapping signal to enable either HDMI or DP output</td><td>I CMOS</td><td>1.8V</td><td>PD 1M</td><td>Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode</td></tr><tr><td>eDP_A_BL_HPD</td><td>D33</td><td>Detection of Hot Plug / Unplug of primary eDP display and notification of the link layer.</td><td>I CMOS</td><td>1.8V</td><td>PD 1M</td><td>Module must tolerate high level in stand-by mode</td></tr><tr><td>eDP_A_BL_EN</td><td>D31</td><td>Primary panel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>eDP_A_BL_PWM</td><td>C31</td><td>Primary panel brightness control through pulse width modulation</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>eDP_B_LANE0_P</td><td>D35</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE0_N</td><td>E35</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE1_P</td><td>E34</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE1_N</td><td>F34</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE2_P</td><td>G35</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE2_N</td><td>H35</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE3_P</td><td>H34</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_LANE3_N</td><td>J34</td><td>Secondary 4-lane eDP differential pair data lines</td><td>O LVDS DP</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_B_AUX_P</td><td>G33</td><td>Secondary bidirectional channel used for link management and device control</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>AC coupled off module</td></tr><tr><td>eDP_B_AUX_N</td><td>H33</td><td>Secondary bidirectional channel used for link management and device control</td><td>I/O LVDS DP</td><td></td><td>PD 100k</td><td>AC coupled off module</td></tr><tr><td>eDP_B_AUX_SEL</td><td>F32</td><td>Auxiliary Selection</td><td>I CMOS</td><td>1.8V</td><td>PD 1M</td><td>Pulled to GND on Carrier for DP operation in Dual Mode (DP++) implementations. Driven to 1.8V on carrier for HDMI mode Module must tolerate high level in stand-by mode</td></tr><tr><td>eDP_B_BL_HPD</td><td>G32</td><td>Detection of Hot Plug / Unplug of secondary eDP display and notification of the link layer.</td><td>I CMOS</td><td>1.8V</td><td>PD 1M</td><td>Module must tolerate high level in stand-by mode</td></tr><tr><td>eDP_B_BL_EN</td><td>E32</td><td>Secondary panel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

<table><tr><td>eDP_B_BL_PWM</td><td>E33</td><td>Secondary panel brightness control through pulse width modulation</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 47: Size-M eDP

# 2.4.4.9 Reserved

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>RESERVED</td><td>J32, K32, L32, M32, M33, N32, N33, P32, P33, P34, R32, R33, T32, T33, AB25, AB26</td><td>Reserved for future use</td><td></td><td></td><td></td><td></td></tr></table>

Table 48: Size-M Reserved Contacts

# 2.4.4.10 Vendor Defined Contacts

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>Vendor Defined</td><td>Y29, Y30, Y31, AA29, AA30, AA31</td><td>Defined by module manufacturer</td><td></td><td></td><td></td><td></td></tr></table>

Table 49: Size-M Vendor Defined Contacts

# 2.4.5 Size-L – Additional Functionality

# 2.4.5.1 Power Supply + Ground

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>VCC_IN_5V</td><td>AE4, AF4, AG4, AH3, AH4, AJ3, AJ4, AK4</td><td>Module power input voltage of 5V</td><td>P</td><td></td><td></td><td></td></tr><tr><td>GND</td><td>AE2, AE34, AF35, AG3, AH2, AH34, AJ35, AK3, AL2, AL34, AM13, AM16, AM19, AM22, AM35, AN3, AN6, AN9, AN11, AN15, AN18, AN21, AN33, AP2, AP5, AP8, AP13, AP16, AP19, AP22, AP25, AP28, AP31, AP34, AR14, AR17, AR20, AR26, AR29, AR32</td><td>Module Signal and power return and GND reference</td><td>P</td><td></td><td></td><td></td></tr></table>

Table 50: Size-L Power + Ground

2.4.5.2 Ethernet / LAN

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ETH_D_(R)(G)MII_CRS</td><td>AE3</td><td>Carrier Sense port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_COL</td><td>AF3</td><td>Collision detect (half speed only) port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(S)(R)(G)MII_TXD0</td><td>AF1</td><td>Transmit data bit 0 (transmitted first) port D</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_D_(S)(R)(G)MII_TXD1</td><td>AG1</td><td>Transmit data bit 1 port D</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_D_(R)(G)MII_TXD2</td><td>AG2</td><td>Transmit data bit 2 port D</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_TXD3</td><td>AF2</td><td>Transmit data bit 3 port D</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_TX_EN(_ER)</td><td>AJ2</td><td>Transmit enable (Error) port D</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_TX_CLK</td><td>AH1</td><td>Transmit clock port D</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(S)(R)(G)MII_RXD0</td><td>AJ1</td><td>Receive data bit 0 (received first) port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_D_(S)(R)(G)MII_RXD1</td><td>AK1</td><td>Receive data bit 1 port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_D_(R)(G)MII_RXD2</td><td>AM1</td><td>Receive data bit 2 port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_RXD3</td><td>AN1</td><td>Receive data bit 3 port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_RX_ER</td><td>AK2</td><td>Receive error port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_RX_DV(_ER)</td><td>AL1</td><td>Receive data valid (Error) port D</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_(R)(G)MII_RX_CLK</td><td>AP1</td><td>Receive clock port D</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_D_SDP</td><td>AM2</td><td>Ethernet port D System Defined Contact</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_CRS</td><td>AN4</td><td>Carrier Sense port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

<table><tr><td>ETH_E_(R)(G)MII_COL</td><td>AR2</td><td>Collision detect (half speed only) port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(S)(R)(G)MII_TXD0</td><td>AR3</td><td>Transmit data bit 0 (transmitted first) port E</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_E_(S)(R)(G)MII_TXD1</td><td>AR4</td><td>Transmit data bit 1 port E</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_E_(R)(G)MII_TXD2</td><td>AP3</td><td>Transmit data bit 2 port E</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_TXD3</td><td>AP4</td><td>Transmit data bit 3 port E</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_TX_EN(_ER)</td><td>AP6</td><td>Transmit enable (Error) port E</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_TX_CLK</td><td>AR5</td><td>Transmit clock port E</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(S)(R)(G)MII_RXD0</td><td>AR6</td><td>Receive data bit 0 (received first) port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_P when used as differential</td></tr><tr><td>ETH_E_(S)(R)(G)MII_RXD1</td><td>AR7</td><td>Receive data bit 1 port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td>_N when used as differential</td></tr><tr><td>ETH_E_(R)(G)MII_RXD2</td><td>AR9</td><td>Receive data bit 2 port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_RXD3</td><td>AR10</td><td>Receive data bit 3 port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_RX_ER</td><td>AP7</td><td>Receive error port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_RX_DV(_ER)</td><td>AR8</td><td>Receive data valid (Error) port E</td><td>I CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_(R)(G)MII_RX_CLK</td><td>AN10</td><td>Receive clock port E</td><td>I/O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr><tr><td>ETH_E_SDP</td><td>AP9</td><td>Ethernet port E System Defined Contact</td><td>O CMOS</td><td>1.8V/2.5V/3.3V</td><td></td><td></td></tr></table>

Table 51: Size-L Ethernet

# 2.4.5.3 GPIO

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO_E_0</td><td>AF32</td><td>General purpose I/O Contact E0</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_1</td><td>AF33</td><td>General purpose I/O Contact E1</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_2</td><td>AG32</td><td>General purpose I/O Contact E2</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_3</td><td>AG33</td><td>General purpose I/O Contact E3</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_4</td><td>AH32</td><td>General purpose I/O Contact E4</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_5</td><td>AH33</td><td>General purpose I/O Contact E5</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_6</td><td>AJ32</td><td>General purpose I/O Contact E6</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>GPIO_E_7</td><td>AJ33</td><td>General purpose I/O Contact E7</td><td>I/O CMOS</td><td>1.8V</td><td></td><td></td></tr></table>

Table 52: Size-L GPIO

2.4.5.4 LVDS – Display Interface

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>LVDS_I2C_CLK</td><td>AM11</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>AM12</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>PU 2k2</td><td></td></tr><tr><td>LVDS_VDD_EN</td><td>AN14</td><td>LVDS channel power enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_BL_PWM</td><td>AN22</td><td>LVDS channel brightness control through pulse width modulation</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_BL_EN</td><td>AN23</td><td>LVDS channel backlight enable, active high</td><td>O CMOS</td><td>1.8V</td><td></td><td></td></tr><tr><td>LVDS_A_CLK_P</td><td>AN13</td><td>LVDS channel A differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_CLK_N</td><td>AN12</td><td>LVDS channel A differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE0_P</td><td>AP18</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE0_N</td><td>AP17</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE1_P</td><td>AR16</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE1_N</td><td>AR15</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE2_P</td><td>AP15</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE2_N</td><td>AP14</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE3_P</td><td>AP12</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_A_LANE3_N</td><td>AP11</td><td>LVDS channel A differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_CLK_P</td><td>AN17</td><td>LVDS channel B differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_CLK_N</td><td>AN16</td><td>LVDS channel B differential pair clock lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr></table>

<table><tr><td>LVDS_B_LANE0_P</td><td>AM21</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE0_N</td><td>AM20</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE1_P</td><td>AN20</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE1_N</td><td>AN19</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE2_P</td><td>AM18</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE2_N</td><td>AM17</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE3_P</td><td>AM15</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr><tr><td>LVDS_B_LANE3_N</td><td>AM14</td><td>LVDS channel B differential pair data lines</td><td>O LVDS LCD</td><td></td><td></td><td></td></tr></table>

Table 53: Size-L LVDS

2.4.5.5 PCIe x4

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIe_C_HSI0_P</td><td>AP33</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI0_N</td><td>AP32</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO0_P</td><td>AR34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO0_N</td><td>AR33</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI1_P</td><td>AN35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI1_N</td><td>AP35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO1_P</td><td>AM34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO1_N</td><td>AN34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI2_P</td><td>AK35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI2_N</td><td>AL35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO2_P</td><td>AJ34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO2_N</td><td>AK34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI3_P</td><td>AG35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSI3_N</td><td>AH35</td><td>Differential PCIe link C receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO3_P</td><td>AF34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_HSO3_N</td><td>AG34</td><td>Differential PCIe link C transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_C_PRSNT#</td><td>AE32</td><td>PCIe Port C present input</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr></table>

<table><tr><td>PCIe_C_PERST#</td><td>AE33</td><td>PCIe Port C reset output</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr><tr><td>PCIe_D_HSI0_P</td><td>AR19</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI0_N</td><td>AR18</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO0_P</td><td>AP21</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO0_N</td><td>AP20</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI1_P</td><td>AR22</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI1_N</td><td>AR21</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO1_P</td><td>AP24</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO1_N</td><td>AP23</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI2_P</td><td>AP27</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI2_N</td><td>AP26</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO2_P</td><td>AR28</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO2_N</td><td>AR27</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI3_P</td><td>AP30</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSI3_N</td><td>AP29</td><td>Differential PCIe link D receive data pair</td><td>I LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO3_P</td><td>AR31</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_HSO3_N</td><td>AR30</td><td>Differential PCIe link D transmit data pair</td><td>O LVDS PCIE</td><td></td><td></td><td>AC coupled off module</td></tr><tr><td>PCIe_D_PRSNT#</td><td>AN31</td><td>PCIe Port D present input</td><td>I OD CMOS</td><td>3.3V</td><td>PU 10k</td><td></td></tr><tr><td>PCIe_D_PERST#</td><td>AN32</td><td>PCIe Port D reset output</td><td>O CMOS</td><td>3.3V</td><td></td><td></td></tr></table>

Table 54: Size-L PCIe x4

# 2.4.5.6 Reserved

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>RESERVED</td><td>AL3, AL4, AM3, AM4, AM5, AM6, AM7, AM8, AM9, AM10, AM23, AM24, AM25, AM26,AM27, AM28, AM29, AM30, AM31, AN2, AN5, AN7, AN8, AN24, AN25, AN26, AN27, AN28, AN29, AN30, AP10</td><td>Reserved for future use</td><td></td><td></td><td></td><td></td></tr></table>

Table 55: Size-L Reserved Contacts

# 2.4.5.7 Vendor Defined Contacts

<table><tr><td>Contact Name</td><td>Contact Acronym</td><td>Functional Description</td><td>I/O Type</td><td>I/O Level</td><td>PU / PD</td><td>Comments</td></tr><tr><td>Vendor Defined</td><td>AK32, AK33, AL32, AL33, AM32, AM33</td><td>Defined by module manufacturer</td><td></td><td></td><td></td><td></td></tr></table>

Table 56: Vendor Defined Contacts

# 2.5 Module Designation

All modules adhering to the Open Standard Module™ Specification shall use a consistent and unique designator describing size and height of the Module. This designator shall be used together with the vendor’s and module name of the Open Standard Module™.

The Open Standard Module™ designator consists of the prefix “OSM-“ combined with two further letters/characters describing size and height of the module.

[vendor’s name] [module name] OSM-[module size][module height]

The following examples illustrate the designator for Open Standard Modules™:

OSM-0F: OSM™ module with Size-0 “Zero” and Height “Flat”
 OSM-SE: OSM™ module with Size-S “Small” and Height “Extended”
 OSM-LE: OSM™ module with Size-L “Large” and Height “Extended”

# 2.6 Packing and Production Technologies

# 2.6.1 Packing Method

All modules adhering to the Open Standard Module™ Specification should be packed and stored in a predefined SMD tape / reel or JEDEC tray, as shown for example below:

![Two black plastic test trays with square cavities, placed on a white surface (no text or symbols visible)](.osm-specification-v1-0/3f81f4d46165241f8774d1a3d7436b852253f00a51b3c6b64718ecb3bd9444ca.jpg)

Figure 27: JEDEC Tray

![Film reel with green circuit board embedded in film, no visible text or symbols](.osm-specification-v1-0/e06b972d0cabd66df954e6dfe08314ca4518df9626259617039dafd1e766aeb6.jpg)

Figure 28: Reel

# 2.6.2 Handling Instruction

For all modules adhering to the Open Standard Module™ Specification the vendor shall provide a detailed set of information regarding the subsequent handling process, such as

Carrier board pad design
 Processing
 Packaging Notes

It is recommended to use following draft for the module’s documentation

# Subject

In the following processing recommendations for the xxxxx1 are given.

# Design

Carrier board pad design

The terminal pad size should be Ø xx mm, like the pad size of the Module. The pitch is xx mm.

(detailed drawing)

# Stencil layout for paste print

The paste should be printed with a stencil thickness of xx µm.

The breakthroughs have to be square (xx mm edge length, xx µm corner radius).

It is recommended to use the solder paste as on the pre-soldered contact pads of the Module: Type of Solder past

# Processing

# Storage

The Module is sensitive to humidity

The Module are delivered in suitable packaging including dry bag.

The storage time of the Module is limited to xx hours at max. +xx °C and max. xx % relative humidity, when the package is opened.

It is not recommended to repeat drying procedures.

# Assembly

The xxxxxx are assembled from the carrier tape (see packaging notes).

The Module has to be picked up eccentrically in the middle of component xxx

(drawing of pick and place pattern)

The pickup tool has to be selected according to the following table:

Dimensions Outer diameter (mm)

Minimum xx.x

Recommended xx.x

Maximum xx.x

# Reflow soldering

The reflow profile shown as follows corresponds to the measurement at the soldering balls in the middle of the.

Drawing of an reflow profile

The Module may only be soldered using a reflow process as described above.

# Packaging notes

The modules are delivered in a carrier tape with a packaging unit of xxxx pieces.

The following illustration shows the carrier tape specification.

(drawing of tape or tray)

# 3 SOFTWARE

Key to success is a breadth of software support, ranging from Bootloader to Operating Systems and API support as well as for security. One of the goals of Open Standard Module™ Specification is to attract market-leaders as well as rising stars who deliver feel-good software-solutions for a broad range of applications and scopes.

All modules adhering to the Open Standard Module™ specification shall provide at least one opensource software environment including the following components:

1 Bootloader
Operating System
 APIs
■ Others

The complete open-source software environment shall be published in a joint/common open Git repository (i.e. github.com).

# 4 ACCESSORIES

# 4.1 Evaluation Carrier Board

All modules adhering to the Open Standard Module™ Specification shall utilize a standardized OSM™

Evaluation Carrier Board, providing access to all predefined features for the predefined sizes.

Ideally this Evaluation Carrier Board is designed and produced by one member of the SGET Standardization group.

# 4.2 Cooling solution

All modules adhering to the Open Standard Module™ Specification may utilize a standardized cooling interface and concept.

There will be a recommendation of a mounting hole pattern in the upcoming Design Guide.

# 5 CERTIFICATION / COMPLIANCE

All modules adhering to the Open Standard Module™ Specification shall fulfill the regional required Conformity Declarations.

# 6 APPENDIX

# 6.1 Abbreviations

<table><tr><td>Abbreviation</td><td>Description</td></tr><tr><td>SGET</td><td>Standardization Group for Embedded Technologies e.V.</td></tr><tr><td>OSB</td><td>Open Standard Module</td></tr><tr><td>PCB</td><td>Printed Circuit Board</td></tr><tr><td>LAN</td><td>Local Area Network</td></tr><tr><td>LVDS</td><td>Low Voltage Differential Signaling</td></tr><tr><td>USB</td><td>Universal Serial Bus</td></tr><tr><td>I2C</td><td>Inter Integrated Circuit Interface</td></tr><tr><td>I2S</td><td>Inter-IC Sound Interface</td></tr><tr><td>PDM</td><td>Pulse Density Modulation</td></tr><tr><td>PWM</td><td>Pulse Width Modulation</td></tr><tr><td>CAN</td><td>Controller Area Network</td></tr><tr><td>SPI</td><td>Serial Peripheral Interface</td></tr><tr><td>UART</td><td>Universal Asynchronous Receiver Transmitter</td></tr><tr><td>PCIe</td><td>Peripheral Component Interconnect Express</td></tr><tr><td>GPIO</td><td>General Purpose Input Output</td></tr><tr><td>eDP</td><td>Embedded DisplayPort</td></tr></table>

Table 57: Abbreviations

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