# PC/104-Plus Specification # Version 2.3 # October 13, 2008 # Please Note This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the PC/104 Embedded Consortium shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification. If errors are found, please notify the PC/104 Embedded Consortium. PC/104, PC/104-Plus, and PCI-104 are trademarks of the PC/104 Embedded Consortium. All other marks are the property of their respective companies. # REVISION HISTORY # Draft 0.7, November 20, 1996 - Preliminary Draft a. Formatted to meet the requirements of the PC/104 Consortium. b. Modify the component restrictions across and to each side of the PC/104 connectors (three sides, .400" from each edge, 4.35" top clearance, .100" bottom clearance). # Draft 0.8, December 16, 1996 - Cleanup for Release a. Correct general typos. b. Correct word reference error. c. Add QuickSwitch part number and clarify Mux requirements. d. Change PCI ONLY to PCI-Only and add note. e. Correct Figure 4 and Figure 5 errors. f. Correct typo in Table 3. # Draft 0.9, January 10, 1997 - Cleanup for Release a. Cleanup minor grammatical errors. # Version 1.0, February 1997 - Initial Release a. Grammatical changes and cleanup per review recommendations. b. Change Footnote 1 on Page 4 to show future support for the M66EN (66MHz Enable) signal. c. Add signals PRSNT[1:2]# and CLKRUN# to Figure 2 to encompass all unused PCI signals. d. Moved the Mechanical section after the Electrical section. e. Clarified the KEY pin usage for universal modules and defined them as ground connections. f. Clarified pin 1 for the PC/104-Plus connectors on Figure 6. g. Added an example manufacturer and part No. for the PCI connector (Figure 7) and Shroud (Figure 8). h. Modified, Table 1, and some text under Section 3.1.7 to add routing recommendations for the PCI interrupt lines INTA - INTD. # Version 1.1, June 1997 - Minor Editorial Corrections a. Correct errors in the Table of Figures and Table of Tables. b. Correct dimensions on the PCI connector (Figure 5). c. Correct part number and dimensions on the shroud (Figure 6). d. Correct general typos and update reference information. # Version 1.2, April 2001 a. Added PCI Connector Specifications and PCI-104 name for “PCI Only”. b. Added PC/104 8-Bit and 16-Bit Connector Specification. c. Removed specific company references. d. Corrected PCISIG and consortium addresses and phone numbers. # Version 2.0, November, 2003 a. Chapter 1. Introduction and contact information updated b. Chapter 2. PCI Signal Definition 1. All PCI signal names have been updated to reflect the PCI Specification Version 2.2 2. Signals SBO\* and SDONE have been removed to reflect PCI Version 2.2 3. “(Not Supported)” has been placed under the Present signal in Figure 2 4. PCI signal descriptions in section 2.1 have been updated to reflect the PCI Specification Version 2.2 5. Section 2.2 has been updated with additional figures and descriptions to help clarify the purpose for signal selection on the expansion modules. Figure 2 and Table 1 reflect the addition of a $4^{th}$ GNT# and REQ# pair to allow for a $4^{th}$ bus mastering expansion module on a PC/104-Plus stack. The “ID Address” column has been removed from table 1 since this is dependent on the PCI Host module. c. Chapter 3. Electrical Specification 1. References to PCI specification Version 2.1 have been change to PCI Specification Version 2.2 2. Section 3.2.4 “Key Locations has been eliminated. Description for the identification of the PCI signaling type has been moved to the “Mechanical Specification” chapter 3. Note 1 of Table 2 has been changed to reflect that the Host board does not need to supply 3.3V to the PCI bus if it is using 3.3V PCI signaling. As with 5V PCI signaling Host cards, it is up to the user to supply 3.3V to the stack. 4. New section on PCI Signaling Voltage (VI/O) Requirements was added. This section discusses 3.3V, 5V, and Universal Add-In Cards d. Chapter 4. Levels of Conformance 1. PCI-104 section was removed since it will be covered in its own Specification Manual e. Chapter 5. Mechanical Specifications 1. Section on clock trace lengths was added 2. A section has been added “Board Identifier” which describes how to label a board to indicate its PCI signaling voltage level capabilities. This replaces the keying of the PCI connector. f. Appendix A. Mechanical Dimensions 1. Figure 4 has been redone in AutoCAD showing both English and Metric units. The shroud keep out region was also added. So was an area for connector overhang at the lower right hand side of the ISA bus. 2. Figure 5: Note 1 “DIN 41612 Part 5” has been removed since this does not apply to the PCI connector 3. Contact finish female interface changed from 20 micoinches minimum to 15 microinches in Figures 9 & 11 4. Mechanical performance withdrawal force changed from 1 ounce minimum average to 1 ounce per pin minimum in Figures 9 & 11 g. Appendix B. Bus Signal Assignments 1. Pin B30 (Reserved) replaced with REQ3# 2. Pin C30 (Reserved) replaced with GNT3# 3. Pin C9 (SBO\*) replaced with Reserved to reflect the PCI Local Bus Specification Revision 2.2 4. Pin D10 (SDONE) replaced with Reserved to reflect the PCI Local Bus Specification Revision 2.2 5. Note 2 at the bottom of Table 3 has been removed h. Specification has been reformatted and updated 1. Chapter 2 “PCI Signal Definition” is now Chapter 3. 2. Chapter 3 “Electrical Specification” is now Chapter 4. 3. Chapter 4 “Levels of Conformance” is now Chapter 5. 4. Chapter 5 “Mechanical Specifications” is now Chapter 6. 5. Chapter 6 "Typical Stack" is now Chapter 2 # Version 2.1, November, 2006 a. Chapter 1. Introduction 1. PC/104 Embedded Consortium contact information has been updated. b. Chapter 3. PCI Signal Definition 1. Figure 4: “INTE#” corrected to “INTA#”. # Version 2.2, January, 2007 a. Figure 4. Added “complementary” to description of Rotary Switch. # Version 2.3, October 13, 2008 a. Corrected copyright and added Logo to cover b. Corrected dimensions in Figure 1. Standoff height is 0.600" (15.24mm) c. Added power management signals to Figure 2, following sections, and Table 2. d. Added +5V\_SB to Table 2 e. Added standoff mechanical drawing in Appendix C f. Fixed page numbers in TOC, TOT, and TOF # TABLE OF CONTENTS # 1. INTRODUCTION....1 1.1 SUMMARY OF KEY DIFFERENCES FROM PC/104 SPECIFICATION:....1 1.2 SUMMARY OF KEY DIFFERENCES (120-PIN PCI AND PCI LOCAL BUS SPECIFICATION) ......1 1.3 REFERENCES....2 # 2. A POSSIBLE MODULE STACK CONFIGURATION....3 # 3. PCI SIGNAL DEFINITION ....4 3.1 PCI BUS SIGNAL DESCRIPTION 5 3.1.1 Address and Data....5 3.1.2 Interface Control Pins....5 3.1.3 Error Reporting....5 3.1.4 Arbitration (Bus Masters Only)....5 3.1.5 System....6 3.1.6 Interrupts 6 3.1.7 Power Management....6 3.2 SIGNAL GROUPING 7 3.3 +5V\_SB, PSON#, AND PME#....9 # 4. ELECTRICAL SPECIFICATION......11 4.1 ISA BUSES....11 4.2 PCI BUS....11 4.2.1 Signal Definitions....11 4.2.2 Signal Assignments....11 4.2.3 Power and Ground Pins....11 4.2.4 AC/DC Signal Specifications....11 4.3 MODULE POWER REQUIREMENTS....12 4.4 PCI SIGNALING VOLTAGE (VI/O) REQUIREMENTS....12 4.4.1 PCI Host Module....12 4.4.1 PCI Host Module....12 4.4.2 Add-In Modules 12 # 5. LEVELS OF CONFORMANCE....14 5.1 PC/104-PLUS "COMPLIANT"....14 5.2 PC/104-PLUS "BUS-COMPATIBLE" 14 # 6. MECHANICAL SPECIFICATION....15 6.1 ISA CONNECTOR....15 6.2 PCI CONNECTOR 15 6.2.1 Clock Trace Lengths....15 6.2.2 Module Dimensions....15 6.2.3 Connector and Shroud....15 6.2.4 Board Identifier ....15 # APPENDICES # A. MECHANICAL DIMENSIONS ...... A-1 B. BUS SIGNAL ASSIGNMENTS ......B-1 C. STANDOFF...... C-1 # TABLE OF FIGURES FIGURE 1: A POSSIBLE MODULE STACK CONFIGURATION....3 FIGURE 2: PCI PIN LIST....4 FIGURE 3: INTERRUPT ROUTING FOR A DESKTOP PC....7 FIGURE 4: SIGNAL SELECT ON AN EXPANSION BOARD 8 FIGURE 5: INT# SELECT....9 FIGURE 6: PC/104-PLUS MODULE DIMENSIONS....A-2 FIGURE 7: PCI CONNECTOR ......A-3 FIGURE 8: PCI CONNECTOR SHROUD ......A-3 FIGURE 9: PCI CONNECTOR SPECIFICATIONS ......A-4 FIGURE 10: 8-BIT AND 16-BIT ISA CONNECTOR (REFERENCE ONLY)......A-5 FIGURE 11: 8-BIT AND 16-BIT ISA CONNECTOR SPECIFICATION (REFERENCE ONLY)......A-6 FIGURE 12: STANDOFF MECHANICAL DIMENSIONS....C-2 # TABLE OF TABLES TABLE 1: ROTARY SWITCH SETTINGS ...... 9 TABLE 2: MODULE POWER REQUIREMENTS ...... 12 TABLE 3: PCI BUS SIGNAL ASSIGNMENTS ...... B-2 TABLE 4: ISA BUS (REFERENCE ONLY) ...... B-3 # PC/104-Plus SPECIFICATION # Version 2.3 # 1. INTRODUCTION The ISA architecture bus has long been a popular choice for embedded applications. With the publication of the PC/104 standard in 1992, this bus architecture was available on a small, rugged form factor which has since become an industry standard. As technological requirements advanced, a need began to arise for a higher performance bus throughput. This is especially true when it comes to graphics devices as well as other high-speed I/O devices such as networks. The PC/104 Consortium met this challenge by incorporating a PCI bus on the PC/104 form factor, which became to be known as PC/104-Plus. This architecture provides a link to versatile legacy hardware while meeting the high-speed requirements for present and future hardware. This document supplies the mechanical and electrical specifications for the “PC/104-Plus” and incorporates all of the PC/104 features, with the added advantage of the high speed PCI bus. The physical size, mounting configuration and electrical interconnect portion of the PC/104 specification shall remain unchanged. # 1.1 Summary of Key Differences From PC/104 Specification: ■ A third connector opposite the ISA connectors supports the PCI bus. ■ The component height on the topside has been reduced from 0.435" to 0.345" and the bottom has been increased from 0.100" to 0.190" to increase the flexibility of the module. ■ Control logic added to handle the requirements for the high-speed bus. # 1.2 Summary of Key Differences (120-pin PCI and PCI Local Bus Specification) ■ The PCI bus connector is a 4x30 (120-pin) 2mm pitch stack-through connector as opposed to the 124-pin edge connector on standard 32-bit PCI Local Bus. ■ The 120-pin PCI does not support 64-bit Extensions, JTAG, PRSNT, or CLKRUN signals. # 1.3 References This document covers the addition of the PCI functions. The following documents should be used as reference for a detailed understanding of the overall system requirements: • "ISA and EISA Theory and Operation" by Edward Solari • "ISA System Architecture" by MindShare, Inc. • PC/104 Specification by PC/104 Embedded Consortium - "PCI and PCI-X Hardware and Software (Architecture and Design Library)" by Edward Solari - "PCI System Architecture" by MindShare, Inc. • PCI Local Bus Specification Revision 2.2 by PCI Special Interest Group Contact the PCI Special Interest Group office for the latest revision of the PCI specification: # PCI Special Interest Group Email: administration@pcisig.com Website: www.pcisig.com If errors are found in this document, please send a written copy of the suggested corrections to: # PC/104 Embedded Consortium E-mail: info@pc104.org Website: www.pc104.org # 2. A POSSIBLE MODULE STACK CONFIGURATION Figure 1 shows a typical module stack with two PC/104-Plus modules, one PC/104 16-bit module, and one PC/104 8-bit module. The maximum configuration for the PCI bus of PC/104-Plus modules is four plus the Host Board. If standard PC/104 modules are used in the stack, they must be the top module(s) because they will normally not include the PCI bus. Figure 1: A Possible Module Stack Configuration ![ Module Type Spacer Width (inches) Spacer Count (plcs) ------------- ------------------------ --------------------- Stackthrough 8-bit module 0.600 4 Stackthrough 16-bit module 0.600 4 Stackthrough PC/104-Plus module 0.600 4 Stackthrough PCI-104 module 0.600 4 Non-stackthrough PCI-104 module 0.600 4 ](.PC104-Plus_Specification_v2.3/b3301e26a8daf1949fc34b88f8313b46dad9954e61637f9f2c9ef0cf4f2a571b.jpg) ![0.435 in (11.05mm) 0.600 in (15.24mm)](.PC104-Plus_Specification_v2.3/8f45152593941541fa4ee93cef0186493e724392170edf35851d33d2343d5074.jpg) # 3. PCI SIGNAL DEFINITION Figure 2 shows the pins in functional groups, with the required pins on the left and the optional pins on the right side. The shaded pins on the right are unsupported features, but are included to show the entire PCI bus as defined in the PCI Local Bus Specification Revision 2.2. This version of the PCI bus is intended as a 32-bit bus running at 33MHz and therefore, 64-bit extension and 66MHz $^{1}$ are not supported at this time. Also not supported are the boundary scan features (JTAG), Present (PRSNT[1:2]#), and Clock running (CLKRUN#). The direction indication on the pins assumes a combination master/target device. Figure 2: PCI Pin List ![The diagram depicts a central block labeled **'PCI COMPLIANT DEVICE'** connected to two columns of pins: **'Required Pins'** on the left and **'Optional Pins'** on the right. All connections are bidirectional. **Required Pins (Left Column):** * **Address & Data**: `AD(31:0)`, `C/BE(3:0)#`, `PAR` * **Interface Control**: `FRAME#`, `TRDY#`, `IRDY#`, `STOP#`, `DEVSEL#`, `IDSEL` * **Error Reporting**: `PERR#`, `SERR#` * **Arbitration (master only)**: `REQ#`, `GNT#` * **System**: `CLK`, `RST#` **Optional Pins (Right Column):** * **Interface Control**: `LOCK#` * **Interrupts**: `INTA#`, `INTB#`, `INTC#`, `INTD#` * **Power Management**: `PME#`, `PS_ON#` * **64-Bit Extension (Not Supported)** (Shaded Grey): `AD(63:32)`, `C/BE(7:4)#`, `PAR64`, `REQ64#`, `ACK64#` * **JTAG (Not Supported)** (Shaded Grey): `TDI`, `TDO`, `TCK`, `TMS`, `TRST#` * **Clock Running (Not Supported)** (Shaded Grey): `CLKRUN#` * **Present (Not Supported)** (Shaded Grey): `PRSNT(1:2)#` * **66MHz Enable**: `M66EN¹`](.PC104-Plus_Specification_v2.3/266f6ae756ec115cb71e3711c89210230f64b7156062164346540fb0f3237993.jpg) # 3.1 PCI Bus Signal Description # 3.1.1 Address and Data
AD[31:00]Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases.
C/BE[3:0]\#Bus Command/Byte Enables are multiplexed. During the address phase of a transaction, they define the bus command. During the data phase, they are used as byte enables.
PARParity is even parity across AD[31:00] and C/BE[3:0]\#. Parity generation is required by all PCI signals.
# 3.1.2 Interface Control Pins
FRAME#Cycle Frame is driven by the current master to indicate the beginning of an access and will remain active until the final data cycle.
TRDY#Target Ready indicates the selected device's ability to complete the current data phase of the transaction. Both IRDY# and TRDY# must be asserted to terminate a data cycle.
IRDY#Initiator Ready indicates the bus master's ability to complete the current data phase of the transaction.
STOP#Stop indicates the current selected device is requesting the master to stop the current transaction.
DEVSEL#Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access.
IDSELInitialization Device Select is used as a chip-select during configuration read and write transactions.
LOCK#Lock indicates an atomic operation to a bridge that may require multiple transactions to complete.
# 3.1.3 Error Reporting
PERR#Parity Error is for reporting data parity errors.
SERR#System Error is for reporting address parity errors.
# 3.1.4 Arbitration (Bus Masters Only)
REQ#Request indicates to the arbitrator that this device desires use of the bus.
GNT#Grant indicates to the requesting device that access has been granted.
# 3.1.5 System CLK Clock provides timing for all transactions on the PCI bus and is an input to every PCI device. RST# Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. M66EN 66 MHz Enable indicates to a device whether the bus segment is operating at 33 MHz or 66 MHz. The PCI bus has been simulated at 33MHz. For the purpose of this specification, 66MHz is not supported. To support future enhancements, the M66EN signal should be grounded on any module that cannot support 66MHz and left open for modules that can support a 66MHz clock. # 3.1.6 Interrupts INTA# Interrupt A is used to request Interrupts. INTB# Interrupt B is used to request Interrupts. INTC# Interrupt C is used to request Interrupts. INTD# Interrupt D is used to request Interrupts. # 3.1.7 Power Management PME# Power Management Event is used to bring the CPU out of power down states such as wake-on-LAN. PSON# Power Supply On is a power supple control signal that can turn the power supply on or off. +5V\_SB +5 Volt Standby is a power source that is always present when main power is supplied to the system. # 3.2 Signal Grouping The PC/104-Plus architecture was developed to take advantage of the versatility and simplicity of the PC market for embedded applications. Like the desktop PC, PC/104-Plus has the ability to add auxiliary boards to expand the capabilities of the CPU. But instead of using slot cards, PC/104-Plus adds additional modules using stack-through connectors. This has two advantages: it reduces the system size and it makes the system more rugged so that it can better withstand shocks and vibrations. To realize a stack-through architecture, a means of selecting the appropriate signals for each expansion card must be established that will easily allow for the installation and configuration of add-in PC/104-Plus and PCI-104 modules. The signals in question include the CLKx, IDSELx, REQx#, GNTx#, and INTx# lines. Normal desktop computers overcome this problem by routing only the necessary signals to each of the slot connectors. For example, on a desktop PC, only CLK1, IDSEL1, REQ1#, and GNT1# are routed to PCI slot 1. Likewise, CLK2, IDSEL2, REQ2#, and GNT2# are routed to slot 2. The interrupts on a desktop PC are handled in a different manner. All four interrupts from the interrupt controller are routed to each PCI slot connector. By convention INTA# on an expansion card is used for single-function devices and the remaining interrupts are used in the case of multi-functional devices. This could place a large burden on INTA# since all of the expansion cards would use this interrupt. To alleviate the burden, PC manufacturers stagger the interrupts on the motherboard to each of the PCI connectors. This is shown in Figure 3. Figure 3: Interrupt routing for a desktop PC ![The image displays a block diagram illustrating signal routing on a motherboard and connections for PCI slotboards. **Labeled Blocks and Contents:** * **Motherboard** (Large outer box containing): * **PCI Host**: Contains labels INTW#, INTX#, INTY#, INTZ#. * **PCI Connector 1**: Contains labels INTA#, INTB#, INTC#, INTD#. * **PCI Connector 2**: Contains labels INTA#, INTB#, INTC#, INTD#. * **PCI Connector 3**: Contains labels INTA#, INTB#, INTC#, INTD#. * **PCI Slotboard 1**: * Left side connections: INTA#, INTB#, INTC#, INTD#. * Right side block: INTA#, INTB#, INTC#, INTD#. * **PCI Slotboard 2**: * Left side connections: INTA#, INTB#, INTC#, INTD#. * Right side block: INTQA, INTB#, INTC#, INTD#. **Connections:** * **PCI Host to PCI Connector 1**: * INTW# connects to INTA#. * INTX# connects to INTB#. * INTY# connects to INTC#. * INTZ# connects to INTD#. * **PCI Connector 1 to PCI Connector 2**: * A line labeled **INTX#** connects the INTB# output of Connector 1 to the INTA# input of Connector 2. * A line labeled **INTY#** connects the INTC# output of Connector 1 to the INTB# input of Connector 2. * A line labeled **INTZ#** connects the INTD# output of Connector 1 to the INTC# input of Connector 2. * A line labeled **INTW#** connects the INTA# output of Connector 1 to the INTD# input of Connector 2. * **PCI Connector 2 to PCI Connector 3**: * A line labeled **INTY#** connects the INTC# output of Connector 2 to the INTA# input of Connector 3. * A line labeled **INTZ#** connects the INTB# output of Connector 2 to the INTB# input of Connector 3. * A line labeled **INTW#** connects the INTA# output of Connector 2 to the INTC# input of Connector 3. * A line labeled **INTX#** connects the INTD# output of Connector 2 to the INTD# input of Connector 3. * **PCI Slotboard Connections**: * Lines labeled INTA#, INTB#, INTC#, INTD# connect the left side to the right side for both Slotboard 1 and Slotboard 2. * Dashed arrows point left next to both Slotboard structures.](.PC104-Plus_Specification_v2.3/2a5d29d5558a1d3d94ac6115564dd0b65433b75598b3cd965beb06247718fdc2.jpg) Since PC/104-Plus is a stack-through architecture, there is only one connector to which all of the expansion boards must connect. A means of selecting the appropriate signals must be established that will easily allow for the installation and configuration of add-in PC/104-Plus and PCI-104 modules. Figure 4 shows such a method that can be applied to the expansion boards. Figure 4: Signal Select on an Expansion Board ![The diagram displays three multiplexer blocks and a control switch, all interconnected. **Labeled Blocks:** 1. **Left Block:** Labeled '**DUAL 4 TO 1 MUX**'. * **Inputs:** '**CLK0**' (0), '**CLK1**' (1), '**CLK2**' (2), '**CLK3**' (3) and '**IDSEL0**' (0), '**IDSEL1**' (1), '**IDSEL2**' (2), '**IDSEL3**' (3). * **Outputs:** '**CLK**', '**IDSEL**'. * **Control:** '**A0**', '**A1**', '**EN#**' (connected to ground). 2. **Middle Block (enclosed in dashed box):** Labeled '**DUAL 4 TO 1 MUX**'. * **Inputs:** '**REQ0#**' (0), '**REQ1#**' (1), '**REQ2#**' (2), '**REQ3#**' (3) and '**GNT0#**' (0), '**GNT1#**' (1), '**GNT2#**' (2), '**GNT3#**' (3). * **Outputs:** '**REQ#**', '**GNT#**'. * **Control:** '**A0**', '**A1**', '**EN#**' (connected to ground). * **Text:** '**This Mux is Only Required for Bus Masters**'. 3. **Right Block (enclosed in dashed box):** Labeled '**DUAL 4 TO 1 MUX**'. * **Inputs:** '**INTA#**' (0), '**INTB#**' (1), '**INTC#**' (2), '**INTD#**' (3) and '**INTB#**' (0), '**INTC#**' (1), '**INTD#**' (2), '**INTA#**' (3). * **Outputs:** '**INT0#**', '**INT1#**'. * **Control:** '**A0**', '**A1**', '**EN#**' (connected to ground). * **Text:** '**1 or 2 Muxes are recommended for INTA Routing. See Table 1 for routing of INT2# and INT3#.**' 4. **Switch:** Labeled '**Complementary Rotary Switch**'. * **Pins:** Labeled '**C**', '**1**', '**2**', '**3**', '**4**', '**5**', '**6**', '**7**', '**0**'. **Connections:** * **Control Lines:** The '**A0**' line connects pin '**1**' of the switch to the '**A0**' input of all three MUXes. The '**A1**' line connects pin '**2**' of the switch to the '**A1**' input of all three MUXes. * **Enable/Power:** The '**EN#**' input of all three MUXes is connected to ground. Pin '**C**' of the switch is connected to ground. Resistors connect the '**A0**' and '**A1**' lines to '**vcc**'. * **Signal Paths:** There are no direct signal connections between the inputs/outputs of the three MUX blocks; they function as separate signal routing paths controlled by the shared A0/A1 lines.](.PC104-Plus_Specification_v2.3/8c484fe5fa0b6d6d235fd6efeacf40973566f9d21fc5e7187ebf45d5b4205581.jpg) The multiplexer chips on the expansion board serve as the equivalent of having multiple PCI slot connectors on the motherboard of a desktop PC. To select the appropriate REQ#, GNT#, CLK, and INT signals for the expansion module, the rotary switch must be adjusted for the position on the stack. For expansion modules requiring more than one interrupt, the staggering of the INTx# lines is accomplished on the expansion module prior to the multiplexers. Figure 5 shows the interrupt routing on a PCI Host Module and on an expansion module with two functions. The Add-on Module portion of Figure 5 shows how the right-hand multiplexer of Figure 4 fits onto an add-on module. If a board has a single function then only half of the multiplexer is required. Figure 5: INT# Select ![This diagram depicts a block diagram labeled at the bottom center as **PCI Host Module**. It contains two main internal components connected by four horizontal lines: 1. **Left Block:** A square block labeled below as **PCI Host**. Inside, from top to bottom, are the labels: * **INTW#** * **INTX#** * **INTY#** * **INTZ#** 2. **Right Block:** A tall, vertical rectangular block labeled below as **PCI Conn.** Inside, aligned horizontally with the left block's labels, are: * **INTA#** * **INTB#** * **INTC#** * **INTD#** **Connections:** Four parallel lines connect the two blocks in a 1-to-1 mapping: * **INTW#** connects to **INTA#** * **INTX#** connects to **INTB#** * **INTY#** connects to **INTC#** * **INTZ#** connects to **INTD#**](.PC104-Plus_Specification_v2.3/1395ab658171d76825dd8b8fba40a5c22ee25bc793802b62612beee21a036fb3.jpg) ![The diagram illustrates an **Add-on Module** contained within a large outer rectangle. Inside this module are three main blocks: 1. **PCI Device** (Left Block): * This block has two lines extending from its right side labeled **INT0#** (top) and **INT1#** (bottom). * These lines connect to the left side of the central block. 2. **Dual 4 to 1 MUX** (Center Block): * This block receives the **INT0#** and **INT1#** lines on its left side. * On its right side, there are two sets of labels: * Top set: **INTA#**, **INTB#**, **INTC#**, **INTD#**. * Bottom set: **INTB#**, **INTC#**, **INTD#**, **INTA#**. 3. **PCI Conn.** (Right Block): * This block has labels on its left side: **INTA#**, **INTB#**, **INTC#**, **INTD#**. **Connections:** * Lines connect the labels on the right side of the **Dual 4 to 1 MUX** to the corresponding labels in the **PCI Conn.** block. * The top set of MUX labels (**INTA#**, **INTB#**, **INTC#**, **INTD#**) connects directly to the matching **PCI Conn.** labels. * The bottom set of MUX labels also connects to the same lines going to the **PCI Conn.** block. Specifically: * The bottom **INTB#** connects to the **INTB#** line. * The bottom **INTC#** connects to the **INTC#** line. * The bottom **INTD#** connects to the **INTD#** line. * The bottom **INTA#** connects to the **INTA#** line. * These connections are marked with dots, indicating that the signals are joined at these points.](.PC104-Plus_Specification_v2.3/c2d9ff09936643e7bb9ded66157469300d9ce2eae59595283e4268b23b6eb2da.jpg) The multiplexer chips are Dual 4:1 Mux/Demux chips. They provide a 5Ω switch that connects the input and output together. These switches provide a bi-directional path with no signal propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. This is typically 250ps at 50pF load. Use one Mux for 1 to 2 interrupts or two Muxes for 3 to 4 interrupts. While other methods of configuring the modules are possible and permissible, the rotary switch is clean and provides for the least possible error in configuration. Table 1 shows the appropriate switch setting and signals used for each module in the stack. Table 1: Rotary Switch Settings
Switch PositionModule SlotREQ#GNT#CLKINT0#INT1#INT2#INT3#
0 or 41REQ0#GNT0#CLK0INTA#INTB#INTC#INTD#
1 or 52REQ1#GNT1#CLK1INTB#INTC#INTD#INTA#
2 or 63REQ2#GNT2#CLK2INTC#INTD#INTA#INTB#
3 or 74REQ3#GNT3#CLK3INTD#INTA#INTB#INTC#
# 3.3 +5V\_SB, PSON#, and PME# To support ATX power supplies and power down features three signals have been added to the PCI bus. They are +5V\_SB which is a power source that is always present when main power is supplied to the system, PSON# which is a power supply control signal that can turn the power supple on or off, and PME# which can be used to bring the CPU out of power down states such as wake-on-LAN. These signals have been implemented on the reserved pins of the PCI expansion bus of the PC/104-Plus and PCI-104 Specifications at pins B1, C9, and D10. Not all manufacturers will implement these signals; therefore to maintain compatibility with existing products it is important for designs that implement these functions to protect against undriven inputs. # 4. ELECTRICAL SPECIFICATION # 4.1 ISA Buses The electrical specifications for the 8-bit and 16-bit ISA buses for bus drive current, bus termination, pullup/pulldown resistors, etc. are unchanged and are defined in the PC/104 Specification. The signal assignments for the J1/P1 and J2/P2 connector are given in Appendix B, Table 4: ISA Bus (Reference Only). # 4.2 PCI Bus The PCI Bus mechanical interface is a stackable 4x30 header. This interface carries all of the required PCI signals per PCI Local Bus Specification Revision 2.2. # 4.2.1 Signal Definitions For full details on the electrical requirements for the PCI bus, reference the PCI Local Bus Specification Revision 2.2. # 4.2.2 Signal Assignments Signals are assigned in the same relative order as in the PCI Local Bus Specification Revision 2.2, but transformed to the corresponding header connector pins. Because of the stack-through nature of the bus, slot-specific signals are duplicated for each plug-in module. The system has been designed to accommodate 4 modules, which are PC/104-Plus, PCI-104, or a combination of the two, so multiple sets of the signals have been duplicated to accommodate one signal for each module. These four signal groups include: IDSEL[3:0], CLK[3:0], REQ#[3:0], GNT#[3:0]. Signal assignments for the J3/P3 connector are given in Appendix B, Table 3: PCI Bus Signal Assignments. # 4.2.3 Power and Ground Pins The total number of power and ground signals remains the same, but the +3.3 V pins have been reduced by two and the ground pins have been increased by two. The change was the result of signal grouping on the bus and has no effect on performance or integrity. # 4.2.4 AC/DC Signal Specifications All bus timing and signal levels are identical to the PCI Local Bus Specification Revision 2.2. # 4.3 Module Power Requirements Table 2 specifies the voltage and maximum power requirements for each PC/104-Plus module. Care should be used in designing PC/104-Plus modules to guarantee the least possible power consumption. A worst case module as specified could use almost 39 Watts of power, which would be unacceptable in most systems. Table 2: Module Power Requirements
SupplyMin. VoltageMax. VoltageMax. CurrentMax. Power
$+3.3V^1$ 3.003.603A10.8W
+5V4.755.252A10.5W
+12V11.412.61A12.6W
-5V-5.25-4.750.2A1.05W
-12V-12.6-11.40.3A3.78W
+5V_SB4.755.251.0A5W
Note 1: Host Boards implementing “5 volt PCI signaling” are not required to supply 3.3 volts to the modules, but must provide a bus and decoupling. Host Boards implementing “3.3 volt PCI signaling” are not required to supply 5 volts to the modules, but must provide a bus and decoupling. # 4.4 PCI Signaling Voltage (VI/O) Requirements # 4.4.1 PCI Host Module The PCI Host board will always determine the PCI signaling level on the bus by setting all VI/O pins to either 3.3V or 5V. If VI/O is set to 3.3V, then the system will use 3.3V I/O signaling and, likewise, if VI/O is set to 5V, then the system will use 5V I/O signaling. Some PCI host modules may only allow one of the options, while others may provide a jumper to allow the user to select the signaling level. Once the signaling level is selected, the remaining boards in the system must use that signaling level. # 4.4.2 Add-In Modules Add-in cards can be 3.3V, 5V, or universal. # 3.3V Add-In Modules 3.3V add-in modules operate in environments where VI/O has been set to 3.3V by the host module. Using 5V add-in modules on a 3.3V stack will result in the 3.3V modules being damaged. # 5V Add-In Modules 5V add-in modules operate in environments where VI/O has been set to 5V by the host module. Using 3.3V add-in modules on a 5V stack will result in the 3.3V modules being damaged. # Universal Add-In Modules Universal add-in board can be used on either 3V or 5V I/O signaling buses. Universal boards either use the VI/O signal to determine its signaling level or are 3V signaling boards that have 5V-tolerant I/O. Many PCI interface chips have a "VI/O" pin that is the power for the I/O buffers that can be directly connected to VI/O. Universal boards will work on either 3V or 5V I/O signaling buses. # 5. LEVELS OF CONFORMANCE This section provides terminology intended to assist manufacturers and users of PC/104-Plus bus-compatible products in defining and specifying conformance with the PC/104-Plus Specification. # 5.1 PC/104-Plus "Compliant" This refers to "PC/104-Plus form-factor" devices that conform to all non-optional aspects of the PC/104-Plus Specification, including both mechanical and electrical specifications. # 5.2 PC/104-Plus "Bus-compatible" This refers to devices which are not "PC/104-Plus form-factor" (i.e., do not comply with the module dimensions of the PC/104-Plus Specification), but provide male or female PC/104-Plus bus connectors that meets both the mechanical and electrical specifications provided for the PC/104-Plus bus connectors. # 6. MECHANICAL SPECIFICATION # 6.1 ISA Connector The mechanical specifications for the ISA bus are defined in the PC/104 Specification. The connector and its placement on the PC/104-Plus module is shown in Figures 6, 10, and 11. Details on the ISA bus can be found in the PC/104 Specification. # 6.2 PCI Connector # 6.2.1 Clock Trace Lengths The clocks are tuned on the Host Board such that the length of CLK3 trace is $\approx0.662"$ less than CLK2, CLK2 trace is $\approx0.662"$ less than CLK1, and CLK1 trace is $\approx0.662"$ less than CLK0. Therefore, the first module on the stack must select CLK0 (the longest trace), the second CLK1, etc. This provides almost no clock skew between modules. Trace length limits are as indicated in the PCI Local Bus Specification Revision 2.2. # 6.2.2 Module Dimensions The mechanical dimensions for this module are identical to PC/104 Specification with the exception of the added connector (J3), some modifications to the I/O connector area, and changes to the component height restrictions. The component height on the topside has been reduced from 0.435" to 0.345" and the bottom has been increased from 0.100" to 0.190". Exceptions are the three regions on the sides of the module (indicated by the dotted region in Figure 6) which have a maximum height of 0.435" for the topside and 0.100" for the bottom side. The mechanical dimensions and restrictions are given in Appendix A, Figure 6: PC/104-Plus Module Dimensions. # 6.2.3 Connector and Shroud The connector for the PCI bus is a 4x30 (120-pin) 2mm pitch connector. The shroud should be installed on the bottom of the PC board when a stack-through connector is used. The mechanical dimensions and restrictions for the PCI connector are given in Appendix A, Figure 7: PCI Connector and Figure 8: PCI Connector Shroud. The shroud should be properly marked to identify the PCI signaling capability of the board (see Section 6.2.4 Board Identifier). # 6.2.4 Board Identifier Manufacturers of PC/104-Plus modules must clearly label near or on the PCI connector the module's PCI signaling capabilities. The label is to guarantee proper module installation. Depending on the type of board manufactured, the label will be one of the following: 3.3V only 5V only Universal # APPENDIX A # MECHANICAL DIMENSIONS Figure 6: PC/104-Plus Module Dimensions Dimensions are in inches / (millimeters) ![ Component Dimension (mm) :--- :--- Top Clearance .345 (8.76) Bottom Clearance .190 (4.83) Dotted Area (3 Sides) .435 (11.05) Bottom Clearance .100 (2.54) Unshaded Area J1 J2 J3 .079 (2.0) J4 .075 (2.0) J5 .079 (2.0) J6 .075 (2.0) J7 .075 (2.0) J8 .075 (2.0) J9 .075 (2.0) J10 .075 (2.0) J11 .075 (2.0) J12 .075 (2.0) J13 .075 (2.0) J14 .075 (2.0) J15 .075 (2.0) J16 .075 (2.0) J17 .075 (2.0) J18 .075 (2.0) J19 .075 (2.0) J20 .075 (2.0) J21 .075 (2.0) J22 .075 (2.0) J23 .075 (2.0) J24 .075 (2.0) J25 .075 (2.0) J26 .075 (2.0) J27 .075 (2.0) J28 .075 (2.0) J29 .075 (2.0) J30 .075 (2.0) J31 .075 (2.0) J32 .075 (2.0) J33 .075 (2.0) J34 .075 (2.0) J35 .075 (2.0) J36 .075 (2.0) J37 .075 (2.0) J38 .075 (2.0) J39 .075 (2.0) J40 .075 (2.0) J41 .075 (2.0) J42 .075 (2.0) J43 .075 (2.0) J44 .075 (2.0) J45 .075 (2.0) J46 .075 (2.0) J47 .075 (2.0) J48 .075 (2.0) J49 .075 (2.0) J50 .075 (2.0) J51 .075 (2.0) J52 .075 (2.0) J53 .075 (2.0) J54 .075 (2.0) J55 .075 (2.0) J56 .075 (2.0) J57 .075 (2.0) J58 .075 (2.0) J59 .075 (2.0) J60 .075 (2.0) J61 .075 (2.0) J62 .075 (2.0) J63 .075 (2.0) J64 .075 (2.0) J65 .075 (2.0) J66 .075 (2.0) J67 .075 (2.0) J68 .075 (2.0) J69 .075 (2.0) J70 .075 (2.0) J71 .075 (2.0) J72 .075 (2.0) J73 .075 (2.0) J74 .075 (2.0) J75 .075 (2.0) J76 .075 (2.0) J77 .075 (2.0) J78 .075 (2.0) J79 .075 (2.0) J80 -12.7( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12.7)( -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12,( ) , (-1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 3, 4, 6, 8, 9, 11, 13, 14, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 3, 4, 6, 8, 9, 11, 3, 4, 6, 8, 9, 11,( ) , (-3, 3, 4, 6, 8, 9, 11,( ) , (-3, 3, 4, 6, 8, 9, 11,( ) , (-3, 3, 4, 6, 8, 9,( ) , (-3, 3, 4, 6, 8,( ) , (-3, 3, 4, 6,( ) , (-3, 3, 4, 6,( ) , (-3, 3, 4, 6,( ) , (-3, 3, 4( ) , (-3, 3( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3, 4( ) , (-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-3),(-4).](.PC104-Plus_Specification_v2.3/af718940fad5fbff531545fedbdf4f358e8ab753f1b00a1c14955819da8039d6.jpg) ![ Dimension Value ----------------- ------- Max Component Height .345 Max Component Height .190 Connector Shroud (value not labeled) ](.PC104-Plus_Specification_v2.3/21fd171cf3c16810c3b7013837fa3f643729ba10c560031cb05c3b6acb579484.jpg) Figure 7: PCI Connector NOTES: 1 PRESS FIT COMPLIANT PINS PER IEC 352-5 CAN BE USED INSTEAD OF SQUARE PINS AS SHOWN. 2 CONFIGURATION CAN BE MADE OF ONE OR MORE PIECES. ![ Dimension Value --------- --------- Length 2.374 ± .010 (60.30 ± .25) Width 2.283 (58.00) Height .0787 (2.00) Top Margin .0787 (2.00) Bottom Margin .1575 (4.00) Bottom Margin .2362 (6.00) Bottom Margin .315 ± .010 (8.00 ± .25) ](.PC104-Plus_Specification_v2.3/19855d39f4582198414861d5320315f5a59b3f148384e4365fbafb65f9c2553b.jpg) ![Pure electrical circuit lines without any symbols](.PC104-Plus_Specification_v2.3/ec16c600f4f96e5fcc77a0573c068d7d7f8cdd5f8f6d0e7c28b608c2850643a9.jpg) ![SOLDER RINGS, IF USED, MUST NOT PROJECT BEYOND THE .368 BASE OUTLINE. .368 ±.010 (9.35 ±.25) .103 (2.62) .198 (5.03) PIN INSERTION .090 (2.29) .472 (11.99) .020 (.50) SQ ±.001 (.0254)](.PC104-Plus_Specification_v2.3/32e04dc86ebf6cf393c5cfba3dbb258352fcb84fb7a465379eecee02ef9a6740.jpg) Figure 8: PCI Connector Shroud NOTE: ![The image features a black outline of a triangle against a white background. Centered inside the shape is the number '1'.](.PC104-Plus_Specification_v2.3/963d456dd5a6ceea12d95c165bec20bb61233936c700882efc07ae180537e16c.jpg) LOCKING PEGS ARE NOT REQUIRED IF THE SHROUD IS PRESS FIT ONTO THE LONG CONNECTOR PINS OR OTHERWISE SECURED. ![2.494 (63.35) .0787 (2.00) TYP .335 (8.51) .310 (7.87) .123 (3.12) 2.400 (60.96) 2.530 ±.010 (64.26 ±.25) φ.062 (1.57) .012 (.30) R .090 (2.29) .218 (5.54) .287 (7.29) .440 ±.010 (11.18 ±.25)](.PC104-Plus_Specification_v2.3/ae99ff854c939660051c9d703d4adc98dd2bb4e1a346c654fc0fce68b3ec6338.jpg) # Figure 9: PCI Connector Specifications # MATERIALS Housing: Contact: Solder: Solder Clip: High Temp Thermoplastic, UL Rated 94-V0 Phosphor Bronze Tin-Lead (63-37), If Applicable Aluminum Alloy, If Applicable # CONTACT FINISH Female Interface: Male Interface: Solder Tail: Underplate: 15 Microinches Minimum Hard Gold Gold Flash Minimum 100 Microinches Minimum Solder 50 Microinches Minimum Nickel # MECHANICAL PERFORMANCE Insertion Force: Withdrawal Force: Normal Force: Durability: Operating Temp: 2.5 Ounce Per Pin Maximum 1 Ounce Per Pin Minimum 50 Grams Minimum (Per Beam) 50 Cycles Minimum -55°C To +85°C Minimum # ELECTRICAL PERFORMANCE Contact Resistance: Current Capacity: Dielectric Strength: Insulation Resistance: <30 Milliohms Maximum 1 Amp Continuous Per Pin 500 Vac 5,000 Megohms Minimum Figure 10: 8-Bit and 16-Bit ISA Connector (Reference Only) NOTES: ![A vertical black line appears on the far left. To its right is a triangle containing the number 1.](.PC104-Plus_Specification_v2.3/2012084986d1861346e68189cf5dbdf77fff844bebd13ed8e31196b788df823f.jpg) PRESS FIT COMPLIANT PINS PER DIN 41612 PART 5 AND IEC 352-5 CAN BE USED INSTEAD OF SQUARE PINS AS SHOWN. 2 CONFIGURATION CAN BE MADE OF ONE OR MORE PIECES. ![.195 (4.95) .435 ±.010 (11.05 ±.25) .140 (3.56) .260 (6.60) PIN INSERTION SOLDER RINGS, IF USED, MUST NOT PROJECT BEYOND THE .435 BASE OUTLINE. .090 (2.29) .480 (12.19) .025 (0.64) SQ ±.001 (.0254) .100 (2.54)](.PC104-Plus_Specification_v2.3/2fa1f866e39c2fddad5b43434a68dfcf9a73e3921c69d9128f2d8a9ab6d78fcc.jpg) ![ Dimension Value --------- --------- Top Row .100 (2.54) Middle Row 3.220 ±.010 (81.79 ±.25) Bottom Row .800 (20.32) Bottom Row .800 (20.32) Bottom Row 2.820 (71.63) Middle Row 1.900 (48.26) Middle Row .400 (10.16) Top Row .100 (2.54) Middle Row 3.220 ±.010 (81.79 ±.25) Bottom Row .800 (20.32) Bottom Row .800 (20.32) Bottom Row 2.820 (71.63) Middle Row 3.95 ±.010 (10.03 ±.25) Top Row .195 (4.95) Middle Row .395 ±.010 (10.03 ±.25) Bottom Row .06 (1.52) ](.PC104-Plus_Specification_v2.3/beff53d7a21954b5789c76a7bdf657c5bb0cdb37eebeff1da006031501994f99.jpg) # Figure 11: 8-Bit and 16-Bit ISA Connector Specification (Reference Only) # MATERIALS Housing: Contact: Solder: Solder Clip: High Temp Thermoplastic, UL Rated 94-V0 Phosphor Bronze Tin-Lead (63-37), If Applicable Aluminum Alloy, If Applicable # CONTACT FINISH Female Interface: Male Interface: Solder Tail: Underplate: 15 Microinches Minimum Hard Gold Gold Flash Minimum 100 Microinches Minimum Solder 50 Microinches Minimum Nickel # MECHANICAL PERFORMANCE Insertion Force: Withdrawal Force: Normal Force: Durability: Operating Temp: 3.5 Ounce Per Pin Maximum 1 Ounce Per Pin Minimum 50 Grams Minimum (Per Beam) 50 Cycles Minimum -55°C To +85°C Minimum # ELECTRICAL PERFORMANCE Contact Resistance: Current Capacity: Dielectric Strength: Insulation Resistance: <30 Milliohms Maximum 1 Amp Continuous Per Pin 1000 Vac 5,000 Megohms Minimum # APPENDIX B # BUS SIGNAL ASSIGNMENTS Table 3: PCI Bus Signal Assignments <table>J3/P3PinABCD1GND+5V_SB+5VAD002VI/OAD02AD01+5V3AD05GNDAD04AD034C/BE0#AD07GNDAD065GNDAD09AD08GND6AD11VI/OAD10M66EN7AD14AD13GNDAD128+3.3VC/BE1#AD15+3.3V9SERR#GNDPSON#PAR10GNDPERR#+3.3VPME#11STOP#+3.3VLOCK#GND12+3.3VTRDY#GNDDEVSEL#13FRAME#GNDIRDY#+3.3V14GNDAD16+3.3VC/BE2#15AD18+3.3VAD17GND16AD21AD20GNDAD1917+3.3VAD23AD22+3.3V18IDSEL0GNDIDSEL1IDSEL219AD24C/BE3#VI/OIDSEL320GNDAD26AD25GND21AD29+5VAD28AD2722+5VAD30GNDAD3123REQ0#GNDREQ1#VI/O24GNDREQ2#+5VGNT0#25GNT1#VI/OGNT2#GND26+5VCLK0GNDCLK127CLK2+5VCLK3GND28GNDINTD#+5VRST#29+12VINTA#INTB#INTC#30-12VREQ3#GNT3#GND Note: 1. The shaded area denotes power or ground signals. Table 4: ISA Bus (Reference Only)
J2/P2
PinRow DRow C
0GNDGND
1MEMCS16*SBHE*
2IOCS16*LA23
3IRQ10LA22
4IRQ11LA21
5IRQ12LA20
6IRQ15LA19
7IRQ14LA18
8DACK0*LA17
9DRQ0MEMR*
10DACK5*MEMW*
11DRQ5SD8
12DACK6*SD9
13DRQ6SD10
14DACK7*SD11
15DRQ7SD12
16+5VSD13
17MASTER16*SD14
18GNDSD15
19GNDKEY
J1/P1
PinRow ARow B
1IOCHK*GND
2SD7RESET
3SD6+5V
4SD5IRQ9
5SD4-5V
6SD3DRQ2
7SD2-12V
8SD1SRDY*
9SD0+12V
10IOCHRDYKEY
11AENSMEMW*
12SA19SMEMR*
13SA18IOW*
14SA17IOR*
15SA16DACK3*
16SA15DRQ3
17SA14DACK1*
18SA13DRQ1
19SA12REFRESH*
20SA11BCLK
21SA10IRQ7
22SA9IRQ6
23SA8IRQ5
24SA7IRQ4
25SA6IRQ3
26SA5DACK2*
27SA4TC
28SA3BALE
29SA2+5V
30SA1OSC
31SA0GND
32GNDGND
# APPENDIX C Standoff Standoffs are used to ensure stacked boards retain their connectivity. The standoffs are preferably made from stainless-steel to provide for maximum strength and height tolerance. Pads must be provided for the standoffs, with the same plating as the pads for the connectors. All critical dimensions are listed. It is up to the user to define the thread typed. The height of the standoff shall be 0.600” +/- 0.005”. The width of the standoff must be able to fit on the Standoff pad called out on the Board Layout & Dimensions Section. The width of the threaded section must be able to fit into the standoff pad hole called out in the Board Layout & Dimensions Section. Figure 12: Standoff Mechanical Dimensions ![0.600 ± 0.005 inches (15.24 ± 0.127 mm) ( 0.250 inches (( 6.350 mm) ( 0.125 inches (( 3.175 mm)](.PC104-Plus_Specification_v2.3/042cbe754d8f01b1676fc2680b847b08e622399b5b22e21ce3fd400fdec0ed9b.jpg) [🔗 Link to the original document](.PC104-Plus_Specification_v2.3/PC104-Plus_Specification_v2.3.pdf)