# PCI/104-Express™ # & # PCIe/104™ # Specification # Including Adoption on 104™, EPIC™ and EBX™ Form Factors Version 1.0 March 24, 2008 # Please Note This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the PC/104 Embedded Consortium shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification. If errors are found, please notify the PC/104 Embedded Consortium. The PC/104 logo, PC/104, PC/104-Plus, PCI-104, PCIe/104, PCI/104-Express, 104, EPIC and EBX are trademarks of the PC/104 Embedded Consortium. All other marks are the property of their respective companies. Copyright 2007 - 2008, PC/104 Embedded Consortium # IMPORTANT INFORMATION AND DISCLAIMERS The PC/104 Embedded Consortium (“Consortium”) makes no warranties with regard to this PCI/104- Express and PCIe/104 Specifications (“Specifications”) and, in particular, neither warrant nor represent that these Specifications or any products made in conformance with them will work in the intended manner. Nor does the Consortium assume responsibility for any errors that the Specifications may contain or have any liabilities or obligations for damages including, but not limited to, special, incidental, indirect, punitive, or consequential damages whether arising from or in connection with the use of these Specifications in any way. This specification is subject to change without notice. While every effort has been made to ensure the accuracy of the material contained within this document, the publishers shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this specification. If errors are found, please notify the publishers. No representations or warranties are made that any product based in whole or part on these Specifications will be free from defects or safe for use for its intended purposes. Any person making, using, or selling such product does so at his or her own risk. The user of these Specifications hereby expressly acknowledges that the Specifications are provided as is, and that the Consortium make no representations, or extends any warranties of any kind, either express or implied, oral, or written, including any warranty of merchantability or fitness for a particular purpose, or warranty or representation that the Specifications or any product or technology utilizing the Specifications or any subset of the Specifications will be free from any claims of infringement of any intellectual property, including patents, copyright and trade secrets nor does the Consortium assume any responsibilities whatsoever with respect to the Specifications or such products. # TRADEMARKS AND COPYRIGHTS The PC/104 logo, PC/104, PC/104-Plus, PCI-104, PCI/104-Express, PCIe/104, 104, EPIC, and EBX are trademarks of the PC/104 Embedded Consortium. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PS/2, PC/XT, PC/AT and IBM are trademarks of International Business Machines Inc. Information regarding the traditional stackable PCI bus found on in the PC/104-Plus and PCI-104 specifications is the property of the PC/104 Embedded Consortium. All other trademarks are the property of their respective companies. # REVISION HISTORY March 21, 2008 \- Initial release Version 1.0 # TABLE OF CONTENTS # 1. INTRODUCTION. 1.1. Purpose .... 1.2. Standard Identification.. 1.3. Description... 1.4. Bus and Signal Group Descriptions.. 3 1.4.1 PCI Express Expansion Bus.. 3 1.4.2 SDVO Links . 1.4.3 PCI Expansion Bus .. 1.4.4 System Management Bus... 1.4.5 ATX and Power Management.. .4 1.5. References.. . 4 # 2. EXPANSION CONNECTOR A .. .. 6 2.1. Functions.. . 6 2.2. Signal Descriptions .. . 6 2.3. Signal Naming Convention. 2.4. Pin Assignment. 7 2.4.1 x16 Link Alternate Uses . .9 2.4.2 DIR Signal . .10 2.4.3 PEx16\_ENA# Signal . 11 2.5. Stack-UP or Stack-DOWN Link Shifting. 2.5.1 PCB Link Shifting.. ..13 2.5.2 Link Shifting Stack Examples.. ..14 2.6. Switching . . 16 2.6.1 Signal Switch . ..16 2.7. System Clocking.. . 16 2.8. Layout Recommendations . 16 2.9. Routing Topology.... 17 2.9.1 Microstrip Example .17 2.9.2 Stripline Example.. .18 2.10. Device connector Break-Out Example .19 # 3. EXPANSION CONNECTOR B... .. 20 3.1. Description. .20 3.2. Functions.. . 20 3.3. Signal Descriptions .. .21 3.4. Pin Assignment. . 22 3.5. +5V\_SB, PSON#, and PME# . . 22 3.6. PCI Signaling Voltage (VI/O) Requirements . .23 3.6.1 PCI Host Module . ..23 3.6.2 Add-In Modules. ..23 # 4. STACKING. .24 4.1. Add-in Device Rules.. . 24 4.2. System Rules . .24 4.3. Stack Configuration Examples . .25 # 5. ELECTRICAL SPECIFICATION.. . 29 5.1. Power and Ground . . 29 5.1.1 Connector A Power Capabilities. .29 5.1.2 Connector B Power Capabilities . .29 5.1.3 Total PCI/104-Express Power Capabilities.. ..29 5.1.4 Total PCIe/104 Power Capabilities.. ..30 5.2. AC/DC Signal Specifications . .30 5.2.2 Stackable PCI Expansion Bus. .30 # 6. MECHANICAL SPECIFICATIONS . .. 31 6.1. Connector A. .31 6.1.1 Part Number. .31 6.1.2 Connector A Specifications . .33 6.1.3 ASP-129637-03 or equivalent (Top Connector) Mechanical Drawings .. ..35 6.1.4 ASP-129646-03 or equivalent (Bottom Connector) Mechanical Drawings.. ..36 6.2. Connector B .. . 37 6.3. Standoff . .37 6.4. Board Layout & Dimensions . . 38 6.4.1 PCIe/104 Layout & Dimensions . 6.4.2 PCI/104-Express Layout & Dimensions.. ..40 6.4.3 Connector A Placement Details . ..42 # APPENDIX A: PC/104 BRIDGE CARD.. .. 43 A.1 Bridge Module Configurations .. . 44 A.2 Stack Configuration Examples . . 45 # APPENDIX B: EPIC FORM FACTOR. . 47 # APPENDIX C: EBX FORM FACTOR. .. 48 # TABLE OF FIGURES Figure 1-1: PCI/104-Express and PCIe/104 Board Layouts on 104 Form Factor .. Figure 2-1 Required Circuitry for a Host Module Configuration for Automatic Link Shifting . . 10 Figure 2-2 Required Device Circuitry for Automatic Link Shifting . 11 Figure 2-3: Automatic Link Shifting Examples for Host and Various Devices ... . 13 Figure 2-4: Automatic Link Shifting Stack-Up Example Consisting of Two x1 Link Device, One x4 Link Device, and One Device with One x1 Link and One x4 Link.. 14 Figure 2-5: Automatic Link Shifting Stack-Down Example Consisting of Two x1 Link Device, One x4 Link Device, and One Device with One x1 Link and One x4 Link . 15 Figure 2-6 Capacitor Placement . . 17 Figure 2-7 MicroStrip Example.. . 18 Figure 2-8 Stripline Example . . 18 Figure 2-9 Example for breakout routing of connector bank 1 from bottom to top with shifting. ..... 1 9 Figure 4-1: Stack-DOWN Configuration Example . . 25 Figure 4-2: Stack-UP Configuration Example with Large Form Factor Host Baseboard . 26 Figure 4-3 PCIe/104 with a PCI Express to PCI Bridge.. . 27 Figure 4-4: Combined Stack-UP and Stack-DOWN Configuration Example. . 28 Figure 6-1: Top Connector ASP-129637-03 or equivalent.. . 31 Figure 6-2: Bottom Connector ASP-129646-03 or equivalent .. . 31 Figure 6-3: Top Half and Bottom Half of Connector A Shown with Pick-and-Place Adapters.... .. 31 Figure 6-4: Mating of Top Half and Bottom Half of Connector A.. . 32 Figure 6-5: ASP-129637-03 or equivalent Mechanical Drawings... ... 35 Figure 6-6: ASP-129646-03 or equivalent Mechanical Drawings.. .. 36 Figure 6-7: Standoff Mechanical Dimensions.... . 37 Figure 6-8 PCIe/104 Module Dimensions.. . 39 Figure 6-9 PCI/104-Express Module Dimensions....... .. 41 Figure 6-10: Top Side and Bottom Side Views of Connector Placements . . 42 Figure 6-11: Basic Configuration of the PCI-to-ISA Bridge Module . . 44 Figure 6-12: Stack-DOWN Configuration of the PCI-to-ISA Bridge Module. .. 44 Figure 6-13: Stack-UP Configuration of the PCI-to-ISA Bridge Module . . 44 Figure 6-14: Stack-DOWN Configuration Example . .. 45 Figure 6-15: Combined Stack-UP Configuration Example . . 46 Figure 6-16: EPIC with PCI/104-Express ..... .. 47 Figure 6-17: EBX with PCI/104-Express. . 48 # TABLE OF TABLES Table 2-1 Connector A Signals: PCI Express and Others .. 6 Table 2-2 Connector A Pin assignments . 8 Table 2-3: x16 Link as Two x8 or Two x4 Links. 9 Table 2-4: x16 Link as SDVO. . 10 Table 2-5: PCIe Signal Switch Specification . 16 Table 2-6: PCIe Signal Switch or equivalent . . 16 Table 2-7: Via and Trace Length Budget . . 17 Table 2-8 PCI Express Routing Specification . 17 Table 2-9 Typical Trace Dimensions for Microstrip with FR4 .. . 18 Table 2-10 Typical Trace Dimensions for Stripline with FR4 .. . 18 Table 3-1 Connector B Signals.. . 21 Table 3-2 Connector Signal Assignment. . 22 Table 5-1: Connector A Power Delivery ...... . 29 Table 5-2: Connector B Power Delivery . . 29 Table 5-3: Combined Connector A and B Power Delivery ...... . 29 Glossary of Terms
TermsDefinitions
ATXAdvanced Technology ExtendedA specification for PC motherboards, power supplies, and system chassis. One of its most notable features is support for “Standby” and “Soft-Off” power savings modes.
DeviceA logical device attached to a PCIe Link. Generally an add-in card.
DMADirect Memory AccessA method for peripherals to efficiently access system memory without CPU intervention.
EBXForm factor for SBC’s
HostThe central connection of a PCIe system, typically a CPU module. This is called the “Root Complex” by the PCIe specification.
ISA BusIndustry Standard ArchitectureA legacy bus used on earlier PCs. It has been phased out of desktop PCs, but is still common in embedded systems.
LaneFundamental unit of a PCI Express connection. A set of differential signal pairs, one pair for transmission, and one pair for reception. Multiple lanes may be combined to increase bandwidth (up to x16). A “by-N Link” is comprised of N Lanes.
LinkThe collection of one or more PCI Express Lanes, plus an additional differential pair for a clock, which make up a standard PCI Express interconnect. According to PCI Express Specification 1.1 a Link can be comprised of 1, 4, 8, or 16 Lanes.
Packet SwitchA device used to attach multiple PCIe devices to a single link on the HOST. The PCIe Specification refers to this simply as a “Switch.” In this document, the term “Packet Switch” is used to differentiate from a “Signal Switch.”
PCIePCI Express
PEGPCI Express Graphics
SBCSingle Board Computer
SDVOSerial Digital Video Output used from Intel 915/945/965 chipsets
Signal SwitchAn analog switch used to select between multiple PCIe devices to attach to a single PCIe link, or multiple links to attach to a single device. Also called a “Channel Switch.”
# 1. INTRODUCTION # 1.1. Purpose This document defines the addition of PCI Express, the next generation serial interconnect bus, to the stackable 104, EPIC, and EBX form factors. PCI Express was chosen because of its performance, scalability, wide market acceptance, and growing silicon availability worldwide. The PCI Express architecture uses familiar software and configuration interfaces of the conventional PCI bus architecture, but provides a new high-performance physical interface while retaining software compatibility with the existing conventional PCI infrastructure. PCI Express is a high performance I/O architecture used in both desktop and mobile applications. This hierarchical, point-to-point interconnect works well with on-board and slot oriented architectures. The purpose of this Specification is to adapt PCI Express to the stacked architecture employed with 104, EPIC and EBX form factors. # 1.2. Standard Identification A PCI-104 board with the addition of PCI Express becomes PCI/104-Express. A board with only the PCI Express connector is called PCIe/104. Each of these configurations can be applied to EPIC and EBX as shown in Appendix B and C. This allows full interchangeability with add-in Devices. # 1.3. Description As computer technology continues to develop, the PC/104 community must expand to the new, widely accepted technologies of today. Currently we are seeing the introduction of PCI Express (PCIe) into the mainstream computer market. Therefore, the PC/104 platform must be promoted with a connector architecture that provides a high-speed interface, maintains the ability to develop low-cost modules, and is sustainable for the foreseeable future. PCI/104-Express meets these needs with a stackable PCIe connector for both up and down stacking, and retains the stackable PCI connector for backward compatibility to PCI-104, PC/104-Plus, and PC/104 peripheral modules. Figure 1-1 shows a basic view of the PCI/104-Express and PCIe/104 layouts. ![PCI Bus: 32 bit/33MHz PC/104-Plus PCI 120 Pin Connector PCI/104-Express Module PCIe/104 PCI Express 156 pin Connector PCIe Bus 3.775 inches (95.89 mm) 3.550 inches (90.17 mm)](.PCI104-Express_Specification_v1.0/5d54acbad78a5d9f1244379dc393d9ed4077dca6133fe27602cf2772cf540729.jpg) ![PCIe/104 3.775 inches (95.89 mm) 156 pin Connector 2 156 PCIe Bus 155 1 3.550 inches (90.17 mm)](.PCI104-Express_Specification_v1.0/a84aa601512f5b767f243df5f84fbb72f773dc91fe1cca77305f1d3351c9691f.jpg) Figure 1-1: PCI/104-Express and PCIe/104 Board Layouts on 104 Form Factor ISA bus backward compatibility can naturally and easily be achieved with the use of a PCI-to-ISA bridge peripheral module (see Appendix A). # This Document for Internal Use Only. PCI/104-Express has the following features: Connector A: PCI Express Bus Four x1 PCIe Links One x16 PCIe Link, or optionally two x8 Links, two x4 PCIe Links, or two SDVO • ATX power and control signals: +5V Standby, Power supply on, Power OK Power: +3.3V, +5V, +12V • SMBus Connector B: PCI Bus: • PCI Bus: 32 bit, 33 MHz, Four Bus Master capable (same as on PC/104-Plus and & PCI-104) • +5V Standby, Power supply on, and power management event signals for ATX power supply Power: +3.3V, +5V, +12V, -12V PCIe/104 has the following features: Connector A: PCI Express Bus Four x1 PCIe Links One x16 PCIe Link, or optionally two x8 Links, two x4 PCIe Links, or two SDVO • ATX power and control signals: +5V Standby, Power supply on, Power OK Power: +3.3V, +5V, +12V • SMBus # 1.4. Bus and Signal Group Descriptions # 1.4.1 PCI Express Expansion Bus PCI/104-Express and PCIe/104 incorporate four x1 PCI Express Links and options for either a single x16 Link, or two x8 Links, or two x4 PCIe Links to allow connections to standard PCI Express device chips. The x16 Link option allows maximum flexibility, configurability, and expandability for current and future designs. Some examples of x16 Link application are next generation graphics chips, gigabit Ethernet chips, or use with a PCI Express Switch which can then branch the high throughput out into any number of various size Links including multiple x16 Link graphics engines. The only limitation is the bandwidth requirement for each of the branched links. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Key PCI attributes, such as its usage model, load-store architecture, and software interfaces, are maintained, whereas its parallel bus implementation is replaced by a highly scalable, fully serial interface. PCI Express takes advantage of recent advances in point-to-point interconnects, Switch-based technology, and packet-protocol to deliver new levels of performance and features. Power Management, Quality of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express. # 1.4.1.1 PEG Link PEG (PCI Express for Graphics) is a graphic interface with 16 differential lanes to connect a high performance video controller. Most of today’s chipsets support the PEG bus. In such chipsets with internal graphics, the PEG bus is used as an alternative to connect an external video controller. The internal chip controller is disabled in this case. The PEG-Bus configuration must be enabled from the Device by connecting the PEG-ENA# signal to ground. For SDVO-applications, the PEG-ENA# remains open. # 1.4.2 SDVO Links Serial Digital Video Output is the interface for up to two LVDS/DVI controllers on a chipset with internal graphics controller. This bus is normally provided as an alternative to the PEG-Bus. SDVO-Links needs up to 7 differential signal pairs per interface. # 1.4.3 PCI Expansion Bus The PCI Expansion Bus is the same 32 bit, 33 MHz PCI bus found on the PC/104-Plus and PCI-104 Specifications with the addition of +5V\_SB, PSON#, and PME#. # 1.4.4 System Management Bus The optional System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate with each other and with the rest of the system. It is based on the principles of operation of I2C. SMBus provides a control bus for system- and power-management related tasks. A system may use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. Accepting messages ensures future expandability. With SMBus, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspended event, report different types of errors, accept control parameters, and return its status. SMBus is described in System Management Bus (SMBus) Specification, Version 2.0. Refer to this specification for DC characteristics and all AC timings. If the system board or add-in card supports SMBus, it must adhere to additional requirements that may be found in Chapter 8 of the PCI Local Bus Specification, Revision. 3.0. An address resolution protocol (ARP) is defined in the SMBus 2.0 Specification that is used to assign slave addresses to SMBus devices. Although optional in the SMBus 2.0 Specification, it is required that systems that connect the SMBus to PCI slots implement ARP for assignment of SMBus slave addresses to SMBus interface devices on PCI add-in cards. The system must execute ARP on a logical SMBus whenever any PCI bus segment associated with the logical SMBus exits the B3 state or a device in an individual slot associated with the logical # This Document for Internal Use Only. SMBus exits the D3cold state. Prior to executing ARP, the sys-tem must insure that all ARP-capable SMBus interface devices are returned to their default address state. The system board provides pull-ups to the +3.3Vaux rail per the above specification and the components attached to these signals need to have a 3.3V signaling tolerance (5V signaling must not be used). Also, the SMBus is used during all power states, so all components attached to the SMBus must remain powered during standby, or ensure that the bus is not pulled down when not powered. The SMBus interface is based upon the System Management Bus Specification (SMBus 2.0 Specification). This two-wire serial interface has low power and low software overhead characteristics that make it well suited for lowbandwidth system management functions. The capabilities enabled by the SMBus interface include, but are not limited to, the following: Support for client management technologies. Support for server management technologies. Support for thermal sensors and other instrumentation devices on add-in cards. Add-in card identification when the bus is in the B3 state or when the PCI device is in the D3hot or D3cold states as defined in the PCI Power Management Interface Specification. # 1.4.5 ATX and Power Management PCI/104-Express and PCIe/104 incorporate all of the necessary control and signal lines for ATX and power management functionalities. These signals include PWR\_OK, PSON#, +5V\_SB, and PME#. The inclusion of these signals allows maximum power savings. PWR\_OK is a “power good” signal. It should be asserted high by the power supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are above the under-voltage thresholds and that sufficient main energy is stored by the converter to guarantee continuous power operation within specifications. Conversely, PWR\_OK should be deasserted to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages falls below its undervoltage threshold, or when main-power has been removed for a sufficiently long enough time that the power supply operation cannot be guaranteed beyond the power-down warning time. PSON# is an active-low, TTL-compatible signal that allows a motherboard to remotely control the power supply in conjunction with features such as soft on/off, Wake-on-LAN, or wake-on-modem. When PSON# is pulled to TTL low, the power supply should turn on the five main DC output rails: +12 VDC, +5 VDC, +3.3 VDC, -5 VDC, and - 12 VDC. When PSON# is pulled to TTL high or open-circuited, the DC output rails should not deliver current and should be held at zero potential with respect to ground. PSON# has no effect on the +5 VSB output, which is always enabled whenever AC power is present. +5V\_SB is a standby supply output that is active whenever AC power is present. It provides a power source for circuits that must remain operational when the five main DC output rails are in a disabled state. Example uses include soft power control, Wake-on-LAN, wake-on-modem, intrusion detection, or suspend state activities. # 1.5. References The following documents should be used as reference for a detailed understanding of the overall system requirements. For latest revisions of the above specifications contact the respective organizations.
PC/104 SpecificationPC/104 Embedded Consortiumwww.pc104.org
PC/104-Plus SpecificationPC/104 Embedded Consortiumwww.pc104.org
PCI-104 SpecificationPC/104 Embedded Consortiumwww.pc104.org
PCI Local Bus Specification Revision 2.2PCI Special Interest Groupwww.pcisig.com
PCI Express Base Specification Revision 1.1PCI Special Interest Groupwww.pcisig.com
ATX Specification Version 2.2Intel Corporationwww.intel.com
System Management Bus (SMBus)Specification Version 2.0SBS Implementers Forumwww.sbs-forum.org
INTEL description of PEG and SDVO in the 915/945/965 chipsetsIntelwww.intel.com
If errors are found in this document, please send a written copy of the suggested corrections to the publishers listed on the title page. # 2. EXPANSION CONNECTOR A # 2.1. Functions Four x1 PCI Express Links ATX power and control signals Power: +3.3V, +5 Volts, +12 Volts, +5 Volts Standby System Management Bus (SMBus) One x16 PCI Express Link, can be configured as two x8 PCI Express Links, two x4 PCI Express Links, or two SDVO Because not all chipsets support all PCI Express link configurations, it is up the Host manufacturer to determine the type and number of PCI Express Links to include in their expansion connector. However, the placement of these PCI Express Links must comply with the pin out described below for Connector A. This will ensure that any x1 or x4 or x8 or x16 PCI Express Device will work on any Host that has an x1, or x4 or x8, or x16, respectively. # 2.2. Signal Descriptions Table 2-1 Connector A Signals: PCI Express and Others
GroupPinsSignal NameHost DirectionDescription
x1PCIe Links4PEx1 [0:3]TpOutputTransmit Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4PEx1 [0:3]TnOutputTransmit Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4PEx1 [0:3]RpInputReceive Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4PEx1 [0:3]RnInputReceive Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
4PEx1 [0:3]CLKpOutputClock Differential Upper Line for x1 Links 0, 1, 2, 3. Shifted when used.
4PEx1 [0:3]CLKnOutputClock Differential Lower Line for x1 Links 0, 1, 2, 3. Shifted when used.
x16, x8, or x4PCIe Links16PEx16_0T(#)pOutputTransmit Differential Upper Lines for the x16, x8 or the x4 Links. The x4 and x8 Links should be shifted when used.
16PEx8 [0:1]T(#)p
8PEx4 [0:1]T(#)p
16PEx16_0T(#)nOutputTransmit Differential Lower Lines for x16, x8 or the x4 Links. The x4 and x8 Links should be shifted when used.
16PEx8 [0:1]T(#)n
8PEx4 [0:1]T(#)n
16PEx16_0R(#)pInputReceive Differential Upper Lines for the x16, x8, or the x4 Links. The x4 and x8 Links should be shifted when used.
16PEx8 [0:1]R(#)p
8PEx4 [0:1]R(#)p
16PEx16_0R(#)nInputReceive Differential Lower Lines for the x16, x8, or the x4 Links. The x4 and x8 Links should be shifted when used.
16PEx8 [0:1]R(#)n
8PEx4 [0:1]R(#)n
1PEx16_x8_x4_CLKpOutputClock Differential Upper Line for x16 or first x8 or x4 Link. Re-driven when used
1PEx16_x8_x4_CLKnOutputClock Differential Lower Line for x16 or first x8 or x4 Link. Re-driven when used
Misc.1DIROutputDirection indicates to the Device if it is installed above or below the Host
PCIe1PERST#OutputReset for PCI Express Bus
PCIe1Reserved WAKE#InputReserved for Wake on Lan
ATX Power Supply1PSON#OutputPower Supply On brings the ATX power supply out of sleep mode.
1PWRGDInputPower Good from the power supply indicates power is good
2+5V_SBPowerStandby Power for advanced power saving modes. Always on
2+5VPower+5V central power planes
2+3.3VPower+3.3V power
1+12VPower+12V central power plane
46GNDPowerGND pins
SMB1SMB_ClkOutputClock for SMBus
1SMB_DataBidirectionalData for SMBus
1SMB_Alert#InputAlert for SMBus
Reserved4Reserved HS+/-Reserved for 2 high speed differential pairs
1Reserved GPIO0Reserved for general purpose I/O
# indicates the lane within a link
[0:3] indicates link 0, 1, 2, or 3
[0:1] indicates link 0 or 1
Table 2-1 shows only the required pins, arranged in functional groups, for the various buses housed in Connector A. This version of the stackable PCIe is as defined in the PCIe Base Specification Revision 1.1 with the exception that Hot plug present detect, Hot plug detect, and JTAG are not supported. # 2.3. Signal Naming Convention The PCI Express signals on Connector A are named so that signal groupings are obvious. The fields in a signal name go from general to specific. The PCI Express signals start with the characters “PE,” followed by the width of the Link (“x1”, “x4”, “x8”, or “x16”), followed by an underscore “\_”. Next is the Link number if there is more than one Link of that width. Then is either “T”, “R”, or “Clk” for Transmit, Receive, or Clock respectively. Next is the lane number in the link in parenthesis, for the links that have more than one lane. Last is “p” or “n” for the positive and negative signal in the differential pair. For example, PEx4\_0T(2)p is the positive signal in lane number 2 of the first x4 Link. A signal on the connector is designated “transmit” or “receive” in a Host-centric manner. The “transmit” pin on the Host connects to the “T” (transmit) pin of the connector. From there, the signal connects to “receive” pin of the Device. In a PCIe system the transmit pins of the chip are always connected to the receive pins of the other chip in the link, and vice-versa. For example, for a specific link, transmit on the Host chip is connected to receive on the Device chip, and receive on the Host is connected to transmit on the Device. Other non-PCIe signals follow a similar convention. # 2.4. Pin Assignment On both of these connectors, the odd-numbered pins are located towards the inside of the board, and the even numbered pins are located towards the edge of the board. Signals were assigned to pins to simplify breakout and reduce trace lengths of the PCI Express signals around Connector A. See Table 2-2. Table 2-2 Connector A Pin assignments
Top View Signal Assignment
1Reserved (GPIO0)+5 VoltsPE_RST# 2
33.3V3.3V 4
5Reserved (HS1+)Reserved (HS0+) 6
7Reserved (HS1-)Reserved (HS0-) 8
9GNDGND 10
11PEx1_1TpPEx1_0Tp 12
13PEx1_1TnPEx1_0Tn 14
15GNDGND 16
17PEx1_2TpPEx1_3Tp 18
19PEx1_2TnPEx1_3Tn 20
21GNDGND 22
23PEx1_1RpPEx1_0Rp 24
25PEx1_1RnPEx1_0Rn 26
27GNDGND 28
29PEx1_2RpPEx1_3Rp 30
31PEx1_2RnPEx1_3Rn 32
33GNDGND 34
35PEx1_1ClkpPEx1_0Clkp 36
37PEx1_1ClknPEx1_0Clkn 38
395V Always5V Always 40
41PEx1_2ClkpPEx1_3Clkp 42
43PEx1_2ClknPEx1_3Clkn 44
45CPU_DIRPWRGOOD 46
47SMB_DATPEx16_x8_x4_Clkp 48
49SMB_CLKPEx16_x8_x4_Clkn 50
51SMB_ALERTPSON# 52
53Reserved / WAKE#+5 VoltsPEG_ENA# 54
55GNDGND 56
57PEx16_0T(8)pPEx16_0T(0)p 58
59PEx16_0T(8)nPEx16_0T(0)n 60
61GNDGND 62
63PEx16_0T(9)pPEx16_0T(1)p 64
65PEx16_0T(9)nPEx16_0T(1)n 66
67GNDGND 68
69PEx16_0T(10)pPEx16_0T(2)p 70
71PEx16_0T(10)nPEx16_0T(2)n 72
73GNDGND 74
75PEx16_0T(11)pPEx16_0T(3)p 76
77PEx16_0T(11)nPEx16_0T(3)n 78
79GNDGND 80
81PEx16_0T(12)pPEx16_0T(4)p 82
83PEx16_0T(12)nPEx16_0T(4)n 84
85GNDGND 86
87PEx16_0T(13)pPEx16_0T(5)p 88
89PEx16_0T(13)nPEx16_0T(5)n 90
91GNDGND 92
93PEx16_0T(14)pPEx16_0T(6)p 94
95PEx16_0T(14)nPEx16_0T(6)n 96
97GNDGND 98
99PEx16_0T(15)pPEx16_0T(7)p 100
101PEx16_0T(15)nPEx16_0T(7)n 102
103GNDGND 104
105SDVO_DAT (PENA#)+12 VoltsSDVO_CLK 106
107GNDGND 108
109PEx16_0R(8)pPEx16_0R(0)p 110
111PEx16_0R(8)nPEx16_0R(0)n 112
113GNDGND 114
115PEx16_0R(9)pPEx16_0R(1)p 116
117PEx16_0R(9)nPEx16_0R(1)n 118
119GNDGND 120
121PEx16_0R(10)pPEx16_0R(2)p 122
123PEx16_0R(10)nPEx16_0R(2)n 124
125GNDGND 126
127PEx16_0R(11)pPEx16_0R(3)p 128
129PEx16_0R(11)nPEx16_0R(3)n 130
131GNDGND 132
133PEx16_0R(12)pPEx16_0R(4)p 134
135PEx16_0R(12)nPEx16_0R(4)n 136
137GNDGND 138
139PEx16_0R(13)pPEx16_0R(5)p 140
141PEx16_0R(13)nPEx16_0R(5)n 142
143GNDGND 144
145PEx16_0R(14)pPEx16_0R(6)p 146
147PEx16_0R(14)nPEx16_0R(6)n 148
149GNDGND 150
151PEx16_0R(15)pPEx16_0R(7)p 152
153PEx16_0R(15)nPEx16_0R(7)n 154
155GNDGND 156
Bottom View Signal Assignment
2PE_RST#+5 VoltsReserved (GPIO0)1
43.3V3.3V3
6Reserved (HS0+)Reserved (HS1+)5
8Reserved (HS0-)Reserved (HS1-)7
10GNDGND9
12PEx1_0TpPEx1_1Tp11
14PEx1_0TnPEx1_1Tn13
16GNDGND15
18PEx1_3TpPEx1_2Tp17
20PEx1_3TnPEx1_2Tn19
22GNDGND21
24PEx1_0RpPEx1_1Rp23
26PEx1_0RnPEx1_1Rn25
28GNDGND27
30PEx1_3RpPEx1_2Rp29
32PEx1_3RnPEx1_2Rn31
34GNDGND33
36PEx1_0ClkpPEx1_1Clkp35
38PEx1_0ClknPEx1_1Clkn37
405V_Always5V_Always39
42PEx1_3ClkpPEx1_2Clkp41
44PEx1_3ClknPEx1_2Clkn43
46PWRGOODCPU_DIR45
48PEx16_x8_x4_ClkpSMB_DAT47
50PEx16_x8_x4_ClknSMB_CLK49
52PSON#SMB_ALERT51
54PEG_ENA#+5 VoltsReserved / WAKE#53
56GNDGND55
58PEx16_0T(0)pPEx16_0T(8)p57
60PEx16_0T(0)nPEx16_0T(8)n59
62GNDGND61
64PEx16_0T(1)pPEx16_0T(9)p63
66PEx16_0T(1)nPEx16_0T(9)n65
68GNDGND67
70PEx16_0T(2)pPEx16_0T(10)p69
72PEx16_0T(2)nPEx16_0T(10)n71
74GNDGND73
76PEx16_0T(3)pPEx16_0T(11)p75
78PEx16_0T(3)nPEx16_0T(11)n77
80GNDGND79
82PEx16_0T(4)pPEx16_0T(12)p81
84PEx16_0T(4)nPEx16_0T(12)n83
86GNDGND85
88PEx16_0T(5)pPEx16_0T(13)p87
90PEx16_0T(5)nPEx16_0T(13)n89
92GNDGND91
94PEx16_0T(6)pPEx16_0T(14)p934
96PEx16_0T(6)nPEx16_0T(14)n95
98GNDGND97
100PEx16_0T(7)pPEx16_0T(15)p99
102PEx16_0T(7)nPEx16_0T(15)n101
104GNDGND103
106SDVO_CLK+12 VoltsSDVO_DAT (PENA#)105
108GNDGND107
110PEx16_0R(0)pPEx16_0R(8)p109
112PEx16_0R(0)nPEx16_0R(8)n111
114GNDGND113
116PEx16_0R(1)pPEx16_0R(9)p115
118PEx16_0R(1)nPEx16_0R(9)n117
120GNDGND119
122PEx16_0R(2)pPEx16_0R(10)p121
124PEx16_0R(2)nPEx16_0R(10)n123
126GNDGND125
128PEx16_0R(3)pPEx16_0R(11)p127
130PEx16_0R(3)nPEx16_0R(11)n129
132GNDGND131
134PEx16_0R(4)pPEx16_0R(12)p133
136PEx16_0R(4)nPEx16_0R(12)n135
138GNDGND137
140PEx16_0R(5)pPEx16_0R(13)p139
142PEx16_0R(5)nPEx16_0R(13)n141
144GNDGND143
146PEx16_0R(6)pPEx16_0R(14)p145
148PEx16_0R(6)nPEx16_0R(14)n147
150GNDGND149
152PEx16_0R(7)pPEx16_0R(15)p151
154PEx16_0R(7)nPEx16_0R(15)n153
156GNDGND155
# 2.4.1 x16 Link Alternate Uses The x16 Link is also able to be configured for alternate uses. These uses include two x8 Links, two x4 Links, or two SDVO. Support for these alternate modes is Host and Device dependant. A Host that supports an x16 Link is not required to support SDVO, two x8, or two x4 Links. Also, a Device that supports operation at x16 is not required to support operation at x8 or x4. # 2.4.1.1 x8 and x4 Links Two x8 Links can be provided on the x16 Link. When a Device uses one of the Links, the other Link is shifted according to the same rules as the x1 Links. Each x8 Link may also be used as an x4 Link. Because there is only one clock provided for the x16 Link and potentially two devices when operating as x8 or x4, any Device that operates at x8 or x4 must re-drive the clock. The clock must not incur more than 10ns of phase delay when it is re-driven. The pin assignments for the x8 and x4 Links are shown in Table 2-3 below. Table 2-3: x16 Link as Two x8 or Two x4 Links
Host Transmit SignalsHost Receive Signals
x16 Signalx8 Signalx4 Signalx16 Signalx8 Signalx4 Signal
PEx16_0T(0)PEx8_0T(0)PEx4_0T(0)PEx16_0R(0)PEx8_0R(0)PEx4_0R(0)
PEx16_0T(1)PEx8_0T(1)PEx4_0T(1)PEx16_0R(1)PEx8_0R(1)PEx4_0R(1)
PEx16_0T(2)PEx8_0T(2)PEx4_0T(2)PEx16_0R(2)PEx8_0R(2)PEx4_0R(2)
PEx16_0T(3)PEx8_0T(3)PEx4_0T(3)PEx16_0R(3)PEx8_0R(3)PEx4_0R(3)
PEx16_0T(4)PEx8_0T(4)PEx16_0R(4)PEx8_0R(4)
PEx16_0T(5)PEx8_0T(5)PEx16_0R(5)PEx8_0R(5)
PEx16_0T(6)PEx8_0T(6)PEx16_0R(6)PEx8_0R(6)
PEx16_0T(7)PEx8_0T(7)PEx16_0R(7)PEx8_0R(7)
PEx16_0T(8)PEx8_1T(0)PEx4_1T(0)PEx16_0R(8)PEx8_1R(0)PEx4_1R(0)
PEx16_0T(9)PEx8_1T(1)PEx4_1T(1)PEx16_0R(9)PEx8_1R(1)PEx4_1R(1)
PEx16_0T(10)PEx8_1T(2)PEx4_1T(2)PEx16_0R(10)PEx8_1R(2)PEx4_1R(2)
PEx16_0T(11)PEx8_1T(3)PEx4_1T(3)PEx16_0R(11)PEx8_1R(3)PEx4_1R(3)
PEx16_0T(12)PEx8_1T(4)PEx16_0R(12)PEx8_1R(4)
PEx16_0T(13)PEx8_1T(5)PEx16_0R(13)PEx8_1R(5)
PEx16_0T(14)PEx8_1T(6)PEx16_0R(14)PEx8_1R(6)
PEx16_0T(15)PEx8_1T(7)PEx16_0R(15)PEx8_1R(7)
# 2.4.1.2 SDVO The x16 Link can also be re-configured as an SDVO connections as shown in Table 2-4. The exact implementation of this is chipset specific. Table 2-4 below shows the configuration when using an Intel® 915/945/965 chipset. When using the x16 Link as SDVO, the PEx16\_ENA signal must be left floating at the Device. Table 2-4: x16 Link as SDVO
x16 Signal NameSDVO Signal Namex16 Signal NameSDVO Signal Name
PEx16_0T(0)SDVO_0REDPEx16_0R(0)SDVO_TVCLKIN
PEx16_0T(1)SDVO_0GREENPEx16_0R(1)SDVO_0INT
PEx16_0T(2)SDVO_0BLUEPEx16_0R(2)SDVO_FLDSTALL
PEx16_0T(3)SDVO_0CLKPEx16_0R(3)
PEx16_0T(4)SDVO_1REDPEx16_0R(4)
PEx16_0T(5)SDVO_1GREENPEx16_0R(5)SDVO_1INT
PEx16_0T(6)SDVO_1BLUEPEx16_0R(6)
PEx16_0T(7)SDVO_1CLKPEx16_0R(7)
PEx16_0T(8)PEx16_0R(8)
PEx16_0T(9)PEx16_0R(9)
PEx16_0T(10)PEx16_0R(10)
PEx16_0T(11)PEx16_0R(11)
PEx16_0T(12)PEx16_0R(12)
PEx16_0T(13)PEx16_0R(13)
PEx16_0T(14)PEx16_0R(14)
PEx16_0T(15)PEx16_0R(15)
# 2.4.2 DIR Signal # 2.4.2.1 DIR Line on Host The DIR line provides a means for the Devices to select the correct Link depending if it is above or below the Host in the stack. The state of the DIR line is always determined by the Host so that the Devices can be designed without regards to the design of other Devices. On the top side connector this line must be tied to ground on the Host. On the bottom side connector the DIR line must be tied to +5 volt power during all implemented power saving modes except power completely off. A Host that supports suspend modes may want to use +5V\_Aux diode ORed with +5V in case the power supply does not provide +5V\_Aux. Shown in Figure 2-1 is the required PCB connection for the DIR line on the Host. ![Link 0 Link 1 Link 2 Link 3 DIR GND PCI Express Host Chipset Host CPU Module +5V Link 0 Link 1 Link 2 Link 3 DIR](.PCI104-Express_Specification_v1.0/95472c9f1b19bf47a2d5b87b5bf65e4283e6f5abb728b43e8919bff19359e381.jpg) Figure 2-1 Required Circuitry for a Host Module Configuration for Automatic Link Shifting # 2.4.2.2 DIR Line on Device On the Device the DIR line is an input to the resident auto-switching multiplexers. A resistor divider is required on the DIR line on each Device to adjust the SELECT line voltage for the switches. Each Device must sink or source less than 300uA of current. Therefore, the divider resistors R1 and R2 shown in Figure 2-2 must total 15K or greater. ![Based on the provided block diagram, here is an accurate description of the labeled blocks and their connections: **Blocks:** * **Left Vertical Block:** A tall rectangle on the far left containing the labels 'Link 0', 'Link 1', 'Link 2', 'Link 3', 'DIR' at the top and 'Link 0', 'Link 1', 'Link 2', 'Link 3', 'DIR' at the bottom. * **Add-On Module:** A large, long horizontal gray rectangle in the center labeled 'Add-On Module' on the right side. * **Select:** A small rectangle inside the 'Add-On Module' labeled 'Select'. Below it is the text 'PCI Express Bi-directional Switches'. * **PCI Express Device:** A small rectangle to the right of the 'Select' block. * **R1:** A resistor box. * **R2:** A resistor box. * **Ground:** A ground symbol connected to R1. **Connections:** * **Main Lines:** Five horizontal lines run from the left vertical block into the 'Add-On Module'. These lines correspond to 'Link 0', 'Link 1', 'Link 2', 'Link 3', and 'DIR'. * **Link Lines:** The lines for 'Link 0', 'Link 1', 'Link 2', and 'Link 3' pass straight through the 'Add-On Module' from left to right. * **DIR Line Circuit:** The line for 'DIR' enters the 'Add-On Module' and connects to a circuit network: * The 'DIR' line connects to a node. From this node, resistor **R1** connects to ground. * From the same node, a line continues to the right to a second node. * From this second node, a line goes to the top input terminal of the **Select** switch. * From this second node, a line goes up through resistor **R2** to the bottom input terminal of the **Select** switch. * **Switch Connection:** The common output terminal of the **Select** switch connects to the **PCI Express Device**.](.PCI104-Express_Specification_v1.0/91b521c42d77b3abb76864a9fd9b159fae2b768a95a0817fa8c91f356eca5d44.jpg) Figure 2-2 Required Device Circuitry for Automatic Link Shifting If the Device is positioned above the Host, then the DIR signal would be grounded and the SELECT line of the multiplexers would allow Link 0 to connect to the PCI device. Links 1, 2, and 3 are then allowed to shift and pass over so that Link 1 is in the Link 0 position, Link 2 is in the Link 1 position, and Link 3 is in the Link 2 position. A left-most Link is now available for the next Device card to be stacked above the first Device. If the Device is stacked below the module, then the DIR line would be set to +5V and the SELECT line of the multiplexers would allow Link 3 to connect to the PCI device. Links 0, 1, and 2 are then allowed to shift and pass over so that Link 2 is in the Link 3 position, Link 1 is in the Link 2 position, and Link 0 is in the Link 1 position. A right-most link is now available for the next Device card to be stacked below the first Device. All Devices can be built using the same methodology as a single configuration. The Links used will always be the left most links or the rights most links depending if the Device gets stacked above or below the Host. # 2.4.3 PEx16\_ENA# Signal The PEG\_ENA# signal is used to indicate the presence of a device on the x16 Link. This signal is pulled up at the Host. Any Device that uses the x16 Link (or the x16 as an x8 or x4) attaches this signal to ground. When the Host sees this signal high, indicating that an x16 Device is not present, it may disable the x16 Link, or convert it to alternate uses, such as SDVO. # 2.5. Stack-UP or Stack-DOWN Link Shifting Connector A contains two differential Link Groups: the x1 PCIe Link Group, and the x4/x8 PCIe Link Group. Within each group are individual point-to-point links which must be automatically shifted if one or more links out of that group are used on a Device. The x16 Link does not constitute a group because there is only one Link. Therefore, it does not require Link shifting Link shifting is utilized so that Devices can be built uniformly and consistently while using dedicated point-to-point connections. Without link shifting, Devices would have to be made with a specific link identified. This would then # This Document for Internal Use Only. require each Device to have multiple configurations, one for each link position. Link shifting at the PCB level allows each Device to have only one universal configuration. In addition to automatic Link shifting, highly embedded systems require that Devices be allowed to stack above or below the Host. The key to this capability is the ability for the Devices to use either the first links or the last links depending on whether the module is above or below the Host. The DIR line tells the Device its position relative to the Host. Note: Devices should not be stacked above and below the Host at the same time in order to avoid signal integrity degradation. # 2.5.1 PCB Link Shifting As a demonstration of link shifting in the presence of multiple link groups, the x1 PCIe and x4 PCIe link groups are used in Figure 2-3: Automatic Link Shifting Examples for Host and Various Devices for a Host and various Device configurations. Any Device may use one or more Links. If multiple Links are used then the necessary link shifting must be implemented on the Device PCB for each Link and Link Group. For example, in the case where two x1 Link devices are resident on the Device, it is required that the remaining two unused Links be shifted two locations in order that other Devices be able to use the remaining Links. It is not enough to shift only one link space as in the case of a one x1 Link Device. ![Flowchart](.PCI104-Express_Specification_v1.0/ed6bcbe35507083c788b13c9b37e5287d081052e53b79b1854841a87359025cc.jpg) Figure 2-3: Automatic Link Shifting Examples for Host and Various Devices # 2.5.2 Link Shifting Stack Examples ![The image displays a block diagram illustrating connections between a CPU and various peripheral modules, organized in horizontal rows. **Blocks:** * **Bottom Row:** Labeled 'CPU'. It is divided into two sections: * 'Four x 1 Links' containing columns labeled '1x1', '2x1', '3x1', and '4x1'. * 'Two x4 Links' containing columns labeled '0x4' (repeated four times) and '1x4' (repeated four times). * **Top Row:** Labeled 'Combination x1 and x4 Link Devices Peripheral Module'. Above the bar are labels 'x1 Link Device' and 'x4 Link Device'. * **Second Row:** Labeled 'x4 Link Device Peripheral Module'. Above the bar is the label 'x4 Link Device'. * **Third Row:** Labeled 'x1 Link Device Peripheral Module'. Above the bar is the label 'x1 Link Device'. * **Fourth Row:** Labeled 'x1 Link Device Peripheral Module'. Above the bar is the label 'x1 Link Device'. **Connections:** * **Combination x1 and x4 Link Devices Peripheral Module (Top Row):** * Connects via a vertical line from the '1x1' column. * Connects via three vertical lines from the '2x1', '3x1', and '4x1' columns. * Connects via four diagonal lines originating from the '0x4' columns section. * **x4 Link Device Peripheral Module (Second Row):** * Connects via four diagonal lines originating from the '1x4' columns section. * **x1 Link Device Peripheral Module (Third Row):** * Connects via one diagonal line from the '1x1' column. * Connects via three vertical lines from the '2x1', '3x1', and '4x1' columns. * **x1 Link Device Peripheral Module (Fourth Row):** * Connects via one diagonal line from the '1x1' column. * Connects via three vertical lines from the '2x1', '3x1', and '4x1' columns.](.PCI104-Express_Specification_v1.0/166c537c0cfa7d18fd431c006a75d0bb3a4cfc61d05a8f829f25f783ea61aaa0.jpg) Figure 2-4: Automatic Link Shifting Stack-Up Example Consisting of Two x1 Link Device, One x4 Link Device, and One Device with One x1 Link and One x4 Link ![The diagram illustrates a connection architecture starting from a CPU and distributing links to various peripheral modules. **Labeled Blocks:** 1. **CPU**: Contains sub-labels 'Four x 1 Links' (with labels '1x1', '2x1', '3x1', '4x1') and 'Two x4 Links' (with labels '0x4', '0x4', '0x4', '0x4', '1x4', '1x4', '1x4', '1x4'). 2. **X4 Link Peripheral Module Automatic Shift** 3. **X4 Link Peripheral Module Automatic Shift** 4. **x1 Link Peripheral Module Automatic Shift** 5. **x1 Link Peripheral Module Automatic Shift** **Connections and Labels:** * **Vertical Lines**: * Lines labeled '1x1', '2x1', '3x1', and '4x1' extend downwards from the CPU. They connect to the left side of the second, fourth, and fifth blocks. They pass through the third block without connecting. * Lines labeled '0x4' and '1x4' extend downwards from the CPU. They connect to the right side of the second and third blocks. They pass through the fourth and fifth blocks without connecting. * **Pointers**: * **'x1 Link Device'**: Points to the connection area for the '4x1' link on the second, fourth, and fifth blocks. * **'x4 Link Device'**: Points to the connection area for the '1x4' links on the second and third blocks.](.PCI104-Express_Specification_v1.0/57fd4266b77ded966517479a68cdb10df4f93530d4a96230de2eca55f0ecf76b.jpg) Figure 2-5: Automatic Link Shifting Stack-Down Example Consisting of Two x1 Link Device, One x4 Link Device, and One Device with One x1 Link and One x4 Link # 2.6. Switching In order to be able to stack a PCIe/104 module above or below a Host, a PCIe signal switch is required on the Device. # 2.6.1 Signal Switch A signal switch is an analog multiplexer that can be used to select between the PCIe Link on the top connector and bottom connector. This switch must be able to perform well at the high data rates found in the PCIe signaling environment. Specifications for this switch are shown in Table 2-5. Table 2-5: PCIe Signal Switch Specification
ParameterMin.Max.Units
Crosstalk @ f = 1.25 GHz-33dB
Off Isolation @ f = 1.25 GHz-33dB
Insertion Loss @ f = 1.25 GHz-3.2dB
Several candidates for the Signal Switch have been identified. They are listed in Table 2-6. Table 2-6: PCIe Signal Switch or equivalent
ManufacturerPart NumberQualification Stage
Texas InstrumentsTS2PCIE2212None
PericomPI2PCIE2412None
National SemiconductorDS25MB100None
NXPCBTU0808EE/GNone
# 2.7. System Clocking The PCIe architecture is based on a 100 MHz reference clock. In PCIe/104, this clock is distributed from the Host to the Devices. The Host may also employ spread spectrum clocking as defined in the PCI Express Base Specification to reduce EMI. In this case it is required that the Device use the distributed clock as its reference clock. Using an on-board oscillator as a reference is not allowed. PCIe/104 does not provide for any termination on unused clock lines, therefore the Host is required to disable any unused clocks. Since there is only one x4\_x8\_x16 clock, it must be re-driven on add-in boards that use this clock. # 2.8. Layout Recommendations The Data rate for PCIe is 2.5 Gbps. This means that significant frequency content exists up to 1.25 GHz. At these speeds, PCB layout becomes very critical. Therefore, the following recommendations should be followed to avoid signal integrity problems: Route all PCIe signal lines (Transmit and Receive) as controlled impedance, 100 Ohm differential pairs and 55 Ohm single ended traces. Spacing from a link to its neighbor must be at least 20 mils in the main routing region, 15 mils for stripline breakout, and 12 mils for microstrip breakout. Symmetrical routing must be used between the two signals of a differential pair. Signals in a differential pair must be matched to within 5 mils. AC coupling capacitors must be provided on the TX lines. Values should be between 75nF and 200nF. A surface mount capacitor must be used. • All PCIe signals should be routed in an adjacent layer to a ground plane. No stubs except the short stub caused by the unused end of the Host connector. SI testing has shown this very short stub to be insignificant in a system with a Host and 6 add-in cards. Do not use 90 degree bends. Use 45 degree bends or curves. Table 2-7: Via and Trace Length Budget
LocationMax. ViasMax. Trace LengthNotes
Host TX lines46000 milsBoth sides of AC cap.
Host RX lines26000 mils
Device TX Lines44000 milsBoth sides of signal switch.
Device RX lines44000 milsBoth sides of signal switch.
Pass-through (lane shifting)21000 milsIncludes stack height
# 2.9. Routing Topology Figure 2-6 Capacitor Placement below shows the positioning of the DC blocking capacitor and PCIe connector in relation to the Host and Device. The DC blocking capacitor is placed on the transmit signals. This will be the signals the Host drives onto the Tx bus connector’s pins and the signals the Device drives onto the Rx signals of the connector. The actual position is not critical; however the position must be closely matched between the signals of a differential pair. ![The diagram depicts a connection layout with a central vertical block and four peripheral blocks. **Labeled Blocks:** * **Host Board** (Top Left Rectangle) * **Device Board** (Top Right Rectangle) * **PCIe/104 Connector** (Center Vertical Rectangle) * **Tx** (Top Left Triangle, pointing right) * **Rx** (Top Right Triangle, pointing left) * **Rx** (Bottom Left Triangle, pointing left) * **Tx** (Bottom Right Triangle, pointing left) * **L** (Label below the bottom arrow) **Connections:** * **Top Path:** Two parallel lines with capacitor symbols connect the **'Tx'** triangle to the left side of the **'PCIe/104 Connector'**. Two parallel lines connect the right side of the **'PCIe/104 Connector'** to the **'Rx'** triangle. * **Bottom Path:** Two parallel lines connect the left side of the **'PCIe/104 Connector'** to the **'Rx'** triangle (bottom left). Two parallel lines with capacitor symbols connect the right side of the **'Tx'** triangle (bottom right) to the left side of the **'PCIe/104 Connector'**. * **Bottom:** A double-headed horizontal arrow labeled **'L'** spans the width at the bottom of the diagram.](.PCI104-Express_Specification_v1.0/fc141fcfc84f7adaa61b54c07923eb133d18d7531d0c4e1e5136641397345efe.jpg) Capacitors are 75 – 200 nF Figure 2-6 Capacitor Placement Table 2-8 below list the general guide lines for PCI Express routing. Table 2-8 PCI Express Routing Specification
InterfaceSingle Ended Impedance (Ohm)Differential Impedance (Ohm)Matching in a pair mil (mm)Matching pair to pair mil (mm)
PCI Express55 ±15%100 ±20%5 (1.27)Not required
# 2.9.1 Microstrip Example Typical trace dimensions for a microstrip over a ground layer are shown in Table 2-9 and Figure 2-7 below. The actual trace dimensions are dependant on layer stackup. The dimensions should be chosen to result in a differential impedance of 100 Ω and a single ended impedance of 55 Ω. Microstrip technology is used on outer layers. Table 2-9 Typical Trace Dimensions for Microstrip with FR4
UnitsNom. Trace WidthNom. Trace SpacePair to Pair SpaceInsulator ThicknessTrace Thickness
ABCD1T
mil57203.5 – 5.51.4 – 2.6
mm0.1270.1780.5080.089 – 0.1400.036 – 0.066
![A B C Ground Plane T D1](.PCI104-Express_Specification_v1.0/c18c1841fddbd0ac892b2458a69e75933d95eb189eb4970ee015bba0496a205e.jpg) Figure 2-7 MicroStrip Example # 2.9.2 Stripline Example Typical trace dimensions for a stripline are shown in Table 2-10 and Figure 2-8 below. The actual trace dimensions are dependant on layer stackup. The dimensions should be chosen to result in a differential impedance of 100 Ω and a single ended impedance of 55 Ω. Stripline technology is used on inner layers. Table 2-10 Typical Trace Dimensions for Stripline with FR4
UnitsNom. Trace WidthNom. Trace SpacePair to Pair SpaceInsulator ThicknessInsulator ThicknessTrace Thickness
ABCD1D2T
mil47203.5 – 5.756 – 141.1 – 1.3
mm0.1020.1780.5080.089 – 0.1460.152 – 0.3560.028 – 0.033
![A B C Ground Plane D2 D1 Ground Plane T](.PCI104-Express_Specification_v1.0/6bd80dc1e184da19c3d29b60f1e8ec2d9a817b7a143e1fbefbeef7a35025a738.jpg) Figure 2-8 Stripline Example # 2.10. Device connector Break-Out Example Figure 2-9 below shows an example of the routing from the Device connector to a Signal Switch. This drawing is not to scale and does not show controlled impedance lines. It is intended to show the general connections and lane shifting on a device for a x1 PCI Express link that can be stacked above or below the CPU. ![The diagram illustrates a PCB routing schematic with a layer legend at the top: 'Green = top layer, Red = bottom layer, Blue = inner layer'. **Labeled Blocks and Components:** * **PCI Express Switch:** A large rectangular block on the left containing vertical green bars. It has internal labels '1', 'Device Clk', 'CPU_DIR', 'Device Rx', and 'Device Tx'. * **Middle Column:** A vertical column of gray horizontal bars (pads) labeled with numbers on the left: '52', '40', '28', '22', '10', '2'. * **Right Column:** A vertical column of gray horizontal bars (pads) labeled with numbers on the right: '51', '1'. * **CPU_DIR:** A vertical gray bar running between the Middle and Right columns. **Connections and Traces:** * **Switch to Middle Column:** Traces leave the right side of the PCI Express Switch. * Green traces (top layer) are labeled 'Clk3', 'RX3', 'TX3'. * Red traces (bottom layer) are labeled 'Clk0', 'RX0', 'TX0'. * These traces connect to the pads in the Middle Column. * **Middle Column to Right Column:** Horizontal lines connect the pads of the Middle Column to the pads of the Right Column. These connections involve Red (bottom layer) and Blue (inner layer) traces. * **Right Column to Exit/CPU_DIR:** * Green traces connect pads in the Right Column to the vertical 'CPU_DIR' bar (e.g., at the top near '51') and exit to the far right edge. * Red traces exit to the far right edge.](.PCI104-Express_Specification_v1.0/f47829fcc69354e9e5fbc1196311117f9156c6417d7e9152b4aee78375bcb88f.jpg) Figure 2-9 Example for breakout routing of connector bank 1 from bottom to top with shifting. # 3. EXPANSION CONNECTOR B # 3.1. Description Expansion Connector B is the stackable PCI Expansion connector of the PC/104-Plus and PCI-104 specifications. For full details and connector location see the PC/104-Plus or PCI-104 Specifications published by the PC/104 Embedded Consortium # 3.2. Functions Four 32 bit, 33 MHz PCI Bus Links each capable of Bus Mastering +5V\_SB, PSON#, PME# for ATX power management Power: +3.3V, +5V, +12V, -12V # 3.3. Signal Descriptions Table 3-1 Connector B Signals
# PinsSignal NameGroupDescription
32AD[31:00]PCI BusAddress and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases.
4C/BE[0,3]#Bus Command/Byte Enables are multiplexed. During the address phase of a transaction, they define the bus command. During the data phase, they are used as byte enables.
1PARParity is even parity across AD [31:00] and C/BE [3:0]#. Parity generation is required by all PCI signals.
1FRAME#Cycle Frame is driven by the current master to indicate the beginning of an access and will remain active until the final data cycle.
1TRDY#Target Ready indicates the selected device's ability to complete the current data phase of the transaction. Both IRDY# and TRDY# must be asserted to terminate a data cycle.
1IRDY#Initiator Ready indicates the bus master's ability to complete the current data phase of the transaction.
1STOP#Stop indicates the current selected device is requesting the master to stop the current transaction.
1DEVSEL#Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access.
4IDSEL[0,3]Initialization Device Select is used as a chip-select during configuration read and write transactions.
1LOCK#Lock indicates an atomic operation to a bridge that may require multiple transactions to complete.
1PERR#Parity Error is for reporting data parity errors.
1SERR#System Error is for reporting address parity errors.
4REQ#[0,3]Request indicates to the arbitrator that this device desires use of the bus.
4GNT#[0,3]Grant indicates to the requesting device that access has been granted.
4CLK[0,3]Clock provides timing for all transactions on the PCI bus and is an input to every PCI device.
1RST#Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state.
1M66EN66 MHz Enable indicates to a device whether the bus segment is operating at 33 MHz or 66 MHz. The PCI bus has been simulated at 33MHz. For the purpose of this specification, 66MHz is not supported.
1INTA#Interrupt A is used to request Interrupts.
1INTB#Interrupt B is used to request Interrupts.
1INTC#Interrupt C is used to request Interrupts.
1INTD#Interrupt D is used to request Interrupts.
1PME#ATX Power SupplyPower Management Event such as wake-on-LAN
1+5V_SBStandby Power for advanced power saving modes. Always on
1PSON#Power Supply On brings the ATX power supply out of sleep mode.
5VI/OPower
10+3.3V+3.3V power lines
8+5V+5V power lines
1+12V+12V power line
1-12V-12V power line
25GNDGround lines
Table 3-1 shows only the required pins, arranged in functional groups, which are required for the stackable PCI Expansion bus. This version of the PCI bus is intended as a 32-bit bus running at 33MHz as defined in the PCI Local Bus Specification Revision 2.2, and therefore, 64-bit extension and 66MHz1 are not supported at this time. Also not supported are the boundary scan features (JTAG), Present (PRSNT [1:2]#), and Clock running (CLKRUN#). The direction indication on the pins assumes a combination master/target device. # 3.4. Pin Assignment Signals are assigned in the same relative order as in the PCI Local Bus Specification Revision 2.2, but transformed to the corresponding header connector pins. Because of the stack-through nature of the bus, slot-specific signals are duplicated for each plug-in module. The system has been designed to accommodate 4 modules, which are PC/104- $P l u s _ { ; }$ , PCI-104, or a combination of the two, so multiple sets of the signals have been duplicated to accommodate one signal for each module. These four signal groups include: IDSEL[3:0], CLK[3:0], REQ#[3:0], GNT#[3:0]. Signal assignments for the J3/P3 connector are given in Table 3-2. Table 3-2 Connector Signal Assignment
ABCD
1GND+5V SB+5VAD00
2VI/OAD02AD01+5V
3AD05GNDAD04AD03
4C/BE0#AD07GNDAD06
5GNDAD09AD08GND
6AD11VI/OAD10M66EN
7AD14AD13GNDAD12
8+3.3VC/BE1#AD15+3.3V
9SERR#GNDPSON#PAR
10GNDPERR#+3.3VPME#
11STOP#+3.3VLOCK#GND
12+3.3VTRDY#GNDDEVSEL#
13FRAME#GNDIRDY#+3.3V
14GNDAD16+3.3VC/BE2#
15AD18+3.3VAD17GND
16AD21AD20GNDAD19
17+3.3VAD23AD22+3.3V
18IDSEL0GNDIDSEL1IDSEL2
19AD24C/BE3#VI/OIDSEL3
20GNDAD26AD25GND
21AD29+5VAD28AD27
22+5VAD30GNDAD31
23REQ0#GNDREQ1#VI/O
24GNDREQ2#+5VGNT0#
25GNT1#VI/OGNT2#GND
26+5VCLK0GNDCLK1
27CLK2+5VCLK3GND
28GNDINTD#+5VRST#
29+12VINTA#INTB#INTC#
30-12VREQ3#GNT3#GND
# 3.5. +5V\_SB, PSON#, and PME# To support ATX power supplies and power down features three signals have been added to the PCI bus. They are +5V\_SB which is a power source that is always present when main power is supplied to the system, PSON# which is a power supple control signal that can turn the power supple on or off, and PME# which can be used to bring the CPU out of power down states such as wake-on-LAN. These signals have been implemented on the reserved pins of the PCI expansion bus of the PC/104-Plus and PCI-104 Specifications at pins B1, C9, and D10. Not all manufacturers will implement these signals; therefore to maintain compatibility with existing products it is important for designs that implement these functions to protect against undriven inputs. # 3.6. PCI Signaling Voltage (VI/O) Requirements # 3.6.1 PCI Host Module The PCI Host board will always determine the PCI signaling level on the bus by setting all VI/O pins to either +3.3V or +5V. If VI/O is set to 3.3V, then the system will use +3.3V I/O signaling and, likewise, if VI/O is set to +5V, then the system will use +5V I/O signaling. Some PCI host modules may only allow one of the options, while others may provide a jumper to allow the user to select the signaling level. Once the signaling level is selected, the remaining boards in the system must use that signaling level. # 3.6.2 Add-In Modules Add-in cards can be 3.3V, 5V, or universal. # 3.6.2.1 3.3V Add-In Modules 3.3V add-in modules operate in environments where VI/O has been set to +3.3V by the host module. Using 5V addin modules on a 3.3V stack will result in the 3.3V modules being damaged. # 3.6.2.2 5V Add-In Modules 5V add-in modules operate in environments where VI/O has been set to +5V by the host module. Using 3.3V add-in modules on a 5V stack will result in the 3.3V modules being damaged. # 3.6.2.3 Universal Add-In Modules Universal add-in boards can be used on either 3V or 5V I/O signaling buses. Universal boards either use the VI/O signal to determine its signaling level or are 3V signaling boards that have 5V-tolerant I/O. Many PCI interface chips have a "VI/O" pin that is the power for the I/O buffers that can be directly connected to VI/O. Universal boards will work on either 3V or 5V I/O signaling buses. # 4. STACKING # 4.1. Add-in Device Rules 1) A Device card must be able to be stacked above or below the Host. Therefore, the Device must be capable of selecting the TX, RX, and clock lines from the top connector or the bottom connector. 2) If any link(s) from a Link group (x1 PCIe, x4 PCIe, and x8 PCIe) is used on the module, the other links in that group must be shifted to the appropriate positions. 3) Any unused signals must be passed between top and bottom using no more than two vias and as short of a trace as possible. # 4.2. System Rules 1) A PCI Express Link may only traverse up to six stacked PCI Express connector heights and all PCI Express modules should be on the same side of the host. 2) A PCIe Link may only be attached to a single connector on the Host. 3) A PCI bus may only traverse up to four stacked PCI connectors, and they must all be on the same side of the Host. Because of the requirements of trace length matching, all PCI Devices must be stacked together and must be next to the Host # 4.3. Stack Configuration Examples ![PCI Memory Chipset Processor Chip PCI/104-Express CPU Module PCI PCIe Device PCIe PCI/104-Express Peripheral Module PCI PCIe Device PCIe PCI/104-Express Peripheral Module PCI PCIe Device PCIe PCI-104 Peripheral Module PCI PCIe Device PCIe PCI-104 Peripheral Module PCI](.PCI104-Express_Specification_v1.0/dbbf925ac757907a56247891414494d60f746030fd277cf9a12ff27a560ae028.jpg) Figure 4-1: Stack-DOWN Configuration Example This Document for Internal Use Only. ![ Component Component Type Area (inches) ----------- ----------------- --------------- PCle/104 Peripheral Module PCIe Device 0.600 PCle/104 Peripheral Module PCIe 15.24 PCle/104 Peripheral Module PCIe Device 0.600 PCle/104 Peripheral Module PCIe 15.24 PCI/104-Express Peripheral Module PCI 0.600 PCI/104-Express Peripheral Module PCI Device 0.600 PCI/104-Express Peripheral Module PCI 15.24 PCI/104-Express Peripheral Module PCI 15.24 Larger Form Factor PCIe/104-Express CPU Module PCI 0.600 Larger Form Factor PCIe/104-Express CPU Module PCIe 0.600 Larger Form Factor PCIe/104-Express CPU Module Processor 0.600 Larger Form Factor PCIe/104-Express CPU Module Memory 0.600 Larger Form Factor PCIe/104-Express CPU Module Chipset 0.600 Larger Form Factor PCIe/104-Express CPU Module PCIe 0.600 ](.PCI104-Express_Specification_v1.0/cdc13254496d46f255205973d4e1cc7e1ebddac42436d04945b288a61ba87901.jpg) Figure 4-2: Stack-UP Configuration Example with Large Form Factor Host Baseboard ![ Module Type Component Memory (inches) Chipset (inches) Processor Chip (inches) --- --- --- --- --- PCIe/104 CPU Module PCIe 0.600 0.600 0.600 PCIe/104 Peripheral Module PCIe 0.600 0.600 0.600 PCIe/104 to PCI-104 Bridge Module PCIe 0.600 0.600 0.600 PCI-104 Peripheral Module PCI 0.600 0.600 0.600 PCI-104 Peripheral Module PCI Device 0.600 0.600 0.600 PCI-104 Peripheral Module PCI Device 0.600 0.600 0.600 PCI-104 Peripheral Module PCI 0.600 0.600 0.600 ](.PCI104-Express_Specification_v1.0/fe9651036c57510e8377d6031c26b33f3ef5b26f4b02740d8d4f801667b367d5.jpg) Figure 4-3 PCIe/104 with a PCI Express to PCI Bridge ![The image is a vertical diagram illustrating a stack of different electronic modules. From top to bottom, the text reads as follows: **Top Four Modules:** * **Green Bar:** PCIe/104 Peripheral Module * **Grey Block:** PCIe Device * **Vertical Connector:** PCIe * **Measurement:** 0.600 inches (15.24 mm) **Fifth Module:** * **Green Bar:** PCI/104-Express CPU Module * **Grey Blocks:** Memory, Chipset, Processor Chip * **Vertical Connectors:** PCIe (right), PCI (left) * **Measurement:** 0.600 inches (15.24 mm) **Sixth and Seventh Modules:** * **Green Bar:** PCI-104 Peripheral Module * **Grey Block:** PCI Device * **Vertical Connector:** PCI * **Measurement:** 0.600 inches (15.24 mm) **Bottom Two Modules:** * **Green Bar:** PC/104-Plus Peripheral Module * **Grey Block:** PCI Device * **Vertical Connector:** PCI * **Measurement:** 0.600 inches (15.24 mm)](.PCI104-Express_Specification_v1.0/13f93e9cebfa34b2a07f099538c50e03df48e8d5e22d480c2eae1d82c8d6713c.jpg) Figure 4-4: Combined Stack-UP and Stack-DOWN Configuration Example Because of the requirement that each type of bus must completely reside on one side of the Host in order to avoid bus splits, only PCI-104 and PCIe/104 modules can be used in this configuration. In this example all of the PCI-104 boards are on the bottom side of the Host and all of the PCIe/104 modules are on the top side of the Host. The reverse configuration is also valid. # 5. ELECTRICAL SPECIFICATION # 5.1. Power and Ground # 5.1.1 Connector A Power Capabilities Power on Connector A comes from +5Vaux, +3.3V, +5V, and +12V. The +5V and +12V are carried on central conductor planes which are dispersed among the three banks of Connector A. The +5Vaux is carried on individual pins. The current carrying capacities of the central panes and pins are shown in Table 5-1 below. Current values include a 20% industry standard de-rating factor at $8 5 ~ ^ { \circ } \mathrm { C } .$ . Note that at lower temperatures the current carrying capacities increase. There is a 2.9 to 1 ratio of current ground to current voltages which helps ensure good current paths.
VoltageMinimum Voltage (V)Maximum Voltage (V)Number of PinsCurrent per Pin (A)Total Current (A)Total Power (W)
+3.3V3.03.621.83.611.9
+5V4.755.252 planes8.416.884.0
+12V11.4012.601 plane8.48.4100.8
+5V_SB4.755.2521.83.618.0
GNDn/an/a461.882.8n/a
Table 5-1: Connector A Power Delivery Standby power is supplied for wake capabilities. Because of the limited amount of power available during standby, it is important for Device cards to be designed to minimize power consumption from the standby rail. Note that during full power operation, the voltage on the Standby rail may exceed the voltage on the +5V rail. Therefore, if powering devices from both the standby and the +5V rail, care must be taken not to exceed the current limits of the Standby rail during normal operation. The +12V rail is intended to provide additional power for high power devices # 5.1.2 Connector B Power Capabilities
VoltageMinimum Voltage (V)Maximum Voltage (V)Number of PinsCurrent per Pin (A)Total Current (A)Total Power (W)
$+3.3V^1$ 3.003.60101.010.033.0
+5V4.755.2581.08.040.0
+12V11.412.611.01.012.0
-12V-12.6-11.411.01.012.0
GNDn/an/a231.023.0n/a
Table 5-2: Connector B Power Delivery # 5.1.3 Total PCI/104-Express Power Capabilities
VoltageMinimum Voltage (V)Maximum Voltage (V)Total Current (A)Total Power (W)
+3.3V3.003.6013.644.9
+5V4.755.2524.8124.0
+12V11.4012.609.4112.8
-12V-12.6-11.41.012.0
+5V Standby4.755.253.618.0
GNDn/an/a105.8n/a
Table 5-3: Combined Connector A and B Power Delivery # 5.1.4 Total PCIe/104 Power Capabilities Since PCIe/104 only utilizes Connector A, see Section 5.1.1 for total PCIe/104 power capabilities. # 5.2. AC/DC Signal Specifications # 5.2.1 Stackable PCI Express Expansion Bus For full details on the electrical requirements for the PCIe bus, reference the PCI Express Base Specification referenced in Section 1.5. # 5.2.1.1 Power and Ground Pins Power and ground planes are shared among all of the interfaces on Connector A. See Section 2 for more details. # 5.2.2 Stackable PCI Expansion Bus For full details on the electrical requirements for the stackable PCI bus, reference the PC/104-Plus or PCI-104 Specifications referenced in Section 1.5. # 5.2.2.1 Power and Ground Pins Power and ground planes are shared among all of the interfaces on Connector A. See Section 2 for more details. # 5.2.3 System Management Bus (SMBus) For full details on the electrical requirements for the SMBus, reference the System Management Bus (SMBus) Specification referenced in Section 1.5. # 5.2.3.1 Power and Ground Pins Power and ground planes are shared among all of the interfaces on Connector A. See Section 2 for more details. # 6. MECHANICAL SPECIFICATIONS # 6.1. Connector A The QMS/QFS series connectors from Samtec’s High Speed Interface line were designed for PC/104’s 0.600 inch (15.24mm) stacking height and standoff tolerances. An equivalent connector can be used. # 6.1.1 Part Number Top Connector: ASP-129637-03 with 0.600 inch (15.24 mm) stack height based on QMS or equivalent Bottom Connector: ASP-129646-03 with 0.600 inch (15.24 mm) stack height based on QFS or equivalent ![Close-up of a black plastic electronic connector with gold pins and terminal slots (no text or symbols visible)](.PCI104-Express_Specification_v1.0/61aa3e6b598ca7e32c596bc6ed9ab5996f7602c2f7bf521890ea0c755abb1aab.jpg) Figure 6-1: Top Connector ASP-129637-03 or equivalent ![Close-up of a black plastic electronic connector with gold pins and gold contacts (no text or symbols visible)](.PCI104-Express_Specification_v1.0/42e1abc823d30a8b676adf4bc10b2b778093dc874294afcefebc25d2b6978562.jpg) Figure 6-2: Bottom Connector ASP-129646-03 or equivalent ![3D rendering of a mechanical component with yellow and gray pins, no visible text or symbols](.PCI104-Express_Specification_v1.0/7e8b5f2081436a79447ea0b473060c504f7beb84b27791c4f431e354798958d5.jpg) Top Connector ![3D rendering of a mechanical or electronic component with yellow and gray components (no visible text or symbols)](.PCI104-Express_Specification_v1.0/93305734b1cde5d4a510b9bcb0995bb0813151c9c708571acd699901b239c5a1.jpg) Bottom Connector Figure 6-3: Top Half and Bottom Half of Connector A Shown with Pick-and-Place Adapters ![Pure mechanical assembly diagram showing two identical components with no text or symbols](.PCI104-Express_Specification_v1.0/2b05eb31a048373b58c5b95c88be22d4e3ae56d79c6fea5ef28786cc2e624170.jpg) Figure 6-4: Mating of Top Half and Bottom Half of Connector A # 6.1.2 Connector A Specifications MATERIALS
Housing:Liquid Crystal Polymer
Terminal & Ground Plane Material:Phosphor Bronze
Terminal Plating:Au over 50μ” (1.27μm) Ni
Plane Plating:Au over 50μ” (1.27μm) Ni
Terminal and Plane Tails:Tin
CONTACT FINISH
Socket Interface:30μ” Au
Terminal Interface:30μ” Au
Underplate:50μ” Ni
MECHANICAL PERFORMANCE
Insertion Force:13.9 lbs initial & 16.8 lbs @ 100 cycles
Withdrawal Force:9.8 lbs initial & 10.0 lbs @ 100 cycles
Normal Force @ nominal deflection:69 grams
Minimum stacking size:14.8mm
Nominal stacking size:15.24mm
Maximum stacking size:15.50mm
Contact wipe (at nom. Height):.044” [1.22mm]
Ground Plane wipe (at nom. Height):.059” [1.50mm]
Durability:50 cycles
Operating Temp:-55 °C to 125 °C
ELECTRICAL PERFORMANCE
PositionsThree banks of 52 pins and 1 plane for 156 total pins and 3 planes
Contact Resistance (initial):30 mOhms
Contact Resistance (@ 1,000 cycles):50 mOhms
Contact Current Capacity:1.8A at 85 °C and with 20% Industry Standard Derating Factor
Ground Plane Resistance:0.5 mOhms
Ground Plane Current Capacity:8.4A at 85 °C and with 20% Industry Standard Derating Factor
Dielectric Withstanding Voltage:900 VAC
Working Voltage:300 VAC
Insulation Resistance:50,000 megaOhms
SOLDERABILITY
Maximum Processing Temperature:230 °C for 60 seconds or 260 °C for 20 seconds
HIGH FREQUENCY PERFORMANCE
Differential Pair Impedance100 Ohms nominal +/- 10%
Single-Ended Impedance50 Ohms nominal +/- 10%
Differential Return Loss (SDD11):-15dB @ 1.25 GHz; -8dB @ 5 GHz
Differential Insertion Loss (SDD21):-1dB @ 1.25 GHz; -3dB @ 5 GHz
Differential Near End Crosstalk (SDD31):-45dB @ 1.25 GHz; -35dB @ 5 GHz
Differential Far End Crosstalk (SDD41):-45dB @ 1.25 GHz; -25 dB @ 5 GHz
This Document for Internal Use Only. # 6.1.3 ASP-129637-03 or equivalent (Top Connector) Mechanical Drawings ![2.515(63.88) REF {78 POS / 26} x .840(21.34) - .005(0.13) .090(2.29) REF .8400(21.336) (TYP) .1075(2.731) 25 EQ SPACES @ .0250(.635) .286(7.26) REF .009(0.23) REF 1.135±.020(28.82±0.51) 2.515(63.88) REF 'A' .212(5.38) REF .105(2.67) REF φ.040(1.02) REF (TYP) .035(0.89) REF 2.415(61.34)](.PCI104-Express_Specification_v1.0/745ff1bd63eb42bc76c2141dff9853ef1a8c5897ed33e8d01c6ea0a06f17f805.jpg) ![.010(0.25) REF .1150+0.0040 (2.921+0.102) .0000 0.000 (MEASURED TERMINAL TO TERMINAL) .3420+0.0040 (8.688+0.102) .0020 0.0051 (SEE NOTES 5, 6, & 7) .006(0.15) (SEE NOTE 6) .022(0.56) REF .296±.006 (7.52±0.15) SECTION 'A'- 'A' SCALE 5:1](.PCI104-Express_Specification_v1.0/0f18427120e0e353400650650e516742099d564faeddc682b99b58691b2801d9.jpg) Figure 6-5: ASP-129637-03 or equivalent Mechanical Drawings # 6.1.4 ASP-129646-03 or equivalent (Bottom Connector) Mechanical Drawings ![2.560 (65.02) REF {(78 POS / 26) x .840(21.34) + .040(1.02)} .0825 (2.096) REF .840 (21.34) .3050 (58.547) .1075 (2.731) 25 EQ SPACES @ .0250 (.635) .320 (8.13) REF .009 (0.23) REF 1.013±0.020 (25.72±0.51) .535 (13.59) REF .275 (6.99) REF 01 A' .356 (9.04) REF .411 (10.44) REF .451 (11.46) .035 (0.89) REF .686 (17.42) REF .A' Ø.040 (1.02) REF (TYP) 2.490 (63.25) REF](.PCI104-Express_Specification_v1.0/852de43765535f72c38d8799c3a8f7885da96c9c6ae41e9aa45017c685281351.jpg) ![.004(0.10) .134(3.40) (MEASURED CONTACT TO CONTACT) .371+0.004 (9.42-0.10 -.002 -0.05) (SEE NOTES 5, 6, & 7) .050(1.26) REF .320±0.006 (8.13±0.15) (APPLIES TO CONTACTS) .004(0.10) (SEE NOTE 6) SECTION 'A'-A' ITEM 4 NOT SHOWN FOR CLARITY](.PCI104-Express_Specification_v1.0/bb55547cb1446a684d6ca2318f92e3be1b3ac792964a7e84a4a4479c3a91acab.jpg) Figure 6-6: ASP-129646-03 or equivalent Mechanical Drawings # 6.2. Connector B Connector B is the standard PCI bus that is used on PC/104-Plus and PCI-104 modules. See the PC/104-Plus or PCI-104 Specification for mechanical specification details of the connector. # 6.3. Standoff Standoffs are used to ensure stacked boards retain their connectivity. The standoffs are preferably made from stainless-steel to provide for maximum strength and height tolerance. Pads must be provided for the standoffs, with the same plating as the pads for the PCIe connectors. All critical dimensions are listed. It is up to the user to define the thread typed. The height of the standoff shall be $0 . 6 0 0 ^ { \circ \prime } + / \mathrm { - } 0 . 0 0 5 ^ { \circ }$ . The width of the standoff must be able to fit on the Standoff pad called out on the Board Layout & Dimensions Section. The width of the threaded section must be able to fit into the standoff pad hole called out in the Board Layout & Dimensions Section. ![( 0.250 inches (( 6.350 mm) 0.600 ± 0.005 inches (15.24 ± 0.127 mm) ( 0.125 inches (( 3.175 mm)](.PCI104-Express_Specification_v1.0/a1cd877f4e9c1ba1c84cea21b5305da3f0dbeb0435723b51df87bbd0ccb36b1c.jpg) Figure 6-7: Standoff Mechanical Dimensions # 6.4. Board Layout & Dimensions # 6.4.1 PCIe/104 Layout & Dimensions The outer mechanical dimensions for this module are identical to PCI/104-Express Specification with the exception of the removal of the PCI connector and some modifications to the I/O connector area. ![ Dimension Type Value --- --- .250 (6.35) DIA PAD 4.050 (102.87) .125 (3.18) DIA HOLE TYP 4 PLACES 3.550 (90.17) 3.250 (82.55) 3.350 (85.09) 3.125 (79.38) 3.225 (81.92) 3.057 (77.65) 3.150 (80.01) 2.775 (70.48) 2.985 (75.819) I/O Connectors may overhang in this area (Includes Mating Connector) 150 Recommended Keep Out Area For Extractor Top (Horizontal Stripe) Bottom (Both Stripes) Both Edges 2.275 (57.78) 1.275(32.38) Unshaded Area Top Clearance = .345 (8.76) Bottom Clearance = .190 (4.83) .775 (19.69) Dotted Area (4 Sides) Top Clearance = .435 (11.05) Bottom Clearance = .100 (2.54) .475 (12.06) -0.00 .350 (8.89) -0.00 .000 -0.50 (-12.70) 3.993 (98.88) 450 (11.43) 3.775 (95.89) 350 (9.27) 3.679 (93.45) 225 (8.25) 3.575 (90.81) 290 (7.37) 3.450 (87.63) 200 (5.08) 450 (11.43) 190 (3.39) Max Component Height = .345 (8.76) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = 190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.83) Max Component Height = .190 (4.63) Max Component Height = .190 (4.83) Max Component Height = .190 (4.63) Max Component Height = .190 (4.83) Max Component Height = .190 (4.63) Max Component Height = .190 (4.83) Max Component Height = .190 (4.63) Max Component Weighting Units: Total Length: 250 (6.35) DIA PAD, Total Length: .125 (3.18) DIA HOLE TYP 4 PLACES, Total Length: 3.250 (82.55), Total Length: 3.125 (79.38), Total Length: 3.057 (77.65), Total Length: 2.775 (70.48), Total Length: 2.275 (57.78), Total Length: 1.275(32.38), Total Length: .775(19.69), Total Length: .475(12.06), Total Length: .350(8.89), Total Length: .000 ](.PCI104-Express_Specification_v1.0/e827f823261fd887ad8053db14749756e22eccde01b1fb25a920a5820e855d46.jpg) Figure 6-8 PCIe/104 Module Dimensions # 6.4.2 PCI/104-Express Layout & Dimensions The outer mechanical dimensions for this module are identical to PC/104-Plus Specification with the exception of the added connector (J3) and some modifications to the I/O connector area, and changes to the component height restrictions. The component height on the top has been reduced from 0.435" to 0.345" and the bottom has been increased from 0.100" to 0.190". Exceptions are the three regions on the sides of the module (indicated by the dotted region in Figure 6-9 which have a maximum height of 0.435” for the top and 0.100” for the bottom. ![The image is a technical drawing with dimensions in inches and millimeters. **Top Section:** - **Header:** 'Dimensions are in inches / (millimeters)' - **Top Left Note:** '.250 (6.35) DIA PAD .125 (3.18) DIA HOLE TYP 4 PLACES' - **Top Hatched Area:** 'I/O Connectors may overhang in this area (Includes Mating Connector)' - **Top Right Dimension:** '4.050 (102.87)' - **Right Side Dimensions:** '3.550 (90.17)', '3.350 (85.09)', '3.150 (80.01)', '2.985 (75.819)' - **Center Note:** '.075 (2.0) Dia Hole Typ 4 Places' - **Right Side Note:** 'Install Switches as close as possible to the signal source.' - **Right Side Note:** 'Keep out region for the shroud.' - **Center Label:** 'J3' - **Center Dimension:** '.079 (2.0)' - **Right Side Box 1:** 'Unshaded Area Top Clearance = .345 (8.76) Bottom Clearance = .190 (4.83)' - **Right Side Box 2:** 'Dotted Area (4 Sides) Top Clearance = .435 (11.05) Bottom Clearance = .100 (2.54)' - **Left Side Dimensions:** '3.250 (82.55)', '3.125 (79.38)', '3.057 (77.65)', '2.775 (70.48)' - **Left Side Note:** 'I/O Connectors may overhang in this area (Includes Mating Connector)' - **Left Side Dimension:** '2.275 (57.78)' - **Left Side Note:** 'Recommended Keep Out Area For Extractor Top (Horizontal Stripe) Bottom (Both Stripe) Both Edges' - **Left Side Dimension:** '1.275(32.38)' - **Left Side Dimensions:** '.775 (19.69)', '.650 (16.51)', '.527 (13.39)', '.475 (12.06)', '.350 (8.89)' - **Left Side Dimension:** '.000' - **Bottom Hatched Area:** 'I/O Connectors may overhang in this area (Includes Mating Connector)' - **Right Hatched Area:** 'I/O Connectors may overhang in this area (Includes Mating Connector)' - **Right Side Dimensions:** '.625 (15.88)', '.570 (14.48)', '.400 (10.16)', '.325 (8.26)' - **Right Side Dimension:** '.200 (5.08)' - **Right Side Dimension:** '.000' - **Right Side Dimension:** '-.500 (-12.70)' - **Right Side Dimension:** '.025 (0.64)' **Middle Section (Side View):** - **Left Dimensions:** '.368 (9.35)', '.062 (1.57)', '.410 (10.41)', '.440 (11.18)' - **Center Label:** 'J3' - **Center Text:** 'Max Component Height = .345 (8.76)' - **Center Text:** 'Max Component Height = .190 (4.83)' - **Center Label:** 'Connector Shroud' - **Left Dimension Stack:** '3.893 (98.88)', '3.775 (95.69)', '3.679 (93.45)', '3.575 (90.81)', '3.450 (87.62)', '3.224 (82.14)' - **Right Dimension Stack:** '450 (11.43)', '365 (9.27)', '325 (8.255)', '290 (7.37)', '.200 (5.08)', '.190 (3.30)' - **Right Dimension:** '.000' - **Right Dimension:** '-.500 (-12.70)' **Bottom Section:** - **Bottom Right Dimension:** '3.0225 (76.77)' - **Bottom Right Dimension:** '.000' - **Bottom Right Dimension Stack:** '.5325 (13.53)', '.625 (15.88)' - **Bottom Right Dimension:** '.025 (0.64)' - **Bottom Right Dimension Stack:** '.460 (11.68)', '.210 (5.33)', '.120 (3.05)' - **Bottom Right Dimension:** '.000' - **Bottom Left Numbers:** '156', '155'](.PCI104-Express_Specification_v1.0/9adb370b0f8f66be9b8b060825fcfb170ac3a2d4aa43866d078a9e09efda5ced.jpg) Figure 6-9 PCI/104-Express Module Dimensions # 6.4.3 Connector A Placement Details Since the QFS (ASP-129646-03) connector is larger than the QMS (ASP-129637-03), the QFS was used to determine the placement of both the QFS and the QMS. The maximum width of the QFS is determined by the recommend solder pad size and placement which is larger than the outer plastic dimensions of the QFS connector. The connector was lined up so that the base of the bottom solder pad lined up with the bottom of the AT ISA connector found on the PC/104 and PC/104-Plus form factors. This allows the retention of the traditional keep out region. With this placement the centerline of the connector (which placement should be based on) is located at 0.310 inches (7.874 mm) from the edge of the board. The horizontal positioning of the QFS connector was calculated by positioning it in the center of the PCB and rounding off to a reasonable even multiple of 0.025 inches (0.635 mm) since this is the distance between two solder pads. The result was the first solder pad being located 0.625 inches (15.875 mm) from the left edge of the PCB as shown in Figure 6-10. With the placement of the topside QFS connector, the QMS connector placement points are determined. The vertical placement point for the QMS is the same as that for the QFS which is 0.310 inches (7.874 mm) from the edge of the PCB to the center ground planes of the connector. ![ Connector Value Label --------- ----- ----- ASP-129637-03 Top View 0.450 (11.43) 2 ASP-129637-03 Top View 0.365 (9.27) 1 ASP-129637-03 Top View 0.290 (7.37) 1 ASP-129637-03 Top View 0.200 (5.08) 1 ASP-129637-03 Top View 0.130 (3.30) 1 ASP-129637-03 Top View 0.000 (0.00) 1 ASP-129637-03 Top View 0.570 (14.48) 2 ASP-129637-03 Top View 0.5325 (13.53) 2 ASP-129637-03 Top View 0.625 (15.88) 2 ASP-129646-03 Bottom View 0.000 (0.00) 1 ASP-129646-03 Bottom View 0.120 (3.05) 1 ASP-129646-03 Bottom View 0.200 (5.08) 1 ASP-129646-03 Bottom View 0.210 (5.33) 1 ASP-129646-03 Bottom View 0.290 (7.37) 2 ASP-129646-03 Bottom View 0.460 (11.68) 2 ](.PCI104-Express_Specification_v1.0/217028e0a4ff8ab3a507e039fd27c0142be6061b401f1ab1d3498dbd9c26c89d.jpg) Figure 6-10: Top Side and Bottom Side Views of Connector Placements Dimensions are in inches / [millimeters] # APPENDIX A: PC/104 BRIDGE CARD Maintaining the stackable PCI bus was chosen over the stackable ISA bus for two reasons. First, many current and most future modern chipsets support both PCI and PCIe. None support ISA. Second, backward compatibility to PC/104, PC/104-Plus, and PCI-104 is easier to achieve if the stackable PCI bus is retained over the stackable ISA bus. If PCIe/104 maintained the stackable ISA bus, the natural position for the stackable PCIe bus would be in the location of the stackable PCI bus as is found on the PC/104-Plus specification. In order to be backward compatible with PC/104-Plus and PCI-104 modules, a PCIe-to-PCI bridge module would need to be created because you cannot realize a PCI bus through an ISA. The problem with this scheme is that the stackable PCI bus and the stackable PCIe bus are competing in the same location. And since the stackable PCI bus uses a stack-though connector, you cannot have both the stackable PCIe connector and the stackable PCI connector on the same bridge board. Thus, a two board bridge module is required. This has potential power and signal integrity issues when routing over such large distances. To realize the stackable ISA bus, one merely needs to create a single board PCI-to-ISA bridge module using off-theshelf PCI-to-ISA bridge chips or FPGA cores. This will get a basic ISA bus without DMA or IRQs. With the addition of three signals (SDMA\_REQ, SDMA\_GNT, and SIRQ) which are present on many chipsets and can be cabled to a bridge board, a full ISA bus can be realized for complete backward compatibility to all PC/104 specifications without any mechanical or electrical interference or deficiency issues. And since the ISA bus is created using a PCI-to-ISA bridge chip, it is a natural electrical and mechanical extension to create the ISA bus off of the PCI expansion bus to support the number of ISA legacy cards already on the market. If the ISA bus was retained then creating a PCI bus off of the PCIe bus would be easy electrically, but mechanically you have problems because the both the PCI expansion bus and the PCI Express expansion bus would reside in the same location. This would then require a two board solution to support the number of PC/104-Plus and PCI-104 cards already on the market. # A.1 Bridge Module Configurations The PCI-to-ISA Bridge module has three possible configurations: Basic, Stack-UP only, and Stack-DOWN Only. Because of the heights of the Q2 (PCI/104-Express and PCIe/104) connectors and the ISA Bus (PC/104-Plus) connector and because they reside in the same general location, interference can occur if a PCI-to-ISA Bridge module is placed next to PCI/104-Express or PCIe/104 module.. In this case a Stack-UP Only or a Stack-DOWN Only version must be used. If there is a PCI-104 module between the PCI-to-ISA Bridge module and a PCI/104- Express or PCIe/104 module then a Basic configuration can be used. ![PCI PCI Device ISA PC/104-Plus Bridge Module PCI](.PCI104-Express_Specification_v1.0/6f2fed793edc0ef53cdd887835390ef1cb5f10561381876f63a2795eea3c0554.jpg) Figure 6-11: Basic Configuration of the PCI-to-ISA Bridge Module ![PCI PCI Device PC/104-Plus Bridge Module PCI ISA](.PCI104-Express_Specification_v1.0/cf76a40535210edea1fab28886134b4d4124a24da621fac95956afddd4133bfd.jpg) Figure 6-12: Stack-DOWN Configuration of the PCI-to-ISA Bridge Module ![PCI PCI Device ISA PC/104-Plus Bridge Module PCI](.PCI104-Express_Specification_v1.0/2b2ac7882c711be4acfdab9354291b643154792f0bf8fc9ae1714bd86dece173.jpg) Figure 6-13: Stack-UP Configuration of the PCI-to-ISA Bridge Module # A.2 Stack Configuration Examples ![ Component Total (inches) ----------- ---------------- PCI/104-Plus CPU Module 15.24 PCI 0.600 PCI 0.600 PCI/104-Plus Peripheral Module 15.24 PCI 0.600 PCI 0.600 PCI-104 Peripheral Module 15.24 PCI 0.600 PCI to-ISA Bridge Device 15.24 PCI/104-Plus Bridge Module 15.24 PCI 0.600 ISA Device 15.24 ISA 0.600 ISA Device 0.600 ISA Device 0.600 ISA 0.600 ISA 0.600 ISA Device 15.24 ISA 0.600 ISA Device 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PCI 0.600 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC/104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104 Peripheral Module 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 15.24 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104PeripheralModule 13.78 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC /104Peripherals 15.24 PC/104Peripherals 15.24 PC/104Peripherals 15.24 PC/104Peripherals 15.24 PC/104Peripherals 15.24 PC/104Peripherals 15.24 PC/104Peripherals 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 15.24 PC/104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC/104PeripheralModule 13.78 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule 9.99 PC/104PeripheralModule (PC) 9.99 PC/104PeripheralModule (ISA) 9.99 PC/104PeripheralModule (ISA) 9.99 PC/104PeripheralModule (ISA) 9.99 PC/104PeripheralModule (ISA) 9.99 PC/104PeripheralModule (ISA) 9.99 PC/104PeripheralModule (ISA) 9.99 DCI / 3D Processor Chip / Memory Chip / Chipset Chip / Processor Chip / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device / PCIe Device : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI' : 'PCI'](.PCI104-Express_Specification_v1.0/b093efba59715203c993115b4255b2a7ed063c368fa15de853a50a69a89b5267.jpg) Figure 6-14: Stack-DOWN Configuration Example ![ISA ISA Device PC/104 Peripheral Module ISA ISA Device 0.600 inches (15.24 mm) PC/104 Peripheral Module ISA ISA Device 0.600 inches (15.24 mm) PCI PCI-to-ISA Bridge Device PC/104-Plus Bridge Module PCI PCI PCIe Device 0.600 inches (15.24 mm) PCI/104-Plus Peripheral Module PCI PCIe 0.600 inches (15.24 mm) PCI/104-Plus CPU Module PCI PCIe](.PCI104-Express_Specification_v1.0/db716d7bf5282a9e973d680f88d0dd740703863ba65330d5c7444bc0a0425698.jpg) Figure 6-15: Combined Stack-UP Configuration Example APPENDIX B: EPIC FORM FACTOR ![ Zone Value ------ ------- (109.93) 4.328 (104.86) 4.128 (101.68) 4.003 (97.23) 3.828 (22.30) 0.878 (19.13) 0.753 (14.05) 0.553 (12.70) 0.500 (0.00) 0.000 (-5.08) -0.200 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 -0.200 -5.08 1746 1.746 1600 1.600 14435 1.4435 13896 1.3896 12713 1.2713 114214 1.14214 10736 1.0736 9796 1.0396 8966 1.0125 7966 1.0396 6966 1.0125 6296 1.0396 5796 1.0125 5596 1.0396 5471 1.0125 54714 1.0396 54722 1.0125 54722 1.0396 54722 1.0125 54722 1.0396 54722 1.0125 54722 1.0396 54722 1.0125 54722 1,3896 54722 13896 54722 13796 54722 13396 54722 13966 54722 13966 54722 13796 54722 13396 54722 13966 54722 13796 54722 13396 54722 13966 54722 13796 54722 13396 54722 (Lower) -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 -5.08 1746 1,746 1600 1,600 14435 1,4435 13896 1,3896 12713 1,2713 114214 1,14214 10736 1,0736 9796 1,0396 8966 1,0125 7966 1,0396 6966 1,0125 6296 1,0396 5796 1,0125 54714 1,0396 54722 1,0125 54722 1,3896 4966 1,3896 4966 1,3896 4966 1,3896 4966 1,3896 4966 1,3896 4966 1,3896 4966 1,3896 (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (II/A) (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Zone) = (II/A) (I/O Zone) = (I/O Zone) = (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/O Z) (I/O Zone) = (I/C ) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) / (N/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) (II/A) \n(I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Zone: I/O Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCSF(nl)( img src='boxdensin'') The image displays a schematic representation of the diagram showing the structure of a circuit board with labeled components and their corresponding internal components and their functions.( img src='boxdensin'') The diagram contains three main components: 'Tall CPU & Power Zone', 'Connector Overhang Zone', and 'Stackable PCIe Connector'. The diagram contains three main components: 'PC/104 PCI Connector', 'PC/104 Expansion Zone', and 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram contains three main components: 'Stackable PCIe Connector'. The diagram includes labels for the diagram elements and notes that these components are not explicitly labeled in the diagram.( img src='boxdensin'') The diagram contains only one label above it.( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')( img src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image source='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src= 'boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='boxdensin')(image src='Box' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ( img src='boxdensin'') The diagram contains two segments: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Top section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the diagram: - Bottom section of the image. - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom section of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image: - Bottom segment of the image:( img src='boxdensin') A(Square Block) B(Connector Overhang Zone) C(Stackable PCIe Connector) D(Connector Overhang Zone) E(Connector Overhang Zone) F(Connector Overhang Zone) G(Connector Overhang Zone) H(Connector Overhang Zone) I(Square Block) J(Connector Overhang Zone) K(Stackable PCIe Connector) L(Connector Overhang Zone) M(Connector Overhang Zone) N(Connector Overhang Zone) O(Connector Overhang Zone) P(Connector Overhang Zone) Q(Connector Overhang Zone) R(Connector Overhang Zone) S(Connector Overhang Zone) T(Connector Overhang Zone) U(Connector Overhang Zone) V(Connector Overhang Zone) W(Connector Overhang Zone) X(Connector Overhang Zone) Y(Connector Overhang Zone) Z(Connector Overhang Zone) AA(Connector Overhang Zone) AB(Connector Overhang Zone) AC(Connector Overhang Zone) AD(Connector Overhang Zone) AE(Connector Overhang Zone) AF(Connector Overhang Zone) AG(Connector Overhang Zone) AH(Connector Overhang Zone) AI(Connector Overhang Zone) AJ(Connector Overhang Zone) AK(Connector Overhang Zone) AL(Connector Overhang Zone) AM(Connector Overhang Zone) AN(Connector Overhang Zone) AO(Connector Overhang Zone) AP(Connector Overhang Zone) AQ(Connector Overhang Zone) AR(Connector Overhang Zone) AS(Connector Overhang Zone) AT(Connector Overhang Zone) AU(Connector Overhang Zone) AV(Connector Overhang Zone) AW(Connector Overhang Zone) AX(Connector Overhang Zone) AZ(Connector Overhang Zone) BA(Connector Overhang Zone) BB(Connector Overhang Zone) BC(Connector Overhang Zone) BD(Connector Overhang Zone) BE(Connector Overhang Zone) BF(Connector Overhang Zone) BG(Connector Overhang Zone) BH(Connector Overhang Zone) BI(Connector Overhang Zone) BJ(Connector Overhang Zone) BK(Connector Overhang Zone) BL(Connector Overhang Zone) BM(Connector Overhang Zone) BN(Connector Overhang Zone) BO(Connector Overhang Zone) BP(Connector Overhang Zone) BQ(Connector Overhang Zone) BR(Connector Overhang Zone) BS(Connector Overhang Zone) BT(Connector Overhang Zone) BU(Connector Overhang Zone) BV(Connector Overhang Zone) BW(Connector Overhang Zone) BX(Connector Overhang Zone) BY(Connector Overhang Zone) end( img src='boxdensin') A(Square Block) B(Connector Overhang Z) C(Stackable PCIe Connector) D(Stackable PCIe Connector) E(Stackable PCIe Connector) F(Stackable PCIe Connector) G(Stackable PCIe Connector) H(Stackable PCIe Connector) I(Square Block) J(Connector Overhang Z) K(Stackable PCIe Connector) L(Stackable PCIe Connector)](.PCI104-Express_Specification_v1.0/5a0ba8474477ce427d147a33101903686455d25cf3500a8129db1df70dbb3802.jpg) Figure 6-16: EPIC with PCI/104-Express APPENDIX C: EBX FORM FACTOR ![ Category Value :--- :--- -0.200 (-5.08) -0.200 (-5.08) 0.000 (0.00) 0.000 (0.00) 0.650 (16.51) 0.650 (16.51) 1.675 (42.55) 1.675 (42.55) 1.875 (47.63) 1.875 (47.63) 2.000 (50.80) 2.000 (50.80) 2.000 (50.80) 2.000 (50.80) 5.125 (130.18) 5.125 (130.18) 5.250 (133.35) 5.250 (133.35) 5.350 (135.89) 5.350 (135.89) 5.550 (140.97) 5.550 (140.97) -0.200 (-5.08) -0.200 (-5.08) 1.000 (25.40) 1.000 (25.40) 2.800 (71.12) 2.800 (71.12) 3.100 (78.74) 3.100 (78.74) 5.700 (144.78) 5.700 (144.78) 6.000 (152.40) 6.000 (152.40) 7.000 (177.80) 7.000 (177.80) 7.800 (198.12) 7.800 (198.12) 7.600 (193.04) 7.600 (193.04) 8.300 (210.82) 8.300 (210.82) -0.200 (-5.08) -0.200 (-5.08) SIMM/DIMM Memory Zone A General Purpose I/O Zone B Power Connector Zone E PC/104 PCI Connector G PCI/104-Plus Expansion Zone G Stackable PCIe Connector G General Purpose I/O Zone J - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PC/104-Plus Expansion Zone G Tali CPU Region (option) H Tali CPU Region (option) G Tali CPU Region (option) H Tali CPU Region (option) G Tali CPU Region (option) H Tali CPU Region (option) G Tali CPU Region (option) H Tali CPU Region (option) G Tali CPU Region (option) H Tali CPU Region (option) G Tali CPU Region (option) = Power Connector Zone B Tali CPU Region (option) = Power Connector Zone E Tali CPU Region (option) = Power Connector Zone E Tali CPU Region (option) = Power Connector Zone = Power Connector Zone E Tali CPU Region (option) = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Z Tali CPU Region (option) = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Connector Zone = Power Indicator Value: \$-2.25 (-5.08)\$ Tali CPU Region (option) = Power Indicator Value: \$-2.25 (-5.08)\$ Tali CPU Region (option) = Power Indicator Value: \$-2.25 (-5.08)\$ Tali CPU Region (option) = Power Indicator Value: \$-2.25 (-5.08)\$ Tali CPU Region (option) = Power Indicator Value: \$-2.25 (-5.08)\$ Tali CPU Region (option), \$-2.25 (-5.08)\$ Tali CPU Region (option), \$-2.25 (-5.08)\$ Tali CPU Region (option), \$-2.25 (-5.08)\$ Tali CPU Region (option), \$-2.25 (-5.08)\$ Tali CPU Region (option), \$-2.25 (-5.08)\$ Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tali CPU Region (option), Tal CPU Region (option), \$-2.25 (-5.08)\$ Tal CPU Region (option), \$-2.25 (-5.08)\$ Tal CPU Region (option), \$-2.25 (-5.08)\$ Tal CPU Region (option), \$-2.25 (-5.08)\$ Tal CPU Region (option), \$-2.25 (-5.08)\$ Tal CPU Region (option), \$-2.25 (-5.08)\$](.PCI104-Express_Specification_v1.0/9ad6de67433ec787e620601f40e928c7b205f9cfe15e99fc2ef2ce81f31f2baf.jpg) Figure 6-17: EBX with PCI/104-Express [🔗 Link to the original document](.PCI104-Express_Specification_v1.0/PCI104-Express_Specification_v1.0.pdf)