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# Hardware Specification

PCI eXtensions for Instrumentation

An Implementation of

Revision 2.3

May 31, 2018

![PXI](.pxi-1-hardware-specification-rev2-3/b2fb9ffad1d612ae5c5afe58d5acdceb74652fe118d7b044cccac23f462745d4.jpg)

Systems Alliance

# IMPORTANT INFORMATION

# Copyright

© Copyright 1997–2018 PXI Systems Alliance. All rights reserved.

This document is copyrighted by the PXI Systems Alliance. Permission is granted to reproduce and distribute this document in its entirety and without modification.

# NOTICE

The PXI Hardware Specification is authored and copyrighted by the PXI Systems Alliance. The intent of the PXI Systems Alliance is for the PXI Hardware Specification to be an open industry standard supported by a wide variety of vendors and products. Vendors and users who are interested in developing PXI-compatible products or services, as well as parties who are interested in working with the PXI Systems Alliance to further promote PXI as an open industry standard are invited to contact the PXI Systems Alliance for further information.

The PXI Systems Alliance wants to receive your comments on this specification. Visit the PXI Systems Alliance web site at http://www.pxisa.org/ for contact information and to learn more about the PXI Systems Alliance.

The attention of adopters is directed to the possibility that compliance with or adoption of the PXI Systems Alliance specifications may require use of an invention covered by patent rights. The PXI Systems Alliance shall not be responsible for identifying patents for which a license may be required by any PXI Systems Alliance specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PXI Systems Alliance specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.

The information contained in this document is subject to change without notice. The material in this document details a PXI Systems Alliance specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company’s products.

The PXI Systems Alliance makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The PXI Systems Alliance shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.

Compliance with this specification does not absolve manufacturers of PXI equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).

# Trademarks

PXI™ is a trademark of the PXI Systems Alliance.

PICMG™ and CompactPCI® are trademarks of the PCI Industrial Computation Manufacturers Group.

Product and company names are trademarks or trade names of their respective companies.

# PXI Hardware Specification Revision History

This section is an overview of the revision history of the PXI Hardware Specification.

# Revision 1.0, August 20, 1997

This is the first public revision of the PXI specification.

# Revision 2.0, July 28, 2000

This revision incorporates changes that include but are not limited to the following:

Transfer of the specification ownership to the PXI System Alliance.
Modification of pin assignment to comply with PICMG 2.0 R3.0 that include addition of GA0-GA4 signals to all slots, removal of PRST#, DEG#, and FAL# from peripheral slots, addition of IPMB bus to all slots, addition of HEALTHY# to all slots, addition of SMB bus to system slot, addition of BD\_SEL# to peripheral slots, changing SYSEN# to UNC on peripheral slots, and changing IDSEL to GND on system slot.
Removal of references to Serialized IRQ due to PICMG 2.0 R3.0 adoption.
Addition of 66MHz PCI operation.
Removal of J5 as a reserved connector.
Allowance of J5 to be populated only in custom PXI boards and backplanes that are offered as a system.
Allowance for star trigger routings other than only peripheral slots in first two segments in PXI backplanes with more than two segments.
Allowance for the local bus to be routed between segments.
Addition of rules about connecting the IDSEL lines of first segment PCI devices, bridges, and peripheral slots to AD[25:31] and routing peripheral slot INT lines to system slot INT lines based on the peripheral slot IDSEL to AD[25:31] connection.
Increased required current on 3.3V for a 5V backplane to comply with requirement of 3.3V being available according to PICMG 2.0 R3.0
Addition of Windows 98 and Windows 2000 software frameworks.
Removal of requirements for PC 9X compliance for controllers and peripherals.
Addition of segment divider glyph.
Removal of SHALL NOT rule for chassis ground to digital ground connection and addition of SHOULD NOT recommendation for chassis ground to digital ground.
Modification of requirements for EMC that includes changing IEC 61326-1:1997 to IEC 61326-1:1998 and IEC CISPR-11 to EN5501.
Addition of maximum Voh and minimum Vol values for trigger bus.
Modification of the legal notice.
Addition of license requirement for use of the PXI logo.

# Revision 2.1, February 4, 2003

This revision incorporates changes that include but are not limited to the following:

Removal of software related rules (Refer to the now separate PXI Software Specification).
Removal of J4 as a reserved connector.
• Addition of rules associated with 6U chassis that support stacking of two 3U modules in a single 6U slot.
Addition of a rule that limits the maximum number of slots in a chassis to 31.
Combining the chassis power supply minimum power requirements tables into one table and removing the recommended current entries in favor of required current entries.

Increasing the -12V required current.
Addition of the minimum current-handling requirement for each slot.
Turning the recommendation that modules document their required current into a rule.
• Addition of a recommendation to limit the maximum power that a module dissipates within a chassis.
• Addition of a rule that requires filler panels to be installed in chassis slots that are not populated.
• Addition of an implementation note that recommends not mapping a module’s registers mapped to PCI I/O Space.
Modification of J2/P2 B19 and J2/P2 B21 pin assignments from GND to RSV on star trigger and peripheral pinouts.

# Revision 2.2, September 22, 2004

This revision incorporates changes that include but are not limited to the following:

Addition of a chassis class that does not support 64-bit PCI and allowance of controllers used in such a chassis to implement rear I/O.
Addition of a low power chassis class that reduces the minimum power requirements.
Addition of module grounding recommendations.
• Addition of rules for 5V tolerance for PXI\_CLK10 and PXI\_CLK10\_IN.
• Addition of pull-up resistor requirements for the PXI\_CLK10\_IN signal.
Addition of recommendation not to use low cost PLLs for PXI\_CLK10 distribution.
Addition of an observation on circuit operation for transitioning between clock sources.
Addition of a recommendation for modules using triggers to connect to all 8 triggers.
Addition of a rule that the pull-up on the PXI\_STAR line be 20K Ohm or greater.
. Addition of a rule that puts requirements on the disabling of external 10 MHz clock sources.

# Revision 2.3, May 31, 2018

This revision incorporates changes that include but are not limited to the following:

• Allowance of modules to draw up to 3 A/pin from the +12V and -12V pins.
Incorporation of the PXI Hardware Specification ECN 1 Revision 2.0 as Appendix A so that a separate document is no longer necessary.

# Contents

# 1. Introduction

1.1 Objectives.........
1.2 Intended Audience and Scope...........
1.3 Background and Terminology..........
1.4 Applicable Documents . 3
1.5 Useful Web Sites. 4

# 2. PXI Architecture Overview

2.1 Mechanical Architecture Overview ........... 5
2.1.1 Chassis Supporting Stacking 3U Modules in a 6U Slot..
2.1.2 System Slot Location .
2.1.3 Additional Mechanical Features.... 8
2.1.4 Interoperability with CompactPCI . 8
2.2 Electrical Architecture Overview.......... 8
2.2.1 Peripheral Component Interconnect (PCI) Features ...... C
2.2.2 Local Bus... 9
2.2.3 System Reference Clock .. . 10
2.2.4 Trigger Bus...... . 10
2.2.5 Star Trigger .... . 10
2.2.6 System Expansion with PCI-PCI Bridge Technology . . 11
2.2.7 32-Bit PCI and Rear I/O.... 11
2.3 Software Architecture Overview...... . 12

# 3. Mechanical Requirements

3.1 CompactPCI Mechanical Requirements ........... ..... 13
3.2 Maximum Number of Slots....... .... 13
3.3 System Slot Location and Rules ..... .. 13
3.4 Logos and Compatibility Glyphs . .. 14
3.5 Slot Numbering for 6U Chassis that Support 3U Stacking........... . 15
3.6 Environmental Testing . . 17
3.7 Cooling Specifications . 17
3.7.1 Plug-in Module Requirements . . 17
3.7.2 Chassis Requirements ..... . 18
3.8 Chassis and Module Grounding Requirements and EMI Guidelines ...... .. 18
3.9 Regulatory Requirements.. .. 18
3.9.1 Requirements for EMC . . 18
3.9.2 Requirements for Electrical Safety .. . 19
3.9.3 Additional Requirements for Chassis... . 19

# 4. Electrical Requirements

4.1 PXI Signal Groups . . 20
4.1.1 P1/J1: Signals .. . 20
4.1.2 P2/J2: Signals .. . 20
4.1.2.1 Signals from CompactPCI 64-bit Connector Specification.......... .. 20
4.1.2.2 PXI Bused Reserved Signals ...... . 21
4.1.2.3 Local Buses .. .. 22
4.1.2.4 Reference Clock: PXI\_CLK10 .. .. 24
4.1.2.5 Trigger Bus ..... .. 25
4.1.2.6 Star Trigger ...... .. 28
4.1.3 Electrical Guidelines for 6U... . 30
4.1.3.1 6U Peripheral Module Connector Population..... . 31
4.1.3.2 6U Chassis that Support Stacking 3U Modules... . 31
4.2 Connector Pin Assignments (J1/P1 and J2/P2)..... ..... 31

4.2.1 General Peripheral Slots...... . 33
4.2.2 System Slot... .. 34
4.2.3 Star Trigger Slot ..... . 35

4.3 Power... . 36

4.3.1 Low Power Chassis Power Supply Specifications....... . 37

4.4 PXI Module Ground Connections.... .... 38

# 5. PXI Software Specification Compliance

# 6. 32-Bit PCI and Rear I/O

6.1 32-Bit PCI-Only General Peripheral Slots ....... ..... 43
6.2 Rear I/O System Slot........... ...... 45
6.3 32-Bit PCI-Only Star Trigger Slot ....... ........ 46

# A. Appendix: Hybrid Slot-Compatible PXI-1 Peripheral Module

A.1 Background ....... ...... 47
A.2 Hybrid Slot-Compatible PXI-1 Peripheral Module ........... ..... 47

# Figures

Figure 1-1. The PXI Architecture ...... 2
Figure 2-1. PXI Peripheral Module Form Factors and Connectors ..... 5
Figure 2-2. Example of a 33 MHz 3U PXI System (Single Bus Segment) ..... 6
Figure 2-3. Example of a 6U Chassis that Supports Stacking 3U Modules ..
Figure 2-4. PXI and CompactPCI Interoperability . . 8
Figure 2-5. PXI Local Bus Routing ...... .. 10
Figure 2-6. PXI Trigger Architecture for Two Bus Segments... . 11
Figure 3-1. Example of PXI Slot Designations for a Chassis.... .. 14
Figure 3-2. PXI Logo ............. ..... 15
Figure 3-3. Star Trigger Slot Glyph ..... .... 15
Figure 3-4. PCI Segment Divider Glyph ...... ..... 15
Figure 3-5. Example of Slot Numbering for a 6U Chassis that Supports 3U Stacking....... .. 16
Figure 3-6. Cooling Airflow Direction in a PXI System ........ .. 17
Figure 4-1. PXI Asynchronous Trigger Timing ..... .. 25
Figure 4-2. PXI Synchronous Trigger Timing.. .. 26
Figure 4-3. PXI Trigger Bus Termination . . 27
Figure 4-4. Text Required for Low Power Chassis ....... ... 38
Figure 4-5. Power and Ground Connections on a PXI Module... .... 39
Figure 6-1. Text Required for Rear I/O Chassis ..... ..... 42
Figure A-1. Example of PXI Slot Designations for a Chassis........ ..... 48
Figure A-2. 6U Hybrid Slot-Compatible PXI-1 Peripheral Module ...... ... 49
Figure A-3. eHM Physical Location on a 3U Peripheral Module .. .. 50
Figure A-4. eHM Physical Location on a 6U Peripheral Module .. .. 51

# Tables

Table 4-1. Local Bus Routings ........ ... 23
Table 4-2. PXI Asynchronous Trigger Timing Parameters..... .. 25
Table 4-3. PXI Synchronous Trigger Timing....... .. 26
Table 4-4. DC Specifications.. . 28
Table 4-5. Pull-Up Resistor Values .. . 28
Table 4-6. Type A, High Current Driver, AC Specifications.. .. 28
Table 4-7. Star Trigger Mapping ...... . 29
Table 4-8. PXI System Signal Groups....... .... 32
Table 4-9. Generic Peripheral Slot Pinout..... ..... 33

Table 4-10. System Slot Pinout ... .. 34

Table 4-11. Star Trigger Slot Pinout .. .. 35

Table 4-12. PXI Chassis Power Supply Minimum Power Requirements ....... .. 36

Table 4-13. Minimum Current Handling Per Slot .... . 37

Table 4-14. Low Power PXI Chassis Power Supply Minimum Power Requirements..... . 38

Table 6-1. 32-Bit PCI-Only Generic Peripheral Slot Pinout ...... .. 44

Table 6-2. Rear I/O System Slot Pinout ......... .... 45

Table 6-3. 32-Bit PCI-Only Star Trigger Pinout ........... .. 46

Table A-1. PXI-1 Peripheral to PXI Express Hybrid Slot Critical Signals..... . 47

# 1. Introduction

This section describes the primary objectives and scope of the PCI eXtensions for Instrumentation (PXI) specification. It also defines the intended audience and lists relevant terminology and documents.

# 1.1 Objectives

PXI was created in response to the needs of a variety of instrumentation and automation users who require ever increasing performance, functionality, and reliability from compact rugged systems that are easy to integrate and use. Existing industry standards are leveraged by PXI to benefit from high component availability at lower costs. Most importantly, by maintaining software compatibility with industry-standard personal computers, PXI allows industrial customers to use the same software tools and environments with which they are familiar.

PXI leverages the electrical features defined by the widely adopted Peripheral Component Interconnect (PCI) specification. It also leverages the CompactPCI form factor, which combines the PCI electrical specification with rugged Eurocard mechanical packaging and high-performance connectors. This combination allows CompactPCI and PXI systems to have up to seven peripheral slots versus four in a desktop PCI system. Systems with more expansion slots can be built by using multiple bus segments with industry-standard PCI-PCI bridges. For example, a 13-slot PXI system can be built using a single PCI-PCI bridge. The PXI Hardware Specification adds electrical features that meet the high-performance requirements of instrumentation applications by providing triggering, local buses, and system clock capabilities. PXI also offers two-way interoperability with CompactPCI products.

By implementing desktop PCI in a rugged form factor, PXI systems can leverage the large base of existing industry-standard software. Desktop PC users have access to different levels of software, from operating systems to low-level device drivers to high-level instrument drivers to complete graphical APIs. All of these software levels can be used in PXI systems. The PXI Systems Alliance maintains a separate Software Specification for PXI modules, chassis, and systems. By having a separate Software Specification, the PXI Systems Alliance can more quickly adopt the latest operating systems and software standards. PXI modules, chassis, and systems developed to comply with this PXI Hardware Specification must also comply with the PXI Software Specification.

Figure 1-1 summarizes the scope of the PXI specification standard by depicting its mechanical, electrical, and software architectures. It also shows how the separate Hardware and Software specifications are partitioned.
![The flowchart is a hierarchical diagram titled **'PXI: PCI eXtensions for Instrumentation'**.  It branches into two main categories: *   **Hardware Specification** *   **Software Specification**  **Hardware Specification** branches into: *   **Mechanical Architecture**, which connects to:     *   **CompactPCI** (which further connects to: **31 Slots Max**, **IEC Connectors**, and **EuroCard Packaging**)     *   **PXI Additions** (which further connects to: **Defined System Slot Location**, **Cooling**, and **Env. Testing**) *   **Electrical Architecture**, which connects to:     *   **PCI and CompactPCI** (which further connects to: **32/64 Bit Transfers**, **33 MHz**, and **66 MHz**)     *   **Instrumentation Functions** (which further connects to: **Trigger Bus**, **Local Bus**, **Reference Clock**, and **Star Trigger**)  **Software Specification** connects to: *   **Software Architecture**, which branches into:     *   **Operating Systems**     *   **Driver Software**     *   **Resource Management**](.pxi-1-hardware-specification-rev2-3/cee6394441292e5b125be7aa8fb8f6201a4715ff1a32917ac764927792a11970.jpg)

Figure 1-1. The PXI Architecture

# 1.2 Intended Audience and Scope

This specification is organized with a top-down approach whereby general descriptions precede the more detailed specifications found deeper in the subsections. This structure is intended to serve the needs of a variety of audiences from product developers to system integrators to end-users. Product developers may want to become familiar with all portions of this specification while end users may be interested in only the feature set description and perhaps the summaries of how these features are implemented. The goal of this specification is to serve as the central source of information relevant to all users and providers of PXI compatible systems.

The first section of this specification describes the features that PXI systems can offer and how these features can be applied to instrumentation. The subsequent sections cover the mechanical, electrical, and software requirements specific to implementing PXI features.

# 1.3 Background and Terminology

This section defines the acronyms and key words that are referred to throughout this specification. This specification uses the following acronyms:

• API—Application Programming Interface
CompactPCI—PICMG 2.0 Specification
Eurocard—European Packaging Specifications (IEC 60297, IEEE 1101.1, IEEE 1101.10, IEEE 1101.11)
GPIB—General Purpose Interface Bus, IEEE 488

ISA—Industry Standard Architecture; desktop PC adapter board specification

PCI—Peripheral Component Interconnect; electrical specification defined by PCISIG

PCISIG—PCI Special Interest Group

PICMG—PCI Industrial Computer Manufacturers Group

PXI—PCI eXtensions for Instrumentation

VISA—Virtual Instrument Software Architecture

VITA—VMEbus International Trade Association

• VME—Versa Module Europe; VMEbus specification governed by the VSO

VPP—VXIplug&play Specification

VSO—VITA Standards Organization

VXI—VME Extensions for Instrumentation

This specification uses several key words, which are defined as follows:

RULE: Rules SHALL be followed to ensure compatibility. A rule is characterized by the use of the words SHALL and SHALL NOT.

RECOMMENDATION: Recommendations consist of advice to implementers that will affect the usability of the final Module. A recommendation is characterized by the use of the words SHOULD and SHOULD NOT.

PERMISSION: Permissions clarify the areas of the specification that are not specifically prohibited. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. A permission is characterized by the use of the word MAY.

OBSERVATION: Observations spell out implications of rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain rules, so that the reader understands why the rule must be followed.

MAY: A key word indicating flexibility of choice with no implied preference. This word is usually associated with a permission.

SHALL: A key word indicating a mandatory requirement. Designers SHALL implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification. This word is usually associated with a rule.

SHOULD: A key word indicating flexibility of choice with a strongly preferred implementation. This word is usually associated with a recommendation.

# 1.4 Applicable Documents

This specification defines extensions to the base PCI and CompactPCI specifications referenced in this section. It is assumed that the reader has a thorough understanding of PCI and CompactPCI. The CompactPCI specification refers to several other applicable documents with which the reader may wish to become familiar. This specification refers to the following documents directly:

PXI Software Specification (Latest Revision)
PCI Local Bus Specification, Rev. 2.3
PICMG 2.0 R3.0 CompactPCI Specification
VXIplug&play Specifications (VPP-3.x and VPP-7)

IEC 61326-1:1997, Electrical equipment for measurement, control, and laboratory use—EMC requirements—Part I, General requirements, International Electrotechnical Commission
IEC 1010-1:1990 + A1:1992, Safety requirements for electrical equipment for measurement, control, and laboratory use—Part 1, General requirements, International Electrotechnical Commission
IEC 60068-1, Environmental testing, International Electrotechnical Commission

# 1.5 Useful Web Sites

Below is a list of web site links that at the time of publication of this specification point to sites with information useful in the understanding and design of PXI products:

<table><tr><td>http://www.pxisa.org/</td><td>PXI specifications</td></tr><tr><td>http://www.picmg.org/</td><td>PICMG specifications</td></tr><tr><td>http://www.ieee.org/</td><td>IEEE specifications</td></tr><tr><td>http://www.iec.org/</td><td>IEC specifications</td></tr><tr><td>http://www.pcisig.com/</td><td>PCI and PCI Express specifications</td></tr><tr><td>http://www.vita.com/</td><td>VME specifications</td></tr><tr><td>http://www.vxi.org/</td><td>VXI specifications</td></tr><tr><td>http://www.vxipnp.org/</td><td>VISA specifications</td></tr></table>

# 2. PXI Architecture Overview

This section presents an overview of PXI system features and capabilities by summarizing the mechanical, electrical and software architectures defined by this specification.

# 2.1 Mechanical Architecture Overview

PXI supports the two module form factors that are depicted in Figure 2-1. The 3U module form factor defines modules that are 100 by 160 mm (3.94 by 6.3 in.) and have two interface connectors. J1 carries the signals required for the 32-bit PCI local bus and J2 carries the signals for 64-bit PCI transfers and the signals for implementing PXI electrical features. The 6U peripheral module form factor defines modules that are 233.35 by 160 mm (9.19 by 6.3 in.) and in the future may carry one additional connector for expansion of the PXI Hardware Specification. 6U System Modules and System Slots may use P3/J3, P4/J4, and P5/J5 for rear I/O purposes.

![This diagram compares the connector layout of a **3U PXI** module and a **6U PXI** module.  **Left Block: 3U PXI** *   Labeled **3U PXI**. *   On the right side, there are two stacked connection blocks:     *   Top block labeled **J2** next to text **64-Bit PCI and PXI Features**.     *   Bottom block labeled **J1** next to text **32-Bit PCI**.  **Right Block: 6U PXI** *   Labeled **6U PXI**. *   On the right side, there are three stacked connection blocks:     *   Top block labeled **J3** (in a dashed outline) next to text **PXI Reserved**.     *   Middle block labeled **J2** next to text **64-Bit PCI and PXI Features**.     *   Bottom block labeled **J1** next to text **32-Bit PCI**.  **Connections and Labels** *   An arrow labeled **Ejector/Injector** points to a latch mechanism at the top right corner of the **6U PXI** module. *   A line connects the top right corner of the **6U PXI** module to the **J3** block area.](.pxi-1-hardware-specification-rev2-3/1e163200141a06dbaad750ac34e22c240c795a2bfe50d104ce7eb80c634ecb05.jpg)

Figure 2-1. PXI Peripheral Module Form Factors and Connectors

Figure 2-2 presents an example of a typical PXI system to help illustrate the following keywords (in italics). A PXI system is composed of a chassis that supports the PXI backplane and provides the means for supporting the system controller module and the peripheral modules. The chassis must have one system slot and may have one or more peripheral slots. Any number of controller expansion slots may be available to the left of the system slot. The optional star trigger controller, when used, must reside next to the system controller module. If a star trigger controller is not used in a system, a peripheral module can be installed in the slot next to the system controller module. The backplane carries the interface connectors (P1, P2, ...) and provides the interconnection between the controller and peripheral modules. A maximum of seven peripheral modules can be used in a single 33 MHz PXI bus segment, and a maximum of 4 peripheral modules can be used in a single 66 MHz PXI bus segment. PCI-PCI bridges can be used to add bus segments for additional peripheral slots.

![Controller Expansion Slots System Controller Module Peripheral Modules Empty Slot Backplane P2 P1 Chassis 1 2 3 4 5 6 7 8 System Slot Star Trigger Controller or Peripheral Slot Seven Maximum Available Peripheral Slots](.pxi-1-hardware-specification-rev2-3/cf989739b58975065cd434a8422c15e1d6fd7fcf26533ffd2bb3509355cb1930.jpg)

Figure 2-2. Example of a 33 MHz 3U PXI System (Single Bus Segment)

# 2.1.1 Chassis Supporting Stacking 3U Modules in a 6U Slot

For efficient use of 3U modules in a 6U chassis, 6U chassis can support stacking two 3U modules in a single 6U slot. This allows one 3U module to be plugged into the P1/P2 position of a 6U slot and another 3U module to be plugged into the P4/P5 position of the same 6U slot simultaneously. A 6U PXI chassis may have any number of 6U slots that support this feature.

Electrically this configuration is accomplished by populating connectors in the P4 and P5 positions of the 6U backplane and routing them as you would P1/P2. PCI bridging is required on the 6U backplane between the PCI bus residing on the P1 and P2 connectors and the PCI bus residing on the P4 and P5 connectors if PCI bus length and loading requirements cannot be met. PCI bridging between the PCI bus residing on the P1 and P2 connectors and the PCI bus residing on the P4 and P5 connectors is not allowed on the system controller module.

Mechanically this configuration can be accomplished by making use of center extrusions fixed within the chassis to physically support the insertion, extraction, and mounting of the lower and upper 3U modules residing in a 6U slot. Alternatively, this may be accomplished mechanically by a stacking adapter attached to the two 3U modules prior to insertion into the 6U slot. Figure 2-3 shows an example of a 6U chassis that supports stacking 3U modules.

![This diagram illustrates a chassis slot layout with top and bottom rows of numbered slots, organized into vertical columns.  **Top Row and Brackets:** *   **Left:** A bracket labeled 'Controller Expansion Slots' covers slot 14 (diamond) and slot 15 (circle). *   **Middle:** A bracket labeled 'Slots Supporting 3U Stacking' covers slot 16 (circle) and slot 17 (circle). *   **Right:** A bracket labeled '3U Stacking Not Supported' covers slot 18 (circle).  **Bottom Row:** *   **Left:** Slot 1 (triangle) is connected by an arrow to the text 'System Slot'. *   **Next:** Slot 2 (diamond) is connected by an arrow to the text 'Star Trigger Controller or Peripheral Slot'. *   **Rest:** Slots 3 through 13 are circles numbered sequentially from left to right.  **Vertical Columns and Connections:** The vertical columns align the top and bottom slots, containing specific module blocks: *   **Column 1 (under Slot 1):** Contains blocks labeled 'P2' (top) and 'P1' (bottom). To the left of this column are vertical dashed lines. *   **Column 2 (under Slot 2):** Contains blocks 'P5' and 'P4' (top section) and 'P2' and 'P1' (bottom section). *   **Column 3 (under Slot 3/Top Slot 16):** Contains blocks labeled '3U Module' (top) and '3U Module' (bottom). *   **Column 4 (under Slot 4/Top Slot 17):** Contains blocks labeled '3U Module' (top) and '3U Module' (bottom). *   **Column 5 (under Slot 5/Top Slot 18):** Contains a block labeled '6U Module'. *   **Columns 6-11 (under Slots 7-12):** Six vertical columns, each containing a block labeled '6U Module'. *   **Column 12 (under Slot 13):** Contains blocks 'P2' (top) and 'P1' (bottom).](.pxi-1-hardware-specification-rev2-3/b7bfeda07cf2cb9403b21a5d25ea4d4b61e344aa7b3796fbf5e1fb457ad1c75f.jpg)

Figure 2-3. Example of a 6U Chassis that Supports Stacking 3U Modules

# 2.1.2 System Slot Location

PXI defines the system slot location to be on the left end of the PCI bus segment in a basic PXI system. This defined arrangement is a subset of the numerous possible configurations allowed by CompactPCI (a CompactPCI system slot may be located anywhere on a backplane). Defining a single location for the system slot simplifies integration and increases the degree of compatibility between PXI controllers and chassis. Furthermore, the PXI Hardware Specification requires that if necessary the system controller module should expand to the left into what are defined as controller expansion slots. Expanding to the left prevents system controllers from using up valuable peripheral slots.

PXI also defines the location of a star trigger controller slot that can accept a peripheral module or a special star trigger module that can provide individual triggers to all other peripheral modules. The star trigger signals are routed from the star trigger slot to each peripheral slot on all PXI backplanes.

# 2.1.3 Additional Mechanical Features

All mechanical specifications defined in PICMG 2.0 R3.0 (CompactPCI Specification) apply directly to PXI systems; however, PXI includes additional requirements that simplify system integration. Forced cooling in a PXI chassis is required and the airflow direction is defined. Environmental testing for operating and storage temperature ratings of all PXI products is required and must be clearly documented by suppliers.

# 2.1.4 Interoperability with CompactPCI

Interoperability among PXI compatible products and standard CompactPCI products is a very important feature provided by this specification. Many PXI-compatible systems will require components that do not implement PXI-specific features. For example, a user may want to use a standard CompactPCI network interface module in a PXI chassis. Likewise, some users may choose to use a PXI compatible module in a standard CompactPCI chassis. In these cases, the user will not be able to use PXI-specific functions but will still be able to use the basic functions of the module. Note that interoperability between PXI-compatible products that use the J2 connector for PXI-defined signals and other application-specific implementations of CompactPCI chassis (which may define other signal definitions for sub-buses on the P2 backplane connector) is not guaranteed. Of course, both CompactPCI and PXI leverage the PCI local bus, thereby ensuring software and electrical compatibility as depicted in Figure 2-4.

![The diagram is titled **PCI Electrical and Software Compatibility** at the top. It is enclosed within a large outer box with a dashed border. Inside this larger container, there is a smaller inner box with a dashed border labeled **Full PXI Feature Set**, which encompasses the **PXI Chassis** and **PXI Peripheral Module** blocks.  The diagram features four labeled blocks and their connections:  *   **PXI Chassis** (a tall vertical rectangle on the left) *   **PXI Peripheral Module** (a horizontal rectangle in the upper center) *   **CompactPCI Peripheral Module** (a horizontal rectangle in the lower center) *   **CompactPCI Chassis** (a tall vertical rectangle on the right)  The connections (arrows) are as follows: *   An arrow points left from **PXI Peripheral Module** to **PXI Chassis**. *   An arrow points right from **PXI Peripheral Module** to **CompactPCI Chassis**. *   An arrow points left from **CompactPCI Peripheral Module** to **PXI Chassis**. *   An arrow points right from **CompactPCI Peripheral Module** to **CompactPCI Chassis**.](.pxi-1-hardware-specification-rev2-3/6d78254ae255e26c6f625ba66cdd596edbb526c1e7b733397fd5107df63a35b1.jpg)

Figure 2-4. PXI and CompactPCI Interoperability

# 2.2 Electrical Architecture Overview

Many instrumentation applications require system timing capabilities that cannot be directly implemented across standard desktop computer backplanes such as ISA, PCI, or PCMCIA. PXI uses the standard PCI bus and adds specific signals for instrumentation including bused trigger lines, slot-specific triggers, a dedicated system clock, and slot-to-slot local buses to address the need for advanced timing, synchronization, and side-band communication.

# 2.2.1 Peripheral Component Interconnect (PCI) Features

PXI offers the same performance features defined by the desktop PCI specification, with one notable exception. A PXI system can have up to eight slots per 33 MHz segment (one system slot and seven peripheral slots), whereas a desktop PCI system can have only five per 33 MHz segment (one motherboard or system slot and four peripheral slots). Similarly, a PXI system can have up to five slots per 66 MHz segment (one system slot and four peripheral slots), whereas a desktop PCI system can have only three per 66 MHz segment (one motherboard or system slot and two peripheral slots). The capability to have three additional 33 MHz peripheral slots and two additional 66 MHz peripheral slots is defined in the CompactPCI specification upon which PXI draws. Otherwise, all the features of PCI transfer into PXI:

33/66 MHz performance
32-bit and 64-bit data transfers
132 Mbytes/s (32-bit, 33 MHz) to 528 Mbytes/s (64-bit, 66 MHz) peak data rates
System expansion via PCI-PCI bridges
3.3V migration
Plug and Play capability

Similar to the PCI specification, it is recommended that PXI modules do not have their internal registers mapped to PCI I/O Space. I/O Space is limited, fragmented, and increasingly more difficult to guarantee allocation.

# 2.2.2 Local Bus

The PXI local bus is a daisy-chained bus that connects each peripheral slot with its adjacent peripheral slots to the left and right. Thus, the right local bus of a given peripheral slot connects to the left local bus of the adjacent slot, and so on. Each local bus is 13 lines wide and can be used to pass analog signals between modules or to provide a high-speed side-band digital communication path that does not affect the PXI bandwidth.

Local bus signals can range from high-speed TTL signals to analog signals as high as 42 V. Keying of adjacent modules is implemented by initialization software that prohibits the use of incompatible modules. This software uses the configuration information specific to each peripheral module to evaluate compatibility before enabling local bus circuitry. This method provides a flexible means for defining local bus functionality that is not limited by hardware keying.

The local bus lines for the leftmost peripheral slot of a PXI backplane are used for the star trigger. Figure 2-5 schematically shows a complete PXI system demonstrating the local buses.

![Based on the provided diagram, here are the labeled blocks and their connections:  **Labeled Blocks:** *   System Controller Slot (1) *   Star Trigger/Peripheral Slot (2) *   Peripheral Slot (3) *   Peripheral Slot (4) *   Peripheral Slot (N-1) *   Peripheral Slot (N) *   External Backplane Interface  **Connections:** *   **Star Triggers:** Lines originate from the left side of **Star Trigger/Peripheral Slot (2)** and fan out to the top inputs of **Star Trigger/Peripheral Slot (2)**, **Peripheral Slot (3)**, **Peripheral Slot (4)**, **Peripheral Slot (N-1)**, and **Peripheral Slot (N)**. *   **PCI Arbitration and Clock Signals:** Lines originate from the right side of **System Controller Slot (1)** and route underneath **Star Trigger/Peripheral Slot (2)** to connect with upward-pointing arrows to the bottom inputs of **Peripheral Slot (3)**, **Peripheral Slot (4)**, **Peripheral Slot (N-1)**, and **Peripheral Slot (N)**. *   **Local Bus:**     *   **Star Trigger/Peripheral Slot (2)** connects to **Peripheral Slot (3)** via a double-headed arrow labeled 'Local Bus'.     *   **Peripheral Slot (3)** connects to **Peripheral Slot (4)** via a double-headed arrow labeled 'Local Bus'.     *   **Peripheral Slot (4)** connects to **Peripheral Slot (N-1)** via a double-headed arrow with ellipses 'oooo'.     *   **Peripheral Slot (N-1)** connects to **Peripheral Slot (N)** via a double-headed arrow labeled 'Local Bus'. *   **External Connection:** **Peripheral Slot (N)** connects to **External Backplane Interface** via a double-headed arrow.](.pxi-1-hardware-specification-rev2-3/de677eefdd15c8953bd06743f25a4b46248cbfcf1563d509755b609dc02cab0c.jpg)

Figure 2-5. PXI Local Bus Routing

# 2.2.3 System Reference Clock

The PXI 10 MHz system clock (PXI\_CLK10) is distributed to all peripheral modules in a system. This common reference clock can be used for synchronization of multiple modules in a measurement or control system. The PXI backplane specification defines implementation guidelines for PXI\_CLK10. As a result, the low-skew qualities afforded by this reference clock make it ideal for precise multimodule synchronization by using trigger bus protocols to qualify individual clock edges.

# 2.2.4 Trigger Bus

The eight PXI-bused trigger lines are highly flexible and can be used in a variety of ways. For example, triggers can be used to synchronize the operation of several different PXI peripheral modules. In other applications, one module can control carefully timed sequences of operations performed on other modules in the system. Triggers may be passed from one module to another, allowing precisely timed responses to asynchronous external events that are being monitored or controlled. The number of triggers that a particular application requires varies with the complexity and number of events involved.

# 2.2.5 Star Trigger

The PXI star trigger bus offers ultra-high performance synchronization features to users of PXI systems. The star trigger bus implements a dedicated trigger line between the first peripheral slot (adjacent to the system slot) and the other peripheral slots. A star trigger controller can be installed in this slot and can be used to provide very precise trigger signals to other peripheral modules. Systems that do not require this advanced trigger can install any standard peripheral module in this slot. Through the required use of line-length equalization techniques for routing the star triggers, PXI systems can meet demanding triggering requirements for which bused triggers are not appropriate. Note that the star trigger can be used to communicate information back to the star trigger controller, as in the case of reporting a slot’s status, as well as responding to information provided by the star trigger controller.

This trigger architecture for PXI gives two unique advantages in augmenting the bused trigger lines. The first advantage is a guarantee of a unique trigger line for each module in the system. For large systems, this eliminates the need to combine multiple module functions on a single trigger line or to artificially limit the number of trigger times available. The second advantage is the low-skew connection from a single trigger point. The PXI backplane defines specific layout requirements such that the star trigger lines provide matched propagation time from the star trigger slot to each module for very precise trigger relationships between each module.

# 2.2.6 System Expansion with PCI-PCI Bridge Technology

A PXI system can be built with more than one bus segment by using standard PCI-PCI bridge technology. The bridge device takes up one PCI load on each of the bus segments that it links together. Thus, a 33 MHz system with two bus segments offers 13 expansion slots for PXI peripheral modules.

$$
(2 \text {   bus   segments }) \times (8 \text {   slots   per   segment }) - (1 \text {   system   controller   slot })
$$

$$
- (2 \text {   slots   for   PCI - PCI   Bridge }) = 1 3 \text {   available   expansion   slots }
$$

Similarly, a three-bus segment 33 MHz system would offer 19 expansion slots for PXI peripheral modules.

The trigger architecture defined by PXI has implications for systems with multiple bus segments. The PXI trigger bus provides connectivity within a single bus segment and does not allow physical connection to an adjacent bus segment. This maintains the high performance characteristics of the trigger bus and allows multisegment systems to partition instruments into logical groups. Multiple segments may be logically linked by providing buffers between physical segments. The star trigger provides the means to independently access all 13 peripheral slots in a two-segment system for applications in which a high number of instruments require synchronization and controlled timing. In PXI systems where there are more than two segments, it is recommended that the star triggers are only routed to the slots in the first two segments, but other routings are allowed. Figure 2-6 shows the PXI trigger architecture for a PXI system with two bus segments.

![**Labeled Blocks:** *   System Controller *   Star Trigger Controller *   PXI Star Trigger *   Slot 1 *   Slot 2 *   Slot 3 *   oo *   Slot 7 *   Slot 8 *   Slot 9 *   Slot 10 *   oo *   Slot 16 *   PCI-PCI Bridge *   Bridge Controls Bus Segment 2 *   PXI Trigger Bus (Segment 1) *   PXI Trigger Bus (Segment 2)  **Connections:** *   **PXI Star Trigger:** Multiple lines originating from the top-left area connect with downward arrows to the top of **Slot 3**, **Slot 7**, **Slot 8**, **Slot 10**, and **Slot 16**. *   **PCI-PCI Bridge:** A double-headed horizontal arrow connects **Slot 8** and **Slot 9**. *   **PXI Trigger Bus (Segment 1):** Double-headed vertical arrows connect the bottom of **Slot 1**, **Slot 2**, **Slot 3**, **Slot 7**, and **Slot 8** to this bus. *   **PXI Trigger Bus (Segment 2):** Double-headed vertical arrows connect the bottom of **Slot 9**, **Slot 10**, and **Slot 16** to this bus.](.pxi-1-hardware-specification-rev2-3/b78678e415f7be949889e89a931a6ae6c6610d30854dc9929888a37e1392280a.jpg)

Figure 2-6. PXI Trigger Architecture for Two Bus Segments

# 2.2.7 32-Bit PCI and Rear I/O

Many PXI modules only require 32-bit PCI support which could be used in lower cost chassis that do not support 64-bit PCI. Additionally since the upper 32-bit PCI signals will not be used in these chassis, suppliers of PXI chassis may decide to use these signals for rear I/O purposes on the system slot. Section 6 of this specification defines chassis that do not support 64-bit PCI. It also defines system controller modules which support supplier specific rear I/O.

# 2.3 Software Architecture Overview

Revision 2.0 and earlier of the PXI Specification included software requirements for PXI modules, chassis, and systems. From PXI Hardware Specification revision 2.1 and higher, the PXI Systems Alliance maintains a separate software specification for PXI modules, chassis, and systems. PXI modules, chassis, and systems developed to comply with this PXI Hardware Specification must also comply with the PXI Software Specification. The Software Architecture Overview is now covered in the PXI Software Specification.

# 3. Mechanical Requirements

This section discusses the additional mechanical requirements for PXI systems. It discusses the location of the system slot, the interoperability of the controller with the chassis, the PXI logo, environmental testing, cooling, grounding, and guidelines for minimizing electromagnetic interference (EMI).

# 3.1 CompactPCI Mechanical Requirements

Both 3U (100 by 160 mm, or 3.94 by 6.3 in.) and 6U (233.35 by 160 mm, or 9.19 by 6.3 in.) form factor modules can implement PXI features as defined in Section 4, Electrical Requirements.

RULE: All mechanical requirements defined in the CompactPCI specification (PICMG 2.0 R3.0) SHALL apply to 3U and 6U PXI compatible modules.

The following sections define additional mechanical requirements and recommendations that are included to ease system integration.

# 3.2 Maximum Number of Slots

Since the CompactPCI specification accommodates 31 slots based on the definition of the Geographical Addressing pins, it is necessary to limit a PXI chassis to 31 slots.

RULE: A PXI chassis SHALL NOT have more than 31 slots.

# 3.3 System Slot Location and Rules

All CompactPCI and PXI compatible systems require a backplane/chassis and a system controller module in the system slot. This requirement allows users to mix and match different controllers with different chassis. However, because the CompactPCI specification allows a system slot to be located anywhere relative to peripheral slots, the possibility for confusion and incompatibility exists. To address this problem the following rules must be followed for PXI-compatible systems:

RULE: The system slot SHALL be defined as the leftmost PXI slot in a basic single bus segment PXI chassis/backplane. For documentation purposes this slot is counted as one controller slot.

RECOMMENDATION: If the system controller module requires more than one slot width, it SHOULD extend to the LEFT of the system slot in full slot increments (one slot equals 20.32 mm, or 0.8 in.) into additional controller expansion slots.

OBSERVATION: In a basic PXI system these additional controller slots are for physical expansion of the system controller module only and cannot support peripheral modules. These slots DO NOT have connectors that interface to the PCI bus routed on the backplane.

OBSERVATION: Extending the system slot module to the LEFT allows all PXI peripheral slots to be utilized.

RECOMMENDATION: The system controller module SHOULD NOT extend to the RIGHT of the system slot into peripheral slots.

OBSERVATION: If a system controller module expands to the right, the number of usable PXI peripheral slots may be compromised and access to the star trigger slot may be eliminated.

RULE: Every PXI system controller module SHALL clearly document how many controller expansion slots (to the left of the system slot) and peripheral slots it occupies.

RULE: Every PXI chassis SHALL clearly document how many peripheral and controller expansion slots are available.

OBSERVATION: The two preceding rules help ensure that end users can easily determine whether a particular controller-chassis pair is compatible and how many peripheral slots are available.

Figure 3-1 depicts slot designations in a PXI system.
![P2 P1 1 2 3 4 5 6 7 8 Three Controller Expansion Slots System Slot Star Trigger Controller Slot Seven Peripheral Slots](.pxi-1-hardware-specification-rev2-3/070af5c70f8209ba5904224c5c1eec3fa5168ad53c7d7d2f1497f34ec1fed6d8.jpg)

Figure 3-1. Example of PXI Slot Designations for a Chassis

# 3.4 Logos and Compatibility Glyphs

RULE: A PXI chassis SHALL clearly mark each physical slot with a unique number. The number SHALL be located within the compatibility glyph.

OBSERVATION: The preceding rule applies to a chassis with multiple bus segments as well as to a single-segment chassis.

PERMISSION: Vendors who are members of the PXI Systems Alliance MAY use the PXI logo as defined below on either the front panel or the injector/ejector handle of products claiming full compliance with the PXI Hardware Specification.

RULE: If the PXI logo is used, the vendor SHALL obtain a license to use the trademarked logo from the PXI Systems Alliance.

RULE: If the PXI logo is used, it SHALL NOT be altered in any way other than scale. The logo SHALL NOT incorporate any additions.

Figure 3-2 shows the PXI logo. Logo artwork as well as the license can be obtained from the PXI Systems Alliance once becoming a member.
![PXI™](.pxi-1-hardware-specification-rev2-3/63cd756ecf5c8663c8267d93e3e1a230899d5063921185fe6f795617a81df87f.jpg)

Figure 3-2. PXI Logo

PERMISSION: The PXI logo MAY be used as a substitute for the CompactPCI logo defined in PICMG 2.0 R3.0. Additionally, a product MAY display both the CompactPCI logo and the PXI logo.

RULE: Modules and backplanes SHALL use the compatibility glyphs as defined in the PICMG 2.0 R3.0 (CompactPCI specification).

RULE: Modules and backplanes SHALL use the glyph shown in Figure 3-3 (square at 45°) for the star trigger slot/module. This slot is always located next to the system slot. Because this slot can also support standard peripheral modules, the peripheral module glyph (circle) SHALL also be used for this slot.

![The image shows a black outline of a diamond shape on a white background.](.pxi-1-hardware-specification-rev2-3/29412fae7f46a09190674e01f636cdc882303780212dc8e0f700fb2ac7a7d18e.jpg)
Figure 3-3. Star Trigger Slot Glyph

RULE: Chassis and backplanes SHALL use the glyph shown in Figure 3-4 (vertical line) between slot numbers to indicate boundaries between PCI segments.

![The image displays three vertical black bars separated by white space.](.pxi-1-hardware-specification-rev2-3/76661d2c8fc6ff3de3c590028b9911ce23db0ff635e2c974ed0d0fbadd6f2bca.jpg)
Figure 3-4. PCI Segment Divider Glyph

# 3.5 Slot Numbering for 6U Chassis that Support 3U Stacking

The CompactPCI specification does not define chassis that support stacking 3U modules in a 6U slot. To make physical slot numbering of these systems explicit, the following rule applies:

RULE: 6U PXI Chassis that support stacking 3U modules in a 6U slot SHALL have their slots numbered, starting with the furthest slot to the left, with the number 1 below the slot. Continuing from left to right, the slots numbers SHALL be incremented by one until all slots have been numbered below the slot. Slots that support stacking 3U modules (P4 and P5 populated) SHALL have a number above the slot starting with one number higher than the highest number used below all the slots. Continuing from left to right on slots that support stacking 3U modules, the slot numbers SHALL be incremented by one until all slots that support stacking 3U modules have been numbered above the slot.

OBSERVATION: 6U PXI Chassis that support stacking 3U modules will not have slot numbers above slots that do not support stacking 3U modules.

Figure 3-5 depicts the slot numbering for a 6U chassis that supports stacking 3U modules.
![This block diagram depicts a chassis slot layout divided into three horizontal sections and vertical columns.  **Top Groupings and Slots:** *   **Controller Expansion Slots:** A bracket on the left covers the first three columns. *   **Slots Supporting 3U Stacking:** A central bracket covers the next five columns. Above these columns are numbered slots: a diamond labeled **14**, followed by circles **15**, **16**, **17**, and **18**. *   **3U Stacking Not Supported:** A bracket on the right covers the remaining five columns.  **Internal Blocks (Vertical Columns):** *   **P1/P2 Blocks:** All 13 vertical columns contain a bottom block labeled **P1** and a block directly above it labeled **P2**. *   **P4/P5 Blocks:** In the five central columns (aligned with top slots 14-18), there are additional blocks stacked above the P2 blocks: a block labeled **P4** and a top block labeled **P5**.  **Bottom Slots and Labels:** *   A row of numbered slots runs along the bottom: a triangle labeled **1**, a diamond labeled **2**, and circles **3** through **13**. *   **System Slot:** An arrow points from this text to the triangle labeled **1**. *   **Star Trigger Controller or Peripheral Slot:** An arrow points from this text to the diamond labeled **2**.](.pxi-1-hardware-specification-rev2-3/d6097634a5e9d019c630c1281a23faa4ca9396b5090b9d5c7c39d12e65fc8b06.jpg)

Figure 3-5. Example of Slot Numbering for a 6U Chassis that Supports 3U Stacking

# 3.6 Environmental Testing

RULE: PXI chassis, system controller modules, and peripheral modules SHALL be tested for storage and operating temperature ranges.

RECOMMENDATION: PXI chassis, system controller modules, and peripheral modules SHOULD be tested for humidity, vibration, and shock.

RECOMMENDATION: All environmental testing SHOULD be carried out according to the procedures described in IEC 60068.

RULE: Test results and reports generated for environmental testing SHALL be made available to end users of PXI systems. All manufacturers of PXI chassis, system controller modules, and peripheral modules SHALL supply operating and storage temperature ratings for their products.

RULE: If a manufacturer chooses to use environmental testing procedures other than those described in IEC 60068, then these procedures, in addition to the test results and reports, SHALL be documented and made available to the customer.

OBSERVATION: It is the system integrator’s responsibility to select modules and chassis appropriate for the application’s environmental requirements.

# 3.7 Cooling Specifications

# 3.7.1 Plug-in Module Requirements

RULE: Plug-in modules SHALL be designed to allow a suitable airflow path from bottom to top as shown in Figure 3-6.

![Technical line drawing of a mechanical assembly with vertical supports and dashed alignment lines (no text or symbols)](.pxi-1-hardware-specification-rev2-3/8333734d890cbe6f2c53ed94faafd260a3a291d35db133fb3fc660391be1c7a4.jpg)

Figure 3-6. Cooling Airflow Direction in a PXI System

RULE: Plug-in module manufacturers SHALL document and make available to the customer the nominal power dissipated by the module under normal operating conditions.

RECOMMENDATION: Single width 3U plug-in modules SHOULD NOT dissipate within the chassis more than 25 watts.

OBSERVATION: Single width 3U modules can dissipate more than 25 watts when used in a PXI chassis that can provide sufficient cooling for more than 25 watts per slot.

RECOMMENDATION: Single width 6U plug-in modules SHOULD NOT dissipate within the chassis more than 50 watts.

OBSERVATION: Single width 6U modules can dissipate more than 50 watts when used in a PXI chassis that can provide sufficient cooling for more than 50 watts per slot.

# 3.7.2 Chassis Requirements

RULE: Chassis SHALL provide active cooling that flows from the bottom to the top of a plugged-in module as shown in Figure 3-6.

RULE: Chassis manufacturers SHALL document and make available to the customer the maximum total wattage that a given chassis can dissipate and the maximum wattage dissipated for the worst-case slot. Furthermore, the manufacturer SHALL document and make available to the customer the specific test procedure used to determine these wattage values.

RULE: PXI chassis SHALL have filler panels installed in slots that do not have modules populated.

OBSERVATION: If filler panels are not installed in slots that do not have modules populated, then proper module cooling cannot be guaranteed.

# 3.8 Chassis and Module Grounding Requirements and EMI Guidelines

RULE: Chassis SHALL provide a direct (low-impedance) means for connecting the chassis ground to earth ground.

OBSERVATION: A grounding stud may be used to provide direct access to chassis ground.

RECOMMENDATION: As defined in PICMG 2.0 R3.0, PXI modules SHOULD use metalized shell connectors for EMI/RFI protection. The shell SHOULD be electrically connected to the front panel through a low impedance path in accordance with IEEE 1101.10.

RECOMMENDATION: PXI modules SHOULD be grounded according to the recommendations contained in section 4.4.

# 3.9 Regulatory Requirements

The following standards assure uniform performance and international portability of PXI systems and modules. Allowances are made for devices not intended for international sale. All regulatory compliance information must be clearly documented for the user. Subsequently issued standards or amendments to these standards shall apply.

# 3.9.1 Requirements for EMC

RULE: Testing SHALL be performed, either by the manufacturer or a competent laboratory, marked accordingly, and documented showing compliance to the following EMC standard(s).

IEC 61326-1:1998, Electrical equipment for measurement, control, and laboratory use—EMC requirements—Part I, General requirements1:

• Localized EMC standards may be substituted if sale and use are restricted accordingly.2

Use current edition of EN 55011, Group 1, Class A or Class B Limits, at 10 m.

Continuous unmonitored operation is assumed unless otherwise specified by manufacturer.

# 3.9.2 Requirements for Electrical Safety

RULE: Testing SHALL be performed, either by a competent organization or qualified manufacturer, marked accordingly, and documented showing compliance to the following electrical safety standard(s). Strictly extra low voltage (SELV) devices do not need formal agency testing, though the basic requirements still apply, such as material flammability specified, DC power outputs fused or limited, and so on.

IEC 1010-1:1990 + A1:1992, Safety requirements for electrical equipment for measurement, control, and laboratory use—Part 1, General requirements:

IEC 950 and amendments are acceptable for applications restricted to the office use only.
• Localized safety standards may be substituted if sale and use are restricted accordingly. 1

# 3.9.3 Additional Requirements for Chassis

RULE: Chassis manufacturers, or a designated party, SHALL demonstrate EMC compliance with a commonly available controller. At minimum the controller SHALL apply a 33 MHz clock to the backplane, or higher as the technology commonly supports, unless the marketing and use of the chassis is restricted to specific kinds of system controllers or platforms. A reasonably common processor speed is sufficient for this test. The complete controller system, including hard drive, floppy drive, serial, parallel, keyboard, mouse, and video ports (as offered with the controller) will be exercised with typical peripherals. Filling remaining slots, if any, is not required. Special shielding or suppression options, if used to achieve compliance, SHALL be documented and available to the user.

RULE: The chassis SHALL be qualified for electrical safety as listed previously. Manufacturer claims of safety compliance are not sufficient without independent verification and regular inspection by a competent agency.

# 4. Electrical Requirements

This chapter discusses the detailed electrical requirements for developing PXI-compatible peripheral modules, controllers, and backplanes. It discusses all signals required for PXI systems and their related implementation requirements. It also discusses appropriate connector pinouts, power supply requirements, and 6U form factor implementation issues.

# 4.1 PXI Signal Groups

This section details all the signals required for PXI systems, including those mapped directly from CompactPCI on P1/J1, the 64-bit signals duplicated on P2/J2, and the PXI-specific signals located on P2/J2. The PXI-specific signals include those required for the trigger bus, the reference clock, the local buses, and the star trigger.

# 4.1.1 P1/J1: Signals

RULE: All signals on the J1 connector of a PXI module and the mating P1 connector of a PXI backplane SHALL meet all the requirements of the PICMG 2.0 R3.0 specification (CompactPCI) for both peripheral modules and system modules.

In order for a system controller module to function correctly in a PXI or CompactPCI system, the BIOS of the controller must have its interrupt routing table configured to allow for the AD[25:31] to IDSEL mapping with associated PCI interrupt routing as defined in the PICMG 2.0 R3.0 specification (CompactPCI). Connecting the IDSEL lines of backplane PCI devices or PCI-PCI bridges on the first PCI segment to address lines other than AD[25:31] or not connecting these devices to the correct ordering of PCI interrupt lines could cause the PXI or CompactPCI system to function incorrectly. Also, since the PCI-PCI bridge specification was written assuming a bridge would be placed on a PCI plug in card, care must be taken to route the interrupts on the secondary side of the bridge depending on which AD[25:31] is used for the bridge’s IDSEL.

RULE: Backplane PCI devices, PCI-PCI bridges, and peripheral slots on the first PCI segment SHALL have their IDSEL lines connected to one of AD[25:31].

RULE: Backplane PCI devices, PCI-PCI bridges, and peripheral slots on the first PCI segment SHALL have their INTA#, INTB#, INTC#, and INTD# pins routed to the system slot’s INTA#, INTB#, INTC#, INTD# pins depending on which AD[25:31] line their IDSEL line is connected to in accordance with the PICMG 2.0 R3.0 specification (CompactPCI).

# 4.1.2 P2/J2: Signals

The PICMG 2.0 R3.0 (CompactPCI) specification defines an open pinout for P2/J2, which allows for custom back-panel I/O implementations. This pinout allows sub-buses on the P2 section of the backplane.

The PXI back-panel I/O definition of signals on the P2/J2 connector consists of signals mapped from the CompactPCI 64-bit connector pinout and new signals defined by this specification. The only differences between the PXI pinout and the CompactPCI 64-bit connector pinout are on signals that are reserved or not used in the CompactPCI specification (PICMG 2.0 R3.0). Therefore, all modules that meet the requirements of the CompactPCI 64-bit specification will function in a PXI system. Furthermore, all PXI modules will work in a system that meets the requirements of the CompactPCI 64-bit specification, but without the complete set of benefits of PXI.

# 4.1.2.1 Signals from CompactPCI 64-bit Connector Specification

To allow for applications that require higher bandwidth than 32-bit PCI can provide, PXI has incorporated the pieces of the CompactPCI 64-bit specification that are necessary to support 64-bit operation and has used the remaining resources for instrumentation. This section describes the signals that are mapped from the CompactPCI 64-bit specification. The remaining signals are described in subsequent sections.

# System Slot

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the system slot: GND, V(I/O), AD[32:63], PAR64, C/BE[4:7]#, DEG#, FAL#, PRST#, SYSEN#, CLK[1:6], GNT[1:6]#, REQ[1:6]#, GA0-GA4, SMB\_ALERT#, SMB\_SCL, SMB\_SDA, and the RSV pins.

RULE: The system slot interface in a PXI system SHALL be as defined in the PICMG 2.0 R3.0 Specification (CompactPCI).

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV (bused reserved) in the CompactPCI 64-bit pinout for directly accessing PXI features on system modules.

# Peripheral Module

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the peripheral slots: GND, V(I/O), AD[32:63], PAR64, C/BE[4:7]#, GA0-GA4, and UNC.

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV, CLK[1:6], GNT[1:6]#, REQ[1:6]#, and RSV in the CompactPCI 64-bit pinout for instrumentation features on peripheral modules. Note that the CLK[1:6], GNT[1:6]# and REQ[1:6]# signals are not implemented on CompactPCI peripheral modules and slots.

# Backplane

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the backplane: GND, V(I/O), AD[32:63], PAR64, C/BE[4:7]#, DEG#, FAL#, and PRST#, SYSEN#, UNC, GA0-GA4, SMB\_ALERT#, SMB\_SCL, SMB\_SDA, and the RSV pins.

RULE: As in the CompactPCI specification, the backplane SHALL route CLK[1:6], GNT[1:6]#, and REQ[1:6]# from the system slot to the appropriate pins of the J1 connectors on the peripheral slots.

RULE: The backplane SHALL leave all the RSV lines on the system slot disconnected.

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV, CLK[1:6], GNT[1:6]#, REQ[1:6]#, and RSV (reserved) on peripheral slots and the BRSV pins on the system slot in the CompactPCI 64-bit pinout for instrumentation features on the backplane. The CLK[1:6], GNT[1:6]# and REQ[1:6]# signals are not implemented on CompactPCI backplane peripheral slots.

OBSERVATION: The PXI implementation of back-panel I/O routes all of the bused reserved signals from the CompactPCI 64-bit pinout as bused signals on the PXI backplane. However, most of the signals are not reserved in the PXI signal definition and are explained in section 4.1.2.5, Trigger Bus.

# 4.1.2.2 PXI Bused Reserved Signals

# System Slot

The following signals are reserved for future PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A system controller module SHALL NOT connect to the PXI\_BRSV signals.

# Peripheral Slots

The following signals are reserved for PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A peripheral module SHALL NOT connect to the PXI\_BRSV signals.

# Backplane

The following signals are reserved for PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A backplane SHALL bus each PXI\_BRSV signal to each slot.

OBSERVATION: PXI\_BRSV signals are implemented on the backplane exactly like CompactPCI BRSV signals.

# 4.1.2.3 Local Buses

PXI implements a daisy-chained local bus between adjacent peripheral modules. The local bus is a user-definable bus (13 lines wide) that can be used for a wide variety of applications. The range of applications may vary from passing an analog signal between two modules to high-speed data movement that does not affect the PXI bandwidth. For most slots, the functionality of the local bus is user-definable; however, there are specific implementations that the PXI Hardware Specification defines.

Note that the system controller module does not implement the local bus as it uses those pins for PCI arbitration and clocking functionality. The slot adjacent to the system slot uses its available local bus left signals for the star trigger functionality defined later. Similarly, the rightmost slot of the bus has no slot to its right; hence, the local bus right pins can either be unused or routed for a chassis-specific implementation. One example of chassis-specific implementation is routing the local bus to another adjacent PXI bus segment. The remainder of the slots can use the local bus for any specified purpose. Refer to Figure 2-5 for a diagram of local bus routing.

The following rules apply to all implementations of the local bus:

# Peripheral Module

RULE: A peripheral module SHALL NOT drive more than ± 42 V onto any local bus line.

RULE: A peripheral module SHALL NOT drive more than 200 mA DC current into any local bus line.

PERMISSION: A peripheral module MAY connect its local bus left to its local bus right if passing the local bus to an additional module is required. This connection should be performed with caution because the length and/or characteristic impedance specifications of the local bus might be violated.

PERMISSION: On a peripheral module, a local bus signal MAY be connected to ground.

OBSERVATION: The preceding permission allows local bus implementations to have improved grounding and/or shielding.

RULE: On a peripheral module, if a local bus signal is not connected to ground, it SHALL power up in a high-impedance state. All local bus signals (except grounded ones) SHALL remain in a high-impedance state until system configuration software has determined that the local bus signals are compatible with the chassis and other peripheral modules in the system.

PERMISSION: A peripheral module MAY pull-up a local bus signal to V (I/O) to prevent an input from powering up in an unstable state.

RULE: Each peripheral module SHALL have a maximum input leakage current of 100 μA on each local bus line.

# Backplane

RULE: On each bus segment, a backplane SHALL route PXI\_LBR[0:12] from each slot in column A of Table 4-1 to the PXI\_LBL[0:12] of the corresponding slot in column B, provided that both slots exist on the bus segment.

Table 4-1. Local Bus Routings

<table><tr><td>A</td><td>B</td></tr><tr><td>IDSEL = AD31</td><td>IDSEL = AD30</td></tr><tr><td>IDSEL = AD30</td><td>IDSEL = AD29</td></tr><tr><td>IDSEL = AD29</td><td>IDSEL = AD28</td></tr><tr><td>IDSEL = AD28</td><td>IDSEL = AD27</td></tr><tr><td>IDSEL = AD27</td><td>IDSEL = AD26</td></tr><tr><td>IDSEL = AD26</td><td>IDSEL = AD25</td></tr></table>

OBSERVATION: If a slot does not exist on the bus segment due to the AD[25:31] being used for the IDSEL of a backplane PCI device or a PCI-PCI bridge, then other local bus routings are possible provided only physically adjacent slots are connected.

OBSERVATION: There is no local bus connection to the system slot.

RULE: The backplane SHALL NOT provide any termination or buffering of local bus signals. Each signal SHALL be implemented as a direct connection between adjacent peripheral slots.

RULE: The signal length of local bus signals between slots SHALL be less than 3 in. and SHALL be matched within 1 in. between all local bus traces. The characteristic impedance of each trace SHALL be $6 5 \Omega \pm 1 0 \%$ .

PERMISSION: The backplane MAY route the local bus between two bus segments provided the signal length rule is met.

RULE: Bus segment boundaries SHALL be documented.

OBSERVATION: Documenting bus segment boundaries allows users to optimize systems by grouping boards that frequently talk to each other on the same segment.

PERMISSION: A slot at the end of a PXI segment or next to the system slot has one local bus that is not routed to another peripheral slot. The backplane MAY route these local buses for other uses.

RULE: A star trigger slot SHALL NOT implement a local bus left. Instead, the remaining pins SHALL be routed to support the star triggers.

RULE: If a chassis implements an external backplane interface with the local bus right of a slot at the end of a PXI segment, it SHALL be the highest numbered slot in the chassis.

OBSERVATION: A chassis will have at most one slot with an external backplane interface.

# 4.1.2.4 Reference Clock: PXI\_CLK10

The PXI backplane is responsible for providing a common reference clock for synchronization of multiple modules in a measurement or control system. The variable frequency of the PCI system clock limits its usefulness in this application. PXI\_CLK10 is a 10 MHz clock provided independently to each peripheral slot. PXI\_CLK10 can be used to run multiple modules in synchronization from a common reference. The low skew qualities make it ideal for qualifying trigger protocols.

# Backplane

RULE: The PXI\_CLK10 provided by the backplane SHALL be a 10 MHz TTL signal. Its accuracy SHALL be ± 100 ppm or better over the specified operating temperature and time.

OBSERVATION: Because of drift over time, the oscillator chosen MAY need to be 50 ppm accurate or better to meet the requirement of the preceding rule.

RULE: The PXI\_CLK10 signal SHALL have a 50% ± 5% duty cycle when measured at the 2.0 V transition point.

RULE: The clock to each peripheral slot SHALL be driven by an independent buffer that has a source impedance matched to the backplane.

RULE: The backplane SHALL provide for a skew of less than 1 ns between slots.

RECOMMENDATION: The use of low cost PLL buffers for driving the clock to each slot may lead to excessive jitter and therefore SHOULD NOT be used.

RECOMMENDATION: A backplane SHOULD allow PXI\_CLK10 to be derived from an external source to allow for a more accurate reference.

OBSERVATION: The star trigger slot has defined a pin, called PXI\_CLK10\_IN, for providing an external clock.

RULE: If a backplane allows PXI\_CLK10 to be derived from an external source, then the backplane SHALL have a 1.5K Ohm ± 5% pull-down resistor on the PXI\_CLK10\_IN signal and receiving circuitry of this signal on the backplane SHALL be TTL compatible and 5V tolerant.

RULE: If the PXI\_CLK10 is switched between sources, the minimum pulse width created SHALL be no less than 30 ns and the minimum time between successive edges of the same polarity SHALL be no less than 80 ns.

OBSERVATION: The preceding rule is intended to prevent a state machine from being corrupted by glitches in the clock during transition.

OBSERVATION: One implementation of a circuit for transitioning between sources could have the ability to select between external source, internal oscillator, and a pull-up to feed the input of a fanout buffer. The circuitry would perform the following steps in order:

1. Detect the external source.
2. Enable the pull up resistor while the internal clock is in the high state.
3. Disable the internal oscillator while in a subsequent high state.
4. Enable the external source while it is in a high state.
5. Disable the pull-up resistor in a subsequent high state of the external source.

# Peripheral

RULE: Peripheral modules’ PXI\_CLK10 receivers SHALL be 5V tolerant.

# 4.1.2.5 Trigger Bus

The PXI trigger bus provides intermodule synchronization and communication. The trigger bus lines can be used for trigger or clock transmission. A few standard triggering protocols are defined to facilitate interoperability, but use of the trigger bus is not limited to the defined protocols. The PXI trigger bus lines may be used as general purpose intermodule bused lines using other manufacturer-defined protocols.

The PXI trigger bus consists of the following eight signals: PXI\_TRIG[0:7].

# Clock Transmission

Variable frequency clock transmission allows multiple modules to share a timebase that is not a derivative of the PXI\_CLK10. For example, two data acquisition modules using a 44.1 kS/s CD audio sampling rate could share a clock that is a multiple of the 44.1 kHz. Type A drivers, defined later, prevent degradation of the clock jitter over the bused transmission medium.

PERMISSION: PXI\_TRIG[0:7] MAY be used for variable frequency clock transmission.

RECOMMENDATION: To facilitate interoperability between sources and receivers of a variable frequency clock, PXI\_TRIG[7] SHOULD be used to source and receive such clocks.

# PXI Trigger Protocols

Some standard protocols are defined in the following sections.

# PXI Asynchronous Trigger

The PXI asynchronous trigger protocol is a single-line broadcast trigger. Figure 4-1 and Table 4-2 show the timing parameters.

RULE: A PXI asynchronous trigger source SHALL meet the timing requirements listed in Table 4-2.

![T_H V_OH = 2.0 V V_OH = 0.8 V T_L](.pxi-1-hardware-specification-rev2-3/eb4f2d9793b4803c4fbc1d3cf80588c1919e3c07cd1a2d49fdd83f0670cd4e8e.jpg)

Figure 4-1. PXI Asynchronous Trigger Timing

Table 4-2. PXI Asynchronous Trigger Timing Parameters

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td></tr><tr><td> $T_h$ </td><td>pulse width high</td><td>18 ns</td><td>—</td></tr><tr><td> $T_l$ </td><td>pulse width low</td><td>18 ns</td><td>—</td></tr><tr><td colspan="4">Note: The pulse width is measured at the driver with a 50 pf equivalent load.</td></tr></table>

OBSERVATION: The preceding rule guarantees PXI asynchronous trigger receivers a minimum of 10 ns pulse widths on PXI asynchronous trigger pulses.

# PXI Synchronous Trigger

The PXI synchronous trigger protocol can be used to synchronize PXI\_CLK10 derived timed operations on module clusters. A PXI\_TRIG line is driven by a module and the participating modules respond to this line synchronously at the next PXI\_CLK10 rising edge. The reference clock is PXI\_CLK10.

Figure 4-2 shows PXI synchronous trigger timing.
![PXI_CLK Output Input V_test V_test T_val T_hd V_test T_su T_h](.pxi-1-hardware-specification-rev2-3/ada5ad62e463b4e8da764a7e0b52d727c4a1732e1f530148fb200fcbbd599772.jpg)

Figure 4-2. PXI Synchronous Trigger Timing

RULE: A PXI synchronous trigger source SHALL meet the timing requirements listed in Table 4-3.

Table 4-3 lists PXI synchronous trigger timing requirements.

Table 4-3. PXI Synchronous Trigger Timing

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td></tr><tr><td> $T_{hd}$ </td><td>Output hold time from PXI_CLK10</td><td>2 ns</td><td>—</td></tr><tr><td> $T_{val}$ </td><td>Output signal valid from PXI_CLK10</td><td>—</td><td>65 ns</td></tr><tr><td> $T_{su}$ </td><td>Input set up time to PXI_CLK10</td><td>23 ns</td><td>—</td></tr><tr><td> $T_h$ </td><td>Input hold time from PXI_CLK10</td><td>0 ns</td><td>—</td></tr><tr><td colspan="4">Note: Minimum times are measured with 0 pf equivalent load. Maximum times are measured with 50 pf equivalent load.</td></tr></table>

OBSERVATION: The output signal valid timing from PXI\_CLK10 allows either rising or falling edges of PXI\_CLK10 to be used for sourcing PXI synchronous triggers.

# Backplane

RULE: For each PXI segment in a PXI chassis, the PXI chassis SHALL bus the PXI\_TRIG[0:7] signal to each PXI slot (system and peripheral) in that segment. A chassis SHALL NOT directly connect PXI\_TRIG buses from different PXI segments. If a system slot controls multiple PXI segments, it SHALL NOT directly connect PXI trigger buses from different segments.

OBSERVATION: Trigger buses from multiple segments are physically disconnected to maintain signal integrity and allow for incident wave switching of Type A trigger drivers. However, the buses may be logically connected by buffering the signals between segments.

RULE: A PXI chassis that logically connects trigger bus segments SHALL use eight bi-directional buffers to connect each trigger line of one segment to the matching trigger line on the other segment. Each buffer SHALL be able to individually route either direction between the two segments and SHALL be able to be individually tri-stated.

RULE: Buffers used for connecting trigger segments SHALL meet the same electrical requirements listed in this section for module triggers.

RULE: PXI\_TRIG[0:7] SHALL be fast Schottky diode terminated at both ends of the bus segment on the backplane to + 5 V and ground as shown in Figure 4-3.

![+5 V PXI_TRIG](.pxi-1-hardware-specification-rev2-3/2611d4261f398e6264356100cac919b39363ff7bbccdcd557f09cde4c1ad718a.jpg)

Figure 4-3. PXI Trigger Bus Termination

RULE: The unloaded characteristic impedance for the backplane $Z _ { \mathrm { l , m i n } } \mathrm { S H A L L }$ be 75 Ω ± 10% using a stripline transmission line geometry.

OBSERVATION: The higher backplane impedance lowers the driver strength requirements for incident wave switching.

RULE: The signal trace lengths of PXI trigger bus signals SHALL be less than 10 in. and matched within 1 in. between all trigger bus signals.

# Peripheral or System Module

RULE: Printed circuit board trace lengths for PXI trigger bus signals SHALL be less than or equal to 1.5 in.

RECOMMENDATION: A PXI module sourcing or receiving a trigger SHOULD connect to all eight triggers and allow any of the eight triggers to be used for the sourcing or receiving functionality.

PERMISSION: A PXI module (system or peripheral) MAY leave any number of PXI trigger bus signals unconnected.

RECOMMENDATION: The following recommendations improve interoperability between modules using the PXI trigger bus. For triggering applications, if a PXI module (system or peripheral) connects to a subset of the PXI trigger signals, it SHOULD connect to PXI\_STAR and PXI\_TRIG[0:n-2] where n is the number of trigger lines on the peripheral module. For sourcing or receiving clocks, PXI\_TRIG[7] SHOULD be used.

RULE: Upon power up, the PXI\_TRIG[0:7] lines and drivers SHALL remain in a high impedance state until configured by software.

RULE: PXI\_TRIG[0:7] I/O buffers SHALL be compliant with the DC specifications listed in Table 4-4.

Table 4-4. DC Specifications

<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Min</td><td>Max</td><td>Notes</td></tr><tr><td>Vih</td><td>Input High Voltage</td><td>—</td><td>2.0 V</td><td> $V_{cc} + 0.5$  V</td><td>1</td></tr><tr><td>Vil</td><td>Input Low Voltage</td><td>—</td><td>- 0.5 V</td><td>0.8 V</td><td>—</td></tr><tr><td>Il</td><td>Leakage Current</td><td>0 &lt; Vin &lt; Vcc</td><td>—</td><td>±70 μA</td><td>1,2</td></tr><tr><td>Voh</td><td>Output High Voltage</td><td>Iout = - 2 mA</td><td>2.4 V</td><td> $V_{cc} + 0.5$  V</td><td>1</td></tr><tr><td>Vol</td><td>Output Low Voltage</td><td>Iout = 4 mA</td><td>- 0.5 V</td><td>0.55 V</td><td>—</td></tr><tr><td>Cpin</td><td>Input, Output, Bidirectional Pin Capacitance</td><td>—</td><td>—</td><td>10 pf</td><td>—</td></tr><tr><td colspan="6">Notes:1Vcc refers to the 5 V power supply rail.2Leakage current includes output leakage for bidirectional buffers in a high-impedance state.</td></tr></table>

OBSERVATION: The DC specifications are met by 5 V tolerant LVTTL-compatible I/O buffers.

PERMISSION: To prevent floating inputs, PXI\_TRIG[0:7] lines used on a PXI module (system or peripheral) MAY be pulled up on the module with a pull-up resistance whose value is shown in Table 4-5.

Table 4-5. Pull-Up Resistor Values

<table><tr><td>Signaling Rail</td><td>Rmin</td><td>Rmax</td></tr><tr><td>5 V</td><td>11 kΩ</td><td> $[Vccmin - Vx]/[Iih]^*$ </td></tr><tr><td>3.3 V</td><td>19 kΩ</td><td> $[Vccmin - Vx]/[Iih]^*$ </td></tr><tr><td colspan="3">*Vx = 2.4 V, which is the desired voltage on the bus in a non-driven state, and Iih is the maximum leakage current for the device buffer.</td></tr></table>

RECOMMENDATION: Type A drivers SHOULD be used for clock transmission over the PXI trigger bus. Type A drivers are capable of incident wave switching on rising edges, preventing jitter degradation due to transmission line effects. Refer to Table 4-6 for Type A driver specifications.

Table 4-6. Type A, High Current Driver, AC Specifications

<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Min</td><td>Max</td></tr><tr><td>Vsoh(AC)</td><td>Switching voltage high</td><td></td><td>2.3 V</td><td>—</td></tr><tr><td>Ioh(AC)</td><td>High source current</td><td>@Vsoh(AC)</td><td>75 mA</td><td>—</td></tr></table>

RECOMMENDATION: Intermediate voltage levels (Vol ≤ V ≤ Voh) may be present on the trigger bus. Schmitt trigger inputs SHOULD be used to guard against sensing multiple transitions on edge-sensitive inputs when the voltage on the bus is at intermediate levels due to transmission line effects on the bus.

RECOMMENDATION: Rising edges SHOULD be used as active edges in asynchronous trigger protocols.

# 4.1.2.6 Star Trigger

In addition to the bused PXI triggers, the PXI bus has included an independent trigger (PXI\_STAR) for each slot that is oriented in a star configuration from the star trigger slot. The star trigger slot is adjacent to the system slot and uses the 13 left local bus signals as the star triggers. This allows a single star trigger slot to control or monitor triggers in two PCI bus segments. In systems with more than two PCI segments, it is recommended that the star triggers are only routed to the slots in the first two segments, but other routings are allowed.

The PXI Hardware Specification does not specify the functionality of the star trigger slot module or even require that the system be constructed with a star trigger module. Typical uses would include triggering multiple modules independently with low skew, monitoring a trigger from peripheral slots, and routing triggers between slots. One star trigger slot pin is dedicated to allow an external 10 MHz frequency standard to be routed as PXI\_CLK10.

# Backplane

RULE: The first slot to the right of the system slot in a chassis SHALL be a star trigger slot.

RULE: A chassis SHALL NOT have more than one star trigger slot.

OBSERVATION: The star trigger slot may also be used as a generic peripheral slot with the exception that the left side local bus is unavailable because these pins connect to the star triggers. The star trigger slot does not have a PXI\_STAR; instead, the pin in the star trigger slot is used for an external frequency reference.

RULE: The PXI backplane SHALL route the signals from the star trigger slot to each peripheral with a trace impedance of 65 Ω ± 10%.

RECOMMENDATION: The PXI backplane SHOULD route the signals from the star trigger slot to each peripheral slot according to Table 4-7.

RULE: If signal routing used from the star trigger to each peripheral slot is other than that routing described in Table 4-7, or if the chassis has been designed for configurable routing, then the chassis vendor SHALL document the possible routings of such a system.

RECOMMENDATION: If the chassis has been designed for configurable routing, then the chassis vendor SHOULD provide software that can be used in all PXI frameworks to allow the user or system integrator to change the routing.

Table 4-7. Star Trigger Mapping

<table><tr><td>Star Trigger Signal</td><td>Physical Peripheral Slot</td></tr><tr><td>PXI_STAR0</td><td>3</td></tr><tr><td>PXI_STAR1</td><td>4</td></tr><tr><td>PXI_STAR2</td><td>5</td></tr><tr><td>PXI_STAR3</td><td>6</td></tr><tr><td>PXI_STAR4</td><td>7</td></tr><tr><td>PXI_STAR5</td><td>8</td></tr><tr><td>PXI_STAR6</td><td>9</td></tr><tr><td>PXI_STAR7</td><td>10</td></tr><tr><td>PXI_STAR8</td><td>11</td></tr><tr><td>PXI_STAR9</td><td>12</td></tr><tr><td>PXI_STAR10</td><td>13</td></tr></table>

Table 4-7. Star Trigger Mapping

<table><tr><td>Star Trigger Signal</td><td>Physical Peripheral Slot</td></tr><tr><td>PXI_STAR11</td><td>14</td></tr><tr><td>PXI_STAR12</td><td>15</td></tr></table>

RULE: The PXI\_STAR line lengths SHALL be matched in propagation delay to within 1 ns, and the delay from the star trigger slot to each peripheral module SHALL NOT exceed 5 ns.

# Peripheral Module

RULE: The driver of PXI\_STAR, which may be the star trigger module or a peripheral module, SHALL have a source impedance of 65 Ω ± 10% to match the backplane impedance.

RULE: When a peripheral module or star trigger controller drives a PXI\_STAR, the signaling levels SHALL NOT exceed 5V.

RULE: A peripheral module SHALL NOT drive its PXI\_STAR when reset.

PERMISSION: A peripheral module MAY pull-up the PXI\_STAR signal to prevent an unstable input.

RULE: If a peripheral module pulls up the PXI\_STAR signal, the pull-up resistor SHALL be 20K Ohm or greater.

RULE: The leakage current of a peripheral module connected to PXI\_STAR SHALL NOT exceed 650 μA.

OBSERVATION: The same trigger protocols defined for the PXI TTL trigger bus MAY be used on the PXI\_STAR signals.

PERMISSION: The PXI\_CLK10\_IN signal of the star trigger slot MAY be used to provide an external 10 MHz reference for PXI\_CLK10.

RULE: A module in the star trigger slot SHALL NOT drive the PXI\_STAR/CLK10\_IN signal, except to provide a reference for PXI\_CLK10.

RULE: If a module when used in a star trigger slot can source an external 10 MHz reference onto the PXI\_CLK10\_IN pin, then the module SHALL only disable the external 10MHz reference while it is in a low state and the signal SHALL be tri-stated or driven low at that time.

OBSERVATION: The presence of a periodic signal on the PXI\_CLK10\_IN signal MAY be used to indicate that an external reference is to be used.

# 4.1.3 Electrical Guidelines for 6U

Larger 6U-size modules are desirable for the extra module space and possibly for future additional functionality that can be provided through the J3 connector. In many cases, the extra space on a 6U module is needed only for extra circuitry, and the module requires only the J1 and J2 connectors for PXI. J3 is reserved for future revisions of the PXI Hardware Specification. This section includes the rule for connector population for 6U modules.

In an effort to make efficient use of 3U PXI modules in 6U PXI chassis, the PXI Hardware Specification defines a 6U slot that allows 3U modules to be stacked within. This allows two 3U modules to be used in 1 6U slot. These systems have P4 and P5 populated in the slots that support stacking 3U modules. P4 and P5 will be routed as if they were another segment of the PXI backplane. This section also covers the electrical rules associated with 6U PXI chassis which support this feature and defines a 6U Star Trigger Controller that can synchronize star triggers going to 3U modules that are stacked in a 6U slot.

# 4.1.3.1 6U Peripheral Module Connector Population

RULE: 6U PXI peripheral modules that are not 6U star trigger controllers SHALL implement only J1 and J2. J3 SHALL NOT be loaded on 6U peripheral modules.

PERMISSION: Since J5 is not reserved for future revisions of the PXI Hardware Specification, vendors MAY use J5 for custom implementations of PXI provided they only offer such a module as part of their custom PXI system.

# 4.1.3.2 6U Chassis that Support Stacking 3U Modules

RULE: 6U slots that support stacking 3U modules SHALL populate P4 and P5.

RULE: 6U slots that support stacking 3U modules SHALL route the signals on the P4 connector according to the rules in sections 4.1.1, 4.1.2, and 4.2 for P1.

RULE: 6U slots that support stacking 3U modules SHALL route the signals on the P5 connector according to the rules in sections 4.1.1, 4.1.2, and 4.2 for P2.

RULE: 6U chassis that support stacking 3U modules SHALL support stacking 3U modules in the star trigger slot.

OBSERVATION: The preceding rule ensures that up to 13 3U modules that reside in the P4/P5 position of 6U slots have their star trigger line routed to the star trigger slot.

PERMISSION: A 6U star trigger controller MAY populate J5 to allow star triggers to connect to 3U modules that have been stacked in the P4/P5 position of the 6U slot.

RULE: A 6U star trigger controller that populates J5 SHALL NOT connect to any signals on the J5 connector other than the star trigger lines and the PXI trigger bus.

RULE: If PCI to PCI bridging between the segment or segments created by the P4 and P5 connectors and the segment or segments created by the P1 and P2 connectors is needed to meet PCI bus length and loading requirements, then it SHALL be provided by the backplane and SHALL NOT be provided by the System Controller Module.

OBSERVATION: The preceding rule allows most 6U CompactPCI System Controller Modules to work in 6U PXI chassis that support stacking 3U modules.

# 4.2 Connector Pin Assignments (J1/P1 and J2/P2)

To help in reviewing the tables in this section and locating the appropriate specification for signal requirements, Table 4-8 lists all signals alphabetically by original specification (PXI, CompactPCI, or PCI).

Table 4-8. PXI System Signal Groups

<table><tr><td>System</td><td colspan="3">Signals</td></tr><tr><td rowspan="3">PXI</td><td>PXI_BRSV</td><td>PXI_LBL[0:12]</td><td>PXI_STAR[0:12]</td></tr><tr><td>PXI_CLK10</td><td>PXI_LBR[0:12]</td><td>PXI_TRIG[0:7]</td></tr><tr><td>PXI_CLK10_IN</td><td></td><td></td></tr><tr><td rowspan="8">Compact PCI</td><td>BD_SEL#</td><td>HEALTHY#</td><td>REQ#[0:6]</td></tr><tr><td>BRSV</td><td>INTP</td><td>RSV</td></tr><tr><td>CLK[0:6]</td><td>INTS</td><td>SYSEN#</td></tr><tr><td>DEG#</td><td>IPMB_PWR</td><td>SMB_ALERT#</td></tr><tr><td>ENUM#</td><td>IPMB_SCL</td><td>SMB_SCL</td></tr><tr><td>FAL#</td><td>IPMB_SDA</td><td>SMB_SDA</td></tr><tr><td>GA0-GA4</td><td>PRST#</td><td>UNC</td></tr><tr><td>GNT#[0:6]</td><td></td><td></td></tr><tr><td rowspan="12">PCI</td><td>ACK64#</td><td>INTD#</td><td>TCK</td></tr><tr><td>AD[0:63]</td><td>IRDY#</td><td>TDI</td></tr><tr><td>C/BE[0:7]#</td><td>LOCK#</td><td>TDO</td></tr><tr><td>CLK</td><td>M66EN</td><td>TMS</td></tr><tr><td>DEVSEL#</td><td>PAR</td><td>TRDY#</td></tr><tr><td>FRAME#</td><td>PAR64</td><td>TRST#</td></tr><tr><td>GND</td><td>PERR#</td><td>V(I/O)</td></tr><tr><td>GNT#</td><td>REQ#</td><td>3.3 V</td></tr><tr><td>IDSEL</td><td>REQ64#</td><td>5 V</td></tr><tr><td>INTA#</td><td>RST#</td><td>+12 V</td></tr><tr><td>INTB#</td><td>SERR#</td><td>-12 V</td></tr><tr><td>INTC#</td><td>STOP#</td><td></td></tr></table>

# 4.2.1 General Peripheral Slots

Table 4-9 gives the peripheral slot pinout for the J1 and J2 connector. PXI-specific signals are shown in bold.

RULE: Peripheral modules and backplane peripheral slots SHALL use the pinout in Table 4-9.

Table 4-9. Generic Peripheral Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONNECTOR</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>RSV</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_LBL0</td><td>GND</td><td>PXI_LBL1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_LBL2</td><td>RSV</td><td>PXI_LBL3</td><td>PXI_LBL4</td><td>PXI_LBL5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_STAR</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_LBL6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_LBL7</td><td>PXI_LBL8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_LBL9</td><td>GND</td><td>PXI_LBL10</td><td>PXI_LBL11</td><td>PXI_LBL12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONNECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BD_SEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# 4.2.2 System Slot

Table 4-10 gives the system slot pinout for the J1 and J2 connectors. PXI-specific signals are shown in bold.

RULE: System modules and backplane system slots SHALL use the pinout in Table 4-10.

Table 4-10. System Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONECTOR</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>DEG#</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONNECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>3.3V</td><td>CLK0</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# 4.2.3 Star Trigger Slot

Table 4-11 gives the peripheral slot pinout for the J1 and J2 connectors of the star trigger slot. PXI-specific signals are shown in bold.

RULE: Star trigger modules and backplane star trigger slots SHALL use the pinout in Table 4-11.

Table 4-11. Star Trigger Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONNECTOR</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>RSV</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_STAR0</td><td>GND</td><td>PXI_STAR1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_STAR2</td><td>RSV</td><td>PXI_STAR3</td><td>PXI_STAR4</td><td>PXI_STAR5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_CLK10_IN</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_STAR6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_STAR7</td><td>PXI_STAR8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_STAR9</td><td>GND</td><td>PXI_STAR10</td><td>PXI_STAR11</td><td>PXI_STAR12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONNECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BD_SEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# 4.3 Power

Minimum chassis power supply requirements are specified to ensure that module designers can design modules knowing that they will operate in any PXI system. The PXI Power requirements specified in this section are minimum current requirements and apply to any PXI chassis regardless of the number of slots or form-factor (3U or 6U).

RULE: The power supply in a PXI chassis SHALL provide at least the required amounts of current specified in Table 4-12.

RULE: 6U slots that support stacking 3U modules SHALL be considered two slots when determining the amount of current required of the power supply.

Table 4-12. PXI Chassis Power Supply Minimum Power Requirements

<table><tr><td rowspan="2"></td><td colspan="2">5 V</td><td colspan="2">3.3 V</td><td>+12 V</td><td>-12 V</td></tr><tr><td>System Slot</td><td>Each Peripheral Slot</td><td>System Slot</td><td>Each Peripheral Slot</td><td>All Slots</td><td>All Slots</td></tr><tr><td>Required Current</td><td>6 A</td><td>2 A</td><td>6 A</td><td>2 A</td><td>0.5 A</td><td>0.25 A</td></tr></table>

OBSERVATION: The minimum current for each voltage rail provided by a power supply in a PXI chassis with N slots can be determined by the following formulas:

$$
5 \mathrm{V}: \quad 6 \mathrm{A} + (\mathrm{N} - 1) \times 2 \mathrm{A}
$$

$$
3. 3 \mathrm{V}: 6 \mathrm{A} + (\mathrm{N} - 1) \times 2 \mathrm{A}
$$

$$
+ 1 2 \mathrm{V}: \mathrm{N} \times 0. 5 \mathrm{A}
$$

$$
- 1 2 \mathrm{V}: \quad \mathrm{N} \times 0. 2 5 \mathrm{A}
$$

For an 8-slot chassis, the minimum current for each voltage rail for the entire chassis would be as follows:

$$
5 \mathrm{V}: \quad 6 \mathrm{A} (\text { system }) + 2 \mathrm{A} \times 7 (\text { peripheral }) = 2 0 \mathrm{A}
$$

$$
3. 3 \mathrm{V}: 6 \mathrm{A} (\text { system }) + 2 \mathrm{A} \times 7 (\text { peripheral }) = 2 0 \mathrm{A}
$$

$$
+ 1 2 \mathrm{V}: 0. 5 \mathrm{A} \times 8 (\text { all   slots }) = 4 \mathrm{A}
$$

$$
- 1 2 \mathrm{V}: 0. 2 5 \times 8 (\text { all   slots }) = 2 \mathrm{A}
$$

For a 14-slot chassis, the minimum current for each voltage rail for the entire chassis would be as follows:

$$
5 \mathrm{V}: \quad 6 \mathrm{A} (\text { system }) + 2 \mathrm{A} \times 1 3 (\text { peripheral }) = 3 2 \mathrm{A}
$$

$$
3. 3 \mathrm{V}: 6 \mathrm{A} (\text { system }) + 2 \mathrm{A} \times 1 3 (\text { peripheral }) = 3 2 \mathrm{A}
$$

$$
+ 1 2 \mathrm{V}: 0. 5 \mathrm{A} \times 1 4 (\text { all   slots }) = 7 \mathrm{A}
$$

$$
- 1 2 \mathrm{V}: 0. 2 5 \times 1 4 (\text { all   slots }) = 3. 5 \mathrm{A}
$$

OBSERVATION: The minimum power provided by a power supply in a PXI chassis with N slots is equivalent to the formula:

$$
5 \mathrm{V} \times (6 \mathrm{A} + (\mathrm{N} - 1) \times 2 \mathrm{A}) + 3. 3 \mathrm{V} \times (6 \mathrm{A} + (\mathrm{N} - 1) \times 2 \mathrm{A}) + 1 2 \mathrm{V} \times (\mathrm{N} \times 0. 5 \mathrm{A}) + 1 2 \mathrm{V} \times (\mathrm{N} \times 0. 2 5 \mathrm{A})
$$

PERMISSION: PXI chassis power supplies MAY provide additional current beyond the required amounts specified in Table 4-12.

OBSERVATION: Having the system supply 3.3 V conserves space and heat in the system slot module because 5 V does not have to be converted to 3.3 V on the module.

OBSERVATION: Each generation of processors requires more power than the previous generation. Providing copious amounts of power and cooling to the system slot of a chassis can extend the product applicability in the future.

RULE: All modules SHALL document and make available to the customer their current requirements to allow users to maximize the capabilities of their power supply.

RULE: The power distribution mechanism of a backplane in a PXI chassis SHALL be capable of providing the amounts of current specified in Table 4-13 to each slot.

Table 4-13. Minimum Current Handling Per Slot

<table><tr><td>5 V</td><td>3.3 V</td><td>+12 V</td><td>-12 V</td></tr><tr><td>6A</td><td>6A</td><td>1A</td><td>1A</td></tr></table>

OBSERVATION: The power supply of a PXI chassis is not required to supply the current listed in Table 4-13 to all slots simultaneously. Overall current per rail supplied by a power supply to all slots is not required to be greater than the minimum power requirements specified in Table 4-12.

RULE: A peripheral or system slot module SHALL NOT draw more than 1 A of current from any +5V or +3.3V power pin or ground pin.

PERMISSION: A module MAY draw a maximum of 3 A from the +12V and -12V power pins, if the chassis is specified to supply this amount of current.

RULE: A module SHALL NOT return more current through the ground pins than is allowed to be drawn from the power pins by the rules and permissions of this specification.

OBSERVATION: A module can draw more than the amounts of the current specified in Table 4-13 when used in a chassis that is specified to supply these current levels.

RULE: Plug-in module manufacturers SHALL document and make it clear when a module exceeds the amounts of current specified in Table 4-13.

# 4.3.1 Low Power Chassis Power Supply Specifications

A chassis designed for portable applications or one with a DC power input may be constrained by the battery and operating hours. This may make meeting the minimum power requirements listed in Table 4-12 impractical, but minimum power requirements for this class of chassis are still important for interoperability with modules. The minimum power requirements for low power chassis are set to allow at least one system controller and two peripheral modules to work in the chassis, regardless of 3U/6U or the number of slots available.

PERMISSION: A low power PXI chassis MAY have less power than is required in Table 4-12.

RULE: A low power PXI chassis that has less power than is required in Table 4-12 input SHALL provide at least the required amounts of current specified in Table 4-14.

Table 4-14. Low Power PXI Chassis Power Supply Minimum Power Requirements

<table><tr><td rowspan="2"></td><td colspan="2">5 V</td><td colspan="2">3.3 V</td><td>+12 V</td><td>-12 V</td></tr><tr><td>System Slot 6 A</td><td>Each Peripheral Slot 2 A</td><td>System Slot 6 A</td><td>Each Peripheral Slot 2 A</td><td>Each Slot 0.5 A</td><td>Each Slot 0.25 A</td></tr><tr><td>Total Required Current</td><td colspan="2">10 A</td><td colspan="2">10 A</td><td>1.5 A</td><td>0.75 A</td></tr></table>

RULE: PXI chassis having less power than is required in Table 4-12 and meet the requirements in Table 4-14 SHALL have the text LOW POWER clearly visible with a character height of at minimum 4 mm on the front of the chassis as shown in Figure 4-4. Logo artwork can be obtained from the PXI Systems Alliance.

# LOW POWER

Figure 4-4. Text Required for Low Power Chassis

# 4.4 PXI Module Ground Connections

The PXI backplane provides power and ground connections on the P1/J1 and P2/J2 connectors. The power connections will carry ripple currents introduced by the PXI chassis power supply and time varying power loads of the modules fitted. The PXI backplane grounds will have a voltage on them because of the current drawn by the modules and returned, by the module, back to the PXI power supply via the backplane.

For applications where the system is to be used to perform parametric measurements it is important to make sure that the currents flowing in the PXI backplane connections do not cause interference which results in unwanted currents or voltages on the ground of the front panel of PXI chassis, the point most commonly used as the reference in single ended outputs (such as RF applications).

An example ground arrangement is shown in Figure 4-5.

![The diagram illustrates the power and grounding connections for a PXI chassis system.  **Labeled Blocks:** *   **Left Side:** A large rectangle labeled 'Chassis Power Supply'. *   **Right Side:** A large rectangle containing two internal blocks labeled 'Digital' and 'Analog'. *   **Labels:** 'L', 'R', 'GND'.  **Connections:** *   **From Chassis Power Supply (Top):**     *   A solid line connects the top output to the top rail of the right block, labeled 'PX I backplane power connections'.     *   A dashed arrow points to the right, labeled 'Power to other modules'. *   **From Chassis Power Supply (Bottom):**     *   A solid line connects the bottom output (labeled 'GND') to the bottom rail of the right block, labeled 'PX I backplane ground'.     *   A dashed arrow points to the right, labeled 'PX I backplane grounds to other modules'.     *   A solid line extends downward from the 'GND' point to a ground symbol. *   **Inside the Right Block:**     *   Capacitor symbols connect the top and bottom rails for both the 'Digital' and 'Analog' sections.     *   A resistor labeled 'L' connects the top rails between the 'Digital' and 'Analog' sections.     *   A switch/resistor symbol labeled 'R' connects the bottom rails between the 'Digital' and 'Analog' sections. *   **From the Right Block:**     *   A dashed arrow points downward from the bottom rail, labeled 'Other Modules'.     *   A thick dashed line labeled 'Front panel grounds' connects to the right edge of the block.     *   This connects to a thick dashed line labeled 'Chassis metalwork' which routes downward and then leftward, connecting back to the 'GND' line of the 'Chassis Power Supply'.     *   A caption at the bottom reads: 'Connection from front panel to power supply ground through chassis metalwork'.](.pxi-1-hardware-specification-rev2-3/c483ffa304a5f4be33d0baca0edf9222687dab152836e4e60e91d583cfbdc441.jpg)

Figure 4-5. Power and Ground Connections on a PXI Module

For clarity only one module, one power supply and one ground connection is shown. In practice a number of connections are made to each module.

Power from the chassis power supply is supplied to the modules from star connection points. Where practical the AC currents flowing down the power supply lines should be returned to the power supply ground star connection.

The impedance of the connection between the front panel grounds of the modules and to the chassis power supply ground is low, but the presence of any current can generate unwanted voltages across the module front panels that will degrade a system’s performance.

The level of current injected into the front panel ground can be reduced by appropriate choice of the decoupling components and the separation of digital and analog grounds, one example of which is shown in Figure 4-5.

RECOMMENDATION: Modules SHOULD be designed so that they minimize the injection of AC currents into the front panel ground of PXI modules.

RECOMMENDATION: Where possible, alternating currents SHOULD be returned to the power supply by using a suitable decoupling arrangement on the PXI power supply and returning the current to the power supply via the PXI backplane ground.

RECOMMENDATION: Where possible high speed digital circuits, and particularly the PCI interface devices, SHOULD use the PXI backplane ground in preference to the module front panel ground in order to avoid injecting AC signals into the module front panels.

RECOMMENDATION: Analog component grounds SHOULD be referenced to the module front panel ground.

RECOMMENDATION: The front panel ground and the PXI (digital) backplane ground SHOULD be separated so that the high speed clock edges do not produce spurious signals in the analog circuits. Some coupling between the two grounds is inevitable through capacitive or inductive coupling; these effects

SHOULD be minimized by careful consideration of the module layout and component placement and the correct use of local decoupling capacitors for the application.

OBSERVATION: Having the front panel ground and the digital ground entirely separated may make the module unduly sensitive to static handling problems. This can be alleviated by adding a resistor between the two grounds whose value is significantly higher than the impedance of the PXI ground to the chassis power supply ground, a value of greater than 10 ohms and less than 100 k ohms being adequate is most cases. The presence of a 10 ohm connection is unlikely to introduce significant current since it is much higher than the resistance from the PXI backplane ground to the power supply.

OBSERVATION: In some modules high speed digital signals may be connected to the front panel ground in order to meet performance standards required of the module, and it may not be possible to follow all the guidelines indicated in this section of the standard.

OBSERVATION: The ground of high speed digital circuits should be returned back to the PXI ground and not the analog ground

OBSERVATION: Analog circuits should be grounded to the front panel of the module.

OBSERVATION: The front panel ground and the PXI ground can be connected together by a resistor (10 ohms or greater) to avoid static handling problems for the PXI module.

OBSERVATION: Modules should be designed to maximize the impedance above 100 kHz between the PXI backplane ground and the module front panel.

# 5. PXI Software Specification Compliance

Revision 2.0 and earlier of the PXI Specification included software requirements for PXI modules, chassis, and systems. From PXI Hardware Specification revision 2.1 and higher, the PXI Systems Alliance maintains a separate software specification for PXI modules, chassis, and systems. PXI modules, chassis, and systems developed to comply with this PXI Hardware Specification must also comply with the PXI Software Specification.

RULE: PXI modules, chassis, and systems SHALL comply with the rules defined in the PXI Software Specification maintained by the PXI Systems Alliance.

# 6. 32-Bit PCI and Rear I/O

Revision 2.1 and earlier of the PXI Hardware Specification required all backplanes be routed to support 64-bit PCI. Many PXI modules only require 32-bit PCI support which could be used in lower cost chassis that support 32-bit PCI only. This section defines a PXI chassis that does not support 64-bit PCI. Additionally since the upper 32-bit PCI signals will not be used in these chassis, suppliers of PXI chassis may decide to use these signals for rear I/O purposes. This allows PXI controllers to pass vendor specific signals through the backplane to support functions such as video and mass storage within or through the back of the chassis. Controllers shall be designed to isolate the rear I/O functionality on the J2 connector based on the state of the 64EN# signal. Because there is a potential for incompatibility between different controller and chassis implementations of rear I/O, chassis that support rear I/O have additional labeling and marketing requirements and controllers that support rear I/O have additional marketing requirements.

RULE: PXI chassis that don’t support 64-bit PCI SHALL leave the 64EN# (J2-B5) pin unconnected.

RULE: PXI controllers that support rear I/O functionality on the upper 32-bit PCI pins on the J2 connector SHALL use 64EN# (J2-B5) to determine if the backplane supports 64-bit PCI. If 64EN# is active (low) the system controller SHALL isolate the rear I/O functionality from the BP(I/O) pins and SHALL pull-up the rear I/O pins to V(I/O) per the CompactPCI specification. If 64EN# is inactive (floating) then the system controller can enable the rear I/O functionality to the BP(I/O) pins.

RULE: PXI chassis that support rear I/O on the upper 32-bit PCI pins (3U and 6U) or support rear I/O on the P3, P4, and P5 (6U) connectors SHALL have the text REAR I/O clearly visible with a character height of at minimum 4 mm on the front of the chassis as shown in Figure 6-1. Logo artwork can be obtained from the PXI Systems Alliance.

# REAR I/O

# Figure 6-1. Text Required for Rear I/O Chassis

RULE: PXI system controllers that implement rear I/O functionality SHALL have the following text in their marketing information, manuals, and datasheets: Notice: This PXI controller implements rear I/O. PXI controllers with rear I/O were designed to operate with a matching rear transition module which provides internal or external chassis I/O. Warning: If this PXI controller is used with a chassis that contains a rear transition module that does not match the controller, the rear I/O functionality may not operate and may cause damage to the PXI controller or the rear transition module.

RULE: PXI chassis that implement rear I/O functionality SHALL have the following text in their marketing information, manuals, and datasheets: Notice: This PXI chassis implements rear I/O. PXI chassis with rear I/O were designed to provide internal or external chassis I/O using a rear transition module that matches the PXI controller. Warning: If this PXI chassis is used with a controller that does not match the rear transition module, the rear I/O functionality may not operate and may cause damage to the PXI controller or the rear transition module.

RULE: PXI system controllers and chassis that implement rear I/O functionality SHALL have their rear I/O pin definition documented in the product manuals.

OBSERVATION: System controller modules might only support a 32-bit PCI interface to the PXI backplane but don’t implement rear I/O functionality. These controllers do not have additional requirements for their marketing information, manuals, or datasheets.

RULE: System controllers that implement rear I/O and backplanes that only support 32-bit PCI SHALL comply with all previous defined rules except they SHALL follow the pin definitions in Table 6-1, Table 6-2, and Table 6-3.

RULE: Backplanes that do not support 64-bit PCI SHALL leave the BP(I/O) and RSV pins unconnected.

PERMISSION: Suppliers MAY decide how to use the BP(I/O) pins on system controllers that support rear I/O.

PERMISSION: Suppliers MAY support a 50mm deep rear transition module in chassis that support 32-bit PCI only.

PERMISSION: Suppliers MAY choose how to make use of the supplier defined signals coming from the BP(I/O) pins in chassis that don’t support 64-bit PCI.

# 6.1 32-Bit PCI-Only General Peripheral Slots

Table 6-1 gives the peripheral slot pinout for the P1 and P2 connector of a backplane that supports 32-bit PCI only. PXI-specific signals are shown in bold.

Table 6-1. 32-Bit PCI-Only Generic Peripheral Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONTECTOR</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>RSV</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_LBL0</td><td>GND</td><td>PXI_LBL1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_LBL2</td><td>RSV</td><td>PXI_LBL3</td><td>PXI_LBL4</td><td>PXI_LBL5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_STAR</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_LBL6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>RSV</td><td>64EN#</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_LBL7</td><td>PXI_LBL8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_LBL9</td><td>GND</td><td>PXI_LBL10</td><td>PXI_LBL11</td><td>PXI_LBL12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONTECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BD_SEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# 6.2 Rear I/O System Slot

Table 6-2 gives the system slot pinout for the P1 and P2 connector of a backplane that supports rear I/O. PXI-specific signals are shown in bold.

Table 6-2. Rear I/O System Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONECTOR</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>DEG#</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>BP(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>BP(I/O)</td><td>GND</td><td>V(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>BP(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>BP(I/O)</td><td>GND</td><td>V(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>BP(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>BP(I/O)</td><td>GND</td><td>V(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>BP(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>BP(I/O)</td><td>GND</td><td>V(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>BP(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BP(I/O)</td><td>64EN#</td><td>V(I/O)</td><td>BP(I/O)</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>BP(I/O)</td><td>GND</td><td>BP(I/O)</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>3.3V</td><td>CLK0</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# 6.3 32-Bit PCI-Only Star Trigger Slot

Table 6-3 gives the star trigger slot pinout for the P1 and P2 connector of a backplane that supports 32-bit PCI only. PXI-specific signals are shown in bold.

Table 6-3. 32-Bit PCI-Only Star Trigger Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2CONECTOR</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>RSV</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_STAR0</td><td>GND</td><td>PXI_STAR1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_STAR2</td><td>RSV</td><td>PXI_STAR3</td><td>PXI_STAR4</td><td>PXI_STAR5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_CLK10_IN</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_STAR6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>RSV</td><td>GND</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>RSV</td><td>64EN#</td><td>V(I/O)</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_STAR7</td><td>PXI_STAR8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_STAR9</td><td>GND</td><td>PXI_STAR10</td><td>PXI_STAR11</td><td>PXI_STAR12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1CONECTOR</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BD_SEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

# A. Appendix: Hybrid Slot-Compatible PXI-1 Peripheral Module

# A.1 Background

The PXI Express Hardware Specification brings PCI Express to the PXI standard and allows addition instrumentation capability. The PXI Express Hardware Specification provides compatibility with PXI-1 (PXI Hardware Specification) Peripheral Modules in two ways. First, PXI Express Chassis may implement Peripheral Slots as defined in this PXI-1 specification. Second, PXI Express Chassis may implement a Slot that supports two types of Peripheral Modules:

• A Peripheral Module with PCI Express capability (known as a PXI Express Peripheral Module)
A Peripheral Module (known as a Hybrid Slot-Compatible PXI-1 Module) that is only a slightly modified version of Peripheral Modules designed to this PXI-1 specification

This appendix serves as the requirements to create a Hybrid Slot-Compatible PXI-1 Module and indicates that such a module is PXI-1 compliant.

# A.2 Hybrid Slot-Compatible PXI-1 Peripheral Module

A Hybrid Slot-Compatible PXI-1 Peripheral Module is a PXI-Peripheral Module that fully complies with this PXI-1 specification, except that the J2 HM connector is replaced with an eHM connect (XJ4) populated in the upper columns of the J2 footprint. The eHM connector is designated the eHM-F2 and defined within the CompactPCI Express specification maintained by the PICMG. Existing PXI-1 Peripheral Modules can be reworked to populate the eHM connector in place of the J2 HM, or new PXI-1 Peripheral Modules can be designed to accept only the eHM connector. In either case, a Peripheral Module meeting the requirements of this appendix is considered PXI-1 compliant.

When creating a Hybrid Slot-Compatible PXI-1 Peripheral Module care should be taken if the Peripheral Module originally connected to certain local bus and star trigger pins. Table 1 shows the signal name from this PXI-1 specification that should be considered and the associated new sign name that the pin becomes with the voltage that may be present when the Hybrid Slot-Compatible PXI-1 Module is used in a PXI Express Hybrid Slot. If a PXI-1 Module connects to a signal in Table 1 that would cause an electrical conflict when used in a PXI Express Hybrid slot, then either the module should use an eHM connector with the conflicting pins not populated or the module should have its design modified prior to creating a Hybrid Slot-Compatible PXI-1 Module to remove the conflict.

Table A-1. PXI-1 Peripheral to PXI Express Hybrid Slot Critical Signals

<table><tr><td>PXI-1 Peripheral Module Signal Name</td><td>PXI Express Hybrid Slot Signal Name</td><td>Voltage Range</td></tr><tr><td>PXI_LBR0</td><td>5Vaux</td><td>5V</td></tr><tr><td>PXI_LBR2</td><td>WAKE#</td><td>0-3.3V</td></tr><tr><td>PXI_LBR3</td><td>ALERT#</td><td>0-3.3V</td></tr><tr><td>PXI_LBR4</td><td>12V</td><td>12V</td></tr><tr><td>PXI_LBR5</td><td>12V</td><td>12V</td></tr><tr><td>PXI_LBL0/PXI_STAR0</td><td>GND</td><td>GND</td></tr><tr><td>PXI_LBL1/PXI_STAR1</td><td>GND</td><td>GND</td></tr><tr><td>PXI_LBL2/PXI_STAR2</td><td>GND</td><td>GND</td></tr><tr><td>PXI_LBL3/PXI_STAR3</td><td>3.3V</td><td>3.3V</td></tr><tr><td>PXI_LBL4/PXI_STAR4</td><td>3.3V</td><td>3.3V</td></tr><tr><td>PXI_LBL5/PXI_STAR5</td><td>3.3V</td><td>3.3V</td></tr></table>

![XJ4 J1](.pxi-1-hardware-specification-rev2-3/871a6ea69beeaaa3c19d4391f01cbe5a77f9a55b7690f397e9803416719a580a.jpg)

Figure A-1. Example of PXI Slot Designations for a Chassis

Figure A-2 shows a 6U Hybrid Slot-Compatible PXI-1 Peripheral Module.
![XJ4 J1](.pxi-1-hardware-specification-rev2-3/fb04203963ad12711b2eb99e06679521cb69cfc38b61e191baf532743c4593ea.jpg)

Figure A-2. 6U Hybrid Slot-Compatible PXI-1 Peripheral Module

Figure A-3 shows the Physical Location where the eHM is populated on a 3U Peripheral Module.
![90.45 (76.45) 46.45 (1.55) 154.93 1. HOLE LOCATION TOLERANCE: ⊕ Ø .13 A B 2. DIMENSIONS IN MILLIMETERS.](.pxi-1-hardware-specification-rev2-3/d6cd26a22f717eb6a0c8c9d5ed2b70804670ee6033da0968ed2a3237e045120f.jpg)

Figure A-3. eHM Physical Location on a 3U Peripheral Module

Figure A-4 shows the Physical Location where the eHM is populated on a 6U Peripheral Module.
![1. HOLE LOCATION TOLERANCE: Ø .13 A B 2. DIMENSIONS IN MILLIMETERS.](.pxi-1-hardware-specification-rev2-3/71e5905cd47d0eb7159e54d8a24524b0609a6880d0a550cce51d4d6b631c28db.jpg)

Figure A-4. eHM Physical Location on a 6U Peripheral Module
[🔗 Link to the original document](.pxi-1-hardware-specification-rev2-3/pxi-1-hardware-specification-rev2-3.pdf)