# PXI Overview

# By Michael Dewey, Marvin Test Solutions

The PCI eXtensions for Instrumentation (PXI) standard has quickly gained adoption and grown in prevalence in automated test systems since its release in 1998. Today, PXI is being selected as the test platform of choice for thousands of applications for a wide range of markets including military, aerospace, consumer electronics, communications, semiconductor, and transportation as well as process control and industrial automation. One of the key elements driving the rapid adoption of PXI is the use of PCI as its communication backplane.

As the commercial PC industry drastically improves the available bus bandwidth by transitioning PCI to PCI Express, PXI has the ability to address even more applications by integrating PCI Express into the PXI standard. Both the PCI Industrial Manufacturers Group (PICMG) which governs CompactPCI, and the PXI Systems Alliance (PXISA) which governs PXI, have worked to ensure that the PCI Express technology can be integrated into these standards, while preserving compatibility with the large installed base of existing systems. With PXI Express, users benefit from significantly increased bandwidth, ensured backward compatibility, and additional timing and synchronization features; improving upon an already established platform.

This document answers frequently asked questions about PXI Express.

# General Concept of PXI Express

# What is PXI Express?

PXI Express technology is the latest addition to the PXI platform. The PXI Express specification integrates PCI Express signaling into the PXI standard. This increases backplane bandwidth from 132 MB/s to 6 GB/s, a 45 times improvement. It also enhances PXI timing and synchronization features by incorporating a 100 MHz differential reference clock and differential trigger lines. The PXI Express specification adds these features to PXI while maintaining backwards compatibility with the PXI standard.

# How does PXI Express compare to other buses in bandwidth and latency?

Bandwidth is the rate at which data is sent across a bus, expressed in megabytes per second; latency is the delay in transmission of data across a bus. With PXI Express, you can achieve a maximum 6 GB/s controller-to-backplane bandwidth, the highest bandwidth in the test and measurement industry. Additionally, up to 2 GB/s of bandwidth can be dedicated to each peripheral slot, depending on the system specifics.

![  Technology           Approximate Latency (μs)   Max Bandwidth (MB/s)     ------------------   ------------------------   --------------------     Gigabit Ethernet     ~1000                      ~150                     Fast Ethernet        ~1000                      ~10                      USB 1.1              ~1000                      ~2                       USB 2.0              ~100                       ~50                      IEEE 1394a           ~100                       ~50                      GPIB (HS 488)        ~5                         ~5                       GPIB (488.1)         ~5                         ~2                       VME/VXI              ~1                         ~50                      PCI/PXI (32/33)      ~2                         ~150                     PCI Express (x4)     ~2                         ~1000                 ](.pxi-overview/aea48c12288ab9ed89aa4a3017fa28de47d9620ca3478bc84f0ec57596e76034.jpg)

Figure 1. PXI Express provides the highest bandwidth and lowest latency in the test and measurement industry.

PXI Express offers the lowest latency of all mainstream commercial test and measurement bus technologies, delivering latency comparable to – and in some cases better than – PCI-based PXI. Also, PXI Express latency is several orders of magnitude better than the latencies of external buses such as USB or Ethernet.

# How Does PXI Express take advantage of the PCI Express 2.0 specification?

In January 2007, PCI Special Interest Group (PCI-SIG) announced the PCI Express 2.0 specification which doubles the per-lane throughput from 250 MB/s to 500 MB/s. This means a 32-lane PCI connector (x32) can support throughput up to 16 GB/s aggregate, and the specification is backwards compatible with the previous PCI Express implementation.

PXI Express does take advantage of PCI Express advancements. The PCI Express 2.0 specification gives PXI Express the ability to continue to provide bandwidth improvements for PXI users. Embedded controllers are now available that offer four x4 Gen 2 PCI Express links for interfacing to the PXI chassis backplane. And when used in conjunction with a PXI Express chassis, total system data throughput of 8 GB/s can be supported. With this capability, you can simultaneously stream a larger set of I/O channels, giving you the ability to support larger and more complex data record-andplayback applications.

PCI-SIG continues to evolve the PCI Express standard and is currently working on the PCI Express 3.0 specification, which will continue to improve the bandwidth capabilities.

# What are the different types of slots in a PXI Express chassis?

A PXI Express chassis can include the following:

 A system slot, which accepts an embedded or remote PXI Express controller
 PXI peripheral slots, which accept PXI modules
PXI Express hybrid peripheral slots, which accept PXI Express peripheral modules, 32-bit CompactPCI peripheral modules, and hybrid-compatible PXI peripheral modules
A system timing slot, which accepts both PXI Express peripheral modules and PXI Express system timing modules

Figure 2 shows a PXI backplane which supports the various PXI slots listed above
![This block diagram illustrates the connectivity of a modular instrument system, likely a PXI/PXIe chassis.  **Labeled Blocks (Left to Right):** *   **System Slot** (Identifier 1, inside a black triangle) *   **PXI Slot** (Identifier 2, inside a circle) *   **Hybrid Slot** (Identifier 3, inside a black circle with superscript 'H') *   **System Timing Slot** (Identifier 4, inside a black square) *   **Hybrid Slot** (Identifier 5, inside a black circle with superscript 'H') *   **PXI Slot** (Identifier 6, inside a circle) *   **PXI Slot** (Identifier 7, inside a circle) *   **PXI Slot** (Identifier 8, inside a circle)  **Connections and Labels:** *   **Red Lines (PCI Express):** Several red lines connect the modules.     *   Three labels reading **'x4 PCI Express'** indicate high-speed connections originating from the System Slot modules, linking to the PXI Slot, Hybrid Slot, and System Timing Slot modules.     *   Red lines visually chain the top modules of slots 2, 3, 4, and 5 together.     *   A label reading **'x1 PCI Express'** is positioned near the bottom left, indicating a connection running from the lowest System Slot module horizontally across the bottom to the right. *   **Grey Bar:** A horizontal grey bar labeled **'PCI Bus'** runs behind the bottom modules of slots 2 through 8. *   **Bridge:** A vertical double-headed arrow connects the right end of the PCI Bus to a box labeled **'PCI Express to PCI Bridge'**. The 'x1 PCI Express' line also terminates at this box.](.pxi-overview/0ffc35b87764f2a9321f0a54a3c920fee4402b63656a18a31288bd297ea59995.jpg)

Figure 2. The backplane layout for a PXI Express chassis which comprises multiple slots

# Does PXI Express replace PXI?

No. PXI Express is part of the PXI platform, and PXI vendors ontinue to invest in both platforms by developing products that are based on both PCI and PCI Express signaling. Many applications, including general data acquisition and motion control, do not require the increased bandwidth of PXI Express, so you need to choose which specification within the PXI platform is right for you. PXI systems already serve a large installed base of applications, and PXI systems based on PCI signaling will be deployed in large numbers for many years to come. Additionally, suppliers of PXI Express chassis include both PXI peripheral slots and PXI Express hybrid peripheral slots, allowing users to incorporate both PXI peripheral modules and PXI Express peripheral modules together in the same chassis and system.

# Is PXI Express backwards compatible with PXI?

Yes. PXI Express maintains both software and hardware compatibility with PXI peripheral modules.

Software: PCI Express uses the same OS and driver model as PCI, resulting in complete software compatibility between PCI-based systems (such as PXI) and PCI Express-based systems (such as PXI Express). This software compatibility is ensured by the PCI-SIG, a group composed of member companies who are committed to the development and enhancement of the PCI and PCI Express standards.

Hardware: PXI Express chassis provide hybrid peripheral slots that accept PXI Express peripheral modules and hybrid slot-compatible PXI peripheral modules. These peripheral slots deliver signaling for PCI and PCI Express.

# Can I use my existing code written for previous PXI systems?

Yes. PXI Express maintains complete software compatibility with PXI. Software compatibility includes operating systems such as Windows 10 and Linux®, application software such as Microsoft Office and other Windows-based APIs.

# What is a PXI Express hybrid slot?

PXI Express chassis have two kinds of peripheral slots: PXI peripheral slots and PXI Express hybrid peripheral slots. The PXI hybrid peripheral slots, shown in Figure 3, can accept either PXI Express peripheral modules, 32-bit CompactPCI boards, or hybrid slot-compatible PXI modules.

![PXI Express Peripheral Module 32-Bit CompactPCI Module Hybrid Slot-Compatible PXI Module](.pxi-overview/59a84123150bf9b74c4bb87968b45021a2c50585b873c698f3b060e029d3d04b.jpg)

Figure 3. A PXI Express hybrid slot accepts PXI Express peripheral modules, 32-bit CompactPCI boards, and hybrid slot-compatible PXI modules.

# What is a hybrid slot-compatible PXI module?

PXI modules that do not include a J2 connector are already hybrid slot-compatible. For modules that do include the J2 connector, you must replace that physical connector to achieve compatibility with PXI Express hybrid peripheral slots. As shown in Steps 1 through 3 below, the J2 connector is removed and replaced with the smaller eHM connector (XJ4). You can still use the resulting hybrid slot-compatible module in existing PXI peripheral slots.

![J2 J1](.pxi-overview/b74c7f03ea306eff4772ba050bce1a68b500457ca98ba2a8860501a5502a8ea7.jpg)

Step 1. Select a PXI peripheral module that you would like to modify.

![Pure mechanical diagram showing a lever and bracket assembly without any text, numbers, or symbols](.pxi-overview/436283a2f39736a467accdf7147b5582f7b72ef5013cccc819c7278852527f75.jpg)

Step 2. Depopulate the J2 connector.

![XJ4 J1](.pxi-overview/041ff5d8fcfbef79e7994e43038ea235843dc7f6f711f01924762862ce26b354.jpg)

Step 3. Populate the eHM (XJ4) connector.

![J2 J1 XJ4 J1](.pxi-overview/ccd8a19b1baa0bb341b07a07464394d46d39741cce3710658703c920b40b0fe2.jpg)

Figure 4. Connector Modification of a PCI-Based PXI Module for Hybrid Slot Compatibility

In general, modified modules only require replacement of the backplane connector, the rest of the module is unchanged. This modification takes advantage of the fact that the lower portion of the J2 connector is largely unused in 32-bit PXI modules, with the exception of its use for local bus functionality.

# What happens to my existing PXI equipment?

You can use existing PXI peripheral modules in PXI Express chassis that have hybrid slots and in PXI chassis. Because the PXI Express specification offers a feature set enhancement and not a replacement for PXI, PXI vendors will continue to develop and sell PXI controllers, chassis, and modules based on PCI signaling.

To use existing PXI peripheral modules in a PXI Express chassis, simply insert the module into one of the several PXI peripheral slots. If the existing equipment does not have a J2 connector, you also can place the module in a hybrid slot. If there are more existing PXI modules that have J2 connectors than there are PXI slots available, the remaining PXI modules can be converted to a hybrid slot compatible configuration.

# Is there a comparable specification for CompactPCI based on PCI Express signaling?

Yes. The CompactPCI Express specification, upon which PXI Express was built, was released in June 2005. The specification is owned and maintained by the PCI Industrial Computer Manufacturers Group (PICMG).

# What does x1, x4, and x16 mean?

With PCI Express, data is sent serially through pairs of transmit and receive connections called lanes, which give data the ability transfer at 250 MB/s per direction. Multiple lanes can be grouped together into x1 (“by-one”), x2, x4, x8, x12, x16, and x32 links to increase bandwidth to the slot. For example, a x16 slot would have bandwidth of 4 GB/s per direction (250 MB/s \* 16).

![x1 x4 x8 x16](.pxi-overview/053b3dc3ec4b8a9da7c20198afe4f661eafc794f80d32924f9e6d31dda883664.jpg)

Figure 5. These examples show the various PCI Express connectors.

Though different lane widths correspond to different physical slot sizes in PCI Express, (Figure 5) PXI Express slots and connections do not differ physically based on the lane width of the link.

# Does every PXI Express slot necessarily have its own dedicated bandwidth?

The answer depends on the implementation of the PCI Express bus in the chassis and controller. If the PCI Express lanes for the slot are directly linked to the controller chipset, then the slot has its own dedicated bandwidth. But if the controller and/or chassis use a PCI Express switch to split the link so that it fans out to several slots, those slots share the bandwidth.

![The image displays a block diagram of a PCI Express switch architecture connecting multiple modules.  **Labeled Blocks:** *   **Three Switches:**     *   Left: '0 PLX PEX8612 PCI Express Switch 5 1'     *   Middle: '0 PLX PEX8612 PCI Express Switch 1 5'     *   Right: '0 PLX PEX8612 PCI Express Switch 1 6' *   **Bridge:** 'PCI Express/PCI Bridge' *   **Links:** 'Link #1', 'Link #2', 'Link #3', 'Link #4' *   **Width Indicators:** 'x4' (appearing multiple times) *   **Bottom Labels:** Circles numbered '1', '2', '3', '4', '5 H', '6 H', '7 H', '8 H' (with '4' in a square and '1' in a triangle).  **Connections:** *   **Switch Chain:**     *   'Link #2' (x4) connects to the Left Switch (Port 0).     *   The Left Switch (Port 1) connects via 'Link #3' (x4) to the Middle Switch (Port 0).     *   The Middle Switch (Port 0) connects via 'Link #4' (x4) to the Right Switch (Port 0). *   **Bridge Connections:**     *   A line connects the 'PCI Express/PCI Bridge' to the Right Switch (Port 0).     *   A large double-headed arrow connects the 'PCI Express/PCI Bridge' to the bottom row of modules (labeled 4, 5, 6, 7, 8). *   **Module Connections (Top Row):**     *   'Link #1' (x4) connects to the first two modules (columns 1 & 2).     *   The Left Switch (Port 5) connects via 'x4' arrows to the third and fourth modules (columns 3 & 4).     *   The Middle Switch (Port 5 and Port 1) connects via 'x4' arrows to the fifth and sixth modules (columns 5 & 6).     *   The Right Switch (Port 1 and Port 6) connects via 'x4' arrows to the seventh and eighth modules (columns 7 & 8).](.pxi-overview/5490a1437dde139cb9387e56cef64c08ae972820e9e3404cfe8822e0f16c9698.jpg)

Figure 6. Backplane architecture shows the PXI Express slot bandwidth capabilities.

In Figure 6 above, the PXI Express chassis has four x4 links that connect the controller slot to the backplane. Slot 2 of the chassis would have dedicated bandwidth back to the controller because it does not require a switch. However, slots 3 and 4 of the chassis route through a switch on the backplane which connectors to a x4 link back to the controller. Because slots 3 and 4 go through a switch, they share bandwidth. Similarly, slots 5 and 6, along with 7 and 8, also use a switch and therefore share the bandwidth of the x4 link back to the controller.

# How is local bus affected?

The PXI local bus provides a daisy-chained connection between each PXI peripheral slot and the adjacent PXI peripheral slots to its left and right. With the exception of a single local bus pin, local bus is not available in the PXI Express hybrid slots or on PXI Express modules. The physical connector space previously used by local bus is now occupied by a connector for PCI Express signaling. Local bus is, however, still available between adjacent PXI slots in the PXI Express chassis and will continue to be available in the future PCI-based PXI chassis.

![The diagram depicts two vertical connector blocks labeled 'PXI Express Hybrid' on the left and 'PXI' on the right.  **Connections and Labels:**  *   **Top Section:** Arrows point between the top sections of the 'PXI Express Hybrid' and 'PXI' blocks. The associated text lists:     *   Power     *   Trigger Bus     *   Star Trigger     *   Clk. 10  *   **Bottom Section:** Arrows point between the bottom sections of the 'PXI Express Hybrid' and 'PXI' blocks. The associated text is:     *   32/33 PCI     *   (132 MB/s per system)  *   **Left Input:** An arrow points to the middle section of the 'PXI Express Hybrid' block. The text is:     *   x8 PCI Express     *   (up to 2 GB/s)     *   Differential Clk. 100 & Star Triggers  *   **Right Input:** An arrow points to the middle section of the 'PXI' block. The text is:     *   Reserved Pins     *   Local Bus (typically unused)](.pxi-overview/06b7f13108398fca827289dc0275f1b8e6486142a8357630879d76c05964e15d.jpg)

Figure 7. A PXI Express hybrid slot provides compatibility with PXI modules with PCI signaling and will work with future PXI Express modules with PCI Express signaling.

# Summary

The PXI Express standard expands the capabilities and performance of the PXI architecture by leveraging the PCI Express specification while preserving compatibility with the PXI standard. In addition, PXI Express maintains complete software compatibility with PXI, allowing users to easily transition applications from PXI to PXI Express platforms.

Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries.
[🔗 Link to the original document](.pxi-overview/pxi-overview.pdf)