![PXI™](.pxi-specification-v2-0/e76286ca0d07f37c404cb750cb188443101fddf2b60a4e9b182d63a255aca09e.jpg)

# Specification

PCI eXtensions for Instrumentation

An Implementation of

Revision 2.0

July 28, 2000

![PXi](.pxi-specification-v2-0/95e8af14d8de8d7b9cded64e0d2ca73215d89c303209f8d6c32820444eb77785.jpg)

Systems Alliance

# IMPORTANT INFORMATION

# Copyright

© Copyright 1997, 2000 PXI Systems Alliance. All rights reserved.

This document is copyrighted by the PXI Systems Alliance. Permission is granted to reproduce and distribute this document in its entirety and without modification.

# NOTICE

The PXI Specification is authored and copyrighted by the PXI Systems Alliance. The intent of the PXI Systems Alliance is for the PXI Specification to be an open industry standard supported by a wide variety of vendors and products. Vendors and users who are interested in developing PXI-compatible products or services, as well as parties who are interested in working with the PXI Systems Alliance to further promote PXI as an open industry standard are invited to contact the PXI Systems Alliance for further information.

The PXI Systems Alliance wants to receive your comments on this specification. Visit the PXI Systems Alliance web site at http://www.pxisa.org/ for contact information and to learn more about the PXI Systems Alliance.

The attention of adopters is directed to the possibility that compliance with or adoption of the PXI Systems Alliance specifications may require use of an invention covered by patent rights. The PXI Systems Alliance shall not be responsible for identifying patents for which a license may be required by any PXI Systems Alliance specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PXI Systems Alliance specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.

The information contained in this document is subject to change without notice. The material in this document details a PXI Systems Alliance specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company’s products.

The PXI Systems Alliance makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The PXI Systems Alliance shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.

Compliance with this specification does not absolve manufacturers of PXI equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).

# Trademarks

PXITM is a trademark of the PXI Systems Alliance.

PICMGTM and CompactPCI® are trademarks of the PCI Industrial Computation Manufacturers Group.

Product and company names are trademarks or trade names of their respective companies.

# PXI Specification Revision History

This section is an overview of the revision history of the PXI specification.

Revision 1.0, August 20, 1997

This is the first public revision of the PXI specification.

Revision 2.0, July 28, 2000

This revision incorporates changes that include but are not limited to the following:

Transfer of the specification ownership to the PXI System Alliance.
Modification of pin assignment to comply with PICMG 2.0 R3.0 that include addition of GA0-GA4 signals to all slots, removal of PRST#, DEG#, and FAL# from peripheral slots, addition of IPMB bus to all slots, addition of HEALTHY# to all slots, addition of SMB bus to system slot, addition of BD\_SEL# to peripheral slots, changing SYSEN# to UNC on peripheral slots, and changing IDSEL to GND on system slot.
• Removal of references to Serialized IRQ due to PICMG 2.0 R3.0 adoption.
• Addition of 66MHz PCI operation.
Removal of J5 as a reserved connector.
Allowance of J5 to be populated only in custom PXI boards and backplanes that are offered as a system.
• Allowance for star trigger routings other than only peripheral slots in first two segments in PXI backplanes with more than two segments.
• Allowance for the local bus to be routed between segments.
Addition of rules about connecting the IDSEL lines of first segment PCI devices, bridges, and peripheral slots to AD[25:31] and routing peripheral slot INT lines to system slot INT lines based on the peripheral slot IDSEL to AD[25:31] connection.
Increased required current on 3.3V for a 5V backplane to comply with requirement of 3.3V being available according to PICMG 2.0 R3.0
• Addition of Windows 98 and Windows 2000 software frameworks.
Removal of requirements for PC 9X compliance for controllers and peripherals.
• Addition of segment divider glyph.
Removal of SHALL NOT rule for chassis ground to digital ground connection and addition of SHOULD NOT recommendation for chassis ground to digital ground.
Modification of requirements for EMC that includes changing IEC 61326-1:1997 to IEC 61326-1:1998 and IEC CISPR-11 to EN5501.
Addition of maximum $\mathrm { V _ { o h } }$ and minimum $\mathrm { \Delta V _ { o l } }$ values for trigger bus.
Modification of the legal notice.
• Addition of license requirement for use of the PXI logo.

# Contents

# 1. Introduction. 9

1.1. Objectives . .9
1.2. Intended Audience and Scope.. ..10
1.3. Background and Terminology . ..10
1.4. Applicable Documents.. 11
1.5. Useful Web Sites.. .12

# 2. PXI Architecture Overview . .13

2.1. Mechanical Architecture Overview .. .13

2.1.1. System Slot Location . .14
2.1.2. Additional Mechanical Features . .15
2.1.3. Interoperability with CompactPCI. .15

2.2. Electrical Architecture Overview . .15

2.2.1. Peripheral Component Interconnect (PCI) Features.. .16
2.2.2. Local Bus ..
2.2.3. System Reference Clock . .17
2.2.4. Trigger Bus . .17
2.2.5. Star Trigger . .17
2.2.6. System Expansion with PCI-PCI Bridge Technology.. .18

2.3. Software Architecture Overview . .19

2.3.1. Common Software Requirements .. .19
2.3.2. Virtual Instrument Software Standards.. .20
2.3.3. Other Software Requirements.. .20

# 3. Mechanical Requirements.. .21

3.1. CompactPCI Mechanical Requirements. ..21
3.2. System Slot Location and Rules . ..21
3.3. Logos and Compatibility Glyphs. .22
3.4. Environmental Testing. ..24
3.5. Cooling Specifications.. .24

3.5.1. Plug-in Module Requirements . .24
3.5.2. Chassis Requirements . .25

3.6. Chassis and Module Grounding Requirements and EMI Guidelines . ..25
3.7. Regulatory Requirements .

3.7.1. Requirements for EMC . ..26
3.7.2. Requirements for Electrical Safety . ..26
3.7.3. Particular Requirements for Chassis. ..26

# 4. Electrical Requirements. ..28

4.1. PXI Signal Groups . ..28

4.1.1. P1/J1: Signals.. .28
4.1.2. P2/J2: Signals.. .29

4.1.2.1. Signals from CompactPCI 64-Bit Connector Specification .29
4.1.2.2. PXI Bused Reserved Signals . .30
4.1.2.3. Local Buses.. .31
4.1.2.4. Reference Clock: PXI\_CLK10 .33
4.1.2.5. Trigger Bus . .34
4.1.2.6. Star Trigger .. .39

4.1.3. Electrical Guidelines for 6U . .41

4.2. Connector Pin Assignments (J1/P1 and J2/P2).. ..42

4.2.1. General Peripheral Slots . .42

4.2.2. System Slot .. .45

4.2.3. Star Trigger Slot.. .47

4.3. Chassis Power Supply Specifications .. .49

5. Software Frameworks and Requirements .. ..51

5.1. Overview... .51

5.2. Motivation. .51

5.3. Framework Definition.. .52

5.4. Windows 95 System Framework . .52

5.4.1. Introduction. .52

5.4.2. Overview of the Framework .

5.4.3. Controller Requirements.. .52

5.4.4. PXI Peripheral Module Requirements. .53

5.5. Windows 98 System Framework . .54

5.5.1. Introduction. .54

5.5.2. Overview of the Framework . .54

5.5.3. Controller Requirements.. .54

5.5.4. PXI Peripheral Module Requirements. .54

5.6. Windows NT System Framework.. .55

5.6.1. Introduction. .55

5.6.2. Overview of the Framework . ..55

5.6.3. Controller Requirements.. .55

5.6.4. PXI Peripheral Module Requirements. ..56

5.7. Windows 2000 System Framework . ..56

5.7.1. Introduction. .56

5.7.2. Overview of the Framework . .56

5.7.3. Controller Requirements. .56

5.7.4. PXI Peripheral Module Requirements. .57

5.8. Support for Existing Instrumentation Standards. ..58

5.9. System Implementation Issues.. .58

5.9.1. System Configuration and Initialization Files . .58

5.9.2. General .ini File Format. .59

5.9.3. PXI System Initialization (pxisys.ini) File .60

5.9.4. Chassis Initialization (chassis.ini) File . ..62

5.9.5. Other Chassis Requirements . ..62

# Figures

Figure 1.1 The PXI Architecture . .10

Figure 2.1 PXI Peripheral Module Form Factors and Connectors . .13

Figure 2.2 Example of a 33 MHz 3U PXI System (Single Bus Segment) . .14

Figure 2.3 PXI and CompactPCI Interoperability . .15

Figure 2.4 PXI Local Bus Routing .. .17

Figure 2.5 PXI Trigger Architecture for Two Bus Segments.. .19

Figure 3.1 Example of PXI Slot Designations for a Chassis . ..22
Figure 3.2 PXI Logo . .23
Figure 3.3 Star Trigger Slot Glyph .23
Figure 3.4 PCI Segment Divider Glyph.. .24
Figure 3.5 Cooling Airflow Direction in a PXI System . .25
Figure 4.1 PXI Asynchronous Trigger Timing.. .35
Figure 4.2 PXI Synchronous Trigger Timing.. .36
Figure 4.3 PXI Trigger Bus Termination. ..37

# Tables

Table 4.1 Local Bus Routings.. .32

Table 4.2 PXI Asynchronous Trigger Timing Parameters .. .35

Table 4.3 PXI Synchronous Trigger Timing . .37

Table 4.4 DC Specifications . .38

Table 4.5 Pull-Up Resistor Values . .39

Table 4.6 Type A, High Current Driver, AC Specifications .. .39

Table 4.7 Star Trigger Mapping . ..40

Table 4.8 PXI System Signal Groups . .42

Table 4.9 Generic Peripheral Slot Pinout . .44

Table 4.10 System Slot Pinout.. .46

Table 4.11 Star Trigger Slot Pinout . .48

Table 4.12 5 V Backplane Power Requirements and Recommendations.. ..49

Table 4.13 3.3 V Backplane Power Requirements and Recommendations.. ..49

Table 5.1 Development Environments Supported by PXI Modules under Windows 95 .53

Table 5.2 Development Environments Supported by PXI Modules under Windows 98 . .55

Table 5.3 Development Environments Supported by PXI Modules under Windows NT. .56

Table 5.4 Development Environments Supported by PXI Modules under Windows 2000 .57

Table 5.5 Tag Line Descriptions.. ..61

Table 5.6 Additional Tag Line Descriptions for chassis.ini . ..62

# 1. Introduction

This section describes the primary objectives and scope of the PCI eXtensions for Instrumentation (PXI) specification. It also defines the intended audience and lists relevant terminology and documents.

# 1.1. Objectives

PXI was created in response to the needs of a variety of instrumentation and automation users who require ever increasing performance, functionality, and reliability from compact rugged systems that are easy to integrate and use. Existing industry standards are leveraged by PXI to benefit from high component availability at lower costs. Most importantly, by maintaining software compatibility with industry-standard personal computers, PXI allows industrial customers to use the same software tools and environments with which they are familiar.

PXI leverages the electrical features defined by the widely adopted Peripheral Component Interconnect (PCI) specification. It also leverages the CompactPCI form factor, which combines the PCI electrical specification with rugged Eurocard mechanical packaging and high-performance connectors. This combination allows CompactPCI and PXI systems to have up to seven peripheral slots versus four in a desktop PCI system. Systems with more expansion slots can be built by using multiple bus segments with industry-standard PCI-PCI bridges. For example, a 13-slot PXI system can be built using a single PCI-PCI bridge. The PXI specification adds electrical features that meet the high-performance requirements of instrumentation applications by providing triggering, local buses, and system clock capabilities. PXI also offers two-way interoperability with CompactPCI products.

By implementing desktop PCI in a rugged form factor, PXI systems can leverage the large base of existing industry-standard software. Desktop PC users have access to different levels of software, from operating systems to low-level device drivers to high-level instrument drivers to complete graphical APIs. All of these software levels can be used in PXI systems. PXI defines software frameworks (for Microsoft Windows 95, Windows 98, Windows NT, and Windows 2000) for complete systems and requires appropriate device driver software for all PXI peripheral modules to ease system integration. Furthermore, PXI implements the Virtual Instrument Software Architecture (VISA). VISA is used to locate and communicate with serial, VXI, and GPIB peripheral modules. PXI extends VISA beyond these interfaces to allow for the location and control of PXI peripheral modules. This extension preserves the model for instrumentation software that has been adopted by the instrumentation community. The result is a very powerful software commonality that spans PXI, CompactPCI, desktop PCI, VXI, GPIB, and other instrumentation architectures.

The diagram in Figure 1.1 summarizes the scope of the PXI specification by depicting its mechanical, electrical, and software architectures.

![This flowchart is a hierarchical diagram titled **PXI: PCI eXtensions for Instrumentation** at the top. It branches into three main categories:  1.  **Mechanical Architecture**, which subdivides into **CompactPCI** and **PXI Additions**.     *   **CompactPCI** connects to: **8 Slots**, **IEC Connectors**, and **EuroCard Packaging**.     *   **PXI Additions** connects to: **Defined System Slot Location**, **Cooling**, and **Env. Testing**.  2.  **Electrical Architecture**, which subdivides into **PCI and CompactPCI** and **Instrumentation Functions**.     *   **PCI and CompactPCI** connects to: **32/64 Bit Transfers**, **33 MHz**, and **66 MHz**.     *   **Instrumentation Functions** connects to: **Trigger Bus**, **Local Bus**, **Reference Clock**, and **Star Trigger**.  3.  **Software Architecture**, which subdivides into **Operating Systems** and **Driver Software**.     *   **Operating Systems** connects to: **Windows NT**, **Windows 95**, **Windows 98**, and **Windows 2000**.     *   **Driver Software** connects to: **Driver Required**, **VISA**, **Graphical API**, and **Language API**.](.pxi-specification-v2-0/38aa2f50f50312f4444c316fd112600276d3e1e838c2e3c739397028184b2fa0.jpg)

Figure 1.1 The PXI Architecture

# 1.2. Intended Audience and Scope

This specification is organized with a top-down approach whereby general descriptions precede the more detailed specifications found deeper in the subsections. This structure is intended to serve the needs of a variety of audiences from product developers to system integrators to end-users. Product developers may want to become familiar with all portions of this specification while end users may be interested in only the feature set description and perhaps the summaries of how these features are implemented. The goal of this specification is to serve as the central source of information relevant to all users and providers of PXI compatible systems.

The first section of this specification describes the features that PXI systems can offer and how these features can be applied to instrumentation. The subsequent sections cover the mechanical, electrical, and software requirements specific to implementing PXI features.

# 1.3. Background and Terminology

This section defines the acronyms and key words that are referred to throughout this specification. This specification uses the following acronyms:

API—Application Programming Interface

CompactPCI – PICMG 2.0 Specification

Eurocard—European Packaging Specifications (IEC 60297, IEEE 1101.1, IEEE 1101.10, IEEE 1101.11)

GPIB—General Purpose Interface Bus, IEEE 488

ISA—Industry Standard Architecture; desktop PC adapter board specification

PCI—Peripheral Component Interconnect; electrical specification defined by PCISIG

PCISIG—PCI Special Interest Group

PICMG—PCI Industrial Computer Manufacturers Group

PXI—PCI eXtensions for Instrumentation

VISA—Virtual Instrument Software Architecture

VITA—VMEbus International Trade Association

VME—Versa Module Europe; VMEbus specification governed by the VSO

VPP—VXIplug&play Specification

VSO—VITA Standards Organization

VXI—VME Extensions for Instrumentation

This specification uses several key words, which are defined as follows:

RULE: Rules SHALL be followed to ensure compatibility. A rule is characterized by the use of the words SHALL and SHALL NOT.

RECOMMENDATION: Recommendations consist of advice to implementers that will affect the usability of the final module. A recommendation is characterized by the use of the words SHOULD and SHOULD NOT.

PERMISSION: Permissions clarify the areas of the specification that are not specifically prohibited. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. A permission is characterized by the use of the word MAY.

OBSERVATION: Observations spell out implications of rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain rules, so that the reader understands why the rule must be followed.

MAY: A key word indicating flexibility of choice with no implied preference. This word is usually associated with a permission.

SHALL: A key word indicating a mandatory requirement. Designers SHALL implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification. This word is usually associated with a rule.

SHOULD: A key word indicating flexibility of choice with a strongly preferred implementation. This word is usually associated with a recommendation.

# 1.4. Applicable Documents

This specification defines extensions to the base PCI and CompactPCI specifications referenced in this section. It is assumed that the reader has a thorough understanding of PCI and CompactPCI. The CompactPCI specification refers to several other

applicable documents with which the reader may wish to become familiar. This specification refers to the following documents directly:

• PCI Local Bus Specification, Rev. 2.2
PICMG 2.0 R3.0 CompactPCI Specification
• VXIplug&play Specifications (VPP-3.x and VPP-7)
IEC 61326-1:1998, Electrical equipment for measurement, control, and laboratory use—EMC requirements—Part I, General requirements, International Electrotechnical Commission
IEC 1010-1:1990 + A1:1992, Safety requirements for electrical equipment for measurement, control, and laboratory use—Part 1, General requirements, International Electrotechnical Commission
• IEC 60068-1, Environmental testing, International Electrotechnical Commission

# 1.5. Useful Web Sites

Below is a list of web site links that at the time of publication of this specification point to sites with information useful in the understanding and design of PXI products.

<table><tr><td>http://www.pxisa.org/ -</td><td>PXI specifications</td></tr><tr><td>http://www.picmg.org/</td><td>PICMG specifications</td></tr><tr><td>http://www.ieee.org/ -</td><td>IEEE specifications</td></tr><tr><td>http://www.iec.org/ -</td><td>IEC specifications</td></tr><tr><td>http://www.pcisig.com/ -</td><td>PCI specifications</td></tr><tr><td>http://www.vita.com/ -</td><td>VME specifications</td></tr><tr><td>http://www.vxi.org/ -</td><td>VXI specifications</td></tr><tr><td>http://www.vxipnp.org/ -</td><td>VISA specifications</td></tr></table>

# 2. PXI Architecture Overview

This section presents an overview of a PXI system’s features and capabilities by summarizing the mechanical, electrical and software architectures defined by this specification.

# 2.1. Mechanical Architecture Overview

PXI supports the two form factors that are depicted in Figure 2.1. The 3U form factor defines modules that are 100 by 160 mm (3.94 by 6.3 in.) and have two interface connectors. J1 carries the signals required for the 32-bit PCI local bus and J2 carries the signals for 64-bit PCI transfers and the signals for implementing PXI electrical features. The 6U form factor defines modules that are 233.35 by 160 mm (9.19 by 6.3 in.) and may carry up to two additional connectors for future expansion of the PXI specification.

![Based on the provided flowchart/block diagram, here are the labeled blocks and connections:  **Labeled Blocks and Components:** *   **3U PXI**: A block on the left.     *   **Connectors (Right Side)**:         *   **J2**: Associated with '64-Bit PCI and PXI Features'.         *   **J1**: Associated with '32-Bit PCI'.     *   **Mechanism (Left Side)**: A vertical line with latches at the top and bottom. *   **6U PXI**: A block on the right.     *   **Connectors (Right Side)**:         *   **J4**: Associated with 'PXI Reserved' (enclosed in a dashed border).         *   **J3**: Associated with 'PXI Reserved' (enclosed in a dashed border).         *   **J2**: Associated with '64-Bit PCI and PXI Features'.         *   **J1**: Associated with '32-Bit PCI'.     *   **Mechanism (Left Side)**: A vertical line with latches at the top and bottom. *   **Ejector/Injector**: A text label.  **Connections:** *   **Ejector/Injector**: An arrow from this label points to the top latch mechanism of the **6U PXI** block. *   **Inter-block Linkage**:     *   A line connects the top latch mechanism of the **3U PXI** block to the top latch mechanism of the **6U PXI** block.     *   A line connects the bottom latch mechanism of the **3U PXI** block to the bottom latch mechanism of the **6U PXI** block. *   **Structural Outlines**: Lines connect the ejector mechanisms to the connector panels on the right side of each block (top latch to top connector area, bottom latch to bottom connector area), forming the rectangular chassis outline for each module.](.pxi-specification-v2-0/9e8efd1e4445080116aa304daf98ba4c2a39cfa44401f91fb3281527d3d05f2b.jpg)

Figure 2.1 PXI Peripheral Module Form Factors and Connectors

Figure 2.2 presents an example of a typical PXI system to help illustrate the following keywords (in italics). A PXI system is composed of a chassis that supports the PXI backplane and provides the means for supporting the system controller module and the peripheral modules. The chassis must have one system slot and may have one or more peripheral slots. Any number of controller expansion slots may be available to the left of the system slot. The optional star trigger controller, when used, must reside next to the system controller module. If a star trigger controller is not used in a system, a peripheral module can be installed in the slot next to the system controller module. The backplane carries the interface connectors (P1, P2, ...) and provides the interconnection between the controller and peripheral modules. A maximum of seven peripheral modules can be used in a single 33 MHz PXI bus segment, and a maximum of 4 peripheral modules can be used in a single 66 MHz PXI bus

segment. PCI-PCI bridges can be used to add bus segments for additional expansion slots.

![Controller Expansion Slots System Controller Module Peripheral Modules Empty Slot Backplane P2 P1 Chassis Ejector Handles 1 2 3 4 5 6 7 8 System Slot Star Trigger Controller or Peripheral Slot Seven Available Peripheral Slots](.pxi-specification-v2-0/52d4f49984bdbed905cd1ba1ca5cd40dd88ae9314aab894c95ef4423fedea40a.jpg)

Figure 2.2 Example of a 33 MHz 3U PXI System (Single Bus Segment)

# 2.1.1. System Slot Location

PXI defines the system slot location to be on the left end of the PCI bus segment in a basic PXI system. This defined arrangement is a subset of the numerous possible configurations allowed by CompactPCI (a CompactPCI system slot may be located anywhere on a backplane). Defining a single location for the system slot simplifies integration and increases the degree of compatibility between PXI controllers and chassis. Furthermore, the PXI specification requires that if necessary the system controller module should expand to the left into what are defined as controller expansion slots. Expanding to the left prevents system controllers from using up valuable peripheral slots.

PXI also defines the location of a star trigger controller slot that can accept a peripheral module or a special star trigger module that can provide individual triggers to all other peripheral modules. The star trigger signals are routed from the star trigger slot to each peripheral slot on all PXI backplanes.

# 2.1.2. Additional Mechanical Features

All mechanical specifications defined in PICMG 2.0 R3.0 (CompactPCI Specification) apply directly to PXI systems; however, PXI includes additional requirements that simplify system integration. Forced cooling in PXI chassis is required and the airflow direction is defined. Environmental testing for operating and storage temperature ratings of all PXI products is required and must be clearly documented by suppliers.

# 2.1.3. Interoperability with CompactPCI

Interoperability among PXI compatible products and standard CompactPCI products is a very important feature provided by this specification. Many PXI-compatible systems will require components that do not implement PXI-specific features. For example, a user may want to use a standard CompactPCI network interface module in a PXI chassis. Likewise, some users may choose to use a PXI compatible module in a standard CompactPCI chassis. In these cases, the user will not be able to use PXI-specific functions but will still be able to use the basic functions of the module. Note that interoperability between PXI-compatible products that use the J2 connector for PXI-defined signals and other application-specific implementations of CompactPCI chassis (which may define other signal definitions for sub-buses on the P2 backplane connector) is not guaranteed. Of course, both CompactPCI and PXI leverage the PCI local bus, thereby ensuring software and electrical compatibility as depicted in Figure 2.3.

![The diagram is titled **'PCI Electrical and Software Compatibility'** and is enclosed within a large dashed border. Inside, a smaller dashed box labeled **'Full PXI Feature Set'** encompasses the **'PXI Chassis'** and the **'PXI Peripheral Module'**.  The diagram features four labeled blocks: *   **'PXI Chassis'** (a tall rectangle on the left) *   **'CompactPCI Chassis'** (a tall rectangle on the right) *   **'PXI Peripheral Module'** (a rectangle in the upper center) *   **'CompactPCI Peripheral Module'** (a rectangle in the lower center)  The connections (arrows) are as follows: *   An arrow points left from **'PXI Peripheral Module'** to **'PXI Chassis'**. *   An arrow points right from **'PXI Peripheral Module'** to **'CompactPCI Chassis'**. *   An arrow points left from **'CompactPCI Peripheral Module'** to **'PXI Chassis'**. *   An arrow points right from **'CompactPCI Peripheral Module'** to **'CompactPCI Chassis'**.](.pxi-specification-v2-0/1592168d6487b941f52bf607d872e49ee9706d505cba0d4c3fc446fe64007032.jpg)

Figure 2.3 PXI and CompactPCI Interoperability

# 2.2. Electrical Architecture Overview

Many instrumentation applications require system timing capabilities that cannot be directly implemented across standard desktop computer backplanes such as ISA, PCI, or PCMCIA. PXI uses the standard PCI bus and adds specific signals for instrumentation including bused trigger lines, slot-specific triggers, a dedicated

system clock, and slot-to-slot local buses to address the need for advanced timing, synchronization, and side-band communication.

# 2.2.1. Peripheral Component Interconnect (PCI) Features

PXI offers the same performance features defined by the desktop PCI specification, with one notable exception. a PXI system can have up to eight slots per 33 MHz segment (one system slot and seven peripheral slots), whereas a desktop PCI system can have only five per 33 MHz segment (one motherboard or system slot and four peripheral slots). Similarly, a PXI system can have up to five slots per 66 MHz segment (one system slot and four peripheral slots), whereas a desktop PCI system can have only three per 66 MHz segment (one motherboard or system slot and two peripheral slots). The capability to have three additional 33 MHz peripheral slots and two additional 66 MHz peripheral slots is defined in the CompactPCI specification upon which PXI draws. Otherwise, all the features of PCI transfer into PXI:

• 33/66 MHz performance
• 32-bit and 64-bit data transfers
• 132 Mbytes/s (32-bit, 33MHz) to 528 Mbytes/s (64-bit, 66 MHz) peak data rates
System expansion via PCI-PCI bridges
• 3.3V migration
• Plug and Play capability

# 2.2.2. Local Bus

The PXI local bus is a daisy-chained bus that connects each peripheral slot with its adjacent peripheral slots to the left and right. Thus, the right local bus of a given peripheral slot connects to the left local bus of the adjacent slot, and so on. Each local bus is 13 lines wide and can be used to pass analog signals between modules or to provide a high-speed side-band digital communication path that does not affect the PXI bandwidth.

Local bus signals can range from high-speed TTL signals to analog signals as high as 42 V. Keying of adjacent modules is implemented by initialization software that prohibits the use of incompatible modules. This software uses the configuration information specific to each peripheral module to evaluate compatibility before enabling local bus circuitry. This method provides a flexible means for defining local bus functionality that is not limited by hardware keying.

The local bus lines for the leftmost peripheral slot of a PXI backplane are used for the star trigger. Figure 2.4 schematically shows a complete PXI system demonstrating the local buses.

![**Labeled Blocks:** *   System Controller Slot (1) *   Star Trigger/Peripheral Slot (2) *   Peripheral Slot (3) *   Peripheral Slot (4) *   Peripheral Slot (N-1) *   Peripheral Slot (N) *   External Backplane Interface  **Connections:** *   **Star Triggers:** Lines connect the top of 'System Controller Slot (1)' to the top of 'Star Trigger/Peripheral Slot (2)', 'Peripheral Slot (3)', 'Peripheral Slot (4)', 'Peripheral Slot (N-1)', and 'Peripheral Slot (N)'. *   **PCI Arbitration and Clock Signals:** Lines connect the bottom of 'System Controller Slot (1)' to the bottom of 'Star Trigger/Peripheral Slot (2)', 'Peripheral Slot (3)', 'Peripheral Slot (4)', 'Peripheral Slot (N-1)', and 'Peripheral Slot (N)'. *   **Local Bus:** Bidirectional arrows connect 'Star Trigger/Peripheral Slot (2)' to 'Peripheral Slot (3)', 'Peripheral Slot (3)' to 'Peripheral Slot (4)', and 'Peripheral Slot (N-1)' to 'Peripheral Slot (N)'. *   A bidirectional arrow connects 'Peripheral Slot (4)' and 'Peripheral Slot (N-1)'. *   A bidirectional arrow connects 'Peripheral Slot (N)' and 'External Backplane Interface'.](.pxi-specification-v2-0/a8e34d7941c1e06c6e603c63b1d009414bd67817c1fae6c72ed051dabd20746a.jpg)

Figure 2.4 PXI Local Bus Routing

# 2.2.3. System Reference Clock

The PXI 10 MHz system clock (PXI\_CLK10) is distributed to all peripheral modules in a system. This common reference clock can be used for synchronization of multiple modules in a measurement or control system. The PXI backplane specification defines implementation guidelines for PXI\_CLK10. As a result, the low skew qualities afforded by this reference clock make it ideal for precise multimodule synchronization by using trigger bus protocols to qualify individual clock edges.

# 2.2.4. Trigger Bus

The eight PXI bused trigger lines are highly flexible and can be used in a variety of ways. For example, triggers can be used to synchronize the operation of several different PXI peripheral modules. In other applications, one module can control carefully timed sequences of operations performed on other modules in the system. Triggers may be passed from one module to another, allowing precisely timed responses to asynchronous external events that are being monitored or controlled. The number of triggers that a particular application requires varies with the complexity and number of events involved.

# 2.2.5. Star Trigger

The PXI star trigger bus offers ultra-high performance synchronization features to users of PXI systems. The star trigger bus implements a dedicated trigger line between the first peripheral slot (adjacent to the system slot) and the other peripheral slots. A star trigger controller can be installed in this slot and can be used to provide very precise trigger signals to other peripheral modules. Systems that do not require this advanced trigger can install any standard peripheral module in this slot. Through the required use of line-length equalization

techniques for routing the star triggers, PXI systems can meet demanding triggering requirements for which bused triggers are not appropriate. Note that the star trigger can be used to communicate information back to the star trigger controller, as in the case of reporting a slot’s status, as well as responding to information provided by the star trigger controller.

This trigger architecture for PXI gives two unique advantages in augmenting the bused trigger lines. The first advantage is a guarantee of a unique trigger line for each module in the system. For large systems, this eliminates the need to combine multiple module functions on a single trigger line or to artificially limit the number of trigger times available. The second advantage is the low-skew connection from a single trigger point. The PXI backplane defines specific layout requirements such that the star trigger lines provide matched propagation time from the star trigger slot to each module for very precise trigger relationships between each module.

# 2.2.6. System Expansion with PCI-PCI Bridge Technology

A PXI system can be built with more than one bus segment by using standard PCI-PCI bridge technology. The bridge device takes up one PCI load on each of the bus segments that it links together. Thus, a 33 MHz system with two bus segments offers 13 expansion slots for PXI peripheral modules.

$$
\begin{array}{r l} & (2 \text { bus segments }) \times (8 \text { slots per segment }) - (1 \text { system controller slot }) \\ & \quad - (2 \text { slots for PCI - PCI Bridge }) = 1 3 \text { available expansion slots } \end{array}
$$

Similarly, a three-bus segment 33 MHz system would offer 19 expansion slots for PXI peripheral modules.

The trigger architecture defined by PXI has implications for systems with multiple bus segments. The PXI trigger bus provides connectivity within a single bus segment and does not allow physical connection to an adjacent bus segment. This maintains the high performance characteristics of the trigger bus and allows multisegment systems to partition instruments into logical groups. Multiple segments may be logically linked by providing buffers between physical segments. The star trigger provides the means to independently access all 13 peripheral slots in a two-segment system for applications in which a high number of instruments require synchronization and controlled timing. In PXI systems where there are more than two segments, it is recommended that the star triggers are only routed to the slots in the first two segments, but other routings are allowed.

![**Labeled Blocks:** *   PXI Star Trigger *   System Controller *   Slot 1 *   Star Trigger Controller *   Slot 2 *   Slot 3 *   oo *   Slot 7 *   Slot 8 *   PCI-PCI Bridge *   Slot 9 *   Bridge Controls Bus Segment 2 *   Slot 10 *   oo *   Slot 16 *   PXI Trigger Bus (Segment 1) *   PXI Trigger Bus (Segment 2)  **Connections:** *   **PXI Star Trigger:** Vertical arrows descend from the 'PXI Star Trigger' label to connect to 'Slot 2', 'Slot 3', 'Slot 7', 'Slot 8', 'Slot 10', and 'Slot 16'. *   **PCI-PCI Bridge:** A double-headed horizontal arrow labeled 'PCI-PCI Bridge' connects 'Slot 8' and 'Slot 9'. *   **PXI Trigger Bus (Segment 1):** A long double-headed arrow labeled 'PXI Trigger Bus (Segment 1)' connects via vertical double-headed arrows to 'Slot 1', 'Slot 2', 'Slot 3', 'Slot 7', and 'Slot 8'. *   **PXI Trigger Bus (Segment 2):** A long double-headed arrow labeled 'PXI Trigger Bus (Segment 2)' connects via vertical double-headed arrows to 'Slot 9', 'Slot 10', and 'Slot 16'. *   **Bus Segments Connection:** A dashed line connects the 'PXI Trigger Bus (Segment 1)' arrow to the 'PXI Trigger Bus (Segment 2)' arrow.](.pxi-specification-v2-0/abe518ab355232585a27d68de2f713d96de72e8e1df493124b9ea62fe67d8278.jpg)

Figure 2.5 PXI Trigger Architecture for Two Bus Segments

# 2.3. Software Architecture Overview

Like other bus architectures, PXI defines standards that allow products from multiple vendors to work together at the hardware interface level. Unlike many other specifications, however, PXI defines software requirements in addition to bus-level electrical requirements, to further ease integration. These requirements include the support of standard operating system frameworks such as Windows 95, Windows 98, Windows NT, and Windows 2000 (WIN32) and the support of instrumentation software standards developed by the VXIplug&play Systems Alliance (VPP and VISA). Appropriate drivers for all peripheral modules are also required. Clearly, the PXI software specification is motivated by the benefits achieved through leveraging existing desktop software technology.

# 2.3.1. Common Software Requirements

The PXI specification presents software frameworks for PXI systems including Microsoft Windows 95, Windows 98, Windows NT, and Windows 2000. A PXI controller operating in either framework must support the currently available operating system and must support future upgrades. The benefit of this requirement is that the controller therefore also supports the most popular industry-standard application programming interfaces, such as Microsoft and Borland C++, Visual Basic, LabVIEW, and LabWindows/CVI.

PXI also requires that all peripheral modules have device driver software that runs in the appropriate framework. Hardware vendors for other industrial buses that do not have software standards often do not provide any software drivers for their devices. The customer is often given only a manual, which describes how to write software to control the device. The cost to the customer, in terms of engineering effort to support these devices, can be enormous. PXI removes this burden by requiring that manufacturers, rather than customers, develop the driver software.

# 2.3.2. Virtual Instrument Software Standards

PXI systems are required to provide the VISA software standard as the mechanism for locating and controlling GPIB, VXI, serial, and PXI instruments. Bringing the VISA standard to PXI preserves an instrumentation user’s investment in software. VISA provides the link from PXI to a VXI chassis and instruments and to standalone GPIB and serial instruments. VISA provides a standard mechanism to locate, configure, and control PXI modules in a user’s system.

# 2.3.3. Other Software Requirements

PXI also requires that certain software components be made available by peripheral module and chassis vendors. Initialization files that define a system’s configuration and capabilities are required for PXI components. The system software uses this information to ensure proper configuration of a system. For example, this mechanism is used to identify whether or not adjacent peripheral modules have a compatible local bus. If any information is missing, the local bus circuitry is not enabled and the functionality cannot be accessed.

# 3. Mechanical Requirements

This section discusses the additional mechanical requirements for PXI systems. It discusses the location of the system slot, the interoperability of the controller with the chassis, the PXI logo, environmental testing, cooling, grounding, and guidelines for minimizing electromagnetic interference (EMI).

# 3.1. CompactPCI Mechanical Requirements

Both 3U (100 by 160 mm, or 3.94 by 6.3 in.) and 6U (233.35 by 160 mm, or 9.19 by 6.3 in.) form factor modules can implement PXI features as defined in Section 4, Electrical Requirements.

RULE: All mechanical requirements defined in the CompactPCI specification (PICMG 2.0 R3.0) SHALL apply to 3U and 6U PXI compatible modules.

The following sections define additional mechanical requirements and recommendations that are included to ease system integration.

# 3.2. System Slot Location and Rules

All CompactPCI and PXI compatible systems require a backplane/chassis and a system controller module in the system slot. This requirement allows users to mix and match different controllers with different chassis. However, because the CompactPCI specification allows a system slot to be located anywhere relative to peripheral slots, the possibility for confusion and incompatibility exists. To address this problem the following rules must be followed for PXI-compatible systems:

RULE: The system slot SHALL be defined as the leftmost PXI slot in a basic single bus segment PXI chassis/backplane. For documentation purposes this slot is counted as one controller slot.

RECOMMENDATION: If the system controller module requires more than one slot width, it SHOULD extend to the LEFT of the system slot in full slot increments (one slot equals 20.32 mm, or 0.8 in.) into additional controller expansion slots.

OBSERVATION: In a basic PXI system these additional controller slots are for physical expansion of the system controller module only and cannot support peripheral modules. These slots DO NOT have connectors that interface to the PCI bus routed on the backplane.

OBSERVATION: Extending the system slot module to the LEFT allows all PXI peripheral slots to be utilized.

RECOMMENDATION: The system controller module SHOULD NOT extend to the RIGHT of the system slot into peripheral slots.

OBSERVATION: If a system controller module expands to the right, the number of usable PXI peripheral slots is compromised and access to the star trigger slot is eliminated.

RULE: Every PXI system controller module SHALL clearly document how many controller expansion slots (to the left of the system slot) and peripheral slots it occupies.

RULE: Every PXI chassis SHALL clearly document how many peripheral and controller expansion slots are available.

OBSERVATION: The two preceding rules help ensure that end users can easily determine whether a particular controller-chassis pair is compatible and how many peripheral slots are left available.

Figure 3.1 depicts slot designations in a PXI system.
![P2 P1 Ejector Handles 1 2 3 4 5 6 7 8 System Slot Three Controller Expansion Slots Star Trigger Controller Slot Seven Peripheral Slots](.pxi-specification-v2-0/1d8d94fcda4c4cb8ecbaafe44c9c4fb52e042b139b76c21cec11f1fefa59eb85.jpg)

Figure 3.1 Example of PXI Slot Designations for a Chassis

# 3.3. Logos and Compatibility Glyphs

RULE: A PXI chassis SHALL clearly mark each physical slot with a unique number. The number SHALL be located within the compatibility glyph.

OBSERVATION: The preceding rule applies to a chassis with multiple bus segments as well as to a single-segment chassis.

PERMISSION: Vendors who are members of the PXI Systems Alliance MAY use the PXI logo as defined below on either the front panel or the injector/ejector handle of products claiming full compliance with the PXI specification.

RULE: If the PXI logo is used, the vendor SHALL obtain a license to use the trademarked logo from the PXI System Alliance.

RULE: If the PXI logo is used, it SHALL NOT be altered in any way other than scale. The logo SHALL NOT incorporate any additions.

Figure 3.2 shows the PXI logo. Logo artwork as well as the license can be obtained from the PXI Systems Alliance once becoming a member.

![PXI™](.pxi-specification-v2-0/057d6596d1f73d9e450d35a2960e4f53511a5f0d2c04e4f0d32a272765b23e1e.jpg)

Figure 3.2 PXI Logo

PERMISSION: The PXI logo MAY be used as a substitute for the CompactPCI logo defined in PICMG 2.0 R3.0. Additionally, a product MAY display both the CompactPCI logo and the PXI logo.

RULE: Modules and backplanes SHALL use the compatibility glyphs as defined in the PICMG 2.0 R3.0 (CompactPCI specification).

RULE: Modules and backplanes SHALL use the glyph shown in Figure 3.3 (square at 45°) for the star trigger slot/module. This slot is always located next to the system slot. Because this slot can also support standard peripheral modules, the peripheral module glyph (circle) SHALL also be used for this slot.

![The image displays a simple geometric shape: a square rotated by 45 degrees, creating a diamond orientation. It consists of a thick black outline with a white interior, set against a plain white background.](.pxi-specification-v2-0/7245f599a8adacaea31af2b341ec14f6a1f98be359116d64ec05c90721a42159.jpg)
Figure 3.3 Star Trigger Slot Glyph

RULE: Chassis and backplanes SHALL use the glyph shown in Figure 3.4 (vertical line) between slot numbers to indicate boundaries between PCI segments.

![-1](.pxi-specification-v2-0/8800b20e9106edcd04e88c5a90afde4ab8dcb332f20183ed7ba7d870e4b1436f.jpg)

Figure 3.4 PCI Segment Divider Glyph

# 3.4. Environmental Testing

RULE: PXI chassis, system controller modules, and peripheral modules SHALL be tested for storage and operating temperature ranges.

RECOMMENDATION: PXI chassis, system controller modules, and peripheral modules SHOULD be tested for humidity, vibration, and shock.

RECOMMENDATION: All environmental testing SHOULD be carried out according to the procedures described in IEC 60068.

RULE: Test results and reports generated for environmental testing SHALL be made available to end users of PXI systems. All manufacturers of PXI chassis, system controller modules, and peripheral modules SHALL supply operating and storage temperature ratings for their products.

RULE: If a manufacturer chooses to use environmental testing procedures other than those described in IEC 60068, then these procedures, in addition to the test results and reports, SHALL be documented and made available to the customer.

OBSERVATION: It is the system integrator’s responsibility to select modules and chassis appropriate for the application’s environmental requirements.

# 3.5. Cooling Specifications

# 3.5.1. Plug-in Module Requirements

RULE: Plug-in modules SHALL be designed to allow a suitable airflow path from bottom to top as shown in Figure 3.5.

![Pure technical line drawing of a mechanical assembly without any text, numbers, or symbols](.pxi-specification-v2-0/26175a7126ded1f57da80968e972e2f37282f3915e00a166c4e89a65c759ffe9.jpg)

Figure 3.5 Cooling Airflow Direction in a PXI System

RULE: Plug-in module manufacturers SHALL document and make available to the customer the nominal wattage generated by the module under normal operating conditions.

# 3.5.2. Chassis Requirements

RULE: Chassis SHALL provide active cooling that flows from the bottom to the top of a plugged-in module as shown in Figure 3.5.

RULE: Chassis manufacturers SHALL document and make available to the customer the maximum total wattage that a given chassis can dissipate and the maximum wattage dissipated for the worst-case slot. Furthermore, the manufacturer SHALL document and make available to the customer the specific test procedure used to determine these wattage values.

# 3.6. Chassis and Module Grounding Requirements and EMI Guidelines

RULE: Chassis SHALL provide a direct (low-impedance) means for connecting the chassis ground to earth ground.

OBSERVATION: A grounding stud may be used to provide direct access to chassis ground.

RECOMMENDATION: As defined in PICMG 2.0 R3.0, PXI modules SHOULD use metalized shell connectors for EMI/RFI protection. The shell SHOULD be electrically connected to the front panel through a low impedance path in accordance with IEEE 1101.10.

RECOMMENDATION: PXI modules SHOULD NOT connect chassis ground through a low-impedance path to logic ground used onboard.

# 3.7. Regulatory Requirements

The following standards assure uniform performance and international portability of PXI systems and modules. Allowances are made for devices not intended for

international sale. All regulatory compliance information must be clearly documented for the user. Subsequently issued standards or amendments to these standards shall apply.

# 3.7.1. Requirements for EMC

RULE: Testing SHALL be performed, either by the manufacturer or a competent laboratory, marked accordingly, and documented showing compliance to the following EMC standard(s).

IEC 61326-1:1998, Electrical equipment for measurement, control, and laboratory use—EMC requirements—Part I, General requirements1 :

• Localized EMC standards may be substituted if sale and use are restricted accordingly.2
Use current edition of EN 55011, Group 1, Class A or Class B Limits, at 10 m.
• Continuous unmonitored operation is assumed unless otherwise specified by manufacturer.

# 3.7.2. Requirements for Electrical Safety

RULE: Testing SHALL be performed, either by a competent organization or qualified manufacturer, marked accordingly, and documented showing compliance to the following electrical safety standard(s). Strictly extra low voltage (SELV) devices do not need formal agency testing, though the basic requirements still apply, such as material flammability specified, DC power outputs fused or limited, and so on.

IEC 1010-1:1990 + A1:1992, Safety requirements for electrical equipment for measurement, control, and laboratory use—Part 1, General requirements:

• IEC 950 and amendments are acceptable for applications restricted to the office use only.
• Localized safety standards may be substituted if sale and use are restricted accordingly. 2

# 3.7.3. Particular Requirements for Chassis

RULE: Chassis manufacturers, or a designated party, SHALL demonstrate EMC compliance with a commonly available controller. At minimum the controller SHALL apply a 33 MHz clock to the backplane, or higher as the technology commonly supports, unless the marketing and use of the chassis is restricted to specific kinds of system controllers or platforms. A reasonably common processor speed is sufficient for this test. The complete controller system, including hard drive, floppy drive, serial, parallel, keyboard, mouse, and video ports (as offered with the controller) will be exercised with typical peripherals. Filling remaining slots, if any, is not required. Special shielding or suppression options, if used to achieve compliance, SHALL be documented and available to the user.

RULE: The chassis SHALL be qualified for electrical safety as listed previously. Manufacturer claims of safety compliance are not sufficient without independent verification and regular inspection by a competent agency.

# 4. Electrical Requirements

This chapter discusses the detailed electrical requirements for developing PXIcompatible peripheral modules, controllers, and backplanes. It discusses all signals required for PXI systems and their related implementation requirements. It also discusses appropriate connector pinouts, power supply requirements, and 6U form factor implementation issues.

# 4.1. PXI Signal Groups

This section details all the signals required for PXI systems, including those mapped directly from CompactPCI on P1/J1, the 64-bit signals duplicated on P2/J2, and the PXI-specific signals located on P2/J2. The PXI-specific signals include those required for the trigger bus, the reference clock, the local buses, and the star trigger.

# 4.1.1. P1/J1: Signals

RULE: All signals on the P1/J1 connector of a PXI module and the mating P1 connector of a PXI backplane SHALL meet all the requirements of the PICMG 2.0 R3.0 specification (CompactPCI) for both peripheral modules and system modules.

In order for a system slot controller module to function correctly in a PXI or CompactPCI system, the BIOS of the controller must have its interrupt routing table configured to allow for the AD[25:31] to IDSEL mapping with associated PCI interrupt routing as defined in the PICMG 2.0 R3.0 specification (CompactPCI). Connecting the IDSEL lines of backplane PCI devices or PCI-PCI bridges on the first PCI segment to address lines other than AD[25:31] or not connecting these devices to the correct ordering of PCI interrupt lines could cause the PXI or CompactPCI system to function incorrectly. Also, since the PCI-PCI bridge specification was written assuming a bridge would be placed on a PCI plug in card, care must be taken to route the interrupts on the secondary side of the bridge depending on which AD[25:31] is used for the bridge’s IDSEL.

RULE: Backplane PCI devices, PCI-PCI bridges, and peripheral slots on the first PCI segment SHALL have their IDSEL lines connected to one of AD[25:31].

RULE: Backplane PCI devices, PCI-PCI bridges, and peripheral slots on the first PCI segment SHALL have their INTA#, INTB#, INTC#, and INTD# pins routed to the system slot’s INTA#, INTB#, INTC#, INTD# pins depending on which AD[25:31] line their IDSEL line is connected to in accordance with the PICMG 2.0 R3.0 specification (CompactPCI).

# 4.1.2. P2/J2: Signals

The PICMG 2.0 R3.0 (CompactPCI) specification defines an open pinout for P2/J2, which allows for custom back-panel I/O implementations.

The PXI back-panel I/O definition of signals on the P2/J2 connector consists of signals mapped from the CompactPCI 64-bit connector pinout and new signals defined by this specification. The only differences between the PXI pinout and the CompactPCI 64-Bit connector pinout are on signals that are reserved or not used in the CompactPCI specification (PICMG 2.0 R3.0). Therefore, all modules that meet the requirements of the CompactPCI 64-bit specification will function in a PXI system. Furthermore, all PXI modules will work in a system that meets the requirements of the CompactPCI 64-bit specification, but without the complete set of benefits of PXI.

# 4.1.2.1. Signals from CompactPCI 64-Bit Connector Specification

To allow for applications that require higher bandwidth than 32-bit PCI can provide, PXI has incorporated the pieces of the CompactPCI 64-bit specification that are necessary to support 64-bit operation and has used the remaining resources for instrumentation. This section describes the signals that are mapped from the CompactPCI 64-bit specification. The remaining signals are described in subsequent sections.

# System Slot

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the system slot: GND, V(I/O), AD[32:63], C/BE[4:7]#, DEG#, FAL#, PRST#, SYSEN#, CLK[1:6], GNT[1:6]#, REQ[1:6]#, GA0-GA4, SMB\_ALERT#, SMB\_SCL, SMB\_SDA, and the RSV pins.

RULE: The system slot interface in a PXI system SHALL be as defined in the PICMG 2.0 R3.0 Specification (CompactPCI).

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV (bused reserved) in the CompactPCI 64-bit pinout for directly accessing PXI features on system modules.

# Peripheral Module

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the peripheral slots: GND, V(I/O), AD[32:63], C/BE[4:7]#, GA0-GA4, and UNC

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV, CLK[1:6], GNT[1:6]#, REQ[1:6]#, and RSV in the CompactPCI 64-bit pinout for instrumentation features on peripheral modules. Note that the CLK[1:6], GNT[1:6]# and REQ[1:6]# signals are not implemented on CompactPCI peripheral modules and slots.

# Backplane

RULE: The following signals SHALL meet all the requirements of the PICMG 2.0 R3.0 specification for the 64-bit CompactPCI pinout on the backplane: GND, V(I/O), AD[32:63], C/BE[4:7]#, DEG#, FAL#, and PRST#, SYSEN#, UNC , GA0-GA4, SMB\_ALERT#, SMB\_SCL, SMB\_SDA, and the RSV pins.

RULE: As in the CompactPCI specification, the backplane SHALL route CLK[1:6], GNT[1:6]#, and REQ[1:6]# from the system slot to the appropriate pins of the J1 connectors on the peripheral slots.

RULE: The backplane SHALL leave all the RSV lines on the system slot disconnected.

OBSERVATION: The PXI implementation of back-panel I/O uses the pins that are BRSV, CLK[1:6], GNT[1:6]#, REQ[1:6]#, and RSV (reserved) on peripheral slots and the BRSV pins on the system slot in the CompactPCI 64-bit pinout for instrumentation features on the backplane. The CLK[1:6], GNT[1:6]# and REQ[1:6]# signals are not implemented on CompactPCI backplane peripheral slots.

OBSERVATION: The PXI implementation of back-panel I/O routes all of the bused reserved signals from the CompactPCI 64-bit pinout as bused signals on the PXI backplane. However, most of the signals are not reserved in the PXI signal definition and are explained in the Section 4.1.2.5, Trigger Bus.

# 4.1.2.2. PXI Bused Reserved Signals

# System Slot

The following signals are reserved for future PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A system controller module SHALL NOT connect to the PXI\_BRSV signals.

# Peripheral Slots

The following signals are reserved for PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A peripheral module SHALL NOT connect to the PXI\_BRSV signals.

# Backplane

The following signals are reserved for PXI use: PXI\_BRSVA15 and PXI\_BRSVB4.

RULE: A backplane SHALL bus each PXI\_BRSV signal to each slot.

OBSERVATION: PXI\_BRSV signals are implemented on the backplane exactly like CompactPCI BRSV signals.

# 4.1.2.3. Local Buses

PXI implements a daisy-chained local bus between adjacent peripheral modules. The local bus is a user-definable bus (13 lines wide) that can be used for a wide variety of applications. The range of applications may vary from passing an analog signal between two modules to high-speed data movement that does not affect the PXI bandwidth. For most slots, the functionality of the local bus is user-definable; however, there are specific implementations that the PXI specification defines.

Note that the system controller module does not implement the local bus as it uses those pins for PCI arbitration and clocking functionality. The slot adjacent to the system slot uses its available local bus left signals for the star trigger functionality defined later. Similarly, the rightmost slot of the bus has no slot to its right; hence, the local bus right pins can either be unused or routed for a chassis-specific implementation. One example of chassis-specific implementation is routing the local bus to another adjacent PXI bus segment. The remainder of the slots can use the local bus for any specified purpose. Refer to Figure 2.4 for a diagram of local bus routing.

For system configuration purposes, the chassis configuration of the local bus can be determined by the initialization (.ini) file of the chassis. The .ini file lists each slot and its location in the system. The system configuration software uses this information to determine whether or not a system is put together properly.

The following rules apply to all implementations of the local bus:

# Peripheral Module

RULE: A peripheral module SHALL NOT drive more than ± 42 V onto any local bus line.

RULE: A peripheral module SHALL NOT drive more than 200 mA DC current into any local bus line.

PERMISSION: A peripheral module MAY connect its local bus left to its local bus right if passing the local bus to an additional module is required. This connection should be performed with caution because

the length and/or characteristic impedance specifications of the local bus might be violated.

PERMISSION: On a peripheral module, a local bus signal MAY be connected to ground.

OBSERVATION: The preceding permission allows local bus implementations to have improved grounding and/or shielding.

RULE: On a peripheral module, if a local bus signal is not connected to ground, it SHALL power up in a high-impedance state. All local bus signals (except grounded ones) SHALL remain in a high-impedance state until system configuration software has determined that the local bus signals are compatible with the chassis and other peripheral modules in the system.

PERMISSION: A peripheral module MAY pull-up a local bus signal to V (I/O) to prevent an input from powering up in an unstable state.

RULE: Each peripheral module SHALL have a maximum input leakage current of 100 µA on each local bus line.

# Backplane

RULE: On each bus segment, a backplane SHALL route PXI\_LBR[0:12] from each slot in column A of Table 4.1 to the PXI\_LBL[0:12] of the corresponding slot in column B, provided that both slots exist on the bus segment.

Table 4.1 Local Bus Routings

<table><tr><td>A</td><td>B</td></tr><tr><td>IDSEL = AD31</td><td>IDSEL = AD30</td></tr><tr><td>IDSEL = AD30</td><td>IDSEL = AD29</td></tr><tr><td>IDSEL = AD29</td><td>IDSEL = AD28</td></tr><tr><td>IDSEL = AD28</td><td>IDSEL = AD27</td></tr><tr><td>IDSEL = AD27</td><td>IDSEL = AD26</td></tr><tr><td>IDSEL = AD26</td><td>IDSEL = AD25</td></tr></table>

OBSERVATION: If a slot does not exist on the bus segment due to the AD[25:31] being used for the IDSEL of a backplane PCI device or a PCI-PCI bridge, then other local bus routings are possible provided only physically adjacent slots are connected.

OBSERVATION: There is no local bus connection to the system slot.

RULE: The backplane SHALL NOT provide any termination or buffering of local bus signals. Each signal SHALL be implemented as a direct connection between adjacent peripheral slots.

RULE: The signal length of local bus signals between slots SHALL be less than 3 in. and SHALL be matched within 1 in. between all local bus traces. The characteristic impedance of each trace SHALL be $6 5 \Omega \pm 1 0 \%$ .

PERMISSION: The backplane MAY route the local bus between two bus segments provided the signal length rule is met.

RULE: Bus segment boundaries SHALL be documented.

OBSERVATION: Documenting bus segment boundaries allows users to optimize systems by grouping boards that frequently talk to each other on the same segment.

PERMISSION: A slot at the end of a PXI segment or next to the system slot has one local bus that is not routed to another peripheral slot. The backplane MAY route these local buses for other uses.

RULE: A star trigger slot SHALL NOT implement a local bus left. Instead, the remaining pins SHALL be routed to support the star triggers.

RULE: If a chassis implements an external backplane interface with the local bus right of a slot at the end of a PXI segment, it SHALL be the highest numbered slot in the chassis.

OBSERVATION: A chassis will have at most one slot with an external backplane interface.

# 4.1.2.4. Reference Clock: PXI\_CLK10

The PXI backplane is responsible for providing a common reference clock for synchronization of multiple modules in a measurement or control system. The variable frequency of the PCI system clock limits its usefulness in this application. PXI\_CLK10 is a 10 MHz clock provided independently to each peripheral slot. PXI\_CLK10 can be used to run multiple modules in synchronization from a common reference. The low skew qualities make it ideal for qualifying trigger protocols.

RULE: The PXI\_CLK10 provided by the backplane SHALL be a 10 MHz TTL signal. Its accuracy SHALL be ± 100 ppm or better over the specified operating temperature and time.

OBSERVATION: Because of drift over time, the oscillator chosen MAY need to be 50 ppm accurate or better to meet the requirement of the preceding rule.

RULE: The PXI\_CLK10 signal SHALL have a 50% ± 5% duty cycle when measured at the 2.0 V transition point.

RULE: The clock to each peripheral slot SHALL be driven by an independent buffer that has a source impedance matched to the backplane.

RULE: The backplane SHALL provide for a skew of less than 1 ns between slots.

RECOMMENDATION: A backplane SHOULD allow PXI\_CLK10 to be derived from an external source to allow for a more accurate reference.

OBSERVATION: The star trigger slot has defined a pin for providing an external clock.

RULE: If the PXI\_CLK10 is switched between sources, the minimum pulse width created SHALL be no less than 30 ns and the minimum time between successive edges of the same polarity SHALL be no less than 80 ns.

OBSERVATION: The preceding rule is intended to prevent a state machine from being corrupted by glitches in the clock during transition.

# 4.1.2.5. Trigger Bus

The PXI trigger bus provides intermodule synchronization and communication. The trigger bus lines can be used for trigger or clock transmission. A few standard triggering protocols are defined to facilitate interoperability, but use of the trigger bus is not limited to the defined protocols. The PXI trigger bus lines may be used as general purpose intermodule bused lines using other manufacturer-defined protocols.

The PXI trigger bus consists of the following eight signals:

PXI\_TRIG[0:7]

# Clock Transmission

Variable frequency clock transmission allows multiple modules to share a timebase that is not a derivative of the PXI\_CLK10. For example, two data acquisition modules using a 44.1 kS/s CD audio sampling rate could share a clock that is a multiple of the 44.1 kHz. Type A drivers, defined later, prevent degradation of the clock jitter over the bused transmission medium.

PERMISSION: PXI\_TRIG[0:7] MAY be used for variable frequency clock transmission.

RECOMMENDATION: To facilitate interoperability between sources and receivers of a variable frequency clock, PXI\_TRIG[7] SHOULD be used to source and receive such clocks.

# PXI Trigger Protocols

Some standard protocols are defined in the following sections.

# PXI Asynchronous Trigger

The PXI asynchronous trigger protocol is a single-line broadcast trigger. Figure 4.1 and Table 4.2 show the timing parameters.

RULE: A PXI asynchronous trigger source SHALL meet the timing requirements listed in Table 4.2.

![T_H V_OH = 2.0 V V_OL = 0.8 V T_L](.pxi-specification-v2-0/a0f399851366bfe961dd1456eb6224c8fbe447cd0cc2a3e4a1c3ef5151123ace.jpg)

Figure 4.1 PXI Asynchronous Trigger Timing

Table 4.2 PXI Asynchronous Trigger Timing Parameters

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td></tr><tr><td> $T_h$ </td><td>pulse width high</td><td>18 ns</td><td>—</td></tr><tr><td> $T_l$ </td><td>pulse width low</td><td>18 ns</td><td>—</td></tr><tr><td colspan="4">Note:The pulse width is measured at the driver with a 50 pf equivalent load.</td></tr></table>

OBSERVATION: The preceding rule guarantees PXI asynchronous trigger receivers a minimum of 10 ns pulse widths on PXI asynchronous trigger pulses.

# PXI Synchronous Trigger

The PXI synchronous trigger protocol can be used to synchronize PXI\_CLK10 derived timed operations on module clusters. A PXI\_TRIG line is driven by a module and the participating modules respond to this line synchronously at the next PXI\_CLK10 rising edge. The reference clock is PXI\_CLK10.

Figure 4.2 shows PXI synchronous trigger timing.

![PXI_CLK10 Output Input -Vtest -Vtest Tval Vtest -Thd Vtest -Tsu -Th](.pxi-specification-v2-0/95043fa6dc35e2865b75c018c8899d1e5a099f609296c686b9c44a37dc844c8c.jpg)

Figure 4.2 PXI Synchronous Trigger Timing

RULE: A PXI synchronous trigger source SHALL meet the timing requirements listed in Table 4.3.

Table 4.3 lists PXI synchronous trigger timing requirements.

Table 4.3 PXI Synchronous Trigger Timing

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td></tr><tr><td> $T_{hd}$ </td><td>Output hold time from PXI_CLK10</td><td>2 ns</td><td>—</td></tr><tr><td> $T_{val}$ </td><td>Output signal valid from PXI_CLK10</td><td>—</td><td>65 ns</td></tr><tr><td> $T_{su}$ </td><td>Input set up time to PXI_CLK10</td><td>23 ns</td><td>—</td></tr><tr><td> $T_{h}$ </td><td>Input hold time from PXI_CLK10</td><td>0 ns</td><td>—</td></tr><tr><td colspan="4">Note:Minimum times are measured with 0 pf equivalent load. Maximum times are measured with 50 pf equivalent load.</td></tr></table>

OBSERVATION: The output signal valid timing from PXI\_CLK10 allows either rising or falling edges of PXI\_CLK10 to be used for sourcing PXI synchronous triggers.

# Backplane

RULE: For each PXI segment in a PXI chassis, the PXI chassis SHALL bus the PXI\_TRIG[0:7] signal to each PXI slot (system and peripheral) in that segment. A chassis SHALL NOT directly connect PXI\_TRIG buses from different PXI segments. If a system slot controls multiple PXI segments, it SHALL NOT directly connect PXI trigger buses from different segments.

OBSERVATION: Trigger buses from multiple segments are physically disconnected to maintain signal integrity and allow for incident wave switching of Type A trigger drivers. However, the buses may be logically connected by buffering the signals between segments.

RULE: PXI\_TRIG[0:7] SHALL be fast Schottky diode terminated at both ends of the bus segment on the backplane to + 5 V and ground as shown in Figure 4.3.

![+5 V PXI_TRIG](.pxi-specification-v2-0/278d82105fed955ded829897945909f8db986e20a5a3a3128448232c74f49027.jpg)

Figure 4.3 PXI Trigger Bus Termination

RULE: The unloaded characteristic impedance for the backplane $Z _ { \mathrm { l , m i n } }$ SHALL be $7 5 \Omega \pm 1 0 \%$ using a stripline transmission line geometry.

OBSERVATION: The higher backplane impedance lowers the driver strength requirements for incident wave switching.

RULE: The signal trace lengths of PXI trigger bus signals SHALL be less than 10 in. and matched within 1 in. between all trigger bus signals.

# Peripheral or System Module

RULE: Printed circuit board trace lengths for PXI trigger bus signals SHALL be less than or equal to 1.5 in.

PERMISSION: A PXI module (system or peripheral) MAY leave any number of PXI trigger bus signals unconnected.

RECOMMENDATION: The following recommendations improve interoperability between modules using the PXI trigger bus. For triggering applications, if a PXI module (system or peripheral) connects to a subset of the PXI trigger signals, it SHOULD connect to PXI\_STAR and PXI\_TRIG[0:n-2] where n is the number of trigger lines on the peripheral module. For sourcing or receiving clocks, PXI\_TRIG[7] SHOULD be used.

RULE: Upon power up, the PXI\_TRIG[0:7] lines and drivers SHALL remain in a high impedance state until configured by software.

RULE: PXI\_TRIG[0:7] I/O buffers SHALL be compliant with the DC specifications listed in Table 4.4.

Table 4.4 DC Specifications

<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Min</td><td>Max</td><td>Notes</td></tr><tr><td>Vih</td><td>Input High Voltage</td><td>—</td><td>2.0 V</td><td> $V_{cc} + 0.5$  V</td><td>1</td></tr><tr><td>Vil</td><td>Input Low Voltage</td><td>—</td><td>-0.5 V</td><td>0.8 V</td><td>—</td></tr><tr><td>Il</td><td>Leakage Current</td><td>0 &lt; Vin &lt; Vcc</td><td>—</td><td>±70 μA</td><td>1, 2</td></tr><tr><td>Voh</td><td>Output High Voltage</td><td>Iout = -2 mA</td><td>2.4 V</td><td> $V_{cc} + 0.5$  V</td><td>1</td></tr><tr><td>Vol</td><td>Output Low Voltage</td><td>Iout = 4 mA</td><td>-0.5 V</td><td>0.55 V</td><td>—</td></tr><tr><td>Cpin</td><td>Input, Output,Bidirectional PinCapacitance</td><td>—</td><td>—</td><td>10 pf</td><td>—</td></tr><tr><td colspan="6">Notes:1. Vcc refers to the 5 V power supply rail.2. Leakage current includes output leakage for bidirectional buffers in a high-impedance state.</td></tr></table>

OBSERVATION: The DC specifications are met by 5 V tolerant LVTTL-compatible I/O buffers.

PERMISSION: To prevent floating inputs, PXI\_TRIG[0:7] lines used on a PXI module (system or peripheral) MAY be pulled up on the module with a pull-up resistance whose value is shown in Table 4.5.

Table 4.5 Pull-Up Resistor Values

<table><tr><td>Signaling Rail</td><td>Rmin</td><td>Rmax</td></tr><tr><td>5 V</td><td>11 kΩ</td><td> $[V_{ccmin} - Vx]/[Iih]*$ </td></tr><tr><td>3.3 V</td><td>19 kΩ</td><td> $[V_{ccmin} - Vx]/[Iih]*$ </td></tr><tr><td colspan="3">*  $V_x = 2.4 V$ , which is the desired voltage on the bus in a non-driven state, and Iih is the maximum leakage current for the device buffer.</td></tr></table>

RECOMMENDATION: Type A drivers SHOULD be used for clock transmission over the PXI trigger bus. Type A drivers are capable of incident wave switching on rising edges, preventing jitter degradation due to transmission line effects. Refer to Table 4.6 for Type A driver specifications.

Table 4.6 Type A, High Current Driver, AC Specifications

<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Min</td><td>Max</td></tr><tr><td>Vsoh(AC)</td><td>Switching voltage high</td><td></td><td>2.3 V</td><td>—</td></tr><tr><td>Ioh(AC)</td><td>High source current</td><td>@Vsoh(AC)</td><td>75 mA</td><td>—</td></tr></table>

RECOMMENDATION: Intermediate voltage levels (Vol ≤ V ≤ Voh) may be present on the trigger bus. Schmitt trigger inputs SHOULD be used to guard against sensing multiple transitions on edge-sensitive inputs when the voltage on the bus is at intermediate levels due to transmission line effects on the bus.

RECOMMENDATION: Rising edges SHOULD be used as active edges in asynchronous trigger protocols.

# 4.1.2.6. Star Trigger

In addition to the bused PXI triggers, the PXI bus has included an independent trigger (PXI\_STAR) for each slot that is oriented in a star configuration from the star trigger slot. The star trigger slot is adjacent to the system slot and uses the 13 left local bus signals as the star triggers. This allows a single star trigger slot to control or monitor triggers in two PCI bus segments. In systems with more than two PCI segments, it is recommended that the star triggers are only routed to the slots in the first two segments, but other routings are allowed.

The PXI specification does not specify the functionality of the star trigger slot module or even require that the system be constructed with a star trigger module. Typical uses would include triggering multiple modules independently with low skew, monitoring a trigger from peripheral slots, and routing triggers between slots. One star trigger slot pin is dedicated to allow an external 10 MHz frequency standard to be routed as PXI\_CLK10.

# Backplane

RULE: The first slot to the right of the system slot in a chassis SHALL be a star trigger slot.

RULE: A chassis SHALL NOT have more than one star trigger slot.

OBSERVATION: The star trigger slot may also be used as a generic peripheral slot with the exception that the left side local bus is unavailable because these pins connect to the star triggers. The star trigger slot does not have a PXI\_STAR; instead, the pin in the star trigger slot is used for an external frequency reference.

RULE: The PXI backplane SHALL route the signals from the star trigger slot to each peripheral with a trace impedance of 65 $\Omega \pm 1 0 \%$ .

Recommendation: The PXI backplane SHOULD route the signals from the star trigger slot to each peripheral slot according to Table 4.7.

RULE: If signal routing from the star trigger to each peripheral slots is used other than the routing described in Table 4.7 or if the chassis has been designed for configurable routing, then the chassis vendor SHALL document the possible routings of such a system.

Recommendation: If the chassis has been designed for configurable routing, then the chassis vendor SHOULD provide software that can be used in all PXI frameworks to allow the user or system integrator to change the routing.

Table 4.7 Star Trigger Mapping

<table><tr><td>Star Trigger Signal</td><td>Physical Peripheral Slot</td></tr><tr><td>PXI STAR0</td><td>3</td></tr><tr><td>PXI STAR1</td><td>4</td></tr><tr><td>PXI STAR2</td><td>5</td></tr><tr><td>PXI STAR3</td><td>6</td></tr><tr><td>PXI STAR4</td><td>7</td></tr><tr><td>PXI STAR5</td><td>8</td></tr><tr><td>PXI STAR6</td><td>9</td></tr><tr><td>PXI STAR7</td><td>10</td></tr><tr><td>PXI_STAR8</td><td>11</td></tr><tr><td>PXI_STAR9</td><td>12</td></tr><tr><td>PXI_STAR10</td><td>13</td></tr><tr><td>PXI_STAR11</td><td>14</td></tr><tr><td>PXI_STAR12</td><td>15</td></tr></table>

RULE: The PXI\_STAR line lengths SHALL be matched in propagation delay to within 1 ns, and the delay from the star trigger slot to each peripheral module SHALL NOT exceed 5 ns.

# Peripheral Module

RULE: The driver of PXI\_STAR, which may be the star trigger module or a peripheral module, SHALL have a source impedance of 65 Ω ± 10% to match the backplane impedance.

RULE: When a peripheral module or star trigger controller drives a PXI\_STAR, the signaling levels SHALL NOT exceed 5V.

RULE: A peripheral module SHALL NOT drive its PXI\_STAR when reset.

PERMISSION: A peripheral module MAY pull-up the PXI\_STAR signal to prevent an unstable input.

RULE: The leakage current of a peripheral module connected to PXI\_STAR SHALL NOT exceed 650 µA.

OBSERVATION: The same trigger protocols defined for the PXI TTL trigger bus MAY be used on the PXI\_STAR signals.

PERMISSION: The PXI\_CLK10\_IN signal of the star trigger slot MAY be used to provide an external 10 MHz reference for PXI\_CLK10.

RULE: A module in the star trigger slot SHALL NOT drive the PXI\_STAR/CLK10\_IN signal, except to provide a reference for PXI\_CLK10.

OBSERVATION: The presence of a periodic signal on the PXI\_CLK10\_IN signal MAY be used to indicate that an external reference is to be used.

# 4.1.3. Electrical Guidelines for 6U

Larger 6U size modules are desirable for the extra module space and possibly for future additional functionality that can be provided through the J3 and J4 connectors. In many cases, the extra space on a 6U module is needed only for extra circuitry, and the module requires only the J1 and J2 connectors for PXI. J3 and J4 are reserved for future revisions of the PXI specification.

RULE: 6U PXI peripheral modules SHALL implement only J1 and J2. J3 and J4 SHALL NOT be loaded on 6U peripheral modules.

PERMISSION: Since J5 is not reserved for future revisions of the PXI specification, vendors MAY use J5 for custom implementations of PXI provided they only offer such a module as part of their custom PXI system.

# 4.2. Connector Pin Assignments (J1/P1 and J2/P2)

To help in reviewing the tables in this section and locating the appropriate specification for signal requirements, Table 4.8 lists all signals alphabetically by original specification (PXI, CompactPCI, or PCI).

Table 4.8 PXI System Signal Groups

<table><tr><td>System</td><td colspan="3">Signals</td></tr><tr><td rowspan="3">PXI</td><td>PXI_BRSV</td><td>PXI_LBL[0:12]</td><td>PXI_STAR[0:12]</td></tr><tr><td>PXI_CLK10</td><td>PXI_LBR[0:12]</td><td>PXI_TRIG[0:7]</td></tr><tr><td>PXI_CLK10_IN</td><td></td><td></td></tr><tr><td rowspan="8">CompactPCI</td><td>BD_SEL#</td><td>HEALTHY#</td><td>REQ#[0:6]</td></tr><tr><td>BRSV</td><td>INTP</td><td>RSV</td></tr><tr><td>CLK[0:6]</td><td>INTS</td><td>SYSEN#</td></tr><tr><td>DEG#</td><td>IPMB_PWR</td><td>SMB_ALERT#</td></tr><tr><td>ENUM#</td><td>IPMB_SCL</td><td>SMB_SCL</td></tr><tr><td>FAL#</td><td>IPMB_SDA</td><td>SMB_SDA</td></tr><tr><td>GA0-GA4</td><td>PRST#</td><td>UNC</td></tr><tr><td>GNT#[0:6]</td><td></td><td></td></tr><tr><td rowspan="12">PCI</td><td>ACK64#</td><td>INTD#</td><td>TCK</td></tr><tr><td>AD[0:63]</td><td>IRDY#</td><td>TDI</td></tr><tr><td>C/BE[0:7]#</td><td>LOCK#</td><td>TDO</td></tr><tr><td>CLK</td><td>M66EN</td><td>TMS</td></tr><tr><td>DEVSEL#</td><td>PAR</td><td>TRDY#</td></tr><tr><td>FRAME#</td><td>PAR64</td><td>TRST#</td></tr><tr><td>GND</td><td>PERR#</td><td>V(I/O)</td></tr><tr><td>GNT#</td><td>REQ#</td><td>3.3 V</td></tr><tr><td>IDSEL</td><td>REQ64#</td><td>5 V</td></tr><tr><td>INTA#</td><td>RST#</td><td>+12 V</td></tr><tr><td>INTB#</td><td>SERR#</td><td>-12 V</td></tr><tr><td>INTC#</td><td>STOP#</td><td></td></tr></table>

# 4.2.1. General Peripheral Slots

Table 4.9 gives the peripheral slot pinout for the J1 and J2 connector.

PXI-specific signals are shown in bold.

RULE: Peripheral modules and backplane peripheral slots SHALL use the pinout in Table 4.9.

Table 4.9 Generic Peripheral Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>GND</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_LBL0</td><td>GND</td><td>PXI_LBL1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_LBL2</td><td>GND</td><td>PXI_LBL3</td><td>PXI_LBL4</td><td>PXI_LBL5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_STAR</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_LBL6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_LBL7</td><td>PXI_LBL8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_LBL9</td><td>GND</td><td>PXI_LBL10</td><td>PXI_LBL11</td><td>PXI_LBL12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BD_SEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td colspan="7">Z A B C D E F</td></tr></table>

# 4.2.2. System Slot

Table 4.10 gives the system slot pinout for the J1 and J2 connectors.

PXI-specific signals are shown in bold.

RULE: System modules and backplane system slots SHALL use the pinout in Table 4.10.

Table 4.10 System Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td><td rowspan="22">P2/J2</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>RSV</td><td>RSV</td><td>RSV</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>RSV</td><td>GND</td><td>RSV</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>DEG#</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]#</td><td>GND</td><td>C/BE[6]#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64#</td><td>ENUM#</td><td>3.3V</td><td>5V</td><td>GND</td><td rowspan="24">P1/J1</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>3.3V</td><td>CLK0</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td colspan="7">Z A B C D E F</td></tr></table>

# 4.2.3. Star Trigger Slot

Table 4.11 gives the peripheral slot pinout for the J1 and J2 connectors of the star trigger slot. PXI-specific signals are shown in bold.

RULE: Star trigger modules and backplane star trigger slots SHALL use the pinout in Table 4.11.

Table 4.11 Star Trigger Slot Pinout

<table><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>GND</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_STAR0</td><td>GND</td><td>PXI_STAR1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_STAR2</td><td>GND</td><td>PXI_STAR3</td><td>PXI_STAR4</td><td>PXI_STAR5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>RSV</td><td>PXI_CLK10_IN</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>RSV</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>RSV</td><td>PXI_STAR6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]\#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]\#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]\#</td><td>GND</td><td>C/BE[6]\#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>UNC</td><td>PXI_STAR7</td><td>PXI_STAR8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_STAR9</td><td>GND</td><td>PXI_STAR10</td><td>PXI_STAR11</td><td>PXI_STAR12</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>5V</td><td>REQ64\#</td><td>ENUM\#</td><td>3.3V</td><td>5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64\#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>3.3V</td><td>AD[4]</td><td>AD[3]</td><td>5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]\#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR\#</td><td>GND</td><td>3.3V</td><td>PAR</td><td>C/BE[1]\#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR\#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL\#</td><td>GND</td><td>V(I/O)</td><td>STOP\#</td><td>LOCK\#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>3.3V</td><td>FRAME\#</td><td>IRDY\#</td><td>BD_SEL\#</td><td>TRDY\#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]\#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]\#</td><td>IDSEL</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ\#</td><td>GND</td><td>3.3V</td><td>CLK</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>RST\#</td><td>GND</td><td>GNT\#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>HEALTHY\#</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA\#</td><td>INTB\#</td><td>INTC\#</td><td>5V</td><td>INTD\#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>5V</td><td>-12V</td><td>TRST\#</td><td>+12V</td><td>5V</td><td>GND</td></tr><tr><td>Pin</td><td colspan="7">Z A B C D E F</td></tr></table>

# 4.3. Chassis Power Supply Specifications

Because minimum power supply requirements are specified for PXI chassis, module designers can design modules knowing that they will work in any PXI system.

RULE: The power supply SHALL provide at least the required amounts of current given in Tables 4.12 and 4.13.

RECOMMENDATION: The power supply SHOULD provide at least the recommended amounts of current in Tables 4.12 and 4.13.

Table 4.12 5 V Backplane Power Requirements and Recommendations

<table><tr><td rowspan="2"></td><td colspan="2">5 V</td><td colspan="2">3.3 V</td><td>+12 V</td><td>-12 V</td></tr><tr><td>System Slot</td><td>Peripheral Slot</td><td>System Slot</td><td>Peripheral Slot</td><td>All Slots</td><td>All Slots</td></tr><tr><td>Required Current</td><td>4 A</td><td>2 A</td><td>6 A</td><td>0 A</td><td>0.5 A</td><td>0.1 A</td></tr><tr><td>Recommended Current</td><td>6 A</td><td>2 A</td><td>6 A</td><td>0 A</td><td>0.5 A</td><td>0.1 A</td></tr></table>

Table 4.13 3.3 V Backplane Power Requirements and Recommendations

<table><tr><td rowspan="2"></td><td colspan="2">5 V</td><td colspan="2">3.3 V</td><td>+12 V</td><td>-12 V</td></tr><tr><td>System Slot</td><td>Peripheral Slot</td><td>System Slot</td><td>Peripheral Slot</td><td>All Slots</td><td>All Slots</td></tr><tr><td>Required Current</td><td>0.5 A</td><td>0.5 A</td><td>6 A</td><td>3 A</td><td>0.5 A</td><td>0.1 A</td></tr><tr><td>Recommended Current</td><td>6 A</td><td>2 A</td><td>6 A</td><td>3 A</td><td>0.5 A</td><td>0.1 A</td></tr></table>

OBSERVATION: By supplying the recommended amounts of power, a PXI system can accommodate a much wider range of system slot designs.

OBSERVATION: Having the system supply 3.3 V conserves space and heat in the system slot module because 5 V does not have to be converted to 3.3 V on the module.

PERMISSION: Power supplies MAY provide additional current.

OBSERVATION: Each generation of processors requires more power than the previous generation. Providing copious amounts of power and cooling to the system slot of a chassis can extend the product applicability in the future.

RULE: All modules that draw more current than the amount required of the power supply SHALL document and make available to the customer their current requirements.

RECOMMENDATION: All modules SHOULD document and make available to the customer their current requirements, to allow users to maximize the capabilities of their power supply.

RULE: A peripheral or system slot module SHALL NOT draw more than 1 A of current from any power pin or return more than 1 A of current through any ground pin.

# 5. Software Frameworks and Requirements

This section discusses the software features associated with a PXI system. It gives an overview of the general motivating factors behind the PXI software specification, along with specific software frameworks.

# 5.1. Overview

Like other bus architectures before it, PXI defines standards that allow products from multiple vendors to work together at the bus level. The PXI specification goes on to mandate software requirements in addition to these bus level requirements. Other buses that have failed to designate software standards have seen the market fragment into competing standards from multiple vendors.

The PXI hardware specification is motivated by the benefits achieved by leveraging existing desktop hardware and software technology into the instrumentation world.

# 5.2. Motivation

Low-cost, rugged, reliable computer systems are needed in instrumentation and automation applications. The demands of reducing product cost and time to market, while increasing reliability, are severely straining custom-built systems. Hardware vendors have implemented many modular multivendor solutions to tackle these problems. However, the majority of costs associated with any system development are more likely related to the software development time, rather than the hardware development time.

PXI, unlike other systems, defines software frameworks as part of its specification. These software frameworks ensure that a user has a complete, multivendor system solution from the start.

The technical forces driving the PXI software frameworks are the same forces that are driving the hardware standard—the immense amounts of capital being applied toward the development of desktop PCs. By aligning with these software developments, PXI systems are poised to initiate a new generation of instrumentation. The frameworks that have been chosen for this specification reflect the dominance of these operating systems on current desktop PCs. As other operating systems become widely accepted and offer the same degree of software leverage as the current frameworks, they may be added to the supported PXI frameworks. Each framework is required to support the VISA software standard. VISA provides an industry-standard mechanism for locating, configuring, and controlling PXI modules.

The currently supported frameworks are the Windows 95, Windows 98, Windows NT, and Windows 2000 frameworks. Many organizations have aligned their entire offices around Microsoft operating systems, because of the reduction in training and support costs that come from a common, familiar computing environment across the office. These same benefits extend to the factory floor or test department.

Thousands of 32-bit applications are running today on the Windows 95, Windows 98, Windows NT, and Windows 2000 platforms, ranging from technical and engineering applications to complete manufacturing and financial solutions. All of these tools can be leveraged to improve instrumentation systems.

The ever-increasing interconnection between computers that design, produce, and test goods is driving the requirement that these systems easily interact with each other. The use of a common operating system across these computers means that a richer set of tools is available for exchanging and sharing data. All of the work being done to interconnect the desktop—ActiveX, COM, ODBC, and so on—is now available to interconnect machines on the factory floor to each other and to the rest of the corporation.

# 5.3. Framework Definition

The software frameworks define PXI system software requirements for both system controller modules and PXI peripheral modules. System controller modules and PXI peripheral modules have to meet certain requirements for operating system and tool support in order to be considered compliant with a given PXI software framework.

RULE: PXI system controller modules and PXI peripheral modules SHALL support at least one of the following frameworks (Windows 95 Windows 98, Windows NT, or Windows 2000).

# 5.4. Windows 95 System Framework

# 5.4.1. Introduction

This section defines the specific requirements for the Windows 95 (WIN95) system framework. It defines all of the unique components that must exist to support this framework. It also describes the optional recommended components.

# 5.4.2. Overview of the Framework

The WIN95 system framework defines a system based on the popular IBM PC personal computer architecture and its compatibles, and is based on the Windows 95 operating system from Microsoft.

# 5.4.3. Controller Requirements

This section defines the system requirements for the WIN95 framework for the system controller module.

RULE: If a system controller module claims conformance to the PXI WIN95 system framework, it SHALL run Windows 95.

RULE: The system controller module SHALL be based on the 80x86 architecture.

OBSERVATION: Processors other than the 80x86 that are supported under Windows 95 may be added in additional frameworks.

RULE: If a system controller module claims conformance to the PXI WIN95 system framework, it SHALL ship with a VISA implementation that supports the PXI bus.

# 5.4.4. PXI Peripheral Module Requirements

Hardware vendors for other industrial buses that do not have software standards often do not provide any software drivers for their modules. The customer is often given only a manual describing how to write software to control the module. The cost to the customer, in terms of engineering effort to support these modules, is huge. PXI removes this burden by requiring that manufacturers, rather than customers, develop this software.

RULE: If a peripheral module claims conformance to the PXI WIN95 system framework, it SHALL provide software for installing, configuring, and controlling this module under Windows 95.

RECOMMENDATION: PXI peripheral modules that are instrumentation class modules SHOULD provide a user-level interface that is supported under the development environments specified in Table 5.1.

Table 5.1 Development Environments Supported by PXI Modules under Windows 95

<table><tr><td>Product</td><td>Company</td><td>Revision</td></tr><tr><td>LabVIEW</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>LabWindows/CVI</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>Visual Basic</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Visual C/C++</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Turbo C/C++</td><td>Borland</td><td>5.0 or higher</td></tr></table>

OBSERVATION: Other system tools MAY be supported in addition to these tools.

# 5.5. Windows 98 System Framework

# 5.5.1. Introduction

This section defines the specific requirements for the Windows 98 (WIN98) system framework. It defines all of the unique components that must exist to support this framework. It also describes the optional recommended components.

# 5.5.2. Overview of the Framework

The WIN98 system framework defines a system based on the popular IBM PC personal computer architecture and its compatibles, and is based on the Windows 98 operating system from Microsoft.

# 5.5.3. Controller Requirements

This section defines the system requirements for the WIN98 framework for the system controller module.

RULE: If a system controller module claims conformance to the PXI WIN98 system framework, it SHALL run Windows 98.

RULE: The system controller module SHALL be based on the 80x86 architecture.

OBSERVATION: Processors other than the 80x86 that are supported under Windows 98 may be added in additional frameworks.

RULE: If a system controller module claims conformance to the PXI WIN98 system framework, it SHALL ship with a VISA implementation that supports the PXI bus.

# 5.5.4. PXI Peripheral Module Requirements

Hardware vendors for other industrial buses that do not have software standards often do not provide any software drivers for their modules. The customer is often given only a manual describing how to write software to control the module. The cost to the customer, in terms of engineering effort to support these modules, is huge. PXI removes this burden by requiring that manufacturers, rather than customers, develop this software.

RULE: If a peripheral module claims conformance to the PXI WIN98 system framework, it SHALL provide software for installing, configuring, and controlling this module under Windows 98.

RECOMMENDATION: PXI peripheral modules that are instrumentation class modules SHOULD provide a user-level interface that is supported under the development environments specified in Table 5.2.

Table 5.2 Development Environments Supported by PXI Modules under Windows 98

<table><tr><td>Product</td><td>Company</td><td>Revision</td></tr><tr><td>LabVIEW</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>LabWindows/CVI</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>Visual Basic</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Visual C/C++</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Turbo C/C++</td><td>Borland</td><td>5.0 or higher</td></tr></table>

OBSERVATION: Other system tools MAY be supported in addition to these tools.

# 5.6. Windows NT System Framework

# 5.6.1. Introduction

This section defines the specific requirements for the Windows NT (WINNT) system framework. It defines all of the unique components that must exist to support this framework. It also describes the optional recommended components.

# 5.6.2. Overview of the Framework

The WINNT system framework defines a system based on the popular IBM PC personal computer architecture and its compatibles, and is based on the Windows NT operating system from Microsoft.

# 5.6.3. Controller Requirements

This section defines the system requirements for the WINNT framework for the system controller module.

RULE: If a system controller module claims conformance to the PXI WINNT system framework, it SHALL run Windows NT version 4.0.

RULE: The system controller module SHALL be based on the 80x86 architecture.

OBSERVATION: Processors other than the 80x86 that are supported under Windows NT may be added in additional frameworks.

RULE: If a system controller module claims conformance to the PXI WINNT system framework, it SHALL ship with a VISA implementation that supports the PXI bus.

# 5.6.4. PXI Peripheral Module Requirements

Hardware vendors for other industrial buses that do not have software standards often do not provide any software drivers for their modules. The customer is often given only a manual describing how to write software to control the module. The cost to the customer, in terms of engineering effort to support these modules, is huge. PXI removes this burden by requiring that manufacturers, rather than customers, develop this software.

RULE: If a peripheral module claims conformance to the PXI WINNT system framework, it SHALL provide software for installing, configuring, and controlling this module under Windows NT.

RECOMMENDATION: PXI peripheral modules that are instrumentation class modules SHOULD provide a user-level interface that is supported under the development environments specified in Table 5.3

Table 5.3 Development Environments Supported by PXI Modules under Windows NT

<table><tr><td>Product</td><td>Company</td><td>Revision</td></tr><tr><td>LabVIEW</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>LabWindows/CVI</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>Visual Basic</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Visual C/C++</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Turbo C/C++</td><td>Borland</td><td>5.0 or higher</td></tr></table>

OBSERVATION: Other system tools MAY be supported in addition to these tools.

# 5.7. Windows 2000 System Framework

# 5.7.1. Introduction

This section defines the specific requirements for the Windows 2000 (WIN2000) system framework. It defines all of the unique components that must exist to support this framework. It also describes the optional recommended components.

# 5.7.2. Overview of the Framework

The WIN2000 system framework defines a system based on the popular IBM PC personal computer architecture and its compatibles, and is based on the Windows 2000 operating system from Microsoft.

# 5.7.3. Controller Requirements

This section defines the system requirements for the WIN2000 framework for the system controller module.

RULE: If a system controller module claims conformance to the PXI WIN98 system framework, it SHALL run Windows 2000.

RULE: The system controller module SHALL be based on the 80x86 architecture.

OBSERVATION: Processors other than the 80x86 that are supported under Windows 2000 may be added in additional frameworks.

RULE: If a system controller module claims conformance to the PXI WIN2000 system framework, it SHALL ship with a VISA implementation that supports the PXI bus.

# 5.7.4. PXI Peripheral Module Requirements

Hardware vendors for other industrial buses that do not have software standards often do not provide any software drivers for their modules. The customer is often given only a manual describing how to write software to control the module. The cost to the customer, in terms of engineering effort to support these modules, is huge. PXI removes this burden by requiring that manufacturers, rather than customers, develop this software.

RULE: If a peripheral module claims conformance to the PXI WIN2000 system framework, it SHALL provide software for installing, configuring, and controlling this module under Windows 2000.

RECOMMENDATION: PXI peripheral modules that are instrumentation class modules SHOULD provide a user-level interface that is supported under the development environments specified in Table 5.4.

Table 5.4 Development Environments Supported by PXI Modules under Windows 2000

<table><tr><td>Product</td><td>Company</td><td>Revision</td></tr><tr><td>LabVIEW</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>LabWindows/CVI</td><td>National Instruments</td><td>4.0 or higher</td></tr><tr><td>Visual Basic</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Visual C/C++</td><td>Microsoft</td><td>5.0 or higher</td></tr><tr><td>Turbo C/C++</td><td>Borland</td><td>5.0 or higher</td></tr></table>

OBSERVATION: Other system tools MAY be supported in addition to these tools.

# 5.8. Support for Existing Instrumentation Standards

The challenge for developing PXI instrumentation systems is to provide a platform that extends the capabilities of new test systems, while supporting existing instrumentation standards. The VXIplug&play System Alliance provides an industry-standard mechanism for communicating with GPIB, VXI, and serial instrumentation through a series of specifications. These specifications define communications standards (VISA), instrument programming interfaces (instrument drivers), and interactive user interfaces (soft front panels). These specifications also define frameworks for the various Windows operating systems.

RULE: A PXI module that controls a VISA supported interface SHALL provide the VISA software as a mechanism for communicating with that interface.

The use of the VISA standard in PXI preserves the user’s investment in existing instrumentation software. VISA provides the link from PXI to a VXI chassis and instruments and standalone GPIB and serial instruments.

RECOMMENDATION: Instrumentation class PXI peripheral modules SHOULD provide instrument drivers and soft front panels that are consistent with the VXIplug&play instrument driver specifications (VPP-3.x and VPP-7).

The goal of supporting VXIplug&play instrument drivers and soft front panels is to provide a familiar development environment to test and measurement customers. Test and measurement customers have come to expect VXI and GPIB instruments to have soft front panels and instrument drivers. VXIplug&play support for native PXI instruments provides a seamless software path between VXI and PXI based systems.

RULE: All PXI system controller modules SHALL be supplied with VISA.

VISA will be used as the software interface for system configuration, slot enumeration, and access to instrumentation features including the trigger bus and the star trigger.

# 5.9. System Implementation Issues

# 5.9.1. System Configuration and Initialization Files

The PXI specification allows many variations of PXI chassis and system modules. To assist system integrators, the manufacturers of PXI chassis and system modules must document the capabilities of their products. The minimum documentation requirements are contained in .ini files, which consist of ASCII text. The .ini files can be read by the system integrator, and can also be used by configuration utilities and device drivers if needed.

The .ini files help the integrator determine if a peripheral module installed in a particular slot may enable circuitry that uses a local bus. For example, in a chassis, the rightmost peripheral slot can use its local bus right signals to

implement an external interface to another bus (such as SCXI). If a peripheral module that uses its local bus right for another purpose is installed in that slot, the local bus circuitry cannot be enabled.

The .ini files also help the integrator determine the physical location of peripheral modules. For example, in a system with four identical data acquisition modules installed, the device driver for the module identifies the modules as four logical entities. The user may need to know the physical slot location of logical module number 2. Utility software can use the .ini files to determine the slot location. The .ini files effectively provide a method of obtaining slot enumeration without requiring additional pins on each slot.

The documentation for a chassis is contained in a chassis.ini file. The information in this file is combined with information about the system module into a single system initialization file, pxisys.ini. The system module manufacturer will either provide a pxisys.ini file for the particular chassis model that contains the system module, or provide a utility that can read an arbitrary chassis.ini file and generate the corresponding pxisys.ini file.

Device drivers and other utility software will read the pxisys.ini (PXI System Initialization) file to determine information about the system. The device drivers should have no need to directly read the chassis.ini file.

OBSERVATION: Issues related to configuring systems consisting of multiple chassis are beyond the scope of this specification. However, the .ini files described in this section may be useful in addressing such issues.

# 5.9.2. General .ini File Format

The .ini files consist of lines of ASCII text. Each .ini file contains one or more sections, and each section contains one or more tag lines. Each tag line describes a specific property of the section.

A .ini file might begin with the following lines:

```ini
# This line is a comment
[Section1]
IsSpecialSection = No
[Section2]
IsSpecialSection = Yes
```

RULE: Each .ini file SHALL contain only ASCII text.

RULE: Each .ini file SHALL contain only the following types of lines: comment line, section header, and tag line.

RULE: A comment line SHALL begin with the ‘#’ character.

RULE: A section header line SHALL begin with the ‘[’ character and end with the ‘]’ character. Text between the two brackets SHALL identify the type of section.

RULE: A tag line SHALL consist of the following three fields: tag, ‘=’ character, and value. The three fields SHALL be each separated by a single space character.

# 5.9.3. PXI System Initialization (pxisys.ini) File

A pxisys.ini file describes the PXI system configuration. In this context, a system configuration is a particular system module model installed in a particular chassis model. The pxisys.ini file contains information that describes the physical location of installed peripheral modules. The file also describes the capabilities of the peripheral slots in the chassis.

RULE: A system module manufacturer SHALL either provide a pxisys.ini file for each supported system configuration or provide a utility that can generate the pxisys.ini file.

OBSERVATION: A utility to create a pxisys.ini file would read the .ini file for the chassis and the .ini file for the system module and generate a pxisys.ini file.

OBSERVATION: The pxisys.ini file is usually read only by PXI peripheral device drivers.

RULE: A pxisys.ini file SHALL have one section for each slot in the system. The section heading line for each section SHALL be ‘[Slotn]’, where n is a decimal integer such that 0 ≤ n ≤999.

RULE: Each physical slot SHALL be labeled so that the user can see the slot number, and this slot number SHALL be used in the heading line for the slot.

RULE: Each backplane PCI device SHALL be assigned a unique slot number to identify it in the .ini file.

RULE: Each section SHALL contain one of each tag line type described in Table 5.5.

OBSERVATION: A backplane PCI-PCI bridge module will have two Slot entries in the .ini file—one for the peripheral PCI module on the upstream bus, and one for the system PCI module on the downstream bus.

Table 5.5 Tag Line Descriptions

<table><tr><td>Tag</td><td>Valid Values</td><td>Description</td></tr><tr><td>IDSEL</td><td>n, where n is the number of the PCI address line that connects to the slot&#x27;s IDSEL pin.</td><td>This tag shows the backplane IDSEL connection to this slot.</td></tr><tr><td>SecondaryBusNumber</td><td>n, where n is a decimal integer such that 0 ≤ n ≤ 255</td><td>If this slot is a PCI-PCI bridge, this is the PCI bus number on the secondary interface of the bridge as defined by the Configuration Cycle section of the PCI specification. If this slot is not a bridge, set the field to 0.</td></tr><tr><td>ExternalBackplaneInterface</td><td>None (other)</td><td>If this slot routes to an external backplane interface, this tag specifies the name of that interface.</td></tr><tr><td>PCIBusNumber</td><td>n, where n is a decimal integer such that 0 ≤ n ≤ 255</td><td>The PCI bus number as defined by the Configuration Cycle section of the PCI spec. The PCIBusNumber and PCIDeviceNumber uniquely identify a module in a system.</td></tr><tr><td>PCIDeviceNumber</td><td>n, where n is a decimal integer such that 0 ≤ n ≤ 31</td><td>The PCI device number as defined by the Configuration Cycle section of the PCI specification. The PCIBusNumber and PCIDeviceNumber uniquely identify a module in a system.</td></tr></table>

RULE: The PCIBusNumber and SecondaryBusNumber fields SHALL contain the PCI bus number as defined by the Configuration Cycle section of the PCI specification when the only PCI-PCI bridges present are those on the controller and the chassis.

OBSERVATION: If modules with bridges are installed in the chassis, config space registers on the modules can be queried to determine the PCI bus number shifting caused by the additional bridges.

# 5.9.4. Chassis Initialization (chassis.ini) File

A chassis.ini file describes the functionality of a PXI chassis. A PXI chassis may include slots that accept peripheral modules, slots that accept system modules, and backplane PCI modules that behave as system modules or peripheral modules.

RULE: A chassis manufacturer SHALL provide a chassis.ini file for each chassis model produced.

RULE: A chassis.ini file SHALL have one section for each slot in the chassis. The section heading line for each section SHALL be ‘[Slotn]’, where n is a decimal integer such that 0 ≤ n ≤999.

RULE: Each physical slot SHALL be labeled so that the user can see the slot number, and this slot number SHALL be used in the heading line for the slot.

RULE: Each backplane PCI device SHALL be assigned a unique slot number to identify it in the .ini file.

RULE: Each section SHALL contain one IDSEL tag line, as described in Table 5.5.

RULE: A chassis.ini file SHALL also contain the tag lines shown in Table 5.6 in each section:

Table 5.6 Additional Tag Line Descriptions for chassis.ini

<table><tr><td>Tag</td><td>Valid Values</td><td>Description</td></tr><tr><td>SlotNumberOfOtherHalfOfBridge</td><td>Nonen, where n is a SlotNumber</td><td>If this slot is part of a PCI-PCI bridge, this tag field shows the SlotNumber of the other PCI module contained in this PCI-PCI bridge.</td></tr><tr><td>SystemSlotNumber</td><td>n, where n is the SlotNumber of the system slot.</td><td>This tag shows the SlotNumber of the system slot for this PCI bus segment.</td></tr></table>

# 5.9.5. Other Chassis Requirements

To assist configuration software in locating the slots, this specification places restrictions on the numbering of system slots.

RULE: For any two physical system slots in the same row, the system slot physically to the left SHALL have a lower slot number. Any system slot SHALL have a SlotNumber lower than all system slots in a rows physically below the slot.
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