# COM-HPC-ALT # Server Type COM-HPC Size E Module with ARM-based Ampere Altra Processor # Features ● Up to 128 Arm-based cores at 190W TDP ● Up to 768GB DDR4 with 6 individual memory channels ● EDK II, seamless support for popular OS, hypervisors, and software ● 64 PCIe Gen4 lanes (3 x16 available) ● CCIX capable, for heterogeneous applications ● Dedicated PCIe and IPMB for remote management ![Close-up of a computer motherboard with CPU socket and heatsink (no visible text or symbols)](.com-hpc-alt-datasheet-20230816/1161afc4d73544c16173e294262bcb9bae6385e8197e5086efa2a018f861454a.jpg) # Specifications # ● Core System # SoC Ampere Computing, Ampere® Altra® Series Processors • M128-26 128 cores, 2.6GHz, 190W TDP • M96-28 96 cores, 2.8GHz, 190W TDP • Q64-22 64 cores, 2.2GHz, 95W TDP • Q32-17 32 cores, 1.7GHz, 65W TDP Note: Additional SKUs are supported by project basis # Memory Six DIMM sockets with individual memory channels Up to 768GB (6x 128GB) DDR4 RDIMM memory, up to 3200MT/s # Embedded BIOS Open Source TianoCore EDK II # Cache 1 MB L2 cache per core, 32 MB System Level Cache # Expansion Busses 64 PCI Express Gen4 Lanes • 8 PCI Express Lanes 0-7 (J1): configurable to x8, x4, x2 • 8 PCI Express Lanes 8-15 (J1): configurable to x8, x4, x2 • 16 PCI Express Lanes 16-31 (J2): configurable to x16, x8, x4 • 16 PCI Express Lanes 32-47 (J2): configurable to x16, x8, x4 • 16 PCI Express Lanes 48-63 (J2): configurable to x16, x8, x4 CCIX for heterogeneous computing (by project basis) SMBus (system), 2x I2C (user), GP\_SPI # Module Management Controller (MMC) Supports IPMB for communication with carrier BMC for remote management usage. Monitors module voltage/current, manages power sequence, AT/ATX mode control, board information, watchdog timer, fan control. # Debug Headers • 40-pin multipurpose flat cable connector for use with DB40-HPC debug module providing BIOS POST code LED, MMC/EC access, SPI BIOS flashing, power testpoints, debug LEDs • JTAG connector for CPU diagnostics # ● Ethernet KR # MAC External LAN controller # Interface Up to 4x 10GBASE-KR or 10GbE SFI (TBC) # ● NBASE-T Ethernet # Intel MAC/PHY Intel® Ethernet Controller I210 # Interface 10/100/1000 Mbit/s Ethernet connection # ● Remote Management Dedicated Interfaces # PCIe\_BMC Dedicated PCIe for carrier BMC, mainly used for KVM (carrier BMC emulates graphics card) # IPMB Provided by MMC, dedicated connection between carrier BMC and module MMC # ● Multi I/O and Storage # USB 4x USB 3.0/2.0/1.0 (USB 0,1,2,3), by PCIe-to-USB host controller # Serial 2x UART ports with console redirection # GPIO 12x GPIO (GPI with interrupt, TBC) # ● TPM # Chipset Infineon (build option) # Type TPM 2.0 (SPI based) # ● Power # Standard Input ATX: 12V±5% / 5Vsb ±5%; or AT: 12V±5% # Management ACPI 5.0 compliant # Power States TBC # Specifications # Mechanical and Environmental # Form Factor PICMG COM-HPC: Rev 1.0 Server Type # Dimension Size E: 200 mm x 160 mm # Operating Temperature Standard: 0°C to 60°C (storage: -20°C to 80°C) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D (TBC) # HALT Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # ● Operating Systems # Standard Support Yocto Hardknott project based Linux 64-bit Ubuntu Server for ARM - 20.04.3 LTS 64-bit CentOS 8 Stream # ● Ordering Information Modules
Module NumberDescription/Configuration
COM-HPC-ALT-M128-26Server Type COM-HPC Size E module with Ampere Altra M128-26, 128C
COM-HPC-ALT-M96-28Server Type COM-HPC Size E module with Ampere Altra M96-28, 96C
COM-HPC-ALT-Q64-22Server Type COM-HPC Size E module with Ampere Altra Q64-22, 64C
COM-HPC-ALT-Q32-17Server Type COM-HPC Size E module with Ampere Altra Q32-17, 32C
\* For processor SKUs not listed, please contact your ADLINK representative for availability. Functional Diagram ![The diagram illustrates the connectivity of an **Ampere Altra®** processor (labeled with **32 / 64 / 80 / 128 cores**) to various interfaces and components.\n\n**Central Component:**\n* A large red block labeled **Ampere Altra®** with **32 / 64 / 80 / 128 cores**.\n\n**Left Side (Header J1):**\n* **PCIe Lanes 0-3, 4-7, 8-11, 12-15:** Each connects to the central chip via lines labeled **1 x4, 2 x2**. These lines route towards **optional x8** brackets above the chip before entering it.\n* **PCIe_BMC x1:** Connects directly to the chip.\n* **ETH_KR 0-3:** Connects to a blue block labeled **4x 10G controller**. The controller connects to the chip and has an arrow labeled **sideband** pointing to the chip.\n* **ETH_KR 4-7:** Listed in J1 but not explicitly connected with a line.\n* **4x USB 3.x/2.0 0-3** and **4x USB 2.0 4-7:** Connect to a blue block labeled **uPD 720201**, which connects to the chip.\n* **SATA Port 0-1:** Connects directly to the chip.\n* **NBASE-T 0:** Connects to a blue block labeled **Intel i210**, which connects to the chip.\n* **BOOT_SPI:** Connects to a blue block labeled **BIOS**, which connects to the chip.\n* **GPP_SPI:** Connects to a blue block labeled **TPM**, which connects to the chip.\n* **SMBus:** Connects directly to the chip.\n* **I2C 0 (w/ ALERT#)** and **I2C 1:** Connect to a blue block labeled **EEPROM**, which connects to the chip.\n* **UART 0**, **UART 1**, **GPIO x 12:** Connect directly to the chip.\n* **USB_PD_I2C** and **IPMB:** Connect to a blue block labeled **MMC**.\n* **eSPI:** Connects to a block labeled **voltage, current, and temperature sensor**.\n\n**Right Side (Header J2):**\n* **PCIe Lane 16-31:** Connects to the chip via a line labeled **1 x16, 2 x8, 4 x4**.\n* **PCIe Lane 32-47:** Connects to the chip via a line labeled **1 x16, 2 x8, 4 x4**.\n* **PCIe Lane 48-63:** Connects to the chip via a line labeled **1 x16, 2 x8, 4 x4**.\n* **ETH_Sidebands**, **ETH_I²C**, **ETH_PHY_RST#**, **ETH_INT#**: Receive a connection via an arrow labeled **sideband** originating from the chip.\n\n**Bottom Section:**\n* **MMC:** Connected to **USB_PD_I²C** and **IPMB** from J1.\n* **DIMM:** Six blue blocks labeled **DIMM 3200 MT/s** are arranged in two rows and connect directly to the central chip via vertical lines.](.com-hpc-alt-datasheet-20230816/fd98dca6333d9de97ef06aa58e5ab075a9d3822b2ce8a9b55c3936434d440ca7.jpg) [🔗 Link to the original document](.com-hpc-alt-datasheet-20230816/com-hpc-alt-datasheet-20230816.pdf)