# COM-HPC-EP # Server Type COM-HPC Size E Module with AMD EPYC™ Embedded 3000 Series Processor # Features ● AMD EPYC™ Embedded 3000 Series SoC, up to 16C/32T at 100W TDP ● Up to 384GB DDR4 in 6 DIMM sockets ● Up to 56 PCIe lanes, supports three PCIe x16 ● Dedicated PCIe and IPMB for remote management ![The image displays a blue, tilted oval shape containing the word 'Preliminary' written in white, sans-serif text. A white curved swoosh is visible beneath the text within the blue shape.](.com-hpc-ep-datasheet-preliminary-20210223/4af53410ac50b3a1464f3580751b652a088de63772eac603ef1c096ee0643a44.jpg) ![Top-down view of a COM-iPC processor module with visible circuitry and gold contacts (no text or symbols on the chip itself)](.com-hpc-ep-datasheet-preliminary-20210223/145d5d4f98ec3fa4ea0a4db08151a4f190a5bcc31524f44f8775b730601ddaf9.jpg) # Specifications # ● Core System # AMD EPYC™ Embedded 3000 Series Processors SoC • EPYC™ 3451, 2.14/3.00GHz, 32MB L3, 100W (16C) • EPYC™ 3351, 1.90/3.00GHz, 32MB L3, 80W (12C) Note: Additional SKUs supported by project basis # Memory 2666 MHz DDR4 memory up to 384GB in 6 DIMM sockets • Supports RDIMM, UDIMM, LRDIMM # Embedded BIOS AMI UEFI with CMOS backup in 32MB SPI BIOS # Cache 32MB L3 for 3451, 3351 # Expansion Busses Up to 56 PCI Express Gen3 lanes • 16 PCI Express Lanes 0-15 (J1): configurable to x16, x8, x4, x2 • 16 PCI Express Lanes 16-31 (J2): configurable to x16, x8, x4 • 16 PCI Express Lanes 32-47 (J2): configurable to x16, x8, x4 • 8 PCI Express Lanes 48-55 (J2): configurable to x8, x4 LPC bus, SMBus (system), 2x I2C (user) # SEMA Board Controller Supports: Voltage/current monitoring, power sequence debug support, AT/ ATX mode control, logistics and forensic information, general purpose I2C, watchdog timer, fan control # Module Management Controller Supports: IPMB, used for communicating with carrier BMC Note: Module Management Controller (MMC ) supported by build option # Debug Headers 30-pin multipurpose flat cable connector for use with DB-30 x86 debug module providing BIOS POST code LED, EC access, SPI BIOS flashing, power testpoints, debug LEDs # ● Ethernet KR # MAC External LAN controller # Interface Up to 4x 10GBASE-KR (TBC) # ● NBASE-T Ethernet # Intel® MAC/PHY Intel® Ethernet Connection i210 # Interface 10/100/1000 Mbit/s Ethernet connection # ● Remote Management Dedicated Interface PCIe\_BMC Dedicated PCIe for carrier BMC, mainly used for KVM (carrier BMC emulates graphics card) # IPMB Offered by MMC, dedicated connection between carrier BMC and module MMC # ● Multi I/O and Storage # USB 4x USB 3.0/2.0/1.1 (USB 0,1,2,3) # SATA Not supported # Serial 2x UART ports with console redirection # GPIO 12x GPIO from EC (SEMA board controller), GPI with interrupt (TBC) # Specifications # ● TPM # Chipset Infineon # Type TPM 2.0 (LPC based) # ● Power # Standard Input ATX: 12V±5% / 5Vsb ±5%; or AT: 12V±5% # Management ACPI 5.0 compliant # Power States C1-C6, S0, S3, S4, S5 , S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5) # ECO mode Supports deep S5 mode for power saving (TBC) # ● Mechanical and Environmental # Form Factor PICMG COM-HPC Rev 1.0, Server Type # Dimension Size E: 200 mm x 160 mm # Operating Temperature Standard: 0°C to 60°C (Storage: -20°C to 80°C) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # HALT Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # ● Operating Systems # Standard Support Windows 10 64-bit, Windows Server 2016 64-bit, Yocto project based Linux 64-bit, Ubuntu 64-bit (TBC) Functional Diagram ![The diagram illustrates the connectivity of an **AMD EPYC™ Embedded 3000 Series** processor to various peripherals and interfaces, divided into a left block (J1) and a right block (J2).\n\n**Central Processor & Memory:**\n* The central block is labeled **AMD EPYC™ Embedded 3000 Series**.\n* Connected to the bottom of the processor are six **DIMM** blocks arranged in two rows.\n\n**Left Side (J1) Connections:**\n* **GROUP 0 Low** brackets **PCIe Lane 0-3** and **PCIe Lane 4-7**.\n * **PCIe Lane 0-3** connects via **1 x4, 2 x2** to **0-3 DIE-0**.\n * **PCIe Lane 4-7** connects via **1 x4, 2 x2** to **8-11 DIE-0**.\n* **GROUP 0 High** brackets **PCIe Lane 8-11** and **PCIe Lane 12-15**.\n * **PCIe Lane 8-11** connects via **1 x2, 1 x4** to **4-7 DIE-1**.\n * **PCIe Lane 12-15** connects via **1 x2, 1 x4** to **12-15 DIE-0**.\n* **PCIe_BMC x1** connects to **26 DIE-0**.\n* **ETH_KR 0-3** and **ETH_KR 4-7** connect to a block labeled **LAN Controller Max. 4x 10G**, which connects to **DIE-0 28-31**.\n* **NBASE-T 0** connects to a small block labeled **LAN**, which connects to **DIE-0 24**.\n* **USB 2.0 Lane 0-3** and **USB 2.0 Lane 4-7** connect via a line labeled **One SSTX/RX pair per Lane**.\n* **USB 3.x Lane 0-3** connects via a line labeled **One SSTX/RX pair per Lane**.\n* **USB_PD_I2C/ALERT#** connects directly to the processor.\n* **SATA Port 0-1** connects directly to the processor.\n* **BOOT_SPI** connects to a block labeled **BIOS**.\n* **GPP_SPI** connects to a block labeled **TPM**.\n* **SMBus**, **I2C 0 (w/ ALERT#)**, **I2C 1**, **UART 0-1**, and **12x GPIO** connect directly to the processor (except GPIO).\n* **12x GPIO** connects to a block labeled **Board Controller**.\n* **IPMB** connects to **Board Controller**.\n* **eSPI/LPC** connects to the **LPC** pin on the processor.\n* **Board Controller** connects to labels **I2C** and **UART**, which are near a dashed box labeled **MMC**.\n\n**Right Side (J2) Connections:**\n* **GROUP 1** brackets **PCIe Lane 16-31**.\n* **GROUP 2** brackets **PCIe Lane 32-47**.\n* **GROUP 3** brackets **PCIe Lane 48-55** and **PCIe Lane 56-63**.\n* **PCIe Lane 16-31** connects via **1 x16, 2 x8, 4 x4** from **0-15 DIE-1**.\n* **PCIe Lane 32-47** connects via **1 x16, 2 x8, 4 x4** from **16-31 DIE-1**.\n* **PCIe Lane 48-55** connects via **1 x8, 2 x4** from **16-23 DIE-0**.\n* **PCIe Lane 56-63** connects directly.\n* **ETH_Sidebands** connects via a line labeled **From LAN controller**.\n* **Rapid_Shutdown** connects directly to the processor.\n\n**Internal Processor Labels:**\n* Top edge labels include **0-3 DIE-0**, **4-7 DIE-1**, **8-11 DIE-0**, **12-15 DIE-0**, **16-31 DIE-1**, and **0-15 DIE-1**.\n* Brackets below these labels indicate configurations: **can be x8**, **can be x16**, and **can be x8**.](.com-hpc-ep-datasheet-preliminary-20210223/4f7fe6b18e3bdfb6d532f51cc3db7d821de39dee94a5b0d3cb943595254ac72f.jpg) # Ordering Information COM-HPC-EP-3451 Server Type COM-HPC Size E module with AMD EPYC™ Embedded 3451, 16C COM-HPC-EP-3351 Server Type COM-HPC Size E module with AMD EPYC™ Embedded 3351, 12C # Accessories # Active Heatsink THSF-EP-BT High profile heatsink with fan for COM-HPC-EP with threaded standoffs for top mounting # Starter Kit Server Type COM-HPC Starter Kit Starter kit for Server Type COM-HPC [🔗 Link to the original document](.com-hpc-ep-datasheet-preliminary-20210223/com-hpc-ep-datasheet-preliminary-20210223.pdf)