# COM-HPC-sIDH/R

Server Type COM-HPC Size D Module based on New Gen Intel® Xeon® D SoC

![Close-up of a computer motherboard with visible CPU socket and surrounding circuitry (no text or symbols)](.com-hpc-sidh-r-datasheet-240816/6d023489639917134d1ba0cc391a5d76a82710acb36534ddb69a9d8709fd2e35.jpg)

# Features

� Up to 20 cores, AVX-512 VNNI
� Up to 256GB DDR4 RDIMM at max. 3200MT/s
� 32 PCIe Gen4 lanes, 16 PCIe Gen3 lanes
� Up to 8x 10G-KR
� Dedicated PCIe and IPMB for remote management
� Extreme Rugged operating temperature range (optional, selected SKU)

Specifications

<table><tr><td rowspan="14">Core System</td><td rowspan="10">SoC</td><td colspan="4">New Gen Intel® Xeon® D-2700 processor (formerly &quot;Ice Lake-D HCC&quot;)</td></tr><tr><td>Xeon® D-2896TER</td><td>2.0/3.2GHz</td><td>30MB</td><td>110W (10C, eTEMP)</td></tr><tr><td>Xeon® D-2899NT</td><td>2.2/3.1GHz</td><td>30MB</td><td>135W (22C)</td></tr><tr><td>Xeon® D-2796TE</td><td>2.0/3.1GHz</td><td>30MB</td><td>118W (20C, eTEMP)</td></tr><tr><td>Xeon® D-2775TE</td><td>2.0/3.1GHz</td><td>25MB</td><td>100W (16C, eTEMP)</td></tr><tr><td>Xeon® D-2752TER</td><td>1.8/2.8GHz</td><td>20MB</td><td>77W (12C, eTEMP)</td></tr><tr><td>Xeon® D-2733NT</td><td>2.1/3.2GHz</td><td>15MB</td><td>80W (8C, QAT)</td></tr><tr><td>Xeon® D-2712T</td><td>1.9/3.0GHz</td><td>15MB</td><td>65W (4C)</td></tr><tr><td colspan="4">Note: Additional non-IOTG SKUs are supported by project basis.</td></tr><tr><td colspan="4">Supports: Intel® VT (including VT-x, VT-d, VT-x with extended page tables),Intel® HT Technology, Intel® SSE4.2, Intel® 64 Architecture, Intel® TurboBoost Technology 2.0, Intel® AVX512-VNNI, Intel® TSX-NI, Intel® PlatformProtection Technology with Intel® TXT, Execute Disable Bit, Intel® DataProtection Technology with Intel® Secure Key, Intel® AES-NINote: Availability of features may vary between processor SKUs.</td></tr><tr><td>Memory</td><td colspan="4">Four DIMM socketsUp to 256GB (4x 64GB) DDR4 RDIMM memory, up to 3200MT/sUp to 512GB (4x 128GB) DDR4 LRDIMM memory (TBC)</td></tr><tr><td>Embedded BIOS</td><td colspan="4">AMI UEFI with CMOS backup in 32MB SPI BIOS</td></tr><tr><td>Cache</td><td colspan="4">Xeon® D-2896TER/D-2899NT/D-2796TE: 30MBXeon® D-2775TE: 25MBXeon® D-2752TER: 20MBXeon® D-2733NT / D-2712T: 15MB</td></tr><tr><td>Expansion Busses</td><td colspan="4">48 PCIe lanes8 PCIe lanes 0-7 (J1): configurable to x8, x4, x28 PCIe lanes 8-15 (J1): configurable to x8, x4, x216 PCIe lanes 16-31 (J2): configurable to x16, x8, x416 PCIe lanes 32-47 (J2): configurable to x16, x8, x4Note: PCIe lanes 0-15, USB 3.0, SATA, NBASE-T and PCIe_BMC source from HSIO.The available total raw bandwidth is equivalent to PCIe x16 Gen3SMBus (system), 2x  $I^{2}C$  (user)</td></tr></table>

Note: “build option” indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.

Specifications

<table><tr><td rowspan="3">Core System</td><td>SEMA Board Controller</td><td>Supports: Voltage/current monitoring, power sequence debug support, AT mode control, logistics and forensic information, genral purpose  $I^{2}C$ , UART, GPIO, watchdog timer, fan control</td></tr><tr><td>Module Management Controller</td><td>Supports: IPMB (in conjunction with carrier BMC for remote management applications) by build option</td></tr><tr><td>Debug Headers</td><td>40-pin multipurpose flat cable connector for use with DB40-HPC debug module providing BIOS POST code LED, MMC/EC access, SPI BIOS flashing, power testpoints, debug LEDs</td></tr><tr><td rowspan="2">Ethernet KR</td><td>MAC</td><td>Intel® Ethernet Controller integrated in SoC</td></tr><tr><td>Interface</td><td>Up to 8x 10GBASE-KR (dependent on SoC SKU)PHY on carrier is required for optical fiber, copper applications8x 10G configurable to multiple 25G, 40G, or higher (dependent on FW support, TBC)</td></tr><tr><td rowspan="2">NBASE-T Ethernet</td><td>Intel® MAC/PHY</td><td>Intel® Ethernet Connection I225 Series(I225-IT supports TSN by build option, TBC)</td></tr><tr><td>Interface</td><td>2.5GbE and 1000/100/10 Mbit/s Ethernet connection</td></tr><tr><td rowspan="2">Remote Management Dedicated Interface</td><td>PCIe_BMC</td><td>Dedicated PCIe for carrier BMC, mainly used for KVM(carrier BMC emulates graphics card)</td></tr><tr><td>IPMB</td><td>Offered by MMC, dedicated connection between carrier BMC and module MMC, build option</td></tr><tr><td rowspan="5">Multi I/O and Storage</td><td>USB</td><td>4x USB 3.0/2.0/1.1 (USB 0,1,2,3)</td></tr><tr><td>SATA</td><td>2x SATA (SATA 0, 1), build option in place of PCIe_BMC (TBC)</td></tr><tr><td>Serial</td><td>2x UART ports with console redirection</td></tr><tr><td>GPIO</td><td>12x GPIO (GPI with interrupt, TBC)</td></tr><tr><td>On-board Storage</td><td>eMMC 5.1 (build option, TBC)</td></tr><tr><td rowspan="2">TPM</td><td>Chipset</td><td>Infineon</td></tr><tr><td>Type</td><td>TPM 2.0 (SPI based)</td></tr><tr><td rowspan="3">Power</td><td>Standard Input</td><td>AT: 12V±5%</td></tr><tr><td>Management</td><td>ACPI 5.0 compliant</td></tr><tr><td>Power States</td><td>TBC</td></tr><tr><td rowspan="6">Mechanical and Environmental</td><td>Form Factor</td><td>PICMG COM-HPC: Rev 1.0 Server Type</td></tr><tr><td>Dimension</td><td>Size D: 160 mm x 160 mm</td></tr><tr><td>Operating Temperature</td><td>Standard: 0°C to 60°C (storage: -20°C to 80°C)Extreme Rugged: -40°C to 85°C (storage: -40°C to 85°C, build option, selected SKUs, TBC)</td></tr><tr><td>Humidity</td><td>5-90% RH operating, non-condensing5-95% RH storage (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D (TBC)</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr><tr><td>Operating Systems</td><td>Standard Support</td><td>Windows 10 IoT Enterprise LTSC, Windows Server 20H1Yocto project based Linux 64-bit, VxWorks (TBC)</td></tr></table>

Note: “build option” indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.

# Ordering Information

Modules

<table><tr><td>COM-HPC-sIDH-D-2896TER</td><td>Server Type COM-HPC Size D module with Intel® Xeon® D-2896TER</td></tr><tr><td>COM-HPC-sIDH-D-2796TE</td><td>Server Type COM-HPC Size D module with Intel® Xeon® D-2796TE</td></tr><tr><td>COM-HPC-sIDH-D-2775TE</td><td>Server Type COM-HPC Size D module with Intel® Xeon® D-2775TE</td></tr><tr><td>COM-HPC-sIDH-D-2752TER</td><td>Server Type COM-HPC Size D module with Intel® Xeon® D-2752TER</td></tr></table>

\*For processor SKUs not listed, please contact your ADLINK representative for availability.

Accessories

<table><tr><td colspan="2">Active Heatsinks</td></tr><tr><td>THSF-sIDHTL-B</td><td>High profile heatsink with Fan for COM-HPC-sIDH with threaded standoffs for bottom mounting</td></tr></table>

# Starter Kit

COM-HPC Server Starter Kit Starter kit for COM-HPC Server

Functional Diagram
![The diagram illustrates the connectivity of an **Intel® Xeon® D** processor (central reddish block) to various interfaces and peripheral blocks.\n\n**Left Side (J1 Interface):**\nA vertical grey block labeled **J1** lists connections:\n*   **PCIe Lane 0-3**, **PCIe Lane 4-7**, **PCIe Lane 8-11**, and **PCIe Lane 12-15** connect to the top-left of the Intel chip. Each connection is labeled '1 x4, 2 x2'.\n*   **PCIe_BMC x1**, **ETH_KR 0-3**, and **ETH_KR 4-7** connect directly to the left edge of the Intel chip. Text nearby reads '1x SSTX/SSRX pair per port'.\n*   **NBASE-T 0** connects to a small blue block labeled **LAN I225** (accompanied by text 'Max. 2.5G').\n*   **USB 2.0 Lane 0-3** and **USB 3.x Lane 0-3** connect to the left edge. **USB 2.0 Lane 4-7** is struck through with a horizontal line.\n*   **USB_PD_I2C/ALERT#** connects to the left edge.\n*   **SATA Port 1** and **SATA Port 0** connect to the left edge.\n*   **BOOT_SPI** connects to a block labeled **BIOS**.\n*   **GPP_SPI** connects to a block labeled **TPM**.\n*   **SMBus** connects to a block labeled **EEPROM (FRU)** and continues to the Intel chip labeled **SMB**.\n*   **I2C 0 (w/ ALERT#)** and **I2C 1** connect to a block labeled **SEMA Board Controller**.\n*   **UART 0-1** connects to the Intel chip label **HSUART**.\n*   **12x GPIO** connects to the **SEMA Board Controller**.\n*   **IPMB** connects to the **SEMA Board Controller** and a block labeled **MMC**.\n*   **eSPI** (bottom left) connects to the **SEMA Board Controller** and the Intel chip label **eSPI**.\n\n**Right Side (J2 Interface & Internal Peripherals):**\n*   A vertical grey block labeled **J2** lists:\n    *   **PCIe Lane 16-31** and **PCIe Lane 32-47** connect to the top-right of the Intel chip. Both are labeled '1 x16, 2 x8, 4 x4' and accompanied by 'Gen4' text.\n    *   **PCIe Lane 48-63** is listed but shows no connection line to the central block.\n    *   **ETH_Sidebands** connects to the right edge of the Intel chip.\n*   **eMMC 5.1 (TBC)** connects to the right edge.\n*   **XDP debug connector** connects to the right edge.\n*   Four **DIMM** blocks are connected at the bottom:\n    *   Two connect to **iMC 0** (labeled **Ch0** and **Ch1**).\n    *   Two connect to **iMC 1** (labeled **Ch3** and **Ch4**).](.com-hpc-sidh-r-datasheet-240816/1ed12efe362d4712ba6e07636be438c450f105c43185c237edfed60ec5b361d0.jpg)
[🔗 Link to the original document](.com-hpc-sidh-r-datasheet-240816/com-hpc-sidh-r-datasheet-240816.pdf)