3U VPXGPGPU Blade with NVIDIA A4500

VPX3-MXM/A4500

Datasheet

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![Green printed circuit board with various electronic components and connectors (no visible text or symbols)](.datasheet-vpx3-mxm-a4500-20260106/c1156dfdcdedf8f8daae760341fa4c4235db76da523495754eff64a8158e76ac.jpg)

# Features

• NVIDIA® A4500 embedded graphics based on Ampere architecture
• 5888 CUDA cores, 17.66 TFLOPS peak FP32 performance
• 16GB GDDR6 memory, 256-bit, Bandwidth: 512 GB/s
• Four DisplayPort 1.4
• VITA 46/48/65 compliant for quick deployment
• SOSA-aligned

Specifications

<table><tr><td rowspan="2">Graphic Core</td><td>GPU</td><td>NVIDIA RTXA4500 GA104-955 GPU</td></tr><tr><td>Memory</td><td>16GB GDDR6 memory, 256-bit, Bandwidth: 512 GB/s</td></tr><tr><td rowspan="5">GPGPU Computing</td><td>CUDA Cores</td><td>5888 CUDA cores, 17.66 TFLOPS peak FP32 performance</td></tr><tr><td>Tensor Cores</td><td>184 Tensor Cores</td></tr><tr><td>RT Cores</td><td>46 RT Cores</td></tr><tr><td>Compute API</td><td>CUDA Compute 8.0 and above, OpenCL1.2</td></tr><tr><td>Graphics API</td><td> $DirectX^®$  12, OpenGL 4.6</td></tr><tr><td rowspan="4">Connectivity</td><td>Video Output</td><td>Four DisplayPort 1.4 outputs to P2</td></tr><tr><td>PCI Express</td><td>PCIe x8 Gen3 to P1 (PCIe x16 Gen3 configurable)</td></tr><tr><td>VITA Standards</td><td>VITA 46/48/65 compliant</td></tr><tr><td>OpenVPXProfile</td><td>Support SOSA slot profile (PCIe x 8): SLT3-PAY-2F2U-14.2.3</td></tr><tr><td>Power Requirement</td><td>Power Input</td><td>12V (VS1/VS2)3.3V_AUX only</td></tr><tr><td rowspan="2">Operating System</td><td>Windows</td><td>Windows 10 64-bit</td></tr><tr><td>Linux</td><td>Support by request</td></tr><tr><td rowspan="2">Miscellaneous</td><td>LED</td><td>Status LED</td></tr><tr><td>Reset Button</td><td>Board reset button on front panel</td></tr></table>

Specifications

<table><tr><td rowspan="4">Mechanical</td><td>Form Factor</td><td>3U VPX 0.85&quot; with conduction cooling; secondary side retainer</td></tr><tr><td>Dimensions</td><td>100mm x 160mm</td></tr><tr><td>MXM Support</td><td>MXM 4.1 Type B+ (110mm)</td></tr><tr><td>Thermal Dissipation</td><td>Conduction-cooling by wedge lock</td></tr><tr><td rowspan="7">Environmental</td><td>Operating Temp.</td><td>-40°C to +85°C at wedge locks, GPU TGP at 80W (VITA47.0, ECC4-CC4)</td></tr><tr><td>Storage Temp.</td><td>-55°C to +105°C</td></tr><tr><td>Vibration</td><td>Random: 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)Sinusoidal: 5g, 20Hz to 2000Hz</td></tr><tr><td>Shock</td><td>40g, 11 ms (VITA47.0, ECC4-OS2)</td></tr><tr><td>Relative Humidity</td><td>95% non-condensing</td></tr><tr><td>Altitude</td><td>60,000 feet. (operating)</td></tr><tr><td>EMC</td><td>CE (EN555032 / EN55035);FCC Part 15BClassA</td></tr></table>

Block Diagram

![The diagram illustrates a hardware architecture centered around a large green block labeled **NVIDIA**. Inside this block are a blue component labeled **GDDR6 16GB** and a vertical stack of four blue blocks labeled **VBIOS**, **5888 CUDA**, **17.66 TFLOPs**, and **Temperature Sensor**.\n\n**Connections:**\n\n*   **From NVIDIA:**\n    *   Four vertical arrows descend to a white block labeled **Configuration**.\n    *   A horizontal line labeled **Vol** connects to the left side of a blue block labeled **IPMC**.\n\n*   **From Configuration:**\n    *   Four vertical arrows labeled **DP-A**, **DP-B**, **DP-C**, and **DP-D** descend to the left section of an orange bar labeled **P2**.\n\n*   **PCIe Switch:**\n    *   A blue block labeled **PCIe Switch** sits below the NVIDIA block.\n    *   An upward arrow connects it to the **NVIDIA** block, labeled **x16** and **PCIe Gen3 1x16**.\n    *   A downward arrow connects it to the middle section of the orange bar labeled **P1**, labeled **1x8 (default)** and **PCIe Gen3 1x8 (default)**.\n\n*   **From IPMC:**\n    *   An upward arrow connects to a grey block labeled **SPI Flash**.\n    *   A rightward line labeled **Sys_Temp.** extends to the right.\n    *   Two downward arrows connect to the right section of the orange bar labeled **P0**. The left arrow is labeled **IPMB_1** and the right arrow is labeled **IPMB_0**.](.datasheet-vpx3-mxm-a4500-20260106/f57ea4b2aca7758278d1ecac690fd27d41fd734735cde3e7f0587f5a8e0fc6f6.jpg)

# Ordering Information

GPGPU Blades, SOSA-aligned payload: SLT3-PAY-2F2U-14.2.3

<table><tr><td>VPX3-MXM/A4500,DP,SOSA,non-COMM,ETT,CC</td><td>3U VPX GPGPU blade with MXM A4500 inside, 4x DP output, SOSA-aligned, conformal coating &amp; ETT, -40 to +85°C, conduction-cooled, supports non-common PCIe clock mode</td></tr><tr><td>VPX3-MXM/A4500,DP,SOSA,COMM,ETT,CC</td><td>3U VPX GPGPU blade with MXM A4500 inside, 4x DP output, SOSA-aligned, conformal coating &amp; ETT, -40 to +85°C, conduction-cooled, supports common PCIe clock mode</td></tr></table>

RTM for Test

<table><tr><td>VPX3-RMXM-DP</td><td>RTM for VPX3-RTX5000-STD-R1 DP output provides four DisplayPort outputs</td></tr></table>
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