6U VPX Dual Nodes Blade with Intel® Xeon® W-11865MRE

VPX6200

Datasheet

![Green printed circuit board with multiple microcontroller and heat sinks (no visible text or symbols)](.datasheet-vpx6200-20241018/d3c30e3fae8ac46f23ebe3872cef0e4b3f8157930664c8b0c30fa56d35566ee4.jpg)

![The image displays a logo featuring the text 'VPX' in a bold, blue, sans-serif typeface. To the upper right of the 'X' is a small 'TM' trademark symbol in grey. Thin, dark grey curved lines sweep behind the text from the bottom left to the top right, forming a partial arc or swoosh. The background is white.](.datasheet-vpx6200-20241018/f173d3e09cdc2d1bd0481997e31c4ca9283bd438322dc8e9a17350a1fd4c608f.jpg)

![The image displays a logo featuring the text 'VPX' followed by 'REDI'. The letters 'V' and 'P' are blue, while the 'X' is black. The word 'REDI' is in orange. A thin black curved line (or swoosh) arcs over the text 'VPX' and extends towards the 'REDI' portion. A small 'TM' trademark symbol is visible in black above the letter 'I'.](.datasheet-vpx6200-20241018/201f4b136dd20b92a1d1750dd2f638b01185cc1514b900d5079253a317550587.jpg)

![The image displays a logo featuring the word 'Open' in orange text followed immediately by 'VPX' in dark blue text. A dark blue curved line arcs around the right side of 'VPX,' and a small 'TM' symbol is visible in the upper right corner.](.datasheet-vpx6200-20241018/4eaf4f77f2f433c055f302238a133a453726601366cfb472eb2cc94ced2949d8.jpg)

![The image features a distressed, red stamp graphic containing the text 'CONDUCTION COOLED' in bold, capital letters arranged in two lines within a rough rectangular border.](.datasheet-vpx6200-20241018/ce675812715fee1b3a7b5a64fe1ef88e5b3b35507b620d5d74e1ba6ddd879284.jpg)

# Features

• Dual nodes, redundancy architecture
• Intel® Xeon® W-11865MRE processor (formerly Tiger Lake-H) per node
• Dual channel 32GB DDR4-3200 soldered with ECC per node
• M.2 2242 slot per node (upgradeable to 1TB by option)
• VITA 46/48/65 compliant for quick deployment
• Supports Windows 10 IoT Enterprise LTSC 21H2 and Linux (kernel 5.13 and higher)

Specifications

<table><tr><td rowspan="8">Processor &amp; System</td><td>Architecture</td><td>Dual nodes, redundancy architecture</td></tr><tr><td>CPU</td><td>Intel® Xeon® W-11865MRE per node (formerly Tiger Lake-H) TDP 45W</td></tr><tr><td>Chipset</td><td>Intel® RM590E chipset per node</td></tr><tr><td>Memory</td><td>Dual channel 32GB DDR4-3200 soldered with ECC per node</td></tr><tr><td>BIOS</td><td>AMI® UEFI BIOS, Dual BIOS per node32MB SPI flash memory per node</td></tr><tr><td>VITA Standards</td><td>VITA 46/48/65 compliant</td></tr><tr><td>Module Profile</td><td>MOD6-PAY-4F2T-12.2.2</td></tr><tr><td>Slot Profile</td><td>SLT6-PAY-4F2T-10.2.2</td></tr><tr><td rowspan="3">Connectivity</td><td>Data Plane</td><td>2x 10GBase-KX4 to P1 per node</td></tr><tr><td>Control Plane</td><td>1x 1000Base-T to P4 per node</td></tr><tr><td>User Defined</td><td>1x 1000Base-KX to P4 per node1x 1000Base-T + 1x 1000Base-BX (BOM option: 1000Base-KX) to P5 for node A1x 1000Base-T + 1x 1000Base-BX (BOM option: 1000Base-KX) to P6 for node B3x PCIe Gen3 x8 to P2, P3, P4, P51x PCIe Gen3 x2 to P3 for node A1x PCIe Gen3 x2 to P4 for node B</td></tr></table>

Specifications

<table><tr><td rowspan="4">Connectivity</td><td>Video</td><td>1x HDMI 1.4 to P5 for node A (HDMI is NOT hot-pluggable in BIOS mode)1x HDMI 1.4 to P6 for node B (HDMI is NOT hot-pluggable in BIOS mode)</td></tr><tr><td>USB</td><td>2x USB 3.2 Gen 1 to P3 for node A2x USB 3.2 Gen 1 to P4 for node B4x USB2.0 to P5 for node A4x USB2.0 to P6 for node BSupports USB 3.0 power (supply 0.9A) with overcurrent protectionSupports USB 2.0 power (supply 0.5A) with overcurrent protection</td></tr><tr><td>Serial Port</td><td>2x RS-232/422 to P5 for node A (COM1, COM2)2x RS-232/422 to P6 for node B (COM1, COM2)Max. data rate for RS-232/422 is 115200bpsRS-232/422 mode configuration via BIOS</td></tr><tr><td>GPIO</td><td>8x GPIO to P3 for node A8x GPIO to P4, P6 for node B3.3V singlingGPIO pins routed to RTM (3.3V with level trigger)</td></tr><tr><td rowspan="2">Storage</td><td>SATA</td><td>1x SATA 6Gb/s to P3 + 2x SATA 6Gb/s to P5 for node A1x SATA 6Gb/s to P4 + 2x SATA 6Gb/s to P6 for node B</td></tr><tr><td>M.2</td><td>1x M.2 M key 2242 slot per nodeSupports interface: PCIe3.0 x4 and SATA3.0Supports module height: S1, S2, D1, D2 (D2 is default)</td></tr><tr><td rowspan="2">Security</td><td>TPM</td><td>Discrete TPM 2.0 chipSupports Intel Secure Boot (UEFI)</td></tr><tr><td>BIOS</td><td>Dual BIOS support</td></tr><tr><td rowspan="2">Power Requirement</td><td>Power Input</td><td>12V (VS1/VS2)5V (VS3)3.3V_AUX only</td></tr><tr><td>Power Consumption</td><td>Max. 100W</td></tr><tr><td rowspan="2">Operating System</td><td>Windows</td><td>Windows 10 IoT Enterprise LTSC 21H2</td></tr><tr><td>Linux</td><td>Linux (kernel 5.13 and higher)</td></tr><tr><td rowspan="9">Miscellaneous</td><td>Watchdog Timer</td><td>System reset and NMI, with programmable interval, 0-6553 seconds via IPMC</td></tr><tr><td>Hardware Monitor</td><td>Monitors CPU temperature, system temperature, Vcore and DC voltages</td></tr><tr><td>IPMC</td><td>SmartFusion SoC provides IPMI software functionsFirmware updateable (via JTAG pin header of VPX6200-RL1)</td></tr><tr><td>Serial Over LAN</td><td>SOL port via IPMC (COM3) for node A</td></tr><tr><td>Management Port</td><td>Management port via UART (COM3) for node B</td></tr><tr><td>DB30 Port</td><td>2x DB30 ports in the front panel for each node in order to flash BIOS and EC even if the system is unbootable</td></tr><tr><td>Heater</td><td>Built-in heater enhances low operating temperature capability</td></tr><tr><td>LEDs</td><td>Status LED on front panel</td></tr><tr><td>Reset Button</td><td>Reset button on front panel</td></tr><tr><td rowspan="3">Mechanical</td><td>Form Factor</td><td>6U VPX, conduction-cooled construction, 0.85&quot; pitch (VITA 48.2)</td></tr><tr><td>Thermal Dissipation</td><td>Conduction-cooling by wedge lock</td></tr><tr><td>M.2 Storage Cover</td><td>Aluminum covers with heatsink design per node for M.2 storage installation</td></tr></table>

Specifications

<table><tr><td rowspan="8">Environmental</td><td>Operating Temp.</td><td>-40°C to +85°C at wedge locks (VITA47.0, ECC4-CC4)</td></tr><tr><td>Storage Temp</td><td>-55°C to +105°C</td></tr><tr><td>Vibration</td><td>Random: 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)Sinusoidal: 5g, 20Hz to 2000Hz</td></tr><tr><td>Shock</td><td>40g, 11 ms (VITA47.0, ECC4-OS2)</td></tr><tr><td>Relative Humidity</td><td>95% non-condensing</td></tr><tr><td>Altitude</td><td>40,000 ft. (operating)</td></tr><tr><td>MTBF</td><td>105,594 hours (without SSD)*according to MIL HDBK 217F Notice 2</td></tr><tr><td>EMC</td><td>CE (EN555032 / EN55035) ; FCC Part 15B Class A</td></tr></table>

Block Diagram
![This diagram illustrates a dual-node system architecture (NODE A and NODE B) interconnected by a PCIe switch and Ethernet controllers.\n\n**NODE A (Left Side):**\n*   **Tiger lake-H 25W~45W Intel Xeon W-11865MRE**: Connects to two **DDR4 3200 16GB max ECC** blocks, **PCIE SW PLX PEX8750** (via **PCIE x8**), **10Gbe X710-BM2** (via **2x 10Gbase-KX4/KR PCIE x8**), and **Tiger Lake PCH-H RM590E** (via **X8 DMI**). Outputs **DDI** to **PTN3360** to **TMDS** to **P5**.\n*   **Tiger Lake PCH-H RM590E**: Connects to **Gbe I350** (via **PCIE x4**), **EC IT5121** (via **SPI**), and **eSPI to LPC ECE1200** (via **eSPI**). Interfaces with external headers: **P5** (**USB2x4**, **SATA x2**), **M.2 SSD 2242** (**PCIE x4**), **P3** (**PCIE x2**, **SATA**), and **SPI** bus to **BIOS1**, **BIOS0**, **TPM**.\n*   **eSPI to LPC ECE1200**: Connects to **UARTA NCT5104D** (via **LPC**).\n*   **UARTA NCT5104D**: Connects to **ISL41334IRZ RS232/422** (via **COM1**) to **P5**, **IPMC** (via **COM3** to **SOL**), and **GPIO** to **Frent Side 80 Part LED**.\n*   **EC IT5121**: Connects to **P3** (via **GPIO x8**) and **DB30** (via **UART/SMBus/I2C**).\n\n**NODE B (Right Side):**\n*   **Tiger lake-H 25W~45W Intel Xeon W-11865MRE**: Connects to two **DDR4 3200 16GB max ECC** blocks, **PCIE SW PLX PEX8750** (via **PCIE x8**), **10Gbe X710-BM2** (via **2x 10Gbase-KX4/KR PCIE x8**), and **Tiger Lake PCH-H RM590E** (via **X8 DMI**). Outputs **DDI** to **PTN3360** to **TMDS** to **P6**.\n*   **Tiger Lake PCH-H RM590E**: Connects to **Gbe I350** (via **PCIE x4**), **EC IT5121** (via **SPI**), and **eSPI to LPC ECE1200** (via **eSPI**). Interfaces with external headers: **P6** (**USB2x4**, **SATA x2**), **M.2 SSD 2242** (**PCIE x4**), **P4** (**PCIE x2**, **SATA**), and **SPI** bus to **BIOS1**, **BIOS0**, **TPM**.\n*   **eSPI to LPC ECE1200**: Connects to **UARTC NCT5104D** (via **LPC**).\n*   **UARTC NCT5104D**: Connects to **ISL41334IRZ RS232/422** (via **COM1**) to **P6**, **IPMC** (via **COM3**), and **GPIO** to **Frent Side 80 Part LED**.\n*   **EC IT5121**: Connects to **P6** (via **GPIO x8**) and **DB30** (via **UART/SMBus/I2C**).\n\n**Center Interconnect:**\n*   **PCIE SW PLX PEX8750**: Connects to **Po** and **Switch_JT AG**. Bridges NODE A and NODE B CPUs (via **PCIE x8**). Connects to **P2, P3, P4, P5** and **P1**.\n*   **10Gbe X710-BM2** (two blocks): Connect to **PCIE SW PLX PEX8750** (via **PCIE x8**).\n*   **Gbe I350** (two blocks): Connect to respective PCHs (via **PCIE x4**) and to each other via **1000BaseT**, **1000BaseKX**, **P4**, **P5**, **P6**.\n*   **DB30** (two blocks): Connect **EC IT5121** units to **IPMC** (via **UART/SMBus/I2C**).\n*   **IPMC A2F200M3F**: Connects to **UARTA NCT5104D** (via **SOL**) and **UARTC NCT5104D** (via **UART_0**, **UART_1**, **IPMC_TTAG**, **IPMC_DEBUG**). Connects to **P5** and **P2**.](.datasheet-vpx6200-20241018/d31169cba8e1cc8c402d4950c084c013d32940c472103b844e02e5642292278f.jpg)

# Ordering Information

Processor Blades

<table><tr><td>VPX6200/W11865MRE/M32/STD</td><td>6U VPX dual nodes blade with Intel® Xeon® W-11865MRE, 32GB DDR4-3200 w/ECC per node, conformal coating, ETT(-40°C to +85°C), conduction-cooled</td></tr></table>

Rear Transition Modules

<table><tr><td>VPX6200-RL1</td><td>VPX6200 RTM L1 board, ETT(-40°C to +85°C), air-cooled</td></tr></table>

![Back view of a network equipment chassis showing internal components and ports (no readable text or symbols)](.datasheet-vpx6200-20241018/96fdca9b46bea33afd87104c680e7793c1f11abf0ae5875cbaa470d32193a76c.jpg)
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