# LEC-MTK-I1200

SMARC 2.1 Short Size Module with

MediaTek MediaTek MT8195 SoC

![Close-up of a blue printed circuit board with various electronic components and connectors (no readable text or symbols)](.lec-mtk-i1200-datasheet-250527/2d24e2a4136e7eb768ef8bef044823f15eb82fb3ded83e074f3ee07491d1af81.jpg)

# Features

• 8-core Arm Cortex -A78 x4 + Cortex-A55 x4
• 5 TOPS APU
• SMARC revision 2.1.1 compliant
• Up to 8GB LPDDR4X
• DSI up to 1080P
• HDMI up to 4K/60Hz

1x onboard UFS up to 256 GB
Dual GbE Ethernet ports
3x CSI interfaces
USB3/USB2 interfaces
10 year product availability

Specifications

<table><tr><td rowspan="4">Processor &amp; System</td><td>CPU</td><td>MT8195 Octa-core CPU: 4x A78 @ 2.2GHz + 4x A55 @ 2.0GHz</td></tr><tr><td>Memory</td><td>4 or 8 GB POP LPDDR4X</td></tr><tr><td>Cache</td><td>256KB L2 per CPU core (2MB unified L3)</td></tr><tr><td>Security</td><td>TPM 2.0 module</td></tr><tr><td rowspan="5">Video</td><td>GPU Core</td><td>Five-core Arm Mali-G57 GPU – Dual 4K @ 60 fps</td></tr><tr><td>GPU Feature Support</td><td>3D graphic accelerator capable of processing 17600M pixel/sec @ 880MHzSupport for OpenGL ES 3.2/2.0/1.1, Vulkan 1.1/1.0, OpenCL 2.2</td></tr><tr><td>HDMI/DP</td><td>HDMI 2.0b 4K @ 60Hz or DisplayPort</td></tr><tr><td>eDP</td><td>4 Lane eDP</td></tr><tr><td>DSI</td><td>2x 4 Lane DSI, maximum resolution 4K p60 with 24-bit RGB</td></tr></table>

Note: “Build option””indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.

Specifications

<table><tr><td>Camera</td><td>CSI</td><td>3x MIPI CS, 1x 2Lane, 2x 4 lane</td></tr><tr><td rowspan="3">System Storage</td><td>SDIO</td><td>1x SDIO (4-bit) compatible with SD/SDIO standard, up to version 3.0</td></tr><tr><td>UFS</td><td>32, 64, 128, or 256 GB (build option)</td></tr><tr><td></td><td>Compatible with UFS gear 2.1</td></tr><tr><td>Debug Header</td><td></td><td>30-pin multipurpose flat cable connector for use with optional DB-30 debug module. Provides JTAG, UART, boot select</td></tr><tr><td>Audio</td><td>Audio Codec</td><td>I2S audio codec located on the carrier</td></tr><tr><td rowspan="2">Dual Ethernet</td><td>Primary LAN</td><td>10/100/1000 Gbps Ethernet</td></tr><tr><td>Secondary LAN</td><td>10/100/1000 Gbps Ethernet</td></tr><tr><td rowspan="2">Wireless</td><td>Wi-Fi</td><td>IEEE 802.11 2X2 MU-MIMO ac/a/b/g/n</td></tr><tr><td>Bluetooth</td><td>Bluetooth 5.0</td></tr><tr><td rowspan="8">Extension Busses</td><td>USB</td><td>2x USB 3.0, 4x USB 2.0</td></tr><tr><td>UART</td><td>Three UART interfaces: SER1 and SER 3 (CTS/RTS), and SER0 (TX/RX/CTS/RTS)</td></tr><tr><td>CAN</td><td>1x CAN2.0B only or mixed CAN2.0B data bit rate up to 8Mbps</td></tr><tr><td>SPI</td><td>2x SPI</td></tr><tr><td>I2S</td><td>1x I2S interface with audio resolution from 16-bits to 32-bits and sample rate up to 192kHz (see Audio Codec support)</td></tr><tr><td>I2C</td><td>4x I2C interfaces</td></tr><tr><td>GPIO</td><td>14x GPIO with interrupt, one GPIO with PWM</td></tr><tr><td>PCIe</td><td>1x PCIe x2 Gen3, 1x PCIe Gen 2</td></tr><tr><td>Power</td><td>Input</td><td>5Vdc +/- 5%</td></tr><tr><td colspan="2">Mechanical and Environmental Form Factor</td><td>SGET SMARC Specifications 2.1.1</td></tr><tr><td rowspan="7"></td><td>Dimension</td><td>SMARC short size module 82 mm x 50 mm</td></tr><tr><td>Operating Temperature</td><td>Standard: 0°C to 60°C</td></tr><tr><td></td><td>Rugged: -40°C to 85°C (optional)</td></tr><tr><td>Humidity</td><td>5-90% RH operating, non-condensing</td></tr><tr><td></td><td>5-95% RH storage (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr><tr><td>Operating Systems</td><td>Standard Support</td><td>Canonical Ubuntu, Yocto Linux</td></tr></table>

Ordering Information

<table><tr><td>Part name</td><td>Description/Configuration</td></tr><tr><td>LEC-MTK-I1200-2G-32G-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 2 GB LPDDR4, 32 GB eMMC, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-4G-32G-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 4 GB LPDDR4, 32 GB eMMC, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-8G-64G-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 8 GB LPDDR4, 64 GB eMMC, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-2G-32G-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 2 GB LPDDR4, 32 GB eMMC, -40°C to 85°C</td></tr><tr><td>LEC-MTK-I1200-4G-32G-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 4 GB LPDDR4, 32 GB eMMC, -40°C to 85°C</td></tr><tr><td>LEC-MTK-I1200-8G-64G-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 8 GB LPDDR4, 64 GB eMMC, -40°C to 85°C</td></tr><tr><td>LEC-MTK-I1200-2G-32G-BW-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 2 GB LPDDR4, 32 GB eMMC, AC Wi-Fi BT 5.1, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-4G-32G-BW-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 4 GB LPDDR4, 32 GB eMMC, AC Wi-Fi BT 5.1, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-8G-64G-BW-CT</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 8 GB LPDDR4, 64 GB eMMC, AC Wi-Fi BT 5.1, 0°C to 60°C</td></tr><tr><td>LEC-MTK-I1200-2G-32G-BW-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 2 GB LPDDR4, 32 GB eMMC, Wi-Fi BT 5.1, -40°C to 85°C</td></tr><tr><td>LEC-MTK-I1200-4G-32G-BW-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 4 GB LPDDR4, 32 GB eMMC, Wi-Fi BT 5.1, -40°C to 85°C</td></tr><tr><td>LEC-MTK-I1200-8G-64G-BW-ER</td><td>SMARC 2.1 Short Size Module with MediaTek Genio 1200 platform, 8 GB LPDDR4, 64 GB eMMC, AC Wi-Fi BT 5.1, -40°C to 85°C</td></tr></table>

# Block Diagram

![Based on the provided flowchart, here is the accurate description of the labeled blocks and their connections:\n\n**Central Processing Unit (SoC)**\n*   **MT8195 4x A78, 4x A55** (Center Block): Contains an **NPU** block.\n\n**Left Column: SMARC Gold Finger 314-pin**\n*   **DSI0/eDP0** connects to **DP MUX 1:2**.\n    *   **DP MUX 1:2** connects to **eDP** (4 Lane) and **DSI0** (4 Lane).\n*   **DSI1** connects to **DSI1** (4 Lane).\n*   **HDMI/DP1** connects to **HDMI/DP MUX**.\n    *   **HDMI/DP MUX** connects to **HDMI TX** and **DisplayPort** (x4 bits).\n*   **SDIO** connects to **MSDC1**.\n*   **SPI0** connects to **SPI M1**.\n*   **SPI1** connects to **SPI M2**.\n*   **CAN0** connects to **SPI to CAN**.\n    *   **SPI to CAN** connects to **SPI M0**.\n*   **I2S0** connects to **I2S01+I2S IN**.\n*   **SER0** (4 Wire) connects to **UART2**.\n*   **SER1** (2 Wire) connects to **UART0**.\n*   **SER3** (2 Wire) connects to **UART3**.\n*   **USB1** (USB 2.0) connects to **USB P1(2.0)**.\n*   **USB0** (USB 2.0 OTG) connects to **USB MUX**.\n    *   **USB MUX** connects to **USB 2.0** (3 lines) leading to **USB P3(2.0)**, **USB P2(2.0)**, and **GPIO3** (dotted line).\n*   **SER2** (4 Wire) connects to **USB to UART**.\n    *   **USB to UART** connects to **USB 2.0** leading to **USB HUB**.\n*   **USB2** (USB 3.0), **USB3** (USB 3.0), **USB4** (USB 2.0), and **USB5** (USB 2.0) all connect to **USB HUB**.\n*   **GbE1** connects to **Ethernet Controller**.\n    *   **Ethernet Controller** connects via **USB 3.0** to **USB HUB**.\n*   **GbE0** connects to **Ethernet PHY**.\n    *   **Ethernet PHY** connects via **2 Lane** to **RGMII**.\n*   **CSI0** connects to **CSI1-2lane P1**.\n*   **CSI1** connects to **CSI0-4lane P1**.\n*   **PCIe A** connects to **PCIe P0 lane0(PCIe Gen3)**.\n*   **PCIe B** and **PCIe C** connect to separate **PCIe MUX** blocks.\n    *   These merge into **PCIe x1** (labeled with **WiFi/BT**) connecting to **PCIe P1(PCIe Gen2)**.\n*   **GPIO** connects to **GPIO**.\n*   **I2C_PM** connects to **I2C2**.\n*   **I2C_GP** connects to **I2C3**.\n*   **I2C_LCD** connects to **I2C0**.\n*   **I2C_CAM0** connects to **I2C1**.\n*   **I2C_CAM1** connects to **I2C4**.\n\n**Bottom Peripherals (Connected to SoC)**\n*   **GPIO** connects to **GPIO Expander0**.\n*   **I2C2** connects to **GPIO Expander1**.\n*   **I2C3** connects to **Crypto Auth.**\n*   **I2C0** connects to **RTC**.\n*   **I2C1** connects to **TPM**.\n\n**Right Side: External Components**\n*   **EMI (0:3)** connects to **LPDDR4x x16 x2ch x2** (x16 bits x4).\n*   **UFS** connects to **UFS** (1 Lane).\n*   **UART0** (2 Lane) connects to **30-pin Debug Connector**.\n*   **JTAG** and **Boot Sel** connect to **30-pin Debug Connector**.\n*   **CSIO-4lane P2** connects via **4 Lane** to **Camera FPC connector**.\n*   **PMIC_ADIUO** connects to **PMIC MT6365**.\n*   **PWRAP_SPI** connects to **PMIC MT6360**.\n*   **SPMI_I2C** connects to two blocks labeled **PMIC MT6315**.\n*   **WiFi/BT** (Red label) connects via **PCIe x1** to **Wifi/BT module (M.2 / 1216)**.\n*   **WiFi/BT** (Yellow label) connects via **USB 3.0/2.0** to **Wifi/BT module**.\n*   **WiFi/BT** (Cyan label) connects via **USB to UART** then **UART** to **Wifi/BT module**.](.lec-mtk-i1200-datasheet-250527/79443be9d9691aeab3ac1a33ac92812c0ce5e3cc90f63a55c1aed9e8c9920d45.jpg)

Note: “Build option””indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.
[🔗 Link to the original document](.lec-mtk-i1200-datasheet-250527/lec-mtk-i1200-datasheet-250527.pdf)