![Green printed circuit board with multiple connectors and components (no visible text or symbols)](.pci-6202-datasheet-en-1/90cd48c8f3ed85e7af7bc2a70c4e2b46909fddfb369805ac326bb19013815697.jpg) ![The image displays a logo on a light blue background. Large, bold, black letters spell out 'PCI' in a slanted font, with a horizontal line running through the center of the 'P' and 'C'. Below this, the word 'CONVENTIONAL' appears in green capital letters, followed by a small registered trademark symbol.](.pci-6202-datasheet-en-1/22650766795ad3f6039bf99b36ff46a64abb30b728bcde87a9e9cfabe96a4f88.jpg) # Introduction The ADLINK PCI-6202 is a 4-CH, 16-bit high resolution voltage output card with hardware timed waveform generation. Four analog output channels can update simultaneously and support up to 1 MS/s update rate per channel. The PCI-6202 features excellent linearity (DNL < 1 LSB), which is suitable for dynamic signal simulation and control applications requiring high accuracy through voltage output. Furthermore, the PCI-6202 provides additional I/O control lines for system integration, such as 16-CH isolated digital input and 16-CH isolated output, 8-CH TTL DI and 8-CH TTL DO, 3-CH encoder inputs, and 4-CH PWM outputs. Combined, these I/O functionalities, solid voltage output linearity, and high accuracy, make the PCI-6202 the best single-board solution for both equipment manufacturers and laboratory research applications. # Features Supports a 32-bit 3.3 V or 5 V PCI bus ■ Hardware-based waveform generation ■ DNL Linearity less than 1 LSB Digital triggering for waveform generation ■ 16-CH isolation digital inputs & 16-CH isolation digital outputs 8-CH TTL DI and 8-CH TTL DO ■ 2-CH timer/counter, base clock: 40 MHz ■ 4-CH PWM output ■ 3-CH encoder inputs, supporting AB phase and CW/CCW ■ Multiple card synchronization through SSI (System Synchronization Interface) bus ■ Operating Systems • Windows 7/Vista/2000/XP/Server 2003 • Linux ■ Recommended Software • AD-Logger • VB.NET/VC.NET/VB/VC++/BCB/Delphi • DAQBench ■ Driver Support • DAQPilot for LabVIEW™ • DAQ-MTLB for MATLAB® • PCIS-DASK for Windows • PCIS-DASK/X for Linux # Specifications # Analog Output ■ Resolution: 16 bits ■ Number of channels: Four (simultaneous update) ■ Maximum update rate: 1 MS/s ■ FIFO buffer size: 8k Samples (4-CH Sharing) ■ Output range: ±10 V ■ DNL: Less than ±1 LSB ■ Offset Error: 0.3 mV ■ Positive Gain Error: 0.3 mV ■ Negative Gain Error: 0.3 mV ■ Settling Time: 3 μs ■ Slew Rate: 20 V/μs ■ Rise Time: 0.67 μs ■ Falling Time: 0.705 μs ■ Output Current Capacity: 5 mA ■ Trigger source: Software, External digital, SSI bus ■ Data Transfer: Software polling, DMA # Isolated Digital Input ■ Number of channels: 16 ■ Maximum input range: 24 V, non-polarity ■ Digital logic level • Input high voltage: 10-24 V • Input low voltage: 0-1.5 V ■ Isolation voltage: 2500 VRMS # Isolated Digital Output ■ Number of channels: 16 ■ Sink current limitation: 250 mA for one channel @ 100% duty ■ Supply voltage: 5-35 VDC ■ Isolation voltage: 2500 VRMS # Encoder Input ■ Number of channels: Three Encoder type • CW/CCW encoder • x1 AB phase encoder • x2 AB phase encoder • x4 AB phase encoder # Function I/O Digital I/O: Eight DO (3.3 V TTL Level)/Eight DI (3.3 V or 5 V TTL Level) ■ General Timer/Counter: Two 32-bit, Base clock: 80 MHz, external to 10 MHz ■ Pulse Generation: Four PWM Outputs • Single pulse generation • Pulse train generation ■ AFI0/AFI1: D/A Convert Clock or Start Trigger # General Specifications ■ PCI Bus: 5 V and 3.3 V universal PCI bus ■ I/O Connector: Two 68-pin SCSI-VHDCI female ■ Operation temperature: 0˚C to 55˚C ■ Storage temperature: -20˚C to 70˚C ■ Relative humidity: 5% to 95%, non-condensing ■ Power requirements: <table>+5 V+12 V500 mA typical110 mA typical ■ Dimensions: 175 mm x 107 mm (not including connectors) # Terminal Boards & Cables ■ DIN-68S-01 Terminal Board with One 68-pin SCSI-II connector and DIN-Rail Mounting (Cables are not included.) ■ ACL-10568-1 68-pin SCSI-VHDCI cable (mating with AMP-787082-7), 1 M \* For more information on mating cables, please refer to P2-61/62. # SSI Bus Cables # (for multiple cards synchronization) ■ ACL-SSI-2 SSI Bus cable for two devices ■ ACL-SSI-3 SSI Bus cable for three devices ■ ACL-SSI-4 SSI Bus cable for four devices # Ordering Information ■ PCI-6202 4-CH 16-Bit 1 MS/s Analog Output & 32-CH Isolation DIO Card Pin Assignment
CNICN2
DO_0135GPTC_OUT0IDI_0135IDI_8
DO_1236GPTC_GATE0IDI_1236IDI_9
DO_2337GPTC_UD0IDI_2337IDI_10
DO_3438GPTC_AUX0IDI_3438IDI_11
DO_4539GPTC_CLK0IDI_4539IDI_12
DO_5640GPTC_OUT1IDI_5640IDI_13
DO_6741GPTC_GATE1IDI_6741IDI_14
DO_7842GPTC_UD1IDI_7842IDI_15
DGND943GPTC_AUX1COM943COM
DGND1044GPTC_CLK1COM1044COM
DI_01145DGNDEA0+1145EA1+
DI_11246DGNDEA0-1246EA1-
DI_21347DGNDEB0+1347EB1+
DI_31448DGNDEB0-1448EB1-
DI_41549DGNDEZ0+1549EZ1+
DI_51650DGNDEZ0-1650EZ1-
DI_61751DGNDEORG01751EORG1
DI_71852DGNDEA2+1852EZ2+
DGND1953PWM_0EA2-1953EZ2-
DGND2054PWM_1EB2+2054EORG2
DGND2155PWM_2EB2-2155Ext. 24V
DGND2256PWM_3Ext. GND2256Ext. 24V
DGND2357AFI0IGND2357Ext. GND
AGND2458AFI1IGND2458IGND
AGND2559NCVDD2559IGND
AGND2660AGNDVDD2660ISO5V
AGND2761AGNDIDO_02761IDO_8
AGND2862AGNDIDO_12862IDO_9
AGND2963AGNDIDO_22963IDO_10
AGND3064AGNDIDO_33064IDO_11
AO_CH03165AGNDIDO_43165IDO_12
AO_CH13266AGNDIDO_53266IDO_13
AO_CH23367AGNDIDO_63367IDO_14
AO_CH33468AGNDIDO_73468IDO_15
PCI-6202 Block Diagram ![The diagram depicts a system architecture centered around a large block labeled **FPGA**. This FPGA block is subdivided into a grid containing the following modules:\n\n**Top Row:**\n* **AO DATA FLOW Control**\n* **FIFO Control**\n* **Calibration Data Storage**\n\n**Middle Row:**\n* **AO Control**\n* **FPGA** (center label)\n* **PCI INTERFACE**\n\n**Bottom Row:**\n* **Calibration Control**\n* **AFI, GPIO, GPTC, Decoder**\n* **SSI Control**\n\n**Connections and Peripheral Blocks:**\n\n* **Left Side:** A vertical double-headed arrow labeled **SCSI CONNECTOR X 2 INTERFACE** connects to four triangular blocks labeled **OP**. Three of these connect directly to the SCSI interface. One **OP** block connects downward to a block labeled **Calibration DAC 10Bit TriamDAC**, which is also connected to a circle labeled **REF VOLTAGE**.\n* **DAC/Latch Cluster:** To the left of the FPGA, a greenish block contains four rows of components: **CH0 16Bit DAC** and **CH0 LATCH**, **CH1 16Bit DAC** and **CH1 LATCH**, **CH2 16Bit DAC** and **CH2 LATCH**, and **CH3 16Bit DAC** and **CH3 LATCH**. Arrows originate from **AO Control** pointing up to these components. A purple arrow labeled **DATA** points from this cluster into **AO DATA FLOW Control**.\n* **Top Right:** A block labeled **EEPROM** connects downward to **Calibration Data Storage**.\n* **Right Side:** A vertical double-headed arrow labeled **PCI INTERFACE** connects to the **PCI INTERFACE** module.\n* **Bottom:** A horizontal double-headed arrow labeled **SSI INTERFACE** connects to **SSI Control**. A horizontal arrow labeled **DIGITAL IO FUNCTION** points left from **AFI, GPIO, GPTC, Decoder**.](.pci-6202-datasheet-en-1/4512b979f682b1872838cdd9b561cd4fd13bad97f7b3e6ac0b614512475c9b8b.jpg) [🔗 Link to the original document](.pci-6202-datasheet-en-1/pci-6202-datasheet-en-1.pdf)