![Green printed circuit board with visible components and connectors (no readable text or symbols)](.pcie-7360-datasheet-en-1/59e98a45145422c9d5715d359bd3fc7f530d015eaed84069f0b476b29f0a39e7.jpg)

# Features

■ x4 lane PCI Express® Interface
■ 8/16/24/32-CH at up to100MHz for DI or DO
8/16-CH at up to 200MHz for DI in external clock mode
■ 400 MB/s maximum throughput
■ Voltage level software selectable from 1.8 V, 2.5 V, and 3.3 V
■ 80-step phase shift in external clock mode
■ Per group (8-bit) input/output direction selectable
■ Support for I2C and SPI programmable serial interfaces for external device communication
■ Scatter-gather DMA support
■ Flexible handshake and external digital trigger modes
■ 8-channel auxiliary programmable I/O

# Software Support

■	Supported Operating System
• Windows 7/8 x64/x86, Linux
Driver and SDK
• LabVIEW, MATLAB, C/C++, Visual Basic, Visual Studio.NET

# Terminal Boards & Cables

■ DIN-68H-01
Terminal board with one 68-pin SCSI-VHDCI connector and 0 or 50 Ω jumper selectable impedance (Cables are not included.)
■ ACL-10279
• 68-pin SCSI-VHDCI cable with 50 Ω impedance
■ SMB-SMB-1M
• SMB to SMB cable, 1M
\* For more information about mating cables, please refer to P3-48/49.

# Ordering Information

■ PCIe-7360

100 MHz 32-CH High-Speed Digital I/O PCI Express® Card

# Introduction

ADLINK’s PCIe-7360 is a high-speed digital I/O board with 32-CH bi-directional parallel I/O, with data rates up to 400 MB/s are available through the x4 PCI Express® interface, and clock rates up to 100 MHz internal or 200 MHz external, ideally suiting high speed and large scale digital data acquisition or exchange applications, such as digital image capture, video playback and IC testing.

# Specifications

# Digital I/O

■ 32-channels, per group (8-channel) input/output direction, with selectable logic levels: 1.8 V, 2.5 V, 3.3 V (software selectable)
■ Power-up status: All digital inputs
■ Impedance:

• Input: 10 kΩ

• Output: 50 Ω

■ Input protection: -1 to 6 V
Data transfer: Programmable I/O, bus-mastering DMA with scatter-gather
■ Maximum data transfer rate: 400 MB/s
■ Digital logic levels:

<table><tr><td colspan="2">Logic Levels</td><td>1.8 V</td><td>2.5 V</td><td>3.3 V</td></tr><tr><td rowspan="2">Digital Input</td><td>Min. input high voltage</td><td>1.2 V</td><td>1.6 V</td><td>2 V</td></tr><tr><td>Max. input low voltage</td><td>0.63 V</td><td>0.7 V</td><td>0.8 V</td></tr><tr><td rowspan="3">Digital Output</td><td>Min. output high voltage</td><td>1.6 V</td><td>2.3 V</td><td>3.1 V</td></tr><tr><td>Max. output low voltage</td><td>0.2 V</td><td>0.2 V</td><td>0.2 V</td></tr><tr><td>Max. output driving current</td><td>8 mA</td><td>16 mA</td><td>32 mA</td></tr></table>

# Clocking Mode

■ Internal clock: up to 100 MHz (100 MHz / N; 1<N<65535)
External clock: up to 100 MHz (support 8/16/24/ 32-bit data width for DI/DO); up to 200 MHz (support 8/16-bit data width for DI only)
■ Handshake
■ Burst handshake

# Trigger Sources

■ Software trigger
■ External digital trigger: AFI[0…7]

# Trigger Modes

■ Post trigger, Retrigger, Pattern match, Handshake

# Change of State Interrupt

■ Interrupt sources: Any of 32 channels or a pre-define channel change-of-state

# Application Function I/O

■ 8 channels
■ Supported modes: static I/O, I2 C or SPI master node, external clock input/output, external digital trigger input, handshake

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **External/Interface Blocks:** 'SMB IN', 'SMB OUT', '100MHz OSC', 'VHDCC-68P CONNECTOR INTERFACE', 'PCI Express x4 INTERFACE'.\n*   **Timing/Clock Blocks:** '80 Steps Phase Shift Control', 'Ext. CLK in', 'Ext. CLK out', 'Int. Timbase', 'Ext. CLK IN/OUT'.\n*   **Main Control Block:** 'Pattern Acquisition/ Generation Timing Control'.\n    *   **Internal Sub-blocks:** 'DI Latch', '8K FIFO', 'DI DMA', 'PCIe INTERFACE', 'DO Buffer', '20K FIFO', 'DO DMA', 'Logic Level Control', 'ADLINK Smart Control Engine', 'I2C/SPI', 'AFI Interface'.\n*   **Logic Level Blocks (Orange Boxes):**\n    *   Top: '1.8/2.5/3.3V Logic Level Selectable' (containing four 'Level Shifter' blocks).\n    *   Bottom: '1.8/2.5/3.3V Logic Level Selectable' (containing two 'Level Shifter' blocks).\n*   **Signal/Data Labels:** 'DI DATA', 'DO DATA', 'AFI BUS', 'DIO7_0', 'DIO15_8', 'DIO23_16', 'DIO31_24', 'AFI5_0', 'AFI7_4'.\n\n**Connections:**\n*   **Clock & Phase Control:**\n    *   'SMB IN' connects via 'Ext. CLK in' to '80 Steps Phase Shift Control'.\n    *   '80 Steps Phase Shift Control' outputs 'Ext. CLK out' to 'SMB OUT'.\n    *   '100MHz OSC' provides 'Int. Timbase' to the 'Pattern Acquisition/ Generation Timing Control'.\n    *   '80 Steps Phase Shift Control' connects via 'Ext. CLK IN/OUT' to the 'Pattern Acquisition/ Generation Timing Control'.\n\n*   **Digital Input Path (Left to Center):**\n    *   The top '1.8/2.5/3.3V Logic Level Selectable' block (with four 'Level Shifter' blocks) connects to the 'VHDCC-68P CONNECTOR INTERFACE' via 'DIO7_0', 'DIO15_8', 'DIO23_16', and 'DIO31_24'.\n    *   Simultaneously, this block outputs 'DI DATA' (blue arrow) into the 'DI Latch' block.\n\n*   **Data Processing Flow (Inside Main Blue Box):**\n    *   'DI Latch' connects to '8K FIFO'.\n    *   '8K FIFO' connects to 'DI DMA'.\n    *   'DI DMA' connects to 'PCIe INTERFACE'.\n    *   'PCIe INTERFACE' connects to the external 'PCI Express x4 INTERFACE'.\n    *   Data returns from 'PCIe INTERFACE' to 'DO DMA'.\n    *   'DO DMA' connects to '20K FIFO'.\n    *   '20K FIFO' connects to 'DO Buffer'.\n\n*   **Digital Output Path (Center to Left/Bottom):**\n    *   'DO Buffer' outputs 'DO DATA' (blue arrow) to the left.\n    *   This connects to the bottom '1.8/2.5/3.3V Logic Level Selectable' block (with two 'Level Shifter' blocks).\n    *   These shifters connect to the 'VHDCC-68P CONNECTOR INTERFACE' via 'AFI5_0' and 'AFI7_4'.\n    *   'AFI Interface' connects via 'AFI BUS' (green arrow) to the bottom '1.8/2.5/3.3V Logic Level Selectable' block.\n    *   'I2C/SPI' connects to the 'AFI BUS' area.\n\n*   **Internal Logic:**\n    *   'ADLINK Smart Control Engine' is centrally located within the main control block.\n    *   'Logic Level Control' is positioned between the DI Latch and FIFO section.](.pcie-7360-datasheet-en-1/d74cc601206819e002f9f5cf5274deed9ced08e8ca812d126e2d8edcb598cae9.jpg)

PCIe-7360 Block Diagram
[🔗 Link to the original document](.pcie-7360-datasheet-en-1/pcie-7360-datasheet-en-1.pdf)