# COM-HPC-cBLS

Client Type COM-HPC Size C Module Based on Intel® Bartlett Lake-S Platform

![Coming soon\nADLINK\nCOM-HPC®](.preliminary-com-hpc-cbls-datasheet-20250618/831efde111b5ddaa95c2be8d0a8ef2cafb11896e9b259fb21c361c86d9e596ae.jpg)

# Features

• Advanced hybrid architecture combining P-cores and E-cores
• Up to 128GB DDR5 SODIMM, ECC/non-ECC
• 1x PCIe Gen5 x16, 4x PCIe Gen4 x4, Multiple PCIe Gen3
• 2x 2.5 GbE LAN
• Best-in-class longevity support

Specifications

<table><tr><td rowspan="9">Core System</td><td rowspan="6">SoC</td><td colspan="2">Intel Core S Processor Platform (formerly Bartlett Lake-S)</td></tr><tr><td>Processor</td><td>TDP</td></tr><tr><td>Core 7</td><td>65W</td></tr><tr><td>Core 5</td><td>65W</td></tr><tr><td>Core 3</td><td>65W</td></tr><tr><td colspan="2">1. Additional 45W SKU available on a project basis.2. ECC is supported when paired with the R680E PCH.Supports: Intel® VT (including VT-x / VT-d), Intel® Turbo Boost Technology 2.0, Intel® VNNI, Intel® TCC and Time-Sensitive Networking (TSN), Intel® Hardware Shield, Intel® TXT, Intel® System Security Report, Intel® APIC-v, Intel® PTT, Intel® TDT, Intel® CET, Intel® AMT, Intel® UPID, Intel® PMT, Intel® Thermal Velocity Boost (TVB) (by SKU)Note: Availability of features may vary between processor SKUs.</td></tr><tr><td>Memory</td><td colspan="2">Up to 128GB (4x 32GB) DDR5 SODIMM memory,max. four sockets (two on top, two at the bottom)Note: It is recommended to check that the bottom side specifications are suitable for your application purposes.</td></tr><tr><td>Embedded BIOS</td><td colspan="2">AMI UEFI with CMOS backup in 32MB SPI BIOS (dual BIOS opt.)</td></tr><tr><td>Cache</td><td colspan="2">36/30/24/12MB</td></tr></table>

Note: “Build option””indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.

Specifications

<table><tr><td rowspan="3">Core System</td><td>Expansion Busses</td><td>1 PCIe Gen5 x16 at 16-31 and 1 PCIe Gen4 x4 at 8-116 PCIe Gen3 x1 at 0-5 (x4, x2, x1)More lanes with R680E/Q670E (all x4, x2, x1):o 1 PCIe Gen4 x4 at 12-15o 1 PCIe Gen4 x4 at 32-35o 1 PCIe Gen4 x4 at 36-39Note: PCIe lanes 0-5, USB 3.0, SATA, NBASE-T and PCIe_BMC source from HSIO. The available total raw bandwidth is equivalent to PCIe x16 Gen3SMBus, 2x I2C, 1x GP SPI, 1x Boot_SPI and eSPI</td></tr><tr><td>SEMA Board Controller</td><td>Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2C, watchdog timer, fan control and failsafe BIOS (dual BIOS by build option)</td></tr><tr><td>Debug Headers</td><td>40-pin multipurpose flat cable connector for use with DB40-HPC debug module providing BIOS POST code LED, MMC/EC access, SPI BIOS flashing, power testpoints, debug LEDs</td></tr><tr><td rowspan="3">Video</td><td>GPU Feature Support</td><td>Intel UHD Graphics 770 driven by Xe architecture, supporting multiple independent and simultaneous display combinations of DisplayPort/HDMI, eDP outputs (4x 4K60)Hardware encode/transcode of HD content (including HEVC)DirectX 12 supportOpenGL 4.6 support</td></tr><tr><td>Display Interface</td><td>DDI 0/1/2 supporting DisplayPort/HDMI/DVIDP1.4a and HDMI2.0b</td></tr><tr><td>eDP</td><td>4 lane support, eDP 1.4b</td></tr><tr><td rowspan="2">Audio</td><td>Chipset</td><td>Intel HD Audio integrated on CPU</td></tr><tr><td>Audio Codec</td><td>On COM-HPC Client Base Carrier (Realtek ALC888)</td></tr><tr><td rowspan="2">NBASE-T Ethernet</td><td>Intel® MAC/PHY</td><td>Intel® Ethernet Connection I226 Series</td></tr><tr><td>Interface</td><td>2x 2.5GbE and 1000/100/10 Mbit/s Ethernet connection</td></tr><tr><td rowspan="5">Multi I/O and Storage</td><td rowspan="2">USB</td><td>4x USB 3.2/2.0/1.1 (USB 0,1,2,3)</td></tr><tr><td>4x USB 2.0/1.1 (USB 4,5,6,7)</td></tr><tr><td>SATA</td><td>2x SATA (SATA 0, 1)</td></tr><tr><td>Serial</td><td>2x UART ports with console redirection</td></tr><tr><td>GPIO</td><td>12x GPIO (GPI with interrupt, TBC)</td></tr><tr><td rowspan="2">TPM (Optional)</td><td>Chipset</td><td>Infineon</td></tr><tr><td>Type</td><td>TPM 2.0 (SPI based)</td></tr><tr><td rowspan="4">Power</td><td>Standard Input</td><td>ATX (TBC): 12V±5% / 5Vsb ±5%; or AT: 12V±5%</td></tr><tr><td>Management</td><td>ACPI 5.0 compliant</td></tr><tr><td>Power States</td><td>TBC</td></tr><tr><td>ECO mode</td><td>TBC</td></tr></table>

Note: “Build option””indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.

Specifications

<table><tr><td rowspan="6">Mechanical and Environmental</td><td>Form Factor</td><td>PICMG COM-HPC: Rev 1.1 Client Type</td></tr><tr><td>Dimensions</td><td>Size C 160X120 mm</td></tr><tr><td>Operating Temperature</td><td>Standard: 0°C to 60°C (storage: -20°C to 80°C)</td></tr><tr><td>Humidity</td><td>5-90% RH operating, non-condensing5-95% RH storage (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D (TBC)</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr><tr><td>Operating Systems</td><td>Standard Support</td><td>Windows 11 IoT Enterprise LTSCWindows 10 IoT Enterprise LTSCUbuntu</td></tr></table>

# Ordering Information

This section will be updated later.

![**Labeled Blocks:**\n\n*   **J1**\n*   **J2**\n*   **Intel Core S Processor Bartlett Lake-S**\n*   **Chipset R680E, Q670E, H610E**\n*   **Embedded Controller**\n*   **DDR5 SODIMM 4800 MT/s** (two blocks)\n*   **Intel i226** (two blocks)\n*   **BIOS flash**\n*   **TPM 2.0**\n*   **EEPROM**\n*   **DB40-HPC connector**\n*   **fan connector**\n*   **LM73 (board)**\n*   **J1 Labels:** eDP, DDI 0, DDI 1, PCIe 0-5, PCIe 0-3 (4 x1 or 1 x4 or 2 x2), PCIe 4-5 (2 x1 or 1 x2), PCIe 4 only, PCIe 8-11, PCIe 12-15, x4, x2, x1, NBASE-T 0, NBASE-T 1, USB3.x_0, USB3.x_1, USB 2.0 0-7, SATA 0-1, HDA, BOOT_SPI, GP_SPI, SMBus, I2C_0, I2C_1, 12xGPIO, 2xUART, eSPI\n*   **Processor Labels:** PCIe x16 GEN5, PCIe x4 Gen4, 6 PCIe Gen3 (HSIO10-15), 4 PCIe Gen4 (HSIO22-25) (Q670E, R680E), 4 PCIe Gen4 (HSIO30-33) (Q670E, R680E), 4 PCIe Gen4 (HSIO34-37) (Q670E, R680E), 1 PCIe (HSIO16), 1 PCIe (HSIO17), USB3.2 Gen2 x1 (HSIO0), USB3.2 Gen2 x1 (HSIO1)\n*   **Chipset Labels:** USB3.2 Gen1 x1 (HSIO2), USB3.2 Gen1 x1 (HSIO3), (HSIO26-27)\n*   **J2 Labels:** DDI 2, PCIe 16-31, PCIe 32-35, PCIe 36-39, x4, x2, x1, USB3.x_2, USB3.x_3\n\n**Connections:**\n\n*   **J1 to Intel Core S Processor Bartlett Lake-S:**\n    *   `eDP` connects to `eDP x4` which connects to the Processor.\n    *   `DDI 0` and `DDI 1` connect directly to the Processor.\n    *   `DDR5 SODIMM 4800 MT/s` connects to the Processor.\n    *   `PCIe 0-5` connects via `PCIe 0-3 (4 x1 or 1 x4 or 2 x2)` and `PCIe 4-5 (2 x1 or 1 x2)` to the Processor via `PCIe x4 Gen4`. A label `PCIe 4 only` is present near this path.\n    *   `PCIe 8-11` connects to the Processor via `6 PCIe Gen3 (HSIO10-15)`.\n\n*   **J1 to Chipset R680E, Q670E, H610E:**\n    *   `PCIe 12-15` (`x4, x2, x1`) connects to the Chipset via `4 PCIe Gen4 (HSIO22-25) (Q670E, R680E)`.\n    *   `NBASE-T 0` connects to `Intel i226` which connects to the Chipset via `1 PCIe (HSIO16)`.\n    *   `NBASE-T 1` connects to `Intel i226` which connects to the Chipset via `1 PCIe (HSIO17)`.\n    *   `USB3.x_0` connects to the Chipset via `USB3.2 Gen2 x1 (HSIO0)`.\n    *   `USB3.x_1` connects to the Chipset via `USB3.2 Gen2 x1 (HSIO1)`.\n    *   `USB 2.0 0-7`, `SATA 0-1` (via `(HSIO26-27)`), and `HDA` connect directly to the Chipset.\n    *   `BOOT_SPI` connects to `BIOS flash`.\n    *   `GP_SPI`, `SMBus`, `I2C_1`, and `I2C_0` (via `EEPROM`) connect to the Chipset via dashed lines.\n\n*   **Intel Core S Processor Bartlett Lake-S to J2:**\n    *   `PCIe x16 GEN5` connects to J2 `PCIe 16-31`.\n    *   `4 PCIe Gen4 (HSIO30-33) (Q670E, R680E)` connects to J2 `PCIe 32-35` via `x4, x2, x1`.\n    *   `4 PCIe Gen4 (HSIO34-37) (Q670E, R680E)` connects to J2 `PCIe 36-39` via `x4, x2, x1`.\n    *   `DDI 2` (from J2) connects to the Processor.\n\n*   **Chipset R680E, Q670E, H610E to J2:**\n    *   `USB3.2 Gen1 x1 (HSIO2)` connects to J2 `USB3.x_2`.\n    *   `USB3.2 Gen1 x1 (HSIO3)` connects to J2 `USB3.x_3`.\n\n*   **Other Connections:**\n    *   The Chipset connects to `DB40-HPC connector`.\n    *   The Chipset connects to the `Embedded Controller`.\n    *   J1 `12xGPIO`, `2xUART`, and `eSPI` connect to the `Embedded Controller`.\n    *   The `Embedded Controller` connects to `fan connector` and `LM73 (board)`.](.preliminary-com-hpc-cbls-datasheet-20250618/839d093aab100c1f3d489e2e268751a8b69c219649ca651d13523977c11f2119.jpg)

Note: “Build option””indicates an alternative BOM configuration to support additional or alternative functions that are not available on the standard product. Be aware that these “build option” part numbers will need to be newly created and this will result in production lead times.
[🔗 Link to the original document](.preliminary-com-hpc-cbls-datasheet-20250618/preliminary-com-hpc-cbls-datasheet-20250618.pdf)