# Spectra IP CORE ORB High Performance Message Processing for FPGAs Spectra IP Core ORB (ICO) is a hardware implementation of CORBA’s GIOP protocol and is part of ADLINK’s Spectra Common Data Bus (CDB) range of high performance embedded messaging solutions. ICO provides an implementation of the GIOP protocol at the gate level and by supporting a highly optimized subset of ORB features it is now possible to provide a single, seamless industry standard data protocol across processor architectures. Specifically designed to support high performance Software Defined Radio (SDR) applications based on the Software Communications Architecture (SCA), ICO can just as easily be used as a general purpose integration solution for use in embedded FPGA applications with no SCA requirements. # FPGA Integration Has Never Been Easier ICO is used as a GIOP message-processing engine for FPGAs and ASICS, enabling a standard protocol to be run across multiple processor architectures (GPP, DSP and FPGA). This reduces the need to support custom protocols and proprietary interfaces. These non-standard types of interface in an FPGA environment are often referred to as Hardware Abstraction Layers (HALs). The major problem with the HAL approach is that they are difficult to implement and maintain and require the hardware developer to understand the low-level details of each proprietary messaging protocol. They also need to be re-written if the underlying hardware changes reducing application portability and increasing time to market and cost for new applications. ICO further eliminates the need to embed general purpose processing cores into FPGAs in order to offer software ORB capability. Although a viable approach, this approach tends to require significant gate count and memory utilization and generally these processing cores cannot be clocked fast enough to deal with the ever-increasing performance requirements of SDR applications. ICO has been written in portable VHDL that can be synthesized onto any FPGA or ASIC device. The ICO development environment consists of: • The ICO IP core message processing engine • • A number of board specific example transports • Supporting user documentation ICO was designed to be modular and configurable. Figure 1 below provides an illustration of ICO’s architecture. Figure 1 below provides an illustration of ICO’s architecture. Components shown in yellow are provided as part of the ICO core, components in blue are generated by the IDL to VHDL compiler for each specific design. ![This flowchart depicts a system architecture divided into two main sections: an **FPGA** (Field Programmable Gate Array) on the left and an **ICO** (Integrated Controller/Processor) on the right, along with an external interface.\n\n**Labeled Blocks:**\n* **External Interface**\n* **FPGA**\n* **ICO**\n* **Transport**\n* **FIFO**\n* **Rx Bridge**\n* **Meta Data ROM** (top right)\n* **Arbitration** (top)\n* **Servant** (left)\n* **Servant** (middle)\n* **Client**\n* **Meta Data ROM** (bottom left)\n* **Arbitration** (bottom)\n* **Tx Bridge**\n\n**Connections:**\n* **External Interface** connects to **Transport** via a pink dashed arrow.\n* **FPGA** connects to **FIFO** via a teal dashed arrow.\n* **Transport** connects to **FIFO** via a teal dashed arrow labeled **GIOP Message**.\n* **FIFO** and **Rx Bridge** are connected by a teal dashed double-headed arrow.\n* **Rx Bridge** and **Meta Data ROM** (top right) are connected by a teal dashed double-headed arrow.\n* **Rx Bridge** connects to **Arbitration** (top) via a teal dashed arrow.\n* **Arbitration** (top) connects to **Servant** (left) via a red dashed arrow.\n* **Arbitration** (top) connects to **Servant** (middle) via a red dashed arrow.\n* **Arbitration** (top) connects to **Client** via a red dashed arrow.\n* **Client** connects back to **Arbitration** (top) via a yellow dashed arrow (far right).\n* **Client** connects to **Arbitration** (bottom) via a yellow dashed arrow.\n* **Transport** connects to **Servant** (left) via a teal dashed arrow labeled **GPIO**.\n* **Servant** (left) connects to **Tx Bridge** via a yellow dashed arrow.\n* **Servant** (middle) connects to **Arbitration** (bottom) via a blue dashed arrow.\n* **Arbitration** (bottom) connects to **Tx Bridge** via a yellow dashed arrow.\n* **Tx Bridge** and **Meta Data ROM** (bottom left) are connected by a blue dashed double-headed arrow.\n* **Tx Bridge** connects to **Transport** via a teal dashed arrow labeled **GIOP Message**.](.spectra-ip-core-orb-datasheet/92936b5d05ab2c3f623c64f642b4e527577681b4212844031b4baefd9384fdc3.jpg) Figure 1 – ICO Architecture # Super Fast Message Processing ICO processes CORBA GIOP messages at hardware speeds which is hundreds of times faster than can be achieved with a conventional software ORB. For example, for a simple interface that supports a two-way synchronous CORBA call and is passed a payload of 1024 bytes as an IN parameter (implemented on a Altera Cyclone III FPGA, clocked at 160MHz), it takes approximately 1.88µS to process the message from the first byte of the incoming message being read by ICO from the transport to the last byte of the reply message being written to the transport by ICO. This represents a data throughput of over 540Mbytes/sec. At higher clock speed and with a more powerful FPGA, for example an Altera Stratix IV, a data throughput rate of over 1Gbyte/sec can be achieved. # Key Features • Supports GIOP version 1.0 protocol • Processes CORBA requests o One way operations o Two way operations • Support for CORBA clients and servers o Servants implemented on FPGA in VHDL o Clients can be internal to the FPGA written in VHDL or external to FPGA (e.g., on a GPP or DSP) implemented by a conventional software application o No arbitrary restriction on the number of clients and servants that can be supported on the FPGA • IDL compiler support o Supports IDL to VHDL language mapping and will auto generate VHDL equivalent of CORBA stubs and skeletons allowing ICO to be easily connected to servants implementing waveform logic Based on CORBA 3 grammar, but only supporting a subset of data types and constructs o Simple data types - Char, Octet, Boolean, Short, Unsigned Short, Long, Unsigned Long, Long Long, Unsigned Long Long, String o Any type (of simple data types) Object type 。 Enumerated types 。 Constructed data types Struct Array o CORBA exceptions support User exceptions o System exceptions Pluggable and open transport interface allows user-defined custom transports to be plugged into ICO • # FPGA Device Coverage Spectra ICO was written in 100% VHDL and was designed to be portable so that a wide range of FPGAs and ASICS can be supported. ICO currently supports the leading FPGA devices from Xilinx and Altera. For the most up to date list of supported FPGAs, please contact ADLINK. # SCA Everywhere Spectra CDB provides the only SCA-compliant CORBA solution that is available across not only GPP, but also DSP and FPGA processing environments. This complete processor coverage has been made possible through the development of specialized CORBA middleware technology designed to support DSPs and FPGAs with Spectra ICO. ADLINK has pioneered the use of lightweight ORB technology for DSPs and advanced hardware ORB technology for FPGAs. The Spectra approach helps decouple SDR applications from the underlying hardware, making hardware upgrades much more straightforward as well as maximizing waveform application portability. # Complementary SDR Products Spectra ICO is part of the most complete family of SDR products and technologies designed to support all of your SCA SDR development needs. # Summary of Spectra ICO Benefits • High performance standards based messaging for FPGAs • Greatly simplifies FPGA application integration • Helps support FPGA application portability • High throughput low latency messaging solution • Helps reduce time to market for new FPGA applications • Low footprint—efficient use of available FPGA resources • Available as part of a complete range of complementary SDR products • Can support a unified messaging protocol across GPP, DSP and FPGA processing elements • Can support a broad range of FPGA devices from the leading vendors • No export restrictions - not subject to International Traffic in Arms Regulations (ITAR) or Joint Tactical Radio System (JTRS) export restrictions # For More Information For further information regarding Spectra ICO or any SDR products, please e-mail: ist\_info@adlinktech.com or visit: ist.adlinktech.com [🔗 Link to the original document](.spectra-ip-core-orb-datasheet/spectra-ip-core-orb-datasheet.pdf)