# EGX-MXM-A4500

NVIDIA Ampere™ GA104 RTX A4500 Embedded Graphics Module

User's Manual

![Close-up of a microprocessor board with integrated circuits and gold contacts (no visible text or symbols)](.0131-egx-mxm-a4500-user-manual/7ed14b23ed29a055dbd6051676be953a8578e9e8dd02c4a5517ce6ddde882c03.jpg)

Manual Rev.: 1.0

Revision Date: Oct. 16, 2022

Part No: 50M-00094-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2022-10-16</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2022 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

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Battery Labels (for products with battery)
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# California Proposition 65 Warning

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WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon featuring horizontal lines, overlaid with a large, bold red checkmark.](.0131-egx-mxm-a4500-user-manual/09175f901a6b5dca5f8391ba3b6da1424b3139d87c0894d56f878c63b3f1151b.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border featuring a large black exclamation point in the center.](.0131-egx-mxm-a4500-user-manual/16dfc54c9488036b98a2888b89beafe6da5f8270c18a42469bc5530833024ea5.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning symbol consisting of a red triangle with rounded corners and a white border. Centered within the red triangle is a large, white exclamation point.](.0131-egx-mxm-a4500-user-manual/e7045fa8cac4677d7e4eeaba29737e97582e5dba78b0575dd6a6310b30c4ab42.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Tables...... vii

# List of Figures ix

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 2
1.3 Specifications.... 3

1.3.1 Graphics Module 3
1.3.2 Display Support and Options....4
1.3.3 Software Support......4
1.3.4 Graphics Options....4

1.4 Functional Block Diagram.... 5
1.5 Mechanical Layout.... 6
1.6 MXM Connector Pin Definitions 9
1.7 Thermal Policy 14
1.8 Unpacking Checklist 15

# 2 System Requirements.... 17

2.1 Power Sequencing.... 17
2.2 Module Power Up and Down 18
2.3 Reset Requirements 18
2.4 System BIOS Settings 19
2.5 Dual Mode DisplayPort Implementation 20
2.6 DVI/HDMI on DisplayPort Interface 21
2.7 Driver Installation 22
2.8 Certifications & Agencies 22

Important Safety Instructions.... 23

Getting Service 25

# List of Tables

Table 1-1: Graphics Module Display Options ....4
Table 1-2: NVIDIA Link Display Types .... 4
Table 1-3: MXM Connector Pin Definitions....9
Table 1-4: Thermal Policy....14

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# List of Figures

Figure 1-1: EGX-MXM-A4500 Functional Block Diagram....5

Figure 1-2: EGX-MXM-A4500 Dimensions 6

Figure 1-3: EGX-MXM-A4500 Top and Side Views....7

Figure 1-4: EGX-MXM-A4500 Bottom View....8

Figure 1-5: MXM Connector....9

Figure 2-1: Power Sequencing 17

Figure 2-2: Module Power Down 18

Figure 2-3: Reset Sequencing 18

Figure 2-4: Sample BIOS Menu Settings....19

Figure 2-5: Dual Mode DisplayPort Implementation ..... 20

Figure 2-6: DVI/HDMI on DisplayPort Interface 21

Figure 2-7: Active IC for HDMI Dongle 22

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# 1 Introduction

# 1.1 Overview

The EGX-MXM-A4500 embedded graphics module features the NVIDIA RTX A4500 embedded GPU based on the advanced NVIDIA Ampere GA104 architecture in MXM 3.1 Type B form factor. The EGX-MXM-A4500 brings a new level of performance to visual graphics and computing applications, fully integrating hardware acceleration for both graphics and computing code, enabling hardware acceleration for a wider class of software applications than ever before.

The EGX-MXM-A4500 is equipped with the latest Ampere GPU architecture using the 7 nanometer (nm) chip process, third generation Tensor Cores with structural sparsity to improve AI performance. It is suitable for embedded, ruggedized, or mobile system designs. With its 5888 CUDA core Ampere GPU and additional 184 Tensors Cores and PCIe Gen4 x16 throughput, the EGX-MXM-A4500 supports 4 FHD displays, delivering the latest leading-edge GPU performance for your embedded system with AI capabilities enabled. Its superior graphics performance, GPU computing and video capabilities are the ideal solution for systems such as digital signage, medical imaging, defense and aerospace applications.

# 1.2 Features

▶ MXM 3.1 Type B FF (82 x 105 mm)
▶ 5888 CUDA cores
▶ 17.66 TFLOPS SP peak performance
▶ 8/16 GB GDDR6 memory
▶ 512 GB/s maximum memory bandwidth
▶ Support for up to 4 DisplayPort 1.4b displays, 80/115W TGP
▶ 5 year performance warranty
▶ NVIDIA RTX A4500 GPU

▷ Package 40 x 40 mm
▷ Base Clock @930 MHz with 115W TGP
▶ Boost Clock @1500 MHz with 115W TGP

# 1.3 Specifications

# 1.3.1 Graphics Module

<table><tr><td colspan="2">Graphics Core</td></tr><tr><td>Architecture</td><td>NVIDIA® Ampere GA104</td></tr><tr><td>GPU</td><td>RTX A4500</td></tr><tr><td>Display Outputs</td><td>4x DisplayPort 1.4.Max. simultaneous display resolution:2x 7680 x 4320 @60Hz4x 5120 x 2880 @ 60Hz4x 4096 x 2160 @ 120Hz</td></tr><tr><td>Signal Interface</td><td>MXM 3.1, PCI Express Gen4 x16 support</td></tr><tr><td colspan="2">GPGPU Computing</td></tr><tr><td>CUDA Support</td><td>5888 CUDA cores, 17.66 TFLOPS SP PeakCUDA Toolkit 8.0, CUDA Compute version 6.1OpenCLTM 1.2, DirectX® 12.1, OpenGL 4.6,Vulcan 1.0 and above</td></tr><tr><td colspan="2">Memory</td></tr><tr><td>GDDR6 Memory</td><td>up to 8GB @12Gbs (6GHz), 16GB @16Gbps (8GHz)</td></tr><tr><td>Configuration</td><td>256Mb x32</td></tr><tr><td>Bandwidth</td><td>256-bit512 GB/s data ratex32 GDDR6 DRAM device data width</td></tr><tr><td colspan="2">Status LED</td></tr><tr><td>Color</td><td>Green: NormalRed: Abnormal</td></tr><tr><td colspan="2">Physical</td></tr><tr><td>Dimensions</td><td>82 (W) x 105 (D) x 4.8 (H) mm</td></tr><tr><td>Locking Mechanism</td><td>Standard MXM 3.1 Type B</td></tr><tr><td colspan="2">Environmental</td></tr><tr><td>Operating Temp.</td><td>Standard: 0 to 55°CExtended: -20°C to 70°C with 80W TGP</td></tr><tr><td>Storage Temp.</td><td>-40°C to 85°C</td></tr><tr><td colspan="2">Operating Systems</td></tr><tr><td>Supported OS</td><td>Windows 10, Windows 11 &amp; Linux Drivers, 64-bit</td></tr></table>

# 1.3.2 Display Support and Options

<table><tr><td>DisplayPort</td><td>▶ 1.2/1.3/1.4▶ Max. pixel clock: 1050 MP/s▶ Max. bandwidth: 25.9 GB/s/connector</td></tr><tr><td>HDMI 2.0</td><td>Max. resolution: 4096 x 2160 at 60 Hz</td></tr><tr><td>HDCP Support</td><td>1.3 (DP), 2.2 (DP, HDMI)</td></tr></table>

# 1.3.3 Software Support

▶ CUDA Toolkit 8.0 and higher
▶ CUDA Compute version 6.1 and higher
▶ OpenCL™ 1.2
▶ DirectX® 12
▶ OpenGL 4.6
▶ Vulcan 1.0

# 1.3.4 Graphics Options

The EGX-MXM-A4500 supports a 4x DisplayPort by default, with five display output options as shown below.

<table><tr><td>MXM port</td><td>DP_A</td><td>DP_B</td><td>DP_C</td><td>DP_D</td><td>LVDS_L</td></tr><tr><td>NVIDIA Link</td><td>Link C</td><td>Link A</td><td>Link E</td><td>Link F</td><td>Link B</td></tr></table>

Table 1-1: Graphics Module Display Options

<table><tr><td>Link</td><td>Display Type</td></tr><tr><td>Link A</td><td>DisplayPort, DVI (Single Link or Dual Link with Link B)</td></tr><tr><td>Link B</td><td>DisplayPort, DVI (Dual Link with A)</td></tr><tr><td>Link C</td><td>DisplayPort, HDMI</td></tr><tr><td>Link D</td><td>Not supported</td></tr><tr><td>Link E</td><td>DisplayPort, HDMI</td></tr><tr><td>Link F</td><td>DisplayPort</td></tr></table>

Table 1-2: NVIDIA Link Display Types

# 1.4 Functional Block Diagram

![The diagram illustrates the connectivity of a central module labeled **EN20-E3_115W and 80W** (Middle Block) with an interface connector (**MxM 3.1 Connector**, Left Block) and various external components (**Right Side**).\n\n**Labeled Blocks:**\n*   **Left Block:** A vertical rectangle labeled **MxM 3.1 Connector**.\n*   **Middle Block:** A vertical rectangle labeled **EN20-E3_115W and 80W**. Inside, it contains labels for various interfaces: **PCIe**, **IFPA**, **IFPB**, **IFPC**, **IFPE**, **IFPF**, **PM**, **I2CS**, **JTAG**, and **SPI**.\n*   **Right Side Components:**\n    *   **8GB/16GB GDDR6** (with subtext **256b, 256Mx16**)\n    *   **Power Supply NVDD-PH1 NVDD-PH5 NVDD-PH2 NVDD-PH6 NVDD-PH3 NVDD-PH7 NVDD-PH4 NVDD-PH8**\n    *   **Power Supply FBVDD-PH1-3**\n    *   **Power Supply PEX_VDD**\n    *   **Power Supply VDD_18A**\n    *   **Power Supply NV3V3**\n*   **Small Box:** **SPI - VBIOS** (located near the bottom left).\n\n**Connections:**\n*   **PCIe:** An arrow labeled **PCIe x16 Gen4** connects **PCIe** (Middle) to **PCIe x16 Gen4** (Left).\n*   **Display Interfaces:** Five arrows labeled **DP1.4** connect the Middle block to the Left block:\n    *   **IFPA** to **DP_B**\n    *   **IFPB** to **LVDS_L**\n    *   **IFPC** to **DP_A**\n    *   **IFPE** to **DP_C**\n    *   **IFPF** to **DP_D**\n*   **Power & Management:**\n    *   An arrow labeled **Power Management (PWR EN, PWR GOOD, WAKE#)** connects **PM** (Middle) to the Left edge.\n    *   An arrow connects **I2CS** (Middle) to the Left edge.\n    *   An arrow connects **JTAG** (Middle) to the Left edge.\n*   **SPI:** A bidirectional connection labeled **SPI** connects **SPI** (Middle) to the **SPI - VBIOS** box.\n*   **GDDR6:** An arrow labeled **GDDR6** connects **GDDR6** (Middle) to the **8GB/16GB GDDR6** box.\n*   **Power Inputs:** Five arrows point from the Right-side Power Supply boxes into the Middle block (from **NVDD...**, **FBVDD...**, **PEX_VDD**, **VDD_18A**, and **NV3V3**).](.0131-egx-mxm-a4500-user-manual/aea10b1cc6d5d0d23f9a4fba3400b5fbcf394d29398de269716fbf94182970c2.jpg)

Figure 1-1: EGX-MXM-A4500 Functional Block Diagram

# 1.5 Mechanical Layout

![The image displays an icon of a white document with a folded top-right corner and faint horizontal lines running across it. A large, bold red checkmark is drawn diagonally over the document.](.0131-egx-mxm-a4500-user-manual/1788c34aec9ca144d668962597edbd5d47ad39dcfeb7d1dd5832ee306452eaea.jpg)
NOTE:

All dimensions shown are in mm

![82\n105](.0131-egx-mxm-a4500-user-manual/f22771f513c1822a4737cd0bdf1a9cfc2bcc406c9a6207c232371c5c64e7e345.jpg)

Figure 1-2: EGX-MXM-A4500 Dimensions

![0\n11.85\n17.20\n30.63\n34.85\n44.12\n57.85\n75\n4.30\n0\nB\nC\nC\nB\n0\n8.25\n21.34\n31.25\n34.93\nC\nC\n17.79\n31.26\n44.71\n54.25\n0.85\n2x4.82\n2xR0.50\n135x0.35\n3.10\n0.50\n39\n37.50\nD\n34.49\n39.51\n1.45MIN](.0131-egx-mxm-a4500-user-manual/79796eda9f73ceaa1f892df76ee94769368ceff0853054e7e5f5fa758a258b20.jpg)

![The image displays a technical drawing of a circle with a horizontal line passing through its center. Two diagonal lines intersect at the center of the circle. On the upper left, the text 'ø 3.20' is shown above a diagonal line with an arrow pointing towards the circle. On the upper right, the text 'ø 8' is shown above a diagonal line with an arrow pointing towards the circle.](.0131-egx-mxm-a4500-user-manual/202f5cfc41d78980c1806598ee81d114f5ea352c357fb991aaf150209e2208de.jpg)
B-Section
Scale 2 : 1

![The image displays a technical drawing of three concentric circles centered around a point. Two dimension lines indicate diameters. One dimension line, labeled 'Ø 6', extends from the top left and points to the outermost circle with an arrowhead. Another dimension line, labeled 'Ø 3.20', extends from the top right and points to the middle circle with an arrowhead.](.0131-egx-mxm-a4500-user-manual/44cd2321d7456de69fc3604bd58c2158dfdd59a5dc9f193bfab6ada9da5a4c71.jpg)
C-Section
Scale 2 : 1
PTH HOLE
2 PCS
PTH HOLE
4 PCS

![1.20\n2.90\n0.85\nA](.0131-egx-mxm-a4500-user-manual/832d22ffa27f4cd45102ab4259a6c62220b7f6a2ba9ab9911a3ad0fc10180d81.jpg)

![45°\n0.18](.0131-egx-mxm-a4500-user-manual/495261ca9c811e6fa485d7ad16ff7c5f2497a772d1000da017dd470329533804.jpg)

A-Section Scale 2:1

TOP SIDE: OD=6.0mm; ID=3.2mm
BOTTOM SIDE: OD=7.0mm; ID=3.2mm
![1.25\n0.50\n1.25\n0.50\n3.75MIN\n1 ±0.05](.0131-egx-mxm-a4500-user-manual/3a0ae2abc5bd23b9acb6d1d17649288026fe7a5f469c99c2a50ed09a14b520a4.jpg)

D-Section Scale 2:1

![1\n0.50\n1\n0.50](.0131-egx-mxm-a4500-user-manual/d8b49b7266c652fe98cc4c386aa8bf01f47111147e63fb18fabd5545ca22b782.jpg)

E-Section Scale 2 : 1
Figure 1-3: EGX-MXM-A4500 Top and Side Views

![0\nB\nC\nC\nB\n3.10\n129x0.35\nE\n39.76\n34.74\n31\n28.75\n2x4.82\n2.35\n1.85](.0131-egx-mxm-a4500-user-manual/2ef049d5fe7f4f9e6eb76b40d05ff3f7ccf915c6246b4db20c8c8adf848cc6be.jpg)

Figure 1-4: EGX-MXM-A4500 Bottom View

# 1.6 MXM Connector Pin Definitions

![Pin 281\nPin 125\nPin 133\n(R G5 X G6)\nPin E1\nPin E3\nPin 134\nPin 124\nPin E2\nPin E4](.0131-egx-mxm-a4500-user-manual/b9f4c6f5c6bd23dc5faf5baf8510c5f520c262184968df1fb47a9dddbf039feb.jpg)

Figure 1-5: MXM Connector

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>E1</td><td>PWR_SRC</td><td></td><td>E2</td><td>PWR_SRC</td><td></td></tr><tr><td>E3</td><td>GND</td><td></td><td>E4</td><td>GND</td><td></td></tr><tr><td>1</td><td>5V</td><td></td><td>2</td><td>PRSNT_R#</td><td>0ohm PD</td></tr><tr><td>3</td><td>5V</td><td></td><td>4</td><td>RSVD</td><td></td></tr><tr><td>5</td><td>5V</td><td></td><td>6</td><td>PWR_GOOD</td><td></td></tr><tr><td>7</td><td>5V</td><td></td><td>8</td><td>PWR_EN</td><td></td></tr><tr><td>9</td><td>5V</td><td></td><td>10</td><td>27MHZ_REF</td><td></td></tr><tr><td>11</td><td>GND</td><td></td><td>12</td><td>GND</td><td></td></tr><tr><td>13</td><td>GND</td><td></td><td>14</td><td>RSVD</td><td></td></tr><tr><td>15</td><td>GND</td><td></td><td>16</td><td>RSVD</td><td></td></tr><tr><td>17</td><td>GND</td><td></td><td>18</td><td>PWR_LEVEL</td><td>100K PU to 3.3V</td></tr><tr><td>19</td><td>RSVD</td><td></td><td>20</td><td>TH_OVERT#</td><td>100K PU to 3.3V</td></tr><tr><td>21</td><td>RSVD</td><td></td><td>22</td><td>TH_ALERT#</td><td>100K PU to 3.3V</td></tr><tr><td>23</td><td>RSVD</td><td></td><td>24</td><td>RSVD</td><td></td></tr><tr><td>25</td><td>RSVD</td><td></td><td>26</td><td>RSVD</td><td></td></tr><tr><td>27</td><td>RSVD</td><td></td><td>28</td><td>RSVD</td><td></td></tr><tr><td>29</td><td>RSVD</td><td></td><td>30</td><td>RSVD</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>31</td><td>RSVD</td><td></td><td>32</td><td>SMB_DAT</td><td>100K PU to 3.3V</td></tr><tr><td>33</td><td>RSVD</td><td></td><td>34</td><td>SMB_CLK</td><td>100K PU to 3.3V</td></tr><tr><td>35</td><td>RSVD</td><td></td><td>36</td><td>GND</td><td></td></tr><tr><td>37</td><td>GND</td><td></td><td>38</td><td>RSVD</td><td></td></tr><tr><td>39</td><td>RSVD</td><td></td><td>40</td><td>RSVD</td><td></td></tr><tr><td>41</td><td>RSVD</td><td></td><td>42</td><td>RSVD</td><td></td></tr><tr><td>43</td><td>RSVD</td><td></td><td>44</td><td>RSVD</td><td></td></tr><tr><td>45</td><td>RSVD</td><td></td><td>46</td><td>GND</td><td></td></tr><tr><td>47</td><td>GND</td><td></td><td>48</td><td>PEX_TX15#</td><td></td></tr><tr><td>49</td><td>PEX_RX15#</td><td></td><td>50</td><td>PEX_TX15</td><td></td></tr><tr><td>51</td><td>PEX_RX15</td><td></td><td>52</td><td>GND</td><td></td></tr><tr><td>53</td><td>GND</td><td></td><td>54</td><td>PEX_TX14#</td><td></td></tr><tr><td>55</td><td>PEX_RX14#</td><td></td><td>56</td><td>PEX_TX14</td><td></td></tr><tr><td>57</td><td>PEX_RX14</td><td></td><td>58</td><td>GND</td><td></td></tr><tr><td>59</td><td>GND</td><td></td><td>60</td><td>PEX_TX13#</td><td></td></tr><tr><td>61</td><td>PEX_RX13#</td><td></td><td>62</td><td>PEX_TX13</td><td></td></tr><tr><td>63</td><td>PEX_RX13</td><td></td><td>64</td><td>GND</td><td></td></tr><tr><td>65</td><td>GND</td><td></td><td>66</td><td>PEX_TX12#</td><td></td></tr><tr><td>67</td><td>PEX_RX12#</td><td></td><td>68</td><td>PEX_TX12</td><td></td></tr><tr><td>69</td><td>PEX_RX12</td><td></td><td>70</td><td>GND</td><td></td></tr><tr><td>71</td><td>GND</td><td></td><td>72</td><td>PEX_TX11#</td><td></td></tr><tr><td>73</td><td>PEX_RX11#</td><td></td><td>74</td><td>PEX_TX11</td><td></td></tr><tr><td>75</td><td>PEX_RX11</td><td></td><td>76</td><td>GND</td><td></td></tr><tr><td>77</td><td>GND</td><td></td><td>78</td><td>PEX_TX10#</td><td></td></tr><tr><td>79</td><td>PEX_RX10#</td><td></td><td>80</td><td>PEX_TX10</td><td></td></tr><tr><td>81</td><td>PEX_RX10</td><td></td><td>82</td><td>GND</td><td></td></tr><tr><td>83</td><td>GND</td><td></td><td>84</td><td>PEX_TX9#</td><td></td></tr><tr><td>85</td><td>PEX_RX9#</td><td></td><td>86</td><td>PEX_TX9</td><td></td></tr><tr><td>87</td><td>PEX_RX9</td><td></td><td>88</td><td>GND</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>89</td><td>GND</td><td></td><td>90</td><td>PEX_TX8#</td><td></td></tr><tr><td>91</td><td>PEX_RX8#</td><td></td><td>92</td><td>PEX_TX8</td><td></td></tr><tr><td>93</td><td>PEX_RX8</td><td></td><td>94</td><td>GND</td><td></td></tr><tr><td>95</td><td>GND</td><td></td><td>96</td><td>PEX_TX7#</td><td></td></tr><tr><td>97</td><td>PEX_RX7#</td><td></td><td>98</td><td>PEX_TX7</td><td></td></tr><tr><td>99</td><td>PEX_RX7</td><td></td><td>100</td><td>GND</td><td></td></tr><tr><td>101</td><td>GND</td><td></td><td>102</td><td>PEX_TX6#</td><td></td></tr><tr><td>103</td><td>PEX_RX6#</td><td></td><td>104</td><td>PEX_TX6</td><td></td></tr><tr><td>105</td><td>PEX_RX6</td><td></td><td>106</td><td>GND</td><td></td></tr><tr><td>107</td><td>GND</td><td></td><td>108</td><td>PEX_TX5#</td><td></td></tr><tr><td>109</td><td>PEX_RX5#</td><td></td><td>110</td><td>PEX_TX5</td><td></td></tr><tr><td>111</td><td>PEX_RX5</td><td></td><td>112</td><td>GND</td><td></td></tr><tr><td>113</td><td>GND</td><td></td><td>114</td><td>PEX_TX4#</td><td></td></tr><tr><td>115</td><td>PEX_RX4#</td><td></td><td>116</td><td>PEX_TX4</td><td></td></tr><tr><td>117</td><td>PEX_RX4</td><td></td><td>118</td><td>GND</td><td></td></tr><tr><td>119</td><td>GND</td><td></td><td>120</td><td>PEX_TX3#</td><td></td></tr><tr><td>121</td><td>PEX_RX3#</td><td></td><td>122</td><td>PEX_TX3</td><td></td></tr><tr><td>123</td><td>PEX_RX3</td><td></td><td>124</td><td>GND</td><td></td></tr><tr><td>125</td><td>GND</td><td></td><td>126</td><td>KEY</td><td></td></tr><tr><td>127</td><td>KEY</td><td></td><td>128</td><td>KEY</td><td></td></tr><tr><td>129</td><td>KEY</td><td></td><td>130</td><td>KEY</td><td></td></tr><tr><td>131</td><td>KEY</td><td></td><td>132</td><td>KEY</td><td></td></tr><tr><td>133</td><td>GND</td><td></td><td>134</td><td>GND</td><td></td></tr><tr><td>135</td><td>PEX_RX2#</td><td></td><td>136</td><td>PEX_TX2#</td><td></td></tr><tr><td>137</td><td>PEX_RX2</td><td></td><td>138</td><td>PEX_TX2</td><td></td></tr><tr><td>139</td><td>GND</td><td></td><td>140</td><td>GND</td><td></td></tr><tr><td>141</td><td>PEX_RX1#</td><td></td><td>142</td><td>PEX_TX1#</td><td></td></tr><tr><td>143</td><td>PEX_RX1</td><td></td><td>144</td><td>PEX_TX1</td><td></td></tr><tr><td>145</td><td>GND</td><td></td><td>146</td><td>GND</td><td></td></tr><tr><td>147</td><td>PEX_RX0#</td><td></td><td>148</td><td>PEX_TX0#</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>149</td><td>PEX_RX0</td><td></td><td>150</td><td>PEX_TX0</td><td></td></tr><tr><td>151</td><td>GND</td><td></td><td>152</td><td>GND</td><td></td></tr><tr><td>153</td><td>PEX_REFCLK#</td><td></td><td>154</td><td>PEX_CLK_REQ#</td><td></td></tr><tr><td>155</td><td>PEX_REFCLK</td><td></td><td>156</td><td>PEX_RST#</td><td></td></tr><tr><td>157</td><td>GND</td><td></td><td>158</td><td>RSVD</td><td></td></tr><tr><td>159</td><td>RSVD</td><td></td><td>160</td><td>RSVD</td><td></td></tr><tr><td>161</td><td>RSVD</td><td></td><td>162</td><td>RSVD</td><td></td></tr><tr><td>163</td><td>RSVD</td><td></td><td>164</td><td>RSVD</td><td></td></tr><tr><td>165</td><td>RSVD</td><td></td><td>166</td><td>GND</td><td></td></tr><tr><td>167</td><td>RSVD</td><td></td><td>168</td><td>RSVD</td><td></td></tr><tr><td>169</td><td>RSVD</td><td></td><td>170</td><td>RSVD</td><td></td></tr><tr><td>171</td><td>RSVD</td><td></td><td>172</td><td>RSVD</td><td></td></tr><tr><td>173</td><td>GND</td><td></td><td>174</td><td>GND</td><td></td></tr><tr><td>175</td><td>RSVD</td><td></td><td>176</td><td>RSVD</td><td></td></tr><tr><td>177</td><td>RSVD</td><td></td><td>178</td><td>RSVD</td><td></td></tr><tr><td>179</td><td>GND</td><td></td><td>180</td><td>GND</td><td></td></tr><tr><td>181</td><td>RSVD</td><td></td><td>182</td><td>RSVD</td><td></td></tr><tr><td>183</td><td>RSVD</td><td></td><td>184</td><td>RSVD</td><td></td></tr><tr><td>185</td><td>GND</td><td></td><td>186</td><td>GND</td><td></td></tr><tr><td>187</td><td>RSVD</td><td></td><td>188</td><td>RSVD</td><td></td></tr><tr><td>189</td><td>RSVD</td><td></td><td>190</td><td>RSVD</td><td></td></tr><tr><td>191</td><td>GND</td><td></td><td>192</td><td>GND</td><td></td></tr><tr><td>193</td><td>RSVD</td><td></td><td>194</td><td>RSVD</td><td></td></tr><tr><td>195</td><td>RSVD</td><td></td><td>196</td><td>RSVD</td><td></td></tr><tr><td>197</td><td>GND</td><td></td><td>198</td><td>GND</td><td></td></tr><tr><td>199</td><td>DP_C_L0#</td><td></td><td>200</td><td>RSVD</td><td></td></tr><tr><td>201</td><td>DP_C_L0</td><td></td><td>202</td><td>RSVD</td><td></td></tr><tr><td>203</td><td>GND</td><td></td><td>204</td><td>GND</td><td></td></tr><tr><td>205</td><td>DP_C_L1#</td><td></td><td>206</td><td>DP_D_L0#</td><td></td></tr><tr><td>207</td><td>DP_C_L1</td><td></td><td>208</td><td>DP_D_L0</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>209</td><td>GND</td><td></td><td>210</td><td>GND</td><td></td></tr><tr><td>211</td><td>DP_C_L2#</td><td></td><td>212</td><td>DP_D_L1#</td><td></td></tr><tr><td>213</td><td>DP_C_L2</td><td></td><td>214</td><td>DP_D_L1</td><td></td></tr><tr><td>215</td><td>GND</td><td></td><td>216</td><td>GND</td><td></td></tr><tr><td>217</td><td>DP_C_L3#</td><td></td><td>218</td><td>DP_D_L2#</td><td></td></tr><tr><td>219</td><td>DP_C_L3</td><td></td><td>220</td><td>DP_D_L2</td><td></td></tr><tr><td>221</td><td>GND</td><td></td><td>222</td><td>GND</td><td></td></tr><tr><td>223</td><td>DP_C_AUX#</td><td></td><td>224</td><td>DP_D_L3#</td><td></td></tr><tr><td>225</td><td>DP_C_AUX</td><td></td><td>226</td><td>DP_D_L3</td><td></td></tr><tr><td>227</td><td>RSVD</td><td></td><td>228</td><td>GND</td><td></td></tr><tr><td>229</td><td>RSVD</td><td></td><td>230</td><td>DP_D_AUX#</td><td></td></tr><tr><td>231</td><td>RSVD</td><td></td><td>232</td><td>DP_D_AUX</td><td></td></tr><tr><td>233</td><td>RSVD</td><td></td><td>234</td><td>DP_C_HPD</td><td>PD 100K</td></tr><tr><td>235</td><td>RSVD</td><td></td><td>236</td><td>DP_D_HPD</td><td>PD 100K</td></tr><tr><td>237</td><td>RSVD</td><td></td><td>238</td><td>RSVD</td><td></td></tr><tr><td>239</td><td>RSVD</td><td></td><td>240</td><td>3V3</td><td></td></tr><tr><td>241</td><td>RSVD</td><td></td><td>242</td><td>3V3</td><td></td></tr><tr><td>243</td><td>RSVD</td><td></td><td>244</td><td>GND</td><td></td></tr><tr><td>245</td><td>RSVD</td><td></td><td>246</td><td>DP_B_L0#</td><td></td></tr><tr><td>247</td><td>RSVD</td><td></td><td>248</td><td>DP_B_L0</td><td></td></tr><tr><td>249</td><td>RSVD</td><td></td><td>250</td><td>GND</td><td></td></tr><tr><td>251</td><td>GND</td><td></td><td>252</td><td>DP_B_L1#</td><td></td></tr><tr><td>253</td><td>DP_A_L0#</td><td></td><td>254</td><td>DP_B_L1</td><td></td></tr><tr><td>255</td><td>DP_A_L0</td><td></td><td>256</td><td>GND</td><td></td></tr><tr><td>257</td><td>GND</td><td></td><td>258</td><td>DP_B_L2#</td><td></td></tr><tr><td>259</td><td>DP_A_L1#</td><td></td><td>260</td><td>DP_B_L2</td><td></td></tr><tr><td>261</td><td>DP_A_L1</td><td></td><td>262</td><td>GND</td><td></td></tr><tr><td>263</td><td>GND</td><td></td><td>264</td><td>DP_B_L3#</td><td></td></tr><tr><td>265</td><td>DP_A_L2#</td><td></td><td>266</td><td>DP_B_L3</td><td></td></tr><tr><td>267</td><td>DP_A_L2</td><td></td><td>268</td><td>GND</td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

<table><tr><td colspan="3">Primary Side (bottom side)</td><td colspan="3">Secondary Side (top side)</td></tr><tr><td>Pin</td><td>Signal</td><td>PU/PD</td><td>Pin</td><td>Signal</td><td>PU/PD</td></tr><tr><td>269</td><td>GND</td><td></td><td>270</td><td>DP_B_AUX#</td><td></td></tr><tr><td>271</td><td>DP_A_L3#</td><td></td><td>272</td><td>DP_B_AUX</td><td></td></tr><tr><td>273</td><td>DP_A_L3</td><td></td><td>274</td><td>DP_B_HPD</td><td>PD 100K</td></tr><tr><td>275</td><td>GND</td><td></td><td>276</td><td>DP_A_HPD</td><td>PD 100K</td></tr><tr><td>277</td><td>DP_A_AUX#</td><td></td><td>278</td><td>3V3</td><td></td></tr><tr><td>279</td><td>DP_A_AUX</td><td></td><td>280</td><td>3V3</td><td></td></tr><tr><td>281</td><td>PRSNT_L#</td><td>0 ohm PD</td><td></td><td></td><td></td></tr></table>

Table 1-3: MXM Connector Pin Definitions

# 1.7 Thermal Policy

The GPU core clock throttles at temperatures ( $T_{J}$ ) past the thresholds shown with the behaviors as listed. Thermal throttling ensures that the highest temperature on the die does not exceed the sense temperature for prolonged periods of time.

<table><tr><td>Parameter</td><td>Value</td><td>Units</td></tr><tr><td>Thermal Resistance (Junction to Case, RJC)</td><td>0.0196</td><td>°C/W</td></tr><tr><td>Thermal Resistance (Junction to PCB Board, RJB)</td><td>1.437</td><td>°C/W</td></tr><tr><td>GPU Maximum Operating Temperature1</td><td>89</td><td>°C</td></tr><tr><td>GPU Slowdown Temperature (THERM_ALERT)2</td><td>98</td><td>°C</td></tr><tr><td>GPU Shutdown Temperature (OVERT)3</td><td>100</td><td>°C</td></tr></table>

Table 1-4: Thermal Policy

![The image features a white document icon with a folded top-left corner. Horizontal gray lines run across the lower section. A large, bold red checkmark is superimposed diagonally over the page.](.0131-egx-mxm-a4500-user-manual/f8c9e9179322d91649d6577590867e295761635d2d2af5dbc0c5a48da9e76d82.jpg)
NOTE:

▶ Max.GPU operating temperature is the maximum at which the GPU is guaranteed to operate at target performance (base clock) under total board power level
▶ THERM\_ALERT generates a 50% (÷2) hardware clock slowdown.
▶ OVERT generates a 87.5% (÷8) hardware clock slowdown

# 1.8 Unpacking Checklist

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

▶ EGX-MXM-A4500 embedded graphics module

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# 2 System Requirements

# 2.1 Power Sequencing

For initial power on, or to Resume from S3 and S4, this sequence must be followed.

![| Module             | Time (ms) |\n| ------------------ | --------- |\n| PWR_SRC            | ≥0        |\n| 5V                 | ≤90       |\n| 3V3                | ≤90       |\n| PWR_EN             | ≤90       |\n| Module Internal Power | ≤90       |\n| PWR_GOOD           | ≤90       |](.0131-egx-mxm-a4500-user-manual/9bebb4f805c26f943c2aa821e02a164105cfc38e25520a33bc6c4be9d27727b9.jpg)

Figure 2-1: Power Sequencing

# 2.2 Module Power Up and Down

Issuing the PWR\_EN signal powers the MXM module down, and the system designer can decide whether to keep the module input power when the MXM module is powered down.

![| Signal Type           | Value |\n|-----------------------|-------|\n| INPUT POWER           | High  |\n| PWR_EN                | Low   |\n| MODULE INTERNAL POWER | Medium|\n| PWR_GOOD              | Low   |](.0131-egx-mxm-a4500-user-manual/368e129e86ff6388f922f7145df85f423045faca0bb66adc411a9107fa6b7e6c.jpg)

Figure 2-2: Module Power Down

# 2.3 Reset Requirements

![| Signal          | Duration (ms) |\n|-----------------|---------------|\n| T_PVPERL        | ≥100          |\n| T_PERST-PG      | ≥100          |\n| T_PERST-CLK     | ≥200          |\n| T_FAIL          | ≤500          |](.0131-egx-mxm-a4500-user-manual/7ce16d8c4d9a41fc9af1043eeb6ab14db2bf0af6008a78bd14e5969d63fa36e4.jpg)

Figure 2-3: Reset Sequencing

# 2.4 System BIOS Settings

The system BIOS must meet the following criteria:

▶ SBIOS must support the "Above 4G decoding" feature to support a resizable BAR1 size.
▶ SBIOS must enable "Above 4G decoding" as the default configuration.

The following is a sample BIOS menu setting for reference. The actual menu setting can vary depending on the specific SBIOS design.

![Aptio Setup Utility - Copyright (C) 2022 American Megatrends, Inc.\nChipset\nSystem Agent (SA) Configuration\nSA PCIe Code Version 7.0.108.64\nVT-d Supported\n► Memory Configuration\n► Graphics Configuration\n► PEG Port Configuration\nVT-d (Enabled)\nAbove 4GB MMIO BIOS (Enabled)\nassignment\nEnable/Disable above\n4GB MemoryMappedIO BIOS\nassignment\nThis is enabled\nautomatically when\nAperture Size is set to\n2048MB.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF8: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nVersion 2.20.1275. Copyright (C) 2022 American Megatrends, Inc.](.0131-egx-mxm-a4500-user-manual/141b19f0030aa260a6f41c6b00544120fac6097161ce672601d604b5ff7c9707.jpg)

![Aptio Setup Utility - Copyright (C) 2022 American Megatrends, Inc.\nChipset\nSystem Agent (SA) Configuration\nSA PCIe Code Version 7.0.108.64\nVT-d Supported\n► Memory Configuration\n► Graphics Configuration\n► PEG Port Configu ABoxe 4GB MMIO BIOS assignment —\nVT-d\nAbove 4GB MMIO B\nassignment\nEnabled\nDisabled\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF8: Previous Values\nF9: Optimized Defaults\nF10: Save & Exit\nESC: Exit\nEnable/Disable above\n4GB MemoryMappedIO BIOS\nassignment\nThis is enabled\nautomatically when\nAperture Size is set to\n2048MB.\nAct Screen\nAct Item\nVersion 2.20.1275. Copyright (C) 2022 American Megatrends, Inc.](.0131-egx-mxm-a4500-user-manual/e3224aa8c5bba2ce30eade25384dca0976adf5d13648c3a022e55a978f194d8e.jpg)

Figure 2-4: Sample BIOS Menu Settings

# 2.5 Dual Mode DisplayPort Implementation

The EGX-MXM-A4500 supports four dual mode DisplayPorts by default. HDMI can be supported via dongle (see “Display Support and Options” on page 4). The system requires a switch circuit to determine whether the AUX or DDC signal is output from the MXM module, and AC coupling capacitors should be placed on the system board.

![This diagram illustrates the signal routing between an **MXM Connector** (left) and a **DisplayPort Connector** (right).\n\n**Top Section:**\n*   Two lines labeled **AUX_N/DDC_DAT** and **AUX_P/DDC_CLK** connect the two connectors.\n*   These lines pass through a rectangular box containing two switches.\n*   To the right of the switches, the **AUX_N/DDC_DAT** line connects to a resistor leading to **3.3V**.\n*   The **AUX_P/DDC_CLK** line connects to a resistor leading to ground.\n*   Below the switch box is the label **CONFIG1 (CABLE ADAPTOR DETECT)**.\n\n**Middle Section:**\n*   A single line runs horizontally through a box labeled **Hot Plug Detect**.\n\n**Bottom Section:**\n*   Two lines labeled **DP_x_Lx_P** and **DP_x_Lx_N** connect the two connectors.\n*   These lines pass through capacitors (represented by parallel plates) located towards the right side of the diagram.](.0131-egx-mxm-a4500-user-manual/f86d34a7bbbd3c70993c66ed092910d9ef5af82f2ac6adbc39acfa098cc374a0.jpg)

Figure 2-5: Dual Mode DisplayPort Implementation

# 2.6 DVI/HDMI on DisplayPort Interface

DVI and HDMI connectors can both be implemented through the DisplayPort interface. To support HDMI display from MXM, the HDMI port needs to be routed from DP\_C and/or DP\_A. To support DVI from MXM, the DVI port needs to be routed from DP\_B and/or LVDS\_L. Dual Link DVI must use DP\_B and LVDS\_L together (see "Graphics Options" on page 4). Circuits required on the system board are as shown. 499Ω with 1% pulldown resistors to the ground on the DP lanes must placed on the DVI/HDMI connector side of the AC coupling, gated by a MOSFET to limit leakage.

![3.3V 3.3V\nHot Plug Detect\nMXM Connector\nAUX_N/DDC_DAT\nAUX_P/DDC_CLK\nLevel Shifter\nDVI/HDMI Connector\nDP_x_Lx_P\nDP_x_Lx_N\n499Ω 1%\n499Ω 1%\nPWR_EN](.0131-egx-mxm-a4500-user-manual/f10b394b035cbadf51d6c73b9aa1787932d98c6f8c5acb31e3d642faa3c8b00e.jpg)

Figure 2-6: DVI/HDMI on DisplayPort Interface

For resolutions higher than 1080P, contact an ADLINK FAE for customized service, or use an active IC for the circuit design.

![MXM Connector\nAUX_P\n100K\nAUX_N\n100K\n3V3\nDP_x_Lx_P\nDP_x_Lx_N\nHot Plug DET\nDP to HDMI Dongle\nDDC_CLK\nDDC_DAT\nHDMI_TX_xP\nHDMI_TX_xN\nHot Plug DET\n100K\nNI\n5V 5V\nHDMI Connector\nNI is Reserve](.0131-egx-mxm-a4500-user-manual/9d894272559e680beaffcc3c232487019ae96751fba2f00af9bc3f9d48c25daa.jpg)

Figure 2-7: Active IC for HDMI Dongle

# 2.7 Driver Installation

Drivers can be downloaded from:

https://www.adlinktech.com/Products/Embedded\_Graphics/embedded-graphics-solutions/EGX-MXM-A4500

# 2.8 Certifications & Agencies

▶ Windows Hardware Quality Lab (WHQL) certified for Windows 10 and Windows 11
▶ EU Reduction of Hazardous Substances (EU-RoHS)
▶ Conformité Européenne (CE)
▶ Federal Communications Commission (FCC)

# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing:
▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power
▶ To avoid electrical shock and/or damage to device:
▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover-ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▶ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up
It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required
▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

<table><tr><td>&lt;img src="images/f071809a6279cab0ce9c02a8dc6b94c4cf7337ab43c0a6defa912c5731f8b2c7.jpg"/&gt;</td><td>BURN HAZARDTouching this surface could result in bodily injury.To reduce risk, allow the surface to cool before touching.RISQUE DE BRÛLURESNe touchez pas cette surface, cela pourrait entraîner des blessures.Pour éviter tout danger, laissez la surface refroidir avant de la toucher.</td></tr></table>

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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