# IMB-C47

# User’s Manual

ATX Motherboard with 12th/13th/14th Gen Intel® Core™ i9/i7/i5/i3 Processors and Intel® Q670 Chipset

![Close-up of a computer motherboard with various electronic components and connectors (no readable text or symbols)](.20260410-47de19e6-512/f302e92e37c8ac2def07b903502345b1be7843d0c12cb39dbd86274b3e1342e6.jpg)

Manual Rev.: 0.3 Preliminary

Revision Date: October 11, 2024

Part Number: 50M-13019-1000

# Preface

# Copyright

Copyright 2024 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines and a solid rectangle below (no text or labels)](.20260410-47de19e6-512/925c65cacd0fce3a3d782d81ec399934901b4b2236a9c54b534272ebd9a9c16a.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.20260410-47de19e6-512/a9c6e2a31cfb78ed86af9c159354492f1e6e6e8ed9d6e4cdaf7e4bc4fee913be.jpg)

![The image features a black outline of a square containing the standard recycling symbol (three chasing arrows forming a triangle). Directly below the square, the text 'Li-ion' is written in bold, black sans-serif font.](.20260410-47de19e6-512/11425fb80e88b7a51baa120ce2f34ffbd8e3ab1f75f827a66395a2dab78f783f.jpg)

![RECYCLF\nRBRC\nLi-ion\n1.800.822.8837](.20260410-47de19e6-512/b4856cf48a65347027ddfb74c6dd4627ca536b3cc350e613b9b57b8a0ded8880.jpg)

![廢電池請回收](.20260410-47de19e6-512/0ff8f4ca46132f308a86d88ebff050da44de84e2ae059cd2e98d9db81dc8f0ab.jpg)

# California Proposition 65 Warning

![This image shows a standard warning sign: a yellow triangle with a thick black border containing a black exclamation point in the center.](.20260410-47de19e6-512/7c363382f3427b571e02d9812f935e546001e575dbce825ffdd5ceb798759885.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2024-09-23</td><td>AL</td></tr><tr><td>0.2</td><td>Specifications and connector pinouts updated</td><td>2024-10-04</td><td>AL</td></tr><tr><td>0.3</td><td>Connector pinouts updated</td><td>2024-10-11</td><td>AL</td></tr></table>

# Table of Contents

# Preface ...

# List of Figures .... ..vi

# List of Tables ...... ..vi

# 1 Introduction....

1.1 Packing List ..
1.2 Optional Accessories .

# 2 Specifications ....

2.1 Core System.. .3
2.2 I/O Interface .. 4
2.3 Video.. .4
2.4 Audio.. .5
2.5 LAN.. .5
2.6 Temperatures . .5
2.7 Humidity... .5
2.8 Certificate (EMC) .. .5
2.9 Form Factor .. .5
2.10 Operating Systems .. .5
2.11 Functional Block Diagram. .6

# 3 Mechanical Layout ..

3.1 IO Panel Connector Locations.
3.2 Mechanical Dimensions. .11

# 4 Connector Pinouts .. .13

4.1 Rear IO Connectors.. .13
4.2 Onboard Headers / Connectors.. .15
4.3 Jumper and Switch Settings . .21
4.4 Expansion Slots .. .. 26

# 5 Driver Installation .............. .29

# 6 BIOS Setup........... .31

6.1 Menu Structure . .31
6.2 Main Menu. .32
6.3 Advanced..
6.4 Chipset.. .. 36
6.5 Security.. .38
6.6 Boot .. ..39

6.7 Save & Exit . .. 40

Safety Instructions.... .41

Getting Services... .42

# List of Figures

Figure 1: Functional Block Diagram . .6

Figure 2: IO Panel Connector Locations .

Figure 3: Onboard Connector – Header and Jumper Locations . .8

Figure 4: Mechanical Dimensions .. ...11

Figure 5: Mechanical Dimensions - IO Panel.. ..11

# List of Tables

Table 1: IO Panel Connector Definitions.

Table 2: Onboard Connector – Header and Jumper Definitions.. .9

# 1 Introduction

ADLINK IMB-C47 ATX is an industrial motherboard supporting 12th/13th/14th Generation Intel® Core™ i9/i7/i5/i3 desktop processors, an Intel® Q670 Chipset, and 7 PCIe expansion slots to provide a cost-competitive embedded computing solution. It includes high-speed data transfer interfaces such as PCIe 4.0, USB 3.0, and SATA 6 Gb/s (SATA III), and dual-channel DDR4 3200 MHz RAM for industrial automation applications. With industrial-grade I/O port design, the IMB-C47 offers a significant competitive advantage for embedded computing applications in terms of device compatibility, durable connectivity, and extreme environment readiness.

# 1.1 Packing List

IMB-C47 ATX motherboard
Rear I/O shield

# 1.2 Optional Accessories

• CPU cooler for 65W CPU (Part Number: 32-20976-0000-A0)
• CPU cooler for 125W CPU (Part Number: 32-21041-0000-A0)
• 2-port USB2.0 cable with bracket (Part Number: 30-25010-3010)
• 2-port USB3.0 cable with bracket (Part Number: 30-25046-0100)
4-port USB 2.0 cable with bracket (Part Number 30-25009-3000)
• SATA cable with bracket (Part Number: 30-10057-7000)
• 2-port COM cable with bracket (Part Number: 30-25003-3000)

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# 2 Specifications

# 2.1 Core System

 CPU:

<table><tr><td>Family</td><td>Number</td><td>CPU Core</td><td>Frequency (GHz)</td><td>Cache(MB)</td><td>Power</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i9-14900T</td><td>24</td><td>1.1GHz</td><td>36MB</td><td>35</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i9-14900K</td><td>24</td><td>3.2GHz</td><td>36MB</td><td>125</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i9-14900</td><td>24</td><td>2.0GHz</td><td>36MB</td><td>65</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i7-14700T</td><td>20</td><td>1.3GHz</td><td>33MB</td><td>35</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i7-14700K</td><td>20</td><td>3.4GHz</td><td>33MB</td><td>125</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i7-14700</td><td>20</td><td>2.1GHz</td><td>33MB</td><td>65</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i5-14600K</td><td>14</td><td>3.5GHz</td><td>24MB</td><td>125</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i5-14500T</td><td>14</td><td>1.7GHz</td><td>24MB</td><td>35</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i5-14500</td><td>14</td><td>2.6GHz</td><td>24MB</td><td>65</td></tr><tr><td>Raptor Lake-S Refresh</td><td>i3-14100T</td><td>4</td><td>2.7GHz</td><td>12MB</td><td>35</td></tr><tr><td>Raptor Lake-S Refresh</td><td>Ri3-14100</td><td>4</td><td>3.5GHz</td><td>12MB</td><td>60</td></tr><tr><td>Raptor Lake-S</td><td>i9-13900K</td><td>24</td><td>3.0GHz</td><td>36MB</td><td>125</td></tr><tr><td>Raptor Lake-S</td><td>i9-13900E</td><td>24</td><td>1.8GHz</td><td>36MB</td><td>65</td></tr><tr><td>Raptor Lake-S</td><td>i7-13700TE</td><td>16</td><td>1.1GHz</td><td>30MB</td><td>35</td></tr><tr><td>Raptor Lake-S</td><td>i7-13700T</td><td>16</td><td>1.4GHz</td><td>30MB</td><td>35</td></tr><tr><td>Raptor Lake-S</td><td>i7-13700K</td><td>16</td><td>2.5GHz</td><td>30MB</td><td>125</td></tr><tr><td>Raptor Lake-S</td><td>i5-13600K</td><td>14</td><td>2.6GHz</td><td>24MB</td><td>125</td></tr><tr><td>Raptor Lake-S</td><td>i5-13500T</td><td>14</td><td>1.6GHz</td><td>24MB</td><td>35</td></tr><tr><td>Raptor Lake-S</td><td>i3-13100T</td><td>4</td><td>2.5GHz</td><td>12MB</td><td>35</td></tr><tr><td>Raptor Lake-S</td><td>i3-13100E</td><td>4</td><td>3.3GHz</td><td>12MB</td><td>60</td></tr><tr><td>Alder Lake-S</td><td>i9-12900K</td><td>16</td><td>2.4GHz</td><td>30MB</td><td>125</td></tr><tr><td>Alder Lake-S</td><td>i9-12900E</td><td>16</td><td>2.3GHz</td><td>30MB</td><td>65</td></tr><tr><td>Alder Lake-S</td><td>i7-12700TE</td><td>12</td><td>1.4GHz</td><td>25MB</td><td>35</td></tr><tr><td>Alder Lake-S</td><td>i7-12700K</td><td>12</td><td>2.7GHz</td><td>25MB</td><td>125</td></tr><tr><td>Alder Lake-S</td><td>i5-12600K</td><td>10</td><td>2.8GHz</td><td>20MB</td><td>125</td></tr><tr><td>Alder Lake-S</td><td>i5-12500E</td><td>6</td><td>2.9GHz</td><td>18MB</td><td>65</td></tr><tr><td>Alder Lake-S</td><td>i3-12100TE</td><td>4</td><td>2.1GHz</td><td>12MB</td><td>35</td></tr><tr><td>Alder Lake-S</td><td>G7400TE</td><td>2</td><td>3.0GHz</td><td>6MB</td><td>35</td></tr></table>

Chipset: Intel® Q670 Express Chipset

Memory: 4x 288-pin dual-channel DDR4 3200 MHz, up to 128 GB

BIOS: AMI® UEFI BIOS, 256 Mb SPI Flash Memory

#  Hardware Monitor: CPU voltage

+3.3V voltage
+5V voltage
+12V voltage
CPU temperature
• System temperature
CPU fan speed
• System fan speed

# 2.2 I/O Interface

# Expansion slots:

• 2x PCIe x16 (supports PCIe Gen4 x8 signals)
• 4x PCIe x4 (supports 3x PCIe Gen4 x4 and 1x PCIe Gen3 x4 signals)
1x PCI

 SATA: 4x SATA 6.0 Gb/s connectors, Intel® software RAID 0/1/5/10 support

#  USB:

6x USB 3.0 connector (rear)
• 2x USB 3.0 (via pin headers)
• 4x USB 2.0 (via pin headers)
• 1x USB 2.0 (vertical type A, internal)

#  COM:

• 4x RS-232 (COM1 by DB9/M, others via headers)
1x RS-232/422/485 (via headers)
1x RS-232/485 (via headers)

 PS/2 Combo Port: 1x PS/2 keyboard/mouse pin header

 DIO: 8-bit GPIO

TPM: Support Intel PTT

M.2 connectors:

• 1x M.2 E-key 2230 (PCIe Gen3 x1, USB2.0, CNVi) for WIFI/Bluetooth Module
• 1x M.2 M-key 2242/2280 (PCIe Gen4 x4 NVMe/SATA Auto Detect) for SSD

# 2.3 Video

Supports four independent displays:

1x DVI-D (DVI-I), max resolution up to 1920x1200@60Hz
. 1x HDMI 1.4b, max resolution up to 4096x2160@30Hz
1x VGA, max resolution up to 1920x1200@60Hz
• 1x eDP (via header), max resolution up to 4096x2304@60Hz

# 2.4 Audio

 Audio Codec: Realtek® ALC897
Interfaces: 1x Mic-in, 1x Line-in, and 1x Line-out connectors (rear)

# 2.5 LAN

 LAN1: Intel® I219-V via RJ45 connector, with 10/100/1000 Mbps
 LAN2: Intel® I226-V via RJ45 connector, with 10/100/1000/2500 Mbps

# 2.6 Temperatures

Operating Temperature: $0 ^ { \circ } \mathsf { C }$ to $6 0 ^ { \circ } \mathsf { C }$
Storage Temperature: $\angle 0 ^ { \circ } \mathsf { C }$ to $7 5 \textdegree$

# 2.7 Humidity

$6 0 ^ { \circ } \mathsf { C }$ at 95% RH, non-condensing

# 2.8 Certificate (EMC)

CE/FCC Class A

# 2.9 Form Factor

ATX: 305 mm x 244 mm (W x L)

# 2.10 Operating Systems

Microsoft® Windows® 10, 64-bit
Microsoft® Windows® 11, 64-bit

2.11 Functional Block Diagram
![**Central Components and Connection:**\n*   **12/13/14th Gen Intel® Processor** connects to **Intel® PCH Q670** via a bidirectional arrow labeled **DMI**.\n\n**Connections to/from 12/13/14th Gen Intel® Processor:**\n*   **Left Side:**\n    *   **VGA DB9FM Port** ↔ **Converter** ↔ **DDI** ↔ Processor\n    *   **HDMI TYPE-A** ↔ **DDI** ↔ Processor\n    *   **DVI-D Port** ↔ **DDI** ↔ Processor\n    *   **eDP Header** ↔ **eDP** ↔ Processor\n*   **Right Side:**\n    *   Processor ↔ **DIMM0+DIMM1** ↔ **DDR4 4x U-DIMM**\n    *   Processor ↔ **PEG 16X** ↔ **PCIE x16 Slot**\n    *   **PEG 16X** → **PEG 8X** → **PCIE x16 Slot**\n    *   Processor ↔ **PCIE X 4** ↔ **PCIE x4 Slot**\n\n**Connections to/from Intel® PCH Q670 (Left Side):**\n*   **SPDIF Header**, **L-OUT/IN/MIC Phone Jack**, and **L-OUT+MIC Header** connect to **AUDIO CODEC**, which connects via **HDA** to the PCH.\n*   **RJ45 Port** ↔ **I219-V** ↔ **GbE** ↔ PCH\n*   **RJ45 Port** ↔ **I226-V** ↔ **PCIE** ↔ PCH\n*   Three **PCIE x4 Port** blocks connect via **PCIE 4X** to the PCH.\n*   **M.2 Key E 2230** ↔ **PCIE+USB2.0** ↔ PCH\n*   **M.2 Key M 2242/2280** ↔ **PCIE 4X / SATA** ↔ PCH\n*   **4x SATA Port** ↔ **SATAx4** ↔ PCH\n*   Two **USB3.0 2xTYPE-A** blocks connect via **2x USB3.0 + 2x USB2.0** to the PCH.\n*   **1x PCI Port** ↔ **PCI Bridge** ↔ **HSIO** ↔ PCH\n*   **SMBus Header** ↔ **SMBus** ↔ PCH\n\n**Connections to/from Intel® PCH Q670 (Right Side):**\n*   **2x USB3.0 + 2x USB2.0** ↔ **USB3.0 Dual-Header**\n*   **1x USB2.0** ↔ **USB2.0 Vertical-TYPE-A**\n*   **4x USB2.0** ↔ **USB2.0 2x Dua-Header**\n*   **2x USB3.0 + 2x USB2.0** ↔ **2x USB3.0 TYPE-A (+PS2)** (Label below line: **KB+MS**)\n*   **eSPI** ↔ **Super I/O**\n    *   **Super I/O** → **RS232** → **COM1 DB9M**\n    *   **Super I/O** → **RS232** → **COM2 Header**\n    *   **Super I/O** → **RS232/485/422** → **COM3 Header**\n    *   **Super I/O** → **RS232/485** → **COM4 Header**\n    *   **Super I/O** → **RS232** → **COM5/6 Header**\n    *   **Super I/O** → **FAN1~3** → **3x FAN Header**\n    *   **Super I/O** → **GPIOx8** → **GPIO Header**\n    *   **Super I/O** → **CASE OPEN Header**\n*   **eSPI** ↔ **Header**\n*   **PWR-ON,RESET,HDD LED** ↔ **F-PANEL**](.20260410-47de19e6-512/93330b54c1fa40ec6434cd67a7dafbddfd2b4bd1c918c53e9672ff6605f76b39.jpg)

Figure 1: Functional Block Diagram

# 3 Mechanical Layout

# 3.1 IO Panel Connector Locations

![A\nB\nC\nD-2\nD-1\nI-1\nE-2\nE-1\nF\nG\nH-4\nH-3\nH-2\nH-1\nI-3\nI-2](.20260410-47de19e6-512/e3050df179097e0ad840f42e887e0529c2391d99637d54d96aee35634791d93c.jpg)

Figure 2: IO Panel Connector Locations

Table 1: IO Panel Connector Definitions

<table><tr><td>Item</td><td>Description</td><td>Description</td></tr><tr><td>A</td><td>PS/2_USB1 (PS/2)</td><td>PS/2 Connector (Keyboard &amp; Mouse)</td></tr><tr><td>B</td><td>DVI_VGA1 (VGA)</td><td>VGA DB15/F Connector</td></tr><tr><td>C</td><td>COM1</td><td>COM1 DB9/M Connector</td></tr><tr><td>D-1</td><td>RJ45_USB1 (LAN1)</td><td>GBE LAN RJ45 Connector1</td></tr><tr><td>D-2</td><td>RJ45_USB2 (LAN2)</td><td>2.5GBE LAN RJ45 Connector2</td></tr><tr><td>E-1</td><td>PS/2_USB1 (USB1)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>E-2</td><td>PS/2_USB1 (USB2)</td><td>USB3.0 TYPE-A Connector</td></tr><tr><td>F</td><td>DVI_VGA1 (DVI-D)</td><td>DVI-I 24+4P/F Connector (Support DVI-D)</td></tr><tr><td>G</td><td>HDMI1</td><td>HDMI TYPE-A Connector</td></tr><tr><td>H-1</td><td>RJ45_USB1 (USB1)</td><td>USB3.0 TYPE-A Connector1</td></tr><tr><td>H-2</td><td>RJ45_USB1 (USB2)</td><td>USB3.0 TYPE-A Connector2</td></tr><tr><td>H-3</td><td>RJ45_USB2 (USB3)</td><td>USB3.0 TYPE-A Connector3</td></tr><tr><td>H-4</td><td>RJ45_USB2 (USB4)</td><td>USB3.0 TYPE-A Connector4</td></tr><tr><td>I-1</td><td>AUDIO1 (BLUE)</td><td>Line-In 3.5mm Jack</td></tr><tr><td>I-2</td><td>AUDIO1 (GREEN)</td><td>Line-Out 3.5mm Jack</td></tr><tr><td>I-3</td><td>AUDIO1 (PINK)</td><td>MIC-In 3.5mm Jack</td></tr></table>

![51 52\n53 54-1 54-2 54-3 54-4\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14-1\n(Lower)\n14-3\n(Lower)\n15\n16\n17\n18\nADLINK\nIMB-C47\nMODEL: IMB-10\nSATAI-2\nSATA3-4\n36 35 34 33 32 31 30-1 29 28 27 26 25 24 23 22 21 19 18\n49 48 47 46\n45\n44\n43\n42\n41\n40\n39\n38\n37](.20260410-47de19e6-512/2b3fd139081e8e2221d820fcb76b84f6ea756c9a586676a899106f7d59626c81.jpg)

Figure 3: Onboard Connector – Header and Jumper Locations

Table 2: Onboard Connector – Header and Jumper Definitions

<table><tr><td>Item</td><td>Description</td><td>Description</td></tr><tr><td>1</td><td>ATX1</td><td>ATX 24P CPU Power Input Connector</td></tr><tr><td>2</td><td>PSON1</td><td>Power On Wafer</td></tr><tr><td>3</td><td>VOLT1</td><td>Power Monitor Wafer</td></tr><tr><td>4</td><td>USB2_1</td><td>USB2.0 Internal Vertical TYPE-A Connector</td></tr><tr><td>5</td><td>F_USB3_1</td><td>Front USB3.0 Box Header</td></tr><tr><td>6</td><td>CLR_CMOS1</td><td>CMOS Clear Select Jumper</td></tr><tr><td>7</td><td>SMBUS1</td><td>SMBUS Wafer</td></tr><tr><td>8</td><td>JP4</td><td>COM3 RS232/422/485 Select Jumper3</td></tr><tr><td>9</td><td>JP15</td><td>COM3 RS422 RX Signal 120Ω Resistive termination Select Jumper</td></tr><tr><td>10</td><td>J_AT/ATX1</td><td>AT or ATX Select Jumper</td></tr><tr><td>11</td><td>J_ME1</td><td>ME Flash Jumper</td></tr><tr><td>12</td><td>J_DNX1</td><td>DNX Force Reload Disable/Enable Select Jumper</td></tr><tr><td>13</td><td>J_COPEN1</td><td>Case Open Header</td></tr><tr><td>14-1</td><td>SATA1</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>14-2</td><td>SATA2</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>14-3</td><td>SATA3</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>14-4</td><td>SATA4</td><td>SATA3.0 7P Upright Connector</td></tr><tr><td>15</td><td>M.2_KEYE_WLAN1</td><td>M.2 Key-E Slot (PCIE+USB2.0+ CNVi, support WIFI+BT/ CNVi Module, 2230)</td></tr><tr><td>16</td><td>M.2_PCIESSD_M1</td><td>M.2 Key-M Slot (PCIe x4 GEN4 NVMe/SATA SSD Auto Detect, 2242/2280)</td></tr><tr><td>17</td><td>J_ESPI1</td><td>ESPI Header (Debug Only)</td></tr><tr><td>18</td><td>JP11</td><td>COM6 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>19</td><td>JP18</td><td>COM4 RS232/RS485 Select Jumper2</td></tr><tr><td>20</td><td>JP17</td><td>COM4 RS485 Signal 120Ω Resistive termination Select Jumper</td></tr><tr><td>21</td><td>JP16</td><td>COM3 RS422 TX/RS485 Signal 120Ω Resistive termination Select Jumper</td></tr><tr><td>22</td><td>JP10</td><td>COM5 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>23</td><td>JP7</td><td>COM4 RS232/RS485 Select Jumper1</td></tr><tr><td>24</td><td>JP9</td><td>COM4 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>25</td><td>JP5</td><td>COM3 RS232/RS422 Select Jumper1</td></tr><tr><td>26</td><td>JP6</td><td>COM3 RS232/RS422 Select Jumper2</td></tr><tr><td>27</td><td>JP8</td><td>COM3 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>28</td><td>JP12</td><td>COM2 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>29</td><td>JP19</td><td>Watch Dog Reset Enable/Disable Select Jumper</td></tr><tr><td>30-1</td><td>COM2</td><td>COM2 Header</td></tr><tr><td>30-2</td><td>COM3</td><td>COM3 Header</td></tr><tr><td>30-3</td><td>COM4</td><td>COM4 Header</td></tr><tr><td>30-4</td><td>COM5</td><td>COM5 Header</td></tr><tr><td>30-5</td><td>COM6</td><td>COM6 Header</td></tr><tr><td>31</td><td>F_PANEL1</td><td>Front Panel Header</td></tr><tr><td>32</td><td>F_USB2_1</td><td>Front USB2.0 Header1</td></tr><tr><td>33</td><td>F_USB2_2</td><td>Front USB2.0 Header2</td></tr><tr><td>34</td><td>J_GPIO1</td><td>GPIO Header</td></tr><tr><td>35</td><td>SYS_FAN2</td><td>System FAN Wafer2</td></tr><tr><td>36</td><td>SYS_FAN1</td><td>System FAN Wafer1</td></tr><tr><td>37</td><td>PCIE_4X_SLOT4</td><td>PCI-E 4x Slot4 (PCIe 4X)</td></tr><tr><td>38</td><td>PCI1</td><td>PCI Slot</td></tr><tr><td>39</td><td>PCIE_4X_SLOT3</td><td>PCI-E 4x Slot3 (PCIe 4X)</td></tr><tr><td>40</td><td>JP14</td><td>PCI CLK 66MHz Enable/Disable Select Jumper</td></tr><tr><td>41</td><td>PCIE_16X_SLOT2</td><td>PCI-E 16x Slot2 (PCIe 8X)</td></tr><tr><td>42</td><td>J_SPDIF1</td><td>SPDIF Out Header</td></tr><tr><td>43</td><td>PCIE_4X_SLOT2</td><td>PCI-E 4x Slot2 (PCIe 4X)</td></tr><tr><td>44</td><td>PCIE_4X_SLOT1</td><td>PCI-E 4x Slot1 (PCIe 4X)</td></tr><tr><td>45</td><td>PCIE_16X_SLOT1</td><td>PCI-E 16x Slot1 (PCIe 8X)</td></tr><tr><td>46</td><td>F_AUDIO1</td><td>Front Audio Header (Line-Out + MIC)</td></tr><tr><td>47</td><td>EDP_P1</td><td>eDP Backlight Control Wafer</td></tr><tr><td>48</td><td>JC_EDP1</td><td>eDP VDD Select Jumper</td></tr><tr><td>49</td><td>EDP1</td><td>eDP Signal Header</td></tr><tr><td>50</td><td>JP3</td><td>COM1 VCC5/DCD+VCC12/RI Select Jumper</td></tr><tr><td>51</td><td>ATX3</td><td>ATX 4P CPU Power Input Connector</td></tr><tr><td>52</td><td>ATX2</td><td>ATX 8P CPU Power Input Connector</td></tr><tr><td>53</td><td>CPU_FAN1</td><td>CPU FAN Wafer</td></tr><tr><td>54-1</td><td>DIMM1</td><td>DDR4 CHA DIMM Slot1</td></tr><tr><td>54-2</td><td>DIMM3</td><td>DDR4 CHA DIMM Slot2</td></tr><tr><td>54-3</td><td>DIMM2</td><td>DDR4 CHB DIMM Slot3</td></tr><tr><td>54-4</td><td>DIMM4</td><td>DDR4 CHB DIMM Slot4</td></tr></table>

# 3.2 Mechanical Dimensions

Top View
![343.8\n0.0\n0.0\n304.8](.20260410-47de19e6-512/36f5647d694ac7d3a883a1baa3f2231ffe49f1436d1daa80cb8ce0b1ea3bd1f1.jpg)

Dimensions: mm

Figure 4: Mechanical Dimensions
Side View
![Diagram of various electronic device ports and connectors (no text or labels)](.20260410-47de19e6-512/7f3bfe06d6ea07bc0d3290fe88485687f4a57d5653b42e6c2b5e605d7bab8f62.jpg)

Dimensions: mm

Figure 5: Mechanical Dimensions - IO Panel

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# 4 Connector Pinouts

See 3.1 Connector Locations on page 7 for connector locations.

# 4.1 Rear IO Connectors

# 4.1.1 HDMI

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDMI1_CON_DP2</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>HDMI1_CON_DN2</td><td>4</td><td>HDMI1_CON_DP1</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>HDMI1_CON_DN1</td></tr><tr><td>7</td><td>HDMI1_CON_DP0</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>HDMI1_CON_DN0</td><td>10</td><td>HDMI1_CON_CKP</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>HDMI1_CON_CKN</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>HDMI1_DDC_CLK</td><td>16</td><td>HDMI1_DDC_DATA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5V_HDMI</td></tr><tr><td>19</td><td>HDMI1_CON_HPD</td><td></td><td></td></tr></table>

![This is a black-and-white line drawing of a rectangular connector, likely a D-sub connector housing. Inside the outline, there are two rows of small squares representing pins. Numbers are printed near specific pins to indicate pin numbers.\n\n**Top Row:**\n*   On the left side: The numbers **19** and **17** appear above the first two squares.\n*   On the right side: The numbers **3** and **1** appear above the last two squares.\n\n**Bottom Row:**\n*   On the left side: The number **18** appears below the first square.\n*   On the right side: The numbers **4** and **2** appear below the last two squares.\n\nThe drawing shows a gap in the middle of both rows where no numbers are present.](.20260410-47de19e6-512/31107f53e79665b7d8594f25143cc3579911639fd82501e945c4ec56fd394ac5.jpg)

# 4.1.2 VGA Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VGA_CON_RED</td><td>2</td><td>VGA_CON_GREEN</td></tr><tr><td>3</td><td>VGA_CON_BLUE</td><td>4</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>+5V_HDMI</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>VGA_DDCDAT</td></tr><tr><td>13</td><td>VGA_CON_HS</td><td>14</td><td>VGA_CON_VS</td></tr><tr><td>15</td><td>VGA_DDCCLK</td><td></td><td></td></tr></table>

![This is a line drawing of a DB-15 connector. It features a rectangular outer casing with a hexagonal mounting hole on the left and right sides. In the center is a D-sub shell containing three rows of five circular pins. Above the top row of pins, the number '5' is positioned above the leftmost pin and '1' above the rightmost pin. Below the bottom row of pins, the number '15' is positioned below the leftmost pin and '11' above the rightmost pin.](.20260410-47de19e6-512/36e336a06fe8533882396ee486d416b658674c8ee78d1bd3564acd66c6e6a2dd.jpg)

# 4.1.3 COM 1 (COM1 DB9/M Connector)

<table><tr><td rowspan="2">Pin</td><td>Signal</td></tr><tr><td>RS-232</td></tr><tr><td>1</td><td>PIN 1 [1]</td></tr><tr><td>2</td><td>RxD</td></tr><tr><td>3</td><td>TxD</td></tr><tr><td>4</td><td>DTR#</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>DSR#</td></tr><tr><td>7</td><td>RTS#</td></tr><tr><td>8</td><td>CTS#</td></tr><tr><td>9</td><td>PIN 9 [1]</td></tr></table>

![1\n5\n6\n9](.20260410-47de19e6-512/5c8236452809b8a0cfa4df2c3fae163b0b3e0bfeef2c4f05142b76227759aca0.jpg)

Note: PIN1 of COM1 can be DCD (default) /5V and Pin9 of COM1 can be RI(Default) / 12V, selectable by “COM1 DCD/RI Select Jumper”. (JP3)

# 4.1.4 Ethernet Connectors (LAN1, LAN2)

RJ45\_USB1 (LAN1) (GBE LAN RJ45 Connector1)

<table><tr><td>Pin</td><td colspan="2">Signal</td><td>Pin</td><td colspan="2">Signal</td></tr><tr><td>1</td><td colspan="2">MDI1_0+</td><td>5</td><td colspan="2">MDI1_2+</td></tr><tr><td>2</td><td colspan="2">MDI1_0-</td><td>6</td><td colspan="2">MDI1_2-</td></tr><tr><td>3</td><td colspan="2">MDI1_1+</td><td>7</td><td colspan="2">MDI1_3+</td></tr><tr><td>4</td><td colspan="2">MDI1_1-</td><td>8</td><td colspan="2">MDI1_3-</td></tr><tr><td rowspan="3">LED1</td><td rowspan="3">Active LED</td><td>ACT: Blinking Green</td><td rowspan="3">LED2</td><td rowspan="3">Speed LED</td><td>1000M: Turn Orange</td></tr><tr><td>LINK only: Lights On</td><td>100M: Turn Green</td></tr><tr><td>Stop: Lights Off</td><td>10M: Lights Off</td></tr></table>

![The image displays a schematic diagram featuring a central rectangular outline with a darker, notch-topped shape inside, resembling an RJ45 jack. The text 'LED1' is positioned at the top left, and 'LED2' is at the top right. Below the diagram, the number '8' is on the left and '1' is on the right. Thin lines connect the number '8' to the bottom-left corner of the central shape and the number '1' to the bottom-right corner. Two small rectangular boxes are drawn near the top interior, aligned under the LED labels.](.20260410-47de19e6-512/ad82a2eccb6121c4a46bdec0752463639c0d8dddfbe0a1c67e077bca8e97e43a.jpg)

Note: RJ45\_USB1 (LAN1) I219-V does not support Intel AMT 12.0 and Intel vPro components by default.

RJ45\_ USB2 (LAN2) (GBE LAN RJ45 Connector2)

<table><tr><td>Pin</td><td colspan="2">Signal</td><td>Pin</td><td colspan="2">Signal</td></tr><tr><td>1</td><td colspan="2">MDI2_0+</td><td>5</td><td colspan="2">MDI2_2+</td></tr><tr><td>2</td><td colspan="2">MDI2_0-</td><td>6</td><td colspan="2">MDI2_2-</td></tr><tr><td>3</td><td colspan="2">MDI2_1+</td><td>7</td><td colspan="2">MDI2_3+</td></tr><tr><td>4</td><td colspan="2">MDI2_1-</td><td>8</td><td colspan="2">MDI2_3-</td></tr><tr><td rowspan="3">LED1</td><td rowspan="3">Active LED</td><td>ACT: Blinking Green</td><td rowspan="3">LED2</td><td rowspan="3">Speed LED</td><td>1000M/2.5G: Turn Orange</td></tr><tr><td>LINK only: Lights On</td><td>100M: Turn Green</td></tr><tr><td>Stop: Lights Off</td><td>10M: Lights Off</td></tr></table>

# 4.2 Onboard Headers / Connectors

# 4.2.1 ATX12V Power Connector (ATX2)

This motherboard provides an 8-pin and 4-pin ATX 12V power connector.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>8</td><td>ATX12V</td><td>7</td><td>ATX12V</td><td>6</td><td>ATX12V</td><td>5</td><td>ATX12V</td></tr><tr><td>4</td><td>GND</td><td>3</td><td>GND</td><td>2</td><td>GND</td><td>1</td><td>GND</td></tr></table>

![The image shows a rectangular grid consisting of eight squares arranged in two rows of four. The numbers '8', '5', '4', and '1' are positioned at the four corners: '8' at the top left, '5' at the top right, '4' at the bottom left, and '1' at the bottom right.](.20260410-47de19e6-512/be91606b9384501bfc319471c9576403e67e259a11181065a50bdd23e65ef29c.jpg)

# 4.2.2 ATX12V Power Connector (ATX3)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>3</td><td>ATX12V</td><td>1</td><td>GND</td></tr><tr><td>4</td><td>ATX12V</td><td>2</td><td>GND</td></tr></table>

![The image displays a black and white schematic diagram of a rectangular object divided into four equal squares arranged in a 2x2 grid. Inside each square is a smaller, solid black square. The top-left and bottom-right squares feature a small rectangular cutout on their top-right corners. The number 3 is positioned to the left of the top row, the number 4 to the left of the bottom row, the number 1 to the right of the top row, and the number 2 to the right of the bottom row.](.20260410-47de19e6-512/ff7ee2a5d8f4527f675040d0f53ea80856b6fc3c1b732b0f2f22df6a6c16bfed.jpg)

# 4.2.3 Fan Connectors (SYS\_FAN1/2, CPU\_FAN1)

![GND\n+12V\nFAN_SPEED_DETECTION\nFAN_SPEED_CONTROL\n1](.20260410-47de19e6-512/e5ae7dbae9521ba7474b95a6e188732c9b1579163401fa30b787a25eaf221ba6.jpg)

# 4.2.4 USB Connectors (USB2\_1)

There are two USB 2.0 Type-A vertical connectors on this motherboard.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>3</td><td>USB_D+</td></tr><tr><td>2</td><td>USB_D-</td></tr><tr><td>1</td><td>USB_PWR</td></tr></table>

![The image displays a vertical rectangular outline with rounded corners. Inside the left side is a thick, vertical black bar. To the right of the rectangle, the number '4' is positioned at the top and the number '1' is positioned at the bottom.](.20260410-47de19e6-512/498ed9eac61086b0e6c6eb1c57bd88f5a6b50c9d5346fae9984bb9fa200ef3a9.jpg)

# 4.2.5 SMBUS1

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>SMB_DATA</td></tr><tr><td>3</td><td>SMB_CLK</td></tr><tr><td>4</td><td>VCC5</td></tr></table>

![A vertical rectangular strip containing three small squares stacked vertically. To the right of the top of the strip is the number 1, and below it is a small number 4.](.20260410-47de19e6-512/4633f990099e04a49688385644618c5dd3f145e2c2ba43d1ded83caf98ee731b.jpg)

# 4.2.6 24-pin ATX Power Input Connector (ATX1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>12</td><td>+3V</td><td>24</td><td>GND</td></tr><tr><td>11</td><td>+12V</td><td>23</td><td>+5V</td></tr><tr><td>10</td><td>+12V</td><td>22</td><td>+5V</td></tr><tr><td>9</td><td>ATX+5VSB</td><td>21</td><td>+5V</td></tr><tr><td>8</td><td>PWROK_PS</td><td>20</td><td>NA</td></tr><tr><td>7</td><td>GND</td><td>19</td><td>GND</td></tr><tr><td>6</td><td>+5V</td><td>18</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>17</td><td>GND</td></tr><tr><td>4</td><td>+5V</td><td>16</td><td>PSON#</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>GND</td></tr><tr><td>2</td><td>+3V</td><td>14</td><td>-12V</td></tr><tr><td>1</td><td>+3V</td><td>13</td><td>+3V</td></tr></table>

![12\n24\n1\n13](.20260410-47de19e6-512/ece8fbe7e26b79a40adea33143f36440f3bf06a4a1c81d4759448a511363b6c6.jpg)

# 4.2.7 USB 3.0 Header (F\_USB3\_1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td></td><td></td><td>1</td><td>VCC5</td></tr><tr><td>4</td><td>VCC5</td><td>3</td><td>USB3.0_RX1-</td></tr><tr><td>6</td><td>USB3.0_RX2-</td><td>5</td><td>USB3.0_RX1+</td></tr><tr><td>8</td><td>USB3.0_RX2+</td><td>7</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>9</td><td>USB3.0_TX1-</td></tr><tr><td>12</td><td>USB3.0_TX2-</td><td>11</td><td>USB3.0_TX1+</td></tr><tr><td>14</td><td>USB3.0_TX2+</td><td>13</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>15</td><td>USB2.0_1-</td></tr><tr><td>18</td><td>USB2.0_2-</td><td>17</td><td>USB2.0_1+</td></tr><tr><td>20</td><td>USB2.0_2+</td><td>19</td><td>N/C</td></tr></table>

Front USB 3.0 Box Header 10\*2 Pin 2.00 mm

# 4.2.8 SATA Connector (SATA 1/2/3/4)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>5</td><td>SATA-B-</td></tr><tr><td>2</td><td>SATA-A+</td><td>6</td><td>SATA-B+</td></tr><tr><td>3</td><td>SATA-A-</td><td>7</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td></td><td></td></tr></table>

# 4.2.9 Front Panel Audio Header (F\_PANEL1)

This header accommodates several system front panel functions.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>HDD 3.3V LED+</td><td>2</td><td>POWER 3.3V LED+</td></tr><tr><td>3</td><td>HDD 3.3V LED-</td><td>4</td><td>POWER 3.3V LED-</td></tr><tr><td>5</td><td>RESET-</td><td>6</td><td>POWER+</td></tr><tr><td>7</td><td>RESET+</td><td>8</td><td>POWER-</td></tr><tr><td>9</td><td>N/C</td><td></td><td></td></tr></table>

Front Panel Header 5\*2 Pin 2.54mm

![The image displays a vertical rectangular diagram, resembling a schematic of a card. Inside the rectangle are two vertical columns of small squares, arranged in ten rows. On the right edge of the rectangle, there are two rectangular cutouts. To the right of the upper cutout is the number 1, and to the right of the lower cutout is the number 3.](.20260410-47de19e6-512/c3bd4cb1bf30492cd261e8b12cd517e93783392c2f2891b483f34ce3be795736.jpg)

![A black and white line drawing depicts a vertical rectangular slot or housing. Inside the outer boundary is an inner rectangular structure featuring a vertical dashed line running down its center. To the left of the dashed line is a small, solid rectangular protrusion. The top of the inner structure has angled cutouts, and the bottom has a small notch. On the right side of the diagram, the numbers '1' and '7' are displayed vertically.](.20260410-47de19e6-512/99eeee1a31715aebe4985074e5a465050fbe480f495259ce01ee500a27ddf48b.jpg)

![The image displays the number '1' on the left and the number '2' on the right. Centered between these numbers is a vertical column of five rounded rectangular frames. The top four frames each contain two small squares, while the bottom frame contains a single small square on the left side.](.20260410-47de19e6-512/94c6bd65af651cb7861e99f2c65315bfcb1a09501e65e70fe22d761133ab151e.jpg)

4.2.10 COM Port Header (COM 2-6)

<table><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM2</td><td>1</td><td>COM2_PIN1 [1]</td><td>2</td><td>COM2_DSR</td></tr><tr><td>3</td><td>COM2_RXD</td><td>4</td><td>COM2_RTS</td></tr><tr><td>5</td><td>COM2_TXD</td><td>6</td><td>COM2_CTS</td></tr><tr><td>7</td><td>COM2_DTR</td><td>8</td><td>COM2_PIN8 [1]</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM3</td><td>1</td><td>COM3_PIN1 [2] [3]</td><td>2</td><td>COM3_DSR</td></tr><tr><td>3</td><td>COM3_PIN3 [3]</td><td>4</td><td>COM3_RTS</td></tr><tr><td>5</td><td>COM3_PIN5 [3]</td><td>6</td><td>COM3_CTS</td></tr><tr><td>7</td><td>COM3_PIN7 [3]</td><td>8</td><td>COM3_PIN8 [2] [3]</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM4</td><td>1</td><td>COM4_PIN1 [4] [5]</td><td>2</td><td>COM4_DSR</td></tr><tr><td>3</td><td>COM4_PIN3 [4]</td><td>4</td><td>COM4_RTS</td></tr><tr><td>5</td><td>COM4_TXD</td><td>6</td><td>COM4_CTS</td></tr><tr><td>7</td><td>COM4_DTR</td><td>8</td><td>COM4_PIN8 [5]</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM5</td><td>1</td><td>COM5_PIN1 [6]</td><td>2</td><td>COM5_DSR</td></tr><tr><td>3</td><td>COM5_RXD</td><td>4</td><td>COM5_RTS</td></tr><tr><td>5</td><td>COM5_TXD</td><td>6</td><td>COM5_CTS</td></tr><tr><td>7</td><td>COM5_DTR</td><td>8</td><td>COM5_PIN8 [6]</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr><tr><td></td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td rowspan="5">COM6</td><td>1</td><td>COM6_PIN1 [7]</td><td>2</td><td>COM6_DSR</td></tr><tr><td>3</td><td>COM6_RXD</td><td>4</td><td>COM6_RTS</td></tr><tr><td>5</td><td>COM6_TXD</td><td>6</td><td>COM6_CTS</td></tr><tr><td>7</td><td>COM6_DTR</td><td>8</td><td>COM6_PIN8 [7]</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

![1\n2](.20260410-47de19e6-512/002ab9ea3e48299f18a51fccdb8640018e451cc5e7c4990d25e7a331f6dc59b7.jpg)

Box Header 5\*2 Pin 2.54mm
Note: [1]: PIN1 of COM2 can be DCD (default) or 5V, and Pin8 of COM2 can be RI (Default) or 12V, selectable by the “COM2 VCC5/DCD+VCC12/RI Select Jumper”. (JP12)
[2]: PIN1 of COM3 can be DCD (default) or 5V, and Pin8 of COM3 can be RI(Default)or 12V, selectable by the “COM3 VCC5/DCD+VCC12/RI Select Jumper”. (JP8)
[3]: COM3 can be RS232 (default), RS422, or RS485 selecting by JP4, JP5, JP6. COM3 can also be to RS485 or RS422 by using the jumper and setting the BIOS to RTS mode.
[4]: COM4 can be RS232 (default) or RS485 selecting by JP7and JP18. COM4 can also be set RS485 by using the jumper and setting the BIOS to RTS mode.
[5]: PIN1 of COM4 can be DCD (default) or 5V, and Pin8 of COM4 can be RI(Default) or 12V, selectable by the “COM4 VCC5/DCD+VCC12/RI Select Jumper”. (JP9)

[6]: PIN1 of COM5 can be DCD (default) or 5V, and Pin8 of COM5 can be RI(Default) or 12V, selectable by the “COM5 VCC5/DCD+VCC12/RI Select Jumper”. (JP10)
[7]: PIN1 of COM6 can be DCD (default) or 5V, and Pin8 of COM6 can be RI(Default) or 12V, selectable by the “COM5 VCC5/DCD+VCC12/RI Select Jumper”. (JP11)

# 4.2.11 ESPI Header (J\_ESPI1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>ESPI_IO0</td><td>2</td><td>VCC3.3_Dual</td></tr><tr><td>3</td><td>ESPI_IO1</td><td></td><td></td></tr><tr><td>5</td><td>ESPI_IO2</td><td>6</td><td>ESPI_CLK</td></tr><tr><td>7</td><td>ESPI_IO3</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>ESPI_CS0</td><td>10</td><td>VCC3.3S</td></tr><tr><td>11</td><td>ESPI_ALERT0_N</td><td>12</td><td>PLT_RST_N [1]</td></tr></table>

![The image displays the number '1' on the left and the number '2' on the right. Between them is a vertical column of seven rounded rectangular boxes. From top to bottom, the boxes contain black square dots arranged as follows: two dots, one dot (on the left), two dots, three dots (one left, one center, one right), two dots, two dots, and two dots.](.20260410-47de19e6-512/49400afb5f7b88acd033bddadc2ec0dcc0d15bfd72eec34493b595cb34af4188.jpg)

ESPI Header (Debug Only) 6\*2 Pin 2.00mm

Note: “H” or “L” indicates whether the default voltage is at high or low level. 95V GPIO)

# 4.2.12 GPIO Header (J\_GPIO1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>SIO_GPI70(0xA06 Bit0, H[1])</td><td>2</td><td>SIO_GPI71(0xA06 Bit1, H)</td></tr><tr><td>3</td><td>SIO_GPI72(0xA06 Bit2, H)</td><td>4</td><td>SIO_GPI73(0xA06 Bit3, H)</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>SIO_GPO74(0xA06 Bit4, H)</td></tr><tr><td>7</td><td>SIO_GPO75(0xA06 Bit5, H)</td><td>8</td><td>SIO_GPO76(0xA06 Bit6, H)</td></tr><tr><td>9</td><td>SIO_GPO77(0xA06 Bit7, H)</td><td>10</td><td>VCC5</td></tr><tr><td></td><td></td><td>12</td><td>N/C</td></tr></table>

![The image displays the number 1 on the left and the number 2 on the right. Between these numbers is a vertical column of five rectangular outlines stacked on top of one another. The top four rectangles each contain two black squares arranged side-by-side. The bottommost rectangle contains a single black square positioned on the right side.](.20260410-47de19e6-512/925ac65f4204a187c111190f26cc38fdad1a7a9b718338e2f7af5bc61f654791.jpg)

GPIO Header 6\*2 Pin 2.00mm

# 4.2.13 USB 2.0 Header (F\_USB2\_1, F\_USB2\_2)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC5</td><td>2</td><td>VCC5</td></tr><tr><td>3</td><td>USB2.0_1-</td><td>4</td><td>USB2.0_2-</td></tr><tr><td>5</td><td>USB2.0_1+</td><td>6</td><td>USB2.0_2+</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td></td><td></td><td>10</td><td>N/C</td></tr></table>

![1\n2](.20260410-47de19e6-512/8c2e48ca6f17915d0ff963238341a51a1a8c6a2f5bd97730488311dd886f8390.jpg)

Front USB2.0 Header2 5\*2 Pin 2.54mm

# 4.2.14 SPDIF Header (J\_SPIDIF1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC5</td><td></td><td></td></tr><tr><td>3</td><td>SPDIF_OUT</td><td>4</td><td>GND</td></tr></table>

SPDIF Out Header 4\*1 Pin 2.54mm

# 4.2.15 Front Panel Audio Header (F\_Audio1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>MIC_IN_L</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>MIC_IN_R</td><td>4</td><td>VCC3.3</td></tr><tr><td>5</td><td>LINE_OUT_R</td><td>6</td><td>MIC_RET</td></tr><tr><td>7</td><td>GND</td><td></td><td></td></tr><tr><td>9</td><td>LINE_OUT_L</td><td>10</td><td>LINE_OUT_RET</td></tr></table>

Front Audio Header (Line-Out + MIC) 5\*2 Pin 2.54mm

# 4.2.16 eDP Backlight Control Wafer (EDP\_P1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>4</td><td>EDP_BKLT_EN</td></tr><tr><td>2</td><td>GND</td><td>5</td><td>VCC12</td></tr><tr><td>3</td><td>EDP_BKLT_CTL</td><td>6</td><td>VCC12</td></tr></table>

eDP Backlight Control Wafer 6\*1 Pin 2mm

# 4.2.17 eDP Signal Header (EDP1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VDD_PANEL [1]</td><td>2</td><td>VDD_PANEL [1]</td></tr><tr><td>3</td><td>VDD_PANEL [1]</td><td></td><td></td></tr><tr><td>5</td><td>GND</td><td>6</td><td>EDP_HPD</td></tr><tr><td>7</td><td>N/C</td><td>8</td><td>N/C</td></tr><tr><td>9</td><td>N/C</td><td>10</td><td>N/C</td></tr><tr><td>11</td><td>N/C</td><td>12</td><td>N/C</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>N/C</td><td>16</td><td>N/C</td></tr><tr><td>17</td><td>N/C</td><td>18</td><td>N/C</td></tr><tr><td>19</td><td>EDP_TX0-</td><td>20</td><td>EDP_TX0+</td></tr><tr><td>21</td><td>EDP_TX1-</td><td>22</td><td>EDP_TX1+</td></tr><tr><td>23</td><td>EDP_TX2-</td><td>24</td><td>EDP_TX2+</td></tr></table>

![The image shows the number '1' in a thin, grey font on the left side. To its right is a vertical column of four identical, rounded rectangular shapes stacked closely together. Inside each of these outer shapes is a smaller, centered square outline. There is a tiny black mark, resembling a comma or speck, near the bottom right corner of the stack.](.20260410-47de19e6-512/4ae5d2c4b28ad0f41e2a07482f9919f0df3c58a6a7f0385b5be63b97f6cdacfe.jpg)

![The image displays a schematic line drawing of a connector or socket pinout. It consists of a vertical rectangular outline divided into four horizontal sections.\n\n*   **Top Section:** Contains two small squares representing contacts. The number '1' is positioned to the left of the left square, and the number '2' is positioned to the right of the right square.\n*   **Second Section:** Contains two small squares.\n*   **Third Section:** Contains one small square on the left side; the right side is empty.\n*   **Bottom Section:** Contains two small squares.](.20260410-47de19e6-512/8fcd53820fc8b45cf1d92e5b66a8e042ca87a11bd944884f905434d596ad5026.jpg)

![The image displays a black-and-white schematic diagram. On the left side, there is a tall, vertical rectangular column containing six small squares stacked vertically. To the right of the upper portion of this column is the number '1'. In the bottom right corner of the image is the number '4'.](.20260410-47de19e6-512/3a9e42ac669870732327db8f8136a755b0f0dbada5858a2de90a7d10b7c37745.jpg)

![1\n2](.20260410-47de19e6-512/c9ced1a65b2ee0ffd398da50f590dff83f289e603f1f3e1f1fe82f1cbb909eb1.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>25</td><td>GND</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>EDP_TX3-</td><td>28</td><td>EDP_TX3+</td></tr><tr><td>29</td><td>EDP_AUX-</td><td>30</td><td>EDP_AUX+</td></tr></table>

eDP Signal Header 15\*2 Pin 2mm
Note: Panel Power VDD can be set to 3.3V (default) /5V selectable by the eDP VDD Select Jumper” (JC\_EDP1).

# 4.3 Jumper and Switch Settings

# 4.3.1 COM1 VCC5/DCD+VCC12/RI Select Jumper (JP3)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM1_PIN1: VCC5COM1_PIN8: VCC12</td></tr><tr><td>3-5 , 4-6(Default)</td><td>COM1_PIN1: DCDCOM1_PIN8: RI</td></tr></table>

![The image displays the number 1 on the left and the number 2 on the right. In the center is a graphic resembling a calculator or keypad. The top portion is a white outline with rounded corners containing two small grey squares side-by-side. The bottom portion is an orange rectangle divided vertically, containing four small grey squares arranged in two columns of two.](.20260410-47de19e6-512/a2785a1a0c07e9652366c15e49b7d282c2d18677b6496fa76ca43f2e22a0e953.jpg)
Jumper 3\*2 Pin 2.54mm
Note: Jumper 1-3/3-5 select the COM1\_PIN1 signal. Jumper 2-4/4-6 select the COM1\_PIN8 signal.

# 4.3.2 COM2 VCC5/DCD+VCC12/RI Select Jumper (JP12)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM2_PIN1: VCC5COM2_PIN8: VCC12</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM2_PIN1: DCDCOM2_PIN8: RI</td></tr></table>

![The image displays a diagram of a door assembly flanked by text. At the top left is the number '1' and at the top right is the number '2'. Below the numbers is a white rectangular frame containing two small grey squares side-by-side. Directly beneath this is a larger orange rectangular area divided vertically into two panels. Inside this orange section are four small grey squares, arranged in two columns of two, each with a cross pattern. To the right of the number '2' is a comma ','.](.20260410-47de19e6-512/5abf1fd0de6cd11febf7d008a508ac600adf779abb144b32b678af2ee122207b.jpg)
Jumper 3\*2 Pin 2.54mm
Note: Jumper 1-3/3-5 select the COM2\_PIN1 signal. Jumper 2-4/4-6 select the COM2\_PIN8 signal.

# 4.3.3 COM3 VCC5/DCD+VCC12/RI Select Jumper (JP8)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM3_PIN1: VCC5COM3_PIN8: VCC12</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM3_PIN1: DCD/RS422_TX-/ RS485-COM3_PIN8: RI</td></tr></table>

![The image shows the number 1 on the left and the number 2 on the right. Centered between them is a structure with a white upper portion featuring a rounded top and two small grey squares. Below this is an orange lower portion divided into two sections, each containing a grid of six small squares.](.20260410-47de19e6-512/cd407415e6c89f9a5115f31c620491f81543c5384414b5218bb77555f299014f.jpg)
Jumper 3\*2 Pin 2.54mm
Note: Jumper 1-3/3-5 select the COM3\_PIN1 signal. Jumper 2-4/4-6 select the COM3\_PIN8 signal.

# 4.3.4 COM4 VCC5/DCD+VCC12/RI Select Jumper (JP9)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM4_PIN1: VCC5COM4_PIN8: VCC12</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM4_PIN1: DCD/TXCOM4_PIN8: RI</td></tr></table>

![The image displays the number '1' to the left and the number '2' to the right of a central building icon. The icon features a white upper section with two small square windows and an orange lower section with two large vertical panels, each containing a 2x2 grid of small grey squares. A small comma is visible below the number '2'.](.20260410-47de19e6-512/c576d276103fa63b90eeaa3562e1cf1524b3e63bac19d0c0848f598716d9eb0c.jpg)

Jumper 3\*2 Pin 2.54mm

Note: Jumper 1-3/3-5 select the COM4\_PIN1 signal. Jumper 2-4/4-6 select the COM4\_PIN8 signal.

# 4.3.5 COM5 VCC5/DCD+VCC12/RI Select Jumper (JP10)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM5_PIN1: VCC5COM5_PIN8: VCC12</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM5_PIN1: DCDCOM5_PIN8: RI</td></tr></table>

![The image displays a low-resolution graphic featuring the number '1' on the left and the number '2' on the right. In the center is a stylized icon resembling a building. The top portion of the icon is a grey rectangle containing two small grey squares. Below it is a larger orange rectangle divided into two vertical columns, with each column containing two small grey squares.](.20260410-47de19e6-512/c4865cb4feb3c8abfa30fae3f67da53fdf3ad5589b1767a268fdd02ff2895d9e.jpg)

Jumper 3\*2 Pin 2.54mm

Note: Jumper 1-3/3-5 select the COM5\_PIN1 signal. Jumper 2-4/4-6 select the COM5\_PIN8 signal.

# 4.3.6 COM6 VCC5/DCD+VCC12/RI Select Jumper (JP11)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-3, 2-4</td><td>COM6_PIN1: VCC5COM6_PIN8: VCC12</td></tr><tr><td>3-5, 4-6(Default)</td><td>COM6_PIN1: DCDCOM6_PIN8: RI</td></tr></table>

![The image displays the numbers '1' and '2' on either side of a central graphic icon. The icon depicts a stylized building with a grey-outlined top section containing two small squares side-by-side. Below this is a solid orange rectangle divided vertically, containing four small squares arranged in two columns.](.20260410-47de19e6-512/0e03ebc6730a754ddaebb6457c0178c22ba845c1ba957f55f9121f683e88364f.jpg)

Jumper 3\*2 Pin 2.54mm

Note: Jumper 1-3/3-5 select the COM6\_PIN1 signal. Jumper 2-4/4-6 select the COM6\_PIN8 signal.

# 4.3.7 COM3 RS232/422/485 Select Jumpers (JP4/JP5/JP6)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>JP4: 1-2JP5: 3-5、4-6JP6: 3-5、4-6(Default)</td><td>COM3: RS232(COM3_PIN1: DCDCOM3_PIN3: RXDCOM3_PIN5: TXDCOM3_PIN7: DTR)</td></tr><tr><td>JP4: 3-4JP5: 1-3、2-4JP6: 1-3、2-4</td><td>COM3: RS422(COM3_PIN1: RS422_TX-COM3_PIN3: RS422_TX+COM3_PIN5:RS422_RX+COM3_PIN7:RS422_RX-)</td></tr><tr><td>JP4: 5-6JP5: 1-3、2-4JP6 (No Effect)</td><td>COM3: RS485(COM3_PIN1: RS485-COM3_PIN3: RS485+)</td></tr></table>

Jumper 3\*2 Pin 2.54mm

![1\nⅡ Ⅱ\nⅡ Ⅱ\nⅡ Ⅱ\n2](.20260410-47de19e6-512/c133de132d38ce2ebd9deeb5796fb597baf5712fea0ed7bc2e39d9d9832368b9.jpg)

![1\n図 図\n図 図\n図 図\n図 図\n2](.20260410-47de19e6-512/33ec4e6014075b3d18692a8a3da82d9cf1aa6986d5ba8cbfe2c4ea67146ceaea.jpg)

# 4.3.8 COM4 RS232/485 Select Jumpers (JP7/JP18)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>JP18: 1-2JP7: 3-5、4-6(Default)</td><td>COM4: RS232(COM4_PIN1: DCDCOM4_PIN3: RXD)</td></tr><tr><td>JP18: 5-6JP7: 1-3、2-4</td><td>COM4: RS485(COM4_PIN1: RS485-COM4_PIN3: RS485+)</td></tr></table>

![1\n2](.20260410-47de19e6-512/d95957dfbb44fcf9309e112251bee52313924adcee9f73d54a97d02191b0def8.jpg)

![1\n図 図\n図 図\n図 図\n図 図\n2](.20260410-47de19e6-512/82f109de898cd5c0a8833f18ab5d7b185c1b1da22891d1ec1ab65640d506ab99.jpg)

# 4.3.9 COM3 RS422 RX Signal 120Ω Resistive Termination Select Jumper (JP15)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>Disable</td></tr><tr><td>2-3</td><td>Enable</td></tr></table>

Jumper 3\*1 Pin 2.54mm

![The image displays a vertical toolbar or menu on the left side of a screen. To the left of the toolbar is the number '1' in light grey. The toolbar consists of a column of white icons resembling documents or pages with a small grey square in the center. The top two icons in this column are enclosed within a thick orange rectangular border, indicating a selection or highlight. Below this highlighted section, a third identical icon is visible.](.20260410-47de19e6-512/2581138ce78c496677840e8fc61b13f8ef003667a57cda51c51228c9a9096ebd.jpg)

# 4.3.10 COM3 RS422 TX/RS485 Signal 120Ω Resistive Termination Select Jumper (JP16)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>Disable</td></tr><tr><td>2-3</td><td>Enable</td></tr></table>

Jumper 3\*1 Pin 2.54mm

![This image displays a cropped section of a digital interface or document. On the far left, a large, faint number '1' is visible. To its right is a vertical column of list items. A thick red rectangle highlights the top two items. Each highlighted item is a white rectangle with rounded corners containing a small square icon with the letter 'E' inside. A third, similar item is visible directly below the red box.](.20260410-47de19e6-512/eef857f67806b2e6b55484ebb81d525959df9cadfe571ee8e9a8357754831023.jpg)

# 4.3.11 COM4 RS485 RX Signal 120Ω Resistive Termination Select Jumper (JP17)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>Disable</td></tr><tr><td>2-3</td><td>Enable</td></tr></table>

Jumper 3\*1 Pin 2.54mm

![The image displays a gray number '1' in the upper left corner. To its right is a vertical column of three square icons. The top two squares are enclosed within a thick orange rectangular border. Each square contains a smaller square icon featuring a circle inside. The bottommost square is unhighlighted and unbordered.](.20260410-47de19e6-512/90e17bdc518542b96fb77cbb2c9953430fa0848451cc92cf3570ea1d1ffaf808.jpg)

# 4.3.12 Case Open Headers (J\_COPEN1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Connected</td><td>Active Case Open</td></tr><tr><td>1-2: Open</td><td>Normal</td></tr></table>

Header 2\*1 Pin 2.54mm

![The image displays the number '11' in black text on the left side. To the right of the number, there are two rounded rectangular outlines stacked vertically. Inside each rectangle is a small, dark, pixelated symbol that resembles a lowercase 'e' or a small square.](.20260410-47de19e6-512/f235431f52626cf47d44349903015da2299da196d9d9fd48abec5b4cb3f9d17a.jpg)

# 4.3.13 DNX Force Reload Disable/Enable Select Jumper (J\_DNX1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Connected</td><td>Enable</td></tr><tr><td>1-2: Open</td><td>Disable</td></tr></table>

Header 2\*1 Pin 2.54mm

![The image features the number '11' on the left side. To its right is a vertical stack of two rounded rectangles. The bottom rectangle contains the number '8', and the top rectangle contains the number '0'.](.20260410-47de19e6-512/7940e23015339ca6d62a90099117cff4a88163b8f87b9e24f06002df752b26b4.jpg)

# 4.3.14 ATX/AT Mode Jumper (J\_AT/ATX1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2 (Default)</td><td>ATX Mode</td></tr><tr><td>2-3</td><td>AT Mode</td></tr></table>

Jumper 3\*1 Pin 2.54mm

![The image displays a large, faint grey number '1' on the left side. To its right is a vertical column of three rounded rectangular boxes. The top two boxes are highlighted with a thick orange border. Inside each of the three boxes is a small icon resembling a square within a square. The bottom box is outlined in faint grey.](.20260410-47de19e6-512/f2f47d5a7c6dbb825abdeebfc0f387ec31a233dbbb5777314ee2721c93427ce4.jpg)

# 4.3.15 ME Flash Jumper (J\_ME1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2: Open (Default)</td><td>ME Protect Enable</td></tr><tr><td>1-2: Connected</td><td>ME Protect Disable</td></tr></table>

Jumper 2\*1 Pin 2.54mm

![The image displays the number '11' in a large, grey font on the left side. To the right of the number are two rectangular boxes stacked vertically, each with rounded corners. Inside the top box is a small icon resembling a grid of squares, and inside the bottom box is a similar grid icon.](.20260410-47de19e6-512/bcdd00691e9caf481f3aa899a3e88871b9acac6bd7225a72316cb003732a4615.jpg)

# 4.3.16 Watchdog Reset Enable/Disable Select Jumper (JP19)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2</td><td>Normal</td></tr><tr><td>2-3(Default)</td><td>Reset</td></tr></table>

Jumper 3\*1 Pin 2.54mm

![The image displays a large, faint gray number '1' on the left side. To its right is a vertical column of three rounded rectangular outlines. Inside each rectangle is a smaller square box containing a stylized letter 'M'. The middle and bottom rectangles are highlighted with a thick, bright orange-red border.](.20260410-47de19e6-512/d11cf31fe36e3312138518e57a16c92f78a94c7170717e32862f6f73e9bbe0bd.jpg)

# 4.3.17 Clear CMOS Jumper (CLR\_CMOS1)

![The image displays the text '1_2' in white on a black background. Below the text is a row of three square boxes. The first two boxes are dark grey with solid white circles in the center. The third box on the right is white with a black circle outline inside.](.20260410-47de19e6-512/29558a1c281b5686f4ed5726d33fd1df3dbe778eef6a1bf7fb3ff9bdb581c805.jpg)
Default

![The image displays the text '2_3' at the top in bold black font. Below this is a schematic graphic featuring a white square with a circle inside, positioned to the left of a dark grey rectangular block divided into two sections, each containing a white circle. At the bottom, the text 'Clear CMOS' appears in black sans-serif lettering.](.20260410-47de19e6-512/b2d0a9a118f61d9e63705eee78ce6801267fda5047b3d9ef3651798bfe1726b2.jpg)

1-2 : Normal
2-3 : Clear CMOS

CLR\_CMOS1 allows you to clear the data in CMOS. To clear and reset the system parameters to the default setup, please turn off the computer and unplug the power cord from the power supply. After waiting for 15 seconds, use a jumper cap to short pin 2 and pin 3 on CLR\_CMOS1 for 5 seconds. However, please do not clear the CMOS immediately after updating the BIOS. If you need to clear the CMOS right after updating the BIOS, you must first boot up the system, and then shut it down before performing the clear-CMOS action. Please do note that the date, time, and user default profile will only be cleared if the CMOS battery is removed.

# 4.3.18 Power Monitor Wafer (VOLT1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VCC5A</td><td>5</td><td>VCC5S</td></tr><tr><td>2</td><td>GND</td><td>6</td><td>VCC3.3S</td></tr><tr><td>3</td><td>GND</td><td>7</td><td>VCC12_N</td></tr><tr><td>4</td><td>VCC5PS</td><td>8</td><td>VCC12S</td></tr></table>

Jumper 8\*1 Pin 2.54mm

![1](.20260410-47de19e6-512/738ed2ad97fb59ec7b6d6b960695f474afae17a8eee2f6acf47aef3612db6945.jpg)

# 4.3.19 Power on Wafer (PSON1)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>PSON_N</td><td>2</td><td>GND</td></tr></table>

Jumper 2\*1 Pin 2.54mm

![A black and white line drawing features a rectangular outline with two small, vertically aligned squares inside it. To the right of the rectangle stands a large, bold number '1'.](.20260410-47de19e6-512/46842c083002b9398d6e742c3858d04a58c815d8ca6f187f744cb58456d69ac1.jpg)

# 4.3.20 eDP VDD Select Jumper (JC\_EDP1)

<table><tr><td>Setting</td><td>Function</td></tr><tr><td>1-2(Default)</td><td>VCC3.3</td></tr><tr><td>2-3</td><td>VCC5</td></tr></table>

![The image displays a light gray number '1' in the background. In the foreground, there is a vertical stack of three rounded rectangular boxes. Each box contains a small icon resembling a document page. The top two boxes are highlighted with a thick orange border.](.20260410-47de19e6-512/17f236f5c5ee2ec4e4ab623501e07bea2d021ed8f4ab33dfe9ca19a6e41538f7.jpg)

# 4.4 Expansion Slots

There are 6 PCI Express slots, 1 PCI slots, 2 M.2 sockets on this motherboard.

# 4.4.1 PCIe and PCI slots:

<table><tr><td></td><td>Slot1 (PCIe1)</td><td>Slot2 (PCIe2)</td><td>Slot3 (PCIe3)</td><td>Slot4 (PCIe4)</td><td>Slot5 (PCIe5)</td><td>Slot6 (PCI)</td><td>Slot7 (PCIe6)</td></tr><tr><td>Source</td><td>CPU</td><td>CPU</td><td>PCH</td><td>CPU</td><td>PCH</td><td>PCI bridge</td><td>PCH</td></tr><tr><td>Bandwidth</td><td>PCIe 4.0</td><td>PCIe 4.0</td><td>PCIe 3.0</td><td>PCIe 4.0</td><td>PCIe 4.0</td><td>PCI</td><td>PCIe 4.0</td></tr><tr><td>Lane Config</td><td>X8</td><td>X4</td><td>X4</td><td>X8</td><td>X4</td><td>PCI</td><td>X4</td></tr></table>

# 4.4.2 M.2 sockets:

M.2 Key-M (M\_2\_PCIESSD\_M1)

<table><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>GND</td><td>+3.3V</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>+3.3V</td><td>4</td></tr><tr><td>5</td><td>PERn3</td><td>NA</td><td>6</td></tr><tr><td>7</td><td>PERp3</td><td>NA</td><td>8</td></tr><tr><td>9</td><td>GND</td><td>LED</td><td>10</td></tr><tr><td>11</td><td>PETn3</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>PETp3</td><td>+3.3V</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>16</td></tr><tr><td>17</td><td>PERn2</td><td>+3.3V</td><td>18</td></tr><tr><td>19</td><td>PERp2</td><td>NA</td><td>20</td></tr><tr><td>21</td><td>GND</td><td>NA</td><td>22</td></tr><tr><td>23</td><td>PETn2</td><td>NA</td><td>24</td></tr><tr><td>25</td><td>PETp2</td><td>NA</td><td>26</td></tr><tr><td>27</td><td>GND</td><td>NA</td><td>28</td></tr><tr><td>29</td><td>PERn1</td><td>NA</td><td>30</td></tr><tr><td>31</td><td>PERp1</td><td>NA</td><td>32</td></tr><tr><td>33</td><td>GND</td><td>NA</td><td>34</td></tr><tr><td>35</td><td>PETn1</td><td>NA</td><td>36</td></tr><tr><td>37</td><td>PETp1</td><td>DEVSLP</td><td>38</td></tr><tr><td>39</td><td>GND</td><td>SMB_CLK</td><td>40</td></tr><tr><td>41</td><td>PERn0</td><td>SMB_DATA</td><td>42</td></tr><tr><td>43</td><td>PERp0</td><td>NA</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>NA</td><td>46</td></tr><tr><td>47</td><td>PETn0</td><td>NA</td><td>48</td></tr><tr><td>49</td><td>PETp0</td><td>PERST#</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>CLKREQ#</td><td>52</td></tr><tr><td>53</td><td>PEFCLKn</td><td>WAKE#</td><td>54</td></tr><tr><td>55</td><td>PEFCLKp</td><td>NA</td><td>56</td></tr><tr><td>57</td><td>GND</td><td>NA</td><td>58</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td>67</td><td>NA</td><td>NA</td><td>68</td></tr><tr><td>69</td><td>PEDET</td><td>+3.3V</td><td>70</td></tr><tr><td>71</td><td>GND</td><td>+3.3V</td><td>72</td></tr><tr><td>73</td><td>GND</td><td>+3.3V</td><td>74</td></tr><tr><td>75</td><td>GND</td><td></td><td></td></tr></table>

M.2 Key-E (M.2\_KEYE\_WLAN1)

<table><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>GND</td><td>+3VSB</td><td>2</td></tr><tr><td>3</td><td>USB_D+</td><td>+3VSB</td><td>4</td></tr><tr><td>5</td><td>USB_D-</td><td>NA</td><td>6</td></tr><tr><td>7</td><td>GND</td><td>NA</td><td>8</td></tr><tr><td>9</td><td>CNV_WGR_D1-</td><td>CNV_RF_RESET</td><td>10</td></tr><tr><td>11</td><td>CNV_WGR_D1+</td><td>NA</td><td>12</td></tr><tr><td>13</td><td>GND</td><td>MODEM_CLKREQ</td><td>14</td></tr><tr><td>15</td><td>CNV_WGR_D0-</td><td>NA</td><td>16</td></tr><tr><td>17</td><td>CNV_WGR_D0+</td><td>GND</td><td>18</td></tr><tr><td>19</td><td>GND</td><td>NA</td><td>20</td></tr><tr><td>21</td><td>CNV_WGR_CLK-</td><td>CNV_BRI_RSP</td><td>22</td></tr><tr><td>23</td><td>CNV_WGR_CLK+</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td>33</td><td>GND</td><td>CNV_BGI_DT</td><td>32</td></tr><tr><td>35</td><td>PETp</td><td>CNV_RGI_RSP</td><td>34</td></tr><tr><td>37</td><td>PETn</td><td>CNV_BRI_DT</td><td>36</td></tr><tr><td>39</td><td>GND</td><td>NA</td><td>38</td></tr><tr><td>41</td><td>PERp</td><td>NA</td><td>40</td></tr><tr><td>43</td><td>PERn</td><td>NA</td><td>42</td></tr><tr><td>45</td><td>GND</td><td>NA</td><td>44</td></tr><tr><td>47</td><td>PEFCLKp</td><td>NA</td><td>46</td></tr><tr><td>49</td><td>PEFCLKn</td><td>NA</td><td>48</td></tr><tr><td>51</td><td>GND</td><td>SUSCLK</td><td>50</td></tr><tr><td>53</td><td>CLKREQ#</td><td>PERST0#</td><td>52</td></tr><tr><td>55</td><td>WAKE#</td><td>W_DISABLE1#</td><td>54</td></tr><tr><td>57</td><td>GND</td><td>W_DISABLE2#</td><td>56</td></tr><tr><td>59</td><td>CNV_WT_D1-</td><td>SMB_DATA</td><td>58</td></tr><tr><td>61</td><td>CNV_WT_D1+</td><td>SMB_CLK</td><td>60</td></tr><tr><td>63</td><td>GND</td><td>NA</td><td>62</td></tr><tr><td>65</td><td>CNV_WT_D0-</td><td>CLKIN_XTAL_LCP</td><td>64</td></tr><tr><td>67</td><td>CNV_WT_D0+</td><td>NA</td><td>66</td></tr><tr><td>69</td><td>GND</td><td>NA</td><td>68</td></tr><tr><td>71</td><td>CNV_WT_CLK-</td><td>NA</td><td>70</td></tr><tr><td>73</td><td>CNV_WT_CLK+</td><td>+3VSB</td><td>72</td></tr><tr><td>75</td><td>GND</td><td>+3VSB</td><td>74</td></tr></table>

# 5 Driver Installation

Download the requisite drivers for your system from the IMB-C47 product page:

https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/ATXMotherboards/IMB-C47

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# 6 BIOS Setup

# 6.1 Menu Structure

This section presents the primary menus of the BIOS (UEFI) Setup Utility. Use the following table as a quick reference forthe contents of the BIOS Setup Utility. The subsections describe the submenus and options for each menu item.

Options to enter BIOS Setup Utility:

• Press [Del] during POST (Power-On-Self-Test)

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td></tr><tr><td>Sets up the system time/date and displays the system information:- BIOS Information- Memory Information- System Date- System Time</td><td>Contains advanced system configurations, including:► CPU Configuration► PCH-FW Configuration► Trusted Computing► ACPI Settings► Super IO Configuration► Hardware Monitor► Power Control► S5 RTC Wake Settings► USB Configuration► Network Stack Configuration► NVMe Configuration</td><td>Displays Hardware Status info, including:► System Agent (SA) Configuration► PCH-IO Configuration</td></tr><tr><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>Changes or clears the supervisor/user password for the system:- Administrator Password- User Password► Secure Boot</td><td>Configures the boot settings and boot priority for available devices:- Setup Prompt Timeout- Bootup Num Lock State- Full Screen LogoFIXED BOOT ORDER Priorities- Boot Option #X</td><td>Exits the BIOS Setup Utility while saving or discard the changes made:Save Options- Save Changes and Exit- Discard Changes and Exit- Save Changes and Reset- Discard Changes and Reset- Save Changes- Discard ChangesDefault Options- Restore Defaults- Save as User Defaults- Restore User DefaultsBoot Override- BIOS: Built-in EFI shellLaunch EFI Shell from filesystem device</td></tr></table>

# 6.2 Main Menu

Upon entering the BIOS Setup Utility, the Main Menu is displayed, providing read-only information about your system and also allows you to set the System Date and Time. Refer to the screenshots and tables below for details of the submenus and settings.

<table><tr><td>Feature</td><td>Options</td></tr><tr><td colspan="2">BIOS Information</td></tr><tr><td>BIOS Vendor</td><td>Info only</td></tr><tr><td>Core Version</td><td>Info only</td></tr><tr><td>Compliancy</td><td>Info only</td></tr><tr><td>Project Version</td><td>IMB-C47_x.xx.xx</td></tr><tr><td>Build Date and Time</td><td>Info only</td></tr><tr><td>Access Level</td><td>Info only</td></tr><tr><td colspan="2">Memory Information</td></tr><tr><td>Total Memory</td><td>Info only</td></tr><tr><td>Memory Frequency</td><td>Info only</td></tr><tr><td>System Date</td><td>xxx mm/dd/yyyy</td></tr><tr><td>System Time</td><td>hh:mm:ss</td></tr></table>

# 6.3 Advanced

This menu contains the following information:

<table><tr><td colspan="2">Feature</td></tr><tr><td>▶ CPU Configuration</td><td>▶ Power Control</td></tr><tr><td>▶ PCH-FW Configuration</td><td>▶ S5 RTC Wake Settings</td></tr><tr><td>▶ Trusted Computing</td><td>▶ USB Configuration</td></tr><tr><td>▶ ACPI Settings</td><td>▶ Network Stack Configuration</td></tr><tr><td>▶ Super IO Configuration</td><td>▶ NVME Configuration</td></tr><tr><td>▶ Hardware Monitor</td><td>▶</td></tr></table>

# 6.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Efficient-core Information</td><td>Displays the E-core Information.</td></tr><tr><td>Performance-core Information</td><td>Displays the P-core Information.</td></tr><tr><td>ID</td><td>Displays the Processor ID.</td></tr><tr><td>Brand String</td><td>Displays the Brand String.</td></tr><tr><td>VMX</td><td>VMX (Virtual-Machine Extensions) supported or not.</td></tr><tr><td>SMX/TXT</td><td>SMX (Safer Mode Extensions) /TXT (Trusted Execution Technology) Supported or Not.</td></tr><tr><td>Intel (R) SpeedStep(tm)</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Intel (R) Speed Shift Technology</td><td>Enables or disables Intel (R) Speed Shift Technology Support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Turbo Mode</td><td>Enables or disables processor Turbo Mode (requires EMTTM enabled too). Auto means enabled.</td></tr><tr><td>C states</td><td>Enables or disables CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Enhanced C-states</td><td>Enables or disables C1E. When enabled, CPU will switch to minimum speed when allcores enter C-State.</td></tr><tr><td>Package C State Limit</td><td>Maximum Package C State Limit Setting. CPU Default: Leaves to factory default value. Auto: Initializes to deepest available Package C State Limit.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Hyper-Threading</td><td>Enables or disables Hyper-Threading Technology.</td></tr></table>

# 6.3.2 PCH-FW Configuration

Configure Management Engine Technology Parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>ME State</td><td>Displays the ME Firmware information.</td></tr></table>

# 6.3.3 Trusted Computing

Trusted Computing Settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>TPM 2.0 Device information</td><td>Displays the information of the TPM 2.0 device.</td></tr><tr><td>Security Device Support</td><td>Enables or Disables BIOS support for security devices. The O.S. will not show security devices. The TCG EFI protocol and INT1A interfaces will not be available.</td></tr></table>

# 6.3.4 ACPI Settings

Set ACPI (Advanced Configuration and Power Management Interface) Parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Enable Hibernation</td><td>Enables or disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Selects the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr></table>

# 6.3.5 Super IO Configuration

System Super IO Chip Parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>COM1-6</td><td>Sets Parameters of Serial Port 1-6.The options after entering the interface settings above are as follows.Serial Port: Enable or Disable Serial Port (COM).Device Settings: Displays the Current Device Settings.Change Settings: If the board is supported, this menu shows. Select an optimal setting for Super IO devices.</td></tr><tr><td>CHASSIS OPEN</td><td>Enables or disables the CHASSIS OPEN function.</td></tr></table>

# To Set Up the Chassis Open Detection:

1) Select “Advanced – Super IO Configuration - CHASSIS OPEN” (This menu shows that only this function is supported);
2) Set the item to “Enabled”.

Sound the alarm if the chassis is opened; stop the alarm when closed.

When the open-box detection cap is shorted, the chassis is considered to have been compromised. The POST interface will prompt for chassis intrusion alarms, and the status record needs to be cleared to close the alarm.

# Clear Chassis Open Status:

1) In the BIOS Setup Utility, press the F3 key and then the Enter key to load the optimization default values. Save & exit to clear the out-of-box status record.

# 6.3.6 Hardware Monitor

Monitor hardware status.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PC Health status</td><td>Displays the current of PC Health Status.</td></tr><tr><td>► Fan function</td><td>Fan function settings.To Set Up the Fan Control:1) Select “Advanced - Hard Monitor - Fan Function” (This menu shows that only this function is supported);2) Select the fan to set up, such as “CPU_FAN1 Mode”. Select the operating mode for this fan: Full on Mode, Automatic Mode, or Manual Mode.3) After selecting manual mode, input the PWM value (range 0-255) to specify the fan speed.4) After selecting Automatic mode, you will find options for Fan off Temperature Limit, Fan start Temperature Timit, Fan start PWM, and PWM SLOPE SETTING.Due to differences in fan performance, the actual performance of smart fans may differ from the set values, it is generally recommended to set the PWM SLOPE SETTING to 8 PWM to ensure that the fan speed correlates with the temperature rise.</td></tr><tr><td>CHASSIS OPEN</td><td>Sound the alarm if chassis is opened; Stop the alarm when closed.To Set Up the Chassis Open Detection:1) Select “Advanced – Hardware Monitor - CHASSIS OPEN” (This menu shows that only this function is supported).2) Set the item to “Enabled”.When the open-box detection cap is shorted, the chassis is considered to have been compromised. The POST interface will prompt for chassis intrusion alarms, and the status record needs to be cleared to close the alarm.To Clear the Chassis Open Status:In the BIOS Setup Utility, press the F3 key and enter key to load the optimization default value. Then save &amp; exit to clear the out-of-box status record.</td></tr></table>

# 6.3.7 Power Control

Power Button Control Settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PowerOn After PowerFail</td><td>Specify which state to enter when power is re-applied after a power failure (G3 state).</td></tr><tr><td>Soft-Off by PWR-BTTN</td><td>Soft-Off by PWR-BTTN. Instant-Off/Delay 4 Sec.</td></tr><tr><td>PCIE OOR FIXED Enabled</td><td>Enables or disables PCIE OOR FIXED.</td></tr></table>

# Set Up Power-on Self:

1) Select “Advanced - Power Control - PowerOn After PowerFail”.
2) Change “PowerOn After PowerFail” value: Power Off, Power On, or Last State.

# 6.3.8 S5 RTC Wake Settings

Enable system to wake from S5 using RTC alarm.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Wake system from S5</td><td>Enables or disables System wake on alarm event. Select Fixed Time for the system to wake at the specified hr::min::sec. Select Dynamic Time for the system to wake at the the current time + the specified increase in minute(s).</td></tr></table>

# To Set Up the Timed Power On:

1) Select “Advanced - S5 RTC Wake Settings - Wake system from S5”;
2) Change it from Disabled to Fixed Time;
3) Set the desired time by customizing the “Wake up day, Wake up hour, Wake up minute, wake up second” that appear. For example, day: 2, hour: 13, minute: 0, second: 0 means the system will boot on the 2nd of each month at 13:00. When day is set to 0, it means the system will power on every day at the specified time.

# 6.3.9 USB Configuration

USB Configuration parameters.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>USB Module Version</td><td>Displays the USB Module version.</td></tr><tr><td>USB Controllers</td><td>Displays the USB controllers.</td></tr><tr><td>USB Devices</td><td>Displays the USB devices.</td></tr><tr><td>Legacy USB Support</td><td>Enables Legacy USB support. The AUTO option disables legacy support if no USB devices are connected. The DISABLE option keeps USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>Enables or disables USB Mass Storage Driver support.</td></tr><tr><td>USB hardware delays and time-outs</td><td>USB transfer time-out: The time-out value for control, bulk, and interrupt transfers. Device reset time-out: The USB mass storage device Start Unit command time-out. Device power-up delay: The maximum time the device will take before it properly reports itself to the host controller. ‘Auto’ uses default value: for a Root port, it is 100ms, for a Hub port, the delay is taken from the hub descriptor.</td></tr></table>

# 6.3.10 Network Stack Configuration

Network Stack Settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Network Stack</td><td>Enables or disables BIOS Network Stack</td></tr></table>

# Open BIOS PXE:

1) Select “Advanced - Network Stack Configuration”.
2) Set Network Stack or BIOS PXE to Enabled.

# 6.3.11 NVME Configuration

NVME Device options settings.

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>NVMe Configuration</td><td>Displays the NVME device information</td></tr></table>

# 6.4 Chipset

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>► System Agent (SA) Configuration</td><td>System Agent (SA) Parameters.</td></tr><tr><td>► PCH-IO Configuration</td><td>PCH Parameters.</td></tr></table>

# 6.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>▸ Memory Configuration</td><td>Memory Configuration Parameters.</td></tr><tr><td>▸ Graphics Configuration</td><td>Graphics Configuration.</td></tr><tr><td>▸ VMD setup menu</td><td>VMD Configuration Settings.</td></tr><tr><td>▸ PCI Express Configuration</td><td>PCI Express Configuration Settings.</td></tr></table>

# 6.4.1.1 Memory Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Memory Information</td><td>Displays the Memory RC version, speed, Timings, etc</td></tr></table>

6.4.1.2 Graphics Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Primary Display</td><td>Select which of IGFX/PEG/PCI graphics devices should be the primary display, or select HG for hybrid graphics.</td></tr><tr><td>Internal Graphics</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enables or disables above 4GB memory-mapped IO BIOS assignment. This is enabled automatically when the aperture size is set to 2048 MB.</td></tr><tr><td>PCIE Resizable BAR Support</td><td>Enables or disables PCIE resizable BAR support.</td></tr></table>

6.4.1.3 VMD setup menu

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Enable VMD controller</td><td>Enables or disables to VMD controller.</td></tr></table>

6.4.1.4 PCI Express Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCIE_4X_SLOT1</td><td>PCI Express Root Port Settings.</td></tr><tr><td>PCIE_16X_SLOT1</td><td>PCI Express Root Port Settings.</td></tr><tr><td>PCIE_16X_SLOT2</td><td>PCI Express Root Port Settings.</td></tr></table>

6.4.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>PCI Express Configuration settings.</td></tr><tr><td>SATA Configuration</td><td>SATA Device Configuration settings.</td></tr><tr><td>LAN1 Controller</td><td>Enables or disables onboard NIC.</td></tr><tr><td>Wake on LAN Enable</td><td>Enables or disables integrated LAN to wake the system.</td></tr></table>

6.4.2.1 PCI Express Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>PCI Express Root Port Settings.▸ LAN2▸ M.2_KEYE_WLAN1▸ PCI1▸ PCIE_4X_SLOT2▸ M.2_PCIESSD_M1▸ PCIE_4X_SLOT3▸ PCIE_4X_SLOT4</td></tr></table>

6.4.2.2 SATA Configuration

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Enables or disables SATA devices.</td></tr><tr><td>SATA Mode Selection</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>M.2_KEYM_SSD1</td><td>Displays SSD Information.</td></tr><tr><td>Serial ATA Port X</td><td>Enables or Disables SATA ports.</td></tr></table>

# 6.5 Security

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Sets Administrator Password.</td></tr><tr><td>User Password</td><td>Sets User Password.</td></tr><tr><td>▶ Secure Boot</td><td>Secures Boot configuration.</td></tr></table>

When you set up an administrator password, it is recommended that you enter the administrator password when you access the BIOS setup program to avoid encountering unavailable BIOS information or settings due to insufficient user rights. (no password is entered as a user).

When you set a user password, you must use the user password to access the BIOS setup program, which means that you need to enter the user password when booting the operating system (using the BIOS boot feature).

# To Set/Change the Administrator Password:

1) Select “Security - Administrator Password”.

2) Enter the password you want to set in the “Create New Password” window and press Enter. You will need to enter your current password to confirm when changing your administrator password before accessing the “Create New Password” window.

3) Enter the password you want to set again to make sure it is entered correctly.

When you want to delete an administrator password, you should change the password by pressing carriage return directly in the “Create New Password” window to clear the password.

# To Set/Change the User Password:

1) Select “Security - User Password”.

2) Enter the password you want to set in the “Create New Password” window that appears and press Enter. You will need to enter the current password to confirm when changing the user's password before accessing the “Create New Password” window.

3) Enter the password you want to set again to make sure it is entered correctly.

When you want to delete a user password, you should change the password by pressing carriage return directly in the “Create New Password” window to clear the password.

# 6.5.1 Secure Boot

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Secure Boot</td><td>Secure Boot feature is active if Secure Boot is enabled, Platform Key (PK) is enrolled, and the system is in user mode. The mode change requires platform reset.</td></tr><tr><td>Secure Boot Mode</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr></table>

# 6.6 Boot

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td>Setup Prompt Timeout</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup Num Lock State</td><td>Select the keyboard Num Lock state.</td></tr><tr><td>Full Screen Logo</td><td>Enables or disables Full Screen Logo option.</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Displays Boot order and allow to set Hard Drive/USB/XXX boot order in this group.</td></tr><tr><td>▶ BIOS USB KeyDrive BBSPriorities</td><td>Sets the system boot order.</td></tr></table>

# Set Boot Sequence:

1) Select the “Boot” menu page.
2) Change “Boot Option #1” to the desired device.
3) If there are more than one similar device, such as multiple hard drives, enter “Hard Disk Drive BBS Priorities” and change the boot order priority among the drives.

When the Boot page has the Boot mode select option, it is recommended that the value of “dual” so that both Legacy and BIOS boot projects can be booted. BIOS boot items will be filtered when selected for Legacy, and legacy boot items will be filtered when selected as BIOS.

# 6.7 Save & Exit

This menu contains the following information:

<table><tr><td>Feature</td><td>Description</td></tr><tr><td colspan="2">Save Options</td></tr><tr><td>Save Changes and Exit</td><td>Exits system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Exits system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Resets the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Resets the system setup without saving any changes.</td></tr><tr><td>Save Changes</td><td>Saves changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Discards changes done so far to any of the setup options.</td></tr><tr><td colspan="2">Default Options</td></tr><tr><td>Restore Defaults</td><td>Restores/Loads default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>Saves the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Restore sthe User Defaults to all the setup options.</td></tr><tr><td colspan="2">Boot Override</td></tr><tr><td>BIOS: Built-in EFI shell</td><td>Launches BIOS Built-in BIOS Shell.</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td>Attempts to launch EFI Shell application (Shell.efi) from one of the available filesystem devices.</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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