# ETX

# ETX-NR667

# User's Manual

![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.31-en/901e56352b06954705b7c9fba4051a8ca439bd961b69c09a0b00d1a9d124d151.jpg)

Manual Revision: 2.31

Revision Date: January 3, 2012

Part Number: 50-1J014-1050

Revision History

<table><tr><td>Revision</td><td>Date</td><td>Change(s)</td></tr><tr><td>2.00</td><td>2008/02/29</td><td>Initial Release</td></tr><tr><td>2.10</td><td>2008/06/27</td><td>Correct SMBus ResourcesAdd Signal DescriptionsAdjust layout</td></tr><tr><td>2.20</td><td>2008/08/20</td><td>Major update to BIOS section</td></tr><tr><td>2.21</td><td>2008/11/12</td><td>Correct Signal Descriptions, correct BIOS grammar</td></tr><tr><td>2.30</td><td>2009/01/19</td><td>Update specifications to A3 board version (change to ALC 262 codec, remove onboard POST code LEDs)</td></tr><tr><td>2.31</td><td>2012/01/03</td><td>Update LVDS and LAN PHY specification</td></tr></table>

# Table of Contents

# Preface 5

# 1 Introduction....7

1.1 Description 7

# 2 Specifications 8

2.1 General 8

2.2 Video 8

2.3 Audio 9

2.4 LAN 9

2.5 Multi I/O 9

2.6 Super I/O 9

2.7 Mechanical and Environment 9

2.8 Power Consumption....10

# 3 Function Diagram 12

# 4 Mechanical Dimensions 13

# 5 Watchdog Timer (WDT) 14

# 6 Pin-out and Signal Descriptions 17

6.1 Connector Locations 17

6.2 Pin Compatibility 17

6.3 Pin Definitions 18

6.4 Signal Descriptions 23

# 7 System Resources....32

7.1 System Memory Map 32

7.2 Direct Memory Access Channels 32

7.3 I/O Address Map 33

7.4 Interrupt Request (IRQ) Lines 35

7.5 PCI Configuration Space Map 36

7.6 PCI Interrupt Routing Map 37

7.7 System Management Bus (I2C-compatible) 37

# 8 BIOS Setup Utility 38

8.1 Starting the BIOS 38
8.2 Main Setup 42
8.3 Advanced BIOS Setup 43
8.4 Power Management 60
8.5 Boot Setup 65
8.6 Security Setup 68
8.7 Exit Menu 71

# 9 BIOS Checkpoints, Beep Codes....73

9.1 Bootblock Initialization Code Checkpoints 74
9.2 Bootblock Recovery Code Checkpoints 75
9.3 POST Code Checkpoints 76
9.4 OEM POST Error Checkpoints 78
9.5 DIM Code Checkpoints 78
9.6 ACPI Runtime Checkpoints....79
9.7 Boot Block Beep Codes 80
9.8 POST BIOS Beep Codes 80
9.9 Troubleshooting POST BIOS Beep Codes 81

# Appendix A: Heatspreaders and Heatsinks 82

A.1 Carrier Board ETX connector heights (Hirose FX8/FX8C Receptacles) 82
A.2 Heatspreader Introduction....83
A.3 Mounting procedures 85
A.4 Standoff types 86
A.5 Heatspreader Dimensions for HTS-NR667-B (threaded standoffs) 87
A.6 Heatspreader Dimensions for HTS-NR667-BT (through-hole standoffs) 88
A.7 THSF-NR667 Series: High Performance Heatsink with Fan 89
A.8 THS-NR667 Series: Low Profile Heatsinks 90
A.9 Dimensions for THS-NR667 Series 91

# Important Safety Instructions 94

# Getting Service 96

# Preface

# Copyright 2009-12 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

AMIBIOS $^{®}$ 8 is a registered trademark of American Megatrends, Inc. ETX $^{®}$ is a registered trademark of Kontron Embedded Modules GmbH.

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image features a graphic icon of a piece of lined paper with a large red checkmark drawn on it. Below the paper graphic is the text 'NOTE:' in black capital letters.](.31-en/e79bd2cdf3caa297b239e2a5c9a1ad119f944583ee149cb7f5f00ad090b47908.jpg)

Additional information, aids, and tips that help users perform tasks.

![The image displays a standard warning sign featuring a yellow triangle with a black border. Inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION:' is printed in black capital letters.](.31-en/d465eb3e081453501311430ba84382920fe3fcde7bb849aae96da1789e9a79e9.jpg)

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a triangular warning sign with a red background and a white border. Centered inside the triangle is a white exclamation mark. Below the triangle, the word 'WARNING:' is written in black, capital letters.](.31-en/be9df3f9de912cb4e687a942726805c21ae03f6ac69116f801dd8376e2c26a49.jpg)

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# 1 Introduction

# 1.1 Description

ETX-NR667 is an ETX v3.02 compliant module specially designed to facilitate speedy development of semi custom designs. ETX is an open standard that targets embedded OEM projects. An ETX core combined with a custom made carrier board represents a value solution that allows OEM customers to get to the market fast. The new ETX v3.02 specification adds SATA support to ETX in the form of two connectors on the module itself, allowing the ETX module 100% board-to-board interface compatible with baseboards made under the earlier ETX v2.xx specification.

The ETX-NR667 combines a Celeron M, Core Duo, or Core 2 Duo CPU with a Intel 945GME/ICH7M chipset.

The Intel 945GME includes a VGA controller that supports CRT VGA and optional TV-out functionality. The chipset's SDVO provides 18/24-bit dual channel LVDS support.

Furthermore, the module offers dual-port SATA and an EIDE controller supporting both PIO and UDMA modes, four USB ports, two serial ports, one parallel port (SPP/ECP/EPP) shared with FDD, one PS/2 keyboard/mouse interface, AC'97 audio interface, and power management functionality. Additionally onboard is an 10/100Base-T Ethernet port, and an HD Audio Codec.

The ETX-NR667 supports embedded features such as RS-232 console redirection, CMOS EEPROM backup for BIOS settings for battery-less operation and PXE (boot over LAN), operation over battery power, and extended power modes such as S0, S3, S4, and S5.

![The image displays the Intel Core 2 Duo badge logo. It features a white upper section with the blue 'intel®' logo. Below that, the text 'Core™ 2' is printed in blue. The bottom section has a blue background containing the white text 'Duo' on the left and 'inside™' on the right.](.31-en/40fde3c114235f64f4f7ce2635101b74447aba7c8db9fa2a0bdf3c6a2d6db904.jpg)

![The image features the Intel Core Duo logo. The upper section shows a white background with a blue oval ring surrounding the word 'intel®' in blue lowercase letters. The lower section is a dark blue rectangle containing the word 'Core™' in large white letters. Below that, 'Duo' is written in white, followed by 'inside™' in smaller, italicized white text.](.31-en/222a1dda918d6db7abf2fba294b6be0d78bd7c30a0c919cf26cef1c56b1f65c8.jpg)

![The image displays a rectangular sticker with rounded corners. The top portion features a white background with the blue 'intel' logo enclosed in a swoosh. The bottom portion has a light blue background displaying the text 'Celeron®M' in a dark blue serif font. Below that is the word 'inside™' in a smaller, dark blue italicized sans-serif font.](.31-en/f8fa2138d4f5779bc97989956e675612ed4c559e21632dbe3c9bb28d2340d57f.jpg)

![ADLINK\nGREEN\nRoHS Compliant](.31-en/b3aea609835e579f01643a6ce3c1623532054674b07ea7ed8ab9930a0eb08f7d.jpg)

ETX-NR667 is an RoHS compliant and lead-free product.

# 2 Specifications

# 2.1 General

▶ CPU (BGA Type):

# Merom Core

Intel Core 2 Duo L7400 LV 1.5 GHz with 4 -MByte L2 cache, 17 W (Low Voltage)

Intel Core 2 Duo U7500 ULV 1.06 GHz with 2 -MByte L2 cache, 10 W (Ultra Low Voltage)

# Yonah Core

Intel Core Duo L2400 1.66 GHz with 2-MByte L2 cache LV 15 W (Low Voltage)

Intel Celeron M 440 1.86 GHz, with 1-MByte L2 cache 27 W

Intel Celeron M 423 ULV 1.06 GHz, with 1-MByte L2 cache 5.5 W (Ultra Low Voltage)

▶ Memory: single SO-DIMM socket memory, for max 2 GB of non-ECC, unbuffered, 533/667 MHz DDR2 memory
Chipset: Intel 945GME Express Graphic Memory Controller Hub and Intel I/O Controller Hub 7 Mobile (ICH7-M)
▶ L2 Cache: 1 MB (Celeron M), 2/4 MB (Core 2 Duo)
▶ BIOS: AMIBIOS8 with CMOS backup feature
OS Support: Windows XP, Windows Vista, Windows XPe, WinCE 6.0, Linux.
▶ Hardware Monitor: supply voltages and CPU temperature
▶ Watchdog Timer: programmable timer ranges to generate RESET
▶ Expansion Busses:

- 32-bit PCI 2.3 Masters at 33 MHz
- ISA 16-bit
- SMBus/I2C

# 2.2 Video

Chipset: 945GME GMCH integrated chipset supports dual independent displays
▶ VGA Interface: analog support up to 2048 x 1536 resolution
LVDS Interface: dual channel 18/24-bit from SDVO
▶ TV-out (optional): NTSC/PAL up to 1024 x 768 resolution, HDTV 480p/720p/1080i/1080p modes support (without Macrovision)

# 2.3 Audio

Chipset: integrated in Intel I/O Controller Hub 7 Mobile (ICH7M)
▶ Audio Codec: Realtek ALC 262 HDA compatible

# 2.4 LAN

Chipset: PCIe x1 Realtek RTL8111C
▶ Interface: 10/100 Mbps with Wake-on-LAN and Alert on LAN support

# 2.5 Multi I/O

▶ IDE (PATA): dual channel IDE with UDMA 33 support
▶ SATA: two-port SATA 3 Gb/s support with connectors on module
▶ USB: supports up to four ports v. 2.0

# 2.6 Super I/O

Chipset: W83627HG
▶ Serial: two high speed RS-232C ports (COM1/COM2)
IrDA: supports SIR IrDA 1.1 compliant
▶ Parallel: SPP, EPP, and ECP mode (pin out shared with FDD)
▶ FDD: one drive (pin out shared with LPT)
▶ Keyboard & Mouse: one PS/2 keyboard and one PS/2 mouse

# 2.7 Mechanical and Environment

▶ Standard Operating Temperature: 0°C to 60°C
▶ Storage Temperature: -40°C to 80°C
▶ Operating Humidity: 5% to 90% Non condensing
ETX Compatibility: ETX Specification 3.02 (SATA connectors on module)

# 2.8 Power Consumption

▶ Input Power: AT mode and ATX mode
▶ Power Management: ACPI 3.0 compliant with battery support
▶ Power States: supports S0, S1, S3, S4, S5

![Yellow lightning bolt symbol on white background (no text or symbols)](.31-en/cbb97811134a7f33ddaeb916b546046d80d70a85e73eff8aa03ee32a860267e1.jpg)

<table><tr><td rowspan="2"></td><td colspan="2">Core 2 Duo U7500, 533MHz</td><td colspan="2">Core 2 Duo L7400, 667MHz</td><td colspan="2">Core Duo T2500, 667MHz</td></tr><tr><td>+5V</td><td>Total</td><td>+5V</td><td>Total</td><td>+5V</td><td>Total</td></tr><tr><td colspan="7">DOS</td></tr><tr><td>Current (A)</td><td>2.92A</td><td>2.92A</td><td>3.62A</td><td>3.62A</td><td>5.28A</td><td>5.28A</td></tr><tr><td>Watts (W)</td><td>14.6W</td><td>14.6W</td><td>18.1W</td><td>18.1W</td><td>26.4W</td><td>26.4W</td></tr><tr><td colspan="7">Linux, Idle</td></tr><tr><td>Current (A)</td><td>2.65A</td><td>2.65A</td><td>2.41A</td><td>2.41A</td><td>3.92A</td><td>3.92A</td></tr><tr><td>Watts (W)</td><td>13.25W</td><td>13.25W</td><td>12.05W</td><td>12.05W</td><td>19.6W</td><td>19.6W</td></tr><tr><td colspan="7">Windows XP, Idle</td></tr><tr><td>Current (A)</td><td>2.69A</td><td>2.69A</td><td>3.12A</td><td>3.12A</td><td>3.91A</td><td>3.91A</td></tr><tr><td>Watts (W)</td><td>13.45W</td><td>13.45W</td><td>15.6W</td><td>15.6W</td><td>19.55W</td><td>19.55W</td></tr><tr><td colspan="7">Windows XP, CPU 100% Usage</td></tr><tr><td>Current (A)</td><td>3.98A</td><td>3.98A</td><td>5.36A</td><td>5.36A</td><td>9.48A</td><td>9.48A</td></tr><tr><td>Watts (W)</td><td>19.9W</td><td>19.9W</td><td>26.8W</td><td>26.8W</td><td>47.4W</td><td>47.4W</td></tr><tr><td colspan="7">Windows XP, Standby</td></tr><tr><td>Current (A)</td><td>1.97A</td><td>1.97A</td><td>2.21A</td><td>2.21A</td><td>2.08A</td><td>2.08A</td></tr><tr><td>Watts (W)</td><td>9.85W</td><td>9.85W</td><td>11.05W</td><td>11.05W</td><td>10.4W</td><td>10.4W</td></tr><tr><td colspan="7">Windows XP, Suspend-to-RAM (S3)</td></tr><tr><td>Current (A)</td><td>141.9mA</td><td>141.9mA</td><td>143.7mA</td><td>143.7mA</td><td>138.6mA</td><td>138.6mA</td></tr><tr><td>Watts (W)</td><td>0.7095W</td><td>0.7095W</td><td>0.7185W</td><td>0.7185W</td><td>0.68A</td><td>0.68A</td></tr></table>

Power Consumption (cont'd):

<table><tr><td rowspan="2"></td><td colspan="2">Core Duo L2400, 667MHz</td><td colspan="2">Celeron M 440, 533MHz</td><td colspan="2">Celeron M 423, 533MHz</td></tr><tr><td>+5V</td><td>Total</td><td>+5V</td><td>Total</td><td>+5V</td><td>Total</td></tr><tr><td colspan="7">DOS</td></tr><tr><td>Current (A)</td><td>3.45A</td><td>3.45A</td><td>4.25A</td><td>4.25A</td><td>2.85A</td><td>2.85A</td></tr><tr><td>Watts (W)</td><td>17.25W</td><td>17.25W</td><td>21.25W</td><td>21.25W</td><td>14.25W</td><td>14.25W</td></tr><tr><td colspan="7">Linux, Idle</td></tr><tr><td>Current (A)</td><td>2.76A</td><td>2.76A</td><td>3.45A</td><td>3.45A</td><td>2.48A</td><td>2.48A</td></tr><tr><td>Watts (W)</td><td>13.8W</td><td>13.8W</td><td>17.25W</td><td>17.25W</td><td>12.4W</td><td>12.4W</td></tr><tr><td colspan="7">Windows XP, Idle</td></tr><tr><td>Current (A)</td><td>2.81A</td><td>2.81A</td><td>3.64A</td><td>3.64A</td><td>2.6A</td><td>2.6A</td></tr><tr><td>Watts (W)</td><td>14.05W</td><td>14.05W</td><td>18.2W</td><td>18.2W</td><td>13W</td><td>13W</td></tr><tr><td colspan="7">Windows XP, CPU 100% Usage</td></tr><tr><td>Current (A)</td><td>5.12A</td><td>5.12A</td><td>4.9A</td><td>4.9A</td><td>3.23A</td><td>3.23A</td></tr><tr><td>Watts (W)</td><td>25.6W</td><td>25.6W</td><td>24.5W</td><td>24.5W</td><td>16.15W</td><td>16.15W</td></tr><tr><td colspan="7">Windows XP, Standby</td></tr><tr><td>Current (A)</td><td>2.05A</td><td>2.05A</td><td>3.05A</td><td>3.05A</td><td>1.93A</td><td>1.93A</td></tr><tr><td>Watts (W)</td><td>10.4W</td><td>10.4W</td><td>15.25W</td><td>15.25W</td><td>9.65W</td><td>9.65W</td></tr><tr><td colspan="7">Windows XP, Suspend-to-RAM (S3)</td></tr><tr><td>Current (A)</td><td>134.5mA</td><td>134.5mA</td><td>142.9mA</td><td>149.9mA</td><td>139.5mA</td><td>139.5mA</td></tr><tr><td>Watts (W)</td><td>0.6725W</td><td>0.6275W</td><td>0.7145W</td><td>0.7145W</td><td>0.6975W</td><td>0.6975W</td></tr></table>

# 3 Function Diagram

![This block diagram illustrates the architecture of a computer system based on the Intel 945GME chipset.\n\n**Central Components:**\n*   **CPU**: Labeled 'Celeron® M 4xx Core™ Duo Core™2 Duo Micro-FCBGA,' it connects directly to the **Northbridge**.\n*   **Northbridge**: Labeled 'Intel® 945GME.' It contains internal blocks for 'PCIe VGA,' 'SDTV HDTV,' 'SDVO_B,' 'SDVO_C,' and 'DDR2 Memory Controller.'\n    *   It connects to the **CPU** above.\n    *   It connects to the **Southbridge** below.\n    *   It connects to **SODIMM** (labeled 'DDR2 667 MHz') on the right.\n    *   It connects to **PCI / ISA** (labeled 'IT8888G') on the right, which then connects to **X2**.\n    *   It connects to several external interfaces on the left: **LAN PHY** ('Realtek RTL8111C'), **PATA** ('IDE0/IDE1'), **VGA**, **TV-out**, and **LVDS** ('Single/Dual 18/24-bit'). These interfaces are grouped near connector **X4**.\n\n**Southbridge and I/O:**\n*   **Southbridge**: Labeled 'Intel® ICH7M.' It contains internal blocks for 'PCI x1,' 'IDE PATA,' 'PCI Express x1,' 'SATA,' 'RTC,' 'SPI,' 'PCI Controller,' 'Audio,' 'USB 2.0,' and 'LPC.'\n    *   It connects to the **Northbridge** above.\n    *   **Left Connections**: It connects to two blocks labeled **SATA**, a block labeled **PCIe to PATA** ('JML368'), and **SMBus** ('I²C').\n    *   **Right Connections**:\n        *   A line labeled **PCI Bus** connects to connector **X1**.\n        *   **Audio** connects to **Audio Codec** ('Realtek ALC262'), which connects to **X1**.\n        *   **USB 2.0** connects to **Four port USB 2.0**, which connects to **X1**.\n\n**Peripheral and Control Logic:**\n*   **BIOS**: Connects to the **Southbridge** (via SPI) and the **Super I/O**.\n*   **Super I/O**: Labeled 'Winbond W83627HG.' It connects to the **Southbridge** (via LPC), **BIOS**, and a **Debug header**.\n*   **X3 (Connector)**: Connects to **Keyboard**, **Mouse**, **LPT1/FDD**, **COM1**, and **COM2**. These peripheral blocks also connect to the **Super I/O**.](.31-en/bbcdb9ecccc9f2bc918ab71c71cd0d611b655bcd6a9e15e26bf740c44ac93f91.jpg)

# 4 Mechanical Dimensions

![SIDE VIEW\n20 (78.74)\n5.00 (196.85)\n2.50 (98.43)\n0.00 (0)\n0.00 (0)\n24.60 (968.5)\nX3\n41.70 (1641.73)\n53.30 (2098.42)\nX4\n70.40 (2771.65)\n92.50 (3641.73)\n87.50 (3444.88)\n95.00 (3740.15)\n0.00 (0)\n2.40 (94.49)\n3.00 (118.11)\nTOP VIEW\nX1-X4 connectors\non bottom side\nNorth badge\nIntel Core 2 Duo\nCPU\nIntel Core 2 Duo\nIntel Core 2 Duo\nIntel Core 2 Duo\nSoul bridge\nIntel 82807 BIM\nX1\nX2\n110.10 (4334.64)\n111.00 (4370.07)\n108.60 (4275.58)\n114.00 (4488.18)\n2.50 (98.43)\n9.20 (362.2)\n24.60 (968.5)\n0.00 (0)\n50.80 (2000)\n70.4 (2771.65)\n87.50 (3444.88)\n92.50 (3641.73)\n95.00 (3740.15)\n110.10 (4334.64)\n111.00 (4370.07)\n111.60 (4393.69)\n114.00 (4488.18)](.31-en/bf045d139a2d625c86ef206d3d7e7054fc5577a4610b10e6222be08e3607ea86.jpg)

All tolerances ± 0.2 mm

# 5 Watchdog Timer (WDT)

ETX-NR667 implements a watchdog timer (WDT) embedded in the LPC based Winbond 83627HG Super I/O controller.

The watchdog timer consists of a one-second/minute resolution counter (CRF6 of logical device 8 on 83627HG) and two watchdog control registers (CRF5 and CRF7 of logical device 8). Once a value is set in the WDT, the timer begins to count down.

Any movement in the keyboard, mouse, or software reset of the value will cause a reload of the timer value. The watchdog output is connected to "reset". When the system hangs up without software re-trigger, the system will be reset.

The watchdog timer has a one second granularity up to 255 seconds or a one minute granularity up to 255 minutes. The keyboard and mouse will only reset the WDT if bit 7 and 6 of CRF7 is set, i.e. values greater than C0h or 192 decimal.

To configure the registers, the following sequence should be followed :

1. Writing 87h to location 2Eh twice to enter the extended function mode
2. Configure the registers to set up the WDT
3. Writing 0AAh to location 2Eh to exit the extended function mode

The example shown on the following pages resets the system after 15 seconds. Both keyboard and mouse interrupts will reload the WDT from CRF6.

begin :
```txt
; Enter the extend function mode, interrupt double-write;
```

```csv
mov dx,2eh
mov al,87h
out dx,al
out dx,al
mov dx,2eh
mov al,2bh ; CR2B, bit4-> 0 = WDTO
; bit4-> 1 = GP24
out dx,al
mov dx,2fh
mov al,0c0h
out dx,al
mov dx,2eh
mov al,07h
out dx,al
mov dx,2fh
mov al,08h ;device 8
out dx,al
mov dx,2eh
mov al,30h
out dx,al
mov dx,2fh
mov al,01h ;enable device 8
out dx,al
mov dx,2eh
mov al,07h
out dx,al
mov dx,2fh
mov al,08h ;device 8
out dx,al
mov dx,2eh
mov al,0f7h
out dx,al ;device 8,CRF7
mov dx,2fh
mov al,0c0h
out dx,al
```

```asm
mov dx,2eh
mov al,07h
out dx,al
mov dx,2fh
mov al,08h
out dx,al ;device 8
mov dx,2eh
mov al,0f5h ;device 8, CRF5
out dx,al
mov dx,2fh
mov al,00h ;bit3 -> 0 = second
;bit3 -> 1 = minute
out dx,al
mov dx,2eh
mov al,07h
out dx,al
mov dx,2fh
mov al,08h
out dx,al ;device 8
mov dx,2eh
mov al,0f6h ;device 8, CRF6
out dx,al
mov dx,2fh
mov al,0fh
out dx,al
;----;
; Exit extend function mode
;----
mov dx,2eh
mov al,0aah
out dx,al
.exit
end
```

# 6 Pin-out and Signal Descriptions

# 6.1 Connector Locations

![- Ethernet\n- IDE1/IDE2\n- Power Signals\n- Speaker, Battery\n- I²C & SMB bus\nX4](.31-en/c6450ada920947d99d5942e6afff8ee4e9e869a6b27a86d6f816b25d7cbddfaf.jpg)

![ETX-NR667\n(top view)](.31-en/16c5a5f5b974b51fb9d31c080ae562421f5434ad9787cebe945c66b582708ab1.jpg)

\- ISA bus

X2

X1

- 32-bit PCI bus
- USB
- Audio

# 6.2 Pin Compatibility

All pins on X1, X2, X3, and X4 of the ETX-NR667 comply with pin and signal descriptions used in the ETX Specification version 3.02". This document contains a description of pins, signal descriptions, and mechanical characteristics of the ETX form factor.

# 6.3 Pin Definitions

X1: PCI-bus, USB, & Audio

X1
![The image displays a vertical diagram featuring a central white rectangular shape with a long, narrow vertical slot running through its middle. Flanking this central shape on both the left and right sides are two vertical strips composed of repeating horizontal rectangular segments, resembling rulers or scales.\n\nThe numbers are positioned at the corners:\n- **99** is at the top left.\n- **100** is at the top right.\n- **1** is at the bottom left.\n- **2** is at the bottom right.](.31-en/b485d9009cdc95d6fb3b7a31b5829082de6ff2f9797bfbd54c48843d2564562a.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>PCICLK3</td><td>4</td><td>PCICLK4</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>PCICLK1</td><td>8</td><td>PCICLK2</td></tr><tr><td>9</td><td>REQ3#</td><td>10</td><td>GNT3#</td></tr><tr><td>11</td><td>GNT2#</td><td>12</td><td> $3V^1$ </td></tr><tr><td>13</td><td>REQ2#</td><td>14</td><td>GNT1#</td></tr><tr><td>15</td><td>REQ1#</td><td>16</td><td> $3V^1$ </td></tr><tr><td>17</td><td>GNT0#</td><td>18</td><td>RSV</td></tr><tr><td>19</td><td>5VCC</td><td>20</td><td>5VCC</td></tr><tr><td>21</td><td>SERIRQ</td><td>22</td><td>REQ0#</td></tr><tr><td>23</td><td>AD0</td><td>24</td><td> $3V^1$ </td></tr><tr><td>25</td><td>AD1</td><td>26</td><td>AD2</td></tr><tr><td>27</td><td>AD4</td><td>28</td><td>AD3</td></tr><tr><td>29</td><td>AD6</td><td>30</td><td>AD5</td></tr><tr><td>31</td><td>CBE0#</td><td>32</td><td>AD7</td></tr><tr><td>33</td><td>AD8</td><td>34</td><td>AD9</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>GND</td></tr><tr><td>37</td><td>AD10</td><td>38</td><td>AUXAL</td></tr><tr><td>39</td><td>AD11</td><td>40</td><td>MIC</td></tr><tr><td>41</td><td>AD12</td><td>42</td><td>AUXAR</td></tr><tr><td>43</td><td>AD13</td><td>44</td><td>ASVCC</td></tr><tr><td>45</td><td>AD14</td><td>46</td><td>SDNL</td></tr><tr><td>47</td><td>AD15</td><td>48</td><td>ASSGND</td></tr><tr><td>49</td><td>CBE1#</td><td>50</td><td>SNDR</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>5VCC</td><td>52</td><td>5VCC</td></tr><tr><td>53</td><td>PAR</td><td>54</td><td>SERR#</td></tr><tr><td>55</td><td>GPERR</td><td>56</td><td>RSV</td></tr><tr><td>57</td><td>PME#</td><td>58</td><td>USB2-</td></tr><tr><td>59</td><td>LOCK#</td><td>60</td><td>DEVSEL#</td></tr><tr><td>61</td><td>TRDY#</td><td>62</td><td>USB3-</td></tr><tr><td>63</td><td>IRDY#</td><td>64</td><td>STOP#</td></tr><tr><td>65</td><td>FRAME#</td><td>66</td><td>USB2+</td></tr><tr><td>67</td><td>GND</td><td>68</td><td>GND</td></tr><tr><td>69</td><td>AD16</td><td>70</td><td>CBE2#</td></tr><tr><td>71</td><td>AD17</td><td>72</td><td>USB3+</td></tr><tr><td>73</td><td>AD19</td><td>74</td><td>AD18</td></tr><tr><td>75</td><td>AD20</td><td>76</td><td>USB0N</td></tr><tr><td>77</td><td>AD22</td><td>78</td><td>AD21</td></tr><tr><td>79</td><td>AD23</td><td>80</td><td>USB1-</td></tr><tr><td>81</td><td>AD24</td><td>82</td><td>CBE3#</td></tr><tr><td>83</td><td>5VCC</td><td>84</td><td>5VCC</td></tr><tr><td>85</td><td>AD25</td><td>86</td><td>AD26</td></tr><tr><td>87</td><td>AD28</td><td>88</td><td>USB0+</td></tr><tr><td>89</td><td>AD27</td><td>90</td><td>AD29</td></tr><tr><td>91</td><td>AD30</td><td>92</td><td>USB1+</td></tr><tr><td>93</td><td>PCIRST#</td><td>94</td><td>AD31</td></tr><tr><td>95</td><td>INTC#</td><td>96</td><td>INTD#</td></tr><tr><td>97</td><td>INTA#</td><td>98</td><td>INTB#</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

![The image displays a digital icon of a white document page featuring faint horizontal lines, overlaid with a large, bold red checkmark.](.31-en/dac8260acad4fe5b3f3ff25e15a4f407d0184da7de13bdaf0941486d2fe0deff.jpg)
NOTE:

The 3V (3.3 V ±5%) is generated onboard. Pins may be used to power devices on the carrier board up to a maximum load of 500 mA.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the word 'CAUTION:' is printed in bold black capital letters.](.31-en/77f1bf6c4f3d9b51ecb0b7ed9c05d9c2b686b3f8a1593f2a9d3fe5c7482b4512.jpg)

Do not connect the 3V pin to external 3.3V supply power.

X2: ISA Bus

X2

![The image displays a schematic line drawing of a connector. A central vertical rectangular shape with notched ends is flanked on both the left and right sides by rows of vertical parallel lines. The four corners are labeled with numbers: '99' at the top left, '100' at the top right, '1' at the bottom left, and '2' at the bottom right.](.31-en/9da1b9d4efb6d02ea892796f4dbf3e530a604f0dbf7a8e8450b11e0a86e70b09.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>SD14</td><td>4</td><td>SD15</td></tr><tr><td>5</td><td>SD13</td><td>6</td><td>MASTER#</td></tr><tr><td>7</td><td>SD12</td><td>8</td><td>DREQ7</td></tr><tr><td>9</td><td>SD11</td><td>10</td><td>DACK7#</td></tr><tr><td>11</td><td>SD10</td><td>12</td><td>DREQ6</td></tr><tr><td>13</td><td>SD9</td><td>14</td><td>DACK6#</td></tr><tr><td>15</td><td>SD8</td><td>16</td><td>DREQ5</td></tr><tr><td>17</td><td>MEMW#</td><td>18</td><td>DACK5#</td></tr><tr><td>19</td><td>MEMR#</td><td>20</td><td>DREQ0</td></tr><tr><td>21</td><td>LA17</td><td>22</td><td>DACK0#</td></tr><tr><td>23</td><td>LA18</td><td>24</td><td>IRQ14</td></tr><tr><td>25</td><td>LA19</td><td>26</td><td>IRQ15</td></tr><tr><td>27</td><td>LA20</td><td>28</td><td> $\text{IRQ12}^{\text{1}}$ </td></tr><tr><td>29</td><td>LA21</td><td>30</td><td>IRQ11</td></tr><tr><td>31</td><td>LA22</td><td>32</td><td>IRQ10</td></tr><tr><td>33</td><td>LA23</td><td>34</td><td>IO16#</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>GND</td></tr><tr><td>37</td><td>SBHE#</td><td>38</td><td>M16#</td></tr><tr><td>39</td><td>SA0</td><td>40</td><td>OSC</td></tr><tr><td>41</td><td>SA1</td><td>42</td><td>BALE</td></tr><tr><td>43</td><td>SA2</td><td>44</td><td>TC</td></tr><tr><td>45</td><td>SA3</td><td>46</td><td>DACK2#</td></tr><tr><td>47</td><td>SA4</td><td>48</td><td>IRQ3</td></tr><tr><td>49</td><td>SA5</td><td>50</td><td>IRQ4</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>5VCC</td><td>52</td><td>5VCC</td></tr><tr><td>53</td><td>SA6</td><td>54</td><td>IRQ5</td></tr><tr><td>55</td><td>SA7</td><td>56</td><td>IRQ6</td></tr><tr><td>57</td><td>SA8</td><td>58</td><td>IRQ7</td></tr><tr><td>59</td><td>SA9</td><td>60</td><td>SYSCLK</td></tr><tr><td>61</td><td>SA10</td><td>62</td><td>REFSH#</td></tr><tr><td>63</td><td>SA11</td><td>64</td><td>DREQ1</td></tr><tr><td>65</td><td>SA12</td><td>66</td><td>DACK1#</td></tr><tr><td>67</td><td>GND</td><td>68</td><td>GND</td></tr><tr><td>69</td><td>SA13</td><td>70</td><td>DREQ3</td></tr><tr><td>71</td><td>SA14</td><td>72</td><td>DACK3#</td></tr><tr><td>73</td><td>SA15</td><td>74</td><td>IOR#</td></tr><tr><td>75</td><td>SA16</td><td>76</td><td>IOW#</td></tr><tr><td>77</td><td>SA18</td><td>78</td><td>SA17</td></tr><tr><td>79</td><td>SA19</td><td>80</td><td>SMEMR#</td></tr><tr><td>81</td><td>IOCHRDY</td><td>82</td><td>AEN</td></tr><tr><td>83</td><td>5VCC</td><td>84</td><td>5VCC</td></tr><tr><td>85</td><td>SD0</td><td>86</td><td>SMEMW#</td></tr><tr><td>87</td><td>SD2</td><td>88</td><td>SD1</td></tr><tr><td>89</td><td>SD3</td><td>90</td><td>NOWS#</td></tr><tr><td>91</td><td>DREQ2</td><td>92</td><td>SD4</td></tr><tr><td>93</td><td>SD5</td><td>94</td><td>IRQ9</td></tr><tr><td>95</td><td>SD6</td><td>96</td><td>SD7</td></tr><tr><td>97</td><td>IOCHK#</td><td>98</td><td>RSTDRV</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

![The image features an icon of a white document with faint horizontal lines and a large red checkmark overlaid. Below the document, the text 'NOTE:' is written in bold, black capital letters.](.31-en/0a2a9fc5a7e4216ac0a5df3eb8c62ada083722e0659a8b4de2cf6e861e775aa0.jpg)

$^{1}$ IRQ12 is reserved for a PS/2 mouse.

X3: CRT, LCD (LVDS), & Video

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>R</td><td>4</td><td>B</td></tr><tr><td>5</td><td>HSY</td><td>6</td><td>G</td></tr><tr><td>7</td><td>VSY</td><td>8</td><td>DDCK</td></tr><tr><td>9</td><td>NC</td><td>10</td><td>DDDA</td></tr><tr><td>11</td><td>LCD16</td><td>12</td><td>LCD18</td></tr><tr><td>13</td><td>LCD17</td><td>14</td><td>LCD19</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>LCD13</td><td>18</td><td>LCD15</td></tr><tr><td>19</td><td>LCD12</td><td>20</td><td>LCD14</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>LCD8</td><td>24</td><td>LCD11</td></tr><tr><td>25</td><td>LCD9</td><td>26</td><td>LCD10</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>GND</td></tr><tr><td>29</td><td>LCD4</td><td>30</td><td>LCD7</td></tr><tr><td>31</td><td>LCD5</td><td>32</td><td>LCD6</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>LCD1</td><td>36</td><td>LCD3</td></tr><tr><td>37</td><td>LCD0</td><td>38</td><td>LCD2</td></tr><tr><td>39</td><td>5VCC</td><td>40</td><td>5VCC</td></tr><tr><td>41</td><td>JILI_SDA</td><td>42</td><td>LTGO0</td></tr><tr><td>43</td><td>JILI_SCL</td><td>44</td><td>BLON#</td></tr><tr><td>45</td><td>NC</td><td>46</td><td>DIGON</td></tr><tr><td>47</td><td>COMP</td><td>48</td><td>Y</td></tr><tr><td>49</td><td>NC</td><td>50</td><td>C</td></tr></table>

X3

![The image displays a vertical schematic diagram featuring a central white rectangle with a thin black border. Flanking this central rectangle on both the left and right sides are columns of dense vertical black lines, resembling barcode tracks.\n\nFour numbers are positioned at the corners of the diagram:\n-   **99** is at the top left.\n-   **100** is at the top right.\n-   **1** is at the bottom left.\n-   **2** is at the bottom right.](.31-en/fc00083de45e1fb8330d581f0e070970b5dc8347b22e2d8c9832dee6ce7477c1.jpg)

First LVDS Channel

<table><tr><td>Signal</td><td>LVDS Signal</td></tr><tr><td>LCD0</td><td>Txout 0-</td></tr><tr><td>LCD1</td><td>Txout 0+</td></tr><tr><td>LCD2</td><td>Txout 1-</td></tr><tr><td>LCD3</td><td>Txout 1+</td></tr><tr><td>LCD4</td><td>Txout 2-</td></tr><tr><td>LCD5</td><td>Txout 2+</td></tr><tr><td>LCD6</td><td>Txclk -</td></tr><tr><td>LCD7</td><td>Txclk +</td></tr><tr><td>LCD8</td><td>Txout 3-</td></tr><tr><td>LCD9</td><td>Txout 3+</td></tr></table>

Second LVDS Channel

<table><tr><td>Signal</td><td>LVDS Signal</td></tr><tr><td>LCD10</td><td>Txout 0-</td></tr><tr><td>LCD11</td><td>Txout 0+</td></tr><tr><td>LCD12</td><td>Txout 1-</td></tr><tr><td>LCD13</td><td>Txout 1+</td></tr><tr><td>LCD14</td><td>Txout 2-</td></tr><tr><td>LCD15</td><td>Txout 2+</td></tr><tr><td>LCD16</td><td>Txclk -</td></tr><tr><td>LCD17</td><td>Txclk +</td></tr><tr><td>LCD18</td><td>Txout 3-</td></tr><tr><td>LCD19</td><td>Txout 3+</td></tr></table>

# X3: COM1/2, LPT1 or FDD, IrDA, Mouse, & Keyboard

# X3

![The image displays a vertical linear barcode graphic. Four numbers are positioned at the corners: '99' in the top left, '100' in the top right, '1' in the bottom left, and '2' in the bottom right. The barcode pattern consists of dense vertical black bars located on the far left and far right edges. Between these bars is a central white area shaped like a vertical rectangle with rectangular notches on its left side.](.31-en/14c431c4f2a3bc30f95ce1efdd123a7d3ee77caf7aa29b5caf9fff96e8e939d0.jpg)

The pinout on the X3 connector for parallel-port interfaces can alternatively be assigned as a floppy disk drive interface in the BIOS (see Sec. 8.3.4, Super IO Configuration). Alternative pinouts for the two interfaces are shown in the tables below. The left table shows the standard functions of the pins in parallel port mode and the he right table shows the alternate function pinout in floppy disk drive mode.

LPT Mode

<table><tr><td>Pin</td><td>Signal</td><td></td><td>Pin</td></tr><tr><td>51</td><td>LPT/FLPY#</td><td>52</td><td>RESERVED</td></tr><tr><td>53</td><td>5VCC</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>STB#</td><td>56</td><td>AFD#</td></tr><tr><td>57</td><td>RESERVED</td><td>58</td><td>PD7</td></tr><tr><td>59</td><td>IRRX</td><td>60</td><td>ERR#</td></tr><tr><td>61</td><td>IRTX</td><td>62</td><td>PD6</td></tr><tr><td>63</td><td>RXD2</td><td>64</td><td>INIT#</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>RTS2#</td><td>68</td><td>PD5</td></tr><tr><td>69</td><td>DTR2#</td><td>70</td><td>SLIN#</td></tr><tr><td>71</td><td>DCD2#</td><td>72</td><td>PD4</td></tr><tr><td>73</td><td>DSR2#</td><td>74</td><td>PD3</td></tr><tr><td>75</td><td>CTS2#</td><td>76</td><td>PD2</td></tr><tr><td>77</td><td>TXD2</td><td>78</td><td>PD1</td></tr><tr><td>79</td><td>RI2#</td><td>80</td><td>PD0</td></tr><tr><td>81</td><td>5VCC</td><td>82</td><td>5VCC</td></tr><tr><td>83</td><td>RXD1</td><td>84</td><td>ACK#</td></tr><tr><td>85</td><td>RTS1#</td><td>86</td><td>BUSY</td></tr><tr><td>87</td><td>DTR1#</td><td>88</td><td>PE</td></tr><tr><td>89</td><td>DCD1#</td><td>90</td><td>SLCT#</td></tr><tr><td>91</td><td>DSR1#</td><td>92</td><td>MSCLK</td></tr><tr><td>93</td><td>CTS1#</td><td>94</td><td>MSDAT</td></tr><tr><td>95</td><td>TXD1</td><td>96</td><td>KBCLK</td></tr><tr><td>97</td><td>RI1#</td><td>98</td><td>KBDAT</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

FDD Mode

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>LPT/FLPY#</td><td>52</td><td>RESERVED</td></tr><tr><td>53</td><td>5VCC</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>RESERVED</td><td>56</td><td>DENSEL</td></tr><tr><td>57</td><td>RESERVED</td><td>58</td><td>RESERVED</td></tr><tr><td>59</td><td>IRRX</td><td>60</td><td>HDSEL#</td></tr><tr><td>61</td><td>IRTX</td><td>62</td><td>RESERVED</td></tr><tr><td>63</td><td>RXD2</td><td>64</td><td>DIR#</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>RTS2#</td><td>68</td><td>RESERVED</td></tr><tr><td>69</td><td>DTR2#</td><td>70</td><td>STEP#</td></tr><tr><td>71</td><td>DCD2#</td><td>72</td><td>DSKCHG#</td></tr><tr><td>73</td><td>DSR2#</td><td>74</td><td>RDATA#</td></tr><tr><td>75</td><td>CTS2#</td><td>76</td><td>WP#</td></tr><tr><td>77</td><td>TXD2</td><td>78</td><td>TRK0#</td></tr><tr><td>79</td><td>RI2#</td><td>80</td><td>INDEX#</td></tr><tr><td>81</td><td>5VCC</td><td>82</td><td>5VCC</td></tr><tr><td>83</td><td>RXD1</td><td>84</td><td>DRV</td></tr><tr><td>85</td><td>RTS1#</td><td>86</td><td>MOT</td></tr><tr><td>87</td><td>DTR1#</td><td>88</td><td>WDATA#</td></tr><tr><td>89</td><td>DCD1#</td><td>90</td><td>WGATE#</td></tr><tr><td>91</td><td>DSR1#</td><td>92</td><td>MSCLK</td></tr><tr><td>93</td><td>CTS1#</td><td>94</td><td>MSDAT</td></tr><tr><td>95</td><td>TXD1</td><td>96</td><td>KBCLK</td></tr><tr><td>97</td><td>RI1#</td><td>98</td><td>KBDAT</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

X4: IDE1, IDE2, Ethernet, & Miscellaneous

X4

![This is a black-and-white line drawing of a vertical scale or ruler. In the center is a long, narrow rectangle with small rectangular notches at the top and bottom centers. Flanking this central rectangle on both the left and right sides are columns of dense, vertical tick marks.\n\nThe text labels are positioned at the extremes:\n- Top left: **99**\n- Top right: **100**\n- Bottom left: **1**\n- Bottom right: **2**](.31-en/8c6edb21d99b04bb37d7eb49abc0746fb9e16b343ffb0804a11d00ab8634d81f.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>5V_SB</td><td>4</td><td>PWGIN</td></tr><tr><td>5</td><td>PS_ON</td><td>6</td><td>SPEAKER</td></tr><tr><td>7</td><td>PWRBTN#</td><td>8</td><td>BATT</td></tr><tr><td>9</td><td>KBINH</td><td>10</td><td>LILED#</td></tr><tr><td>11</td><td> $RSMRST^1$ </td><td>12</td><td>ACTLED#</td></tr><tr><td>13</td><td> $ROMKBCS^2$ </td><td>14</td><td>SPDLED#</td></tr><tr><td>15</td><td> $EXT\_PRG^2$ </td><td>16</td><td> $I2CLK^3$ </td></tr><tr><td>17</td><td>5VCC</td><td>18</td><td>5VCC</td></tr><tr><td>19</td><td>OVCR#</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>EXTSMI#</td><td>22</td><td> $I2DAT^3$ </td></tr><tr><td>23</td><td> $SMBCLK^3$ </td><td>24</td><td> $SMBDATA^3$ </td></tr><tr><td>25</td><td>S_CS3#</td><td>26</td><td>SMBALRT#</td></tr><tr><td>27</td><td>S_CS1#</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>S_A2</td><td>30</td><td>P_CS3#</td></tr><tr><td>31</td><td>S_A0</td><td>32</td><td>P_CS1#</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>PDIAG_S</td><td>36</td><td>P_A2</td></tr><tr><td>37</td><td>S_A1</td><td>38</td><td>P_A0</td></tr><tr><td>39</td><td>S_INTRQ</td><td>40</td><td>P_A1</td></tr><tr><td>41</td><td> $BATLOW^2$ </td><td>42</td><td> $GPE1^2$ </td></tr><tr><td>43</td><td>S_AK#</td><td>44</td><td>P_INTRQ</td></tr><tr><td>45</td><td>S_RDY</td><td>46</td><td>P_AK#</td></tr><tr><td>47</td><td>S_IOR#</td><td>48</td><td>P_RDY</td></tr><tr><td>49</td><td>5VCC</td><td>50</td><td>5VCC</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>S_IOW#</td><td>52</td><td>P_IOR#</td></tr><tr><td>53</td><td>S_DRQ</td><td>54</td><td>P_IOW#</td></tr><tr><td>55</td><td>S_D15</td><td>56</td><td>P_DRQ</td></tr><tr><td>57</td><td>S_D0</td><td>58</td><td>P_D15</td></tr><tr><td>59</td><td>S_D14</td><td>60</td><td>P_D0</td></tr><tr><td>61</td><td>S_D1</td><td>62</td><td>P_D14</td></tr><tr><td>63</td><td>S_D13</td><td>64</td><td>P_D1</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr><tr><td>67</td><td>S_D2</td><td>68</td><td>P_D13</td></tr><tr><td>69</td><td>S_D12</td><td>70</td><td>P_D2</td></tr><tr><td>71</td><td>S_D3</td><td>72</td><td>P_D12</td></tr><tr><td>73</td><td>S_D11</td><td>74</td><td>P_D3</td></tr><tr><td>75</td><td>S_D4</td><td>76</td><td>P_D11</td></tr><tr><td>77</td><td>S_D10</td><td>78</td><td>P_D4</td></tr><tr><td>79</td><td>S_D5</td><td>80</td><td>P_D10</td></tr><tr><td>81</td><td>5VCC</td><td>82</td><td>5VCC</td></tr><tr><td>83</td><td>S_D9</td><td>84</td><td>P_D5</td></tr><tr><td>85</td><td>S_D6</td><td>86</td><td>P_D9</td></tr><tr><td>87</td><td>S_D8</td><td>88</td><td>P_D6</td></tr><tr><td>89</td><td>GPE2 $^{2}$ </td><td>90</td><td>CBLID_P#</td></tr><tr><td>91</td><td>RXD#</td><td>92</td><td>P_D8</td></tr><tr><td>93</td><td>RXD</td><td>94</td><td>S_D7</td></tr><tr><td>95</td><td>TXD#</td><td>96</td><td>P_D7</td></tr><tr><td>97</td><td>TXD</td><td>98</td><td>HDRST#</td></tr><tr><td>99</td><td>GND</td><td>100</td><td>GND</td></tr></table>

![The image displays an icon of a white document with a folded top-right corner, overlaid with a large red checkmark. Below the document graphic is the text 'NOTE:' in black, capital letters.](.31-en/d4b1e71e7979fdc86d4f2fd4bea1c7dde4cb307aebbc5a7bd238664248b7f0dc.jpg)

$^{1}$ May be affected by external circuitry to reset the power management logic of the ETX module. Most designs do not use and pin is not connected.

$^{2}$ Reserved, do not connect

$^{3}$ See also: section 7.7 System Management Bus (I2C-compatible)

$^{4}$ Available, but not supported on the ETX-NR667

6.4 Signal Descriptions

X1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>2</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>3</td><td>PCICLK3</td><td>PCI Clock Slot 3</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>4</td><td>PCICLK4</td><td>PCI Clock Slot 4</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>5</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>6</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>7</td><td>PCICLK1</td><td>PCI Clock Slot 1</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>8</td><td>PCICLK2</td><td>PCI Clock Slot 2</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>9</td><td>REQ3#</td><td>PCI Bus Request 3</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>10</td><td>GNT3#</td><td>PCI Bus Grant 3</td><td>O-3,3</td><td>-</td><td>int. PU 20k 3,3V</td></tr><tr><td>11</td><td>GNT2#</td><td>PCI Bus Grant 2</td><td>O-3,3</td><td>-</td><td>int. PU 20k 3,3V</td></tr><tr><td>12</td><td>3V</td><td>Power +3,3V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>13</td><td>REQ2#</td><td>PCI Bus Request 2</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>14</td><td>GNT1#</td><td>PCI Bus Grant 1</td><td>O-3,3</td><td>-</td><td>int. PU 20k 3,3V</td></tr><tr><td>15</td><td>REQ1#</td><td>PCI Bus Request 1</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>16</td><td>3V</td><td>Power +3,3V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>17</td><td>GNT0#</td><td>PCI Bus Grant 0</td><td>O-3,3</td><td>-</td><td>int. PU 20k 3,3V</td></tr><tr><td>18</td><td>RSVD</td><td>-</td><td>NC</td><td>-</td><td>Reserved</td></tr><tr><td>19</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>20</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>21</td><td>SERIRQ</td><td>Serial Interrupt Request</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>22</td><td>REQ0#</td><td>PCI Bus Request 0</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>23</td><td>AD0</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td></td></tr><tr><td>24</td><td>3V</td><td>Power +3,3V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>25</td><td>AD1</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>26</td><td>AD2</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>27</td><td>AD4</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>28</td><td>AD3</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>29</td><td>AD6</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>30</td><td>AD5</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>31</td><td>CBE0#</td><td>PCI Bus Command and Byte enables 0</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>32</td><td>AD7</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>33</td><td>AD8</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>34</td><td>AD9</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>35</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>36</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>37</td><td>AD10</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>38</td><td>AUXAL</td><td>Auxiliary Line Input Left</td><td>I</td><td></td><td></td></tr><tr><td>39</td><td>AD11</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>40</td><td>MIC</td><td>Microphone Input</td><td>I</td><td>-</td><td>-</td></tr><tr><td>41</td><td>AD12</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>42</td><td>AUXAR</td><td>Auxiliary Line Input Right</td><td>I</td><td></td><td></td></tr><tr><td>43</td><td>AD13</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>44</td><td>ASVCC</td><td>Analog Supply of Sound Controller</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>45</td><td>AD14</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>46</td><td>SNDL</td><td>Audio Out Left</td><td>O</td><td>-</td><td>-</td></tr><tr><td>47</td><td>AD15</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>48</td><td>ASGND</td><td>Analog Ground of Sound Controller</td><td>P</td><td>-</td><td>-</td></tr><tr><td>49</td><td>CBE1#</td><td>PCI Bus Command and Byte enables 1</td><td>IO-3,3</td><td>-</td><td>-</td></tr><tr><td>50</td><td>SNDR</td><td>Audio Out Right</td><td>O</td><td>-</td><td>-</td></tr></table>

Signal Descriptions (cont'd)
X1

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>51</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td></td><td></td></tr><tr><td>52</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td></td><td></td></tr><tr><td>53</td><td>PAR</td><td>PCI Bus Parity</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>54</td><td>SERR#</td><td>PCI Bus System Error</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>55</td><td>GPERR#</td><td>PCI Bus Grant Error</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>56</td><td>RSV</td><td>-</td><td>NC</td><td></td><td>Reserved</td></tr><tr><td>57</td><td>PME#</td><td>PCI Power Management Event</td><td>IO-3,3</td><td></td><td>int. PU 20k 3,3V</td></tr><tr><td>58</td><td>USB2N</td><td>USB Data- Port2</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>59</td><td>LOCK#</td><td>PCI Bus Lock</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>60</td><td>DEVSEL#</td><td>PCI Bus Device Select</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>61</td><td>TRDY#</td><td>PIC Bus Target Ready</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>62</td><td>USB3N</td><td>USB Data- Port3</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>63</td><td>IRDY#</td><td>PCI Bus Initiator Ready</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>64</td><td>STOP#</td><td>PCI Bus Stop</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>65</td><td>FRAME#</td><td>PCI Bus Cycle Frame</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>66</td><td>USB2P</td><td>USB Data+ Port2</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>67</td><td>GND</td><td>Ground</td><td>PWR</td><td></td><td></td></tr><tr><td>68</td><td>GND</td><td>Ground</td><td>PWR</td><td></td><td></td></tr><tr><td>69</td><td>AD16</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>70</td><td>CBE2#</td><td>PCI Bus Command and Byte enables 2</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>71</td><td>AD17</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>72</td><td>USB3P</td><td>USB Data+ Port3</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>73</td><td>AD19</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>74</td><td>AD18</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>75</td><td>AD20</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>76</td><td>USB0N</td><td>USB Data- Port0</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>77</td><td>AD22</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>78</td><td>AD21</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>79</td><td>AD23</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>80</td><td>USB1N</td><td>USB Data- Port1</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>81</td><td>AD24</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>82</td><td>CBE3#</td><td>PCI Bus Command and Byte enables 3</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>83</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td></td><td></td></tr><tr><td>84</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td></td><td></td></tr><tr><td>85</td><td>AD25</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>86</td><td>AD26</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>87</td><td>AD28</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>88</td><td>USB0P</td><td>USB Data+ Port0</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>89</td><td>AD27</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>90</td><td>AD29</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>91</td><td>AD30</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>92</td><td>USB1P</td><td>USB Data+ Port1</td><td>I/O - DP</td><td></td><td>int. PD 15k</td></tr><tr><td>93</td><td>PCIRST#</td><td>PCI Bus Reset</td><td>O-3,3</td><td></td><td></td></tr><tr><td>94</td><td>AD31</td><td>PCI Adress &amp; Data Bus line</td><td>IO-3,3</td><td></td><td></td></tr><tr><td>95</td><td>INTC#</td><td>PCI BUS Interrupt Reauest C</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>96</td><td>INTD#</td><td>PCI BUS Interrupt Reauest D</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>97</td><td>INTA#</td><td>PCI BUS Interrupt Reauest A</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>98</td><td>INTB#</td><td>PCI BUS Interrupt Reauest B</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>99</td><td>GND</td><td>Ground</td><td>PWR</td><td></td><td></td></tr><tr><td>100</td><td>GND</td><td>Ground</td><td>PWR</td><td></td><td></td></tr></table>

# Signal Descriptions (cont'd)

# X2

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>2</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>3</td><td>SD14</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>4</td><td>SD15</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>5</td><td>SD13</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>6</td><td>MASTER#</td><td>ISA 16-Bit Master</td><td>I-5</td><td>PU 330R 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>7</td><td>SD12</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>8</td><td>DREQ7</td><td>ISA DMA Request 7</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>9</td><td>SD11</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>10</td><td>DACK7#</td><td>ISA DMA Acknowledge 7</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>11</td><td>SD10</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>12</td><td>DREQ6</td><td>ISA DMA Request 6</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>13</td><td>SD9</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>14</td><td>DACK6#</td><td>ISA DMA Acknowledge 6</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>15</td><td>SD8</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>16</td><td>DREQ5</td><td>ISA DMA Request 5</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>17</td><td>MEMW#</td><td>ISA Memory Write</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>18</td><td>DACK5#</td><td>ISA DMA Acknowledge 5</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>19</td><td>MEMR#</td><td>ISA Memory Read</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>20</td><td>DREQ0</td><td>ISA DMA Request 0</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>21</td><td>LA17</td><td>ISA Address Bus (SA17)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>22</td><td>DACK0#</td><td>ISA DMA Acknowledge 0</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>23</td><td>LA18</td><td>ISA Address Bus (SA18)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>24</td><td>IRQ14</td><td>ISA Interrupt Request 14 / ROMChip Select</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>25</td><td>LA19</td><td>ISA Address Bus (SA19)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>26</td><td>IRQ15</td><td>ISA Interrupt Request 15</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>27</td><td>LA20</td><td>ISA Address Bus (SA20)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>28</td><td>IRQ12</td><td>ISA Interrupt Request 12</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>29</td><td>LA21</td><td>ISA Address Bus (SA21)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>30</td><td>IRQ11</td><td>ISA Interrupt Request 11</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>31</td><td>LA22</td><td>ISA Address Bus (SA22)</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>32</td><td>IRQ10</td><td>ISA Interrupt Request 10</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>33</td><td>LA23</td><td>ISA Address Bus (SA23)</td><td>O-5</td><td>PU 4k7 5V</td><td></td></tr><tr><td>34</td><td>IO16#</td><td>ISA 16-Bit I/O Access</td><td>I-5</td><td>PU 330R 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>35</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>36</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>37</td><td>SBHE#</td><td>ISA System Byte High Enable</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>38</td><td>M16#</td><td>ISA 16-Bit Memory Access</td><td>IO-5</td><td>PU 330R 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>39</td><td>SA0</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>40</td><td>OSC</td><td>ISA Oscillator (CLK_ISA14#)</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>41</td><td>SA1</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>42</td><td>BALE</td><td>ISA Buffer Address Latch Enable</td><td>IO-5</td><td>PD 4k7</td><td>int. PU 50k 5V in</td></tr><tr><td>43</td><td>SA2</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td></td></tr><tr><td>44</td><td>TC</td><td>ISA Terminal Count</td><td>IO-5</td><td>PD 4k7</td><td>int. PU 50k 5V in</td></tr><tr><td>45</td><td>SA3</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>46</td><td>DACK2#</td><td>ISA DMA Acknowledge 2</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>47</td><td>SA4</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>48</td><td>IRQ3</td><td>ISA Interrupt Request 3</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>49</td><td>SA5</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>50</td><td>IRQ4</td><td>ISA Interrupt Request 4</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr></table>

Signal Descriptions (cont'd)
X2

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>51</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>52</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>53</td><td>SA6</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>54</td><td>IRQ5</td><td>ISA Interrupt Request 5</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>55</td><td>SA7</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>56</td><td>IRQ6</td><td>ISA Interrupt Request 6</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>57</td><td>SA8</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>58</td><td>IRQ7</td><td>ISA Interrupt Request 7</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>59</td><td>SA9</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>60</td><td>SYSCLK</td><td>ISA Bus Clock (CLK_SYS_ISA)</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>61</td><td>SA10</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>62</td><td>REFSH#</td><td>ISA System Refresh Control</td><td>IO-5</td><td>PU 1k 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>63</td><td>SA11</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>64</td><td>DREQ1</td><td>ISA DMA Request 1</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>65</td><td>SA12</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>66</td><td>DACK1#</td><td>ISA DMA Acknowledge 1</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>67</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>68</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>69</td><td>SA13</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>70</td><td>DREQ3</td><td>ISA DMA Request 3</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>71</td><td>SA14</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>72</td><td>DACK3#</td><td>ISA DMA Acknowledge 3</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>73</td><td>SA15</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>74</td><td>IOR#</td><td>ISA I/O Read</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>75</td><td>SA16</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>76</td><td>IOW#</td><td>ISA I/O Write</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>77</td><td>SA18</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>78</td><td>SA17</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>79</td><td>SA19</td><td>ISA Address Bus</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>80</td><td>SMEMR#</td><td>ISA System Memory Read</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>81</td><td>IOCHRDY</td><td>ISA I/O Channel Ready</td><td>IO-5</td><td>PU 1k 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>82</td><td>AEN</td><td>ISA Address Enable</td><td>IO-5</td><td>PD 47k</td><td>int. PU 50k 5V in</td></tr><tr><td>83</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>84</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>85</td><td>SD0</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>86</td><td>SMEMW#</td><td>ISA System Memory Write</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>87</td><td>SD2</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>88</td><td>SD1</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>89</td><td>SD3</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>90</td><td>NOWS#</td><td>ISA No Wait Staits</td><td>I-5</td><td>PU 330R 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>91</td><td>DREQ2</td><td>ISA DMA Request 2</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PD 50k</td></tr><tr><td>92</td><td>SD4</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>93</td><td>SD5</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>94</td><td>IRQ9</td><td>ISA Interrupt Request 9</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>95</td><td>SD6</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>96</td><td>SD7</td><td>ISA Data Bus</td><td>IO-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>97</td><td>IOCHK#</td><td>ISA I/O Channel Check</td><td>I-5</td><td>PU 4k7 5V</td><td>int. PU 50k 5V in</td></tr><tr><td>98</td><td>RSTDRV</td><td>ISA Reset</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>99</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>100</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr></table>

# Signal Descriptions (cont'd)

# X3

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>2</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>3</td><td>R</td><td>Analog Video Out RGB - Red Channel</td><td>OA</td><td>-</td><td>-</td></tr><tr><td>4</td><td>B</td><td>Analog Video Out RGB - Blue Channel</td><td>OA</td><td>-</td><td>-</td></tr><tr><td>5</td><td>HSY</td><td>Horizontal Synchronization Pulse</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>6</td><td>G</td><td>Analog Video Out RGB - Green Channel</td><td>OA</td><td>-</td><td>-</td></tr><tr><td>7</td><td>VSY</td><td>Vertical Synchronization Pulse</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>8</td><td>DDCK</td><td>Display Data Channel Clock</td><td>IO-5</td><td>PU 10k 5V</td><td>-</td></tr><tr><td>9</td><td>DETECT#</td><td>Panel Hot-Plug Detection</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>10</td><td>DDDA</td><td>Display Data Channel Data</td><td>IO-5</td><td>PU 10k 5V</td><td>-</td></tr><tr><td>11</td><td>LCD16</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>12</td><td>LCD18</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>13</td><td>LCD17</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>14</td><td>LCD19</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>15</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>16</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>17</td><td>LCD13</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>18</td><td>LCD15</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>19</td><td>LCD12</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>20</td><td>LCD14</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>21</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>22</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>23</td><td>LCD8</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>24</td><td>LCD11</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>25</td><td>LCD9</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>26</td><td>LCD10</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>27</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>28</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>29</td><td>LCD4</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>30</td><td>LCD7</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>31</td><td>LCD5</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>32</td><td>LCD6</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>33</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>34</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>35</td><td>LCD1</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>36</td><td>LCD3</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>37</td><td>LCD0</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>38</td><td>LCD2</td><td>LVDS Channel Data</td><td>O - DP</td><td>-</td><td>-</td></tr><tr><td>39</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>40</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>41</td><td>JILI_DAT</td><td>JILI I2C Data Signal</td><td>IO-3,3</td><td>PU 4k7 3,3V</td><td>-</td></tr><tr><td>42</td><td>LTGIO0</td><td>Display Backlight Control</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>43</td><td>JILI_CLK</td><td>JILI I2C Clock Signal</td><td>IO-3,3</td><td>PU 4k7 3,3V</td><td>-</td></tr><tr><td>44</td><td>BLON#</td><td>Display Backlight On</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>45</td><td>BIASON</td><td>Display Contrast</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>46</td><td>DIGON</td><td>Display Power On</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>47</td><td>COMP</td><td>Composite Video / SCART Blue</td><td>OA</td><td>-</td><td>-</td></tr><tr><td>48</td><td>Y</td><td>S-Video Luminance / SCART Red</td><td>OA</td><td>-</td><td>-</td></tr><tr><td>49</td><td>SYNC</td><td>Composite Sync</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>50</td><td>C</td><td>S-Video Chrominance / SCART Green</td><td>OA</td><td>-</td><td>-</td></tr></table>

Signal Descriptions (cont'd)
X3

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>51</td><td>LPT | FLPY#</td><td>LPT / Floppy Interface Select</td><td>IO-3,3</td><td>PU 10k 3,3V</td><td>-</td></tr><tr><td>52</td><td>RSV</td><td>-</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>53</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>54</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>55</td><td>STB# | RSV</td><td>LPT Strobe Signal</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>56</td><td>AFD# | DENSEL</td><td>LPT Automatic Feed / Floppy Density Select</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>57</td><td>RSV</td><td>-</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>58</td><td>PD7 | RSV</td><td>LPT Data Bus D7</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>59</td><td>IRRX</td><td>Infrared Receive</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>60</td><td>ERR# | HDSEL#</td><td>LPT Error / Floppy Head Select</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>61</td><td>IRTX</td><td>Infrared Transmit</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>62</td><td>PD6 | RSV</td><td>LPT Data Bus D6</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>63</td><td>RXD2</td><td>Data Receive COM2</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>64</td><td>INIT# | DIR#</td><td>LPT Initiate / Floppy Direction</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>65</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>66</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>67</td><td>RTS2#</td><td>Request to Send COM2</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>68</td><td>PD5 | RSV</td><td>LPT Data Bus D5</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>69</td><td>DTR2#</td><td>Data Terminal Ready COM2</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>70</td><td>SLIN# | STEP#</td><td>LPT Select / Floppy Motor Step</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>71</td><td>DCD2#</td><td>Data Carrier Detect COM2</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>72</td><td>PD4 | DSKCHG#</td><td>LPT Data Bus D4</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>73</td><td>DSR2#</td><td>Data Set Ready COM2</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>74</td><td>PD3 | RDATA#</td><td>LPT Data Bus D3</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>75</td><td>CTS2#</td><td>Clear to Send COM2</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>76</td><td>PD2 | WP#</td><td>LPT Data Bus D2</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>77</td><td>TXD2</td><td>Data Transmit COM2</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>78</td><td>PD1 | TRK0#</td><td>LPT Data Bus D1</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>79</td><td>RI2#</td><td>Ring Indicator COM2</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>80</td><td>PD0 | INDEX#</td><td>LPT Data Bus D0</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>81</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>82</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>83</td><td>RXD1#</td><td>Data Receive COM1</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>84</td><td>ACK# | DRV</td><td>LPT Acknowledge / Floppy Drive Select</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>85</td><td>RTS1#</td><td>Request to Send COM1</td><td>O-5</td><td>PD 4k7</td><td>-</td></tr><tr><td>86</td><td>BUSY# | MOT</td><td>LPT Busy / Floppy Motor Select</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>87</td><td>DTR1#</td><td>Data Terminal Ready COM1</td><td>O-5</td><td>-</td><td>-</td></tr><tr><td>88</td><td>PE | WDATA#</td><td>LPT Paper Empty / Floppy Raw Write Data</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>89</td><td>DCD1#</td><td>Data Carrier Detect COM1</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>90</td><td>SLCT#|WGATE#</td><td>LPT Power On / Floppy Write Enable</td><td>IO-5</td><td>-</td><td>-</td></tr><tr><td>91</td><td>DSR1#</td><td>Data Set Ready COM1</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>92</td><td>MSCLK</td><td>Mouse Clock</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>93</td><td>CTS1#</td><td>Clear to Send COM1</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>94</td><td>MSDAT</td><td>Mouse Data</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>95</td><td>TXD1</td><td>Data Transmit COM1</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>96</td><td>KBCLK</td><td>Keyboard Clock</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>97</td><td>RI1#</td><td>Ring Indicator COM1</td><td>I-5</td><td>-</td><td>-</td></tr><tr><td>98</td><td>KBDAT</td><td>Keyboard Data</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>99</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>100</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr></table>

# Signal Descriptions (cont'd)

# X4

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>1</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>2</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>3</td><td>5V_SB</td><td>Supply of internal suspend Circuit</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>4</td><td>PWGIN</td><td>Power Good / Reset Input</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>5</td><td>PS_ON</td><td>Power Supply On</td><td>O-5</td><td>PU 4k7 5V</td><td>-</td></tr><tr><td>6</td><td>SPEAKER</td><td>Speaker Output</td><td>O-5</td><td>PU 1k 5V</td><td>-</td></tr><tr><td>7</td><td>PWRBTN#</td><td>Power Button</td><td>I-5</td><td>PU 10k 3,3VSB</td><td>-</td></tr><tr><td>8</td><td>BATT</td><td>Battery Supply</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>9</td><td>KBINH</td><td>Keyboard Inhibit Control Input</td><td>I-5</td><td>PU 8k2 5V</td><td>-</td></tr><tr><td>10</td><td>LILED</td><td>Ethernet Link LED</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>11</td><td>RSMRST#</td><td>Resume Reset input</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>12</td><td>ACTLED</td><td>Ethernet Activity LED</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>13</td><td>ROMKBCS#</td><td>-</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>14</td><td>SPDLED</td><td>Ethernet Speed LED</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>15</td><td>EXT_PRG</td><td>-</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>16</td><td>I2CLK</td><td>I2C Bus Clock</td><td>O-5</td><td>PU 8k2 3,3V</td><td></td></tr><tr><td>17</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>18</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>19</td><td>OVCR#</td><td>Over Current Detect for USB</td><td>I-3,3</td><td>PU 4k7 3,3V</td><td>-</td></tr><tr><td>20</td><td>GPCS#</td><td>-</td><td>O-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>21</td><td>EXTSMI#</td><td>System Management Interrupt Input</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>22</td><td>I2DAT</td><td>I2C Bus Data</td><td>IO-5</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>23</td><td>SMBCLK</td><td>SM Bus Clock</td><td>O-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>24</td><td>SMBDATA</td><td>SM Bus Data</td><td>IO-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>25</td><td>S_CS3#</td><td>Secondary IDE Chip Select Channel 1</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>26</td><td>SMBALERT</td><td>SM Bus Alert</td><td>I-3,3</td><td>PU 10k 3,3V</td><td>-</td></tr><tr><td>27</td><td>S_CS1#</td><td>Secondary IDE Chip Select Channel 0</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>28</td><td>DASP_S</td><td>-</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>29</td><td>S_A2</td><td>Secondary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>30</td><td>P_CS3#</td><td>Primary IDE Chip Select Channel 1</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>31</td><td>S_A0</td><td>Secondary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>32</td><td>P_CS1#</td><td>Primary IDE Chip Select Channel 0</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>33</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>34</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>35</td><td>PDIAG_S</td><td>80-conductor IDE cable Channel 1</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>36</td><td>P_A2</td><td>Primary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>37</td><td>S_A1</td><td>Secondary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>38</td><td>P_A0</td><td>Primary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>39</td><td>S_INTRQ</td><td>Secondary IDE Interrupt Request</td><td>I-3,3</td><td>PD 10k</td><td>-</td></tr><tr><td>40</td><td>P_A1</td><td>Primary IDE Adress Bus</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>41</td><td>BATLOW#</td><td>Battery Low</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>42</td><td>GPE1#</td><td>-</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>43</td><td>S_AK#</td><td>Secondary IDE DMA Acknowledge</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>44</td><td>P_INTRQ</td><td>Primary IDE Interrupt Request</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>45</td><td>S_RDY</td><td>Secondary IDE Ready</td><td>I-3,3</td><td>PU 4k7 3,3V</td><td>-</td></tr><tr><td>46</td><td>P_AK#</td><td>Primary IDE DMA Acknowledge</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>47</td><td>S_IOR#</td><td>Secondary IDE IO Read</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>48</td><td>P_RDY</td><td>Primary IDE Ready</td><td>I-3,3</td><td>PU 4k7 3,3V</td><td>-</td></tr><tr><td>49</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>50</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr></table>

Signal Descriptions (cont'd)
X4

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Type</td><td>PU/PD</td><td>Comment</td></tr><tr><td>51</td><td>S_IOW#</td><td>Secondary IDE IO Write</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>52</td><td>P_IOR#</td><td>Primary IDE IO Read</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>53</td><td>S_DRQ</td><td>Secondary IDE DMA Request</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>54</td><td>P_IOW#</td><td>Primary IDE IO Write</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>55</td><td>S_D15</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>56</td><td>P_DRQ</td><td>Primary IDE DMA Request</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>57</td><td>S_D0</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>58</td><td>P_D15</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>59</td><td>S_D14</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>60</td><td>P_D0</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>61</td><td>S_D1</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>62</td><td>P_D14</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>63</td><td>S_D13</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>64</td><td>P_D1</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>65</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>66</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>67</td><td>S_D2</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>68</td><td>P_D13</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>69</td><td>S_D12</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>70</td><td>P_D2</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>71</td><td>S_D3</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>72</td><td>P_D12</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>73</td><td>S_D11</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>74</td><td>P_D3</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>75</td><td>S_D4</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>76</td><td>P_D11</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>77</td><td>S_D10</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>78</td><td>P_D4</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>79</td><td>S_D5</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>80</td><td>P_D10</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>81</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>82</td><td>5VCC</td><td>Power +5V</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>83</td><td>S_D9</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>84</td><td>P_D5</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>85</td><td>S_D6</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>86</td><td>P_D9</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>87</td><td>S_D8</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>88</td><td>P_D6</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>89</td><td>GPE2#</td><td>-</td><td>I-3,3</td><td>PU 8k2 3,3V</td><td>-</td></tr><tr><td>90</td><td>CBLID_P#</td><td>80-conductor IDE cable Channel 0</td><td>I-3,3</td><td>-</td><td>-</td></tr><tr><td>91</td><td>RXD#</td><td>Ethernet Receive Differential Signal ( RXD-)</td><td>I - DP</td><td>-</td><td>-</td></tr><tr><td>92</td><td>P_D8</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>93</td><td>RXD</td><td>Ethernet Receive Differential Signal ( RXD+)</td><td>I - DP</td><td>-</td><td>-</td></tr><tr><td>94</td><td>S_D7</td><td>Secondary IDE Data Bus</td><td>IO</td><td>-</td><td>-</td></tr><tr><td>95</td><td>TXD#</td><td>Ethernet Transmit Differential Signal (TXD-)</td><td>O -DP</td><td>-</td><td>-</td></tr><tr><td>96</td><td>P_D7</td><td>Primary IDE Data Bus</td><td>IO</td><td>-</td><td>int. PD 11k5</td></tr><tr><td>97</td><td>TXD</td><td>Ethernet Transmit Differential Signal (TXD+)</td><td>O -DP</td><td>-</td><td>-</td></tr><tr><td>98</td><td>HDRST#</td><td>Hard Drive Reset</td><td>O-3,3</td><td>-</td><td>-</td></tr><tr><td>99</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr><tr><td>100</td><td>GND</td><td>Ground</td><td>PWR</td><td>-</td><td>-</td></tr></table>

Signal Descriptions (cont'd)

<table><tr><td colspan="2">Signal Type Legend</td></tr><tr><td>IO-2,5</td><td>Bi-directional 2,5 V Input/Output</td></tr><tr><td>IO-3,3</td><td>Bi-directional 3,3 V Input/Output</td></tr><tr><td>IO-5</td><td>Bi-directional 5 V Input/Output</td></tr><tr><td>I-3,3</td><td>3,3 V Input</td></tr><tr><td>I-5</td><td>5 V Input</td></tr><tr><td>O-2,5</td><td>2,5 V Output</td></tr><tr><td>O-3,3</td><td>3,3 V Output</td></tr><tr><td>O-5</td><td>5 V Output</td></tr><tr><td>IO</td><td>Input/Output</td></tr><tr><td>OA</td><td>Analog Output</td></tr><tr><td>I/O - DP</td><td>Differential Pair Input/Output</td></tr><tr><td>O - DP</td><td>Differential Pair Output</td></tr><tr><td>I - DP</td><td>Differential Pair Input</td></tr><tr><td>PWR</td><td>Power or Ground</td></tr><tr><td>PU</td><td>Pull-Up Resistor</td></tr><tr><td>PD</td><td>Pull-Down Resistor</td></tr><tr><td>NC</td><td>Not Connected / Reserved</td></tr></table>

# 7 System Resources

# 7.1 System Memory Map

<table><tr><td>Address Range (decimal)</td><td>Address Range (hex)</td><td>Size</td><td>Description</td></tr><tr><td>(4GB-2MB)</td><td>FFE00000 - FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB-18MB)-(4GB-17MB-1)</td><td>FEE00000 - FEEFFFFFF</td><td>1 MB</td><td>FSB Interrupt Memory Space</td></tr><tr><td>(4GB-20MB)-(4GB-19MB-1)</td><td>FEC00000 - FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB - 16MB</td><td>F00000 - FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>960 K - 1024 K</td><td>F0000 - FFFFF</td><td>64 KB</td><td>System BIOS Area</td></tr><tr><td>896 K - 960 K</td><td>E0000 - EFFFF</td><td>64 KB</td><td>Extended System BIOS Area</td></tr><tr><td>768 K - 896 K</td><td>C0000 - DFFFF</td><td>128 KB</td><td>PCI expansion ROM areaC0000 - CEFFF: Onboard VGA BIOSCF000 - D1FFF: PXE option ROM when onboard LAN boot ROM is enabled.</td></tr></table>

# 7.2 Direct Memory Access Channels

<table><tr><td>Channel Number</td><td>Data Width</td><td>System Resource</td></tr><tr><td>0</td><td>8-bits</td><td>Parallel port, Note 1</td></tr><tr><td>1</td><td>8-bits</td><td>Parallel port, Note 1</td></tr><tr><td>2</td><td>8-bits</td><td>Diskette drive, Note 1</td></tr><tr><td>3</td><td>8-bits</td><td>Parallel port, Note 1</td></tr><tr><td>4</td><td></td><td>Reserved, Cascade Channel</td></tr><tr><td>5</td><td>16-bits</td><td>Open</td></tr><tr><td>6</td><td>16-bits</td><td>Open</td></tr><tr><td>7</td><td>16-bits</td><td>Open</td></tr></table>

![The image displays a document icon featuring a large red checkmark superimposed over a piece of lined paper. Below the icon, the text 'NOTE ::' is written in black capital letters.](.31-en/14daee28743274df355f2a6d6478366a3828befae5d5cb457629087ab84067d4.jpg)

DMA channel 0/1/3 is selected when using parallel port. Floppy and parallel port can't be used at the same time.

7.3 I/O Address Map

<table><tr><td>Address (hex)</td><td>Size</td><td>Description</td></tr><tr><td>0000 - 001F</td><td>32 bytes</td><td>DMA controller</td></tr><tr><td>0020 - 0021</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>0024 - 0025</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>0028 - 0029</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>002C - 002D</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>002E - 002F</td><td>2 bytes</td><td>LPC SIO</td></tr><tr><td>0030 - 0031</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>0034 - 0035</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>0038 - 0039</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>003C - 003D</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>0040 - 0043</td><td>4 bytes</td><td>Counter/Timer</td></tr><tr><td>0048 - 004B</td><td>4 bytes</td><td>Counter/Timer</td></tr><tr><td>004E - 004F</td><td>2 bytes</td><td>TPM configuration port</td></tr><tr><td>0050 - 0053</td><td>4 bytes</td><td>Counter/Timer</td></tr><tr><td>0060</td><td>1 byte</td><td>Keyboard controller</td></tr><tr><td>0061</td><td>1 byte</td><td>NMI, speaker control</td></tr><tr><td>0063</td><td>1 byte</td><td>NMI controller</td></tr><tr><td>0064</td><td>1 byte</td><td>Keyboard controller</td></tr><tr><td>0065</td><td>1 byte</td><td>NMI controller</td></tr><tr><td>0067</td><td>1 byte</td><td>NMI controller</td></tr><tr><td>0070 - 0071</td><td>2 bytes</td><td>Real time clock controller</td></tr><tr><td>0072 - 0073</td><td>2 bytes</td><td>Real time clock controller</td></tr><tr><td>0074 - 0075</td><td>2 bytes</td><td>Real time clock controller</td></tr><tr><td>0076 - 0077</td><td>2 bytes</td><td>Real time clock controller</td></tr><tr><td>0080 - 0091</td><td>18 bytes</td><td>DMA controller</td></tr><tr><td>0092</td><td>1 bytes</td><td>Reset Generator</td></tr><tr><td>0093 - 009F</td><td>13 bytes</td><td>DMA controller</td></tr><tr><td>00A0 - 00A1</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00A4 - 00A5</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00A8 - 00A9</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00AC - 00AD</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00B0 - 00B1</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00B2 - 00B3</td><td>2 bytes</td><td>Power Management</td></tr><tr><td>00B4 - 00B5</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00B8 - 00B9</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00BC - 00BD</td><td>2 bytes</td><td>Interrupt controller</td></tr><tr><td>00C0 - 00DF</td><td>32 bytes</td><td>DMA controller</td></tr><tr><td>00F0 - 00FF</td><td>16 bytes</td><td>Numeric processor</td></tr><tr><td>0170 - 0177</td><td>8 bytes</td><td>Secondary IDE controller</td></tr><tr><td>01F0 - 01F7</td><td>8 bytes</td><td>Primary IDE controller</td></tr><tr><td>0274 - 0277</td><td>4 bytes</td><td>ISA PnP read port</td></tr><tr><td>0278 - 027F</td><td>8 bytes</td><td>LPT2</td></tr><tr><td>0290 - 029F</td><td>16 bytes</td><td>Onboard Sensor index(0x295)/data port (0x296)</td></tr><tr><td>02E8 - 02EF</td><td>8 bytes</td><td>COM4/Video</td></tr></table>

I/O Address Map (cont'd)

<table><tr><td>Address (hex)</td><td>Size</td><td>Description</td></tr><tr><td>02F8 – 02FF</td><td>8 bytes</td><td>COM2</td></tr><tr><td>0376 – 0377</td><td>2 bytes</td><td>Secondary IDE controller</td></tr><tr><td>0378 – 037F</td><td>8 bytes</td><td>LPT1</td></tr><tr><td>03B0 – 03BB</td><td>12 bytes</td><td>Video (monochrome)</td></tr><tr><td>03BC – 03BF</td><td>4 bytes</td><td>LPT3</td></tr><tr><td>03C0 – 03DF</td><td>32 bytes</td><td>Video (VGA†)</td></tr><tr><td>03E8 – 03EF</td><td>8 bytes</td><td>COM3</td></tr><tr><td>03F0 – 03F5, 03F7</td><td>7 bytes</td><td>Diskette controller</td></tr><tr><td>03F6 – 03F7</td><td>2 bytes</td><td>Primary IDE controller</td></tr><tr><td>03F8 – 03FF</td><td>8 bytes</td><td>COM1</td></tr><tr><td>0400 – 041F</td><td>32 bytes</td><td>Onboard SMBus control registers</td></tr><tr><td>0480 – 04BF</td><td>64 bytes</td><td>GPIO control registers</td></tr><tr><td>04D0 – 04D1</td><td>2 bytes</td><td>Edge/level triggered PIC</td></tr><tr><td>0800 – 087F</td><td>128 bytes</td><td>ACPI control registers.</td></tr><tr><td>0CF8 – 0CFF*</td><td>8 bytes</td><td>PCI configuration registers</td></tr><tr><td>0CF9**</td><td>1 byte</td><td>Reset control register</td></tr><tr><td>04700 – 0470F</td><td>16 bytes</td><td>TPM control registers</td></tr></table>

![The image displays a digital icon featuring a white document sheet with faint horizontal grey lines. A large, bold red checkmark is stamped diagonally across the upper portion of the document. Beneath the graphic, the text 'NOTE:' appears in bold, black capital letters.](.31-en/e79e74105231592b10cedfca477f6d4e806d45285429f85f3f6614302b4e25f3.jpg)

\* DWORD access only
\*\* Byte access only
\*\*\*Following I/O ports are forwarded to ISA bus.
0200 - 023F : 64 bytes
0240 - 025F : 32 bytes
0280 - 028F: 16 bytes
02A0 - 02DF: 64 bytes
0300 - 033F: 64 bytes
0380 - 39F: 32 bytes

# 7.4 Interrupt Request (IRQ) Lines

PIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>N/A</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2) / PCI / ISA</td><td>IRQ3 via SERIRQ, IRQ3 at ISA bus</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1) / PCI / ISA</td><td>IRQ4 via SERIRQ, IRQ4 at ISA bus</td><td>Note (1)</td></tr><tr><td>5</td><td>Parallel Port 2 (LPT2) / PCI / ISA</td><td>IRQ5 via SERIRQ, IRQ5 at ISA bus</td><td>Note (1)</td></tr><tr><td>6</td><td>Floppy Drive Controller</td><td>IRQ6 via SERIRQ</td><td>No</td></tr><tr><td>7</td><td>Parallel Port 1 (LPT1) / PCI / ISA</td><td>IRQ7 via SERIRQ, IRQ7 at ISA bus</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>SCI / PCI</td><td>IRQ9 via SERIRQ, IRQ9 at ISA bus</td><td>Note (1), (2)</td></tr><tr><td>10</td><td>PCI / ISA</td><td>IRQ10 via SERIRQ, IRQ10 at ISA bus</td><td>Note (1)</td></tr><tr><td>11</td><td>PCI / ISA</td><td>IRQ11 via SERIRQ, IRQ11 at ISA bus</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse / PCI / ISA</td><td>IRQ12 via SERIRQ, IRQ12 at ISA bus</td><td>Note (1)</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>No</td></tr><tr><td>14</td><td>Primary IDE controller / PCI / ISA</td><td>IRQ14 via SERIRQ, IRQ14 at ISA bus</td><td>Note (1)</td></tr><tr><td>15</td><td>Secondary IDE controller / PCI / ISA</td><td>IRQ15 via SERIRQ, IRQ15 at ISA bus</td><td>Note (1)</td></tr></table>

![This image features a graphic of a white document icon with a folded top-right corner. A large, red checkmark is centered on the paper, which has faint horizontal lines. Below the icon, the text 'NOTE:' is displayed in bold, black capital letters.](.31-en/3da3bb0d8505608ac9aa439b6434c1c13868bee25d07064dd0a3b5cf6d399e73.jpg)

(1) These IRQs can be used for PCI devices when onboard device is disabled. If IRQ is from ISA, user must reserve IRQ for ISA in BIOS setup menu.
(2) BIOS doesn't open IRQ 9 setting for ISA bus.

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>N/A</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2) / PCI / ISA</td><td>IRQ3 via SERIRQ, IRQ3 at ISA bus</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1) / PCI / ISA</td><td>IRQ4 via SERIRQ, IRQ4 at ISA bus</td><td>Note (1)</td></tr><tr><td>5</td><td>Parallel Port 2 (LPT2) / PCI / ISA</td><td>IRQ5 via SERIRQ, IRQ5 at ISA bus</td><td>Note (1)</td></tr><tr><td>6</td><td>Floppy Drive Controller</td><td>IRQ6 via SERIRQ</td><td>No</td></tr><tr><td>7</td><td>Parallel Port 1 (LPT1) / PCI / ISA</td><td>IRQ7 via SERIRQ, IRQ7 at ISA bus</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A No</td><td></td></tr><tr><td>9</td><td>SCI / PCI</td><td>IRQ9 via SERIRQ, IRQ9 at ISA bus</td><td>Note (1), (2)</td></tr><tr><td>10</td><td>PCI / ISA</td><td>IRQ10 via SERIRQ, IRQ10 at ISA bus</td><td>Note (1)</td></tr><tr><td>11</td><td>PCI / ISA</td><td>IRQ11 via SERIRQ, IRQ11 at ISA bus</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse / PCI / ISA</td><td>IRQ12 via SERIRQ, IRQ12 at ISA bus</td><td>Note (1)</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>No</td></tr><tr><td>14</td><td>Primary IDE controller / PCI / ISA</td><td>IRQ14 via SERIRQ, IRQ14 at ISA bus</td><td>Note (1)</td></tr></table>

APIC Mode (cont'd)

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>15</td><td>Secondary IDE controller / PCI / ISA</td><td>IRQ15 via SERIRQ, IRQ15 at ISA bus</td><td>Note (1)</td></tr><tr><td>16</td><td>N/A</td><td>PCI Slot INT A, Audio, Express IDE controller, VGA controller</td><td>Yes</td></tr><tr><td>17</td><td>N/A</td><td>PCI Slot INT B Yes</td><td></td></tr><tr><td>18</td><td>N/A</td><td>PCI Slot INT C Yes</td><td></td></tr><tr><td>19</td><td>N/A</td><td>PCI Slot INT D, USB controller, SMBus, SATA controller</td><td>Yes</td></tr><tr><td>20</td><td>N/A</td><td>Onboard Lan controller</td><td>No</td></tr><tr><td>21</td><td>N/A</td><td></td><td>No</td></tr><tr><td>22</td><td>N/A</td><td></td><td>No</td></tr><tr><td>23</td><td>N/A</td><td>EHCI, USB</td><td>No</td></tr></table>

![The image displays an icon of a white document featuring three thin, horizontal grey lines. A large, red checkmark is overlaid on the right side of the document. Below the document graphic, the text 'NOTE:' is written in black capital letters.](.31-en/99284584ffb21d99e5d6f18af8f505cd5d718dbd795133958703273ea4833fb8.jpg)

(1) These IRQs can be used for PCI devices when an onboard device is disabled. If IRQ is from ISA, user must reserve IRQ for ISA in BIOS setup menu.

(2) BIOS doesn't open IRQ 9 setting for ISA bus.

7.5 PCI Configuration Space Map

<table><tr><td>Bus #</td><td>Device #</td><td>Function #</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel 945 GME GMCH Host-Hub Interface Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel Integrated Graphics Device</td></tr><tr><td>00h</td><td>02h</td><td>01h</td><td>Internal</td><td>Intel Integrated Graphics Device (Function 1)</td></tr><tr><td>00h</td><td>1Bh</td><td>00h</td><td>Internal</td><td>High Definition Audio controller</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel ICH Express Root port</td></tr><tr><td>00h</td><td>1Dh</td><td>00h</td><td>Internal</td><td>Intel USB UHCI Controller 1</td></tr><tr><td>00h</td><td>1Dh</td><td>01h</td><td>Internal</td><td>Intel USB UHCI Controller 2</td></tr><tr><td>00h</td><td>1Dh</td><td>07h</td><td>Internal</td><td>Intel USB EHCI Controller</td></tr><tr><td>00h</td><td>1Eh</td><td>00h</td><td>N/A</td><td>Intel Hub Interface to PCI Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>N/A</td><td>Intel LPC Interface Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>01h</td><td>Internal</td><td>Intel IDE Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>02h</td><td>Internal</td><td>Intel SATA controller</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>Intel SMBus Controller</td></tr><tr><td>01h</td><td>00h</td><td>00h</td><td>Internal</td><td>PCI Express IDE controller</td></tr><tr><td>02h</td><td>07h</td><td>00h</td><td>N/A</td><td>PCI-to-ISA bridge</td></tr><tr><td>02h</td><td>08h</td><td>00h</td><td>Internal</td><td>Intel LAN controller</td></tr><tr><td>02h</td><td>03h</td><td>00h</td><td>PIRQA-PIRQD</td><td>External PCI Slot 1</td></tr><tr><td>02h</td><td>04h</td><td>00h</td><td>PIRQA-PIRQD</td><td>External PCI Slot 2</td></tr><tr><td>02h</td><td>05h</td><td>00h</td><td>PIRQA-PIRQD</td><td>External PCI Slot 3</td></tr><tr><td>02h</td><td>06h</td><td>00h</td><td>PIRQA-PIRQD</td><td>External PCI Slot 4</td></tr></table>

7.6 PCI Interrupt Routing Map

<table><tr><td>PIRQ</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td><td>G</td><td>H</td></tr><tr><td>INT Line</td><td>INTA</td><td>INTB</td><td>INTC</td><td>INTD</td><td></td><td></td><td></td><td></td></tr><tr><td>VGA</td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>UHCI 1</td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td></tr><tr><td>UHCI 2</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td></tr><tr><td>EHCI</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td></tr><tr><td>SATA</td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td></tr><tr><td>SMbus</td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td></tr><tr><td>Audio</td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCI Slot1</td><td>INTA</td><td>INTB</td><td>INTC</td><td>INTD</td><td></td><td></td><td></td><td></td></tr><tr><td>PCI Slot2</td><td>INTD</td><td>INTA</td><td>INTB</td><td>INTC</td><td></td><td></td><td></td><td></td></tr><tr><td>PCI Slot3</td><td>INTC</td><td>INTD</td><td>INTA</td><td>INTB</td><td></td><td></td><td></td><td></td></tr><tr><td>PCI Slot4</td><td>INTB</td><td>INTC</td><td>INTD</td><td>INTA</td><td></td><td></td><td></td><td></td></tr><tr><td>LAN</td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td></tr></table>

# 7.7 System Management Bus (I²C-compatible)

Internally the SMB bus and I2C bus are one and the same. The ICH7-M Southbridge supports SMBDAT and SMBCLK lines that are I2C-compatible.

The X4 connector has pins for both the I2C and SMB bus. Both are connected to the same internal bus: the SMB bus. It is advisable to always connect external I2C devices to the I2C pins and SMB devices to the SMB pins to ensure compatibility with other modules that might support two internal busses (a separate I2C and SMB bus).

<table><tr><td>Address</td><td>Function</td><td>Device</td></tr><tr><td>2Eh</td><td>Super I/O Read/Write</td><td>SIO</td></tr><tr><td>A0h</td><td>Memory SPD</td><td>SO-DIMM</td></tr><tr><td>D2h</td><td>Clock Generator</td><td>CLK GEN</td></tr></table>

# 8 BIOS Setup Utility

The following chapter describes basic navigation for the AMIBIOS8 BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt;Delete&gt; key on your keyboard when you see the following text prompt:
&lt;Press DEL or Delete to run Setup&gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.

![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST3B410A 007A](.31-en/a2542f38291df8de0ce42d8c4704a4224e34855db29899badaa8800cb2b1767e.jpg)

![The image displays a graphic of a white document with horizontal lines, featuring a large red checkmark in the upper right corner. Below the document graphic, the text 'NOTE:' appears in black capital letters.](.31-en/b56b8ae360e2143849d15ef0fe4f1f25a4a4d76f3e226c49e2057ff806a179bd.jpg)

In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# 8.1.1 Main Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Main</td><td>Advanced</td><td>Power</td><td>Boot</td><td>Security</td><td>Exit</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td colspan="5">System Overview</td><td rowspan="30">Use [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use  $\left\lbrack  +\right\rbrack$  or [-] to configure system Time. Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="29" colspan="5">AMIBIOS Version :08.00.14 Build Date:07/29/08 ID :NR667001 Processor Speed :255MHz Count :255 System Memory Size :504MB System Time [21:00:18] System Date [Fri 01/04/2002]</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

# 8.1.2 Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

These keys include &lt;F1&gt;, &lt;F10&gt;, &lt;Enter&gt;, &lt;ESC&gt;, &lt;Arrow&gt; keys, and so on.

![This flowchart describes the navigation structure of the **BIOS Setup Utility**.\n\n**Blocks and Labels:**\n*   **BIOS Setup Utility**\n*   **Screens**\n*   **Left and Right Keys to Select a Setup Screen**\n*   **Screen 1**, **Screen 2**, **Screen 3**, **Screen 4**, **Screen 5**\n*   **Items**\n*   **Tab Key to Select Fields**\n*   **± To Change Field Values** (Note: The symbol inside the boxes is likely a '±' sign)\n*   **Up and Down Keys to Select a Setup Item**\n*   **Fields**\n\n**Connections:**\n1.  **BIOS Setup Utility** connects via a downward arrow to **Screens**.\n2.  **Screens** connects via a downward arrow to **Items**.\n3.  **Left and Right Keys to Select a Setup Screen** connects via a dashed arrow to **Screen 1**.\n4.  **Screen 1** through **Screen 5** are arranged horizontally and connected to each other by double-headed horizontal arrows.\n5.  **Tab Key to Select Fields** connects via a dashed arrow to the first box (containing '±') in the top row below **Items**.\n6.  **± To Change Field Values** connects via a dashed arrow to the third box (containing '±') in the top row.\n7.  The three boxes in the top row below **Items** are connected horizontally by double-headed arrows.\n8.  Vertical double-headed arrows (pointing up and down) are positioned between the top and bottom rows of boxes.\n9.  **Up and Down Keys to Select a Setup Item** connects via a dashed arrow to the vertical arrows.\n10. The three boxes in the bottom row (containing '±') are connected horizontally by double-headed arrows.\n11. **Fields** connects via an arrow to the bottom row of boxes.](.31-en/b3dd0c39756fe0fac8118b7d9e0393f23293abc0bed34414b000578ae645f5c9.jpg)

![The image displays a line-art icon of a document with horizontal lines, stamped with a large red checkmark. Beneath the icon, the text 'NOTE:' is written in bold, black capital letters.](.31-en/9cc70b139da9290cd08b5962ba2a948d7f4dd3e9f812e180576da8819402c1a7.jpg)

There is a hot key legend located in the right frame on most setup screens.

<table><tr><td>Hot Key</td><td>Description</td></tr><tr><td> $\rightarrow \leftarrow$ </td><td>Left/Right The Left and Rightkeys allow you to select a setup screen.For example: Main screen, Advanced screen, Chipset screen, and so on.</td></tr><tr><td> $\uparrow \downarrow$ </td><td>Up/Down The Up and Downkeys allow you to select a setup item or sub-screen.</td></tr><tr><td>+ -</td><td>Plus/Minus The Plus and Minuskeys allow you to change the field value of a particular setup item.For example: Date and Time.</td></tr><tr><td>Tab</td><td>Thekey allows you to select setup fields.</td></tr></table>

![The image displays a white icon of a document with faint horizontal lines and a large red checkmark centered on it. Below this graphic, the text 'NOTE :' is written in black capital letters.](.31-en/619fc0550b1743d355c192c3b02632f8953c6170417b2fa6556b87a7dd7a2f9c.jpg)

The &lt;F8&gt; key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the &lt;F8&gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

# Hot Key Description

F1 The &lt; F1 &gt; key allows you to display the General Help screen.

Press the &lt; F1 &gt; key to open the General Help screen.

General Help

<table><tr><td>←→</td><td>Select Screen</td><td>↓↑</td><td>Select Item</td></tr><tr><td>+-</td><td>Change Screen</td><td>Enter</td><td>Go to Sub Screen</td></tr><tr><td>PGDN</td><td>Next Page</td><td>PGUP</td><td>Previous Page</td></tr><tr><td>Home</td><td>Go to Top of the Screen</td><td>End</td><td>Go to Bottom of Screen</td></tr><tr><td>F2/F3</td><td>Change Colors</td><td>F7</td><td>Discard Changes</td></tr><tr><td>F8</td><td>Load Failsafe Defaults</td><td>F9</td><td>Load Optimal Defaults</td></tr><tr><td>F10</td><td>Save and Exit</td><td>ESC</td><td>Exit</td></tr></table>

[Ok]

F10 The &lt; F10 &gt; key allows you to save any changes you have made and exit Setup. Press the &lt; F10 &gt; key to save your changes. The following screen will appear:

Save configuration changes and exit now?

[Ok]

[Cancel]

Press the &lt;Enter&gt; key to save the configuration and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

ESC The &lt;Esc&gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt;Esc&gt; key to exit the setup without saving your changes. The following screen will appear:

Discard changes and exit setup now?

[Ok]

[Cancel]

Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

Enter The &lt;Enter&gt; key allows you to display or change the setup option listed for a particular setup item. The &lt;Enter&gt; key can also allow you to display the setup sub-screens.

# 8.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.

<table><tr><td colspan="5">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>Power</td><td>Boot</td><td>Security Exit</td></tr><tr><td colspan="4">System Overview</td><td rowspan="2">Use [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use  $\left\lbrack  +\right\rbrack$  or  $\left\lbrack  -\right\rbrack$  to configure system Time.</td></tr><tr><td rowspan="2" colspan="4">AMIBIOS Version :08.00.14 Build Date:07/29/08 ID :NR667001 Processor Speed :255MHz Count :255 System Memory Size :504MB System Time [21:00:18] System Date [Fri 01/04/2002]</td></tr><tr><td>← Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit</td></tr></table>

# 8.2.1 System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the &lt;Arrow&gt; keys. Enter new values using the keyboard. Press the &lt;Tab&gt; key or the &lt;Arrow&gt; keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

![The image displays an icon of a white document page with horizontal lines and a large red checkmark overlaid on it. Below the page graphic, the text 'NOTE:' appears in bold, black, uppercase letters.](.31-en/71a5cbf35aff1fcf4d57f988904a974ade0a087d09e354fd15997f94f0386c76.jpg)

The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

# 8.3 Advanced BIOS Setup

Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Advanced BIOS Setup screen is shown below.

The sub menus are described on the following pages.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Main Advanced Power Boot Security Exit</td></tr><tr><td>Advanced Settings</td><td>Configure CPU.</td></tr><tr><td>CPU Configuration
Chipset Configuration
Video Function Configuration
IDE Configuration
Onboard Device Configuration
USB Configuration
PCIPnP Configuration
Remote Access Configuration
Trusted Computing</td><td>Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

![The image displays a standard warning symbol featuring a triangle with a black border and a red gradient background that is lighter at the top and darker at the bottom. In the center of the triangle is a white exclamation point. Below the triangle, the text 'WARNING:' is printed in black, bold, capital letters.](.31-en/a9ae3a1919af7aebf11c3d826f9cdb19476c1894eaec0e062493b4f151f059a8.jpg)

Setting incorrect or conflicting values in Advanced BIOS Setup may cause system malfunctions.

# 8.3.1 CPU Configuration

# CPU Configuration Settings

You can use this screen to select options for the CPU Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;- &gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>Configure advanced CPU settings
Module Version -13.04</td><td>Disabled for WindowsXP</td></tr><tr><td>Manufacturer:Intel
Brand String:
Frequency :255MHz
FSB Speed :667MHz</td><td></td></tr><tr><td>Cache L1 :0 KB
Cache L2 :0 KB</td><td></td></tr><tr><td>Max CPUID Value Limit: [Enabled]
Execute Disable Bit [Enabled]
Core Multi-Processing [Enabled]
Vanderpool Technology: [Enabled]
Intel(R) SpeedStep(tm) tech. [Disabled]
Intel(R) C-State tech.
C1 Config. [Standard]
C2 Config. [Standard]</td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Max CPUID Value Limit

When the computer is booted up, the operating system executes the CPUID instruction to identify the processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input value CPUID recognizes. This determines the kind of basic information CPUID can provide the operating system. This option allows you to circumvent problems with older operating systems.

When Enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When Disabled, the processor will return the actual maximum CPUID input value of the processor when queried.

# Execute Disable Bit

This is an Intel hardware-based security feature that can help reduce system exposure to viruses and malicious code. It allows the processor to classify areas in memory where application code can or cannot execute. When a malicious worm attempts to insert code in the buffer, the processor disables its code execution, preventing damage and worm propagation. To use Execute Disable Bit you must have a PC or server with a processor with Execute Disable Bit capability and a supporting operating system.

# Core Multi-Processing

This item is visible depending on the CPU being used on the board. Multi-core capability of the CPU is enabled/disabled by this setting if the CPU supports this feature.

# Vanderpool Technology

This is used to enable or disable the Intel Virtualization Technology (IVT) extension, which is also known by the development code name Vanderpool. It allows multiple operating systems to run simultaneously on the same system. It does this by creating virtual machines, each running its own x86 operating system. When Enabled, the IVT extensions will be enabled, allowing for hardware-assisted virtual machine management. When Disabled, the IVT extensions will be disabled. However, software virtual machine managers like VMware can still be used if virtualization is required.

# Intel SpeedStep tech.

This option enables or disables Intel SpeedStep technology.

# Cx Config.

Controls the C-state of the CPU.

# 8.3.2 Chipset Configuration

# Chipset Configuration Settings

Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the &lt;Arrow&gt; keys. The Chipset BIOS Setup screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>Advanced Chipset Settings</td><td>Options</td></tr><tr><td>DRAM Frequency [Auto] Configure DRAM Timing by SPD [Enabled] Memory Hole [Disabled] POST code Route [PCI]</td><td>Auto 400 MHz 533 MHz ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# DRAM Frequency

Sets the DRAM frequency. The frequency can be set by BIOS automatically or configured manually.

# Configure DRAM Timing by SPD

Enable/Disable whether the DRAM timing is configured by SPD or set by manually.

# Memory Hole

Enable/disable the Memory Hole function. Memory Hole will be located at 15MB-16MB of system memory.

# POST Code Route

This option controls the output of the data of IO port 80h to either PCI or LPC bus.

# 8.3.3 Video Function Configuration

# Video Function Configuration Settings

You can use this screen to select options for Video Function configuration settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The video function BIOS Setup screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>Video Function Configuration</td><td rowspan="4">Select which graphics controller to use as the primary boot device.</td></tr><tr><td>Boots Graphic Adapter Priority [PEG/PCI] Internal Graphics Mode Select [Enabled, 8MB]</td></tr><tr><td>DUMT Mode Select [DUMT Model] DUMT/FIXED Memory [128MB]</td></tr><tr><td>Boot Display Device [CRT] Flat Panel Type [640x480]</td></tr><tr><td></td><td>← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Boots Graphic Adapter Priority

Select which graphics controller to use as the primary boot display device. IGD = Integrated Graphic Device. PEG/PCI = external PCI/express graphic device.

# Internal Graphics Mode Select

Select the amount of system memory used by the Integrated Graphic Device.

# DVMT Mode Select

Unified Memory Architecture (UMA) is a concept whereby system memory is shared by both CPU and graphics processor. While this reduces cost, it also reduces the system's performance by taking up a large portion of memory for the graphics processor. Intel's Dynamic Video Memory Technology (DVMT) takes that concept further by allowing the system to dynamically allocate memory resources according to the demands of the system at any point in time. The key idea in DVMT is to improve the efficiency of the memory allocated to either system or graphics processor.

When set to Fixed Mode, the graphics driver will reserve a fixed portion of the system memory as graphics memory. When set to DVMT Mode, the graphics chip will dynamically allocate system memory as graphics memory, according to system and graphics requirements. When set to Combo Mode, the graphics driver will allocate a fixed amount of memory as dedicated graphics memory, as well as allow more system memory to be dynamically allocated between the graphics processor and the operating system.

# DVMT/FIXED Memory

Sets the amount of memory according to DVMT Mode Select.

# Boot Display Device

Selects which display interface is active on boot up.

# Flat Panel Type

If LVDS is selected as Boot Display Device, this option opens provides resolution settings for correct timing output to the LVDS interface.

# 8.3.4 IDE Configuration

# IDE Configuration Settings

You can use this screen to select options for the IDE Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;- &gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>IDE Configuration</td><td>Options</td></tr><tr><td>ATA/IDE Configuration [Compatible] Legacy IDE Channels [SATA Pri, PATA Sec]</td><td>Disabled Compatible Enhanced</td></tr><tr><td>► Primary IDE Master : [Not Detected]</td><td></td></tr><tr><td>► Primary IDE Slave : [Not Detected]</td><td></td></tr><tr><td>► Secondary IDE Master : [Not Detected]</td><td></td></tr><tr><td>► Secondary IDE Slave : [Not Detected]</td><td></td></tr><tr><td>JMicron 36x ATA Controller [Enabled]</td><td>← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# ATA/IDE Configuration

This item specifies whether the IDE channels should be initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced.

# Legacy IDE Channels

When running in compatible mode, the SATA channel can be configured as a legacy IDE channel. The location of the IDE channel is selectable.

# Primary IDE Master/Slave, Secondary IDE Master/Slave

Select one of the hard disk drives to configure it. Press &lt; Enter &gt; to access its sub menu.

# JMicro 36x ATA Controller

The South Bridge only supports the primary IDE channel. An ATA controller is used to provide an IDE interface to the secondary channel. Set it to Enabled or Disabled depending on the usage of the secondary IDE channel.

# 8.3.5 Onboard Device Configuration

# Onboard Device Configuration Settings

You can use this screen to specify options for the onboard device configuration Settings. Use the up and down &lt;Arrow &gt; keys to select an item. Use the &lt; + &gt; and &lt; - &gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY
Advanced</td></tr><tr><td>Onboard Device Configuration</td><td>Options</td></tr><tr><td>Audio Controller [Auto]
Onboard LAN Controller [Enabled]
Onboard Lan Boot ROM [Disabled]</td><td>Auto
Azalia
AC&#x27;97 Audio and Modem
All Disabled</td></tr><tr><td>► SuperIO Configuration</td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Audio Controller

Set this value to Enable/Disable the Audio Controller.

# Onboard LAN Controller

Set this value to Enable/Disable the LAN Controller.

# Onboard Lan Boot ROM

Set this value to enable/disable the onboard LAN's PXE ROM to enable boot from LAN. Setting to Disabled can shorten the POST time without initializing LAN PXE ROM if boot from LAN is not needed.

# SuperIO Configuration Screen

SuperIO configuration screen is a sub-menu of Onboard Device Configuration. You can use this screen to select options for the Super IO settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;- &gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Advanced</td><td></td></tr><tr><td>Configure Win627 Super IO ChipsetSerial Port1 Address [3F8/IRQ4]Serial Port2 Address [2F8/IRQ3]Serial Port2 Mode [Normal]LPT Setting / FDD [378]Parallel Port Mode [Normal]Parallel Port IRQ [IRQ7]Floppy A [1.44 MB 3 $\frac{1}{2}$ &quot;]</td><td>Allows BIOS to Select Serial Port1 Base Addresses.&lt; Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Serial Port1 Address

This option specifies the base I/O port address and Interrupt Request address of serial port 1.

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Disabled</td><td>Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable.</td></tr><tr><td>3F8/IRQ4</td><td>Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt address.</td></tr><tr><td>3E8/IRQ4</td><td>Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 4 for the interrupt address.</td></tr><tr><td>2F8/IRQ3</td><td>Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 3 for the interrupt address.</td></tr><tr><td>2E8/IRQ3</td><td>Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 3 for the interrupt address.</td></tr></table>

# Serial Port2 Address

This option specifies the base I/O port address and Interrupt Request address of Serial Port2. The settings of Serial Port2 are the same as Serial Port1. However, the setting used by Serial Port1 will not be available for Serial Port2. For example, if Serial Port1 uses 3F8/IRQ4, the option, the 3F8/IRQ4 will not appear in the options of Serial Port2.

# Serial Port2 Mode

This option allows the BIOS to select a mode for Serial Port2. The settings are Normal, IrDA, and ASK IR.

# LPT Setting / FDD

Assigns resources to LPT1 or an FDD drive. LPT1 and FDD share the same pins on the X3 connector and only one may be used at a time.

# Parallel Port Mode

This option specifies the parallel port mode.

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Normal</td><td>Set this value to allow the standard parallel port mode to be used.</td></tr><tr><td>EPP</td><td>The parallel port can be used with devices that adhere to the Enhanced Parallel Port (EPP) specification. EPP uses the existing parallel port signals to provide asymmetric bidirectional data transfer driven by the host device.</td></tr><tr><td>ECP</td><td>The parallel port can be used with devices that adhere to the Extended Capabilities Port (ECP) specification. ECP uses the DMA protocol to achieve data transfer rates up to 2.5 Megabits per second. ECP provides symmetric Bidirectional communication.</td></tr><tr><td>EPP+ECP</td><td>Allows the parallel port to support both the ECP and EPP modes simultaneously.</td></tr></table>

# Parallel Port IRQ

This option specifies the IRQ used by the parallel port.

<table><tr><td>Option</td><td>Description</td></tr><tr><td>IRQ5</td><td>Set this value to allow the serial port to use Interrupt 5.</td></tr><tr><td>IRQ7</td><td>Set this value to allow the serial port to use Interrupt 7. The majority of parallel ports on computer systems use IRQ7 and I/O Port 378H as the standard setting.</td></tr></table>

# Floppy Drive A:

This option selects the floppy type. The Optimal and Fail-Safe settings for floppy drive A: is 1.44 MB 3½".

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Disabled</td><td>Set this value to prevent the use of the selected floppy disk drive channel. This option should be set if no floppy disk drive is installed on the specified channel.</td></tr><tr><td>360 KB 5 1⁄4&quot;</td><td>Set this value if the floppy disk drive attached to the corresponding channel is a 360 KB 51⁄4&quot; floppy disk drive.</td></tr><tr><td>1.2 MB 5 1⁄4&quot;</td><td>Set this value if the floppy disk drive attached to the corresponding channel is a 1.2 MB 51⁄4&quot; floppy disk drive.</td></tr><tr><td>720 KB 3 1⁄2&quot;</td><td>Set this value if the floppy disk drive attached to the corresponding channel is a 720 KB 31⁄2&quot; floppy disk drive.</td></tr><tr><td>1.44 MB 3 1⁄2&quot;</td><td>Set this value if the floppy disk drive attached to the corresponding channel is a 1.44 MB 31⁄2&quot; floppy disk drive. This is the default setting for Floppy Drive A.</td></tr><tr><td>2.88 MB 3 1⁄2&quot;</td><td>Set this value if the floppy disk drive attached to the corresponding channel is a 2.88 MB 31⁄2&quot; floppy disk drive.</td></tr></table>

# 8.3.6 USB Configuration

# USB Configuration Settings

You can use this screen to specify options for the USB configuration Settings. Use the up and down &lt;Arrow &gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>USB Configuration</td><td>Options</td></tr><tr><td>Module Version - 2.24.0-11.4</td><td>Disabled
Enabled</td></tr><tr><td>USB Devices Enabled :
1 Drive</td><td></td></tr><tr><td>USB Functions [Enabled]</td><td></td></tr><tr><td>USB 2.0 Controller [Enabled]</td><td></td></tr><tr><td>Legacy USB Support [Enabled]</td><td></td></tr><tr><td>Port 64/60 Emulation [Disabled]</td><td></td></tr><tr><td>USB 2.0 Controller Mode [FullSpeed]</td><td></td></tr><tr><td>BIOS EHCI Hand-Off [Enabled]</td><td></td></tr><tr><td>► USB Mass Storage Device Configuration</td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# USB Function

Set this value to allow the system to Disable, Enable, and select a set number of onboard USB ports.

# USB 2.0 Controller

Depends on the setting of USB Function. If USB Function is set to Disabled, this option will have no effect. Enabled will open USB 2.0 functionality to all USB ports.

# Legacy USB Support

Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is not enabled, any attached USB mouse or keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or keyboard can control the system even when there are no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB Support (see below).

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Disabled</td><td>Set this value to prevent the use of any USB device in DOS or during system boot.</td></tr><tr><td>Enabled</td><td>Set this value to allow the use of USB devices during boot and while using DOS.</td></tr><tr><td>Auto</td><td>This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS.</td></tr></table>

# Port 64/60 Emulation

It uses USB to receive the IO port 64/60 trap to emulate the legacy keyboard controller.

# USB 2.0 Controller Mode

The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps).

# BIOS EHCI hand-off

This option provides a work around for OSes without ECHI hand-off support. The EHCI ownership change should be claimed by the EHCI driver.

# USB Mass Storage Device Configuration

This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on the USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>USB Mass Storage Device Configuration
USB Mass Storage Reset Delay [20 Sec]
Device #1 USB Flash Disk
Emulation Type [Auto]</td><td>Number of seconds
POST waits for the
USB mass storage
device after start
unit command.
← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# 8.3.7 PCIPnP Configuration

# PCIPnP Configuration Settings

You can display a Plug and Play BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys to select an item. The Plug and Play BIOS Setup screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Advanced</td><td></td></tr><tr><td>Advanced PCI/PnP Settings</td><td rowspan="8">Value in units of PCI clocks for PCI device latency timer register.</td></tr><tr><td>WARNING: Setting wrong values in below sections may cause system to malfunction.</td></tr><tr><td>PCI Latency Timer [64]</td></tr><tr><td>Palette Snooping [Disabled]</td></tr><tr><td>IRQ3 [Available]</td></tr><tr><td>IRQ4 [Available]</td></tr><tr><td>IRQ5 [Available]</td></tr><tr><td>IRQ7 [Available]</td></tr><tr><td>IRQ9 [Available]</td><td rowspan="6">← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td>IRQ10 [Available]</td></tr><tr><td>IRQ11 [Available]</td></tr><tr><td>IRQ14 [Available]</td></tr><tr><td>IRQ15 [Available]</td></tr><tr><td>Enable ISA PnP configuration [Disabled]</td></tr><tr><td colspan="2">v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# PCI Latency Timer

Set this value to allow the PCI Latency Timer to be adjusted. This option sets the latency of all PCI devices on the PCI bus.

# Palette Snooping

Set this value to allow the system to modify the Palette Snooping settings.

Disabled - should not be changed unless the VGA card manufacturer requires Palette Snooping to be Enabled.

Enabled - This setting informs the PCI devices that an ISA based Graphics device is installed in the system. It does this so the ISA based Graphics card will function correctly. This does not necessarily indicate a physical ISA adapter card. The graphics chipset can be mounted on a PCI card. Always check with your adapter card's manuals first, before modifying the setting in the BIOS.

# IRQ

Set this value to allow the IRQ settings to be modified. Available - This setting allows the specified IRQ to be used by a PCI/PnP device. Reserved - This setting allows the specified IRQ to be used by a legacy ISA device.

# Enable ISA PnP configuration

Some ISA PnP cards need BIOS to configure resources of the card. Due to the limited IO ranges that the PCI-to-ISA bridge can forward to ISA bus, the ISA PnP configuration I/O port is disabled by default. The board only opens some ISA I/O port windows for use. When there is an ISA PnP card that needs a resource to be configured, enable this item and BIOS will detect and configure the resource of the ISA PnP card automatically.

# 8.3.8 Remote Access Configuration

# Remote Access Configuration

Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Advanced</td><td></td></tr><tr><td colspan="2">Configure Remote Access type and parameters</td></tr><tr><td>Remote Access</td><td>[Enabled]</td></tr><tr><td>Serial port number</td><td>[COM1]</td></tr><tr><td>Base Address, IRQ</td><td>[3F8h, 4]</td></tr><tr><td>Serial Port Mode</td><td>[115200 8,n,1]</td></tr><tr><td>Flow Control</td><td>[None]</td></tr><tr><td>Redirection After BIOS POST</td><td>[Always]</td></tr><tr><td>Terminal Type</td><td>[ANSI]</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>[Enabled]</td></tr><tr><td>Sredir Memory Display Delay</td><td>[No Delay]</td></tr><tr><td></td><td></td></tr></table>

# Remote Access

Select this option to Enable or Disable the BIOS remote access feature.

![The image displays a graphic icon featuring a white document with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark. Below the document icon is the text 'NOTE:' in black, capital serif letters.](.31-en/8a59537a8b22001a8d267c634027762316e16989be1d9344c9f8f8ced3b16052.jpg)

Enabled Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot.

# Serial Port Number

Select the serial port you want to use for the remote access interface. You can set the value for this option to either COM1 or COM2.

![The image displays a white document icon with a folded top-right corner featuring a large red checkmark. Below the icon is the text 'NOTE:' in dark grey capital letters.](.31-en/504a58ee6ae0d76840d4de1d853fa3c8b5943f4a7be3ae137e791a561661b2a1.jpg)

If you have changed the resource assignment of the serial ports in Advanced>Onboard Device Configuration>SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the available Remote Access options.

# Serial Port Mode

Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1.

# Flow Control

Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software.

# Redirection After BIOS POST

This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Disabled</td><td>Set this value to turn off the redirection after POST</td></tr><tr><td>Boot Loader</td><td>Set this value to allow the redirection to be active during POST and Boot Loader.</td></tr><tr><td>Always</td><td>Set this value to allow the redirection to be always active.</td></tr></table>

# Terminal Type

This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8.

# VT-UTF8 Combo Key Support

This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled.

# Sredir Memory Display Delay

This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec.

# 8.3.9 Trusted Computing

Trusted computing is an industry standard to make personal computers more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>Trusted Computing</td><td rowspan="4">Enable/Disable TPM
TCG (TPM 1.1/1.2) supp
in BIOS</td></tr><tr><td>TCG/TPM SUPPORT [Yes]</td></tr><tr><td>TPM Enable/Disable Status [No State]</td></tr><tr><td>TPM Owner Status [No State]</td></tr><tr><td></td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# 8.4 Power Management

Select the Power tab from the setup screen to enter the power management BIOS Setup screen. You can select any of the items in the left frame of the screen, such as ACPI Configuration, to go to the sub menu for that item. The power management BIOS Setup screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Main Advanced Power Boot Security Exit</td></tr><tr><td>Power Management Settings</td><td>Section for Advanced ACPI Configuration.</td></tr><tr><td>ACPI Configuration
APM Configuration
Hardware Health Configuration</td><td>Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# 8.4.1 ACPI Configuration

# Advanced ACPI Configuration

You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;- &gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on this page. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Power</td><td></td></tr><tr><td>General ACPI ConfigurationSuspend mode [S3 (STR)]Repost Video on S3 Resume [No]ACPI OS shutdown mode [ATX]</td><td>Select the ACPI state used for System Suspend.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Suspend mode

This setting selects either S1 (POS) or S3 (STR) system suspend mode. The Optimal and Fail-Safe Default setting is S3 (STR).

<table><tr><td>Option</td><td>Description</td></tr><tr><td>S1 (POS)</td><td>Power On Suspend - Under this setting the CPU is not executing instructions, all power resources that supply system level reference of S0 are off, system memory context is maintained, devices that reference power resources that are on are on, and devices that can wake-up the system can cause the cpu to continue to execute from where it left off.</td></tr><tr><td>S3 (STR)</td><td>Suspend to RAM - Under this setting the system enters a low power state instead of being completely shut off. This allows the computer system to boot up in a few seconds.</td></tr></table>

# Repost Video on S3 Resume

This setting is only visible when suspend mode is set to S3 (STR). Use this option to select whether or not to perform BIOS video initialization after resuming from S3.

# ACPI OS shutdown mode

This setting selects either ATX or AT shutdown mode. ATX mode is the default.

# 8.4.2 APM Configuration

Select the Advanced tab from the setup screen to enter the APM Configuration Setup screen. You can display a Power Management/APM Setup option by highlighting it using the &lt;Arrow&gt; keys.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Power</td><td></td></tr><tr><td>APM Configuration</td><td>Enable or disable APM.</td></tr><tr><td>Power Management/APM [Enabled]</td><td></td></tr><tr><td>Video Power Down Mode [Disabled]</td><td></td></tr><tr><td>Hard Disk Power Down Mode [Disabled]</td><td></td></tr><tr><td>Suspend Time Out [Disabled]</td><td></td></tr><tr><td>Throttle Slow Clock Ratio [50%]</td><td></td></tr><tr><td>Advanced Resume Event Controls</td><td></td></tr><tr><td>Resume On LAN [Disabled]</td><td></td></tr><tr><td>Resume On PME# [Disabled]</td><td></td></tr><tr><td>Resume On RTC Alarm [Disabled]</td><td></td></tr><tr><td>Restore on AC Power Loss [Last State]</td><td>← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Power Management/APM

Set this value to Enable or Disable Power Management/APM (Advanced Power Management) features.

# Video Power Down Mode

This option specifies the Power State that the video subsystem enters when the BIOS places it in a power saving state after the specified period of display inactivity has expired. The options are Disabled and Suspend.

# Hard Disk Drive Power Down Mode

This option specifies the power conserving state that the hard disk drive enters after the specified period of hard drive inactivity has expired.

# Suspend Time Out

This option specifies the length of time the system waits before it enters suspend mode. The options are Disabled, 1 Min, 2 Min, 4 Min, 8 Min, 10 Min, 20 Min, 30 Min, 40 Min, 50 Min, and 60 Min.

# Throttle Slow Clock Ratio

When the system enters suspend or standby mode, the CPU clock runs only part of the time. You may select the percent of time that the clock runs. You may select the percentage of time that the clock runs. When CPU temperature exceeds the setting of CPU Throttling Temperature, the CPU clock will also be throttled according to this setting.

# Advanced Resume Event Controls

These settings specify which events will generate a system wake event. The available events are On LAN, PME# and RTC Alarm. The options are Enabled and Disabled.

# Restore on AC Power Loss

Determines what state the computer enters when AC power is restored after a power loss. The options for this value are Last State, Power On and Power Off.

<table><tr><td>Option</td><td>Description</td></tr><tr><td>Power Off</td><td>Set this value to always power off the system while AC power is restored.</td></tr><tr><td>Power On</td><td>Set this value to always power on the system while AC power is restored.</td></tr><tr><td>Last State</td><td>Set this value to power off/on the system depending on the last system power state while AC power is restored.</td></tr></table>

# 8.4.3 Hardware Health Configuration

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Power</td><td></td></tr><tr><td>Hardware Health Configuration</td><td rowspan="4">Enables Hardware
Health Monitoring
Device.</td></tr><tr><td>H/W Health Function [Enabled]
CPU Throttling Temperature [Disabled]</td></tr><tr><td>Hardware Health Event Monitoring</td></tr><tr><td>System Temperature :36°C/96°F
CPU Temperature :38°C/100°F</td></tr><tr><td>Vcore :0.951 V
+1.05V :1.064 V
+3.3Vin :3.500 V
+5Vin :5.053 V
UBAT :3.129 V</td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# H/W Health Function

This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. The options are Enabled and Disabled.

# CPU Throttling Temperature

This option is designed for temperature protection of the CPU. Temperature values can be set to let the system know when it should control the clock rate of the CPU. Once CPU's temperature exceeds the set temperature, the CPU clock will run at part-time according to "Throttle Slow Clock Ratio" setting (see APM Configuration above).

# 8.5 Boot Setup

Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display an Boot BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Boot Settings screen is shown below:

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Main Advanced Power Boot Security Exit</td></tr><tr><td>Boot Settings</td><td>Configure Settings during System Boot.</td></tr><tr><td>► Boot Settings Configuration</td><td></td></tr><tr><td>1st Boot Device [Removable Dev.]</td><td></td></tr><tr><td>2nd Boot Device [CD/DVD]</td><td></td></tr><tr><td>3rd Boot Device [Hard Drivel]</td><td></td></tr><tr><td>4th Boot Device [USB:USB Flash Disk]</td><td></td></tr><tr><td>5th Boot Device [Network]</td><td></td></tr><tr><td>► Hard Disk Drives</td><td></td></tr><tr><td>► Removable Drives</td><td></td></tr><tr><td>► CD/DVD Drives</td><td></td></tr><tr><td>► USB Drives</td><td></td></tr><tr><td>► Network Drives</td><td>← Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Boot Settings Configuration

Use this screen to select options for the Boot Settings Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

# BIOS SETUP UTILITY

# Boot

# Boot Settings Configuration

Quick Boot

Quiet Boot

Bootup Num-Lock

[Enabled]

[Disabled]

[On]

Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Quick Boot

Disabled - Set this value to allow the BIOS to perform all POST tests.

Enabled - Set this value to allow the BIOS to skip certain POST tests to boot faster.

# Quiet Boot

Disabled - Set this value to allow the computer system to display the POST messages.

Enabled - Set this value to allow the computer system to display the OEM logo.

# Bootup Num-Lock

Set this value to allow the Number Lock setting to be modified during boot up.

Off - This option does not enable the keyboard Number Lock automatically. To use the 10-keys on the keyboard, press the Number Lock key located on the upper left-hand corner of the 10-key pad. The Number Lock LED on the keyboard will light up when the Number Lock is engaged.

On - Set this value to allow the Number Lock on the keyboard to be enabled automatically when the computer system is boot up. This allows the immediate use of 10-keys numeric keypad located on the right side of the keyboard. To confirm this, the Number Lock LED light on the keyboard will be lit.

# Boot Device Priority

Set the boot device options to determine the sequence in which the computer checks which device to boot from.

# Boot Device Groups

The Boot devices are listed in groups by device type. First press &lt;Enter&gt; to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press &lt;+&gt;, &lt;-&gt; or &lt;PageUp&gt;, &lt;PageDown&gt; key to move it up/down in the priority list. For example, USB storage disks will be listed as "USB Drives" in the sub-menu as below. Only the first device in each device group will be available for selection in the Boot Device Priority option.

<table><tr><td colspan="2">BIOS SETUP UTILITY
Boot</td></tr><tr><td>USB Drives</td><td rowspan="2">Specifies the boot sequence from the available devices.</td></tr><tr><td>1st Drive [USB:USB Flash Disk]</td></tr><tr><td></td><td>← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# 8.6 Security Setup

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Main Advanced Power Boot Security Exit</td></tr><tr><td>Security Settings</td><td rowspan="2">Install or Change the password.</td></tr><tr><td>Supervisor Password :Not Installed
User Password :Not Installed</td></tr><tr><td>Change Supervisor Password
Change User Password
Clear User Password</td><td>← Select Screen
↑↓ Select Item
Enter Change
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# 8.6.1 Password Support

# Two Levels of Password Protection

Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password.

The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure.

# Remember the Password

Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM.

Select Security Setup from the Setup main BIOS setup menu. Security Setup options, such as password protection and virus protection, are described in this section. To access the sub menu for the following items, select the item and press &lt;Enter&gt;:0 Change Supervisor Password

- Change User Password
- Clear User Password

# Supervisor Password

Indicates whether a supervisor password has been set.

# User Password

Indicates whether a user password has been set.

# Change Supervisor Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the supervisor password.

# Change User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the user password.

# Clear User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to clear the user password.

# 8.6.2 Change Supervisor Password

Select Change Supervisor Password from the Security Setup menu and press &lt; Enter &gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes.

# 8.6.3 Change User Password

Select Change User Password from the Security Setup menu and press &lt; Enter &gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes.

# 8.6.4 Clear User Password

Select Clear User Password from the Security Setup menu and press &lt; Enter &gt;.

Clear New Password

[Ok] [Cancel]

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after setup completes.

# 8.7 Exit Menu

Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Exit BIOS Setup screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td>Main Advanced Power Boot Security Exit</td><td></td></tr><tr><td>Exit Options Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe Defaults</td><td>Exit system setup after saving the changes. F10 key can be used for this operation. Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Save Changes and Exit

When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect. Select Exit Saving Changes from the Exit menu and press &lt;Enter&gt;.

Save Configuration Changes and Exit Now?

[Ok] [Cancel]

appears in the window. Select Ok to save changes and exit.

# Discard Changes and Exit

Select this option to quit Setup without making any permanent changes to the system configuration. Select Exit Discarding Changes from the Exit menu and press &lt;Enter&gt;.

Discard Changes and Exit Setup Now?

[Ok] [Cancel]

appears in the window. Select Ok to discard changes and exit.

# Discard Changes

Select Discard Changes from the Exit menu and press &lt;Enter&gt;.

Select Ok to discard changes.

# Load Optimal Defaults

Automatically sets all Setup options to a complete set of default settings when you Select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems.

Select Load Optimal Defaults from the Exit menu and press &lt; Enter &gt;.

Select Ok to load optimal defaults.

# Load Failsafe Defaults

Automatically sets all Setup options to a complete set of default settings when you Select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the Fail-Safe Setup options if your computer is experiencing system configuration problems.

Select Load Fail-Safe Defaults from the Exit menu and press &lt; Enter &gt;.

Load Fail-Safe Defaults?

[Ok] [Cancel]

appears in the window. Select Ok to load Fail-Safe defaults.

# 9 BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMIBIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a "POST Card" or "POST Diagnostic Card". These are ISA or PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMIBIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMIBIOS checkpoints.

![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2001 American Megatrends, Inc.\nBIOS Date: 10/01/01 12:39:39 Ver: 08.00.03\nPentium (R) III Processor, 933MHz\nPress DEL to run Setup\nChecking NURAM..\nCheckpoint Display\nEVALUATION COPY, NOT FOR SALE\n(C) American Megatrends Inc.,\n63-0100-000001-00101111-100101-015-0AAXT004-Y2KC\n6B3B](.31-en/fc81513f558b74fd79a5878523ec8e0493c29732ddef7bb1dd8da662eb3f23a1.jpg)

# 9.1 Bootblock Initialization Code Checkpoints

The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS:

![The image displays a document icon featuring a white page with a folded top-right corner and faint horizontal lines. A large red checkmark crosses over the center of the page. Below the icon, the text 'NOTE:' appears in black capital letters.](.31-en/97942125dd40aadb66d7e5afd298d9ea0387dd162b82e245e76d923fffff187b.jpg)

Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

<table><tr><td>Checkpoint</td><td>Description</td></tr><tr><td>Before D0</td><td>If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this point. Stack will be enabled from this point.</td></tr><tr><td>D0</td><td>Early Boot Strap Processor (BSP) initialization like microcode update, frequency and other CPU critical initialization. Early chipset initialization is done.</td></tr><tr><td>D1</td><td>Early super I/O initialization is done including RTC and keyboard controller. Serial port is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled.</td></tr><tr><td>D2</td><td>Verify the boot block checksum. System will hang here if checksum is bad.</td></tr><tr><td>D3</td><td>Disable CACHE before memory detection. Execute full memory sizing module. If memory sizing module not executed, start memory refresh and do memory sizing in Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.</td></tr><tr><td>D4</td><td>Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.</td></tr><tr><td>D5</td><td>Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly.</td></tr><tr><td>D6</td><td>Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.</td></tr><tr><td>D7</td><td>Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.</td></tr><tr><td>D8</td><td>The Runtime module is uncompressed into memory. CPUID information is stored in memory.</td></tr><tr><td>D9</td><td>Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.</td></tr><tr><td>DA</td><td>Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.</td></tr><tr><td>DC</td><td>System is waking from ACPI S3 state</td></tr><tr><td>E1-E8, EC-EE</td><td>OEM memory detection/configuration error. This range is reserved for chipset vendors &amp; system manufacturers. The error associated with this value may be different from one platform to the next.</td></tr></table>

# 9.2 Bootblock Recovery Code Checkpoints

The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS:

![The image displays a white document icon with a folded top corner, featuring a large red checkmark in the center. Below the graphic, the text 'NOTE:' is written in bold, black capital letters.](.31-en/fc747174e44efc89ea4d5d984351846b94a78229fb5dd344a3492b67fcccfbcc.jpg)

Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.

<table><tr><td>Checkpoint</td><td>Description</td></tr><tr><td>E0</td><td>Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.</td></tr><tr><td>E9</td><td>Set up floppy controller and data. Attempt to read from floppy.</td></tr><tr><td>EA</td><td>Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.</td></tr><tr><td>EB</td><td>Disable ATAPI hardware. Jump back to checkpoint E9.</td></tr><tr><td>EF</td><td>Read error occurred on media. Jump back to checkpoint EB.</td></tr><tr><td>F0</td><td>Search for pre-defined recovery file name in root directory.</td></tr><tr><td>F1</td><td>Recovery file not found.</td></tr><tr><td>F2</td><td>Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.</td></tr><tr><td>F3</td><td>Start reading the recovery file cluster by cluster.</td></tr><tr><td>F5</td><td>Disable L1 cache.</td></tr><tr><td>FA</td><td>Check the validity of the recovery file configuration to the current configuration of the flash part.</td></tr><tr><td>FB</td><td>Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.</td></tr><tr><td>F4</td><td>The recovery file size does not equal the found flash part size.</td></tr><tr><td>FC</td><td>Erase the flash part.</td></tr><tr><td>FD</td><td>Program the flash part.</td></tr><tr><td>FF</td><td>The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.</td></tr></table>

# 9.3 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS preboot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS:

![The image displays a digital icon featuring a white document shape with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed over the left side of the document. Below the document graphic, the text 'NOTE:' is written in black capital letters.](.31-en/e653948da115efb8d39ae95a3c0a0853f6f3ef5c3e81174fce86d94251525ed4.jpg)

Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs From add-in PCI devices.

<table><tr><td>Checkpoint</td><td>Description</td></tr><tr><td>03</td><td>Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable &quot;wCMOSFlags.&quot;</td></tr><tr><td>04</td><td>Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system</td></tr><tr><td>05</td><td>Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.</td></tr><tr><td>06</td><td>Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to &quot;POSTINT1ChHandlerBlock.&quot;</td></tr><tr><td>07</td><td>Fixes CPU POST interface calling pointer.</td></tr><tr><td>08</td><td>Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.</td></tr><tr><td>C0</td><td>Early CPU Init Start -- Disable Cache - Init Local APIC</td></tr><tr><td>C1</td><td>Set up boot strap processor Information</td></tr><tr><td>C2</td><td>Set up boot strap processor for POST</td></tr><tr><td>C5</td><td>Enumerate and set up application processors</td></tr><tr><td>C6</td><td>Re-enable cache for boot strap processor</td></tr><tr><td>C7</td><td>Early CPU Init Exit</td></tr><tr><td>0A</td><td>Initializes the 8042 compatible Key Board Controller.</td></tr><tr><td>0B</td><td>Detects the presence of PS/2 mouse.</td></tr><tr><td>0C</td><td>Detects the presence of Keyboard in KBC port.</td></tr><tr><td>0E</td><td>Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.</td></tr><tr><td>13</td><td>Early POST initialization of chipset registers.</td></tr><tr><td>20</td><td>Relocate System Management Interrupt vector for all CPU in the system.</td></tr><tr><td>24</td><td>Uncompress and initialize any platform specific BIOS modules. GPNV is initialized at this checkpoint.</td></tr><tr><td>2A</td><td>Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information.</td></tr><tr><td>2C</td><td>Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.</td></tr><tr><td>2E</td><td>Initializes all the output devices.</td></tr></table>

POST Code Checkpoints cont'd:

<table><tr><td>Checkpoint</td><td>Description</td></tr><tr><td>31</td><td>Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.</td></tr><tr><td>33</td><td>Initializes the silent boot module. Set the window for displaying text information.</td></tr><tr><td>37</td><td>Displaying sign-on message, CPU information, setup key message, and any OEM specific information.</td></tr><tr><td>38</td><td>Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point.</td></tr><tr><td>39</td><td>Initializes DMAC-1 &amp; DMAC-2.</td></tr><tr><td>3A</td><td>Initialize RTC date/time.</td></tr><tr><td>3B</td><td>Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system.</td></tr><tr><td>3C</td><td>Mid POST initialization of chipset registers.</td></tr><tr><td>40</td><td>Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, ... etc.) successfully installed in the system and update the BDA, EBDA...etc.</td></tr><tr><td>52</td><td>Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.</td></tr><tr><td>60</td><td>Initializes NUM-LOCK status and programs the KBD typematic rate.</td></tr><tr><td>75</td><td>Initialize Int-13 and prepare for IPL detection.</td></tr><tr><td>78</td><td>Initializes IPL devices controlled by BIOS and option ROMs.</td></tr><tr><td>7C</td><td>Generate and write contents of ESCD in NVRam.</td></tr><tr><td>84</td><td>Log errors encountered during POST.</td></tr><tr><td>85</td><td>Display errors to the user and gets the user response for error.</td></tr><tr><td>87</td><td>Execute BIOS setup if needed / requested. Check boot password if installed.</td></tr><tr><td>8C</td><td>Late POST initialization of chipset registers.</td></tr><tr><td>8D</td><td>Build ACPI tables (if ACPI is supported)</td></tr><tr><td>8E</td><td>Program the peripheral parameters. Enable/Disable NMI as selected</td></tr><tr><td>90</td><td>Initialization of system management interrupt by invoking all handlers. Please note this checkpoint comes right after checkpoint 20h</td></tr><tr><td>A1</td><td>Clean-up work needed before booting to OS.</td></tr><tr><td>A2</td><td>Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.</td></tr><tr><td>A4</td><td>Initialize runtime language module. Display boot option popup menu.</td></tr><tr><td>A7</td><td>Displays the system configuration screen if enabled. Initialize the CPU&#x27;s before boot, which includes the programming of the MTRR&#x27;s.</td></tr><tr><td>A9</td><td>Wait for user input at config display if needed.</td></tr><tr><td>AA</td><td>Uninstall POST INT1Ch vector and INT09h vector.</td></tr><tr><td>AB</td><td>Prepare BBS for Int 19 boot. Init MP tables.</td></tr><tr><td>AC</td><td>End of POST initialization of chipset registers. De-initializes the ADM module.</td></tr><tr><td>B1</td><td>Save system context for ACPI. Prepare CPU for OS boot including final MTRR values.</td></tr><tr><td>00</td><td>Passes control to OS Loader (typically INT19h).</td></tr></table>

# 9.4 OEM POST Error Checkpoints

Checkpoints from the range 61h to 70h are reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next.

# 9.5 DIM Code Checkpoints

The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed:

![The image displays a white document icon with a large red checkmark. Below the document is the text 'NOTE:' in black capital letters.](.31-en/2e4b11e9334a525965416b9e5f4329af0a671c0b378089a42e2eeddb8f1d96f8.jpg)

Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

<table><tr><td>Checkpoint</td><td>Description</td></tr><tr><td>2A</td><td>Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI- PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.</td></tr><tr><td>38</td><td>Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.</td></tr></table>

While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows:

# HIGH BYTE XY

The upper nibble 'X' indicates the function number that is being executed. 'X' can be from 0 to 7.

0 = func#0, disable all devices on the BUS concerned.
1 = func#1, static devices initialization on the BUS concerned.
2 = func#2, output device initialization on the BUS concerned.
3 = func#3, input device initialization on the BUS concerned.
4 = func#4, IPL device initialization on the BUS concerned.
5 = func#5, general device initialization on the BUS concerned.
6 = func#6, error reporting for the BUS concerned.
7 = func#7, add-on ROM initialization for all BUSes.
8 = func#8, BBS ROM initialization for all BUSes.

The lower nibble 'Y' indicates the BUS on which the different routines are being executed. 'Y' can be from 0 to 5.

0 = Generic DIM (Device Initialization Manager).

1 = Onboard System devices.

2 = ISA devices.

3 = EISA devices.

4 = ISA PnP devices.

5 = PCI devices.

# 9.6 ACPI Runtime Checkpoints

ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events:

![The image displays a white document icon with a folded top-right corner. A large red checkmark with a gradient shading is placed centrally on the document. Below the icon, the text 'NOTE:' is written in black, capital letters.](.31-en/3830650f460c4c3c274a470e3984271327b608e50200521ce20a4a3ff1602695.jpg)

Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices.

# 9.7 Boot Block Beep Codes

<table><tr><td>No. of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Insert diskette in floppy drive A:</td></tr><tr><td>2</td><td>‘AMIBOOT.ROM’ file not found in root directory of diskette in A:</td></tr><tr><td>3</td><td>Base Memory error</td></tr><tr><td>4</td><td>Flash Programming successful</td></tr><tr><td>5</td><td>Floppy read error</td></tr><tr><td>6</td><td>Keyboard controller BAT command failed</td></tr><tr><td>7</td><td>No Flash EPROM detected</td></tr><tr><td>8</td><td>Floppy controller failure</td></tr><tr><td>9</td><td>Boot Block BIOS checksum error</td></tr><tr><td>10</td><td>Flash Erase error</td></tr><tr><td>11</td><td>Flash Program error</td></tr><tr><td>12</td><td>‘AMIBOOT.ROM’ file size error</td></tr><tr><td>13</td><td>BIOS ROM image mismatch (file layout does not match image present in flash device)</td></tr></table>

# 9.8 POST BIOS Beep Codes

<table><tr><td>No. of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory refresh timer error.</td></tr><tr><td>2</td><td>Parity error in base memory (first 64KB block)</td></tr><tr><td>3</td><td>Base memory read/write test error</td></tr><tr><td>4</td><td>Motherboard timer not operational</td></tr><tr><td>5</td><td>Processor error</td></tr><tr><td>6</td><td>8042 Gate A20 test error (cannot switch to protected mode)</td></tr><tr><td>7</td><td>General exception error (processor exception interrupt error)</td></tr><tr><td>8</td><td>Display memory error (system video adapter)</td></tr><tr><td>9</td><td>AMIBIOS ROM checksum error</td></tr><tr><td>10</td><td>CMOS shutdown register read/write error</td></tr><tr><td>11</td><td>Cache memory test failed</td></tr></table>

# 9.9 Troubleshooting POST BIOS Beep Codes

<table><tr><td>No. of Beeps</td><td>Description</td></tr><tr><td>1, 2 or 3</td><td>Reseat the memory, or replace with known good modules.</td></tr><tr><td>4-7, 9-11</td><td>Fatal error indicating a serious problem with the system. Consult your system manufacturer.Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card. Remove all expansion cards except the video adapter.- If beep codes are generated when all other expansion cards are absent, consult your system manufacturer&#x27;s technical support.- If beep codes are not generated when all other expansion cards are absent, one of the add-in cards is causing the malfunction. Insert the cards back into the system one at a time until the problem happens again. This will reveal the malfunctioning card.</td></tr><tr><td>8</td><td>If the system video adapter is an add-in card, replace or reseat the video adapter. If the video adapter is an integrated part of the system board, the board may be faulty.</td></tr></table>

# Appendix A: Heatspreaders and Heatsinks

# A.1 Carrier Board ETX connector heights (Hirose FX8/FX8C Receptacles)

For different stacking heights, the receptacles for ETX carrier boards are available in two heights, 3 mm and 9.5 mm. When 3 mm receptacles are chosen, the carrier board should be free of components.

# FX8-100S-SV

100-pin board-to-board connector for

3 mm board stacking

This connector can be used with :

\- 3 mm through-hole standoffs (SMT type)

\- 3 mm threaded standoffs (DIP type)

![3D rendering of a metallic connector with multiple pins and a rectangular body (no text or symbols visible)](.31-en/11f42644011a107fd9092483ea5a9821a5726572f6196bf2586de6a255036db0.jpg)

# FX8C-100S-SV5

100-pin board-to-board connector for

9.5 mm board stacking

This connector can be used with :

\- 9.5 mm through-hole standoffs (SMT type)

\- 9.5 mm threaded standoffs (DIP type)

![3D rendering of a rectangular electronic component with internal fins and threaded edges (no text or symbols)](.31-en/ac8818eefd078d677b4d8bc467c38b669a7a7f3e2e63b1705d376e5d089a8eaa.jpg)

# FX8C/FX8 Common Spec

▶ Current capacity 0.4 A per pin
▶ Rated voltage 100 V AC
▶ Insulation resistance 100 M or greater @ 250 V DC
▶ Withstand voltage 300 V AC r.m.s.
▶ Contact resistance 45 m or less @ 100 mA DC
▶ Insulation PPS resin (Light brown, UL94V-0)
Contacts phosphor bronze (gold plated contacts and leads)

# A.2 Heatspreader Introduction

The function of the heatspreader is to ensure an identical mechanical profile for every ETX module. In this way the thermal solution, that is built on top of the heatspreader is compatible with any ETX module, not just the ETX-NR667.

![Close-up of a finger pressing a metallic component on a workbench, with no visible text or symbols.](.31-en/38572f1c34d093dc4bfc96f34e6476d61f3d7e16145804e54f16d0e96bdab256.jpg)

![Close-up of a hand holding a small blue and purple plastic component on a white surface, with a small metallic object nearby (no text or symbols visible)](.31-en/2beaaca7a5f72d88830a269df704a5f747fb92ac7c9dada11d406f68e0701f0f.jpg)

Remove the protective layer from CPU, Northbridge, and Southbridge pads before placing the heatspreader on the module.

![Metallic electronic component with multiple square and L-shaped cutouts, mounted on a base plate (no visible text or symbols)](.31-en/d8471cb5ed2772f9d789ad7b4344e45ff1b01b3eb9c215460031f10dc93ddb88.jpg)

Heatpads for BGA type CPU, Northbridge and Southbridge. The cutout area allows clearance for memory and SATA connectors.

![Exterior view of a silver computer drive chassis (no visible text or labels)](.31-en/f901435460e3afbd1ffc2888026cc3b0c7fb7aacbb20e526679d5ee7b564481e.jpg)

Heatspreader placed on ETX-NR667.

![Close-up of a layered material sample with a dark rectangular substrate and a lighter gray layer, placed on a blue surface (no text or symbols visible)](.31-en/c83720aaa9f42c0e7fa4c2eb4d914c24872fef1b77f767a7cba6b0966f3f800a.jpg)

Heatpads for CPU & North Bridge (from top to bottom):
![Close-up of a blue and purple textured block on a metallic surface, with no visible text or symbols.](.31-en/ffc44afa2e8dd36a9d53a9c82c71ccb0d3b9cb2b51b4ae60e4ac305edd99166a.jpg)

Heatpads for South Bridge (from top to bottom):

- Protective layer (blue)
- Flexible heat pad (purple)
- Aluminum heatspreader plate (silver)

- Face change (grey)
- Aluminum pad (silver)
- Flexible heat pad (purple)
- Aluminum heatspreader plate (silver)

# A.3 Mounting procedures

There are several standard ways to mount an ETX board with heatspreader on a carrier board. ETX boards may be mounted with 9 mm ETX connectors on the carrier board or standard 3 mm connectors. There are also two different types of heatspreaders to choose from: heatspreaders with threaded standoffs which require inserting screws from under the carrier, or top mounting heatspreaders using through-hole heatspreader standoffs and threaded carrier board standoffs.

Top Mounting
3 mm Hirose FX8-100S-SV
Carrier Board Connectors
![M2.5 : 14 mm\nwith spring / washer\n6 mm through-hole\nstandoffs\nHeatspreader\nETX Module\n3 mm threaded\nstandoff (DIP)\nCarrier](.31-en/c132f36a85fbe9218fc6dcf0950c39c95664a50d6b9d63eb887c983f9b1988e7.jpg)

Bottom Mounting
3 mm Hirose FX8-100S-SV
Carrier Board Connectors
![Heatspreader\n6 mm threaded\nstandoffs\nETX Module\n3 mm through-hole\nstandoff (SMT)\nCarrier\nM2.5 : 12 mm\nwith spring / washer](.31-en/0581d8004cd174e81f8f0a12cb892da0a373c66bffae15ccbc1b790ffd8a7616.jpg)

Top Mounting
9 mm Hirose FX8C-100S-SV5
Carrier Board Connectors
![M2.5 : 14 mm\nwith spring / washer\n6 mm through-hole\nstandoffs\nHeatspreader\nETX Module\n9.5 mm threaded\nstandoff (DIP)\nCarrier](.31-en/15537bee1db785fb26ee346162fec379e83108bf01b01c5c0bfd8579f398c226.jpg)

Bottom Mounting
9 mm Hirose FX8C-100S-SV5
Carrier Board Connectors
![Heatspreader\n6 mm threaded\nstandoffs\nETX Module\n9.5 mm through-hole\nstandoff (SMT)\nCarrier\nM2.5 : 16 mm\nwith spring / washer](.31-en/1edc361872292a498376b9a481b8fe5b8765cd6436f0d5b6fcf33646a928a67f.jpg)

# A.4 Standoff types

For different mounting procedures there are different, readily available standoffs. Note that threaded standoffs are both DIP and SMT type and the through-hole types are all SMT type. Other types not listed can be made available upon request.

<table><tr><td>33-72000-0030&lt;img src="images/3a8c9fdb01f813d32b0432d614d97eb42e5f30ce4f02aabcc03c21942a8c4c10.jpg"/&gt;</td><td>3 mm through-hole standoff (SMT type)for HTS-NR667-B with 3 mm Hirose carrier board connectors</td></tr><tr><td>33-72011-0030&lt;img src="images/e44beaba292404b0b58b11eb0d6a27d01b135b386741d3b98a5054d14cdc9bf4.jpg"/&gt;</td><td>3 mm threaded standoff (DIP type)for HTS-NR667-BT with 3 mm Hirose carrier board connectors</td></tr><tr><td>33-72007-9P50&lt;img src="images/189663b5930164449c13c800fca3eec4c414fdb1b45ddcb28d7dec472385026e.jpg"/&gt;</td><td>9.5 mm through-hole standoff (SMT type)for HTS-NR667-BT with 9 mm Hirose carrier board connectors</td></tr><tr><td>33-72011-9P50&lt;img src="images/994afa24e93226fa49599efbf76af459c2554d8866b3059360836d0b738487fb.jpg"/&gt;</td><td>9.5 mm threaded standoff (DIP type)for HTS-NR667-B with 9 mm Hirose carrier board connectors</td></tr></table>

# A.5 Heatspreader Dimensions for HTS-NR667-B (threaded standoffs)

![The image displays a graphic icon featuring a white document with a folded top-right corner and faint horizontal lines representing text. A large red checkmark is superimposed over the center of the document. Below the icon, the text 'NOTE:' is written in black, capital letters.](.31-en/2a63714f7bf78f39e8be2f05cc96632306b81db5823a0ae0594546fb80e59ce1.jpg)

Only for BGA type LV and ULV PU's below 15 watts.

![1.15\n2.2\n36.50\nB\n35\n5-M2.5x8L Standoff\nA\nC\n44.7\n10.00\nR2\nR3\nA\n64.00\n25.00\n78\n40\nA\n3.5\n3.5\n14.00\n4.50\n73\nB\n87](.31-en/f5d6f40d0ad009bf5ba80cf1522c84ac9147969b43fcd99d71312cb48474e2a7.jpg)

The heatspreader comes with four M2.5 at 12 mm with washer/spacer.

# A.6 Heatspreader Dimensions for HTS-NR667-BT (through-hole standoffs)

![The image displays a white document icon with a folded top-right corner. A large red checkmark is centered on the paper, which has faint horizontal lines. Below the document, the text 'NOTE:' appears in black capital letters.](.31-en/a41c675c88e3df4b21575e2a5d5be85bfeec3a324d615395d4c0329d7208ddb4.jpg)

Only for BGA type LV and ULV PU's below 15 watts.

![1.15\n2.20\n36.50\nB\n35.00\nA\nM2.5X8L Standoff\n14.50\nR2.00\nR2.00\n51.70\n44.70\nC\n3.50\n10.00\n64.00\n25.00\n40.00\n78.00\nC\nA\nA\n4.50\nB\n3.50\n14.00\n73.00\n87.00\n4X-Ø2.8 Through](.31-en/f89192f1724d66aab1adc78fc7622553558f8cecb9f1f820a41691b4fbfc7e76.jpg)

The heatspreader comes with four M2.5 14mm screws with washer/spacer. If using 9.5 mm standoffs on the carrier board, M2.5 18mm screws with washer/spring are required and must be ordered separately.

# A.7 THSF-NR667 Series: High Performance Heatsink with Fan

The THSF-NR667-B (BGA, soldered type CPU) is a high performance heatsink that can easily support CPU types with thermal outputs of up to 35 watts. The fan on the heatsink requires a 12V power source.

![Close-up of a heat exchanger cooling unit with copper heat sinks and a fan (no visible text or symbols)](.31-en/5b8077ab057989e0c0446f808e4cbacdacf91e734f4c32e5fc4680aa484be2e1.jpg)

Aluminum body, with copper CPU head and 12V high performance fan

![Computer motherboard with CPU socket, RAM slots, and heatsink (no visible text or labels)](.31-en/111769e84938196bade2499b84d1ad912d92c8ea18a88b810788fd779485c616.jpg)

THSF-NR667-B installed on ETX-NR667 and ETX-carrier board.

# A.8 THS-NR667 Series: Low Profile Heatsinks

The THS-NR667 Heatsink Series (for BGA type CPUs only) are low profile heatsinks that are optimized for reduced height applications. Although the heatsinks are fanless, they still require some airflow to efficiently cool applications. The heatsinks are available in two cooling fin orientations and have both top and bottom mounting options (threaded vs through-hole standoffs).

![Two views of a green circuit board: one showing internal components, the other showing a metallic heating element (no text or symbols visible)](.31-en/faa6277facc72b945f1debbb8b02e9279978c3365d591826266ddf2cd93b71f5.jpg)

THSF-NR667-BL heatsink with ETX-NR667

![Four square patterned fabric swatches arranged on a white rectangular base, no text or symbols visible.](.31-en/390dec3f10b6cb531f7143cea1f6198b150943fe09ac4b1a7e7b2c0d1ec3674a.jpg)

Pads for CPU, Northbridge, and Southbridge

![Exterior view of a flat electronic device with a metallic heat sink and green circuit board (no text or symbols visible)](.31-en/9693a3f3e841934e6aab33163fcd990b0707f0af4676f708f3d35dac40d510af.jpg)

Heatsink mounted on ETX-NR667

![The image displays a digital icon featuring a white document with faint horizontal lines, overlaid with a large red checkmark. Beneath the document graphic, the text 'NOTE:' is written in black capital letters.](.31-en/ebe549e0f1d7ab7d55aa7a86325cb8aa37f06210b109a203cec672490a5c4d32.jpg)

Only for BGA- type CPU's below 22 watts.

# A.9 Dimensions for THS-NR667 Series

THS-NR667-BL

Heatsink with long fins and threaded standoffs for bottom mounting
![Ø4.0 / M2.5\nx6 pcs\n114.0\n108.0\n26.4\n45.9\n21.5\n95.0\n90.0\n2.5\n3.0\n4.0\n3.0\n4.0\n7.0\n2.5\n2.0\n2.0\nM2.5 H6 standoffs x6\n3.7](.31-en/57ecc8a5e55f546e6e953968649af8e075c9a26bc9f6539e9c93d360826f0adf.jpg)

# THS-NR667-BTL

Heatsink with long fins and and through-hole standoffs for top mounting
![Ø4.0 / Ø2.5\nx4 pcs\n114.0\n26.4\n108.0\n45.9\n21.5\n95.0\n90.0\n2.5\n3.0\n4.0\n3.0\n4.0\n7.0\n2.5\n2.0\n2.0\n8.0\n3.7\nThroughhole standoffs x4\nØ4.0 external\nØ2.5 internal\nM2.5 H6\nstandoffs x2](.31-en/01ff4620041b536d1b07a2379701381c8933457b372dfb3440caeffab82c34cf.jpg)

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# Important Safety Instructions

For user safety, please read and follow all instructions, warnings, cautions, and notes marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.
- Keep this user's manual for future reference.
Read the specifications section of this manual for detailed information on the operating environment of this equipment.
When installing/mounting or uninstalling/removing equipment:

\- Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

- Keep equipment away from water or liquid sources;
- Keep equipment away from high heat or high humidity;
- Keep equipment properly ventilated (do not block or cover ventilation openings);
- Make sure to use recommended voltage and power source settings;
- Always install and operate equipment near an easily accessible electrical socket-outlet;
- Secure the power cord (do not place any object on/over the power cord);
- Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
- If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
▶ A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard yellow warning triangle with a black border. Inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION:' is printed in black capital letters.](.31-en/83ccd3dbb4d271f9ebe1b3e409d7f8d35018e2ab14e99fffa8d5f610bf3a8fd1.jpg)

Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries according to the instructions.

▶ Equipment must be serviced by authorized technicians when:

- The power cord or plug is damaged;
- Liquid has penetrated the equipment;
- It has been exposed to high humidity/moisture;
- It is not functioning or does not function according to the user's manual;
- It has been dropped and/or damaged; and/or,
- It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)

300 Fang Chun Rd., Zhangjiang Hi-Tech Park,

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)

Rm. 801, Power Creative E, No. 1, B/D

Shang Di East Rd., Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8625

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园

A1 栋 2 楼 C 区 (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,

High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

Tel: +49-211-495-5552

Fax: +49-211-495-5557

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

神田 374 ビル 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 서울시 서초구 서초동 1675-12 모인터빌딩 8 층

8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu,

Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre,

Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza,

Margosa Main Road, Malleswaram, Bangalore-560055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 6 Hasadna St., Kfar Saba 44424, Israel

Tel: +972-9-7446541

Fax: +972-9-7446542

Email: israel@adlinktech.com

![The image displays the standard recycling symbol, often called the Mobius loop. It features a black circular background containing three white arrows arranged in a continuous triangular formation. The arrows are bent and point in a clockwise direction, with each arrow consisting of a pointed head and a tail section composed of three parallel stripes.](.31-en/ca55158e0d6f01df261433a2718183ec02c6e3fedfce7290bfeafc7f68722d62.jpg)
[🔗 Link to the original document](.31-en/31-en.pdf)