# LittleBoard™ 735

# Single Board Computer

# Reference Manual

P/N 50-1Z020-1020

# DISCLAIMER

ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages. ADLINK reserves the right to revise this publication from time to time without obligation to notify any person of such revisions. If errors are found, please contact ADLINK at the address shown at the bottom of this notice.

# TRADEMARKS

CoreModule and the Ampro logo are registered trademarks, and ADLINK, Little Board, LittleBoard, MightyBoard, MightySystem, MilSystem, MiniModule, ReadyBoard, ReadyBox, ReadyPanel, ReadySystem, and RuffSystem are trademarks of ADLINK Technology, Inc. All other marks are the property of their respective companies.

REVISION HISTORY

<table><tr><td>Revision</td><td>Reason for Change</td><td>Date</td></tr><tr><td>00</td><td>Initial Release</td><td>April/09</td></tr><tr><td>2.0</td><td>Revised PCI-to-ISA section in ch 4; revised +5V to be default JP5 setting in Table 2-3; revised environmental specifications in Table 2-5; added Table 2-7 for cooling solutions; revised Appendix A</td><td>April/10</td></tr><tr><td>1010</td><td>Replaced EOL Ethernet chip; revised locations of components and connectors; added active heatsink</td><td>Nov/10</td></tr><tr><td>1020</td><td>Added J47 and J48 LAN LED headers (replaced fast RJ-45 with Gigabit RJ-45 in rev 1010); re-defined pins 1 and 3 in Table 3-13; changed Serial Console to Remote Access in Ch 3 &amp; 4; revised function definitions in Table 2-1; changed description of J3 in Table 2-2; added fan voltage caution to Ch 3; revised BIOS Setup procedures in Ch 4; added BIOS Setup Utility section to Ch 4; updated index</td><td>May/12</td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td></tr></table>

ADLINK Technology, Incorporated

5215 Hellyer Avenue, #110

San Jose, CA 95138-1007

Tel. 408 360-0200

Fax 408 360-0222

www.adlinktech.com

© Copyright 2009, 2010, 2011, 2012 ADLINK Technology, Incorporated

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Contents

# Chapter 1 About This Manual ..

Purpose of this Manual ..

References ..

# Chapter 2 Product Overview...........

EBX Architecture... .3

Product Description.. .4

Board Features . .5

Block Diagram . .7

Major Components (ICs).. ..8

Headers and Connectors ........ ..12

Jumper Header Definitions . ..15

Specifications......... ....17

Physical Specifications ..... ..17

Mechanical Specifications .. ..17

Environmental Specifications ...18

Power Specifications ...18

Thermal/Cooling Requirements ..... ..19

# Chapter 3 Hardware . .21

Overview .. ..21

Interrupt Channel Assignments . .22

Memory Map .. ..23

I/O Address Map . ..23

Floppy Drive Interface .. ..24

Parallel Port Interface ..25

Serial Interfaces ..26

Utility Interfaces ..29

Utility 1 Interface ..30

Keyboard ..30

External Battery ....... ...30

Power-On LED ...30

Reset Switch .... ...30

Speaker ..30

Utility 2 Interface ..31

System Management Bus (SMBus) ..31

Mouse ..... ...31

Power Button. ..31

USB Interfaces ...... ..32

USB 2.0 Support. .32

Legacy USB Support .32

USB0 and USB1 .33

USB2 and USB3. ..33

USB4 and USB5 ..34

Audio Interface... ..34

Video Interfaces ..35

VGA Interface ..36

LVDS Interface ..36

TV-Out Interface ..37

Power Interfaces . 38

Power-In Interface . . 38

ATX Power-On Interface . 38

Power Button and Reset Switch Interface . 38

Miscellaneous . .. 39

Real Time Clock (RTC) . 39

Temperature Monitoring . 39

User GPIO Signals . 39

SMBus Interface . . 40

Oops! Jumper (BIOS Recovery) . 40

Remote Access . . 40

Remote Access Setup ...... .... 41

Hot (Serial) Cable . 41

Watchdog Timer ....... . 41

Optional CPU Fan . 42

GLAN1 LED . 42

GLAN2 LED . . 42

Battery Input . . 43

Chapter 4 BIOS Setup ..... . 45

Introduction.. . 45

Entering BIOS Setup (Local Video Display).. .. 45

Entering BIOS Setup (Remote Access) . 45

PCI-to-ISA Bridge Mapping . 46

Logo Screen Utility (Splash Screen) . . 46

Logo Screen Image Requirements . . 46

BIOS Setup Menus.. . 47

BIOS Main Setup Screen . 47

BIOS Advanced Setup Screen . 48

BIOS PCIPnP Setup Screen . 54

BIOS Boot Setup Screen . 55

BIOS Security Setup Screen . 57

BIOS Chipset Setup Screen ...... . 58

BIOS Exit Setup Screen . 59

Appendix A Technical Support .. . 61

Index ... . 63

# List of Figures

Figure 2-1. Stacking PC/104 Modules with the LittleBoard 735 . 4

Figure 2-2. Functional Block Diagram .

Figure 2-3. Component Locations (Top Side).. . 10

Figure 2-4. Component Locations (Bottom Side) .. . 11

Figure 2-5. Pin Sequence Identification.. . 13

Figure 2-6. Connector Locations (Top Side).. . 14

Figure 2-7. Jumper Header Locations (Top Side) . .. 16

Figure 2-8. LittleBoard 735 Dimensions . . 17

Figure 3-1. RS485 Serial Port Implementation .. . 26

Figure 3-2. Oops! Jumper Connection............. ..... 40

Figure 3-3. Hot Cable Jumper . . 41

Figure 4-1. BIOS Main Setup Screen ......... .... 47

Figure 4-2. BIOS Advanced Setup Screen.. ...48

Figure 4-3. BIOS PCIPnP Setup Screen.. ..54

Figure 4-4. BIOS Boot Setup Screen .. ..55

Figure 4-5. BIOS Security Setup Screen.. ..57

Figure 4-6. BIOS Chipset Setup Screen ........ ...58

Figure 4-7. BIOS Exit Setup Screen.. ..59

# List of Tables

Table 2-1. Major Integrated Circuit Descriptions and Functions ..... .8

Table 2-2. Header and Connector Descriptions.. ..12

Table 2-3. Jumper Settings ......... ....15

Table 2-4. Weight and Footprint Dimensions.. ..17

Table 2-5. Environmental Requirements.. ...18

Table 2-6. Power Supply Requirements . ...18

Table 2-7. ADLINK Optional Cooling Solutions....... ....19

Table 3-1. Interrupt Channel Assignments...... ..22

Table 3-2. Memory Map .... .23

Table 3-3. I/O Address Map ........ ..23

Table 3-4. Parallel Interface Pin Signals (J16)... ..25

Table 3-5. Serial A Interface Pin Signals (J11) .. .27

Table 3-6. Serial B Interface Pin Signals (J12) .. .28

Table 3-7. Utility 1 Interface Pin Signals (J15) ... ..30

Table 3-8. SMBus Reserved Addresses ...... ..31

Table 3-9. Utility 2 Interface Pin Signals (J13) .. ..31

Table 3-10. USB 0 & 1 Interface Pin Signals (J44) .. ..33

Table 3-11. USB 2 & 3 Interface Pin Signals (J14) .. ..33

Table 3-12. USB 4 & 5 Interface Pin Signals (J39) .. .34

Table 3-13. Audio Interface Pin Signals (J9)... ..34

Table 3-14. VGA Interface Pin Signals (J3) .. ..36

Table 3-15. LVDS Interface Pin Signals (J26) . .36

Table 3-16. TV-Out Pin Signals (J36) ..... ..37

Table 3-17. Power-In Interface Pin Signals (J19) ..... ...38

Table 3-18. ATX Power-On Interface Pin Signals (J30).. ..38

Table 3-19. Power Button Interface Pin Signals (J46) . .38

Table 3-20. User GPIO Pin Signals (J40) . ...39

Table 3-21. SMBus Pin Signals (J45) .. ..40

Table 3-22. Optional CPU Fan (J34) . .42

Table 3-23. Ethernet External LED Pin Signal Descriptions (J47) .. ...42

Table 3-24. Ethernet External LED Pin Signal Descriptions (J48) . ..42

Table 3-25. External Battery Input Header (J35) ...43

Table 4-1. BIOS Setup Menus ... ..47

Table A-1. Technical Support Contact Information........ ....61

# Purpose of this Manual

This manual is for designers of systems based on the LittleBoard™ 735 single board computer (SBC). This manual contains information that permits designers to create an embedded system based on specific design requirements.

Information provided in this reference manual includes:

• LittleBoard 735 specifications
Environmental requirements
Major integrated circuits (chips) and features implemented
• LittleBoard 735 connector/pin numbers and definitions
• BIOS Setup information

Information not provided in this reference manual includes:

• Detailed chip specifications
• Internal component operation
Standard connector pin-out tables
Internal registers or signal operations
Bus or signal timing for industry standard busses and signals

# References

The following list of references may be helpful for you to complete your design successfully.

# Specifications:

EBX Spec Revision 2.0, March 1, 2005
For the latest version of the EBX specifications, contact the PC/104 Consortium, at:
Web site: http://www.pc104.org
PCI Express Mini Card Spec Revision 1.0
For latest revision of the PCI Express Mini Card specifications, contact the PCI Special Interest Group Office, at:
Web site: http://www.pcisig.com/specifications/pciexpress/mini
• PC/104 Spec Revision 2.5, November 2003
PC/104-Plus Spec Revision 2, November 2003
For latest revision of the PC/104 specifications, contact the PC/104 Consortium, at:
Web site: http://www.pc104.org
• PCI 2.2 Compliant Specifications
For latest revision of the PCI specifications, contact the PCI Special Interest Group Office at:
Web site: http://www.pcisig.com

• AMI BIOS Core 8 User’s Guide

Web site: http://www.ami.com/support/doc/MAN-EZP-80.pdf

Chip specifications used on the LittleBoard 735:

• Intel Corporation and the Atom N270 processor used for the embedded CPU.

Web site: http://download.intel.com/design/processor/datashts/320032.pdf

Intel Corporation and the 82945GSE and 82801GBM chips, used for the Memory Hub/Video controller and I/O Hub, respectively.

Web site: http://download.intel.com/design/processor/datashts/309219.pdf = Memory Hub

Web site: http://www.intel.com/Assets/PDF/datasheet/307013.pdf = I/O Hub

Intel Corporation and the 82574IT chips (2), used for the Gigabit Ethernet controllers, respectively.

Web site: http://download.intel.com/design/network/datashts/82574.pdf = Gigabit Ethernet

Standard Microsystems Corp and the SCH3114I-NU chip, used for the Super I/O controller.

Web site: http://www.smsc.com/main/catalog/sch311x.html

• Realtek and the ALC203 chip, used for the Audio CODEC.

Web site: http://www.realtek.com.tw/search/default.aspx?keyword=ALC203

ITE Tech. Inc. and the IT8888F chip, used for the PCI-to-ISA bridge conversion.

Web site: http://www.ite.com.tw/EN/products\_more.aspx?CategoryID=3&ID=5,76

# NOTE

If you are unable to locate the datasheets using the links provided, go to the manufacturer’s web site where you should be able to perform a search using the chip datasheet number or name listed, including the extension, htm, pdf, etc.

This introduction presents general information about the EBX architecture and the LittleBoard 735 single board computer (SBC). After reading this chapter you should understand:

EBX Architecture
LittleBoard 735 Description
LittleBoard 735 Features
• Block Diagram
• Major Components
. Headers and Connectors
Jumper Headers
Specifications (physical, environmental, power, cooling)

# EBX Architecture

The “Embedded Board, eXpandable” (EBX) standard is the result of a collaboration between industry leaders Motorola and Ampro to unify the embedded computing industry through a full featured embedded single-board computer (SBC) standard. The EBX standard principally defines physical size, mounting hole pattern, and power connector locations. It does not specify processor type or electrical characteristics. There are recommended connector placements for serial/parallel, Ethernet, graphics, and memory expansion.

Derived from the Ampro LittleBoard form-factor originated in 1984, EBX combines a standard footprint with open interfaces. The EBX form-factor is small enough for deeply embedded applications, yet large enough to contain the functions of a fully embedded SBC (Single Board Computer) including CPU, memory, mass storage interfaces, display controller, serial and parallel ports, today’s advanced operating systems, and other system functions. This embedded SBC standard ensures that embedded system OEMs can standardize their designs and that embedded computing solutions can be designed into space constrained environments with off-the-shelf components.

The EBX standard boasts highly flexible and adaptable system expansion, allowing easy and modular additions of functions such as USB 2.0 ports and Firewire or wireless networking not usually contained in standard product offerings. The EBX system expansion is based on popular existing industry standards, PC/ 104™ and PC/104-Plus™. PC/104 places the ISA bus on compact 3.6" x 3.8" modules with self-stacking capability. PC/104-Plus adds the power of a PCI bus to PC/104 while retaining the basic form-factor. Using PC/104 expansion cards, the PC/104 standard offers access to PC cards from the mobile and handheld computing markets.

The EBX standard integrates all these off-the-shelf standards into a highly embeddable SBC form-factor. EBX supports the legacy of PC/104, hosting the wide variety of embedded system oriented expansion modules from hundreds of companies worldwide. PC/104 brings the advantages of the latest portable and mobile system expansion technologies to embedded applications. See Figure 2-1 on page 4.

The EBX standard also brings stability to the embedded board market and offers OEMs assurance that a wide range of products will be available from multiple sources – now and in the future. The EBX standard is open to continuing technology advancements since it is processor independent. It creates opportunity for economies of scale in chassis, power supply, and peripheral devices.

The EBX specification is freely available to all interested. For further technical information on the EBX standard, go to the PC/104 Consortium web site at www.pc104.org.

![4-40 screws (4) —— PC/104 Module\n0.6 inch spacers (4) —— PC/104 Plus Module\nPCI Stackthrough Headers\n0.6 inch spacers (4) —— Little Board735\n4-40 nuts (4) —— ISABus Stackthrough Expansion Headers\nLB735stackthru](.50-1z020-1020-lb735-refman-final-en/df25d3136bdab2e0270fa8fcf74a07a6bc0c322984abe36bef852ddf97299a09.jpg)

Figure 2-1. Stacking PC/104 Modules with the LittleBoard 735

# Product Description

The LittleBoard 735 is an exceptionally high integration, high performance, rugged, and high quality singleboard system, which contains all the component subsystems of a PC motherboard plus the equivalent of up to 3 expansion boards. Based on the Intel Atom N270 low power, high-integration processor, the LittleBoard 735 gives designers a complete, high performance, embedded processor based on the EBX form factor and conforms to the EBX V2.0 specifications.

Each LittleBoard 735 incorporates an Intel 945GSE chipset for the Graphics and Memory Hub (Northbridge) and the I/O Hub (Southbridge) controllers. This set includes the 82945GSE, Graphics and Memory Controller Hub, (also GMCH), which controls the graphics and memory interface. The other chip in this set is the 82801GBM, I/O Controller Hub 7 Mobile (ICH7-M), which controls some of the I/O functions on the board. One additional chip provides the remainder of the I/O functions: the Standard Microsystems, SCH3114I-NU, Super I/O controller. Together the Intel and SMSC chips provide four serial ports, an EPP/ECP parallel port, six USB 2.0 ports, PS/2 keyboard and mouse interfaces, floppy, one Ultra/ DMA 33/66/100 IDE controller supporting Compact Flash, two independent 10/100/1000BaseT Ethernet interfaces, an audio AC’97 CODEC, PCIe Mini Card, GPIO, SMBus, and two SATA ports on the board. To provide the ISA bus on the board through the PC/104 connector, an ITE IT8888G-L, PCI-to-ISA Bridge is included. The LittleBoard 735 also supports up to 2GB of DDR2 RAM in a single 200-pin SODIMM slot, and a Graphics Media Accelerator (GMA), which provides VGA, TV Out, and LVDS flat panel video interfaces for most LCD panels and CRT monitors.

The LittleBoard 735 can be expanded through the PC/104 and PC/104-Plus expansion for additional system functions, as these buses offer compact, self-stacking, modular expandability. The PC/104 and PC/104-Plus buses are the embedded system versions of the signal set provided on a desktop PC’s ISA and PCI buses at 8MHz and 33MHz clock speeds, respectively.

Among the many embedded-PC enhancements on the LittleBoard 735 that ensure embedded system operation and application versatility are a Watchdog Timer, serial console support, battery-free boot, onboard, high-density Compact Flash socket, and BIOS extensions for OEM boot customization.

The LittleBoard 735 is particularly well suited to either embedded or portable applications and meets the size, power consumption, temperature range, quality, and reliability demands of embedded system applications. It can be stacked with ADLINK MiniModules™ or other PC/104-compliant expansion boards, or it can be used as a powerful computing engine.

# Board Features

# CPU features

Intel 1.6GHz LV, Atom N270 Processor
♦ 512KB L2 cache
♦ 533MHz FSB

# • Memory

Single standard 200-pin DDR2 SODIMM socket
Supports non-ECC, unbuffered memory
Supports +2.5V DDR2, 533MHz RAM up to 2GB

# PC/104-Plus Bus Interfaces

♦ PCI Bus up to 33MHz
♦ PCI 2.2 compliant signals
♦ PC/104 (ISA) Bus up to 8MHz

# • IDE Interfaces

♦ Provides one enhanced IDE controller (Compact Flash)
Supports Ultra DMA 33/66/100 modes
Supports ATAPI and DVD peripherals
Supports IDE native and ATA compatibility modes

# Floppy Disk Interface

Supports one standard floppy disk drive interface
Supports all standard PC/AT formats: 360KB, 1.2MB, 720KB, 1.44MB, 2.88MB

# Parallel Port

♦ Provides a standard printer interface
Supports IEEE standard 1284 protocols of EPP and ECP outputs
Supports Bi-directional data lines
Supports 16 byte FIFO for ECP mode

# . Serial Ports

Four buffered serial ports with full handshaking
Provides 16550-equivalent controllers, each with a built-in 16-byte FIFO buffer
Supports full modem capability on three of the four ports
Supports RS232, RS485, or RS422 operation on each port
Supports programmable word length, stop bits, and parity
Supports 16-bit programmable baud-rate generator and an interrupt generator

# • USB Ports

Provides three root USB hubs
♦ Provides up to six USB ports
Supports USB boot devices
Supports USB v2.0 EHCI and UHCI v1.1
Supports over-current detection status

Keyboard/Mouse Interface

♦ Provides PS/2 keyboard interface
♦ Provides PS/2 mouse interface

Audio Interface

♦ Provides AC’97 CODEC on board
Supports AC’97 standard

Ethernet Interface

♦ Provides two fully independent Gigabit Ethernet ports
♦ Provides integrated LEDs on each port (Link/Activity and Speed)
♦ Provides two Intel 82574IT controller chips
Supports IEEE 802.3 10/100BaseT and 10/100/1000BaseT compatible physical layers
Provides headers for two external Gigabit Ethernet LEDs
Supports Auto-negotiation for speed, duplex mode, and flow control
Supports full duplex or half-duplex mode
Full-duplex mode supports transmit and receive frames simultaneously
Supports IEEE 802.3x Flow control in full duplex mode
Half-duplex mode supports enhanced proprietary collision reduction mode

Video Interfaces (VGA/LVDS/TV Out)

Support VGA (2048 x 1536) with up to 64MB UMA (Unified Memory Architecture)
♦ AGP 4X equivalent graphics performance
♦ Dual channel 9-, 12-, or 18-bit LVDS
♦ LVDS outputs (1 or 2 channel, four differential signals: 3-bits + clock)
♦ Provide one TV Out header

• Miscellaneous

Real Time Clock (RTC) with replaceable battery
Battery-free boot (boots even if battery is dead or missing)
♦ Supports both on-board or external battery for Real Time Clock operation
Thermal and Voltage monitoring
GPIO interface
SMBus interface
♦ Oops! Jumper (BIOS recovery) support
Remote Access
Watchdog Timer (WDT)

# Block Diagram

Figure 2-2 shows the functional components of the LittleBoard 735.
![Here is an accurate and concise description of the flowchart, listing the labeled blocks and their connections with verbatim text.\n\n**Labeled Blocks:**\n*   CPU Intel Atom N270\n*   Clock\n*   Graphics and Memory Hub (Northbridge) 82945GSE\n*   DDR2 SODIMM\n*   TV Out Header\n*   VGA Header\n*   LVDS Header\n*   I/O Hub (Southbridge) 82801GBM (ICH7-M)\n*   SATA Connectors (2)\n*   SMBus Header\n*   GPIO Header\n*   Compact Flash\n*   IDE Header\n*   USB Port 0\n*   USB Port 1\n*   USB Port 2\n*   USB Port 3\n*   USB Port 4\n*   USB Port 5\n*   PCI - ISA Bridge\n*   PC/104 Connector\n*   PC/104-Plus Bus Connector\n*   Gigabit Ethernet Controller 82574IT with Internal Transformer\n*   GLAN2 RJ45 Connector\n*   GLAN1 RJ45 Connector\n*   AC'97 CODEC\n*   PCI Express Mini Card Connector\n*   Super I/O SCH3114I-NU\n*   Utility 1 - PS/2 keyboard, battery, reset, speaker\n*   Utility 2 - PS/2 mouse, SMBus, power button\n*   Floppy\n*   Parallel\n*   RS232 Transceiver and RS422/485 Transceiver\n*   COM 2\n*   COM 1\n*   COM 3\n*   COM 4\n\n**Connections:**\n*   **CPU Intel Atom N270** connects to **Clock** and **Graphics and Memory Hub (Northbridge) 82945GSE**.\n*   **Clock** connects to **CPU Intel Atom N270** and **Graphics and Memory Hub (Northbridge) 82945GSE**.\n*   **Graphics and Memory Hub (Northbridge) 82945GSE** connects to **CPU Intel Atom N270**, **Clock**, **DDR2 SODIMM**, **I/O Hub (Southbridge) 82801GBM (ICH7-M)**, **TV Out Header**, **VGA Header**, and **LVDS Header**.\n*   **DDR2 SODIMM** connects to **Graphics and Memory Hub (Northbridge) 82945GSE**.\n*   **TV Out Header**, **VGA Header**, and **LVDS Header** connect to **Graphics and Memory Hub (Northbridge) 82945GSE**.\n*   **I/O Hub (Southbridge) 82801GBM (ICH7-M)** connects to:\n    *   **Graphics and Memory Hub (Northbridge) 82945GSE**\n    *   **SATA Connectors (2)**\n    *   **SMBus Header** (line labeled **SMBus**)\n    *   **GPIO Header**\n    *   **Compact Flash** (line labeled **IDE**)\n    *   **USB** (line connects to the list of USB ports)\n    *   **PCIe x1 Port3** (line connects to left **Gigabit Ethernet Controller**)\n    *   **PCIe x1 Port1** (line connects to right **Gigabit Ethernet Controller**)\n    *   **PCIe x1 Port2** (line connects to **PCI Express Mini Card Connector**)\n    *   **PCI Bus** (line connects to **PCI - ISA Bridge** and **PC/104-Plus Bus Connector**)\n    *   **AC'97 CODEC**\n    *   **LPC Bus** (line connects to **Super I/O**)\n*   **SATA Connectors (2)** connects to **I/O Hub (Southbridge) 82801GBM (ICH7-M)**.\n*   **SMBus Header** connects to **I/O Hub (Southbridge) 82801GBM (ICH7-M)**.\n*   **GPIO Header** connects to **I/O Hub (Southbridge) 82801GBM (ICH7-M)**.\n*   **Compact Flash** connects to **I/O Hub (Southbridge) 82801GBM (ICH7-M)** and **IDE Header**.\n*   **IDE Header** connects to **Compact Flash**.\n*   **USB** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to **USB Port 0**, **USB Port 1**, **USB Port 2**, **USB Port 3**, **USB Port 4**, and **USB Port 5**.\n*   **PCIe x1 Port3** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to a **Gigabit Ethernet Controller 82574IT with Internal Transformer**.\n*   **PCIe x1 Port1** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to a **Gigabit Ethernet Controller 82574IT with Internal Transformer**.\n*   **PCIe x1 Port2** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to **PCI Express Mini Card Connector**.\n*   **PCI Bus** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to **PCI - ISA Bridge** and **PC/104-Plus Bus Connector**.\n*   **PCI - ISA Bridge** connects to **PCI Bus** and **PC/104 Connector** (line labeled **ISA**).\n*   **PC/104 Connector** connects to **PCI - ISA Bridge**.\n*   **Gigabit Ethernet Controller 82574IT with Internal Transformer** (two instances) connects to **PCIe x1 Port3** / **PCIe x1 Port1** respectively, and **MDI** (line).\n*   **MDI** (two instances) connects **Gigabit Ethernet Controller 82574IT with Internal Transformer** to **GLAN2 RJ45 Connector** / **GLAN1 RJ45 Connector** respectively.\n*   **AC'97 CODEC** connects to **I/O Hub (Southbridge) 82801GBM (ICH7-M)**.\n*   **PCI Express Mini Card Connector** connects to **PCIe x1 Port2**.\n*   **LPC Bus** connects **I/O Hub (Southbridge) 82801GBM (ICH7-M)** to **Super I/O SCH3114I-NU**.\n*   **Super I/O SCH3114I-NU** connects to:\n    *   **LPC Bus**\n    *   **Utility 1 - PS/2 keyboard, battery, reset, speaker**\n    *   **Utility 2 - PS/2 mouse, SMBus, power button**\n    *   **Floppy**\n    *   **Parallel**\n    *   **RS232 Transceiver and RS422/485 Transceiver** (left instance)\n    *   **RS232 Transceiver and RS422/485 Transceiver** (right instance)\n*   **Utility 1 - PS/2 keyboard, battery, reset, speaker** connects to **Super I/O SCH3114I-NU**.\n*   **Utility 2 - PS/2 mouse, SMBus, power button** connects to **Super I/O SCH3114I-NU**.\n*   **Floppy** connects to **Super I/O SCH3114I-NU**.\n*   **Parallel** connects to **Super I/O SCH3114I-NU**.\n*   **RS232 Transceiver and RS422/485 Transceiver** (left instance) connects to **Super I/O SCH3114I-NU**, **COM 2**, and **COM 1**.\n*   **RS232 Transceiver and RS422/485 Transceiver** (right instance) connects to **Super I/O SCH3114I-NU**, **COM 3**, and **COM 4**.](.50-1z020-1020-lb735-refman-final-en/1d3d522e8b47ff392483776ed5c70ead2700fdb9c1d92c3c28f4258fd74c361a.jpg)

Figure 2-2. Functional Block Diagram

# Major Components (ICs)

Table 2-1 lists the major ICs on the LittleBoard 735, including a brief description of each. Figures 2-3 and 2-4 show the locations of the chips.

Table 2-1. Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U1)</td><td>Intel</td><td>Atom N270</td><td>Single-core 1.6GHz, 2.5W processor with on-die 512kB, 8-way L2 cache</td><td>Manages Northbridge graphics and memory hubs and Southbridge I/O hub</td></tr><tr><td>Graphics and Memory Chipset (U2)</td><td>Intel</td><td>82945GSE</td><td>Northbridge Graphics and Memory controller hub</td><td>Provides graphics controller and memory controller</td></tr><tr><td>I/O Hub (U4)</td><td>Intel</td><td>82801GBM (ICH7-M)</td><td>Southbridge Input/Output controller hub</td><td>Provides interfaces and controllers for peripheral devices</td></tr><tr><td>Super I/O (U15 on back of the board) [See Figure 2-4]</td><td>SMSC</td><td>SCH3114I-NU</td><td>Legacy I/O controller</td><td>Provides LPC I/O functions for serial, floppy, parallel, and utility interfaces</td></tr><tr><td>Ethernet Controller 1 (U10)</td><td>Intel</td><td>82574IT</td><td>GLAN1 Gigabit Ethernet controller</td><td>Generates PCIe 10T/100TX/1000TEthernet signals</td></tr><tr><td>Ethernet Controller 2 (U37)</td><td>Intel</td><td>82574IT</td><td>GLAN2 Gigabit Ethernet controller</td><td>Generates PCIe 10T/100TX/1000TEthernet signals</td></tr><tr><td>ISA Bridge (U13)</td><td>ITE</td><td>IT8888F</td><td>Interface between PCI bus and ISA bus</td><td>Migrates legacy ISA bus</td></tr><tr><td>Audio AC'97 CODEC (U14)</td><td>Realtek</td><td>ALC203-LF</td><td>Encoder and decoder of audio data for transmission, storage, encryption, playback, or editing</td><td>Supports 20-bit DAC and 18-bit ADC resolutions</td></tr><tr><td>RS232 Transceiver (U17)</td><td>Analog Devices</td><td>ADM213EARSZ</td><td>RS232 Transceiver for COM1 and COM2</td><td>Transmits and receives RS232 signals for serial ports 1 and 2</td></tr><tr><td>RS485/422 Transceiver (U19)</td><td>Linear</td><td>LTC1334CG#PBF</td><td>RS422/485 Transceiver for COM1 and COM2</td><td>Transmits and receives RS485/422 signals for serial ports 1 and 2</td></tr><tr><td>RS232 Transceiver (U21)</td><td>Analog Devices</td><td>ADM213EARSZ</td><td>RS232 Transceiver for COM3 and COM4</td><td>Transmits and receives RS232 signals for serial ports 3 and 4</td></tr><tr><td>RS485/422 Transceiver (U22)</td><td>Linear</td><td>LTC1334CG#PBF</td><td>RS422/485 Transceiver for COM3 and COM4</td><td>Transmits and receives RS485/422 signals for serial ports 3 and 4</td></tr></table>

#

U1 - CPU
U2 - Northbridge Memory Hub
U4 - Southbridge I/O Hub
U10 - GLAN1 Ethernet Controller
U13 - PCI-to-ISA Bridge
U14 - Audio CODEC
U17 - RS232 Transceiver - COM1/COM2
U19 - RS485/422 Transceiver - COM1/COM2
U21 - RS232 Transceiver - COM3/COM4
U22 - RS485/422 Transceiver - COM3/COM4
U37 - GLAN2 Ethernet Controller

![U4\nU1\nU2\nU14\nU7\nU13\nU17 U19\nU22 U21\nU10\nU37](.50-1z020-1020-lb735-refman-final-en/9870c544e9c23ec639b5d5a8f1d7a4fea8b9ed8b3837048baab27e22af5b754f.jpg)

LB735\_Comp\_Top\_d
Figure 2-3. Component Locations (Top Side)

Key:

U15 - Super IO Controller
J37 - PCI Express Mini Card Socket
J38 - PCI Express Mini Card Latch

![J37\nJ38\nU15](.50-1z020-1020-lb735-refman-final-en/1eaeeb3f384aef643a055cc3f3afad6ac785825e0cbec38823a189ba73c854b8.jpg)

LB735\_Back\_b
Figure 2-4. Component Locations (Bottom Side)

# Headers and Connectors

Table 2-2 describes the headers and connectors shown in Figure 2-6 on page 14. All I/O headers use 0.100" (2.54mm) pitch unless otherwise indicated.

Table 2-2. Header and Connector Descriptions

<table><tr><td>Jack #</td><td>Name</td><td>Description</td></tr><tr><td>BAT1</td><td>Battery Socket</td><td>Battery socket for 3 volt Lithium battery</td></tr><tr><td>J1A,B,C,D</td><td>PC/104 bus</td><td>104-pin standard connector for PC/104</td></tr><tr><td>J2A,B,C,D</td><td>PC/104-Plus</td><td>120-pin, 0.079" (2mm), standard connector for PCI bus</td></tr><tr><td>J3</td><td>Video (VGA)</td><td>12-pin, 0.079" (2mm), header for output to a VGA compatible display</td></tr><tr><td>J6</td><td>IDE</td><td>40-pin standard header for the primary IDE interface</td></tr><tr><td>J8</td><td>Compact Flash</td><td>50-pin, 0.050" (1.27mm), socket accepts Type I or Type II Compact Flash cards</td></tr><tr><td>J9</td><td>Audio In/Out</td><td>26-pin, 0.079" (2mm), header for all of the audio signals (input/output)</td></tr><tr><td>J10</td><td>GLAN1</td><td>8-pin, RJ45 connector for 10/100/1000BaseT Gigabit Ethernet port 1 with magnetics</td></tr><tr><td>J11</td><td>Serial A</td><td>20-pin header for serial ports 1 and 2 (COM 1 &amp; COM 2)</td></tr><tr><td>J12</td><td>Serial B</td><td>20-pin header for serial ports 3 and 4 (COM 3 &amp; COM 4)</td></tr><tr><td>J13</td><td>Utility 2</td><td>24-pin header for mouse, SMBus, and power button</td></tr><tr><td>J14</td><td>USB 2 &amp; 3</td><td>10-pin, 0.079" (2mm) header for USB2 and USB3 ports</td></tr><tr><td>J15</td><td>Utility 1</td><td>16-pin header for keyboard, external battery, reset switch, and speaker</td></tr><tr><td>J16</td><td>Parallel</td><td>26-pin header for parallel port</td></tr><tr><td>J17</td><td>Floppy</td><td>34-pin header for floppy disk drive interface</td></tr><tr><td>J18</td><td>GLAN2</td><td>8-pin, RJ45 connector for 10/100/1000BaseT Gigabit Ethernet port 2 with magnetics</td></tr><tr><td>J19</td><td>Power In</td><td>7-pin, 0.156" (3.96mm), header for input power</td></tr><tr><td>J26</td><td>Video (LVDS)</td><td>30-pin, 0.079" (2mm), header for LVDS compatible video displays</td></tr><tr><td>J30</td><td>Power On</td><td>3-pin header for ATX power-on functions</td></tr><tr><td>J31</td><td>Memory</td><td>200-pin, 0.024" (0.60mm) socket for DDR2 SDRAM SODIMM</td></tr><tr><td>J32</td><td>SATA1</td><td>7-pin, 0.050" (1.27mm) standard connector for serial ATA</td></tr><tr><td>J33</td><td>SATA2</td><td>7-pin, 0.050" (1.27mm) standard connector for serial ATA</td></tr><tr><td>J34</td><td>Optional Fan</td><td>3-pin header provides +5V or +12V, tach, and ground to optional CPU fan</td></tr><tr><td>J35</td><td>Battery Input</td><td>2-pin, 0.049" (1.24mm) header for power from external battery</td></tr><tr><td>J36</td><td>TV Out</td><td>6-pin header for TV Out signals</td></tr><tr><td>J37</td><td>PCI Express Mini Card (on back of the board; see Figure 2-4 on page 11)</td><td>52-pin, 0.012" (0.30mm) standard socket for PCI Express Mini Card functions</td></tr><tr><td>J38</td><td>Latch (on back of the board; see Figure 2-4 on page 11)</td><td>Latch for the PCI Express Mini Card connector</td></tr><tr><td>J39</td><td>USB 4 &amp; 5</td><td>10-pin, 0.079" (2mm) header for USB4 and USB5 ports</td></tr><tr><td>J40</td><td>GPIO</td><td>10-pin, 0.079" (2mm) header for General Purpose IO signals</td></tr><tr><td>J41</td><td>DNP</td><td>Do not populate</td></tr><tr><td>J42</td><td>DNP</td><td>Do not populate</td></tr><tr><td>J43</td><td>DNP</td><td>Do not populate</td></tr><tr><td>J44</td><td>USB 0 &amp; 1</td><td>10-pin, 0.079" (2mm) header for USB0 and USB1 ports</td></tr><tr><td>J45</td><td>SMBus</td><td>5-pin, 0.049" (1.25mm) header for external device connection</td></tr><tr><td>J46</td><td>Power On Button and Reset Switch</td><td>5-pin header for power-on button and reset switch</td></tr><tr><td>J47</td><td>LED - GLAN1</td><td>5-pin, 0.049" (1.25mm) header for Gigabit Ethernet1 external LED</td></tr><tr><td>J48</td><td>LED - GLAN2</td><td>5-pin, 0.049" (1.25mm) header for Gigabit Ethernet2 external LED</td></tr></table>

# NOTE

The pinout tables in Chapter 3 of this manual identify pin sequence using the following methods: A 20-pin header with two rows of pins, using odd/even numbering, where pin 2 is directly across from pin 1, is noted as 20-pin, 2 rows, odd/even (1, 2). Alternately, a 20-pin connector using consecutive numbering, where pin 11 is directly across from pin 1, is noted in this way: 20-pin, 2 rows, consecutive (1, 11). The second number in the parenthesis is always directly across from pin 1. See Figure 2-5.

![| Row | Value |\n|-----|-------|\n| 19  | 19    |\n| 9   | 9     |\n| 7   | 7     |\n| 5   | 5     |\n| 3   | 3     |\n| 1   | 1     |\n| 20  | 20    |\n| 10  | 10    |\n| 8   | 8     |\n| 6   | 6     |\n| 4   | 4     |\n| 2   | 2     |\n| 10  | 10    |\n| 5   | 5     |\n| 4   | 4     |\n| 3   | 3     |\n| 2   | 2     |\n| 1   | 1     |\n| 0   | 0     |\n| 0   | -1    |\n| 0   | -2    |\n| 0   | -3    |\n| 0   | -4    |\n| 0   | -5    |\n| 0   | -6    |\n| 0   | -7    |\n| 0   | -8    |\n| 0   | -9    |\n| 0   | -10   |\n| 0   | -11   |\n| 1   | 11    |\n| 0   | -11   |\nLB735_ConNum](.50-1z020-1020-lb735-refman-final-en/6c5d49fec12afadbc549f0cc21c5ad9bf55ead29305a942cdacd108551b925d8.jpg)

Figure 2-5. Pin Sequence Identification

![Key:\nBAT1 - Battery Socket\nJ1 - PC/104 Connector\nJ2 - PC/104-Plus\nJ3 - Video (VGA)\nJ6 - IDE\nJ8 - Compact Flash\nJ9 - Audio\nJ10 - RJ45 GLAN1 Ethernet\nJ11 - Serial A - COM1/COM2\nJ12 - Serial B - COM3/COM4\nJ13 - Utility 2\nJ14 - USB2 & USB3\nJ15 - Utility 1\nJ16 - Parallel\nJ17 - Floppy\nJ18 - RJ45 GLAN2 Ethernet\nJ19 - Power In\nJ26 - Video (LVDS)\nJ30 - Power On\nJ31 - SODIMM Socket\nJ32 - SATA1\nJ33 - SATA2\nJ34 - Fan\nJ35 - Battery\nJ36 - TV Out\nJ39 - USB4 & USB5\nJ40 - GPIO\nJ41 - DNP\nJ42 - DNP\nJ43 - DNP\nJ44 - USB0 & USB1\nJ45 - SMBus\nJ46 - Power Button and Reset Switch\nJ47 - LED - GLAN1\nJ48 - LED - GLAN2\nJP1 - See jumper table\nJP2 - See jumper table\nJP3 - See jumper table\nJP4 - See jumper table\nJP5 - See jumper table\nJP6 - See jumper table\nJP7 - See jumper table\nJP8 - See jumper table\nJP9 - See jumper table\nJP10 - See jumper table\nJP3 - See jumper table\nJP4 - See jumper table\nJP5 - See jumper table\nJP6 - See jumper table\nJP7 - See jumper table\nJP8 - See jumper table\nJP9 - See jumper table\nJP10 - See jumper table\nJ33 J32 J26 J3 J9\nJP40 JP8 JP36 J36 J31\nAB ABCD J34 J30 J45 BAT1 J47 J10 J18 Ethernet Grounding Pad Board Grounding Pad](.50-1z020-1020-lb735-refman-final-en/db7e7e6a20c37580396d29847702ef921d909160e7d76c0395912f112fa794ba.jpg)

Figure 2-6. Connector Locations (Top Side)

# CAUTION

The two Ethernet ports share a common ground (transformer center tap), that is floating until you determine how the common ground is connected. The grounding holes (8) of the LittleBoard 735 are connected to ground potential (return) of the DC power supply connected to the board through J19.

# NOTE

Pin 1 is shown as a black pin (square or round) on all headers in all illustrations.

# Jumper Header Definitions

Table 2-3 describes the jumper headers shown in Figure 2-7.
Table 2-3. Jumper Settings

<table><tr><td>Jumper #</td><td>Installed</td><td>Removed/Installed</td></tr><tr><td>JP1 – RTC (Real Time Clock) Reset</td><td>Enable (pins 1-2)</td><td>Disable (Removed) Default</td></tr><tr><td>JP2 – Power Management</td><td>Power Up by S3 (pins 1-2)Default</td><td>Power Up by S5 (pins 2-3)</td></tr><tr><td>JP3 – Serial Port 2RS485 Termination</td><td>Enable Termination (pins 1-2)</td><td>Disable Termination (Removed)Default</td></tr><tr><td>JP4 – Serial Port 1RS485 Termination</td><td>Enable Termination (pins 1-2)</td><td>Disable Termination (Removed)Default</td></tr><tr><td>JP5 – Fan Voltage Selection</td><td>Enable +5V (pins 1-2) Default</td><td>Enable +12V (pins 2-3)</td></tr><tr><td>JP6 – Compact Flash Master/Slave</td><td>Enable Slave (pins 1-2) Default[ATA Master]</td><td>Enable Master (pins 2-3)[ATA Slave]</td></tr><tr><td>JP7 – Compact Flash Voltage Selection</td><td>Enable +5V (pins 1-2)</td><td>Enable +3.3V (pins 2-3) Default</td></tr><tr><td>JP8 – LVDS Voltage Selection</td><td>Enable +3.3V (pins 1-2) Default</td><td>Enable +5V (pins 2-3)</td></tr><tr><td>JP9 – Serial Port 4RS485 Termination</td><td>Enable Termination (pins 1-2)</td><td>Disable Termination (Removed)Default</td></tr><tr><td>JP10 – Serial Port 3RS485 Termination</td><td>Enable Termination (pins 1-2)</td><td>Disable Termination (Removed)Default</td></tr></table>

Note: Only the jumper headers listed above are populated on the board. Jumpers or shunts use $. 0 7 9 "$ (2mm) pitch.

![Key:\nJP1 - RTC Reset\nJP2 - Power Management\nJP3 - Serial2 RS485\nJP4 - Serial1 RS485\nJP5 - Fan Voltage\nJP6 - Compact Flash Master/Slave\nJP7 - Compact Flash Voltage\nJP8 - LVDS Voltage\nJP9 - Serial4 RS485\nJP10 - Serial3 RS485\nJP1\nJP8\nJP5\nJP2\nJP9\nJP4\nJP10\nJP3\nJP7JP6\nLB735_Jmpr_a](.50-1z020-1020-lb735-refman-final-en/ae27445429cd6d1138508bb6861c54840778717f2e0ad52ca71091de2b7fed98.jpg)

Figure 2-7. Jumper Header Locations (Top Side)

# Specifications

# Physical Specifications

Table 2-4 lists the physical dimensions of the board.
Table 2-4. Weight and Footprint Dimensions

<table><tr><td>Item</td><td>Dimension</td><td rowspan="6">NOTE</td><td rowspan="6">Overall height is measured from the upper board surface to the highest permanent component (J10, RJ45 connector) on the upper board surface. This measurement does not include the various heatsinks on the board. The heatsinks increase this dimension. See Table 2-7.</td></tr><tr><td>Weight</td><td>0.280kg. (0.60lbs.)</td></tr><tr><td>Height (overall)</td><td>16.26mm (0.64&quot;)</td></tr><tr><td>Width</td><td>146mm (5.75&quot;)</td></tr><tr><td>Length</td><td>203mm (8.0&quot;)</td></tr><tr><td>Thickness</td><td>2.36mm (0.093&quot;)</td></tr></table>

# Mechanical Specifications

Figure 2-8 shows the top side view of the LittleBoard 735 with mechanical mounting dimensions.
![0.20\n0\n0.20\n0\n2.65\n2.80\n5.80\n5.70\nLB735_Dimen_Top_d\n7.22\n7.60\n7.80\n0.20\n0\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.20\n0.5.35\n5.55\n5.35](.50-1z020-1020-lb735-refman-final-en/7c6fe39d23b0b8340c3a3ae6fb297f545e440a0bde1f40c7388ecc8120e9563c.jpg)

Figure 2-8. LittleBoard 735 Dimensions

NOTE All dimensions are given in inches.

# Environmental Specifications

Table 2-5 provides the most efficient operating and storage condition ranges required for this board.
Table 2-5. Environmental Requirements

<table><tr><td></td><td>Parameter</td><td>1.6GHz Atom N270 Conditions</td></tr><tr><td rowspan="3">Temperature</td><td>Operating</td><td>-20° to +70°C(-4° to +158°F)</td></tr><tr><td>Extended(Optional)</td><td>-40° to +80°C(-40° to +176°F)</td></tr><tr><td>Storage</td><td>-55° to +85°C(-67° to +185°F)</td></tr><tr><td rowspan="2">Humidity</td><td>Operating</td><td>5% to 95%relative humidity,non-condensing</td></tr><tr><td>Non-operating</td><td>5% to 95%relative humidity,non-condensing</td></tr></table>

# Power Specifications

Table 2-6 provides the power requirements for the LittleBoard 735.
Table 2-6. Power Supply Requirements

<table><tr><td>Parameter</td><td>1.6GHz Atom N270 Characteristics</td><td>800MHz Atom N270 Characteristics w/clock-down speed from 1.6GHz</td><td>1.6GHz Atom N270 Characteristics w/fan</td></tr><tr><td>Input Type</td><td>Regulated DC voltages</td><td>Regulated DC voltages</td><td>Regulated DC voltages</td></tr><tr><td>Peak In-rush Current</td><td>8.00A (40.00W)</td><td>8.00A (40.00W)</td><td>8.00A (40.00W)</td></tr><tr><td>Idle Current</td><td>1.58A (7.91W)</td><td>1.50A (7.48W)</td><td>1.64A (8.22W)</td></tr><tr><td>BIT Current</td><td>3.17A (15.83W)</td><td>2.90A (14.52W)</td><td>3.25A (16.25W)</td></tr></table>

# Operating configurations:

In-rush operating configuration includes video, 1GB DDR2 RAM, and power.
Idle operating configuration includes the in-rush configuration as well as one SATA hard drive, I/O board, floppy drive, and PS/2 keyboard and mouse.
BIT = Burn-In-Test. Operating configuration includes idle configuration as well as a second SATA hard drive, four serial loop-backs, two Ethernet connections, four USB loop-backs, one USB flash drive, and one USB Compact Flash reader with 64MB Compact Flash.

# Thermal/Cooling Requirements

The LittleBoard 735 is designed to operate at its maximum CPU speed of 1.6GHz and requires a cooling solution to cool the CPU, Memory Hub, I/O Hub and voltage regulators on the board. ADLINK offers two cooling solutions. (See Table 2-7.)

Table 2-7. ADLINK Optional Cooling Solutions

<table><tr><td>Cooling Solution</td><td>Description</td><td>Height of Cooling Solution (without LittleBoard 735)</td></tr><tr><td>Passive Heatsink (without fan)</td><td>Qualified to maintain optimal performance up to +70°C.</td><td>0.67&quot; (17.06mm)</td></tr><tr><td>Active Heatsink (with fan)</td><td>Qualified to maintain optimal performance up to +80°C.</td><td>2.61&quot; (66.42mm)</td></tr></table>

NOTE These two cooling solutions exceed the standard height limitation described in the EBX specification.

# Overview

This chapter discusses the features of the LittleBoard 735 I/O interfaces in the following order:

Interrupt Channel Assignments
• Memory Map
• I/O Address Map
Floppy Interface
. Parallel Interface
. Serial Interfaces
Utility Interfaces
♦ Keyboard
♦ Mouse
♦ Battery
+ Power Button
▲ Reset Switch
♦ Speaker
♦ SMBus
• USB Interfaces
Audio Interface
Video Interfaces
CRT
♦ LVDS
TV Out
Power Interfaces
♦ Power In
ATX Power On
+ Power Button
Miscellaneous
Time of Day/RTC
Temperature Monitoring
♦ User GPIO Interface
+ SMBus Interface
♦ Oops! Jumper (BIOS recovery)
♦ Remote Access
▲ Watchdog Timer
Optional CPU fan

External Battery Input
♦ Dual LED interfaces for Gigabit Ethernet

# NOTE

ADLINK Technology, Inc. only supports the features and options described in this manual. The main integrated circuits (ICs) on the LittleBoard 735 may provide more features or options than are listed in this manual, and those features and options may not function as specified in the IC documentation.

This chapter does not include pinout tables for standard headers and connectors such as PC/104, Ethernet RJ45, 40-pin IDE, Floppy, and Compact Flash.

# Interrupt Channel Assignments

The interrupt channel assignments are shown in Table 3-1.

Table 3-1. Interrupt Channel Assignments

<table><tr><td>Device vs IRQ No.</td><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td><td>9</td><td>10</td><td>11</td><td>12</td><td>13</td><td>14</td><td>15</td></tr><tr><td>Timer</td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Keyboard</td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Secondary Cascade</td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>COM1</td><td></td><td></td><td></td><td>O</td><td>D</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td>O</td><td></td><td></td><td></td><td></td></tr><tr><td>COM2</td><td></td><td></td><td></td><td>D</td><td>O</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td>O</td><td></td><td></td><td></td><td></td></tr><tr><td>COM3</td><td></td><td></td><td></td><td>O</td><td>O</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td>D</td><td></td><td></td><td></td><td></td></tr><tr><td>COM4</td><td></td><td></td><td></td><td>O</td><td>O</td><td></td><td></td><td></td><td></td><td></td><td>D</td><td>O</td><td></td><td></td><td></td><td></td></tr><tr><td>Floppy</td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Parallel</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td></td><td>D</td><td></td><td></td><td></td><td></td><td></td><td></td><td>O</td><td>O</td></tr><tr><td>RTC</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>IDE</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>D</td><td></td></tr><tr><td>Math Coprocessor</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td></tr><tr><td>PS/2 Mouse</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td></tr><tr><td>PCI INTA</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTB</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTC</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTD</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTE</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTF</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTG</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTH</td><td colspan="16">Automatically Assigned</td></tr></table>

Legend: D = Default, O = Optional, X = Fixed

# NOTE

The PCI IRQs for the Ethernet, Video, and Internal Local Bus are automatically assigned by the BIOS Plug and Play logic. Local ISA IRQs assigned during initialization can not be used by external devices.

# Memory Map

The following table provides the common PC/AT memory allocations. Memory below 000500h is used by the BIOS.

Table 3-2. Memory Map

<table><tr><td colspan="2">Base Address</td><td>Function</td></tr><tr><td>00000000h -</td><td>0009FFFFh</td><td>Conventional Memory</td></tr><tr><td>000A0000h -</td><td>000AFFFFh</td><td>Graphics Memory</td></tr><tr><td>000B0000h -</td><td>000B7FFFh</td><td>Mono Text Memory</td></tr><tr><td>000B8000h -</td><td>000BFFFFh</td><td>Color Text Memory</td></tr><tr><td>000C0000h -</td><td>000CFFFFh</td><td>Standard Video BIOS</td></tr><tr><td>000D0000h -</td><td>000DFFFFh</td><td>Reserved for Extended BIOS*</td></tr><tr><td>000E0000h -</td><td>000EFFFFh</td><td>Extended System BIOS Area</td></tr><tr><td>000F0000h -</td><td>000FFFFFFh</td><td>System BIOS Area (Storage and RAM Shadowing)</td></tr><tr><td colspan="2">Top 0, 1, or 8MB of DRAM</td><td>Integrated Graphics Memory</td></tr><tr><td>FFE00000h -</td><td>FFFFFFFFh</td><td>System Flash</td></tr></table>

\* The BIOS contains a setting to forward memory to the ISA bus.

# I/O Address Map

Table 3-3 provides the list of I/O addresses on the LittleBoard 735.

Table 3-3. I/O Address Map

<table><tr><td>Address (hex)</td><td>Subsystem</td></tr><tr><td>0000-000F</td><td>Primary DMA Controller</td></tr><tr><td>0020-0021</td><td>Master Interrupt Controller</td></tr><tr><td>0040-0043</td><td>Programmable Interrupt Timer (Clock/Timer)</td></tr><tr><td>0060</td><td>Keyboard Controller</td></tr><tr><td>0061</td><td>NMI, Speaker control</td></tr><tr><td>0063</td><td>NMI Controller</td></tr><tr><td>0064</td><td>Keyboard Controller</td></tr><tr><td>0065</td><td>NMI Controller</td></tr><tr><td>0067</td><td>NMI Controller</td></tr><tr><td>0070-007F</td><td>CMOS RAM, NMI Mask Reg, RT Clock</td></tr><tr><td>0080</td><td>System reserved</td></tr><tr><td>0081-0083</td><td>DMA Page Registers</td></tr><tr><td>0084-0086</td><td>System reserved</td></tr><tr><td>0087</td><td>DMA Page Register</td></tr><tr><td>0088</td><td>System reserved</td></tr><tr><td>0089-008B</td><td>DMA Page Registers</td></tr><tr><td>008C-008E</td><td>System reserved</td></tr><tr><td>008F</td><td>DMA Page Register</td></tr><tr><td>0090-0091</td><td>System reserved</td></tr><tr><td>0092</td><td>Fast A20 gate and CPU reset</td></tr><tr><td>0093-009F</td><td>System reserved</td></tr><tr><td>00A0-00A1</td><td>Slave Interrupt Controller</td></tr><tr><td>00A2-00BF</td><td>System reserved</td></tr><tr><td>00C0-00DF</td><td>Slave DMA Controller #2</td></tr><tr><td>00E0-00EF</td><td>System reserved</td></tr><tr><td>00F0-00FF</td><td>Math Coprocessor</td></tr><tr><td>01F0-01F7</td><td>IDE Hard Disk Controller</td></tr><tr><td>0200-0240h</td><td>Mapped to ISA</td></tr><tr><td>0240-0260h</td><td>Mapped to ISA</td></tr><tr><td>0279h</td><td>Mapped to ISA</td></tr><tr><td>02E8-02EF</td><td>Serial Port 4 (COM4)</td></tr><tr><td>02F8-02FF</td><td>Serial Port 2 (COM2)</td></tr><tr><td>0300-0340h</td><td>Mapped to ISA</td></tr><tr><td>0340-0360h</td><td>Mapped to ISA</td></tr><tr><td>0378-037F</td><td>Parallel Port (Standard and EPP)</td></tr><tr><td>03B0-03BB</td><td>Video (monochrome)</td></tr><tr><td>03C0-03DF</td><td>Video (VGA)</td></tr><tr><td>03E8-03EF</td><td>Serial Port 3 (COM3)</td></tr><tr><td>03F0-03F5</td><td>Floppy Disk Controller</td></tr><tr><td>03F6</td><td>IDE Hard Disk Controller</td></tr><tr><td>03F7</td><td>Floppy Disk Controller</td></tr><tr><td>03F8-03FF</td><td>Serial Port 1 (COM1)</td></tr><tr><td>04D0-04D1</td><td>Edge/Level Trigger PIC</td></tr><tr><td>0778-077F</td><td>Parallel Port (ECP Extensions) (Port 378+400)</td></tr><tr><td>0A79h</td><td>Mapped to ISA</td></tr><tr><td>0CF8-0CFF</td><td>PCI Configuration Registers</td></tr><tr><td>0CF9</td><td>Reset Control Register</td></tr></table>

# Floppy Drive Interface

The SCH3114I-NU (U15) chip provides the floppy controller and supports one floppy drive. The floppy signals are provided through a standard 34-pin header (J17). The floppy controller will support a 360k, 720k, 1.2M, 1.44M, or 2.88M drive.

The floppy drive header provides 34 pins, 2 rows, odd/even sequence (1, 2) with 0.100" (2.54mm) pitch.

# Parallel Port Interface

The parallel port supports standard parallel, Bi-directional, ECP, and EPP protocols. The SCH3114I-NU chip (U15) provides the parallel port interface signals.

The parallel header provides 26 pins, 2 rows, odd/even sequence (1, 2), with 0.100" (2.54mm) pitch.

Table 3-4. Parallel Interface Pin Signals (J16)

<table><tr><td>Pin #</td><td>Signal</td><td>In/Out</td><td>Description</td></tr><tr><td>1</td><td>Strobe*</td><td>Out</td><td>Strobe* – This is an output signal used to strobe data into the printer. I/O pin in ECP/EPP mode.</td></tr><tr><td>2</td><td>AFD*</td><td>Out</td><td>Auto Feed* – This is a request signal into the printer to automatically feed one line after each line is printed.</td></tr><tr><td>3</td><td>PD0</td><td>I/O</td><td>Parallel Port Data 0 – These pins (PD0 to PD7) provide parallel port data.</td></tr><tr><td>4</td><td>ERR*</td><td>Out</td><td>Error* – This is a status output signal from the printer. A Low State indicates an error condition on the printer.</td></tr><tr><td>5</td><td>PD1</td><td>I/O</td><td>Parallel Port Data 1 – Refer to pin 3 for more information.</td></tr><tr><td>6</td><td>INIT*</td><td>Out</td><td>Initialize* – This signal used to Initialize printer. Output in standard Mode, I/O in ECP/EPP mode.</td></tr><tr><td>7</td><td>PD2</td><td>I/O</td><td>Parallel Port Data 2 – Refer to pin 3 for more information.</td></tr><tr><td>8</td><td>SLIN</td><td>Out</td><td>Select In – This output signal is used to select the printer. I/O pin in ECP/EPP mode.</td></tr><tr><td>9</td><td>PD3</td><td>I/O</td><td>Parallel Port Data 3 – Refer to pin 3 for more information.</td></tr><tr><td>10, 12</td><td>GND</td><td></td><td>Ground</td></tr><tr><td>11</td><td>PD4</td><td>I/O</td><td>Parallel Port Data 4 – Refer to pin 3 for more information.</td></tr><tr><td>13</td><td>PD5</td><td>I/O</td><td>Parallel Port Data 5 – Refer to pin 3 for more information.</td></tr><tr><td>14, 16</td><td>GND</td><td></td><td>Ground</td></tr><tr><td>15</td><td>PD6</td><td>I/O</td><td>Parallel Port Data 6 – Refer to pin 3 for more information.</td></tr><tr><td>17</td><td>PD7</td><td>I/O</td><td>Parallel Port Data 7 – Refer to pin 3 for more information.</td></tr><tr><td>18, 20</td><td>GND</td><td></td><td>Ground</td></tr><tr><td>19</td><td>ACK*</td><td>In</td><td>Acknowledge* – This printer output status indicates it has received the data and is ready to accept new data if the signal state is Low.</td></tr><tr><td>21</td><td>BUSY</td><td>In</td><td>Busy – This printer output status indicates the printer is not ready to accept data if the signal state is High.</td></tr><tr><td>22, 24</td><td>GND</td><td></td><td>Ground</td></tr><tr><td>23</td><td>PE</td><td>In</td><td>Paper End – The printer output status indicates the printer is out of paper if the signal state is High.</td></tr><tr><td>25</td><td>SLCT</td><td>In</td><td>Select – This printer output status indicates the printer is selected and powered on if the signal state is High.</td></tr><tr><td>26</td><td>Key/NC</td><td></td><td>Key - Not connected</td></tr></table>

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.

# Serial Interfaces

Two MAX213ECAI+ chips and two LTC1334CG#PBF chips provide the circuitry for the four serial ports. The two MAX213ECAI+ chips provide the RS232 mode, and the two LTC1334CG#PBF chips provide the RS485/RS422 modes. The four serial ports support the following features:

• Four individual 16550-compatible UARTs
Programmable word length, stop bits and parity
16-bit programmable baud rate generator
Interrupt generator
Loop-back mode
. Four individual 16-bit FIFOs
Serial A Interface (J11)

♦ Serial Port 1 (COM1) supports RS232/RS485/RS422 and full modem support
♦ Serial Port 2 (COM2) supports RS232/RS485/RS422 and full modem support

• Serial B Interface (J12)

♦ Serial Port 3 (COM3) supports RS232/RS485/RS422 and full modem support
Serial Port 4 (COM4) supports RS232/RS485/RS422

# NOTE

The RS232 and RS485/RS422 modes can be selected for any serial port in BIOS Setup under the Advanced menu. However, the RS232 mode is the default selection (Standard) for any serial port.

To implement the two-wire RS485 mode on any serial port, you must tie the equivalent pins together for each port.

For example, on Serial Port 1, tie pin 3 to pin 5 and pin 4 to pin 6 at the Serial A interface header (J11) as shown in Figure 3-1. As an alternate, tie pin 2 to pin 3 and pin 7 to pin 8 at the DB9 serial connector for Serial Port 1 as shown in Figure 3-1. Refer also to the following tables for the specific pin signals on each connector.

# NOTE

The RS422 mode uses a four-wire interface and does not require any pins tied together, but you must select RS485 in BIOS Setup and make sure the termination jumper is removed.

![Serial A Interface (J11)\nfor Serial Port 1\n(or COM1 Port)\nTop View\n19 9 7 5 3 1\n20 10 8 6 4 2\nOr Standard DB9 Serial\nPort Connector (Male)\nFront View\n1 2 3 4 5\n6 7 8 9\nLB73RS485conn_b](.50-1z020-1020-lb735-refman-final-en/2269bdb3e815dc1a35d94b78c3824bc4db3a36505e6649e6a1e282d439e5ca27.jpg)

Figure 3-1. RS485 Serial Port Implementation

Table 3-5 defines the pins and corresponding signals for the Serial A interface header (Serial Ports 1 and 2) and Table 3-6 defines the pins and corresponding signals for the Serial B interface header (Serial Ports 3 and 4).

Both Serial A and B headers use 20 pins, 2 rows, odd/even sequence (1, 2) with 0.100" (2.54mm) pitch.

Table 3-5. Serial A Interface Pin Signals (J11)

<table><tr><td>Pin #</td><td>Pin # DB9</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>1 (COM1)</td><td>DCD1*</td><td>Data Carrier Detect 1 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR1 as part of the DTR/DSR handshake.</td></tr><tr><td>2</td><td>6</td><td>DSR1*</td><td>Data Set Ready 1 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR1 for overall readiness to communicate.</td></tr><tr><td rowspan="2">3</td><td rowspan="2">2</td><td>RXD1</td><td>Receive Data 1 – Serial port 1 receive data in.</td></tr><tr><td>RX1-</td><td>RX1- – If in RS485 or RS422 mode, this pin is Receive Data 1 -.</td></tr><tr><td rowspan="2">4</td><td rowspan="2">7</td><td>RTS1*</td><td>Request To Send 1 – Indicates Serial port 1 is ready to transmit data. Used as hardware handshake with CTS1 for low level flow control.</td></tr><tr><td>TX1+</td><td>TX1+ – If in RS485 or RS422 mode, this pin is Transmit Data 1 +.</td></tr><tr><td rowspan="2">5</td><td rowspan="2">3</td><td>TXD1</td><td>Transmit Data 1 – Serial port 1 transmit data out.</td></tr><tr><td>TX1-</td><td>TX1- – If in RS485 or RS422 mode, this pin is Transmit Data 1 -.</td></tr><tr><td rowspan="2">6</td><td rowspan="2">8</td><td>CTS1*</td><td>Clear to Send 1 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS1 for low level flow control.</td></tr><tr><td>RX1+</td><td>RX1+ – If in RS485 or RS422 mode, this pin is Receive Data 1 -.</td></tr><tr><td>7</td><td>4</td><td>DTR1*</td><td>Data Terminal Ready 1 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR1 for overall readiness to communicate.</td></tr><tr><td>8</td><td>9</td><td>RI1*</td><td>Ring Indicator 1 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>9</td><td>5</td><td>GND</td><td>Ground</td></tr><tr><td rowspan="2">10</td><td rowspan="2">NC</td><td>KEY</td><td>Key</td></tr><tr><td>NC</td><td>Not connected</td></tr><tr><td>11</td><td>1 (COM2)</td><td>DCD2*</td><td>Data Carrier Detect 2 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR2 as part of the DTR/DSR handshake.</td></tr><tr><td>12</td><td>6</td><td>DSR2*</td><td>Data Set Ready 2 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR2 for overall readiness to communicate.</td></tr><tr><td rowspan="2">13</td><td rowspan="2">2</td><td>RXD2</td><td>Receive Data 2 – Serial port 2 receive data in.</td></tr><tr><td>RX2-</td><td>RX1- – If in RS485 or RS422 mode, this pin is Receive Data 1 -.</td></tr><tr><td rowspan="2">14</td><td rowspan="2">7</td><td>RTS2*</td><td>Request To Send 2 – Indicates Serial port 2 is ready to transmit data. Used as hardware handshake with CTS2 for low level flow control.</td></tr><tr><td>TX2+</td><td>TX2+ – If in RS485 or RS422 mode, this pin is Transmit Data 2 +.</td></tr><tr><td rowspan="2">15</td><td rowspan="2">3</td><td>TXD2</td><td>Transmit Data 2 – Serial port 2 transmit data out</td></tr><tr><td>TX2-CTS2*</td><td>TX2- – If in RS485 or RS422 mode, this pin is Transmit Data 2 -.Clear To Send 2 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS2 for low level flow control.</td></tr><tr><td rowspan="2">16</td><td rowspan="2">8</td><td></td><td></td></tr><tr><td>RX2+</td><td>RX2+ – If in RS485 or RS422 mode, this pin is Receive Data 2 -.</td></tr><tr><td>17</td><td>4</td><td>DTR2*</td><td>Data Terminal Ready 2 – Indicates Serial port 1 is powered, initialized, and ready. Used as hardware handshake with DSR2 for overall readiness to communicate.</td></tr><tr><td>18</td><td>9</td><td>RI2*</td><td>Ring Indicator 2 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>19</td><td>5</td><td>GND</td><td>Ground</td></tr><tr><td>20</td><td>NC</td><td>NC</td><td>Not connected</td></tr></table>

Note: The shaded table cells denote ground. Signals are listed in the table with RS232 first, followed by RS422/RS485. The \* symbol indicates the signal is Active Low.

Note: The shaded table cells denote ground. Signals are listed in the table with RS232 first, followed by RS485/RS422. The \* symbol indicates the signal is Active Low.
Table 3-6. Serial B Interface Pin Signals (J12)

<table><tr><td>Pin #</td><td>Pin #DB9</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>1(COM3)</td><td>DCD3*</td><td>Data Carrier Detect 3 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR3 as part of the DTR/DSR handshake.</td></tr><tr><td>2</td><td>6</td><td>DSR3*</td><td>Data Set Ready 3 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR3 for overall readiness to communicate.</td></tr><tr><td rowspan="2">3</td><td rowspan="2">2</td><td>RXD3</td><td>Receive Data 3 – Serial port 3 receive data in</td></tr><tr><td>RX3-</td><td>RX3- – If in RS485 or RS422 mode, this pin is Receive Data 3 -.</td></tr><tr><td rowspan="2">4</td><td rowspan="2">7</td><td>RTS3*</td><td>Request To Send 3 – Indicates Serial port 3 is ready to transmit data. Used as hardware handshake with CTS3 for low level flow control.</td></tr><tr><td>TX3+</td><td>TX3+ – If in RS485 or RS422 mode, this pin is Transmit Data 3 +.</td></tr><tr><td rowspan="2">5</td><td rowspan="2">3</td><td>TXD3</td><td>Transmit Data 3 – Serial port 3 transmit data out</td></tr><tr><td>TX3-</td><td>TX3- – If in RS485 or RS422 mode, this pin is Transmit Data 3 -.</td></tr><tr><td rowspan="2">6</td><td rowspan="2">8</td><td>CTS3*</td><td>Clear To Send 3 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS3 for low level flow control.</td></tr><tr><td>RX3+</td><td>RX3+ – If in RS485 or RS422 mode, this pin is Receive Data 3 -.</td></tr><tr><td>7</td><td>4</td><td>DTR3*</td><td>Data Terminal Ready 3 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR3 for overall readiness to communicate.</td></tr><tr><td>8</td><td>9</td><td>RI3*</td><td>Ring Indicator 3 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>9</td><td>5</td><td>GND</td><td>Ground</td></tr><tr><td>10</td><td>NC</td><td>KEY</td><td>Not Connected</td></tr><tr><td>11</td><td>1 (COM4)</td><td>DCD4*</td><td>Data Carrier Detect 4 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR4 as part of the DTR/DSR handshake.</td></tr><tr><td>12</td><td>6</td><td>DSR4*</td><td>Data Set Ready 4 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR4 for overall readiness to communicate.</td></tr><tr><td rowspan="2">13</td><td rowspan="2">2</td><td>RXD4</td><td>Receive Data 4 – Serial port 4 receive data in</td></tr><tr><td>RX4-</td><td>RX4- – If in RS485 or RS422 mode, this pin is Receive Data 4 -.</td></tr><tr><td rowspan="2">14</td><td rowspan="2">7</td><td>RTS4*</td><td>Request To Send 4 – Indicator to serial output port 4 is ready to transmit data. Used as hardware handshake with CTS4 for low level flow control.</td></tr><tr><td>TX4+</td><td>TX4+ – If in RS485 or RS422 mode, this pin is Transmit Data 4 +.</td></tr><tr><td rowspan="2">15</td><td rowspan="2">3</td><td>TXD4</td><td>Transmit Data 4 – Serial port 4 transmit data out</td></tr><tr><td>TX4-</td><td>TX4- – If in RS485 or RS422 mode, this pin is Transmit Data 4 -.</td></tr><tr><td rowspan="2">16</td><td rowspan="2">8</td><td>CTS4*</td><td>Clear To Send 4 – Indicator to serial port 4 that external serial communications device is ready to receive data. Used as hardware handshake with RTS4 for low level flow control.</td></tr><tr><td>RX4+</td><td>RX4+ – If in RS485 or RS422 mode, this pin is Receive Data 4 +.</td></tr><tr><td>17</td><td>4</td><td>DTR4*</td><td>Data Terminal Ready 4 – Indicates this Serial port is powered, initialized, and ready. Used as hardware handshake with DSR4 for overall readiness to communicate.</td></tr><tr><td>18</td><td>9</td><td>RI4*</td><td>Ring Indicator 4 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>19</td><td>5</td><td>GND</td><td>Ground</td></tr><tr><td>20</td><td>NC</td><td>NC</td><td>Not connected</td></tr></table>

# Utility Interfaces

The Utility interfaces consist of two headers that provide the standard interface signals for the following devices:

• Utility 1 (J15)

♦ PS/2 Keyboard
+ External battery
▲ Reset Switch
Power-On LED
♦ Speaker

• Utility 2 (J13)

PS/2 Mouse
♦ SMBus
♦ Power button

# Utility 1 Interface

The Utility 1 (J15) interface routes various signals to devices such as keyboard, speaker, battery, power-on LED, and reset switch. Table 3-7 defines the pin signals for the J15, Utility 1 header, which consists of 16 pins, 2 rows, odd/even (1, 2) sequence with 0.100" (2.54mm) pitch and provides the following functions.

# Keyboard

The signal lines for a PS/2 keyboard are provided through the Utility 1 interface, which is also fully PC/AT compatible.

# External Battery

An external battery input connection is provided through the Utility 1 interface as well as the J35 header to support the Real Time Clock in the event the on-board battery is not used.

# Power-On LED

The power-on LED signal provides +3.3 volts power for an external LED that indicates the system is powered on.

# Reset Switch

The signal lines for a reset switch are provided through the Utility 1 interface as well as through the J46 Power Button header.

NOTE To perform the equivalent of a power-on reset, the reset button must be pressed and held for a minimum of four seconds.

# Speaker

The signal lines for a speaker port with 0.1-watt drive are provided through the Utility 1 interface.

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.
Table 3-7. Utility 1 Interface Pin Signals (J15)

<table><tr><td>Pin #</td><td>Signal</td><td>I/O</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>-</td><td>Not connected (-12V Power)</td></tr><tr><td>2</td><td>GND</td><td>-</td><td>Ground</td></tr><tr><td>3</td><td>NC</td><td>-</td><td>Not connected (-5V Power)</td></tr><tr><td>4</td><td>GND</td><td>-</td><td>Ground</td></tr><tr><td>5</td><td>LED</td><td>O</td><td>Power-On LED – This on-board +3.3 volts is provided through 330 ohm resistor to an external Power-On LED.</td></tr><tr><td>6</td><td>NC</td><td>-</td><td>Not connected (Power Good)</td></tr><tr><td>7</td><td>SPKR+</td><td>O</td><td>+ Speaker Output – This signal drives external PC "Beep" speaker.</td></tr><tr><td>8</td><td>GND</td><td>-</td><td>Ground</td></tr><tr><td>9</td><td>RSTSW*</td><td>I/O</td><td>Reset Switch – This signal is provided for an external reset switch.</td></tr><tr><td>10</td><td>NC</td><td>-</td><td>Not connected (Keyboard Switch)</td></tr><tr><td>11</td><td>KBDATA</td><td>I/O</td><td>Keyboard Data – Data signal provided to external keyboard connector.</td></tr><tr><td>12</td><td>KBCLK</td><td>I/O</td><td>Keyboard Clock – Clock signal provided to external keyboard connector.</td></tr><tr><td>13</td><td>GND</td><td>-</td><td>Keyboard Ground</td></tr><tr><td>14</td><td>KBDPWR</td><td>-</td><td>Keyboard Power – This +5 volts is provided to external keyboard connector. Requires external fuse for keyboard/mouse protection.</td></tr><tr><td>15</td><td>BATV+</td><td>-</td><td>Backup Battery – This connection provides an additional backup battery from an external source. It can also be used in place of the on-board backup battery, B1, shipped with all LittleBoard 735s. Each RTS battery input is protected with a zener diode.</td></tr><tr><td>16</td><td>BATV-</td><td>-</td><td>Battery - Return (Grounded)</td></tr></table>

# Utility 2 Interface

The Utility 2 (J13) interface routes various signals to devices such as a mouse or power button. Table 3-9 defines the pin signals of the J13, Utility 2 interface header, which consists of 24 pins, 2 rows, odd/even (1, 2) pin sequence with 0.100" (2.54mm) pitch and provides the following functions.

# System Management Bus (SMBus)

The ICH7-M, I/O Hub, 82801GBM (Southbridge), contains both a host and slave SMBus port, but the host cannot access the slave internally. The slave port allows an external master access to the I/O Hub through the Utility 2 header (J13) as well as the J45 SMBus header. The master contained in the 82801GBM is used to communicate with the DDR2 SODIMM and the clock generator. Table 3-8 lists the corresponding binary addresses of these devices on the SMBus.

Table 3-8. SMBus Reserved Addresses

<table><tr><td>Component</td><td>Address Binary</td></tr><tr><td>DDR2 SODIMM</td><td> $1010,000x_b$ </td></tr><tr><td>Clock Generator (9LPRS501)</td><td> $1101,001x_b$ </td></tr><tr><td>I/O Hub (82801GBM)</td><td> $0000,000x_b$  (default) Programmable Master</td></tr></table>

# Mouse

The signal lines for a PS/2 mouse are provided through the Utility 2 interface (J13).

# Power Button

A power button can be connected to the board through the Utility 2 interface as well as through the J46 Power Button header. Press and hold the green button on the power button cable for at least four seconds to power off the system. To power on the system, press and release the green button and wait for the system to boot.

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.
Table 3-9. Utility 2 Interface Pin Signals (J13)

<table><tr><td>Pin #</td><td>Signal</td><td>I/O</td><td>Description</td></tr><tr><td>1</td><td>NC</td><td>-</td><td>Not connected (Lid Switch)</td></tr><tr><td>2</td><td>PWRBT*</td><td>I</td><td>Power Button – This signal allows the user to turn off and on the power supply from an external switch.</td></tr><tr><td>3</td><td>BATLOW*</td><td>I</td><td>Battery Low – This signal from an external battery indicates to the I/O Hub there is insufficient power to boot the system.</td></tr><tr><td>4</td><td>NC</td><td>-</td><td>Not connected (IR Mode select)</td></tr><tr><td>5</td><td>NC</td><td>-</td><td>Not connected (IR Transmit Data)</td></tr><tr><td>6</td><td>NC</td><td>-</td><td>Not connected (IR Receive Data)</td></tr><tr><td>7</td><td>GND</td><td>-</td><td>Ground</td></tr><tr><td>8</td><td>VCC</td><td>-</td><td>+5 Volts</td></tr><tr><td>9</td><td>MDATA</td><td>I/O</td><td>Mouse Data – Data signal provided to external mouse connector.</td></tr><tr><td>10</td><td>MCLK</td><td>I/O</td><td>Mouse Clock–Clock signal provided to external mouse connector</td></tr><tr><td>11</td><td>GND</td><td>-</td><td>Ground</td></tr><tr><td>12</td><td>VCC</td><td>-</td><td>+5 Volts</td></tr><tr><td>13</td><td>SMBCLK</td><td>I/O</td><td>SMBus Clock – Clock signal provided to external devices.</td></tr><tr><td>14</td><td>SMBDATA</td><td>I/O</td><td>SMBus Data – Data signal provided to external devices.</td></tr><tr><td>15</td><td>NC</td><td>-</td><td>Not connected (+5V USB Port Power)</td></tr><tr><td>16</td><td>NC</td><td>-</td><td>Not connected (+5V USB Port Power)</td></tr><tr><td>17</td><td>NC</td><td>-</td><td>Not connected (USB 0 Negative Data Signal)</td></tr><tr><td>18</td><td>NC</td><td>-</td><td>Not connected (USB 1 Negative Data Signal)</td></tr><tr><td>19</td><td>NC</td><td>-</td><td>Not connected (USB 0 Positive Data Signal)</td></tr><tr><td>20</td><td>NC</td><td>-</td><td>Not connected (USB 1 Positive Data Signal)</td></tr><tr><td>21</td><td>NC</td><td>-</td><td>Not connected (USB Port ground)</td></tr><tr><td>22</td><td>NC</td><td>-</td><td>Not connected (USB Port ground)</td></tr><tr><td>23</td><td>NC</td><td>-</td><td>Not connected [USB Port shield (Cable Shield)]</td></tr><tr><td>24</td><td>NC</td><td>-</td><td>Not connected [USB Port shield (Cable Shield)]</td></tr></table>

# USB Interfaces

The I/O Hub (82801GBM) provides the USB solution for both legacy UHCI controller (USB 1.1) and EHCI controller (USB 2.0) support. The I/O Hub (Southbridge) contains port-routing logic that determines which controller (UHCI or EHCI) handles the USB data signals. The J44 header provides two of the six USB ports: USB0 and USB1. The J14 header provides USB2 and USB3, and the J39 header provides USB4 and USB5.

# USB 2.0 Support

The I/O Hub (Southbridge) contains an Enhanced Host Controller Interface (EHCI) compliant host controller, which supports up to six high-speed USB 2.0 Specification compliant root ports. The higher speed USB 2.0 specification allows data transfers up to 480 Mbps using the same pins as the six full-speed/ low-speed USB UHCI ports. The I/O Hub (Southbridge) port-routing logic determines which of the controllers (UHCI or the EHCI) processes the USB signals.The USB 2.0 features implemented in the USB ports include the following:

One EHCI host controller for all six USB ports
Supports USB V2.0 Specification

# Legacy USB Support

The I/O Hub (Southbridge) supports three USB Universal Host Controller Interfaces (UHCI) and each Host Controller includes a root hub with two separate USB ports each, for a total of six USB ports. The USB Legacy features implemented in the USB ports include the following:

Three root hubs for six USB ports
Support for USB v1.1 and UHCI v1.1 with integrated physical layer transceivers
Improved arbitration latency for UHCI controllers
UHCI controllers support Analog Front End (AFE) embedded cell instead of USB I/O buffers to allow for USB high-speed signaling rates
Three shared over-current fuses, located on the board, are used on all six USB ports

# CAUTION

ADLINK does not recommend connecting a USB boot device to the LittleBoard 735 through an external hub. Instead, connect the USB boot device directly to the LittleBoard 735.

# USB0 and USB1

Table 3-10 lists the USB0 and USB1 pin signals which use 10 pins, 2 rows, odd/even sequence (1, 2) with 0.079" (2mm) pitch.

Table 3-10. USB 0 & 1 Interface Pin Signals (J44)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>USBPWR0</td><td>+5 volts power, USB 0</td></tr><tr><td>2</td><td>USBPWR1</td><td>+5 volts power, USB 1</td></tr><tr><td>3</td><td>USB0-</td><td>USB 0 Data Negative</td></tr><tr><td>4</td><td>USB1-</td><td>USB 1 Data Negative</td></tr><tr><td>5</td><td>USB0+</td><td>USB 0 Data Positive</td></tr><tr><td>6</td><td>USB1+</td><td>USB 1 Data Positive</td></tr><tr><td>7</td><td>USB GND0</td><td>USB 0 Ground</td></tr><tr><td>8</td><td>USB GND1</td><td>USB 1 Ground</td></tr><tr><td>9</td><td>USB GND0</td><td>USB 0 Ground</td></tr><tr><td>10</td><td>USB GND1</td><td>USB 1 Ground</td></tr></table>

Note: The shaded table cells denote power or ground.

# USB2 and USB3

Table 3-11 lists the USB2 and USB3 pin signals which use 10 pins, 2 rows, odd/even sequence (1, 2) with 0.079" (2mm) pitch.

Table 3-11. USB 2 & 3 Interface Pin Signals (J14)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>USBPWR2</td><td>+5 volts power, USB 2</td></tr><tr><td>2</td><td>USBPWR3</td><td>+5 volts power, USB 3</td></tr><tr><td>3</td><td>USB2-</td><td>USB 2 Data Negative</td></tr><tr><td>4</td><td>USB3-</td><td>USB 3 Data Negative</td></tr><tr><td>5</td><td>USB2+</td><td>USB 2 Data Positive</td></tr><tr><td>6</td><td>USB3+</td><td>USB 3 Data Positive</td></tr><tr><td>7</td><td>USB GND2</td><td>USB 2 Ground</td></tr><tr><td>8</td><td>USB GND3</td><td>USB 3 Ground</td></tr><tr><td>9</td><td>USB GND2</td><td>USB 2 Ground</td></tr><tr><td>10</td><td>USB GND3</td><td>USB 3 Ground</td></tr></table>

Note: The shaded table cells denote power or ground.

# USB4 and USB5

Table 3-12 lists the USB4 and USB5 pin signals which use 10 pins, 2 rows, odd/even sequence (1, 2) with 0.079" (2mm) pitch.
Table 3-12. USB 4 & 5 Interface Pin Signals (J39)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>USBPWR4</td><td>+5 volts power, USB 4</td></tr><tr><td>2</td><td>USBPWR5</td><td>+5 volts power, USB 5</td></tr><tr><td>3</td><td>USB4-</td><td>USB 4 Data Negative</td></tr><tr><td>4</td><td>USB5-</td><td>USB 5 Data Negative</td></tr><tr><td>5</td><td>USB4+</td><td>USB 4 Data Positive</td></tr><tr><td>6</td><td>USB5+</td><td>USB 5 Data Negative</td></tr><tr><td>7</td><td>USB GND4</td><td>USB 4 Ground</td></tr><tr><td>8</td><td>USB GND5</td><td>USB 5 Ground</td></tr><tr><td>9</td><td>USB GND4</td><td>USB 4 Ground</td></tr><tr><td>10</td><td>USB GND5</td><td>USB 5 Ground</td></tr></table>

Note: The shaded table cells denote power or ground.

# Audio Interface

The audio solution on the LittleBoard 735 is provided by the Realtek ALC203-LF audio CODEC. The chip is defined by AC97 and is revision 2.2 compliant. The audio interface signals are supplied to the 26-pin 2mm connector (J9). Refer to the following list for the Audio CODEC (ALC203-LF) features.

Analog Mixer Dynamic Range 97dB (typ)
D/A Dynamic Range 89dB (typ) and A/D Dynamic Range 90dB (typ)
AC’97 Rev 2.1 compliant
High quality Sample Rate Conversion (SRC) from 4kHz to 48kHz
• 3D Sound circuitry and PC-Beep passthrough to Line Out while reset is held active low
True Line Level Output with volume control independent of Line Out

Note: The shaded table cells denote power or ground.
Table 3-13 describes the pin signals of the audio interface which uses 26 pins, 2 rows, odd/even sequence (1, 2) with 0.079" (2mm) pitch.
Table 3-13. Audio Interface Pin Signals (J9)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>AUX_L</td><td>Auxiliary Audio I/O signal left channel</td></tr><tr><td>2</td><td>AUX_GND</td><td>Auxiliary Audio ground</td></tr><tr><td>3</td><td>VIDEO_R</td><td>Video Audio I/O signal right channel</td></tr><tr><td>4</td><td>CD_L</td><td>CD-ROM signal left channel</td></tr><tr><td>5</td><td>CD_GND</td><td>CD-ROM Audio ground</td></tr><tr><td>6</td><td>CD_R</td><td>CD-ROM signal right channel</td></tr><tr><td>7</td><td>LINE_IN_L</td><td>Line In signal left channel</td></tr><tr><td>8</td><td>LINE_IN_GND</td><td>Line In Audio ground</td></tr><tr><td>9</td><td>LINE_IN_R</td><td>Line In signal right channel</td></tr><tr><td>10</td><td>MIC1</td><td>Microphone In signal 1 or left channel</td></tr><tr><td>11</td><td>MIC_GND</td><td>Microphone Audio ground</td></tr><tr><td>12</td><td>MIC2</td><td>Microphone In signal 2 or right channel</td></tr><tr><td>13</td><td>MIC_REF</td><td>Microphone reference signal</td></tr><tr><td>14</td><td>NC/KEY</td><td>Not Connected - Key</td></tr><tr><td>15</td><td>PHONE_IN</td><td>Phone signal In</td></tr><tr><td>16</td><td>PHONE_GND</td><td>Phone Audio ground</td></tr><tr><td>17</td><td>MONO_OUT</td><td>Monaural signal Out</td></tr><tr><td>18</td><td>MONO_GND</td><td>Monaural Audio ground</td></tr><tr><td>19</td><td>+AOUT_L</td><td>+ Audio Out signal Left channel</td></tr><tr><td>20</td><td>-AOUT_L</td><td>- Audio Out Left ground</td></tr><tr><td>21</td><td>+AOUT_R</td><td>+ Audio Out signal Right channel</td></tr><tr><td>22</td><td>-AOUT_R</td><td>- Audio Out Right ground</td></tr><tr><td>23</td><td>GND</td><td>Audio Ground (tied to all audio grounds)</td></tr><tr><td>24</td><td>HP_L</td><td>Headphone signal Left channel</td></tr><tr><td>25</td><td>HP_R</td><td>Headphone signal Right channel</td></tr><tr><td>26</td><td>NC</td><td>Not Connected (Headphone In)</td></tr></table>

# Video Interfaces

The 82945GSE chip provides the graphics control and video signals for traditional glass CRT monitors and LCD flat panel displays. The chip features are listed below:

# VGA features:

Support for an integrated 400-MHz, 24-bit RAMDAC to drive a progressive scan analog monitor and outputs to three, 8-bit DACs that provide the R, G, and B signals to the monitor
Support for resolutions up to QXGA (2048x1536)
Support for a maximum allowable video frame buffer size of 224MB UMA (Unified Memory Architecture)

# LVDS Flat Panel features:

Support for an integrated dual channel LFP Transmitter interface
Support for LVDS LCD panel resolutions up to UXGA(1600X1200)
Support for a maximum pixel format of 18 bpp with SSC supported frequency range from 25 MHz to 112 MHz (single channel/dual channel)

# TV Out features:

Support for three integrated 10-bit DACS
Support for overscaling
Provide NTSC/PAL
Provide component, s-video, and composite output interfaces
Support HDTV: 480p/720p/1080i/1080p

# VGA Interface

Table 3-14 describes the pin signals of the VGA interface, which uses 12 pins, 2 rows, odd/even sequence (1, 2) with 0.079" (2mm) pitch.
Table 3-14. VGA Interface Pin Signals (J3)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>RED</td><td>Red – This is the Red analog output signal to the CRT.</td></tr><tr><td>2</td><td>GND</td><td>Ground (Red Return)</td></tr><tr><td>3</td><td>GREEN</td><td>Green – This is the Green analog output signal to the CRT.</td></tr><tr><td>4</td><td>GND</td><td>Ground (Green Return)</td></tr><tr><td>5</td><td>BLUE</td><td>Blue – This is the Blue analog output signal to the CRT.</td></tr><tr><td>6</td><td>GND</td><td>Ground (Blue Return)</td></tr><tr><td>7</td><td>HSYNC</td><td>Horizontal Sync – This signal is used for the digital horizontal sync output to the CRT.</td></tr><tr><td>8</td><td>GND</td><td>Ground</td></tr><tr><td>9</td><td>VSYNC</td><td>Vertical Sync – This signal is used for the digital vertical sync output to the CRT.</td></tr><tr><td>10</td><td>PWR</td><td>Power – Provided through fuse (F1) to +5 volts +/- 5%. F1 is next to J3 connector on board.</td></tr><tr><td>11</td><td>SDA</td><td>DDC (Display Data Channel) Data</td></tr><tr><td>12</td><td>SCL</td><td>DDC (Display Data Channel) Clock</td></tr></table>

Note: The shaded table cells denote power or ground.

# LVDS Interface

Note: The shaded table cells denote power or ground.
Table 3-15 describes the pin signals of the LVDS interface, which provides a 30-pin header with 2 rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch.
Table 3-15. LVDS Interface Pin Signals (J26)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td><td>Line</td><td>Channel</td></tr><tr><td>1</td><td>+12V</td><td>+12 volt input</td><td rowspan="4">NA</td><td rowspan="4">NA</td></tr><tr><td>2</td><td>+VCC (+3.3V/+5V)</td><td>JP1 determines voltage on pin</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>GND</td><td>Ground</td></tr><tr><td>5</td><td>LBCLK_P</td><td>Clock Positive Output</td><td rowspan="2">Clock</td><td rowspan="10">Channel 2</td></tr><tr><td>6</td><td>LBCLK_N</td><td>Clock Negative Output</td></tr><tr><td>7</td><td>Not Supported</td><td>N/A</td><td rowspan="2">N/S</td></tr><tr><td>8</td><td>Not Supported</td><td>N/A</td></tr><tr><td>9</td><td>LBDATA2_P</td><td>Data Positive Output</td><td rowspan="2">2</td></tr><tr><td>10</td><td>LBDATA2_N</td><td>Data Negative Output</td></tr><tr><td>11</td><td>LBDATA1_P</td><td>Data Positive Output</td><td rowspan="2">1</td></tr><tr><td>12</td><td>LBDATA1_N</td><td>Data Negative Output</td></tr><tr><td>13</td><td>LBDATA0_P</td><td>Data Positive Output</td><td rowspan="2">0</td></tr><tr><td>14</td><td>LBDATA0_N</td><td>Data Negative Output</td></tr><tr><td>15</td><td>LVDS_BKLT_CTL</td><td>Control Panel Backlight</td><td>NA</td><td>NA</td></tr><tr><td>16</td><td>LVDD_EN</td><td>Enable Panel Power</td><td>NA</td><td>NA</td></tr><tr><td>17</td><td>LACLK_P</td><td>Clock Positive Output</td><td rowspan="2">Clock</td><td rowspan="4">Channel 1</td></tr><tr><td>18</td><td>LACLK_N</td><td>Clock Negative Output</td></tr><tr><td>19</td><td>Not Supported</td><td>N/A</td><td rowspan="2">N/S</td></tr><tr><td>20</td><td>Not Supported</td><td>N/A</td></tr><tr><td>21</td><td>LADATA2_P</td><td>Data Positive Output</td><td rowspan="2">2</td><td rowspan="6"></td></tr><tr><td>22</td><td>LADATA2_N</td><td>Data Negative Output</td></tr><tr><td>23</td><td>LADATA1_P</td><td>Data Positive Output</td><td rowspan="2">1</td></tr><tr><td>24</td><td>LADATA1_N</td><td>Data Negative Output</td></tr><tr><td>25</td><td>LADATA0_P</td><td>Data Positive Output</td><td rowspan="2">0</td></tr><tr><td>26</td><td>LADATA0_N</td><td>Data Negative Output</td></tr><tr><td>27</td><td>L_DDC_CLK</td><td>Display Data Channel Clock</td><td>NA</td><td>NA</td></tr><tr><td>28</td><td>L_DDC_DAT</td><td>Display Data Channel Data</td><td>NA</td><td>NA</td></tr><tr><td>29</td><td>LVDS_BKLT_EN</td><td>Enable Backlight Inverter</td><td>NA</td><td>NA</td></tr><tr><td>30</td><td>NC</td><td>Not Connected</td><td>NA</td><td>NA</td></tr></table>

NOTE Pins 5-14 constitute $2 ^ { \mathrm { n d } }$ channel interface of two channels. Pins 15-26 constitute $1 ^ { \mathrm { s t } }$ channel interface of two channels, or a single channel interface.

# TV-Out Interface

Table 3-16 describes the pin signals of the TV-Out interface, which provides a 6-pin header with 2 rows, odd/even sequence (1, 2), and 0.100" (2.54mm) pitch.

Table 3-16. TV-Out Pin Signals (J36)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>TVDAC A</td><td>TVDAC Channel A Output:TVDAC_A supports the following:Composite: CVBS signalComponent: Chrominance (Pb) analog signal</td></tr><tr><td>2</td><td>TV_GND</td><td>Ground</td></tr><tr><td>3</td><td>TVDAC B</td><td>TVDAC Channel B Output:TVDAC_B supports the following:S-Video: Luminance analog signalComponent: Luminance (Y) analog signal</td></tr><tr><td>4</td><td>TV_GND</td><td>Ground</td></tr><tr><td>5</td><td>TVDAC C</td><td>TVDAC Channel C Output:TVDAC_C supports the following:S-Video: Chrominance analog signalComponent: Chrominance (Pr) analog signal</td></tr><tr><td>6</td><td>TV_GND</td><td>Ground</td></tr></table>

Note: The shaded table cells denote ground.

# Power Interfaces

# Power-In Interface

The LittleBoard 735 derives all of its onboard voltages from an external DC power supply through the J10 Power-In header and requires only +5 volts for operation.

Table 3-17 lists the pin signals for the J19 power-in interface, which provides a 7-pin, single-row header with 0.156" (3.96mm) pitch.

Table 3-17. Power-In Interface Pin Signals (J19)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>+5V</td><td>+5.0 Volts – This +5.0 volts DC +/- 5% is the only voltage required for operation.</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+12V</td><td>+12 Volts – This +12 volts is for the PC/104, PC/104-Plus, and LVDS power only.</td></tr><tr><td>5</td><td>+3.3V</td><td>+3.3 Volts – This +3.3 volts is for PC/104-Plus Bus power only (optional).</td></tr><tr><td>6</td><td>GND</td><td>Ground</td></tr><tr><td>7</td><td>+5V</td><td>+5.0 Volts – This +5.0 volts DC +/- 5% is the only voltage required for operation.</td></tr></table>

Note: The shaded table cells denote power or ground.

# ATX Power-On Interface

This 3-pin header (J30) provides ATX control of the power supply.

Table 3-18 lists the pin signals for the ATX Power-On interface, which provides a 3-pin, single-row header with 0.100" (2.54mm) pitch.

Table 3-18. ATX Power-On Interface Pin Signals (J30)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>PS_ON*</td><td>Power Supply On – This signal provides the LittleBoard 735 ATX control of the power supply.</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>VCC5_ATX_STBY</td><td>+5V Standby (+5V, 500mA) – This voltage is supplied from the ATX power supply and is required for ATX operation.</td></tr></table>

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.

# Power Button and Reset Switch Interface

A power button signal is provided by connecting ground to pin-1 on this header (J46). A hardware reset switch signal is provided by connecting ground to pin 3 on this header. Press and hold the green button on the power button cable for at least four seconds to power off the system. To power on the system, press and release the green button and wait for the system to boot. To perform a hardware reset, press and release the red button on the power button cable.

Table 3-19 lists the pin signals for the J46 Power Button and Reset Switch interface, which provides a 5-pin, single-row header with 0.100" (2.54mm) pitch.

Note: The shaded table cell denotes power or ground. The \* symbol indicates the signal is Active Low.
Table 3-19. Power Button Interface Pin Signals (J46)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>PWRBTN*</td><td>Power Button input (connect between pins 1 &amp; 2)</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>RST_SW*</td><td>Reset Switch input or output (connect between pins 3 &amp; 2)</td></tr><tr><td>4</td><td>NC</td><td>Not Connected</td></tr><tr><td>5</td><td>NC</td><td>Not Connected</td></tr></table>

# Miscellaneous

# Real Time Clock (RTC)

The ICH7-M Southbridge contains a Real Time Clock (RTC) with 256 bytes of battery-backed memory. If the battery is not present, the BIOS provides a battery-free boot option to complete the boot process. Under these conditions all setup information is restored from flash memory during POST along with the default date and time information.

NOTE Some operating systems require a valid default date and time to function.

# Temperature Monitoring

The Intel Atom processor supports the THERMTRIP# signal for catastrophic thermal protection. The THERMTRIP# is an open drain signal from the processor which is used to shut down the processor core voltage. This signal is connected to the THERMTRIP# input signal and indicates that a thermal trip from the processor occurred and the ICH7-M will immediately transition to the S5 state.

NOTE The LittleBoard 735 requires a heatsink for the Atom N270 processor.

# User GPIO Signals

The LittleBoard 735 provides GPIO pins for custom use. The signals are routed to the J40 header, and the Enable and Initialize values are set in the BIOS. An example of how to use the GPIO pins resides in the Miscellaneous Source Code Examples on the LittleBoard 735 Support Software QuickDriveTM.

The example program can be built by using the make.bat file. This produces a 16-bit DOS executable application, gpio.exe, which can be run on the LittleBoard 735 to demonstrate the use of GPIO pins. For more information about the GPIO pin operation, refer to the Programming Manuals for the Southbridge (82801GBM) and Super I/O (SCH3114I-NU) controllers at:

http://www.intel.com/assets/pdf/datasheet/307013.pdf

http://www.smsc.com/main/catalog/sch311x.html

Table 3-20 lists the pin signals for the J40 GPIO interface, which provides a 10-pin header with two rows, odd/even sequence, and 0.079" (2mm) pitch.

Note: The shaded table cells denote power or ground.
Table 3-20. User GPIO Pin Signals (J40)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>VCC</td><td>+3.3 Volts DC  $\pm$  5%</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>GPIO</td><td>User defined</td></tr><tr><td>4</td><td>GPO0</td><td>User defined</td></tr><tr><td>5</td><td>GPI1</td><td>User defined</td></tr><tr><td>6</td><td>GPO1</td><td>User defined</td></tr><tr><td>7</td><td>GPI2</td><td>User defined</td></tr><tr><td>8</td><td>GPO2</td><td>User defined</td></tr><tr><td>9</td><td>GPI3</td><td>User defined</td></tr><tr><td>10</td><td>GPO3</td><td>User defined</td></tr></table>

# SMBus Interface

Compatible with most I2C devices, this interface allows the processor to communicate with SMBus slave peripherals through the Host SMBus controller on the ICH7-M.

Table 3-21 lists the pin signals for the SMBus interface (J45), which provides a 5-pin, single-row header with 0.49" pitch.

Table 3-21. SMBus Pin Signals (J45)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>SCL</td><td>SMBus Clock Reset</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>SDA</td><td>SMBus Data Reset</td></tr><tr><td>4</td><td>VCC</td><td>+3.3 Volts DC +/- 5%</td></tr><tr><td>5</td><td>ALERT</td><td>SMBus Alert</td></tr></table>

Note: The shaded table cells denote power or ground.

# Oops! Jumper (BIOS Recovery)

The Oops! jumper is provided in the event the BIOS settings you have selected prevent you from booting the system. By using the Oops! jumper you can prevent the current BIOS settings in the EEPROM from being loaded, forcing the use of the default settings. Connect the DTR pin to the RI pin on serial port 1 (COM 1) prior to boot up to prevent the present BIOS settings from loading. After booting with the Oops! jumper in place, remove the Oops! jumper and go into BIOS Setup. Change the desired BIOS settings, or select the default settings, and save changes before rebooting the system.

To convert the Serial A interface to an Oops! jumper, short together the DTR (7) and RI (8) pins on the Serial A (J11) header for Serial Port 1. As an alternate, short the equivalent pins, 4 and 9, on the Serial Port 1 DB9 connector as shown in Figure 3-2.

![Serial A Interface (J11)\nfor Serial Port 1\n(or COM1 Port)\nTop View\n19 9 7 5 3 1\n20 10 8 6 4 2\nOr Standard DB9 Serial\nPort Connector (Male)\nFront View\n1 2 3 4 5\n6 7 8 9\nLB735OpsJumper_b](.50-1z020-1020-lb735-refman-final-en/646e8770ca5f2cd95753037d571216851a1dc3b96772fec86dd997a4cd34fa20.jpg)

Figure 3-2. Oops! Jumper Connection

# Remote Access

The LittleBoard 735 supports the remote access (or console redirection) feature. This I/O function is provided by an ANSI-compatible serial terminal, or the equivalent terminal emulation software running on another system. This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display.

# Remote Access Setup

The remote access feature is implemented by connecting a standard null modem cable or modified serial cable (or “Hot Cable”) between one of the serial ports, such as Serial 1 (J11A) and the serial terminal, or a PC with communications software. The BIOS Setup Utility controls the remote access settings on the LittleBoard 735. Refer to Chapter 4, BIOS Setup for the settings of the remote access option, the serial terminal, or PC with communications software and the connection procedure.

# Hot (Serial) Cable

To convert a standard serial cable to a Hot Cable, specific pins must be shorted together at the Serial port connector or at the DB9 cable connector. For example, short the RTS (7) and RI (9) at the rear of the respective DB9 cable connector as shown in Figure 3-3.

![Standard DB9 Cable\nConnector (Female)\nRear View\n5 4 3 2 1\n9 8 7 6\nLB735Hotcable](.50-1z020-1020-lb735-refman-final-en/47ad7e3f779e6a9c3ed3dbddbe8ec1248528947457e36552e720ad9b88a28326.jpg)

Figure 3-3. Hot Cable Jumper

# Watchdog Timer

The Watchdog Timer (WDT) restarts the system if a mishap occurs, ensuring proper start-up after the interruption. Possible problems include failure to boot properly, the application software’s loss of control, failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions.

The WDT (Watchdog Timer) can be used both during the boot process and during normal system operation.

During the Boot process – If the operating system fails to boot in the time interval set in the BIOS, the system will reset.

Enable the WDT in Boot Settings Configuration of BIOS Setup. Set the WDT for a time-out interval in seconds, between 1 and 255, in one-second increments in the Boot Setting Configuration screen. Ensure you allow enough time for the boot process to complete and for the OS to boot. The OS or application must tickle the WDT as soon as it comes up. This can be done by accessing the hardware directly or through a BIOS call.

During System Operation – An application can set up the WDT hardware through a BIOS call, or by accessing the hardware directly. Some ADLINK Board Support Packages provide an API interface to the WDT. The application must tickle the WDT in the time set when the WDT is initialized or the system will be reset. You can use a BIOS call to tickle the WDT or access the hardware directly.

The BIOS implements interrupt 15 function 0C3h to manipulate the WDT.

Watchdog Code examples – ADLINK has provided source code examples on the LittleBoard 735 Support Software QuickDrive illustrating how to control the WDT. The code examples can be easily copied to your development environment to compile and test the examples, or make any desired changes before compiling. Refer to the WDT Readme file on the LittleBoard 735 Support Software QuickDrive.

# Optional CPU Fan

Table 3-22 lists the pin signals of the optional CPU Fan interface, which provides a 3-pin, single-row header with 0.100" (2.54mm) pitch.

# CAUTION

The voltage to the fan should not exceed 130mA on the LB-735-R-18 model and 250mA on the LB-735-P-18 and LB-735-F-18 models or significant damage to the board may occur. See the LittleBoard 735 Hardware Release Notes for more details.

Table 3-22. Optional CPU Fan (J34)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>Fan_Tach</td><td>Fan Tachometer – This signal monitors the fan speed</td></tr><tr><td>2</td><td>VCC</td><td>+5.0 volts DC +/- 5%</td></tr><tr><td>3</td><td>GND</td><td>Ground and Modulation – This signal controls the fan speed</td></tr></table>

Note: The shaded table cells denote power or ground.

# GLAN1 LED

Table 3-23 lists the pin signals of the J47, external GLAN1 LED interface, which provides a 5-pin, single-row header with 0.049" (1.24mm) pitch.

Table 3-23. Ethernet External LED Pin Signal Descriptions (J47)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>+V3.3_S5</td><td>+3.3 Volts Ethernet Power</td></tr><tr><td>2</td><td>ACT_LED1*</td><td>Ethernet Activity</td></tr><tr><td>3</td><td>SPEED_LED1*</td><td>Ethernet Speed</td></tr><tr><td>4</td><td>LINK1000_LED1*</td><td>Ethernet Connection</td></tr><tr><td>5</td><td>GND</td><td>Ethernet Ground</td></tr></table>

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.

# GLAN2 LED

Table 3-23 lists the pin signals of the J48, external GLAN2 LED interface, which provides a 5-pin, single-row header with 0.049" (1.24mm) pitch. .

Table 3-24. Ethernet External LED Pin Signal Descriptions (J48)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>+V3.3_S5</td><td>+3.3 Volts Ethernet Power</td></tr><tr><td>2</td><td>ACT_LED2*</td><td>Ethernet Activity</td></tr><tr><td>3</td><td>SPEED_LED2*</td><td>Ethernet Speed</td></tr><tr><td>4</td><td>LINK1000_LED2*</td><td>Ethernet Connection</td></tr><tr><td>5</td><td>GND</td><td>Ethernet Ground</td></tr></table>

Note: The shaded table cells denote power or ground. The \* symbol indicates the signal is Active Low.

# Battery Input

Table 3-25 lists the pin signals of the External Battery Input interface, which provides a 2-pin, single-row header with 0.049" (1.24mm) pitch.
Table 3-25. External Battery Input Header (J35)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>VCC</td><td>+5.0 volts DC +/- 5%</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded table cells denote power or ground.

# Introduction

This chapter assumes the user is familiar with general BIOS Setup and does not attempt to describe the BIOS functions. Refer to “BIOS Setup Menus” on page 47 in this chapter for a map of the BIOS Setup settings. If ADLINK has added to or modified any of the standard BIOS functions, these functions will be described.

# Entering BIOS Setup (Local Video Display)

To enter BIOS Setup using a local video display for the LittleBoard 735:

1. Turn on the display and the power supply to the LittleBoard 735.
2. Start Setup by pressing the [Del] key when the following message appears on the AMI boot screen.

Press DEL to run Setup

NOTE If the setting for Quick Boot is [Enabled], you may not see this prompt appear on screen. If this happens, press the [Del] key earlier in the boot sequence to enter BIOS Setup.

3. Follow the instructions on the right side of the screen to navigate through the selections and modify any settings.

# Entering BIOS Setup (Remote Access)

This section describes how to enable the Remote Access in VGA mode and enter the BIOS setup through a serial terminal or PC.

1. Turn on the power supply to the LittleBoard 735 and enter the BIOS Setup Utility in VGA mode.
2. Set the BIOS feature Remote Access to [Enabled] under the Advanced menu.
3. Accept the default options or make your own selections for the balance of the Remote Access fields and record your settings.
4. Ensure you select the type of remote serial terminal you will be using and record your selection.
5. Select Save Changes and Exit and then shut down the LittleBoard 735.
6. Connect the remote serial terminal (or the PC with communications software) to the COM port you selected and recorded earlier in the BIOS Setup Utility.
7. Turn on the remote serial terminal or PC and set it to the settings you selected in the BIOS Setup Utility. The default settings for the LittleBoard 735 are:

♦ [COM2] for Serial Port Number
[115200 8, n, 1] for Serial Port Mode
♦ [None] for Flow Control
♦ [Always] for Redirection After BIOS POST
♦ [ANSI] for Terminal Type
[Enabled] for VT-UTF8 Combo Key Support
♦ [No Delay] for Srdir Mem Display Delay

8. Restore power to the LittleBoard 735 and look for the screen prompt.
9. Press the Del key to enter Setup (early in the boot sequence if Quick Boot is set to [Enabled].)

If Quick Boot is set to [Enabled], you may never see the screen prompt.

10. Use the &lt;Enter&gt; key to select the screen menus listed in the Opening BIOS screen.

NOTE The serial console port is not hardware protected. Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions.

# PCI-to-ISA Bridge Mapping

The LittleBoard 735 supports ISA bus based modules with an on-board PCI-to-ISA bridge. The PCI-to-ISA bridge optionally maps the following resources to ISA based modules:

. IRQs
• DMA Channels

The LittleBoard 735 system BIOS, maps the above resources based on information provided in the BIOS Setup screens. By default, IRQs or DMA channels to be mapped to ISA modules must be explicitly specified by the user in the BIOS Setup screens.

The IRQs and DMA channels are mapped with the “PCIPnP/IRQx” fields in BIOS setup (where x specifies the IRQ number.) The IRQs 3, 4, 5, 7, 9, 10, 11, 14, and 15 can be mapped to ISA based modules by changing the default setting for these IRQs from “Available” to “Reserved”.

Any of the DMA channels 0, 1, 3, 5, 6, 7 can be mapped to ISA modules by changing the default setting of “Available” to “Reserved”.

# Logo Screen Utility (Splash Screen)

The LittleBoard 735 BIOS supports a graphical logo utility, which can be customized by the user and displayed when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any custom image the user wants to display during the boot process. The custom image can be displayed as the first image displayed on screen during the boot process and remain there, depending on the options selected in BIOS Setup, while the OS boots.

# Logo Screen Image Requirements

The user’s image may be customized with any standard image editing tool.

The LittleBoard 735 logo screen utility supports the following image formats:

• Bitmap image
Exactly 640 x 480 pixels
Exactly 16 colors
. Bitmap image
16-Color, 640x480 pixels
256-Color, 640x480 pixels
. JPG image
16-Color, 640x480 pixels
• PCX image
♦ 256-Color, 640x480 pixels

• A file size no larger than the sample image

# BIOS Setup Menus

This section provides illustrations of the seven main setup screens in the LittleBoard 735 BIOS Setup Utility. Below each illustration is a bullet list of the screen’s submenus and setting selections. The setting selections are presented in brackets after each submenu or menu item and the optimal default settings are presented in bold. For more detailed definitions of the BIOS settings, refer to the AMIBIOS8 manual: http://www.ami.com/support/doc/MAN-EZP-80.pdf

Table 4-1. BIOS Setup Menus

<table><tr><td>BIOS Setup Utility Menu</td><td>Item/Topic</td></tr><tr><td>Main Settings</td><td>Date and Time</td></tr><tr><td>Advanced Settings</td><td>CPU settings, IDE Drive Configurations, Floppy, Super I/O, Hardware Health, ACPI, APM, MPS, PCI Express, Smbios, Remote Access (Serial Console), USB Configuration, and PCI to ISA Bridge</td></tr><tr><td>PCIPnP (PCI, Plug n&#x27; Play)</td><td>PCI settings, Plug &amp; Play settings, Interrupt settings, DMA channel settings, and Reserved memory size</td></tr><tr><td>Boot</td><td>Boot-up Settings</td></tr><tr><td>Security</td><td>Setting or changing Passwords</td></tr><tr><td>Chipset</td><td>Northbridge and Southbridge settings</td></tr><tr><td>Exit</td><td>Exiting with or without changing settings, Loading Optimal or Failsafe conditions</td></tr></table>

# BIOS Main Setup Screen

<table><tr><td colspan="7">BIOS Setup Utility</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">System Overview</td><td rowspan="2" colspan="2">Use [ENTER], [TAB] or [SHIFT-TAB] to select a field. Use  $\left\lbrack  +\right\rbrack$  or [-] to configure system Time.</td></tr><tr><td rowspan="2" colspan="5">AMIBIOS Version : 08.XX.XX Build Date: XX/XX/XX ID : LB735XXX.X Processor Genuine Intel (R) CPU N270 @ 1.60GHz Speed : 1600MHz Count : X System Memory Size :XXXXMB System Time System Date [XX:XX:XX] [Xxx XX/XX/20XX]</td></tr><tr><td> $\leftrightarrow$  Select Screen  $\downarrow   \uparrow$  Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit</td><td></td></tr></table>

v02.XX (C) Copyright 1985-20XX, American Megatrends, Inc.
Figure 4-1. BIOS Main Setup Screen

• Date & Time

♦ System Time (hh:mm:ss) – This is a 24-hour clock setting in hours, minutes, and seconds.

♦ System Date (day of week, mm:dd:yyyy) – This field requires the alpha-numeric entry of the day of week, day of the month, calendar month, and all 4 digits of the year, indicating the century plus year (Fri 10/21/2011).

BIOS Advanced Setup Screen

<table><tr><td colspan="7">BIOS Setup Utility</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Advanced Settings</td><td colspan="2">Configure CPU.</td></tr><tr><td colspan="5">WARNING: Setting wrong values in below sections may cause system to malfunction.</td><td colspan="2"></td></tr><tr><td colspan="5">CPU ConfigurationIDE ConfigurationFloppy ConfigurationSuperIO ConfigurationHardware Health ConfigurationACPI ConfigurationAPM ConfigurationMPS ConfigurationPCI Express ConfigurationSmbios ConfigurationRemote Access ConfigurationUSB ConfigurationPCI-ISA Bridge Configuration</td><td>←→</td><td>Select Screen↓↑ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

LB735\_BIOS\_AdvancedScreen\_a
v02.XX (C) Copyright 1985-20XX, American Megatrends, Inc.

Figure 4-2. BIOS Advanced Setup Screen

# CPU Configuration

Manufacture: Intel
♦ Genuine Intel® CPU N270 @ 1.60GHz
Frequency: 1.60GHz
♦ FSB Speed: 532MHz
Cache L1: 24KB
Cache L2: 512KB
Ratio Actual Value: 12

♦ Max CPUID Limit [Disabled; Enabled]
Execute - Disable Bit Capability [Disabled; Enabled]
♦ Intel (R) Speed Step (tm) tech [Disabled; Enabled]
♦ Intel (R) C-State tech [Disabled; Enabled]
Enhanced C-States [Disabled; Enabled]

# IDE Configuration

♦ ATA/IDE Configuration [Disabled; Compatible; Enhanced]
Legacy IDE Channels [SATA Only; Reserved; SATA Pri, PATA Sec; PATA Only]
Primary IDE Master : [Not Detected]
Type – [Not Installed; Auto; CD/DVD; ARMD]
• LBA/Large Mode – [Disabled; Auto]
Block (Multi-Sector Transfer) – [Disabled; Auto]
PIO Mode – [Auto; 0; 1; 2; 3; 4]
DMA Mode – [Auto]
S.M.A.R.T. – [Auto; Disabled; Enabled]
32Bit Data Transfer – [Disabled; Enabled]

Primary IDE Slave : [Not Detected]

Type – [Not Installed; Auto; CD/DVD; ARMD]
LBA/Large Mode – [Disabled; Auto]
Block (Multi-Sector Transfer) – [Disabled; Auto]
PIO Mode – [Auto; 0; 1; 2; 3; 4]
DMA Mode – [Auto]
S.M.A.R.T. – [Auto; Disabled; Enabled]
32Bit Data Transfer – [Disabled; Enabled]

♦ Secondary IDE Master : [Not Detected]

Type – [Not Installed; Auto; CD/DVD; ARMD]
LBA/Large Mode – [Disabled; Auto]
Block (Multi-Sector Transfer) – [Disabled; Auto]
PIO Mode – [Auto; 0; 1; 2; 3; 4]
DMA Mode – [Auto]
S.M.A.R.T. – [Auto; Disabled; Enabled]
32Bit Data Transfer – [Disabled; Enabled]

Secondary IDE Slave : [Not Detected]

Type – [Not Installed; Auto; CD/DVD; ARMD]
LBA/Large Mode – [Disabled; Auto]
Block (Multi-Sector Transfer) – [Disabled; Auto]
PIO Mode – [Auto; 0; 1; 2; 3; 4]
DMA Mode – [Auto]
S.M.A.R.T. – [Auto; Disabled; Enabled]
32Bit Data Transfer – [Disabled; Enabled]

Hard Disk drive Write Protect – [Disabled; Enabled]
IDE Detect Time Out (Sec) – [0; 5; 10; 15; 20; 25; 30; 35]
♦ ATA (PI) 80Pin Cable Detection – [Host & Device; Host; Device]

# • Floppy Configuration

Floppy A – [Disabled; 360 KB 51/4"; 1.2 MB 51/4"; 720 KB 31/2"; 1.44 MB 31/2"; 2.88 MB 31/2"]

# • Super IO Configuration

♦ OnBoard Floppy Controller – [Disabled; Enabled]
♦ Serial Port1 Address – [Disabled; 3F8; 3E8; 2E8]
Serial Port1 IRQ – [3; 4; 10; 11]
RS-485 Control for SP1 – [Disabled; Enabled]
- (Appears only if Enabled is selected) Auto Direction Control Sel [FC off; FC on]
- (Appears only if Enabled is selected) Signal Select SP1 [nDTR ; nRTS]
- (Appears only if Enabled is selected) Polarity SP1 [Low; High]

♦ Serial Port2 Address – [Disabled; 2F8; 3E8; 2E8]

Serial Port2 IRQ – [3; 4; 10; 11]
Serial Port2 Mode – [Normal; IrDA; ASK IR]
- (Appears only if IrDA or ASK IR is selected) IR Duplex Mode [Full Duplex; Half Duplex]
- (Appears only if IrDA or ASK IR is selected) COMB Receiver Polarity [High; Low]
- (Appears only if IrDA or ASK IR is selected) COMB Xmitter Polarity [High; Low]
RS-485 Control for SP2 – [Disabled; Enabled]
- (Appears only if Enabled is selected) Auto Direction Control Sel [FC off; FC on]
- (Appears only if Enabled is selected) Signal Select SP2 [nDTR ; nRTS]
- (Appears only if Enabled is selected) Polarity SP2 [Low; High]

Serial Port3 Address – [Disabled; 3F8; 2F8; 3E8; 2E8; 2F0; 2E0]

Serial Port3 IRQ – [3; 4; 10; 11]
RS-485 Control for SP3 – [Disabled; Enabled]
- (Appears only if Enabled is selected) Auto Direction Control Sel [FC off; FC on]
- (Appears only if Enabled is selected) Signal Select SP3 [nDTR ; nRTS]
- (Appears only if Enabled is selected) Polarity SP3 [Low; High]

Serial Port4 Address – [Disabled; 3F8; 2F8; 3E8; 2E8; 2F0; 2E0]

Serial Port4 IRQ – [3; 4; 10; 11]
RS-485 Control for SP4 – [Disabled; Enabled]
- (Appears only if Enabled is selected) Auto Direction Control Sel [FC off; FC on]
- (Appears only if Enabled is selected) Signal Select SP4 [nDTR; nRTS]
- (Appears only if Enabled is selected) Polarity SP4 [Low; High]

Parallel Port Address – [Disabled; 378; 278; 3BC]

• Parallel Port Mode – [Normal; SPP (Bi-Dir); EPP + SPP; ECP; ECP + EPP]
- (Appears only if EPP+SPP is selected) EPP Version [1.9; 1.7]
- (Appears only if ECP is selected) ECP Mode DMA Channel [DMA0; DMA1; DMA3]
- (Appears only if ECP+EPP is selected) EPP Version [1.9; 1.7]
- (Appears only if ECP+EPP is selected) ECP Mode DMA Channel [DMA0; DMA1; DMA3]

Parallel Port IRQ – [IRQ5; IRQ7]

# Hardware Health Configuration

H/W Health Function [Disabled; Enabled]
♦ PWM Mode Setting [Fan Always On Full; Fan Disable Mode; Set duty cycle]
♦ PWM Ramp Rate [4.85 Hz; 9.62 Hz; 14.49 Hz; 24.39 Hz; 38.46 Hz; 55.56 Hz; 100 Hz; 200 Hz]
(Appears only if “Set duty cycle” is selected) PWM Control Duty Cycle [200]
CPU Temperature : XX°C/XX°F
Board Temperature : XX°C/XX°F
Fan Speed : XXX
Vcc : X.XXX V
VTR : X.XXX V
♦ VBAT : X.XXX V

# ACPI Configuration

General ACPI Configuration
Suspend mode [S1 (POS); S3 (STR); Auto]
Repost Video on S3 Resume [No; Yes]
♦ Advanced ACPI Configuration
ACPI Version Features [ACPI v1.0; ACPI v2.0; ACPI v3.0]
ACPI OS Shutdown Mode [ATX; AT]
Headless mode [Disabled; Enabled]
Chipset ACPI Configuration
APIC ACPI SCI IRQ [Disabled; Enabled]

# APM Configuration

♦ Power Management/APM [Disabled; Enabled]
♦ Video Power Down Mode [Disabled; Suspend]
Hard Disk Power Down Mode [Disabled; Suspend]
Suspend Time Out [Disabled; 1 Min; 2 Min; 4 Min; 8 Min; 10 Min; 20 Min; 30 Min; 40 Min; 50 Min; 60 Min]
♦ Throttle Slow Clock Ratio [87.5%; 75.0%; 62.5%; 50%; 37.5%; 25%; 12.5%]
♦ Keyboard & PS/2 Mouse [IGNORE; MONITOR]
♦ Power Button Mode [On/Off; Suspend]
♦ Advanced Resume Events Controls
Resume On RTC Alarm [Disabled; Enabled]
- (Appears only if Enabled is selected) RTC Alarm Date (Days) [15]
- (Appears only if Enabled is selected) RTC Alarm Time [XX:XX:XX]

# MPS Configuration

♦ MPS Revision [1.1; 1.4]

# PCI Express Configuration

Active State Power-Management [Disabled; Enabled]

SB PCIE Ports Configuration
- PCIE Mini Card [Auto; Enabled; Disabled]
- PCIE High Priority Port [Disabled; PCIE Onboard Gbit Ethernet; PCIE Mini Card; PCIE Onboard Gbit Ethernet2]
- PCIE Onboard GbE1 IOxAPIC Enab [Disabled; Enabled]
- PCIE Mini Card IOxAPIC Enable [Disabled; Enabled]
- PCIE Onboard GbE2 IOxAPIC Enab [Disabled; Enabled]

# Smbios Configuration

♦ Smbios Smi Support [Disabled; Enabled]

# • Remote Access Configuration

♦ Remote Access – [Hotcable; Enabled]
Serial port number – [COM1; COM2]
Base Address, IRQ [2F8h, 3]
♦ Serial Port Mode – [115200 8, n, 1; 57600 8, n, 1; 38400 8, n, 1; 19200 8, n, 1; 09600 8, n, 1]
Flow Control – [None; Hardware; Software]
Redirection After BIOS POST – [Disabled; Boot Loader; Always]
Terminal Type – [ANSI; VT100; VT-UTF8]
Note: If VT-UTF8 is selected, the following item disappears from the screen.
♦ VT-UTF8 Combo Key Support – [Disabled; Enabled]
♦ Sredir Memory Display Delay – [No Delay; Delay 1 sec; Delay 2 sec; Delay 4 sec]

# USB Configuration

♦ Module Version - X.XX.X-XX.X
USB Devices Enabled : X Xxxxxxxxxx
♦ Legacy USB Support – [Disabled; Enabled; Auto]
♦ USB 2.0 Controller Mode – [FullSpeed; HiSpeed]
BIOS EHCI Hand-Off – [Disabled; Enabled]
USB Device Wakeup From S3/S4 – [Disabled; Enabled]
♦ Hotplug USB FDD Support – [Disabled; Enabled; Auto]
USB Mass Storage Device Configuration
USB Mass Storage Reset Delay – [10 Sec; 20 Sec; 30 Sec; 40 Sec]
Device #1 [USB Hotplug FDD]
Emulation Type – [Auto; Floppy; Forced FDD; Hard Disk; CDROM]

# PCI-ISA Bridge Configuration

♦ ISA Port Window 0 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
♦ ISA Port Window 0 High Byte – [0200]
♦ ISA Port Window 0 Low Byte – [0000]
♦ ISA Port Window 1 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
♦ ISA Port Window 1 High Byte – [0200]
♦ ISA Port Window 1 Low Byte – [0040]

♦ ISA Port Window 2 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
ISA Port Window 2 High Byte – [0300]
ISA Port Window 2 Low Byte – [0000]
♦ ISA Port Window 3 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
ISA Port Window 3 High Byte – [0300]
ISA Port Window 3 Low Byte – [0040]
ISA Port Window 4 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
ISA Port Window 4 High Byte – [0A00]
ISA Port Window 4 Low Byte – [0079]
♦ ISA Port Window 5 Byte Length – [Disabled; 01; 02; 04; 08; 10; 20; 40; 80]
ISA Port Window 5 High Byte – [0200]
ISA Port Window 5 Low Byte – [0079]
♦ ISA Memory Window 0 KB Length – [Disabled; 16; 32; 64; 128; 256; 512; 1024; 2048]
ISA Memory Window 0 High Byte – [000000]
ISA Memory Window 0 Mid Byte – [000000]
ISA Memory Window 0 Low Byte – [000000]
ISA Memory Window 1 KB Length – [Disabled; 16; 32; 64; 128; 256; 512; 1024; 2048]
ISA Memory Window 1 High Byte – [000000]
ISA Memory Window 1 Mid Byte – [000000]
ISA Memory Window 1 Low Byte – [000000]
ISA Memory Window 2 KB Length – [Disabled; 16; 32; 64; 128; 256; 512; 1024; 2048]
ISA Memory Window 2 High Byte – [000000]
ISA Memory Window 2 Mid Byte – [000000]
ISA Memory Window 2 Low Byte – [000000]
ISA Memory Window 3 KB Length – [Disabled; 16; 32; 64; 128; 256; 512; 1024; 2048]
ISA Memory Window 3 High Byte – [000000]
ISA Memory Window 3 Mid Byte – [000000]
ISA Memory Window 3 Low Byte – [000000]

# BIOS PCIPnP Setup Screen

<table><tr><td colspan="6">BIOS Setup Utility</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Advance PCI/PnP Settings</td><td rowspan="20">Clear NVRAM during System Boot.</td></tr><tr><td colspan="5">WARNING: Setting wrong values in below sections may cause system to malfunction.</td></tr><tr><td colspan="5">Clear NVRAM [No]</td></tr><tr><td colspan="5">Plug &amp; Play O/S [Yes]</td></tr><tr><td colspan="5">PCI Latency Timer [64]</td></tr><tr><td colspan="5">Allocate IRQ to PCI VGA [Yes]</td></tr><tr><td colspan="5">Pallette Snooping [Disabled]</td></tr><tr><td colspan="5">PCI IDE BusMaster [Enabled]</td></tr><tr><td colspan="5">OffBoard PCI/ISA IDE Card [Auto]</td></tr><tr><td colspan="5">IRQ3 [Available]</td></tr><tr><td colspan="5">IRQ4 [Available]</td></tr><tr><td colspan="5">IRQ5 [Available]</td></tr><tr><td colspan="5">IRQ6 [Available]</td></tr><tr><td colspan="5">IRQ7 [Available]</td></tr><tr><td colspan="5">IRQ9 [Available]</td></tr><tr><td colspan="5">IRQ10 [Available]</td></tr><tr><td colspan="5">IRQ11 [Available]</td></tr><tr><td colspan="5">IRQ12 [Available]</td></tr><tr><td colspan="5">IRQ14 [Available]</td></tr><tr><td colspan="5">IRQ15 [Available]</td></tr><tr><td colspan="5">DMA Channel 0 [Available]</td><td>←→ Select Screen</td></tr><tr><td colspan="5">DMA Channel 1 [Available]</td><td>↓↑ Select Item</td></tr><tr><td colspan="5">DMA Channel 3 [Available]</td><td>+ - Change Option</td></tr><tr><td colspan="5">DMA Channel 5 [Available]</td><td>F1 General Help</td></tr><tr><td colspan="5">DMA Channel 6 [Available]</td><td>F10 Save and Exit</td></tr><tr><td colspan="5">DMA Channel 7 [Available]</td><td>ESC Exit</td></tr><tr><td colspan="5">Reserved Memory Size [Disabled]</td><td></td></tr></table>

LB735\_BIOS\_PCIPnPScreen\_a
v02.XX (C) Copyright 1985-20XX, American Megatrends, Inc.

Figure 4-3. BIOS PCIPnP Setup Screen

Clear NVRAM – [No; Yes]
• Plug & Play O/S – [No; Yes]
• PCI Latency timer – [32; 64; 96; 128; 160; 192; 224; 248]
• Allocate IRQ to PCI VGA – [Yes; No]
Palette Snooping – [Disabled; Enabled]
PCI IDE BusMaster – [Disabled; Enabled]
OffBoard PCI/ISA IDE Card – [Auto; PCI Slot1; PCI Slot2; PCI Slot3; PCI Slot4]
IRQ3 – [Available; Reserved]
IRQ4 – [Available; Reserved]
IRQ5 – [Available; Reserved]
IRQ6 – [Available; Reserved]
IRQ7 – [Available; Reserved]

IRQ9 – [Available; Reserved]
IRQ10 – [Available; Reserved]
IRQ11 – [Available; Reserved]
IRQ12 – [Available; Reserved]
IRQ14 – [Available; Reserved]
IRQ15 – [Available; Reserved]
. DMA Channel 0 – [Available; Reserved]
• DMA Channel 1 – [Available; Reserved]
• DMA Channel 3 – [Available; Reserved]
. DMA Channel 5 – [Available; Reserved]
. DMA Channel 6 – [Available; Reserved]
• DMA Channel 7 – [Available; Reserved]
Reserved Memory Size – [Disabled; 16k; 32k; 64k]

# BIOS Boot Setup Screen

<table><tr><td colspan="6">BIOS Setup Utility</td></tr><tr><td colspan="6">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td colspan="4">Boot Settings</td><td colspan="2">Configure Settings during System Boot.</td></tr><tr><td colspan="4">▶ Boot Settings Configuration</td><td></td><td></td></tr><tr><td colspan="4">1st Boot Device [1st FLOPPY DRIVE]</td><td></td><td></td></tr><tr><td colspan="4">2nd Boot Device [CD/DVD]</td><td></td><td></td></tr><tr><td colspan="4">3rd Boot Device [Hard Drive]</td><td></td><td></td></tr><tr><td colspan="4">4th Boot Device [USB:USB Hotplug FD]</td><td></td><td></td></tr><tr><td colspan="4">5th Boot Device [Network:IBA GE Slo]</td><td></td><td></td></tr><tr><td colspan="4">▶ Hard Disk Drives</td><td rowspan="2" colspan="2">←→ Select Screen ↓↑ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="4">▶ Removable Drives CD/DVD Drives USB Drives Network Drives</td></tr></table>

v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc.
Figure 4-4. BIOS Boot Setup Screen

# . Boot Settings Configuration

Quick Boot – [Disabled; Enabled]
♦ Quiet Boot – [Disabled; Enabled]
♦ Add On ROM Display Mode – [Force BIOS; Keep Current]
Bootup Num-Lock – [Off; On]
♦ PS/2 Mouse Support – [Disabled; Enabled; Auto]

Wait for 'F1' If Error – [Disabled; Enabled]
Hit 'DEL' Message Display – [Disabled; Enabled]
♦ Interrupt 19 Capture – [Disabled; Enabled]
Watchdog Timeout in Seconds – [Disabled]
GPIO Port Configuration – [Disabled; Enabled]
♦ GPIO Port Mask – [11110000]
GPIO Port Init Value – [00000000]
♦ OnBoard Gbit Ethernet Boot ROM – [Enabled; Disabled]
♦ OnBoard Gbit Ethernet2 Boot ROM – [Enabled; Disabled]
1st Boot Device – [1st FLOPPY DRIVE; CD/DVD; Hard Drive; USB: USB Hotplug FDD; Network: IBA GE Slot 0200 v1327; Disabled]
2nd Boot Device – [1st FLOPPY DRIVE; CD/DVD; Hard Drive; USB: USB Hotplug FDD; Network: IBA GE Slot 0200 v1327; Disabled]
3rd Boot Device – [1st FLOPPY DRIVE; CD/DVD; Hard Drive; USB: USB Hotplug FDD; Network: IBA GE Slot 0200 v1327; Disabled]
4th Boot Device – [1st FLOPPY DRIVE; CD/DVD; Hard Drive; USB: USB Hotplug FDD; Network: IBA GE Slot 0200 v1327; Disabled]
5th Boot Device – [1st FLOPPY DRIVE; CD/DVD; Hard Drive; USB: USB Hotplug FDD; Network: IBA GE Slot 0200 v1327; Disabled]

Hard Disk Drives

1st Drive – [Not Installed]

♦ Removable Drives

1st Drive – [1st FLOPPY DRIVE; Disabled]

♦ CD/DVD Drives

1st Drive – [Not Installed]

♦ USB Drives

1st Drive – [USB:USB Hotplug FDD; Disabled]

Network drives

1st Drive – [Network:IBA GE Slot 0200 v1327; Network:IBA GE Slot 0100 v1327; Disabled]

2nd Drive – [Network:IBA GE Slot 0200 v1327; Network:IBA GE Slot 0100 v1327; Disabled]

# BIOS Security Setup Screen

<table><tr><td colspan="7">BIOS Setup Utility</td><td></td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td><td></td></tr><tr><td colspan="5">Security Settings</td><td rowspan="3" colspan="2">Install or Change the password.</td><td></td></tr><tr><td colspan="5">Supervisor Password :Not installed
User Password :Not installed</td><td></td></tr><tr><td colspan="5">Change Supervisor Password
Change User Password</td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td>←→</td><td>Select Screen
↓↑</td><td>Select Item
Enter Change
F1 General Help
F10 Save and Exit
ESC Exit</td></tr></table>

LB735\_BIOS\_SecurityScreen\_a
v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc.

Figure 4-5. BIOS Security Setup Screen

# • Security Settings

Supervisor Password – [Not Installed]
♦ User Password – [Not Installed]
♦ Change Supervisor Password
a. Select Change Supervisor Password from the Security Setup menu.
b. Press &lt;Enter&gt; to access the pop-up entry field, Enter New Password.
c. Type the password and press &lt;Enter&gt; again.
d. The screen will not display the password as you type.
e. Re-type the password when prompted by the pop-up entry field and press &lt;Enter&gt; again. If the password is not confirmed when you re-type it, an error message will appear. The password is stored in NVRAM if you have successfully entered the password.

# Change User Password

a. Select Change User Password from the Security Setup menu.
b. Press &lt;Enter&gt; to access the pop-up entry field, Enter New Password.
c. Type the password and press &lt;Enter&gt; again.
d. The screen will not display the password as you type.
e. Re-type the password when prompted by the pop-up entry field and press &lt;Enter&gt; again. If the password is not confirmed when you re-type it, an error message will appear. The password is stored in NVRAM if you have successfully entered the password.

# BIOS Chipset Setup Screen

<table><tr><td colspan="6">BIOS Setup Utility</td></tr><tr><td colspan="6">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td colspan="4">Advanced Chipset SettingsWARNING: Setting wrong values in below sections may cause system to malfunction.► NorthBridge Configuration► SouthBridge Configuration</td><td colspan="2">Configure North Bridge features.↔ Select Screen↓↑ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

LB735\_BIOS\_ChipsetScreen\_a
v02.xx (C) Copyright 1985-20xx, American Megatrends, Inc.

Figure 4-6. BIOS Chipset Setup Screen

# • NorthBridge Configuration

DRAM Frequency – [Auto; 400 MHz; 533 MHz]
♦ Configure DRAM Timing by SPD – [Disabled; Enabled]
♦ Memory Hole – [Disabled; 15MB-16MB]
Boot Graphics Adapter Priority – [IGD; PCI/IGD]
♦ Internal Graphics Mode Select – [Disabled; Enabled, 1 MB; Enabled, 8 MB]
Chipset Thermal Throttling – [Disabled; Enabled]
♦ DT in SPD – [Disabled; Enabled]
TS on DIMM – [Disabled; Enabled]
♦ Video Function Configuration

DVMT Mode Select – [Fixed Mode; DVMT Mode]
- DVTM/FIXED Memory – [64MB; 128MB; Maximum DVTM]
Boot Display Device – [Auto; CRT; LFP; LFP+CRT]
Flat Panel Type – [640x480 18-bit; 800x600 18-bit; 1024x768 18-bit; 1280x1024 18-bit; 1400x1050 18-bit; 1600x1200 18-bit; 1280x768 18-bit; 1680x1050 18-bit; 1920x1200 18-bit; 1280x800 18-bit; 1280x600 18-bit; 2048x1536 18-bit]
Local Flat Panel Scaling [Auto; Forced Scaling; Disabled]

# SouthBridge Configuration

USB Functions – [Disabled; 2 USB Ports; 4 USB Ports; 6 USB Ports]
USB 2.0 Controller – [Enabled; Disabled]
AC’97 Audio Controller – [Enabled; Disabled]
SMBus Controller – [Enabled; Disabled]
High Precision Event Timer – [Enabled; Disabled]
SLP\_S4# Min. Assertion Width – [4 to 5 seconds; 3 to 4 seconds; 2 to 3 seconds; 1 to 2 seconds]
Restore on AC Power Loss – [Power Off; Power On; Last State]

# BIOS Exit Setup Screen

<table><tr><td colspan="7">BIOS Setup Utility</td></tr><tr><td colspan="7">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td colspan="4">Exit Options Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe Defaults</td><td colspan="3">Exit system setup after saving the changes. F10 key can be used for this operation.  $\leftrightarrow$  Select Screen  $\downarrow   \uparrow$  Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit</td></tr></table>

x02.xx (C) Copyright 1985-20xx, American Megatrends, Inc.

Figure 4-7. BIOS Exit Setup Screen

Save Changes and Exit

The &lt; F10 &gt; key can be used for this operation.

Discard Changes and Exit

The &lt; ESC &gt; key can be used for this operation.

Discard Changes

The &lt; F7 &gt; key can be used for this operation.

Load Optimal Defaults

The &lt; F9 &gt; key can be used for this operation.

Load Failsafe Defaults

The &lt; F8 &gt; key can be used for this operation.

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed in the Table A-1 below. Requests for support through the Ask an Expert web page are given the highest priority, and usually will be addressed within one working day.

ADLINK Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro by ADLINK web page at http://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK” unique to you with access to exclusive services and account information.

Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered followed by an e-mail response. Once you have submitted your request, you must log in to My Stuff where you can check status, update your request, and access other features.
Download Service – This service is also free and available 24 hours a day at http://www.adlinktech.com. For certain downloads such as technical documents and software, you must register online before you can log in to this service.

Table A-1. Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://www.adlinktech.com/AAE/</td></tr><tr><td>Web Site</td><td>http://www.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>Contact us should you require any service or assistance.ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Zhonghe DistrictNew Taipei City 235, Taiwan新北市中和區建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech Park,Pudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.com</td></tr></table>

Table A-1. Technical Support Contact Information

<table><tr><td rowspan="8"></td><td>ADLINK Technology BeijingAddress:北京市海淀区上地东路1号盈创动力大厦E座801室(100085)Rm. 801, Power Creative E, No. 1, B/DShang Di East Rd., Beijing, 100085 ChinaTel: +86-10-5885-8666Fax: +86-10-5885-8625Email: market@adlinktech.com</td></tr><tr><td>ADLINK Technology ShenzhenAddress:深圳市南山区科技园南区高新南七道数字技术园A1栋2楼C区(518057)2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 ChinaTel: +86-755-2643-4858Fax: +86-755-2664-6353Email: market@adlinktech.com</td></tr><tr><td>ADLINK Technology (Europe) GmbHAddress: Nord Carree 3, 40477 Duesseldorf, GermanyTel: +49-211-495-5552Fax: +49-211-495-5557Email: emea@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (French Liaison Office)Address: 15 rue Emile Baudot, 91300 Massy CEDEX, FranceTel: +33 (0) 1 60 12 35 66Fax: +33 (0) 1 60 12 35 66Email: france@adlinktech.com</td></tr><tr><td>ADLINK Technology Japan CorporationAddress: 〒101-0045 東京都千代田区神田鍛冶町3-7-4神田374ビル4FKANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho, Chiyoda-ku, Tokyo 101-0045, JapanTel: +81-3-4455-3722Fax: +81-3-5209-6013Email: japan@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Korean Liaison Office)Address: 서울시 서초구 서초동 1506-25 한도B/D 2층2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu, Seoul 137-070, KoreaTel: +82-2-2057-0565Fax: +82-2-2057-0563Email: korea@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd.Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584Tel: +65-6844-2261Fax: +65-6844-2263Email: singapore@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)Address: No. 1357, &quot;Anupama&quot;, Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, IndiaTel: +91-80-65605817Fax: +91-80-22443548Email: india@adlinktech.com</td></tr></table>

# A

AMI BIOS 8 user’s guide specification reference 2

assistance, technical . 61

Atom N270 CPU . ...2, 4, 5

audio

CODEC datasheet reference . 2

interface description . . 34

interface features 6

interface pin-out list . 34

# B

battery

features 6

input interface .. 43

interface description . .. 30

Real Time Clock (RTC) . 39

beep speaker . .. 30

BIOS

access to BIOS setup (local display) ............. 45

Advanced setup screen .. 48

Boot setup screen .. 55

Chipset setup screen . .. 58

Exit setup screen . 59

logo screen (Splash) . .. 46

Main setup screen . 47

PCIPnP setup screen . 54

recovery feature ... 6, 40

Security setup screen . 57

setup screens .. 47

setup supported features . .. 47

setup using remote access . 45

User Guide reference 2

Watchdog Timer (WDT) feature . 41

block diagram 7

board features . 5

boot features . 6

#

connectors

headers and connectors list . 12

console redirection . 40

CPU

datasheet reference . 2

fan interface (optional) pin-out list . 42

features 5

# D

dimensions . 17

# E

EBX

Architecture 3

specification reference

Environmental specifications . . 18

Ethernet

chip specification reference 2

ground ..14

interface features .6

LED interfaces ..42

# F

fan

interface pin-out list . ..42

voltage limits ..42

floppy interface

description ..24

features 5

# G

GLAN LED interfaces ..42

GPIO interface ..39

Graphics Memory Hub datasheet reference ..........2

# H

hardware overview ..21

headers and connectors list .12

heatsinks descriptions ..19

height, overall . ..17

hot cable (modified serial cable) ..41

humidity ranges ..18

# I

I/O address map .23

ICH datasheet reference 2

IDE interface features 5

interrupt channel assignments .22

IRQs . ..22

ISA bus features 5

# J

jumper header locations ..15

# K

keyboard interface

description ..30

features . ..6

# L

LAN LED interfaces ..42

LED

Ethernet pin-out lists .42

power-on .30

length .17

logo screen (Splash)

customization ..46

requirements ..46

LVDS

interface features .. 6, 35

interface pin-out list . .36

# M

major ICs

list ..8

specification web sites 2

memory

features 5

map . 23

miscellaneous

features 6

hardware functions ..21, 39

modified serial cable . 41

mouse interface features 6

#

Northbridge datasheet reference 2

#

on-line support . 61

Oops! Jumper

(BIOS recovery) description .. 40

features . 6

#

parallel port

description . 25

features 5

pin-out list . 25

PC/104-Plus

bus features . 5

PCI Express Mini Card specification reference .... 1

PCI specification reference

PCI-to-ISA bridge

datasheet reference 2

mapping . . 46

pin sequence identification . 13

pin-1 locations . . 14

power

consumption table . 18

input voltage requirements . 38

interface descriptions . 38

power button and reset switch interface ........ 38

power-in interface pin-out list . 38

specifications . 18

processor requirements, heatsinks . 19

product description . 4

PS/2 interface

features 6

keyboard . 30

#

Real Time Clock

description . 39

features . 6

references, specification

registration, web site . 61

remote access

description .. 40

features 6

procedure . 45

reset switch

interface description . 30

interface pin-out list . 38

RS232 function . 26

RS485 function . 26

# S

sample code

GPIO 39

WDT 41

serial ports

access to BIOS setup . 45

features 5

pin-out lists . 27

remote access . 40

terminal, ANSI-compatible . 40

SMBus

description . 31

interface pin-out list . 40

slave addresses . 31

Southbridge datasheet reference 2

speaker . . 30

specification references

Super I/O controller datasheet reference 2

supported features

200-pin DDR2 SODIMM socket 5

AT power-in interface . 38

Atom N270 CPU 5

ATX power-on interface . 38

audio AC’97 interface ... 6, 34

battery-free boot . 6

console redirection . 40

CPU optional fan header . 42

Ethernet interfaces 6

external battery ... 6, 30

external GLAN Activity LED . 42

floppy interface ... 5, 24

heatsinks . 19

I/O address map . 23

IRQ assignments . 22

ISA bus 5

jumper headers, on board 15

logo screen (Splash) . 46

LVDS interface . 36

memory 5

memory map . 23

on-board battery 6

Oops! jumper (BIOS recovery) ... 6, 40

parallel port ... 5, 25

PC ’Beep’ speaker interface . 30

PC/104 bus 5

PC/104-Plus bus 5

power button . 38

PS/2 interfaces ... 6, 30

Real Time Clock ... 6, 39

remote access ... 6, 40

reset switch interface . 30

RS485 function . 26

serial ports ... 5, 26

SMBus devices . . 31

thermal monitoring . ... 6, 39

USB 2.0 description . 32

USB ports . . 5

user GPIO capability . 39

VGA interface . . 36

video interfaces .... 6, 35

voltage monitoring 6

Watchdog Timer (WDT) . 6

# T

technical support . 61

temperature

monitoring description . 39

ranges . 18

terminal emulation software . 40

thermal

cooling requirements 19

monitoring description . 39

monitoring features 6

thickness, board . 17

TV Out

interface features ... 6, 35

interface pin-out list . 37

two-wire serial port . 26

# U

USB

features 5

interface descriptions . 32

pin-out list (ports 0 & 1) . 33

pin-out list (ports 2 & 3) . 33

pin-out list (ports 4 & 5) . 34

utility interfaces

functions ..21

functions (utility 1) .30

functions (utility 2) .31

pin-out list (utility 1) .30

pin-out list (utility 2) .31

# V

VGA

interface features .. 6, 35

interface pin-out list .36

video

interface features .6

LVDS interface pin-out list .36

TV Out interface pin-out list .37

VGA interface pin-out list .36

voltage

ATX power supply requirement .38

CPU fan limits ...42

monitoring features .6

power-in requirements .38

#

Watchdog Timer

description .41

features .6

web sites

ADLINK .61

major IC specifications

standards specifications

weight .17

width .17
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