# ReadyBoard™ 820

# Single Board Computer

# Reference Manual

P/N 50-1Z064-1000

# DISCLAIMER

ADLINK Technology, Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated ADLINK products, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. ADLINK shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages. ADLINK reserves the right to revise this publication from time to time without obligation to notify any person of such revisions. If errors are found, please contact ADLINK at the address listed below this Disclaimer.

# TRADEMARKS

CoreModule and the Ampro logo are registered trademarks, and ADLINK, Little Board, LittleBoard, MightyBoard, MightySystem, Milsystem, MiniModule, ReadyBoard, ReadyBox, ReadyPanel, ReadySystem, and RuffSystem are trademarks of ADLINK Technology, Inc. All other marks are the property of their respective companies.

REVISION HISTORY

<table><tr><td>Revision</td><td>Reason for Change</td><td>Date</td></tr><tr><td>A, A</td><td>Initial Release</td><td>Jan/07</td></tr><tr><td>B, A</td><td>Added 1.0GHz CPU version; added PCI-104, USB 4&amp;5, parallel / floppy; changed connector and component ID numbers; removed 1.8 Mhz CPU version, LCD interface; revised power specifications</td><td>Feb/08</td></tr><tr><td>B, B</td><td>Changed system memory requirement from ‘Up to 2GB’ to ‘Up to 1GB’; corrected chipset from 915GM to 915GME; added Caution for Table 3-17; updated table 3-1; corrected pin 1 of J14 in fig 2-6</td><td>June/09</td></tr><tr><td>1000</td><td>Removed requirement from the Power On section under Table 3-18 that the J2 header requires Standby voltage; changed memory specification to ‘Up to 2GB’; changed document part number to 50-1Z064-1000</td><td>Oct/10</td></tr></table>

ADLINK Technology, Incorporated

5215 Hellyer Avenue

San Jose, CA 95138-1007

Tel. 408 360-0200

Fax 408 360-0222

www.adlinktech.com

© Copyright 2007, 2008, 2009, 2010 ADLINK Technology, Incorporated

# Audience

This manual provides reference only for computer design engineers, including but not limited to hardware and software designers and applications engineers. ADLINK Technology, Inc. assumes you are qualified to design and implement prototype computer equipment.

# Contents

# Chapter 1 About This Manual ..

Purpose of this Manual ..

References ..

# Chapter 2 Product Overview...........

EPIC Architecture .3

Product Description.. .4

Board Features . .5

Block Diagram . ..8

Major Integrated Circuits . .9

Header and Connector Definitions....... .....10

Additional Components.. ..13

Jumper Header Definitions ......... ..13

Specifications......... ...14

Power Specifications ....... ..14

Environmental Specifications...... ..14

Thermal/Cooling Requirements. ..15

Physical Specifications ...... ....15

Mechanical Specifications . ..15

# Chapter 3 Hardware . .17

Overview .... ..17

Channel Interrupt Assignments.. ..19

Memory Map . ..20

I/O Address Map . ..20

Floppy/Parallel Interface ...... ..21

Serial Interfaces ..23

USB Interfaces.. ..26

USB 2.0 Support.. ..26

Legacy USB Support . .26

USB2 and USB3 .27

USB4 and USB5 .27

Audio Interface........ ..27

Video Interfaces ...... ..28

PanelLink. ..29

LVDS Interface (Low Voltage Differential Signaling) ..30

Utility Interface ....... ...31

Miscellaneous .. ..31

Real Time Clock (RTC) . ..31

External Battery (BT1) ... ..31

Temperature Monitoring ..31

User GPIO Signals .32

Serial Console . .32

Infrared (IrDA) Port .. ..32

System Management Bus (SMBus).. .33

Watchdog Timer ... ..34

Power Interfaces . . 34

Power In .. .. 34

Power On ....... .. 35

Optional System Fan .. . 35

Power and Sleep States.... . 35

Power-On Switch . 35

Sleep States (ACPI) .. . 36

Wake Up Activities . . 37

Chapter 4 BIOS Setup .... . 39

Introduction........... .. 39

Entering BIOS Setup (VGA Display) . . 39

Entering BIOS Setup (Remote Access) . 39

OEM Logo (Splash) Utility ....... .. 40

Logo Image Requirements..... . 40

Appendix A Technical Support . . 41

Index .... . 43

# List of Figures

Figure 2-1. Typical ReadyBoard and PC/104 Module Stack .. 3

Figure 2-2. PC/104 Modules Stacked on a ReadyBoard 820. 4

Figure 2-3. Functional Block Diagram . 8

Figure 2-4. Component Locations . 10

Figure 2-5. Connector Pin Identifications...... .... 12

Figure 2-6. Connector Locations . 12

Figure 2-7. I/O Panel Dimensions.... .. 15

Figure 3-1. RS485 Serial Port Implementation .. . 23

# List of Tables

Table 2-1. Major Integrated Circuit Descriptions and Functions..... 9

Table 2-2. Header and Connector Descriptions . .. 10

Table 2-3. Additional Component Descriptions ...... .... 13

Table 2-4. Jumper Settings . . 13

Table 2-5. Power Supply Requirements. . 14

Table 2-6. Environmental Requirements ..... .. 14

Table 2-7. Weight and Footprint Dimensions . .. 15

Table 3-1. Channel Interrupt Assignments . . 19

Table 3-2. Memory Map ............ .. 20

Table 3-3. I/O Address Map ........ .. 20

Table 3-4. Floppy/Parallel Interface Pin/Signal Descriptions (J14) . . 21

Table 3-5. Serial A (COM1 and COM2) Interface Pin/Signal Descriptions (J18) . .. 24

Table 3-6. Serial B (COM3 and COM4) Interface Pin/Signal Descriptions (J15) ....... ... 25

Table 3-7. USB 2 & 3 Interface Pin/Signal Descriptions (J4) . . 27

Table 3-8. USB 4 & 5 Interface Pin/Signal Descriptions (J11) .. . 27

Table 3-9. Audio Interface Pin/Signal Descriptions (J20) . 28

Table 3-10. PanelLink Pin/Signal Descriptions (J5) .. . 29

Table 3-11. LVDS Interface Pin/Signal Descriptions (J19).. .. 30

Table 3-12. Utility Interface Pin/Signal Descriptions (J16) .. 31

Table 3-13. User GPIO Signals Pin/Signal Descriptions (J12).. .. 32

Table 3-14. Infrared (IrDA) Interface Pin/Signal Descriptions (J6) . . 33

Table 3-15. SMBus Reserved Addresses. ..33

Table 3-16. SMBus Signals Pin/Signal Descriptions (J13) . ..33

Table 3-17. Power In Pin/Signal Descriptions (J1).. ..34

Table 3-18. Power On Header Pin/Signal Descriptions (J2).. ..35

Table 3-19. Optional System Fan Interface Pin/Signal Descriptions (J17) ...... ...35

Table 3-20. Wake Up Activities and Conditions ... ..37

Table A-1. Technical Support Contact Information.. ..41

# Purpose of this Manual

This manual is for designers of systems based on the ReadyBoard 820 Single Board Computer (SBC). The information in this manual helps designers create embedded systems based on specific design requirements.

Information provided in this reference manual includes:

• ReadyBoard 820 Specifications
Environmental requirements
Major integrated circuits (chips) and features implemented
ReadyBoard 820 connector/pin numbers and definitions
BIOS Setup information

Information not provided in this reference manual includes:

• Detailed chip specifications
• Internal component operation
• Internal registers or signal operations
Bus or signal timing for industry standard busses and signals

# References

The following list of references may help you successfully complete your design.

# Specifications

EPIC Specification Revision 1.0, January 2005
Web site: http://www.ampro.com/RP/EPIC\_Specification\_v1.0.pdf
• Audio CODEC 1997 Standard, including all revisions
For the latest version of the Audio (AC'97) standard developed by Intel Corporation, refer to:
Web site: http://inst.eecs.berkeley.edu/\~cs150/Documents/ac97\_r23.pdf
• Compact Flash Specification Revision 4.0, July 2006
For the latest revision of the Compact Flash specification, refer to the Compact Flash Association at:
Web site: http://www.CompactFlash.org

Chip specifications used on the ReadyBoard 820:

Intel Corporation and the Celeron® M 373 and Pentium® M 738 CPUs; the chips 915GME and 82801FBM ICH6-M, used for the Memory Hub (Northbridge/Video controller) and I/O Hub (Southbridge), respectively.

Web site: http://www.intel.com

Winbond Electronics, Corp. and the W83627HF chip used for the Super I/O controller

Web site: http://www.winbond-usa.com/products/winbond\_products/pdfs/PCIC/627hf.pdf

Fintek and the F81216D chip used for the Secondary I/O (LPC UART) controller (48-pin)

Web site: http://www.fintek.com.tw/eng/

Intel Corporation and the Gigabit Ethernet PCI Express 82573V, used for the Gigabit Ethernet controller.

Web site: http://www.intel.com/design/network/products/lan/controllers/82573.htm

• Intel Corporation and the 82551QM, used for the Fast Ethernet controller.

Web site: http://www.intel.com/design/network/products/lan/controllers/82551qm.htm

# NOTE

If you are unable to locate the datasheets using the links provided, search the internet to find the manufacturer’s web site and locate the documents you need.

This overview presents general information about the EPIC form factor and the ReadyBoard 820 Single Board Computer (SBC). After reading this chapter you should understand:

EPIC architecture
Product Description
. ReadyBoard 820 features
• Major components
• Connectors
. Specifications

# EPIC Architecture

In 2004, five companies collaborated to fill the void between the EBX size and the PC/104 size with a new industry standard form factor (115mm x 165mm, or 4.5" x 6.5") called “Embedded Platform for Industrial Computing™ (EPIC).” The EPIC standard principally defines physical size, mounting hole pattern, and power connector locations. It does not specify processor type or electrical characteristics. There are recommended connector placements for I/O, graphics, and memory expansion. This embedded SBC standard ensures that embedded system OEMs can standardize their designs and that full featured embedded computing solutions can be designed into even more space constrained environments than ever before.

The EPIC standard boasts the same highly flexible and adaptable system expansion as EBX, allowing easy and modular addition of functions such as Firewire or wireless networking not usually contained in standard product offerings. The EBX system expansion is based on popular existing industry standards, PC/104™, PC/104-Plus™, and PCI-104™. PC/104 places the ISA bus on compact 3.6" x 3.8" modules with selfstacking capability. PC/104-Plus adds the power of a PCI bus to PC/104 while retaining the basic form factor, but PCI-104 expansion cards only provide the PCI Bus to the PC/104 form factor. Using PC/104 expansion cards, an EPIC board can be easily adapted to meet a variety of embedded applications. See Figures 2-1 and 2-2.

The EPIC standard also brings stability to the mid-sized embedded board market and offers OEMs assurance that a wide range of products will be available from multiple sources – now and in the future. The EPIC specification is freely available to all interested companies, and may be used without licenses or royalties. For further technical information on the EPIC standard, visit the web site at: http://www.epic-sbc.org.

![screws (4) or\n(0.6 inch spacers (4)\nfor next board)\nPC/104 Module\n0.6 inch spacers (4)\nPC/104 Plus Module\nPCI Bus\nStackthrough\nConnectors\n0.8 inch spacers (4)\nReadyBoard (EPIC-Compatible)\nnuts (4)\nor chassis standoffs\nISABus\nExpansion\nStackthrough\nConnectors\nI/O\nConnectors\nEPICstackthru](.50-1z064-1000-rb820-refman/fc88c7a257ba9ef640246c1b4ecc8db5c65fc6ab7354365f9e5fd9dd3c04cdec.jpg)

Figure 2-1. Typical ReadyBoard and PC/104 Module Stack

# Product Description

The ReadyBoard 820 is a mid-sized, EPIC-compatible, high quality single-board system, which contains all the component subsystems of a PC/AT PCI motherboard plus the equivalent of up to 4 PCI expansion boards. The ReadyBoard 820 is based on the ultra high performance, high-integration, Intel Celeron M or Pentium M processors. One of these processors with the matching chipset give designers a complete integration solution based on the EPIC form factor that conforms to the Revision 1.0 of the EPIC standard.

Each ReadyBoard 820 incorporates an Intel® 915GME chipset for the Memory Hub (Northbridge) and I/O Hub (Southbridge) controllers. The chipset consists of the Intel 82915GME memory hub, which controls graphics and memory interfaces and the Intel 82801FBM I/O Hub Controller which controls I/O functions. The Winbond Electronics Corp. Super I/O controller, W83627HF, adds I/O functions. Together, the Intel, Winbond, and Fintek chips provide four serial ports, a floppy or EPP/ECP parallel port, four USB 2.0 ports, two SATA ports, PS/2 keyboard and mouse interfaces, an Ultra/DMA 33/66/100 IDE controller supporting two IDE drives or one IDE drive and one Compact Flash socket, AGP 4X graphics equivalent controller, which provides CRT and LVDS flat panel video interfaces for the most popular flat panels, and an audio AC’97 CODEC. The ReadyBoard 820 also supports two independent Ethernet interfaces, 10/100BaseT and 1000BaseT, and up to 2 GB of non-ECC DDR2 RAM in a single 200-pin SODIMM socket.

The ReadyBoard 820 can be expanded through the PCI-104 expansion bus to accept PCI-104 cards that offer compact, self-stacking, modular expandability for additional system functions. The PCI-104 bus only implements the signal set for the PCI bus and is available on the 120-pin (4 rows of 30 pins) expansion bus connector. If required for an application, the PC/104 bus—an embedded system version of the signal set provided on a desktop PC's ISA bus—is provided by the optional ADLINK MiniModule ISA expansion board. The PCI bus operates at 33 MHz clock speed, and if included as an option, the ISA bus operates at 8 MHz clock speed. See Figure 2-2.

Among the many embedded enhancements on the ReadyBoard 820 that ensure embedded system operation and application versatility are a watchdog timer, serial console support, battery-free boot, customizable logo screen, on-board high-density Compact Flash socket, and ACPI support for sleep states.

The ReadyBoard 820 is particularly well suited to embedded applications by meeting the size, power consumption, temperature range, quality, and reliability demands of embedded system applications. It can be stacked with ADLINK MiniModules™ or other PCI-104 compliant expansion boards, or it can be used as a powerful computing engine. The ReadyBoard 820 requires only a +5V power supply.

![Screws (4)\nPC/104 Module\n0.6 inch Spacers (4)\nAmpro MiniModule ISA\nPCI Stackthrough Connectors\n0.6 inch Spacers (4)\nPC/104-Plus Module\nPCI Stackthrough Connectors\n0.8 inch Spacers (4)\nReadyBoard 820 (EPIC-Compatible)\nNuts (4)\nor Chassis Standoffs\nRB820stackhru\nISABus Expansion Stackthrough Connectors\nI/O Connectors](.50-1z064-1000-rb820-refman/8e919b518d0aa04c2e18916ebaa8c71e0f8ad7791606def2e94bc0d0b87d8280.jpg)

Figure 2-2. PC/104 Modules Stacked on a ReadyBoard 820

# Board Features

# CPU Features

Provide 1.0 GHz Low Voltage (LV) Celeron M 373 or 1.4GHz Low Voltage (LV) Pentium® M 738 processors
Support a Front Side Bus (FSB) of 400MHz

# • Memory

♦ Provides a single standard 200-pin DDR2 SODIMM socket
Supports a single +1.8V DDR2 SODIMM up to 2GB
Supports up to 2GB DDR2 (400MHz) SDRAM
Supports unregistered/unbuffered non-ECC DDR2 SDRAM

# PCI-104 Bus Interface

Supports PCI 2.3 standard
♦ Supports 33 MHz PCI Bus speed
Supports optional PC/104 standard (add-on MiniModule ISA expansion board) at 8 MHz

# Serial ATA Interface (SATA)

♦ Provides two 7-pin SATA ports
Provides 1.5 GB/second data transfer rate

# . IDE Interface

♦ Provides one enhanced IDE controller (2 devices)
♦ Provides one 44-pin IDE connector
Supports dual bus master mode
Supports Ultra DMA 33/66/100 modes
Supports ATAPI and DVD peripherals
Supports IDE native and ATA compatibility modes

# Floppy/Parallel Interface

Shared floppy/parallel connector
Supports one floppy disk drive (1 standard 34-pin floppy drive)
Supports all standard PC/AT formats: 360 kB, 1.2 MB, 720 kB, 1.44 MB, 2.88 MB
Supports standard printer port
Supports IEEE standard 1284 protocols of EPP and ECP outputs
Bi-directional data lines
Supports 16 byte FIFO for ECP mode

# • USB Ports

♦ Provide three root USB hubs
Provide six USB ports
A Provide two standard USB connectors (USB 0 and 1) and two 10-pin headers (USB 2 and 3 and USB 4 and 5)
Support USB bootable devices

Support USB 2.0 and legacy USB v1.1
Provide over-current fuses on board

# • Serial Ports

♦ Provide four buffered serial ports with full handshaking
♦ Provide two 20-pin headers for four serial ports
Provide 16550-equivalent controllers, each with a built-in 16-byte FIFO buffer
Support RS232 capability on all four ports
Support full modem capability on three of the four ports
Support RS485 or RS422 operation on two of the four ports (COM3 & COM4)
Support programmable word length, stop bits, and parity
♦ Support 16-bit programmable baud-rate generator and an interrupt generator

# Infrared Interface

♦ Provides a five-pin IrDA interface header
Supports IrDA v1.1
Supports HPSIR and ASKIR infrared modes
Supports IR mode select from the Super I/O chip

# Keyboard/Mouse Interface

♦ Provides PS/2 keyboard interface (shared with mouse)
♦ Provides PS/2 mouse interface (shared with keyboard)
Provides shared over-current fuse

# • Audio Interface

Supports AC'97 audio standard
♦ AC'97 CODEC on board
Provides non-amplified Stereo Line In/Out
♦ Provides non-amplified MIC in (Mono)

# Ethernet Interface – Gigabit and 10/100

♦ Includes two fully independent RJ45 Ethernet ports
♦ Integrated LEDs on each port (Link/Activity and Speed)
Supports IEEE 802.3 10BaseT/100BaseTX compatible physical layer
Supports IEEE 802.11 10BaseT/100BaseTX/1000BaseT compatible physical layer
Supports auto-negotiation for speed, duplex mode, and flow control
Supports full duplex or half-duplex mode

Full-duplex mode supports transmit and receive frames simultaneously
Supports IEEE 802.3x flow control in full duplex mode
Half-duplex mode supports enhanced proprietary collision reduction mode

Supports LAN Boot

Video Interfaces (CRT/PanelLink/LVDS)

Support CRT (2048x1536) with 64MB BIOS dependent UMA (Unified Memory Architecture)
Integrated graphics controller
♦ PanelLink outputs (allow capacity to bring out TMDS signals to a DVI connector)
♦ LVDS outputs (1 or 2 channel, four differential signals: 3-bits + clock)

Miscellaneous

♦ Provides real-time clock (RTC) with replaceable battery
Supports battery-free boot
♦ Provides external battery connection for RTC operation
Provides user GPIO interface header
Thermal and voltage monitoring
♦ Provides connector for optional CPU fan (+12 volt power supply required)
Supports a customizable Logo (Splash) Screen
Supports Serial Console
♦ Provides Watchdog Timer

# Block Diagram

Figure 2-3 shows the functional components of the ReadyBoard 820.
![Based on the provided flowchart, here is an accurate and concise description of the labeled blocks and their connections:\n\n**Central Processing & Memory System (Top Section)**\n*   **Blocks:** Intel Celeron M or Pentium M CPU, Memory Hub 82915GME (Northbridge), CRT VGA, LVDS LCD, PanelLink, DDR2 SODIMM, Memory Bus, Clock, Temp.\n*   **Connections:**\n    *   **Intel Celeron M or Pentium M CPU** connects bidirectionally to **Memory Hub 82915GME (Northbridge)**.\n    *   **Memory Hub 82915GME (Northbridge)** connects bidirectionally to **CRT VGA**, **LVDS LCD**, and **PanelLink**.\n    *   **Memory Hub 82915GME (Northbridge)** connects via **Memory Bus** bidirectionally to **DDR2 SODIMM**.\n    *   **Clock** connects to **Intel Celeron M or Pentium M CPU** and **Temp**.\n    *   **SMBus** connects **Memory Hub 82915GME (Northbridge)**, **DDR2 SODIMM**, **Clock**, **Temp**, and **I/O Hub 82801FBM (Southbridge) (ICH6-M)**.\n\n**I/O Hub & Peripheral Controllers (Middle Section)**\n*   **Blocks:** I/O Hub 82801FBM (Southbridge) (ICH6-M), PCIe Bus, AC'97 Link, AC'97 CODEC, PCI Bus, PATA, SATA, IDE, IDE Devices, (HDDs, CD-ROM, etc.), Compact Flash, USB 2.0, USB Port 0 through USB Port 5.\n*   **Connections:**\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **PCIe Bus** bidirectionally to **Ethernet Controller 82573V**.\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **AC'97 Link** to **AC'97 CODEC**.\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **PCI Bus** bidirectionally to **Ethernet Controller 82551QM** and **PCI-104 Bus Connector**.\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **PATA** bidirectionally to **IDE**. **IDE** connects to **IDE Devices, (HDDs, CD-ROM, etc.)**, which connects to **Compact Flash**.\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **SATA** bidirectionally to **SATA**.\n    *   **I/O Hub 82801FBM (Southbridge) (ICH6-M)** connects via **USB 2.0** to the stack of **USB Port 0** through **USB Port 5**.\n\n**Ethernet & Magnetics (Left Side)**\n*   **Blocks:** Ethernet Controller 82573V, Ethernet Controller 82551QM, PCI-104 Bus Connector, Magnetics-RJ45 (appears twice).\n*   **Connections:**\n    *   **Ethernet Controller 82573V** connects to the top **Magnetics-RJ45**.\n    *   **Ethernet Controller 82551QM** connects to the bottom **Magnetics-RJ45** and **PCI-104 Bus Connector**.\n    *   **PCI-104 Bus Connector** connects to the bottom **Magnetics-RJ45**.\n\n**Super I/O & LPC Bus (Bottom Section)**\n*   **Blocks:** Super I/O W83627HF, Floppy/Parallel, CPU Fan, IrDA 1.1, Keyboard/Mouse, COM1, COM2, RS232, GPIO (User Defined), LPC Bus, 512kB ROM BIOS, LPC I/O (Secondary) F81216D, COM3, COM4, RS232/RS422/RS485.\n*   **Connections:**\n    *   **LPC Bus** connects **I/O Hub 82801FBM (Southbridge) (ICH6-M)** to **Super I/O W83627HF**, **LPC I/O (Secondary) F81216D**, and **512kB ROM BIOS**.\n    *   **Super I/O W83627HF** connects bidirectionally to **Floppy/Parallel**, **CPU Fan**, **IrDA 1.1**, **Keyboard/Mouse**, **COM1**, **COM2**, and **GPIO (User Defined)**. (**COM1** and **COM2** are labeled under **RS232**).\n    *   **LPC I/O (Secondary) F81216D** connects to **COM3** and **COM4**. (**COM3** and **COM4** are labeled under **RS232/RS422/RS485**).](.50-1z064-1000-rb820-refman/648c954d49067db72d3c3a5d0e7a77d354b5ac46afa0961a23a7e728da926048.jpg)

Figure 2-3. Functional Block Diagram

# Major Integrated Circuits

Table 2-1 lists the major Integrated Circuits (ICs) on the ReadyBoard 820, including a brief description of each, and Figure 2-4 shows the locations of the major chips.

Table 2-1. Major Integrated Circuit Descriptions and Functions

<table><tr><td>Chip Type</td><td>Mfg.</td><td>Model</td><td>Description</td><td>Function</td></tr><tr><td>CPU (U2)</td><td>Intel</td><td>Celeron M Pentium M</td><td>LV 1.0GHz (Celeron M) or LV 1.4GHz (Pentium M)</td><td>Embedded CPU</td></tr><tr><td>Memory Hub (U3)</td><td>Intel</td><td>915GME</td><td>Northbridge - Memory and Video functions</td><td>Memory and Video</td></tr><tr><td>I/O Hub (U4)</td><td>Intel</td><td>82801FB (ICH6-M)</td><td>Southbridge - Provides some of the I/O functions (HDD, Audio, USB, LAN, PCI)</td><td>I/O Functions</td></tr><tr><td>Super I/O (U8)</td><td>Winbond</td><td>W83627HF</td><td>Provides most of remaining I/O functions (FDD, COM1/2, KB, MS, LPT, Fan, IrDA)</td><td>I/O Functions</td></tr><tr><td>LPC (I/O) UART Controller (U20 - on back of the board)</td><td>Fintek</td><td>F81216D</td><td>LPC controller for Serial Ports 3 &amp; 4 (COM 3 &amp; 4)</td><td>UART (I/O) Controller</td></tr><tr><td>Audio &#x27;97 CODEC (U21 - on back of the board)</td><td>Realtek</td><td>ALC655</td><td>Audio &#x27;97 CODEC for audio In/Out signals</td><td>Audio In/ Out</td></tr><tr><td>Ethernet Controller (U11)</td><td>Intel</td><td>82573V</td><td>Gigabit Ethernet – This chip provides one independent 1000BaseT network channel</td><td>Ethernet function</td></tr><tr><td>Ethernet Controller (U10)</td><td>Intel</td><td>82551QM</td><td>Fast Ethernet – This chip provides one independent 10/100BaseTX network channel</td><td>Ethernet function</td></tr></table>

![U8\nU2\nU3\nU10\nU11\nU4](.50-1z064-1000-rb820-refman/83872bad0123c7208ea3346c60ef92e8d37545d8a53c2b91d27d0f866f965a7e.jpg)

Figure 2-4. Component Locations

# Header and Connector Definitions

Table 2-2 describes the headers and connectors shown in Figure 2-6. All I/O headers and connectors use 0.100" (2.54mm) pitch unless otherwise indicated.

Table 2-2. Header and Connector Descriptions

<table><tr><td>Jack #</td><td>Signal/Device</td><td>Description</td></tr><tr><td>BT1</td><td>RTC Battery (B1)</td><td>2-pin, 0.049" (1.25mm) header for battery input</td></tr><tr><td>D6</td><td>Power and IDE Activity LEDs</td><td>Yellow diode indicates IDE activity, and green diode indicates power activity. Reside on the ReadyBoard 820.</td></tr><tr><td>DIMM1</td><td>SODIMM (on back of the board)</td><td>200-pin socket for DDR2 SODIMM</td></tr><tr><td>J1</td><td>Power In</td><td>4-pin, 0.200" (5.08mm) header for input power +5V, +12V, GND</td></tr><tr><td>J2</td><td>Power On</td><td>3-pin, 0.079" (2mm) header for Power On and +5V standby voltages</td></tr><tr><td>J3</td><td>PCI-104</td><td>120-pin, 0.079" (2mm) connector for PCI bus</td></tr><tr><td>J4</td><td>USB 2 &amp; 3</td><td>10-pin, 0.079" (2mm) header provides USB2 and USB3 output</td></tr><tr><td>J5</td><td>PanelLink</td><td>16-pin, 0.079" (2mm) header for Digital Visual Interface (DVI) output</td></tr><tr><td>J6</td><td>IrDA</td><td>5-pin, header for IrDA signals</td></tr><tr><td>J7</td><td>Factory Only</td><td>Not loaded</td></tr><tr><td>J8</td><td>SATA1</td><td>7-pin connector for serial ATA</td></tr><tr><td>J9</td><td>IDE</td><td>44-pin, 0.079" (2mm) header for the IDE interface</td></tr><tr><td>J10</td><td>SATA0</td><td>7-pin connector for serial ATA</td></tr><tr><td>J11</td><td>USB 4 &amp; 5</td><td>10-pin, 0.079" (2mm) header provides USB4 and USB5 output</td></tr><tr><td>J12</td><td>GPIO</td><td>10-pin, 0.079" (2mm) header for GPIO signals</td></tr><tr><td>J13</td><td>SMBus</td><td>5-pin, 0.079" (2mm) SMBus header for external device connection</td></tr><tr><td>J14</td><td>Floppy/Parallel Port</td><td>26-pin, 0.079" (2mm) header for floppy/parallel port interface</td></tr><tr><td>J15</td><td>Serial B</td><td>20-pin, 0.079" (2mm) header for Serial ports 3 &amp; 4 (COM3 &amp; COM4)</td></tr><tr><td>J16</td><td>Utility</td><td>5-pin, header for external Battery, Reset, Speaker</td></tr><tr><td>J17</td><td>Fan</td><td>3-pin, header provides +5v, tach, and ground to fan</td></tr><tr><td>J18</td><td>Serial A</td><td>20-pin, 0.079" (2mm) header for Serial ports 1 &amp; 2 (COM1 &amp; COM2)</td></tr><tr><td>J19</td><td>Video (LVDS)</td><td>30-pin, 0.079" (2mm) header for LVDS video display</td></tr><tr><td>J20</td><td>Audio In/Out</td><td>16-pin, 0.079" (2mm) header for Line In L/R, Line Out L/R, Mic in</td></tr><tr><td>J21</td><td>Fast 10/100 Ethernet + LEDs</td><td>14-pin connector for 8-pin RJ45 and LEDs for Ethernet port</td></tr><tr><td>J22</td><td>Gigabit Ethernet + LEDs</td><td>14-pin connector for 8-pin RJ45 and LEDs for Ethernet port</td></tr><tr><td>J23A/B</td><td>USB 0 &amp; 1</td><td>8-pin connector for two 4-pin interfaces provides USB0 and USB1 output</td></tr><tr><td>J24</td><td>Keyboard/Mouse</td><td>6-pin, 0.079" (2mm) PS/2 Keyboard/Mouse connector (dual output cable)</td></tr><tr><td>J25</td><td>Reset Switch</td><td>4-pin, push-button switch for hard reset</td></tr><tr><td>J26</td><td>Video (CRT VGA)</td><td>15-pin connector for output to a CRT monitor</td></tr><tr><td>J27</td><td>Compact Flash (on back of the board)</td><td>50-pin, 0.050" (1.27mm) socket accepts Compact Flash cards (Type I or II)</td></tr></table>

# NOTE

The pinout tables in Chapter 3 of this manual identify pin sequence using the following methods: A 20-pin header with two rows of pins, using odd/even numbering, where pin 2 is directly across from pin 1, is noted as 20-pin, 2 rows, odd/ even (1, 2). Alternately, a 20-pin connector using consecutive numbering, where pin 11 is directly across from pin 1, is noted in this way: 20-pin, 2 rows, consecutive (1, 11). The second number in the parenthesis is always directly across from pin-1. See Figure 2-5.

![| Row/Column | Value |\n| ---------- | ----- |\n| Odd/Even   | 19    |\n| Two rows   | 9     |\n| Odd/Even   | 7     |\n| Odd/Even   | 5     |\n| Odd/Even   | 3     |\n| Odd/Even   | 1     |\n| Consecutive| 10    |\n| Consecutive| 5     |\n| Consecutive| 4     |\n| Consecutive| 3     |\n| Consecutive| 2     |\n| Consecutive| 1     |](.50-1z064-1000-rb820-refman/659fb07e21f6ffd958a096fae879f0d72ff79a005feae414b060f36abc292fdd.jpg)

Figure 2-5. Header Pin Identifications

![J15 JP5 J12\nJ17\nJ18\nJP6\nJP7\nJ26 J19\nJ21\nJ22\nJ23\nF1\nJ24\nJ25\nD6\nJ13 JP3 JP2\nJ16\nJ11 J14 JP4 BT1 J10 J8 J4\nJ1 J2 JP1\nJ3\nJ5\nJ6 RB820 Conn View_b](.50-1z064-1000-rb820-refman/82f1f4b5f86385ee6f8cf7102a33af3e8d06bbd3f9a0d805d855490bbe157e53.jpg)

Figure 2-6. Headerand Connector Locations

NOTE Pin 1 is shown as a black pin (square or round) on all headers in all illustrations.

# Additional Components

Fuse F1, in Table 2-3, is shown in Figure 2-6. Fuses F2, F3, and F4 can be found on the back of the board.

Table 2-3. Additional Component Descriptions

<table><tr><td>Component</td><td>Description</td></tr><tr><td>Fuse F1(on front of the board)</td><td>Auto reset, 1.1A, overcurrent fuse for the Keyboard/Mouse (J24)</td></tr><tr><td>Fuse F2(on back of the board)</td><td>Auto reset, 1.6A, overcurrent fuse for the USB 2 &amp; 3 (J4)</td></tr><tr><td>Fuse F3(on back of the board)</td><td>Auto reset, 1.6A, overcurrent fuse for the USB 4 &amp; 5 (J11)</td></tr><tr><td>Fuse F4(on back of the board)</td><td>Auto reset, 1.6A, overcurrent fuse for the USB 0 &amp; 1 (J23)</td></tr></table>

# Jumper Header Definitions

Table 2-4 describes the jumper headers shown in Figure 2-6 on page 12.

Table 2-4. Jumper Settings

<table><tr><td>Jumper #</td><td>Installed</td><td>Removed/Installed</td></tr><tr><td>JP1* – PC/104+ SERIRQ (SerialIRQ)</td><td>Enabled (pins 1-2)</td><td>Disabled (removed) Default</td></tr><tr><td>JP2 – Clear CMOS Setup</td><td>Normal (pins 1-2) Default</td><td>Clear CMOS Setup (pins 2-3)</td></tr><tr><td>JP3 – Compact Flash Voltage Setup</td><td>+3.3V (pins 1-2)</td><td>+5V (pins 2-3) (removed) Default</td></tr><tr><td>JP4 – Compact Flash Card Setup</td><td>Master (pins 1-2)</td><td>Slave (removed) Default</td></tr><tr><td>JP5 – COM3 RS422/485</td><td>Termination (pins 1-2)</td><td>No Termination (removed) Default</td></tr><tr><td>JP5 – COM4 RS422/485</td><td>Termination (pins 3-4)</td><td>No Termination (removed) Default</td></tr><tr><td>JP6 – LCD Backlight Voltage Setup</td><td>+5V (pins 1-2) Default</td><td>+12V (pins 2-3)</td></tr><tr><td>JP7 – LCD Voltage Setup</td><td>+3.3V (pins 1-2) Default</td><td>+5V (pins 2-3)</td></tr></table>

NOTE \*The ISA interrupts are required on pin 31 of the PCI-104 connector, when using the MiniModule ISA board. Use the ISA IRQ jumper (JP1) to enable ISA interrupts. For full PCI-104 compatibility, the jumper should be removed (default setting). Refer to the MiniModule ISA manual for more information.

# Specifications

# Power Specifications

Table 2-5 lists the power requirements for the ReadyBoard 820.
Table 2-5. Power Supply Requirements

<table><tr><td>Parameter</td><td>1.0GHz Intel Celeron M Characteristics</td><td>1.4GHz Intel Pentium M Characteristics</td></tr><tr><td>Input Type</td><td>Regulated DC voltages</td><td>Regulated DC voltages</td></tr><tr><td>In-rush Current</td><td>8.06A (40.30W)</td><td>8.06A (40.30W)</td></tr><tr><td>Idle Power</td><td>2.51A (12.54W)</td><td>2.75A (13.75W)</td></tr><tr><td>BIT Current</td><td>3.62A (18.12W)</td><td>4.20A (21.02W)</td></tr></table>

# Operating configurations:

In-rush operating configuration includes video and 512MB RAM.
Idle operating configuration includes the in-rush configuration as well as one IDE hard drive with Windows XP, keyboard, and mouse.
BIT (Burn-In-Test) operating configuration includes idle configuration as well as four serial loop-backs, one on-board Compact Flash drive with 64MB Compact Flash, two Ethernet connections, two USB Compact Flash readers with 64MB Compact Flash, two SATA hard drives, one external-power USB CD-ROM, one USB Jump drive.

# Environmental Specifications

Table 2-6 provides the most efficient operating and storage condition ranges required for this board.
Table 2-6. Environmental Requirements

<table><tr><td></td><td>Parameter</td><td>1.0MHz Celeron M Conditions</td><td>1.4MHz Pentium M Conditions</td></tr><tr><td rowspan="2">Temperature</td><td>Operating</td><td>+0 to +60°C(+32° to +140°F)</td><td>+0 to +60°C(+32° to +140°F)</td></tr><tr><td>Storage</td><td>-20° to +75°C(-4° to +167°F)</td><td>-20° to +75°C(-4° to +167°F)</td></tr><tr><td rowspan="2">Humidity</td><td>Operating</td><td>5% to 90%relative humidity,non-condensing</td><td>5% to 90%relative humidity,non-condensing</td></tr><tr><td>Non-operating</td><td>5% to 95%relative humidity,non-condensing</td><td>5% to 95%relative humidity,non-condensing</td></tr></table>

# Thermal/Cooling Requirements

The CPU, Memory Hub (Northbridge), I/O Hub (Southbridge), and voltage regulators are the main sources of heat on the board. The ReadyBoard 820 is designed to operate at its maximum CPU speed of 1.0 or 1.4GHz. Both CPU versions, the I/O Hub, and the Memory Hub require heatsinks.

# Physical Specifications

Table 2-7 lists the physical dimensions of the board, and Figure 2-7 on page 15 shows the dimensions of the I/O panel.

Table 2-7. Weight and Footprint Dimensions

<table><tr><td>Item</td><td>Dimension</td><td rowspan="6">NOTE</td><td rowspan="6">Overall height is measured from the upper board surface to the highest permanent component (USB connector, J23) on the upper board surface. This measurement does not include the heatsinks or fan available for this board.</td></tr><tr><td>Weight</td><td>0.24kg. (0.52lbs.)</td></tr><tr><td>Height (overall)</td><td>16.51mm (0.65&quot;)</td></tr><tr><td>Width</td><td>115mm (4.5&quot;)</td></tr><tr><td>Length</td><td>165mm (6.5&quot;)</td></tr><tr><td>Thickness</td><td>1.57mm (0.062&quot;)</td></tr></table>

# Mechanical Specifications

Figure 2-7 shows the I/O panel dimensions of the ReadyBoard 820.
![Ethernet 1\nGigabit\nEthernet 2\nUSB 0 & 1\n(USB 0 Lower)\nKeyboard/\nMouse\nReset\nSwitch\nPower/IDE\nActivity\nLED\nCompact Flash Socket\nRB820/sideview_B\n165.1\n30.835\n1.701\n16.256\nMounting\nHole Center at (4) Corners (x 8 dims)\n15.849\n2.54\n13.893\n15.849\n1.727\n15.290\n1.391\n16.510\n12.954\n14.071\n1.828\n6.985\n2.032\n6.985\n9.906\n4.572\n9.398\n5.080\n7.899\n12.700\n47.625\n34.29\n8.588\nAll Dimensions in this drawing section are in Millimeters and are approximate.\nBoard thickness is 1.574mm](.50-1z064-1000-rb820-refman/d0ad7def803d74ef8a7a7c95b17f9ca1c89c154eae81b0b34649a0f9997975ea.jpg)

Figure 2-7. I/O Panel Dimensions

# Overview

This chapter discusses features of the ReadyBoard 820 in the following order:

Channel Interrupt Assignments
• Memory Map
• I/O Address Map
Floppy/Parallel Interface
. Serial Interfaces
. USB Interfaces

♦ USB 2.0 Support
♦ Legacy USB Support

Audio Interface

Video Interfaces

♦ CRT
♦ PanelLink
♦ LVDS

Infrared (IrDA)

Utility Interface

♦ External Power-On Switch
External Reset Switch
External Speaker (Beep)

. Miscellaneous

♦ Real Time Clock (RTC)
External Battery (BT1)
Temperature Monitoring
♦ User GPIO Signals
▲ Serial Console
Infrared (IrDA) Port
System Management Bus (SMBus)
Watchdog Timer

. Power Interface

+ Power In
♦ Power On
♦ Optional System Fan

• Power and Sleep States

♦ Power-On Switch
Sleep States (ACPI)
Wake Up Activities

# NOTE

ADLINK Technology, Inc. supports only the features/options tested and listed in this manual. The main integrated circuits (chips) used in the ReadyBoard 820 may provide more features or options than are listed for the ReadyBoard 820, but some of these chip features/options are not supported on the board and may not function as specified in the chip documentation.

This chapter does not include pinout tables for standard headers and connectors such as PCI-104, Ethernet RJ45, 44-pin IDE, and Compact Flash.

# Channel Interrupt Assignments

The channel interrupt assignments are shown in Table 3-1.

Table 3-1. Channel Interrupt Assignments

<table><tr><td>Device vs IRQ No.</td><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td><td>9</td><td>10</td><td>11</td><td>12</td><td>13</td><td>14</td><td>15</td></tr><tr><td>Timer</td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Keyboard</td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Secondary Cascade</td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>COM1</td><td></td><td></td><td></td><td></td><td>D</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>COM2</td><td></td><td></td><td></td><td>D</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>COM3</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td></td><td></td><td></td><td></td><td></td><td>D</td><td></td><td></td><td></td><td></td></tr><tr><td>COM4</td><td></td><td></td><td></td><td></td><td></td><td>D</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td></td><td></td><td></td><td></td></tr><tr><td>Floppy</td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Parallel</td><td></td><td></td><td></td><td></td><td></td><td>O</td><td></td><td>D</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>RTC</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>IDE</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>D</td><td></td></tr><tr><td>Math Coprocessor</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td></tr><tr><td>PS/2 Mouse</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>X</td><td></td><td></td><td></td></tr><tr><td>PCI INTA</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTB</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTC</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTD</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTE</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTF</td><td colspan="16">Automatically Assigned</td></tr><tr><td>PCI INTH</td><td colspan="16">Automatically Assigned</td></tr><tr><td>USB</td><td colspan="16">Automatically Assigned</td></tr><tr><td>VGA</td><td colspan="16">Automatically Assigned</td></tr><tr><td>Ethernet</td><td colspan="16">Automatically Assigned</td></tr></table>

Legend: D = Default, O = Optional, X = Fixed

NOTE The IRQs for the Ethernet, Video, and Internal LPC bus are automatically assigned by the BIOS Plug and Play logic. Local IRQs assigned during initialization can not be used by external devices.

# Memory Map

The following table provides the common PC/AT memory allocations. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management. Memory below 000500h is used by the BIOS.

Table 3-2. Memory Map

<table><tr><td colspan="2">Base Address</td><td>Function</td></tr><tr><td>00000000h</td><td>- 0009FFFFh</td><td>Conventional Memory</td></tr><tr><td>000A0000h</td><td>- 000AFFFFh</td><td>Graphics Memory</td></tr><tr><td>000B0000h</td><td>- 000B7FFFh</td><td>Mono Text Memory</td></tr><tr><td>000B8000h</td><td>- 000BFFFFh</td><td>Color Text Memory</td></tr><tr><td>000C0000h</td><td>- 000CFFFFh</td><td>Standard Video BIOS</td></tr><tr><td>000D0000h</td><td>- 000DFFFFh</td><td>Reserved for Extended BIOS</td></tr><tr><td>000E0000h</td><td>- 000EFFFFh</td><td>Extended System BIOS Area</td></tr><tr><td>000F0000h</td><td>- 000FFFFFFh</td><td>System BIOS Area (Storage and RAM Shadowing)</td></tr><tr><td>00100000h</td><td>- 04000000h</td><td>Extended Memory (If onboard VGA is enabled, then the amount of memory assigned is subtracted from extended memory)</td></tr><tr><td>FFF80000h</td><td>- FFFFFFFH</td><td>System Flash</td></tr></table>

# I/O Address Map

Table 3-3 shows the I/O address map. These are DOS-level addresses. The OS typically hides these physical addresses by way of memory management.

Table 3-3. I/O Address Map

<table><tr><td>Address (hex)</td><td>Subsystem</td></tr><tr><td>000-00F</td><td>Primary DMA Controller</td></tr><tr><td>020-021</td><td>Master Interrupt Controller</td></tr><tr><td>040-043</td><td>Programmable Interrupt Timer (Clock/Timer)</td></tr><tr><td>060-06F</td><td>Keyboard Controller</td></tr><tr><td>070-07F</td><td>CMOS RAM, NMI Mask Reg, RT Clock</td></tr><tr><td>080-09F</td><td>DMA Page Registers</td></tr><tr><td>092</td><td>Fast A20 gate and CPU reset</td></tr><tr><td>094</td><td>Motherboard enable</td></tr><tr><td>102</td><td>Video subsystem register</td></tr><tr><td>0A0-0BF</td><td>Slave Interrupt Controller</td></tr><tr><td>0C0-0DF</td><td>Slave DMA Controller #2</td></tr><tr><td>0F0-0FF</td><td>Math Coprocessor</td></tr><tr><td>1F0-1F8</td><td>IDE Hard Disk Controller</td></tr><tr><td>278-27F</td><td>Parallel Port</td></tr><tr><td>2E8-2FF</td><td>Serial Port 4 (COM4)</td></tr><tr><td>2F8-2FF</td><td>Serial Port 2 (COM2)</td></tr><tr><td>378-37F</td><td>Parallel Port (Standard and EPP)</td></tr><tr><td>3C0-3DF</td><td>VGA</td></tr><tr><td>3E8-3EF</td><td>Serial Port 3 (COM3)</td></tr><tr><td>3F0-3F7</td><td>Floppy Disk Controller</td></tr><tr><td>3F8-3FF</td><td>Serial Port 1 (COM1)</td></tr><tr><td>778-77A</td><td>Parallel Port (ECP Extensions) (Port 378+400)</td></tr><tr><td>CF8-CFF</td><td>PCIe bus Configuration Address and Data</td></tr></table>

# Floppy/Parallel Interface

The Super I/O controller (W83627HF) provides the floppy controller and the parallel port controller. The floppy controller and the parallel port controller share the same output connector (J14) on the board and the device selection is made in the BIOS Setup Utility.

Floppy Port Controller supports one floppy drive in the standard formats, such as 360 kB, 720 kB, 1.2 MB, 1.44 MB, or 2.88 MB drives.
• Parallel Port controller supports standard parallel, Bi-directional, ECP and EPP protocols.

# NOTE

Due to the multiplexed nature of the signals for the floppy and parallel ports, you can only connect one of these devices at a time. Refer to Chapter 4, BIOS Setup Utility later in this manual when selecting the floppy or parallel device in the BIOS Setup Utility. A reboot is necessary for the change of BIOS settings to take affect.

Table 3-4 describes the floppy/parallel port (J14) pin/signals with 26-pins, 2 rows, consecutive (1, 14) with 2 mm pin spacing.

Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-4. Floppy/Parallel Interface Pin/Signal Descriptions (J14)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>Strobe*</td><td>Parallel Strobe* – This is an output signal used to strobe data into the printer. I/O pin in ECP/EPP mode.</td></tr><tr><td>2</td><td>PD0INDEX*</td><td>Parallel Port Data 0 – These pins (0 to 7) provide parallel port data signals.Floppy Index – Detects head positioned over the beginning of a track.</td></tr><tr><td>3</td><td>PD1TRK0*</td><td>Parallel Port Data 1 – See pin-2 (PD0) for more information.Floppy Track 0 – Detects when head is positioned over track 0.</td></tr><tr><td>4</td><td>PD2WPRT*</td><td>Parallel Port Data 2 – See pin-2 (PD0) for more information.Floppy Write Protect – Senses if diskette is write protected.</td></tr><tr><td>5</td><td>PD3RDATA*</td><td>Parallel Port Data 3 – See pin-2 (PD0) for more information.Floppy Read Data – Raw serial bit stream from the drive for read operations.</td></tr><tr><td>6</td><td>PD4DSKCHG*</td><td>Parallel Port Data 4 – See pin-2 (PD0) for more information.Floppy Disk Change – Senses when drive door is open or the diskette has been changed since the last drive selection.</td></tr><tr><td>7</td><td>PD5</td><td>Parallel Port Data 5 – See pin-2 (PD0) for more information.</td></tr><tr><td>8</td><td>PD6</td><td>Parallel Port Data 6 – See pin-2 (PD0) for more information.</td></tr><tr><td>9</td><td>PD7</td><td>Parallel Port Data 7 – See pin-2 (PD0) for more information.</td></tr><tr><td>10</td><td>ACK*DS1*</td><td>Parallel Acknowledge * – This is a status output signal from the printer. A Low State indicates it has received the data and is ready to accept new data.Floppy Drive Select 1 – Select drive 1.</td></tr><tr><td>11</td><td>BUSYMTR1*</td><td>Parallel Busy – This is a status output signal from the printer. A High State indicates the printer is not ready to accept data.Floppy Motor Control 1 – Select motor on drive 1.</td></tr><tr><td>12</td><td>PEWDATA*</td><td>Parallel Paper End – This is a status output signal from the printer. A High State indicates it is out of paper.Floppy Write Data – Encoded data to the drive for write operations.</td></tr><tr><td>13</td><td>PSLCTWGATE*</td><td>Printer Select – This is a status output signal from the printer. A High State indicates it is selected and powered on.Floppy Write Enable – Drive signal to enable current flow in the write head.</td></tr><tr><td>14</td><td>AFD*DRVEN0*</td><td>Parallel Auto Feed* – This is a request signal into the printer to automatically feed one line after each line is printed.Floppy Drive Density Select Bit 0</td></tr><tr><td>15</td><td>ERR*HDSEL*</td><td>Parallel Error – This is a error status output signal from the printer. A Low State indicates an error condition on the printer.Floppy Head Select – Selects the side for Read/Write operations (0 = side 1, 1 = side 0)</td></tr><tr><td>16</td><td>PINIT*DIR*</td><td>Printer Initialize* – This signal is used to Initialize printer. Output in standard mode, I/O in ECP/EPP mode.Floppy Direction – Direction of head movement (0 = inward motion, 1 = outward motion).</td></tr><tr><td>17</td><td>SLINSTEP*</td><td>Parallel Select In – This output signal to the printer is used to select the printer. I/O pin in ECP/EPP mode.Floppy Step – Low pulse for each track-to-track movement of the head.</td></tr><tr><td>18</td><td>GND</td><td>Ground</td></tr><tr><td>19</td><td>GND</td><td>Ground</td></tr><tr><td>20</td><td>GND</td><td>Ground</td></tr><tr><td>21</td><td>GND</td><td>Ground</td></tr><tr><td>22</td><td>GND</td><td>Ground</td></tr><tr><td>23</td><td>GND</td><td>Ground</td></tr><tr><td>24</td><td>GND</td><td>Ground</td></tr><tr><td>25</td><td>GND</td><td>Ground</td></tr><tr><td>26</td><td>NC</td><td>Not Connected</td></tr></table>

# Serial Interfaces

The Super I/O (W83627HF) chip and the LPC UART controller (F81216D) provide the circuitry for the four serial ports. The Super I/O chip provides serial ports 1 and 2 through connector J18. The LPC UART controller provides serial ports 3 and 4 through connector J15. The four serial ports support the following features:

Four individual 16550-compatible UARTs
Programmable word length, stop bits and parity
16-bit programmable baud rate generator
Interrupt generator
• Loop-back mode
Four individual 16-bit FIFOs
. Serial A Interface

Serial Port 1 (COM1) supports RS232 and full modem support
Serial Port 2 (COM2) supports RS232 and full modem support

Serial B Interface

♦ Serial Port 3 (COM3) supports RS232/RS485/RS422 and full modem support
Serial Port 4 (COM4) supports RS232/RS485/RS422

# NOTE

The RS232/RS485/RS422 modes are selected in BIOS Setup under the Advanced/Super I/O Configuration menu for Serial ports 3 (COM3) and 4 (COM4). However, the RS232 mode is the default (Standard) for any serial port.

RS485 mode termination is selected with jumper connector JP5, pins 1-2 (COM3), and pins 3-4 (COM4), when the RS485 mode is selected in BIOS Setup.

To implement the two-wire RS485 mode on serial ports 3 or 4, you must tie the equivalent pins together for the selected port.

For example, on Serial Port 3, tie pin 3 to 5 and pin 4 to 6 at the Serial B interface header as shown in Figure 3-1. As an alternate, tie pin 2 to 3 and pin 7 to 8 on the DB9 connector for serial port 3 as shown in Figure 3-1. Refer to the following tables for the specific pin signals of serial ports 3 and 4 on the serial B connector.

The RS422 mode uses a four-wire interface and does not need any pins tied together, but you must select RS485 mode in BIOS Setup.

![Serial B Interface\nfor Serial Port 3\n(or COM3 Port)\nTop View\n19 9 7 5 3 1 Or\n20 10 8 6 4 2](.50-1z064-1000-rb820-refman/eec93f7a139abbc487fa4ad1aacc9b095dc043ed91b9d1301e5b18fd67714290.jpg)

![Standard DB9\nConnector\n(Male)\nFront View\n5 4 3 2 1\n9 8 7 6\nRB820_RS485_b](.50-1z064-1000-rb820-refman/6910255e9aa43f9c902cdf275c39fe7b3821e96713463af39f0d59c8ab6ea9f8.jpg)

Figure 3-1. RS485 Serial Port Implementation

Table 3-5. Serial A (COM1 and COM2) Interface Pin/Signal Descriptions (J18)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DCD1*</td><td>Data Carrier Detect 1 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open).</td></tr><tr><td>2</td><td>DSR1*</td><td>Data Set Ready 1 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR1 for overall readiness to communicate.</td></tr><tr><td>3</td><td>RXD1</td><td>Receive Data 1 – Serial port 1 receive data in</td></tr><tr><td>4</td><td>RTS1*</td><td>Request To Send 1 – Indicates Serial port 1 is ready to transmit data. Used as hardware handshake with CTS3 for low level flow control.</td></tr><tr><td>5</td><td>TXD1</td><td>Transmit Data 1 – Serial port 1 transmit data out</td></tr><tr><td>6</td><td>CTS1*</td><td>Clear To Send 1 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS1 for low level flow control.</td></tr><tr><td>7</td><td>DTR1*</td><td>Data Terminal Ready 1 – Indicates Serial port 1 is powered, initialized, and ready. Used as hardware handshake with DSR1 for overall readiness to communicate.</td></tr><tr><td>8</td><td>RI1*</td><td>Ring Indicator 1 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>9</td><td>GND</td><td>Ground</td></tr><tr><td>10</td><td>NC</td><td>Not connected</td></tr><tr><td>11</td><td>DCD2*</td><td>Data Carrier Detect 2 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open).</td></tr><tr><td>12</td><td>DSR2*</td><td>Data Set Ready 2 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR2 for overall readiness to communicate.</td></tr><tr><td>13</td><td>RXD2</td><td>Receive Data 2 – Serial port 2 receive data in</td></tr><tr><td>14</td><td>RTS2*</td><td>Request To Send 2 – Indicates Serial port 2 is ready to transmit data. Used as hardware handshake with CTS2 for low level flow control.</td></tr><tr><td>15</td><td>TXD2</td><td>Transmit Data 2 – Serial port 2 transmit data out</td></tr><tr><td>16</td><td>CTS2*</td><td>Clear To Send 2 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS2 for low level flow control.</td></tr><tr><td>17</td><td>DTR2*</td><td>Data Terminal Ready 2 – Indicates Serial port 2 is powered, initialized, and ready. Used as hardware handshake with DSR2 for overall readiness to communicate.</td></tr><tr><td>18</td><td>NC</td><td>Not connected</td></tr><tr><td>19</td><td>GND</td><td>Ground</td></tr><tr><td>20</td><td>NC</td><td>Not connected</td></tr></table>

Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.

Table 3-6. Serial B (COM3 and COM4) Interface Pin/Signal Descriptions (J15)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DCD3*</td><td>Data Carrier Detect 3 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR3 as part of the DTR3/DSR3 handshake.</td></tr><tr><td>2</td><td>DSR3*</td><td>Data Set Ready 3 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR3 for overall readiness to communicate.</td></tr><tr><td rowspan="2">3</td><td>RXD3</td><td>Receive Data 3 – Serial port 3 receive data in</td></tr><tr><td>RX3-</td><td>RX3- – If in RS485 or RS422 mode, this pin is Receive Data 3 -.</td></tr><tr><td rowspan="2">4</td><td>RTS3*</td><td>Request To Send 3 – Indicates Serial port 3 is ready to transmit data. Used as hardware handshake with CTS3 for low level flow control.</td></tr><tr><td>TX3+</td><td>TX3+ – If in RS485 or RS422 mode, this pin is Transmit Data 3 +.</td></tr><tr><td rowspan="2">5</td><td>TXD3</td><td>Transmit Data 3 – Serial port 3 transmit data out</td></tr><tr><td>TX3-</td><td>TX3- – If in RS485 or RS422 mode, this pin is Transmit Data 3 -.</td></tr><tr><td rowspan="2">6</td><td>CTS3*</td><td>Clear To Send 3 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS3 for low level flow control.</td></tr><tr><td>RX3+</td><td>RX3+ – If in RS485 or RS422 mode, this pin is Receive Data 3 -.</td></tr><tr><td>7</td><td>DTR3*</td><td>Data Terminal Ready 3 – Indicates Serial port 3 is powered, initialized, and ready. Used as hardware handshake with DSR3 for overall readiness to communicate.</td></tr><tr><td>8</td><td>RI3*</td><td>Ring Indicator 3 – Indicates external serial communications device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel.</td></tr><tr><td>9</td><td>GND</td><td>Ground</td></tr><tr><td>10</td><td>NC</td><td>Not connected</td></tr><tr><td>11</td><td>DCD4*</td><td>Data Carrier Detect 4 – Indicates external serial communications device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input will be driven by DTR4 as part of the DTR4/DSR4 handshake.</td></tr><tr><td>12</td><td>DSR4*</td><td>Data Set Ready 4 – Indicates external serial communications device is powered, initialized, and ready. Used as hardware handshake with DTR4 for overall readiness to communicate.</td></tr><tr><td rowspan="2">13</td><td>RXD4</td><td>Receive Data 4 – Serial port 4 receive data in</td></tr><tr><td>RX4-</td><td>RX4- – If in RS485 or RS422 mode, this pin is Receive Data 4 -.</td></tr><tr><td rowspan="2">14</td><td>RTS4*</td><td>Request To Send 4 – Indicates Serial port 4 is ready to transmit data. Used as hardware handshake with CTS4 for low level flow control.</td></tr><tr><td>TX4+</td><td>TX4+ – If in RS485 or RS422 mode, this pin is Transmit Data 4 +.</td></tr><tr><td rowspan="2">15</td><td>TXD4</td><td>Transmit Data 4 – Serial port 4 transmit data out</td></tr><tr><td>TX4-</td><td>TX4- – If in RS485 or RS422 mode, this pin is Transmit Data 4 -.</td></tr><tr><td rowspan="2">16</td><td>CTS4*</td><td>Clear To Send 4 – Indicates external serial communications device is ready to receive data. Used as hardware handshake with RTS4 for low level flow control.</td></tr><tr><td>RX4+</td><td>RX4+ – If in RS485 or RS422 mode, this pin is Receive Data 4 +.</td></tr><tr><td>17</td><td>DTR4*</td><td>Data Terminal Ready 4 – Indicates Serial port 3 is powered, initialized, and ready. Used as hardware handshake with DSR4 for overall readiness to communicate.</td></tr><tr><td>18</td><td>NC</td><td>Not connected</td></tr><tr><td>19</td><td>GND</td><td>Ground</td></tr><tr><td>20</td><td>NC</td><td>Not connected</td></tr></table>

Note: The shaded area denotes power or ground. Signals are listed in the following order: RS232 followed by RS485/RS422. The signals marked with \* = Negative true logic.

# USB Interfaces

The I/O Hub (82801FBM) provides the USB solution for both legacy UHCI controller and EHCI controller (USB 2.0) support. The I/O Hub (Southbridge) contains port-routing logic that determines which controller (UHCI or EHCI) handles the USB data signals. The PC-style (or Standard) connector (J23) provides two of the six USB ports: USB0 and USB1. The J4 header provides USB2 and USB3, and J11 provides USB4 and USB5.

# USB 2.0 Support

The I/O Hub (Southbridge) contains an Enhanced Host Controller Interface (EHCI) compliant host controller, which supports up to six high-speed USB 2.0 Specification compliant root ports. The higher speed USB 2.0 specification allows data transfers up to 480 Mbps using the same pins as the six full-speed/ low-speed USB UHCI ports. The I/O Hub (Southbridge) port-routing logic determines which of the controllers (UHCI or the EHCI) processes the USB signals.The USB 2.0 features implemented in the USB ports include the following:

One EHCI host controller for all six USB ports
Supports USB V2.0 Specification
Over-current fuses, located on the board, where USB0 and USB1 share a single fuse (F4), USB2 and USB3 share a single fuse (F2), and USB4 and USB5 share a single fuse (F3). See Table 2-3 on page 13.

# Legacy USB Support

The I/O Hub (Southbridge) supports three USB Universal Host Controller Interfaces (UHCI) and each Host Controller includes a root hub with two separate USB ports each, for a total of six USB ports. The USB Legacy features implemented in the USB ports include the following:

Three root hubs for six USB ports
Support for USB v1.1, UHCI with integrated physical layer transceivers
Improved arbitration latency for UHCI controllers
UHCI controllers support Analog Front End (AFE) embedded cell instead of USB I/O buffers to allow for USB high-speed signaling rates
• Three shared over-current fuses, located on the board, are used on all six USB ports

# USB2 and USB3

Table 3-7 describes USB 2 & 3, J4: 10-pins, 2 rows, odd/even (1, 2) with 2 mm pin spacing.

Table 3-7. USB 2 & 3 Interface Pin/Signal Descriptions (J4)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1, 2</td><td>VCC</td><td>USB Voltage – +5V through shared fuse (F2)</td></tr><tr><td>3</td><td>USBP2-</td><td>Universal Serial Bus Port 2 Data Negative</td></tr><tr><td>4</td><td>USBP3-</td><td>Universal Serial Bus Port 3 Data Negative</td></tr><tr><td>5</td><td>USBP2+</td><td>Universal Serial Bus Port 2 Data Positive</td></tr><tr><td>6</td><td>USBP3+</td><td>Universal Serial Bus Port 3 Data Positive</td></tr><tr><td>7, 8, 9, 10</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded area denotes power or ground.

# USB4 and USB5

Table 3-8 describes USB 4 & 5, J11: 10-pins, 2 rows, odd/even (1, 2) with 2 mm pin spacing.

Table 3-8. USB 4 & 5 Interface Pin/Signal Descriptions (J11)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1, 2</td><td>VCC</td><td>USB Voltage – +5V through shared fuse (F3)</td></tr><tr><td>3</td><td>USBP4-</td><td>Universal Serial Bus Port 2 Data Negative</td></tr><tr><td>4</td><td>USBP5-</td><td>Universal Serial Bus Port 3 Data Negative</td></tr><tr><td>5</td><td>USBP4+</td><td>Universal Serial Bus Port 2 Data Positive</td></tr><tr><td>6</td><td>USBP5+</td><td>Universal Serial Bus Port 3 Data Positive</td></tr><tr><td>7, 8, 9, 10</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded area denotes power or ground.

# Audio Interface

The audio solution on the ReadyBoard 820 is provided by the I/O Hub, 82801DBM (Southbridge) and the on-board Audio CODEC (ALC655). These two chips use a digital interface to communicate between the two, which is defined by AC’97 and is revision 2.3 compliant. The input or output signals for the audio interface go through the 16-pin connector (J20), which has the respective audio connections, and are listed in Table 3-9.

Audio CODEC (ALC655) features

AC’97 Rev 2.3 compliant
18-bit full duplex performance
Variable sampling rate at 1Hz resolution
Stereo (Left and Right) Line In
Stereo (Left and Right) Line Out
Microphone (mono) in

• PC Beep speaker signal also fed to CODEC for the Line Out (Left and Right) channels

Table 3-9. Audio Interface Pin/Signal Descriptions (J20)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1, 3</td><td>NC</td><td>Not Connected</td></tr><tr><td>2, 4, 7, 8, 11, 12, 13, 14, 16</td><td>GND_AUD</td><td>Audio ground</td></tr><tr><td>5</td><td>LINE_OUTL</td><td>Line Out signal left channel</td></tr><tr><td>6</td><td>LINE_OUTR</td><td>Line Out signal right channel</td></tr><tr><td>9</td><td>LINE_INL</td><td>Line in signal left channel</td></tr><tr><td>10</td><td>LINE_INR</td><td>Line in signal right channel</td></tr><tr><td>15</td><td>MICIN</td><td>Microphone signal in</td></tr></table>

Note: The shaded area denotes power or ground.

# Video Interfaces

The Memory Hub, 82915GME (Northbridge) provides the graphics control and video signals for traditional CRT monitors, DVI high-resolution displays, and LVDS flat panel displays. The Memory Hub (Northbridge) features are listed below.

Support for 2D/3D graphics with extensive set of instructions including:

3D rendering and display
BLT operations
• MPEG2 decode acceleration
• 3D overlay

# CRT features:

Support for an integrated 400-MHz, 24-bit RAMDAC to drive a progressive scan analog monitor and outputs to three, 8-bit DACs that provide the R, G, and B signals to the monitor
Support for resolutions up to 1600 x 1200 at 85-Hz refresh, or up to 2048x1536 at 75-Hz refresh
Support for a maximum allowable video frame buffer size of 64MB UMA (Unified Memory Architecture)

# PanelLink features:

Lossless (digital) transmission of video signal
Display hardware independence
Plug and play capabilities (EDID and DDC2B)
Digital and analog support in a single connector

# LVDS Flat Panel features:

Support for an integrated dual channel LFP Transmitter interface
Support for LVDS LCD panel resolutions up to UXGA (1600X1200)
Support for a maximum pixel format of 18 bpp with SSC supported frequency range from 25 MHz to 112 MHz (single channel/dual channel)
Support for 1 or 2 channel LVDS output
• The 82915GME chip supports the LVDS port on Pipe B of two pipelines

Support for the LVDS port independently or simultaneously with the Analog Display (CRT) port
• Support for Spread Spectrum Clocking; center and down spread support utilizing an external SSC clock
Support for panel up-scaling (to fit a smaller source image onto a specific native panel size) as well as panning and centering CRT interface

# PanelLink

This header provides the capacity to bring out the TMDS signals to a DVI (Digital Visual Interface) connector.

Table 3-10. PanelLink Pin/Signal Descriptions (J5)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>TDC2+</td><td>TMDS Data 2+</td></tr><tr><td>2</td><td>VCC5</td><td>+5 Volt Power</td></tr><tr><td>3</td><td>TDC2-</td><td>TMDS Data 2-</td></tr><tr><td>4</td><td>HPDET</td><td>Hot Plug Detect</td></tr><tr><td>5</td><td>TDC1+</td><td>TMDS Data 1+</td></tr><tr><td>6</td><td>GND</td><td>Digital Ground</td></tr><tr><td>7</td><td>TDC1-</td><td>TMDS Data 1-</td></tr><tr><td>8</td><td>GND</td><td>Digital Ground</td></tr><tr><td>9</td><td>TDC0+</td><td>TMDS Data 0+</td></tr><tr><td>10</td><td>SDADDC</td><td>DDC Data</td></tr><tr><td>11</td><td>TDC0-</td><td>TMDS Data 0-</td></tr><tr><td>12</td><td>SCLDDC</td><td>DDC Clock</td></tr><tr><td>13</td><td>TLC+</td><td>TMDS Clock+</td></tr><tr><td>14</td><td>GND</td><td>Digital Ground</td></tr><tr><td>15</td><td>TLC-</td><td>TMDS Clock-</td></tr><tr><td>16</td><td>GND</td><td>Digital Ground</td></tr></table>

Note: The shaded area denotes power or ground.

# LVDS Interface (Low Voltage Differential Signaling)

Table 3-11. LVDS Interface Pin/Signal Descriptions (J19)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td><td>Line</td><td>Channel</td><td rowspan="31">NOTE</td><td rowspan="31">Pins 17-26constitute 1st channelinterface oftwo channels,or a singlechannelinterface. Pins5-14constitute 2ndchannelinterface oftwo channels.</td></tr><tr><td>1</td><td>VCC_INTRV</td><td>JP6 = +5 or +12V source</td><td></td><td></td></tr><tr><td>2</td><td>VCC_LCD</td><td>JP7 = +3.3 or +5V source</td><td></td><td></td></tr><tr><td>3</td><td>GND</td><td>Ground</td><td rowspan="2">Gnd</td><td></td></tr><tr><td>4</td><td>GND</td><td>Ground</td><td></td></tr><tr><td>5</td><td>LVDSB_Clk+</td><td>Clock Positive Output</td><td rowspan="2">Clk</td><td rowspan="10">Channel 2</td></tr><tr><td>6</td><td>LVDSB_Clk-</td><td>Clock Negative Output</td></tr><tr><td>7</td><td>LVDSB_Y3</td><td>Not Connected</td><td rowspan="2">3</td></tr><tr><td>8</td><td>LVDSB_Y3</td><td>Not Connected</td></tr><tr><td>9</td><td>LVDSB_Y2+</td><td>Data Positive Output</td><td rowspan="2">2</td></tr><tr><td>10</td><td>LVDSB_Y2-</td><td>Data Negative Output</td></tr><tr><td>11</td><td>LVDSB_Y1+</td><td>Data Positive Output</td><td rowspan="2">1</td></tr><tr><td>12</td><td>LVDSB_Y1-</td><td>Data Negative Output</td></tr><tr><td>13</td><td>LVDSB_Y0+</td><td>Data Positive Output</td><td rowspan="2">0</td></tr><tr><td>14</td><td>LVDSB_Y0-</td><td>Data Negative Output</td></tr><tr><td>15</td><td>LVD_BKLTCtrl</td><td>Backlight Control</td><td></td><td></td></tr><tr><td>16</td><td>LCD_EN</td><td>LCD Enable</td><td></td><td></td></tr><tr><td>17</td><td>LVDS_Clk+</td><td>Data Positive Output</td><td rowspan="2">Clk</td><td rowspan="10">Channel 1</td></tr><tr><td>18</td><td>LVDS_Clk-</td><td>Data Negative Output</td></tr><tr><td>19</td><td>LVDS_Y3+</td><td>Not Connected</td><td rowspan="2">3</td></tr><tr><td>20</td><td>LVDS_Y3-</td><td>Not Connected</td></tr><tr><td>21</td><td>LVDS_Y2+</td><td>Data Positive Output</td><td rowspan="2">2</td></tr><tr><td>22</td><td>LVDS_Y2-</td><td>Data Negative Output</td></tr><tr><td>23</td><td>LVDS_Y1+</td><td>Data Positive Output</td><td rowspan="2">1</td></tr><tr><td>24</td><td>LVDS_Y1-</td><td>Data Negative Output</td></tr><tr><td>25</td><td>LVDS_Y0+</td><td>Data Positive Output</td><td rowspan="2">0</td></tr><tr><td>26</td><td>LVDS_Y0-</td><td>Data Negative Output</td></tr><tr><td>27</td><td>LDDCCLK</td><td>Clock</td><td></td><td></td></tr><tr><td>28</td><td>LDDCDATA</td><td>Data</td><td></td><td></td></tr><tr><td>29</td><td>LBKTLEN</td><td>Backlight Enable</td><td></td><td></td></tr><tr><td>30</td><td>NC</td><td>Not connected</td><td></td><td></td></tr></table>

Note: The shaded areas denote power or ground.

# Utility Interface

Power-On – This control signal externally is provided through a switch by connecting ground to pin 1 on the Utility connector (J16).
Reset Switch – This signal is provided externally through a switch by connecting ground to pin 3 on the Utility connector (J16). This signal line is shared with Reset Switch (J25).
PC Beep Speaker – The output signals from the Southbridge (82801FBM) and the Super I/O (W83627HF) are fed to pin 5 of the Utility connector (J16) through an OR circuit, and in conjunction with the +5V signal (pin 4), drives an external PC Beep speaker. The PC Beep speaker signal from the Southbridge is also fed to the on-board Audio CODEC to provide a PC Beep signal for the Line out connections.

Table 3-12. Utility Interface Pin/Signal Descriptions (J16)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>PS_On</td><td>Power On input (connect between pins 1 &amp; 2)</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>RST_SW</td><td>Reset Switch input or output (connect between pins 3 &amp; 2)</td></tr><tr><td>4</td><td>+5V</td><td>+5 Volts</td></tr><tr><td>5</td><td>Speaker</td><td>PC Beep Speaker + Output (connect between pins 5 &amp; 4)</td></tr></table>

Note: The shaded area denotes power or ground.

# Miscellaneous

# Real Time Clock (RTC)

The ReadyBoard 820 contains a Real Time Clock (RTC). The CMOS RAM is backed up with a Lithium Battery. If the battery is not present, a battery-free boot option in the BIOS completes the boot process and resets the clock to the default date and time.

# External Battery (BT1)

An external battery input connection is provided through the battery connector (BT1) for an external battery. The external battery is used to power the Real Time Clock. ADLINK provides a small Lithium battery, taped to the board and connected to the external battery connection (BT1). This small external Lithium battery serves as an on-board power source.

# Temperature Monitoring

The Super I/O controller (W83627HF) performs the temperature monitoring function and receives input directly from one thermistor (RT2) on the front of the board.

NOTE The ReadyBoard 820 requires heatsinks for the CPU, Northbridge, and Southbridge.

# User GPIO Signals

The ReadyBoard 820 provides GPIO pins for custom use. The signals are routed to the J12 header, and the enable and initialize values are set in the BIOS.

For more information about GPIO pin operation, refer to the Programming Manual for the Super I/O (W83627HF) controller at:

http://www.winbond-usa.com/products/winbond\_products/pdfs/PCIC/627hf.pdf

Table 3-13. User GPIO Signals Pin/Signal Descriptions (J12)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>GND</td><td>Ground</td></tr><tr><td>2</td><td>VCC</td><td>+5 Volts DC  $\pm$  5%</td></tr><tr><td>3</td><td>GPIO4</td><td>User defined</td></tr><tr><td>4</td><td>GPIO5</td><td>User defined</td></tr><tr><td>5</td><td>GPIO6</td><td>User defined</td></tr><tr><td>6</td><td>GPIO7</td><td>User defined</td></tr><tr><td>7</td><td>GPIO0</td><td>User defined</td></tr><tr><td>8</td><td>GPIO1</td><td>User defined</td></tr><tr><td>9</td><td>GPIO2</td><td>User defined</td></tr><tr><td>10</td><td>GPIO3</td><td>User defined</td></tr></table>

Note: The shaded area denotes power or ground.

# Serial Console

The ReadyBoard 820 supports the serial console (or console redirection) feature. This I/O function is provided by an ANSI-compatible serial terminal, or the equivalent terminal emulation software running on another system. This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display.

# Infrared (IrDA) Port

The Infrared Data Association (IrDA) signals pass through a two-way communications header for an external IrDA device using infrared as the transmission medium. There are two basic infrared implementations provided; the Hewlett-Packard Serial Infrared (HPSIR) and the Amplitude Shift Keyed Infrared (ASKIR) methods. HPSIR is a serial implementation of infrared developed by Hewlett-Packard. The IrDA (HPSIR and ASKIR) signals share the same header as the IrDA model select signals. These signals are operating system (OS) and/or application dependent and are based on the user's application, but can be configured and enabled in the BIOS Setup Utility.

The HPSIR method allows serial communication at baud rates up to 115k baud. Each word is sent serially beginning with a zero value start bit. A zero is sent when a single infrared pulse is sent at the beginning of the serial bit time. A one is sent when no infrared pulse is sent during the bit time.

The Amplitude Shift Keyed Infrared (ASKIR) allows serial communication at baud rates up to 19.2k baud. Each word is sent serially beginning with a zero value start bit. A zero is sent when a 500kHz waveform is sent for the duration of the serial bit time. A one is sent when no transmission is sent during the serial bit time.

Both of these methods require an understanding of the timing diagrams provided in the Super I/O controller (W83627HF) specifications available from the manufacture’s web site and referred to earlier in this manual.

For more information, refer to the W83627HF chip databook and the Infrared Data Association web site at http://www.irda.org.

NOTE For faster speeds and infrared applications not covered in this brief description, refer to the W83627HF chip specifications by Winbond.

Table 3-14. Infrared (IrDA) Interface Pin/Signal Descriptions (J6)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>VCC</td><td>+5 volts</td></tr><tr><td>2</td><td>IRTX</td><td>IR Transmit Data</td></tr><tr><td>3</td><td>CIRRX</td><td>IR Mode Select</td></tr><tr><td>4</td><td>IRRX</td><td>IR Receive Data</td></tr><tr><td>5</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded area denotes power or ground.

# System Management Bus (SMBus)

The I/O Hub (Southbridge) chip (82801DBM) contains both a host and slave SMBus port; but the host cannot access the slave internally. The slave port allows an external master access to the I/O Hub through connector (J13). The master contained in the I/O Hub (82801DBM) is used to communicate with the SODIMM EPROM, Super I/O, Ethernet 1 and 2, and the clock generator. Table 3-15 lists the device name and corresponding reserved binary addresses on the SMBus. Table 3-16 lists the SMBus pin/signals on 5- pins, 1 row, 2 mm pin spacing on the external SMBus connector (J13).

Table 3-15. SMBus Reserved Addresses

<table><tr><td>Component</td><td>Address Binary</td></tr><tr><td>SODIMM EPROM</td><td> $1010,000x_b$ </td></tr><tr><td>Clock Generator (ICS950201)</td><td> $1101,001x_b$ </td></tr><tr><td>I/O Hub (82801DBM)</td><td> $1000,100x_b$ </td></tr><tr><td>I/O Hub (82801DBM)</td><td> $0001,000x_b$ </td></tr></table>

Note: The I/O Hub has two reserved addresses.

Table 3-16. SMBus Signals Pin/Signal Descriptions (J13)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>VCC5Dual</td><td>+5V standby voltage</td></tr><tr><td>2</td><td>SMBCLK</td><td>SMBus Clock</td></tr><tr><td>3</td><td>SMBDATA</td><td>SMBus Data</td></tr><tr><td>4</td><td>SMBALERT*</td><td>SMBus Alert</td></tr><tr><td>5</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.

# Watchdog Timer

The Watchdog Timer (WDT) restarts the system if a mishap occurs. Possible problems include failure to boot properly, the application software’s loss of control, unexpected conditions on the bus, or other hardware or software malfunctions.

The WDT (Watchdog Timer) can be used both during the boot process and during normal system operation.

During the Boot process – If the operating system fails to boot in the time interval set in the BIOS, the system will reset.

Enable the WDT in the Boot Settings of BIOS Setup. Set the WDT for a time-out interval in seconds, between 1 and 255, in one second increments. Ensure you allow enough time for the operating system (OS) to boot. The OS or application must tickle the WDT before the timer expires.

During System Operation – An application can set up the WDT hardware through a BIOS call, or by accessing the hardware directly. Some ADLINK Board Support Packages provide an API interface to the WDT. The application must tickle the WDT before the timer expires or the system will be reset. The BIOS implements interrupt 15 function 0C3h to manipulate the WDT.

# Power Interfaces

The ReadyBoard 820 uses various voltages onboard, but only one voltage is required externally (+5 volts) through the external connector, which uses a 4-pin header with 0.200" (5.08 mm) spacing. The optional +12V volts is also provided on the input connector as a pass through voltage, but is not used on the board except for LVDS power, PCI-104 bus, and optional ISA bus power. All other onboard voltages, including the CPU core voltages, are derived from the externally supplied +5 volts DC +/- 5%.

# Power In

Table 3-17 lists the pin signals for Power In header (J1).

# CAUTION

This table matches the board even though the +5V and +12V are swapped in comparison to typical AT power supply cables.

Table 3-17. Power In Pin/Signal Descriptions (J1)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>+5V</td><td>+5.0 volts DC +/- 5%</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+12V</td><td>This pass through +12 voltage is primarily for PCI-104 bus power, and LCD power (may also be backlight power).</td></tr></table>

Note: The shaded area denotes power or ground. The +12V on the Power In connector (J1) is used for the LVDS (LCD panel), PCI-104 Bus, and optional ISA Bus power, but may also be supplied externally.

# Power On

The signals on this header allow the ATX power supply to be turned off (soft off) from the ReadyBoard 820 by operating system (OS) control. However, if you use a non-ATX power supply, then you will not have the soft off feature for sleep states normally provided by ATX power supplies.

Table 3-18. Power On Header Pin/Signal Descriptions (J2)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>VCC5SBY</td><td>+5V Standby Voltage – This voltage (refer to ATX Specification 2.2 or later for minimum requirement) is supplied from the ATX power supply and is required for normal operation and sleep states.</td></tr><tr><td>2</td><td>GND</td><td>Ground</td></tr><tr><td>3</td><td>PS_ON*</td><td>Power Supply On – This signal is sent to the ATX power supply from the ReadyBoard 820 to turn on the ATX power supply. This signal can also be used to turn off the ATX power supply or go into a suspended or standby state.</td></tr></table>

Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.

# Optional System Fan

The ReadyBoard 820 has an optional system fan connector for those environmental situations where customers may require it.

Table 3-19. Optional System Fan Interface Pin/Signal Descriptions (J17)

<table><tr><td>Pin #</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DET</td><td>Fan Speed Detect – This is the fan speed tachometer signal.</td></tr><tr><td>2</td><td>+5</td><td>+5 volts DC +/- 5%</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr></table>

Note: The shaded area denotes power or ground.

# Power and Sleep States

The following information applies to the ReadyBoard 820 only if an ATX power supply is used to provide power. If a non-ATX power supply is used, the ReadyBoard 820 is controlled only by the Power On/Off switch on the power supply and the various sleep states are not available.

# Power-On Switch

The Power-On switch turns the ReadyBoard 820 and its attached power supply to a fully On condition, if you are using an ATX power supply. Normally—if the operating system (OS) supports sleep states—the OS will turn off the ReadyBoard 820 and its power supply during the OS shut down process. If the OS supports sleep states, the Power-On switch will also transition the ReadyBoard and its power supply between a fully Powered-On state, various sleep states depending on the OS control setting, and a fully Powered-Off state. If the OS does not support sleep states, then the Power-On switch only turns on or off power to the ReadyBoard 820.

The sleep states are OS dependent and not available if your OS does not support power management based on the ACPI standard. An OS supporting ACPI will allow the Power-On switch to be configured through a user interface.

The Power-On switch is provided externally by connecting a momentary switch between pins 1 and 2 on the Utility connector (J16). The Power-On signal occurs when ground is placed on pin 2 of J16.

# Sleep States (ACPI)

The ReadyBoard 820 supports the ACPI (Advanced Configuration and Power Interface) standard, which is a key component of certain Operating Systems’ power management. The supported features (sleep states) listed here are only available when an ACPI-compliant OS is used for the ReadyBoard, such as Windows 2000/XP. The term “sleep” state refers to a reduced power consumption state, which can be re-started (awakened), restoring full operation to the ReadyBoard 820.

In these various sleep states, the ReadyBoard 820 appears to be off, indicated by such things as no display on the attached monitor and no activity for the connected CD-ROM or hard drives. However, when the ReadyBoard 820 detects certain types of activity (i.e. power button, mouse, keyboard, or LAN activity), it returns to a fully operational state. The type of activity detected is based on those supported by the ReadyBoard 820.

The ReadyBoard 820 supports at least four ACPI power states, depending on the operating system used and its ability to manage sleep states. Typically, the Power On switch is used to wake up from a sleep state, or transition from one state to another, but this is dependent on the operating system.

1st state is normal Power-On (S0).

To go to a fully powered on state, the ReadyBoard 820 must either be powered Off (S5), or in a sleep state (S1 or S4), and then the Power On/Off switch is pressed for less than 4 seconds (default).
The ReadyBoard 820 can transition from this state (S0) to the various states described below, depending on the power management capability of the OS and how it is programmed.

2nd state is a standby state (S1).

In this state, no internal operations take place except for the internal RTC (Real Time Clock) and the contents of RAM. This typically includes no activity for the CPU, CD-ROM, or hard disk drives. The CPU may be active, and the peripheral devices may power down if no signals occur or power to the device(s) is not provided. The ReadyBoard 820 appears to be off including the Power-On LED.

♦ Normally, to enter this sleep state, the ReadyBoard 820 must be fully powered on (S0) while the OS transitions the ReadyBoard into this standby state (S1) under user control.
To exit this sleep state, typically the power button is used to wake up the ReadyBoard 820 to restore full operation, including the Power-On LED. Typically, pressing the power switch for less than 4 seconds (default) will restore full operation.

3rd state is Suspend to RAM or Standby [Windows] (S3).

In this state, main memory (RAM) and the internal RTC (Real Time Clock) are the only devices where power is maintained. This state (Suspend to RAM) stores the state of the operating system prior to shutdown including all open applications and open documents, etc. in main memory. This allows users to resume their work exactly where they left off just prior to entering this state (S3) when the system restores power and the contents of main memory.

This state takes longer to restore and uses less power than S1 or S2, but if AC power is completely lost, the contents of main memory (RAM), including any changes to documents or data stored in RAM during S3, is also lost.

♦ To enter the Suspend to RAM (S3) or Standby state, the computer must be fully powered on and the OS transitions the computer into this sleep state under user control.
♦ To exit this sleep state, typically pressing the Power On switch for less then 4 seconds (default) will restore full operation.

4th state is a hibernate or suspend-to-disk state (S4).

In this state, no internal operations take place, except for the internal RTC. This includes no activity for the CPU, CD-ROM, or hard disk drives. The ReadyBoard 820 appears to be off, including the external Power-On LED if connected. Your system will take longer to wake-up in this sleep state, however, since your data is saved to the disk, it is more secure and should not be lost in the event of a power failure.

♦ To enter a hibernate or suspend-to-disk state, the ReadyBoard 820 must be fully powered on while the OS transitions the ReadyBoard 820 into this sleep state (S4) under user control.

To exit this sleep state, typically pressing the power switch for less than 4 seconds (default) will restore full operation.

$5 ^ { \mathrm { t h } }$ state is the normal power off or shutdown (S5).

All activity stops, except the internal clock, if there is a backup battery installed. Removing the power cord from the power source ensures all activity is stopped, except the internal clock.

♦ To go to a fully powered down state, the ReadyBoard 820 must either be powered on, or in a sleep state, and then the Power On/Off switch is pressed for more than 4 seconds.
♦ To go to a fully powered up state, press the power switch for less than 4 seconds (default) and full operation is restored.

The OS may provide additional programming features to change the activation time for each state, and to shutdown or transition the ReadyBoard 820 at certain times, depending on the way the OS interface is programmed. Refer to the OS vender’s documentation for power management under the ACPI standard.

# NOTE

Some operating systems use the keyboard, mouse, Wake-on-Ring (serial port), and Wake-on-LAN (Ethernet port) as an activity to wake up the system from a sleep state. Refer to Table 3-20 for the wake up activity conditions supported by the ReadyBoard 820.

# Wake Up Activities

The wake up events listed in Table 3-20 can be used to wake up the ReadyBoard 820 from any of the supported sleep states mentioned above.

Table 3-20. Wake Up Activities and Conditions

<table><tr><td>Signal/Device</td><td>Condition</td></tr><tr><td>Power On Switch</td><td>If the Power-On switch is pressed for more than 4 seconds, the system will wake up from any of the sleep states.</td></tr><tr><td>Ethernet Ports (2) (LAN Ports)</td><td>If Wake On LAN is [Enabled], then the system will wake from one of the sleep states through direct addressing, magic packets, or link status changes.</td></tr><tr><td>PS/2 Keyboard &amp; Mouse</td><td>If you use a PS/2 keyboard or mouse, any activity from the keyboard or mouse could wake the system.</td></tr><tr><td>USB Devices</td><td>If you use a USB keyboard or mouse instead of a PS/2 device, the USB device could wake the system.</td></tr><tr><td>Serial Ports (2)</td><td>If Wake On Ring is [Enabled], then Serial Ports 1 and 2 can be used to wake the system.</td></tr></table>

# Introduction

This section assumes the user is familiar with general BIOS Setup. Refer to the appropriate PC reference manuals for information about the on-board ROM-BIOS software interface. If ADLINK has added to or modified the standard functions, these functions will be described.

# Entering BIOS Setup (VGA Display)

To access BIOS Setup using a VGA display for the ReadyBoard 820:

1. Turn on the VGA monitor and the power supply to the ReadyBoard 820.
2. Start Setup by pressing the [Del] key when the following message appears on the boot screen.

Press DEL to run Setup

NOTE If the setting for Quick Boot is [Enabled], you may not see this prompt appear on screen. If this happens, press the &lt;Del&gt; key early in the boot sequence to enter BIOS Setup.

3. Follow the instructions on the right side of the screen to navigate through the selections and modify any settings.

# Entering BIOS Setup (Remote Access)

This section describes how to enable the Remote Access in VGA mode and enter the BIOS setup through a serial terminal or PC.

1. Turn on the power supply to the ReadyBoard 820 and enter the BIOS Setup Utility in VGA mode.
2. Set the BIOS feature Remote Access Configuration to [Enable] under the Advanced menu.
3. Accept the default options or make your own selections for the balance of the Remote Access fields and record your settings.
4. Ensure you select the type of remote serial terminal you will be using and record your selection.
5. Select Save Changes and Exit and then shut down the ReadyBoard 820.
6. Connect the remote serial terminal (or the PC with communications software) to the COM port you selected and recorded earlier in the BIOS Setup Utility.
7. Turn on the remote serial terminal or PC and set it to the settings you selected in the BIOS Setup Utility. The default settings for the ReadyBoard 820 are:

COM1
+ 115200
▲ 8 bits
♦ 1 stop bit
+ no parity
no flow control
♦ [Always] for Redirection After BIOS POST

8. Restore power to the ReadyBoard 820 and press the F4 key after you see the following screen prompt.

Press &lt;space bar&gt; to update BIOS

NOTE If Quick Boot is set to [Enabled], you may not see the screen prompt and might need to press F4 earlier in the boot sequence to enter Setup.

9. Use the &lt;Enter&gt; key to select the screen menus listed in the Opening BIOS screen.

NOTE The serial console port is not hardware protected. Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions.

# OEM Logo (Splash) Utility

The ReadyBoard 820 BIOS supports a graphical logo utility, which can be customized by the user and displayed when enabled through the BIOS Setup Utility. The graphical image can be a company logo or any custom image the user wants to display during the boot process. The custom image can be displayed as the first image displayed on screen during the boot process and remain there, depending on the options selected in BIOS Setup, while the OS boots.

# Logo Image Requirements

The user’s image may be customized with any image editing tool, and the system will automatically convert the image into an acceptable format to the tools (files and utilities) provided by ADLINK. The ReadyBoard 820 OEM Logo utility supports the following image formats:

. Bitmap image
16-Color, 640x480 pixels
256-Color, 640x480 pixels
• JPG image
16-Color, 640x480 pixels
PCX image
256-Color, 640x480 pixels
• A file size not larger than the sample image

NOTE For procedures on loading custom images, see the OEM Logo Utility document available on the Ampro By ADLINK web site.

ADLINK Technology, Inc. provides a number of methods for contacting Technical Support listed below in Table A-1. Requests for support through the Ask an Expert are given the highest priority, and usually will be addressed within one working day.

ADLINK’s Ask an Expert – This is a comprehensive support center designed to meet all your technical needs. This service is free and available 24 hours a day through the Ampro By ADLINK web page at http://www.adlinktech.com/AAE/. This includes a searchable database of Frequently Asked Questions, which will help you with the common information requested by most customers. This is a good source of information to look at first for your technical solutions. However, you must register online if you wish to use the Ask a Question feature.

ADLINK strongly suggests that you register with the web site. By creating a profile on the ADLINK web site, you will have a portal page called “My ADLINK” unique to you with access to exclusive services and account information.

Personal Assistance – You may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature. Requests can be submitted 24 hours a day, 7 days a week. You will receive immediate confirmation that your request has been entered. Once you have submitted your request, you must log in to go to My Stuff area where you can check status, update your request, and access other features.
Download Service – This service is also free and available 24 hours a day at http://www.adlinktech.com. For certain downloads such as technical documents and software, you must register online before you can log in to this service.

Table A-1. Technical Support Contact Information

<table><tr><td>Method</td><td>Contact Information</td></tr><tr><td>Ask an Expert</td><td>http://www.adlinktech.com/AAE/</td></tr><tr><td>Web Site</td><td>http://www.adlinktech.com</td></tr><tr><td>Standard Mail</td><td>Contact us should you require any service or assistance.ADLINK Technology, Inc.Address: 9F, No.166 Jian Yi Road, Chungho City,Taipei County 235, Taiwan台北縣中和市建一路166號9樓Tel: +886-2-8226-5877Fax: +886-2-8226-5717Email: service@adlinktech.comAmpro ADLINK Technology, Inc.Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USATel: +1-408-360-0200Toll Free: +1-800-966-5200 (USA only)Fax: +1-408-360-0222Email: info@adlinktech.comADLINK Technology (China) Co., Ltd.Address: 上海市浦东新区张江高科技园区芳春路300号(201203)300 Fang Chun Rd., Zhangjiang Hi-Tech Park,Pudong New Area, Shanghai, 201203 ChinaTel: +86-21-5132-8988Fax: +86-21-5132-3588Email: market@adlinktech.comADLINK Technology BeijingAddress:北京市海淀区上地东路1号盈创动力大厦E座801室(100085)Rm. 801, Power Creative E, No. 1, B/DShang Di East Rd., Beijing, 100085 ChinaTel:+86-10-5885-8666Fax:+86-10-5885-8625Email:market@adlinktech.com</td></tr><tr><td rowspan="7"></td><td>ADLINK Technology ShenzhenAddress:深圳市南山区科技园南区高新南七道数字技术园A1栋2楼C区(518057)2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 ChinaTel:+86-755-2643-4858Fax:+86-755-2664-6353Email:market@adlinktech.com</td></tr><tr><td>ADLINK Technology (Europe) GmbHAddress:Nord Carree 3, 40477 Duesseldorf, GermanyTel:+49-211-495-5552Fax:+49-211-495-5557Email:emea@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (French Liaison Office)Address:15 rue Emile Baudot, 91300 Massy CEDEX, FranceTel:+33 (0) 1 60 12 35 66Fax:+33 (0) 1 60 12 35 66Email:france@adlinktech.com</td></tr><tr><td>ADLINK Technology Japan CorporationAddress:151-0072 東京都渋谷区幡ヶ谷1-1-2 朝日生命幡ヶ谷ビル8FAsahiseimei Hatagaya Bldg. 8F1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, JapanTel:+81-3-4455-3722Fax:+81-3-5333-6040Email:japan@adlinktech.com</td></tr><tr><td>ADLINK Technology, Inc. (Korean Liaison Office)Address:서울시 서초구 서초동 1506-25 한도B/D 2층2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu, Seoul 137-070, KoreaTel:+82-2-2057-0565Fax:+82-2-2057-0563Email:korea@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd.Address:84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584Tel:+65-6844-2261Fax:+65-6844-2263Email:singapore@adlinktech.com</td></tr><tr><td>ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)Address:No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, IndiaTel:+91-80-65605817Fax:+91-80-22443548Email:india@adlinktech.com</td></tr></table>

# A

ACPI

reduced power consumption . 36

Architecture

EPIC (Embedded Platform for Industrial Computing) . 3

# B

BIOS Setup

accessing BIOS setup (VGA) . 39

accessing serial console . 39

splash screen configuration . 40

watchdog timer (WDT) . 34

# C

console redirection

serial console . 32

console redirection feature . 32

CRT interface

pin-out list . . 29

# D

dimensions

# E

Embedded Platform for Industrial Computing

(EPIC) .. 3

Environmental specifications . . 14

Ethernet chip specifications

web sites . . 2

# F

Fuses . 13

# H

headers

header list . . 10

pin identification 11

pin sequence description 11

# I

Infrared (IrDA)

pin-out list . 33

IRQ list . 19

# J

jumper header locations . 13

# L

Lithium Battery

RTC . 31

logo screen

requirements . 40

LVDS interface

pin-out list . . 30

# M

major chip specifications

web sites .

major integrated circuits

see also major chip specifications

Memory map ..20

# P

Pin-1 locations .12

processor requirements

heatsink requirements .15

# R

ReadyBoard 820

ACPI features ..35

ACPI power states .36

Audio interface features .27

block diagram .8

Celeron M CPUs 4

console redirection .32

CPU features 5

dimensions .15

EPIC Architecture . .3

features .

fuses .13

GPIO features ..32

header list .. .10

Infrared (IrDA) features .32

input power .34

major integrated circuit list .9

Mechanical Specification drawing .15

miscellaneous features .31

Pentium M CPUs 4

pin-1 locations .12

product description .4

see also supported features .4

serial console option .32

Serial port features .23

shared floppy/parallel interface .21

sleep states .35

splash screen customization ..40

USB boot 5

USB features .26

video features .28

wake-up activity limitation .37

Watchdog Timer .34

weight .15

Real Time Clock (RTC) ..31

reference material .33

RTC

Lithium Battery .31

# S

Serial A

pin-out list .24

Serial B

pin-out list .25

Serial Communications Software .32

serial console

accessing BIOS . 39

console redirection . 32

serial terminal . 32

terminal emulation software . 32

serial terminal

ANSI-compatible . 32

serial terminal emulation . 32

sleep states

reduced power consumption . 36

SMBus

supported features . 33

splash screen

customer defined . 40

supported features

200-pin DDR2 SODIMM socket . 5

AC’97 audio interface 6

Advanced Configuration and Power Interface (ACPI) . 36

audio interface . 27

Battery-free boot 7

console redirection . 32

CRT (VGA) video interface . 28

Ethernet interface 6

external battery 7

floppy disk drive . 21

heatsinks 15

I/O address map . . 20

IDE devices 5

Infrared (IrDA) interface ...6, 32

input power (+5V) . 34

Intel Celeron M CPU 5

Intel Pentium M CPU’s 5

IRQ assignments . 19

jumper headers onboard 13

Lithium Battery . 31

LVDS video interface . 28

memory 5

memory map ... . 20

onboard fuses . 13

OS power management . 36

parallel port . 21

PCI-104 4

Real-Time Clock (RTC)

required power-on connection . 35

RS485 termination . 23

serial console .. 7, 32

serial ports . ... 6, 23

shared floppy/parallel interface . 21

sleep states . 35

SMBus devices . 33

splash screen . 40

Splash Screen, user defined 7

thermal sensors .. 7, 31

USB 2.0 ports . 26

USB boot device 5

USB ports . . 5

user GPIO capability . 32

user GPIO interface 7

video interfaces 7

voltage sensor 7

Watchdog Timer ... 7, 34

System fan (optional)

pin-out list . 35

# T

Technical Support

Ask an Expert . . 41

contact information . 41

terminal emulation software

serial console . 32

thermal cooling

processor requirements 1 5

thermal sensors

supported feature 31

#

Watchdog Timer (WDT)

2 to 255 sec interval . 34

functions . . 34

web sites

Ethernet chip specifications 2

infrared specifications . 33

major chip specifications

weight . 15
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