| J1 Pin # | Signal | PCI Pin # | Description |
| NC | 1 (A1) | Not connected (Test Reset) |
| +12V | 2 (A2) | +12 volt power |
| NC | 3 (A3) | Not connected (Test Mode Select) |
| NC | 4 (A4) | Not connected (Test Data Input) |
| +5V | 5 (A5) | +5 volt power |
| 97 | INTA* | 6 (A6) | Interrupt A – This signal is used to request an interrupt. |
| 95 | INTC* | 7 (A7) | Interrupt C – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| +5V | 8 (A8) | +5 volt power |
| NC | 9 (A9) | Not connected (Reserved) |
| +5VI/O | 10 (A10) | +5.0 volt I/O |
| NC | 11 (A11) | Not connected (Reserved) |
| GND | 12 (A12) | Ground |
| GND | 13 (A13) | Ground |
| 3.3Vaux | 14 (A14) | 3.3 Volt Auxiliary – This voltage is an optional power source that delivers power to the PCI add-in card for generation of power management events when the main power to the card has been turned off by software. A system or add-in card that does not support PCI bus power management must treat the 3.3Vaux pin as reserved. |
| 93 | RST* | 15 (A15) | PCI Bus Reset – This signal is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Anytime Reset is asserted, all PCI output signals must be driven to the benign state. |
| +5VI/O | 16 (A16) | +5 volt I/O |
| GNT#* | 17 (A17) | Grant # – This is a point-to-point signal and indicates to the agent that access to the bus has been granted. Every master has its own Grant signal, which must be ignored while RST is asserted. |
| GND | 18 (A18) | Ground |
| 57 | PME* | 19 (A19) | Power Management Event – This signal is an optional signal that can be used by a device to request a change in the device or system power state. |
| 91 | AD[30] | 20 (A20) | Address/Data bus 30 – These signals (AD31 – AD0) are multiplexed on the same PCI connector pins. During the address phase of a PCI cycle, AD31 – AD0 contain a 32-bit address or other destination information. During the data phase, AD31 – AD0 contain data. |
| +3.3V | 21 (A21) | +3.3 volt power |
| 87 | AD[28] | 22 (A22) | Address/Data bus 28 – Refer to J1, pin-91 for more information |
| 86 | AD[26] | 23 (A23) | Address/Data bus 26 – Refer to J1, pin-91 for more information |
| GND | 24 (A24) | Ground |
| 81 | AD[24] | 25 (A25) | Address/Data bus 24 – Refer to J1, pin-91 for more information) |
| 60 | IDSEL | 26 (A26) | Initialization Device Select – This signal is used as a chip select during configuration read and write transactions. |
| +3.3V | 27 (A27) | +3.3 volt power |
| 77 | AD[22] | 28 (A28) | Address/Data bus 22 – Refer to J1, pin-91 for more information |
| 75 | AD[20] | 29 (A29) | Address/Data bus 20 – Refer to J1, pin-91 for more information |
| GND | 30 (A30) | Ground |
| 74 | AD[18] | 31 (A31) | Address/Data bus 18 – Refer to J1, pin-91 for more information |
| 69 | AD[16] | 32 (A32) | Address/Data bus 16 – Refer to J1, pin-91 for more information |
| +3.3V | 33 (A33) | +3.3 volt power |
| 65 | FRAME* | 34 (A34) | PCI bus Frame access – This signal is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle. |
| GND | 35 (A35) | Ground |
| 61 | TRDY* | 36 (A36) | Target Ready – This signal indicates the selected device’s ability to complete the current cycle of transaction. Both IRDY* and TRDY* must be asserted to terminate a data cycle. |
| GND | 37 (A37) | Ground |
| 64 | STOP* | 38 (A38) | Stop – This signal is driven by the current PCI target to request the master to stop the current transaction. |
| +3.3V | 39 (A39) | +3.3 volt power |
| NC | 40 (A40) | Not connected (Reserved) |
| NC | 41 (A41) | Not connected (Reserved) |
| GND | 42 (A42) | Ground |
| 53 | PAR | 43 (A43) | PCI bus Parity bit – This signal is the even parity bit on AD[31:0] and CBE[3:0]*. |
| 47 | AD[15] | 44 (A44) | Address/Data bus 15 – Refer to J1, pin-91 for more information |
| +3.3V | 45 (A45) | +3.3 volt power |
| 43 | AD[13] | 46 (A46) | Address/Data bus 13 – Refer to J1, pin-91 for more information |
| 39 | AD[11]GND | 47 (A47)48 (A48) | Address/Data bus 11 – Refer to J1, pin-91 for more informationGround |
| 34 | AD[09] | 49 (A49) | Address/Data bus 9 – Refer to J1, pin-91 for more information |
| Key | 50 (A50) | Key |
| Key | 51 (A51) | Key |
| 31 | CBE[0]* | 52 (A52) | PCI Bus Command/Byte Enable 0 – This signal line is one of four signal lines multiplexed on the same pins, so that during the address cycle, the command is defined and during the data cycle, the byte enable is defined. |
| +3.3V | 53 (A53) | +3.3 volt power |
| 29 | AD[06] | 54 (A54) | Address/Data bus 06 – Refer to J1, pin-91 for more information |
| 27 | AD[04] | 55 (A55) | Address/Data bus 04 – Refer to J1, pin-91 for more information |
| GND | 56 (A56) | Ground |
| 26 | AD[02] | 57 (A57) | Address/Data bus 02 – Refer to J1, pin-91 for more information |
| 23 | AD[00] | 58 (A58) | Address/Data bus 00 – Refer to J1, pin-91 for more information |
| +3.3VI/O | 59 (A59) | +3.3 volt I/O |
| NU | 60 (A60) | Not used in 32-bit system (Request 64-bit Transfer) tied to +5v through 4.7k ohm resistor. |
| +5V | 61 (A61) | +5 volt power |
| +5V | 62 (A62) | +5 volt power |
| -12V | 63 (B1) | -12 volt power |
| NC | 64 (B2) | Not connected (Test Clock) |
| GND | 65 (B3) | Ground |
| NC | 66 (B4) | Not connected (Test Output) |
| +5V | 67 (B5) | +5 volt power |
| +5V | 68 (B6) | +5 volt power |
| 98 | INTB* | 69 (B7) | Interrupt B – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| 96 | INTD* | 70 (B8) | Interrupt D – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| NU | 71 (B9) | Not used (Present 1) |
| NC | 72 (B10) | Not connected (Reserved) |
| NU | 73 (B11) | Not used (Present 2) |
| GND | 74 (B12) | Ground |
| GND | 75 (B13) | Ground |
| NC | 76 (B14) | Not connected (Reserved) |
| GND | 77 (B15) | Ground |
| CLK | 78 (B16) | Clock – This signal provides timing for all transactions on the PCI bus and is an input to every PCI device. |
| GND | 79 (B17) | Ground |
| REQ#* | 80 (B18) | Request # – This is a point-to-point signal and indicates to the arbiter that this agent desires use of the bus. Every master has its own Request, which must be tri-stated while Reset is asserted. |
| +5VI/O | 81 (B19) | +5 volt I/O |
| 94 | AD[31] | 82 (B20) | Address/Data bus 31 – Refer to J1, pin-91 for more information |
| 90 | AD[29] | 83 (B21) | Address/Data bus 29 – Refer to J1, pin-91 for more information |
| GND | 84 (B22) | Ground |
| 89 | AD[27] | 85 (B23) | Address/Data bus 27 – Refer to J1, pin-91 for more information |
| 85 | AD[25] | 86 (B24) | Address/Data bus 25 – Refer to J1, pin-91 for more information |
| +3.3V | 87 (B25) | +3.3 volt power |
| 82 | CBE[3]* | 88 (B26) | Bus Command and Byte Enable 3 – Refer to J1, pin-31 for more information. |
| 79 | AD[23] | 89 (B27) | Address/Data bus 23 – Refer to J1, pin-91 for more information |
| GND | 90 (B28) | Ground |
| 78 | AD[21] | 91 (B29) | Address/Data bus 21 – Refer to J1, pin-91 for more information |
| 73 | AD[19] | 92 (B30) | Address/Data bus 19 – Refer to J1, pin-91 for more information |
| +3.3V | 93 (B31) | +3.3 volt power |
| 71 | AD[17] | 94 (B32) | Address/Data bus 17 – Refer to J1, pin-91 for more information |
| 70 | CBE[2]* | 95 (B33) | Bus Command and Byte Enable 2 – Refer to J1, pin-31 for more information. |
| GND | 96 (B34) | Ground |
| 63 | IRDY* | 97 (B35) | Initiator Ready – This signal indicates the master's ability to complete the current data cycle of the transaction. |
| +3.3V | 98 (B36) | +3.3 volt power |
| 60 | DEVSEL* | 99 (B37) | Device Select – This signal is driven by the target device when its address is decoded. |
| GND | 100 (B38) | Ground |
| 59 | LOCK* | 101 (B39) | Lock – This signal indicates an operation that may require multiple transactions to complete. |
| 55 | PERR* | 102 (B40) | Parity Error – This signal is driven by the PCI target during a write to indicate a data parity error has been detected. |
| +3.3V | 103 (B41) | +3.3 volt power |
| 54 | SERR* | 104 (B42) | System Error – This signal is for reporting address parity errors. |
| +3.3V | 105 (B43) | +3.3 volt power |
| 49 | CBE[1]* | 106 (B44) | Bus Command and Byte Enable 1 – Refer to J1, pin-31 for more information. |
| 45 | AD[14] | 107 (B45) | Address/Data bus 14 – Refer to J1, pin-91 for more information |
| GND | 108 (B46) | Ground |
| 41 | AD[12] | 109 (B47) | Address/Data bus 12 – Refer to J1, pin-91 for more information |
| 37 | AD[10] | 110 (B48) | Address/Data bus 10 – Refer to J1, pin-91 for more information |
| GND | 111 (B49) | Ground |
| Key | 112 (B50) | Key |
| Key | 113 (B51) | Key |
| 33 | AD[08] | 114 (B52) | Address/Data bus 08 – Refer to J1, pin-91 for more information |
| 32 | AD[07] | 115 (B53) | Address/Data bus 07 – Refer to J1, pin-91 for more information |
| +3.3V | 116 (B54) | +3.3 volt power |
| 30 | AD[05] | 117 (B55) | Address/Data bus 05 – Refer to J1, pin-91 for more information |
| 28 | AD[03] | 118 (B56) | Address/Data bus 03 – Refer to J1, pin-91 for more information |
| GND | 119 (B57) | Ground |
| 25 | AD[01] | 120 (B58) | Address/Data bus 01 – Refer to J1, pin-91 for more information |
| +5V I/O | 121 (B59) | +5 volt I/O |
| NU | 122 (B60) | Not used in 32-bit system (Acknowledge 64-bit Transfer) tied to +5v through 4.7k ohm resistor. |
| +5V | 123 (B61) | +5 volt power |
| +5V | 124 (B62) | +5 volt power |
# Universal Serial Bus (USB)
The ETX 802 module supports up to four USB ports on the baseboard and the supported features are listed below.
• USB v2.0 and backwards compatible to Universal OHCI v1.1
• Two root USB hubs and 4 USB ports
• Supports USB boot of floppy disk drives, hard disk drives, CD-ROMs, or other USB boot devices.
• Integrated physical layer transceivers
• Over-current detection status on USB ports 1 and 2
Table 3-5. Simplified USB Interface Pin/Signal Descriptions (J1)
| J1 Pin # | Signal | Description |
| 1, 2 | GND | Ground |
| 3 | PCICLK3 | PCI clock 3 – This signal line is one of four signal lines. These clock signals provide the timing outputs for four external PCI devices and the timing for all transactions on the PCI bus. |
| 4 | PCICLK4 | PCI clock 4 – Refer to J1, pin-3 for more information. |
| 5, 6 | GND | Ground |
| 7 | PCICLK1 | PCI clock 1 – Refer to J1, pin-3 for more information. |
| 8 | PCICLK2 | PCI clock 2 – Refer to J1, pin-3 for more information. |
| 9 | REQ3* | Bus Request 3 – This signal line is one of four signal lines. These signals indicate to the arbitrator that the device desires use of the bus. |
| 10 | GNT3* | Grant 3 – This signal line is one of four signal lines. These signal lines indicate access has been granted to the requesting device (PCI Masters). |
| 11 | GNT2* | Grant 3 – Refer to J1, pin-10 for more information. |
| 12 | +3.3V | +3.3 volts +/- 5% |
| 13 | REQ2* | Bus Request 0 – This signal line is one of three signal lines. These signals indicate the device desires use of the bus to the arbitrator. |
| 14 | GNT1* | Grant 1 – Refer to J1, pin-10 for more information. |
| 15 | REQ1* | Bus Request 1 – Refer to J1, pin-13 for more information. |
| 16 | +3.3V | +3.3 volts +/- 5% |
| 17 | GNT0* | Grant 0 – Refer to J1, pin-10 for more information. |
| 18 | NC | Not Connected (Reserved) |
| 19, 20 | VCC | DC Power – +5 volts +/- 5% |
| 21 | SERIRQ | Serial Interrupt Request – This signal supports the serial interrupt protocol. |
| 22 | REQ0* | Bus Request 0 – Refer to J1, pin-13 for more information. |
| 23 | AD0 | Address/Data bus 0 – These signalsare multiplexed on the same PCI connector pins. During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31 – AD0 contain data. |
| 24 | +3.3V | +3.3 volts +/- 5% |
| 25 | AD1 | Address/Data bus 1 – Refer to J1, pin-23 for more information. |
| 26 | AD2 | Address/Data bus 2 – Refer to J1, pin-23 for more information. |
| 27 | AD4 | Address/Data bus 4 – Refer to J1, pin-23 for more information. |
| 28 | AD3 | Address/Data bus 3 – Refer to J1, pin-23 for more information. |
| 29 | AD6 | Address/Data bus 6 – Refer to J1, pin-23 for more information. |
| 30 | AD5 | Address/Data bus 5 – Refer to J1, pin-23 for more information. |
| 31 | CBE0* | PCI Bus Command/Byte Enable 0 – This signal line is one of four signal lines multiplexed on the same pins, so that during the address cycle, the command is defined and during the data cycle, the byte enable is defined. |
| 32 | AD7 | Address/Data bus 7 – Refer to J1, pin-23 for more information. |
| 33 | AD8 | Address/Data bus 8 – Refer to J1, pin-23 for more information. |
| 34 | AD9 | Address/Data bus 9 – Refer to J1, pin-23 for more information. |
| 35, 36 | GND | Ground |
| 37 | AD10 | Address/Data bus 10 – Refer to J1, pin-23 for more information. |
| 38 | AUXAL | Auxiliary A Input Left – This signal is normally used for an external CD-ROM analog output or similar live-level audio source. Minimum input impedance is 5k Ohms and nominal input level is 1 volt RMS. |
| 39 | AD11 | Address/Data bus 11 – Refer to J1, pin-23 for more information. |
| 40 | MIC | Microphone reference signal – This microphone input signal has a minimum input impedance of 5k Ohms, and the maximum input voltage is 0.15 V p-p. |
| 41 | AD12 | Address/Data bus 12 – Refer to J1, pin-23 for more information. |
| 42 | AUXAR | Auxiliary A Input Right – This signal is normally used for an external CD-ROM analog output or similar live-level audio source. Minimum input impedance is 5k Ohms and nominal input level is 1 volt RMS. |
| 43 | AD13 | Address/Data bus 13 – Refer to J1, pin-23 for more information. |
| 44 | ASVCC | Analog Supply Voltage – This test voltage is used for the sound controller, but is not available for customer use. |
| 45 | AD14 | Address/Data bus 14 – Refer to J1, pin-23 for more information. |
| 46 | SNDL | Stereo Line Output Left channel – Output signal has a nominal 1 volt RMS level into 10k impedance load. This output signal can not drive low-impedance speakers directly. |
| 47 | AD15 | Address/Data bus 15 – Refer to J1, pin-23 for more information. |
| 48 | ASGND | Analog Ground – This ground is used for the sound controller and an external amplifier to achieved the lowest audio noise levels. |
| 49 | CBE1* | Bus Command and Byte Enable 1 – Refer to J1, pin-31 for more information. |
| 50 | SNDR | Stereo Line Output Right channel – This output signal has a nominal level of 1 volt RMS into 10k impedance load. This output signal can not drive low-impedance speakers directly |
| 51, 52 | VCC | DC Power – +5 volts +/- 5% |
| 53 | PAR | PCI bus Parity bit – This signal is even parity bit on AD[31:0] and CBE[3:0]*. |
| 54 | SERR* | System Error – This signal is for reporting address parity errors. |
| 55 | PERR* | Parity Error – This signal is driven by the PCI target during a write to indicate a data parity error has been detected. |
| 56 | NC | Not connected (Reserved) |
| 57 | PME* | Power Management Event – This signal is an optional signal that can be used by a device to request a change in the device or system power state. |
| 58 | USB2- | Universal Serial Bus Port 2 Data Negative Polarity |
| 59 | LOCK* | Lock – This signal indicates an operation that may require multiple transactions to complete. |
| 60 | DEVSEL* | Device Select – Driven by the target device when its address is decoded. |
| 61 | TRDY* | Target Ready – This signal indicates the selected device’s ability to complete the current cycle of transaction. Both IRDY and TRDY must be asserted to terminate a data cycle. |
| 62 | USB3- | Universal Serial Bus Port 3 Data Negative Polarity |
| 63 | IRDY* | Initiator Ready – Indicates the master's ability to complete the current data cycle. |
| 64 | STOP* | Stop – Driven by the current PCI target when requesting the master stop the current transaction. |
| 65 | FRAME* | PCI bus Frame access – Driven by the current master to indicate the start of a transaction and will remain active until the final data cycle. |
| 66 | USB2+ | Universal Serial Bus Port 2 Data Positive Polarity |
| 67, 68 | GND | Ground |
| 69 | AD16 | Address/Data bus 16 – Refer to J1, pin-23 for more information. |
| 70 | CBE2* | Bus Command and Byte Enable 2 – Refer to J1, pin-31 for more information. |
| 71 | AD17 | Address/Data bus 17 – Refer to J1, pin-23 for more information. |
| 72 | USB3+ | Universal Serial Bus Port 3 Data Positive Polarity |
| 73 | AD19 | Address/Data bus 19 – Refer to J1, pin-23 for more information. |
| 74 | AD18 | Address/Data bus 18 – Refer to J1, pin-23 for more information. |
| 75 | AD20 | Address/Data bus 20 – Refer to J1, pin-23 for more information. |
| 76 | USB0- | Universal Serial Bus Port 0 Data Negative Polarity |
| 77 | AD22 | Address/Data bus 22 – Refer to J1, pin-23 for more information. |
| 78 | AD21 | Address/Data bus 21 – Refer to J1, pin-23 for more information. |
| 79 | AD23 | Address/Data bus 23 – Refer to J1, pin-23 for more information. |
| 80 | USB1- | Universal Serial Bus Port 0 Data Negative Polarity |
| 81 | AD24 | Address/Data bus 24 – Refer to J1, pin-23 for more information. |
| 82 | CBE3* | Bus Command and Byte Enable 3 – Refer to J1, pin-31 for more information. |
| 83, 84 | VCC | DC Power – +5 volts +/- 5% |
| 85 | AD25 | Address/Data bus 25 – Refer to J1, pin-23 for more information. |
| 86 | AD26 | Address/Data bus 26 – Refer to J1, pin-23 for more information. |
| 87 | AD28 | Address/Data bus 28 – Refer to J1, pin-23 for more information. |
| 88 | USB0+ | Universal Serial Bus Port 0 Data Positive Polarity |
| 89 | AD27 | Address/Data bus 27 – Refer to J1, pin-23 for more information. |
| 90 | AD29 | Address/Data bus 29 – Refer to J1, pin-23 for more information. |
| 91 | AD30 | Address/Data bus 30 – Refer to J1, pin-23 for more information. |
| 92 | USB1+ | Universal Serial Bus Port 1 Data Positive Polarity |
| 93 | PCIRST* | PCI Bus Reset – Signal resets entire PCI Bus. Asserted during a system reset. |
| 94 | AD31 | Address/Data bus 31 – Refer to J1, pin-23 for more information. |
| 95 | INTC* | Interrupt C – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| 96 | INTD* | Interrupt D – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| 97 | INTA* | Interrupt A – This signal is used to request an interrupt. |
| 98 | INTB* | Interrupt B – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| 99, 100 | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
# ISA Bus Interface (J2)
The J2 connector has 100 pins and is only used for the ISA Bus interface.
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-9. Complete J2 ISA Bus Interface Pin/Signal Descriptions (J2)
| J2 Pin # | Signal | Description |
| 1, 2 | GND | Ground |
| 3 | SD14 | System Data 14 – These signals (0 to 19) provide system data bits. |
| 4 | SD15 | System Data 15 – Refer to SD14 pin-3, for more information. |
| 5 | SD13 | System Data 13 – Refer to SD14, pin-3, for more information. |
| 6 | BUSM* | Bus Master – This signal is used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a device can pull -MASTER low which will allow it to control the system address, data, and control lines. After -MASTER is low, the device should wait one CLK period before driving the address and data lines, and two clock periods before issuing a read or write command. |
| 7 | SD12 | System Data 12 – Refer to SD14, pin-3, for more information. |
| 8 | DREQ7 | DMA Request 7 – Used by I/O resources to request DMA service. Must be held high until associated DACK7 line is active. |
| 9 | SD11 | System Data 11 – Refer to SD14, pin-3, for more information. |
| 10 | DACK7* | DMA Acknowledge 7 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 11 | SD10 | System Data 10 – Refer to SD14, pin-3, for more information. |
| 12 | DREQ6 | DMA Request 6 – Used by I/O resources to request DMA service. Must be held high until associated DACK6 line is active. |
| 13 | SD9 | System Data 9 – Refer to SD14, pin-3, for more information. |
| 14 | DACK6* | DMA Acknowledge 6 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 15 | SD8 | System Data 8 – Refer to SD14, pin-3, for more information. |
| 16 | DREQ5 | DMA Request 5 – Used by I/O resources to request DMA service. Must be held high until associated DACK5 line is active. |
| 17 | MEMW* | Memory Write – This signal instructs a selected memory device to store data currently on the data bus. It is active on all memory write cycles. |
| 18 | DACK5* | DMA Acknowledge 5 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 19 | MEMR* | Memory Read – This signal instructs a selected memory device to drive data onto the data bus. It is active on all memory read cycles. |
| 20 | DREQ0 | DMA Request 0 – Used by I/O resources to request DMA service. Must be held high until associated DACK0 line is active. |
| 21 | LA17 | Latchable Address 17 – These signals (0-23) must be latched by the resource if the line is required for the entire data cycle. |
| 22 | DACK0* | DMA Acknowledge 0 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 23 | LA18 | Latchable Address 18 – Refer to LA17 pin-21, for more information. |
| 24 | IRQ14 | Interrupt Request 14 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 25 | LA19 | Latchable Address 19 – Refer to LA17 pin-21, for more information. |
| 26 | IRQ15 | Interrupt Request 15 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 27 | LA20 | Latchable Address 20 – Refer to LA17 pin-21, for more information. |
| 28 | IRQ12 | Interrupt Request 12 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 29 | LA21 | Latchable Address 21– Refer to LA17 pin-21, for more information. |
| 30 | IRQ11 | Interrupt Request 11 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 31 | LA22 | Latchable Address 22 – Refer to LA17 pin-21, for more information. |
| 32 | IRQ10 | Interrupt Request 10 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 33 | LA23 | Latchable Address 23 – Refer to LA17 pin-21, for more information. |
| 34 | IO16* | I/O Chip Select 16 – This signal is driven low by an I/O slave device to indicate it is capable of performing a 16-bit I/O data transfer. This signal is driven from a decode of the SA15 to SA0 address lines. |
| 35, 36 | GND | Ground |
| 37 | SBHE* | System Byte High Enable – This signal is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8). |
| 38 | M16* | Memory Chip Select 16 – This is signal is driven low by a memory slave device to indicates it is cable of performing a 16-bit memory data transfer. This signal is driven from a decode of the LA23 to LA17 address lines. |
| 39 | SA0 | System Address 0 – These signals (0 to 19) provide system address bits. |
| 40 | OSC | Oscillator – This clock signal operates at 14.3 MHz. This signal is not synchronous with the system clock (SYSCLK). |
| 41 | SA1 | System Address 1– Refer to SA0 pin-39, for more information. |
| 42 | BALE | Buffered Address Latch Enable – This signal is used to latch the LA23 to LA17 signals or decodes of these signals. Addresses are latched on the falling edge of BALE. It is forced high during DMA cycles. When used with AENx, it indicates a valid processor or DMA address. |
| 43 | SA2 | System Address 2 – Refer to SA0 pin-39, for more information. |
| 44 | TC | Terminal Count – This signal is a pulse to indicate a terminal count has been reached on a DMA channel operation. |
| 45 | SA3 | System Address 3 – Refer to SA0 pin-39, for more information. |
| 46 | DACK2* | DMA Acknowledge 2 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 47 | SA4 | System Address 4 – Refer to SA0 pin-39, for more information. |
| 48 | IRQ3 | Interrupt Request 3 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 49 | SA5 | System Address 5 – Refer to SA0 pin-39, for more information. |
| 50 | IRQ4 | Interrupt Request 4 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 51, 52 | VCC | DC Power – +5 volts +/- 5% |
| 53 | SA6 | System Address 6 – Refer to SA0 pin-39, for more information. |
| 54 | IRQ5 | Interrupt Request 5 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 55 | SA7 | System Address 7 – Refer to SA0 pin-39, for more information. |
| 56 | IRQ6 | Interrupt Request 6 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 57 | SA8 | System Address 8 – Refer to SA0 pin-39, for more information. |
| 58 | IRQ7 | Interrupt Request 7 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 59 | SA9 | System Address 9 – Refer to SA0 pin-39, for more information. |
| 60 | SYSCLK | System Clock – This is a free running clock typically in the 8 MHz to 10 MHz range, although its exact frequency is not guaranteed. |
| 61 | SA10 | System Address 10 – Refer to SA0 pin-39, for more information. |
| 62 | REFSH* | Memory Refresh – This signal is driven low to indicate a memory refresh cycle is in progress. Memory is refreshed every 15.6 usec. |
| 63 | SA11 | System Address 11 – Refer to SA0 pin-39, for more information. |
| 64 | DREQ1 | DMA Request 1– Used by I/O resources to request DMA service. Must be held high until associated DACK1 line is active. |
| 65 | SA12 | System Address 12 – Refer to SA0 pin-39, for more information. |
| 66 | DACK1* | DMA Acknowledge 1 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 67, 68 | GND | Ground |
| 69 | SA13 | System Address 13 – Refer to SA0 pin-39, for more information. |
| 70 | DREQ3 | DMA Request 3 – Used by I/O resources to request DMA service. Must be held high until associated DACK3 line is active. |
| 71 | SA14 | System Address 14 – Refer to SA0 pin-39, for more information. |
| 72 | DACK3* | DMA Acknowledge 3 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 73 | SA15 | System Address 15 – Refer to SA0 pin-39, for more information. |
| 74 | IOR* | I/O Read – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to drive read data onto the data bus. |
| 75 | SA16 | System Address 16 – Refer to SA0 pin-39, for more information. |
| 76 | IOW* | I/O Write – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to capture the write data on the data bus. |
| 77 | SA18 | System Address 18 – Refer to SA0 pin-39, for more information. |
| 78 | SA17 | System Address 17 – Refer to SA0 pin-39, for more information. |
| 79 | SA19 | System Address 19 – Refer to SA0 pin-39, for more information. |
| 80 | SMEMR* | System Memory Read – This signal is used by bus owner to request a memory device to drive data onto the data bus and only active for lower 1 MB. Used for legacy compatibility with 8-bit cards. |
| 81 | IOCHRDY | I/O Channel Ready – This signal allows slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signal’s normal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read, or write command. The signal is released high when the device is ready to complete the cycle. |
| 82 | AEN | Address Enable – This signal is used to degate the system processor and other devices from the bus during DMA transfers. When this signal is active, the system DMA controller has control of the address, data, and read/write signals. This signal should be included as part of ISA board select decodes to prevent incorrect board selects during DMA cycles. |
| 83, 84 | VCC | DC Power – +5 volts +/- 5% |
| 85 | SD0 | System Data 0 – Refer to SD14 pin-3, for more information. |
| 86 | SMEMW* | System Memory Write – This signal is used by bus owner to request a memory device to store data currently on the data bus and only active for the lower 1 MB. Used for legacy compatibility with 8-bit cards. |
| 87 | SD2 | System Data 2 – Refer to SD14 pin-3, for more information. |
| 88 | SD1 | System Data 1 – Refer to SD14 pin-3, for more information. |
| 89 | SD3 | System Data 3 – Refer to SD14 pin-3, for more information. |
| 90 | NOWS* | No Wait State – This signal is driven low by a bus slave device to indicate it is capable of performing a bus cycle without inserting any additional wait states. To perform a 16-bit memory cycle without wait states, this signal is derived from an address decode. |
| 91 | DREQ2 | DMA Request 2 – Used by I/O resources to request DMA service. Must be held high until associated DACK2 line is active. |
| 92 | SD4 | System Data 4 – Refer to SD14 pin-3, for more information. |
| 93 | SD5 | System Data 5 – Refer to SD14 pin-3, for more information. |
| 94 | IRQ9 | Interrupt Request 9 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 95 | SD6 | System Data 6 – Refer to SD14 pin-3, for more information. |
| 96 | SD7 | System Data 7 – Refer to SD14 pin-3, for more information. |
| 97 | IOCHK* | I/O Channel Check – This signal may be activated by ISA boards to request that a non-maskable interrupt (NMI) be generated to the system processor. It is driven active to indicate an uncorrectable error has been detected. |
| 98 | RSTDRV | Reset Drive – This signal is used to reset or initialize system logic on power up or subsequent system reset. |
| 99 | GND | Ground |
| 100 | GND | Ground |
# Primary I/O Interface (J3)
The J3 connector has 100 pins and is used for Floppy or Printer (LPT1) interface, Serial interfaces (COM1 and COM2), Mouse and Keyboard interfaces, Infrared (IrDA) interface, and the video interfaces for standard CRT video and LVDS interfaces.
# Floppy Interface
The Floppy interface shares signal lines with the Parallel interface and is provided by the Super I/O chip (LPC47B272). The BIOS settings determine which one is operational. A Standard 34-pin floppy drive connector is listed in Table 3-10 for reference along with the J3 connector pins. This type of connector can be located on the custom baseboard if desired.
• Supports two floppy drives
• 16 bytes of FIFO with data rates up to 1 Mbps
Table 3-10. Simplified Floppy Drive Interface Pin/Signal Descriptions (J3)
| J3 Pin # | Signal | Description |
| 1, 2 | GND | Ground |
| 3 | Red | Red – This is the Red analog output signal to the CRT. |
| 4 | Blue | Blue – This is the Blue analog output signal to the CRT. |
| 5 | HSYNC | Horizontal Sync – This signal is used for the digital horizontal sync output to the CRT. |
| 6 | Green | Green – This is the Green analog output signal to the CRT. |
| 7 | VSYNC | Vertical Sync – This signal is used for the digital vertical sync output to the CRT. |
| 8 | DDCK | Display Data Channel Clock – This signal line provides the data clock signal to the Memory Hub from the monitor. This is part of the Plug and Play standard developed by the VESA trade association. |
| 9 | NC | Not Connected (DETECT*) |
| 10 | DDDA | Display Data Channel Data – This signal line provides information to the Memory Hub about the monitor type, brand, model. This is part of the Plug and Play standard developed by the VESA trade association. |
| 11 | LVDS_ZClk- | Clock Negative Output, Clock, Channel 2 |
| 12 | LVDS_Z3- | Data Negative Output, Line 3, Channel 2 |
| 13 | LVDS_ZClk+ | Clock Positive Output, Clock, Channel 2 |
| 14 | LVDS_Z3+ | Data Positive Output, Line 3, Channel 2 |
| 15, 16 | GND | Ground |
| 17 | LVDS_Z1+ | Data Positive Output, Line 1, Channel 2 |
| 18 | LVDS_Z2+ | Data Positive Output, Line 2, Channel 2 |
| 19 | LVDS_Z1- | Data Negative Output, Line 1, Channel 2 |
| 20 | LVDS_Z2- | Data Negative Output, Line 2, Channel 2 |
| 21, 22 | GND | Ground |
| 23 | LVDS_Y3- | Data Negative Output, Line 3, Channel 1 |
| 24 | LVDS_Z0+ | Data Positive Output, Line 0, Channel 2 |
| 25 | LVDS_Y3+ | Data Positive Output, Line 3, Channel 1 |
| 26 | LVDS_Z0- | Data Negative Output, Line 0, Channel 2 |
| 27, 28 | GND | Ground |
| 29 | LVDS_Y2- | Data Negative Output, Line 2, Channel 1 |
| 30 | LVDS_YClk+ | Clock Positive Output, Clock, Channel 1 |
| 31 | LVDS_Y2+ | Data Positive Output, Line 2, Channel 1 |
| 32 | LVDS_YClk- | Clock Negative Output, Clock, Channel 1 |
| 33, 34 | GND | Ground |
| 35 | LVDS_Y0+ | Data Positive Output, Line 0, Channel 1 |
| 36 | LVDS_Y1+ | Data Positive Output, Line 1, Channel 1 |
| 37 | LVDS_Y0- | Data Negative Output, Line 0, Channel 1 |
| 38 | LVDS_Y1- | Data Negative Output, Line 1, Channel 1 |
| 39, 40 | VCC | DC Power – +5V +/- 5% |
| 41 | FP_I2C_DAT | Flat Panel I2C Data – This is the I2C data interface to the parameter EEPROM used with the flat panel |
| 42 | NC | Not Connected (LTGIO0) |
| 43 | FP_I2C_CLK | Flat Panel I2C Clock – This is the I2C clock interface to the parameter EEPROM used with the flat panel. |
| 44 | BLON* | Backlight On – This signal controls the external backlight power for the flat panel. |
| 45 | BIASON | BIAS ON – This signal controls the flat panel contrast voltage. |
| 46 | DIGON | Digital Power On – This signal controls the digital flat panel power up. |
| 47 | NC | Not Connected (Composite Analog Output) |
| 48 | NC | Not Connected (S-Video Y Analog Output) |
| 49 | NC | Not Connected (Sync Output ) |
| 50 | NC | Not Connected (S-Video C Analog Output) |
| 51 | LPT/FLPY* | Parallel/Floppy Select – This signal selects the parallel or floppy port signals. If this signal is Low at boot time, the floppy drive is selected. If this signal is High at boot time, the parallel port is selected. This state can not be changed until the next boot cycle. |
| 52 | NC | Not Connected (Reserved) |
| 53 | VCC | DC Power – +5 volts +/- 5% |
| 54 | GND | Ground |
| 55 | Strobe* | Parallel Strobe – This output signal is used to strobe data into the printer. I/O pin in ECP/EPP mode. |
| DS0* | Floppy Drive Select 0 – Selects drive 0. |
| 56 | AFD* | Parallel Auto Feed – This is a output signal from the printer to automatically feed one line after each line is printed. |
| DENSEL | Floppy Drive Density Select – This signal indicates if a low (250/300 kbps) or high (500/1 kbps) data rate is selected. |
| 57 | NC | Not Connected (Reserved) |
| 58 | PD7 | Parallel Port Data 7 – This signal (0 to 7) provides a parallel port data signal and is the printer data MSB. |
| 59 | IRRX | IR Receive Data (HPSIR or ASKIR) |
| 60 | ERR* | Parallel Error – This is a status output signal from the printer. A low state indicates an error condition on the printer. |
| HDSEL* | Floppy Head Select – Selects floppy diskette side for Read/Write operations (0 = side 1, 1 = side 0). |
| 61 | IRTX | IR Transmit Data (HPSIR or ASKIR) |
| 62 | PD6 | Parallel Port Data 5 – Refer to pin-58 and 80 for more information. |
| MTR0* | Floppy Motor Control 0 – Select motor on drive 0. |
| 63 | RXD2 | Receive Data 2 – Serial port 2 receive data in. |
| 64 | INIT* | Parallel Initialize - This signal initializes the printer. Output in standard mode, I/O in ECP/EPP mode. |
| DIR* | Floppy Direction - Direction of head movement (0 = inward motion, 1 = outward motion). |
| 65, 66 | GND | Ground |
| 67 | RTS2* | Request To Send 2 - Indicates Serial port 2 is ready to transmit data. Used as hardware handshake with CTS2 for low level flow control. |
| 68 | PD5 | Parallel Port Data 5 - Refer to pin-58 and 80 for more information. |
| 69 | DTR2* | Data Terminal Ready 2 - Indicates Serial port 2 is powered, initialized, and ready. Used as hardware handshake with DSR2 for overall readiness. |
| 70 | SLCTIN | Parallel Select In - This output signal is used to select the printer. I/O pin in ECP/EPP mode. |
| STEP* | Floppy Step - Low pulse for each track-to-track movement of the head. |
| 71 | DCD2* | Data Carrier Detect 2 - Indicates external serial device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR2 as part of the DTR2/DSR2 handshake. |
| 72 | PD4 | Parallel Port Data 4 - Refer to pin-58 and 80 for more information. |
| DSKCHG* | Floppy Disk Change - Senses the drive door is open or the diskette has been changed since the last drive selection. |
| 73 | DSR2* | Data Set Ready 2 - Indicates external serial device is powered, initialized, and ready. Used as hardware handshake with DTR2 for overall readiness. |
| 74 | PD3 | Parallel Port Data 3 - Refer to pin-58 and 80 for more information. |
| RDATA* | Floppy Read Data - Raw serial bit stream from drive for read operations. |
| 75 | CTS2* | Clear To Send 2 - Indicates external serial device is ready to receive data. Used as hardware handshake with RTS2 for low level flow control. |
| 76 | PD2 | Parallel Port Data 2 - Refer to pin-58 and 80 for more information. |
| WPT* | Floppy Write Protect - Senses the diskette is write protected. |
| 77 | TXD2 | Transmit Data 2 - Serial port 2 transmit data out. |
| 78 | PD1 | Parallel Port Data 1 - Refer to pin-58 and 80 for more information. |
| TRK0* | Floppy Track 0 - Sensor detects when head is positioned over track 0. |
| 79 | RI2* | Ring Indicator 2 - Indicates external serial device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. |
| 80 | PD0 | Parallel Port Data 0 - This pin (0 to 7) provides a parallel port data signal and is the printer data LSB. |
| INDEX* | Floppy Index - Sense to detect that the head is positioned over the beginning of a track. |
| 81, 82 | VCC | +5 volts +/- 5% |
| 83 | RXD1 | Receive Data 1 - Serial port 1 receive data in. |
| 84 | ACK* | Parallel Acknowledge - This is a status input signal from the printer. A Low State indicates it has received the data and is ready to accept new data. |
| DR1 | Floppy Drive Select 1 - This signal selects drive 1. |
| 85 | RTS1* | Request To Send 1 – Indicates Serial port 1 is ready to transmit data. Used as hardware handshake with CTS1 for low level flow control. |
| 86 | BUSY | Parallel Busy – This is a status input signal from the printer. A high state indicates the printer is not ready to accept data. |
| MTR1 | Floppy Motor Control 1 – This signal selects motor on drive 1. |
| 87 | DTR1* | Data Terminal Ready 1 – Indicates Serial port 1 is powered, initialized, and ready. Used as hardware handshake with DSR1 for overall readiness. |
| 88 | PE | Parallel Paper End – This is a status input signal from the printer. A high state indicates it is out of paper. |
| WDATA* | Floppy Write Data – Sends encoded data to drive for write operations. |
| 89 | DCD1* | Data Carrier Detect 1 – Indicates external serial device is detecting a carrier signal (i.e., a communication channel is currently open). In direct connect environments, this input is driven by DTR1 as part of the DTR1/DSR1 handshake. |
| 90 | SLCT | Parallel Select – This is a status output signal from the printer. A high state indicates it is selected and powered on. |
| WGATE* | Floppy Write Enable – Signal enables current flow in drive write head. |
| 91 | DSR1* | Data Set Ready 1 – Indicates external serial device is powered, initialized, and ready. Used as hardware handshake with DTR1 for overall readiness. |
| 92 | MSCLK | Mouse Clock signal – This signal clocks the data from the mouse. |
| 93 | CTS1* | Clear To Send 1 – Indicates external serial device is ready to receive data. Used as hardware handshake with RTS1 for low level flow control. |
| 94 | MSDAT | Mouse Data signal – This signal provides the mouse data. |
| 95 | TXD1 | Transmit Data 1 – Serial port 1 transmit data out. |
| 96 | KBCLK | Keyboard Clock signal – This signal clocks the data from the keyboard. |
| 97 | RI1* | Ring Indicator 1 – Indicates external serial device is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. |
| 98 | KBDAT | Keyboard Data signal – This signal provides the keyboard data. |
| 99 | GND | Ground |
| 100 | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
# IDE and Auxiliary Interface (J4)
The J4 connector has 100 pins and is used for Primary IDE, Secondary IDE, Ethernet port, RTC/Battery, speaker, power management, SMBus, and miscellaneous power interface signals.
# IDE Ports
• Supports 2 EIDE channels (Primary and Secondary)
• Supports EIDE Ultra DMA 33/66/100 in Master Mode
• Supports ATAPI compliant devices including DVD devices
• Supports PIO IDE transfers up to 14 Mbytes/sec
• Supports IDE Bus Master transfers up to 100 Mbytes/sec
The standard 40-pin cable pin-outs are listed in Tables 3-17 and 3-18 for reference along with the J4 connector pins. One or both channels can be routed to the IDE connector or a compact flash socket on a custom baseboard per the application requirements.
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 3-17. Simplified Primary IDE Interface Pin/Signal Descriptions (J4)
| J4 Pin # | Signal | 40-Pin # | Description |
| 98 | HDRST* | 1 | Hard Reset – Low active hardware reset (RSTDRV inverted) |
| GND | 2 | Ground |
| 96 | PIDE_D7 | 3 | Disk Data 7– These signals (0 to 15) provide the disk data signals |
| 92 | PIDE_D8 | 4 | Disk Data 8 – Refer to D7, pin-3, for more information. |
| 88 | PIDE_D6 | 5 | Disk Data 6 – Refer to D7, pin-3, for more information. |
| 86 | PIDE_D9 | 6 | Disk Data 9 – Refer to D7, pin-3, for more information. |
| 84 | PIDE_D5 | 7 | Disk Data 5 – Refer to D7, pin-3, for more information. |
| 80 | PIDE_D10 | 8 | Disk Data 10 – Refer to D7, pin-3, for more information. |
| 78 | PIDE_D4 | 9 | Disk Data 4 – Refer to D7, pin-3, for more information. |
| 76 | PIDE_D11 | 10 | Disk Data 11 – Refer to D7, pin-3, for more information. |
| 74 | PIDE_D3 | 11 | Disk Data 3 – Refer to D7, pin-3, for more information. |
| 72 | PIDE_D12 | 12 | Disk Data 12 – Refer to D7, pin-3, for more information. |
| 70 | PIDE_D2 | 13 | Disk Data 2 – Refer to D7, pin-3, for more information. |
| 68 | PIDE_D13 | 14 | Disk Data 13 – Refer to D7, pin-3, for more information. |
| 64 | PIDE_D1 | 15 | Disk Data 1 – Refer to D7, pin-3, for more information. |
| 62 | PIDE_D14 | 16 | Disk Data 14 – Refer to D7, pin-3, for more information. |
| 60 | PIDE_D0 | 17 | Disk Data 0 – Refer to D7, pin-3, for more information. |
| 58 | PIDE_D15 | 18 | Disk Data 15 – Refer to D7, pin-3, for more information. |
| GND | 19 | Ground |
| Key | 20 | Key pin plug |
| 56 | PIDE_DRQ | 21 | DMA Request – Used for DMA transfers between host and drive(direction of transfer controlled by IOR and IOW). Also used in an asynchronous mode with ACK. Drive asserts an IRQ when ready to transfer or receive data. |
| GND | 22 | Ground |
| 54 | PIDE_IOW* | 23 | Drive I/O Write – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| GND | 24 | Ground |
| 52 | PIDE_IOR* | 25 | Drive I/O Read – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| GND | 26 | Ground |
| 48 | PIDE_RDY | 27 | I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 90 | CBLID_P* | 28 | Cable ID Select – Detects the presence of an 80 conductor IDE cable on the primary IDE channel. This allows BIOS or system software to determine if is necessary to enable high-speed transfer modes (DMA66 or DMA100). |
| 46 | PIDE_AK* | 29 | DMA Channel Acknowledge – Used by the host to acknowledge data has been accepted or data is available. Used in response to DMARQ asserted. |
| GND | 30 | Ground |
| 44 | PIDE_INTRQ | 31 | Drive Interrupt Request (IRQ 14) – Asserted by drive when a pending interrupt exist (PIO transfer of data to or from the drive to the host). |
| NC | 32 | Not Connected (IOCS16*) |
| 40 | PIDE_A1 | 33 | Drive Address Bus 1 – Used <0 to 2> to indicate which byte in the ATA command block or control block (register) is being accessed. |
| NC | 34 | Not Connected (Passed Diagnostics) |
| 38 | PIDE_A0 | 35 | Drive Address Bus 0 – Refer to J4, pin-40, for more information. |
| 36 | PIDE_A2 | 36 | Drive Address Bus 2 – Refer to J4, pin-40, for more information. |
| 32 | PIDE_CS1* | 37 | Chip Select 0 – Selects host-accessible Command Block Register. |
| 30 | PIDE_CS3* | 38 | Chip Select 1 – Selects host-accessible Command Block Register. |
| NC | 39 | Not Connected (Drive Active/Drive Present) |
| GND | 40 | Ground |
Table 3-18. Simplified Secondary IDE Interface Pin/Signal Descriptions (J4)
| J4 Pin # | Signal | 40-Pin # | Description |
| NC | 1 | Not Connected (Hard Reset) |
| GND | 2 | Ground |
| 94 | SIDE_D7 | 3 | Disk Data – These signals <0 to 15> provide the disk data signals. |
| 87 | SIDE_D8 | 4 | Disk Data 8 – Refer to D7, pin-3, for more information. |
| 85 | SIDE_D6 | 5 | Disk Data 6 – Refer to D7, pin-3, for more information. |
| 83 | SIDE_D9 | 6 | Disk Data 9 – Refer to D7, pin-3, for more information. |
| 79 | SIDE_D5 | 7 | Disk Data 5 – Refer to D7, pin-3, for more information. |
| 77 | SIDE_D10 | 8 | Disk Data 10 – Refer to D7, pin-3, for more information. |
| 75 | SIDE_D4 | 9 | Disk Data 4 – Refer to D7, pin-3, for more information. |
| 73 | SIDE_D11 | 10 | Disk Data 11 – Refer to D7, pin-3, for more information. |
| 71 | SIDE_D3 | 11 | Disk Data 3 – Refer to D7, pin-3, for more information. |
| 69 | SIDE_D12 | 12 | Disk Data 12 – Refer to D7, pin-3, for more information. |
| 67 | SIDE_D2 | 13 | Disk Data 2 – Refer to D7, pin-3, for more information. |
| 63 | SIDE_D13 | 14 | Disk Data 13 – Refer to D7, pin-3, for more information. |
| 61 | SIDE_D1 | 15 | Disk Data 1 – Refer to D7, pin-3, for more information. |
| 59 | SIDE_D14 | 16 | Disk Data 14 – Refer to D7, pin-3, for more information. |
| 57 | SIDE_D0 | 17 | Disk Data 0 – Refer to D7, pin-3, for more information. |
| 55 | SIDE_D15 | 18 | Disk Data 15 – Refer to D7, pin-3, for more information. |
| GND | 19 | Ground |
| Key | 20 | Key pin plug |
| 53 | SIDE_DRQ | 21 | DMA Request – Used for DMA transfers between host and drive(direction of transfer controlled by IOR and IOW). Also used in an asynchronous mode with ACK. Drive asserts an IRQ when ready to transfer or receive data. |
| GND | 22 | Ground |
| 51 | SIDE_IOW* | 23 | Drive I/O Write – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| GND | 24 | Ground |
| 47 | SIDE_IOR* | 25 | Drive I/O Read – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| GND | 26 | Ground |
| 45 | SIDE_RDY | 27 | I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| NC | 28 | Not Connected (Cable ID) |
| 43 | SIDE_AK* | 29 | DMA Channel Acknowledge – Used by the host to acknowledge data has been accepted or data is available. Used in response to DMARQ asserted. |
| GND | 30 | Ground |
| 39 | SIDE_INTRQ | 31 | Drive Interrupt Request (IRQ 15) – Asserted by drive when a pending interrupt exist (PIO transfer of data to or from the drive to the host). |
| NC | 32 | Not Connected (IOCS16*) |
| 37 | SIDE_A1 | 33 | Drive Address Bus 1 – Used <0 to 2> to indicate which byte in the ATA command block or control block (register) is being accessed. |
| 35 | SPDIAG* | 34 | Passed Diagnostics – Used for Master/Slave negotiation on the Secondary IDE channel. If it is asserted by the Slave, indicates to master, slave has passed its internal Diagnostics command. If a compact flash is connected to the baseboard, this signal must be routed to the SDASP pin of any other device connected to the Secondary IDE channel.This pin may also be used to detect the presence of an 80 conductor IDE cable, which is required for support of the DMA66 or DMA100 high-speed transfers. |
| 31 | SIDE_A0 | 35 | Drive Address Bus 0 – Refer to J4, pin-37, for more information. |
| 29 | SIDE_A2 | 36 | Drive Address Bus 2 – Refer to J4, pin-37, for more information. |
| 27 | SIDE_CS1* | 37 | Chip Select 0 – Selects host-accessible Command Block Register. |
| 25 | SIDE_CS3* | 38 | Chip Select 1 – Selects host-accessible Command Block Register. |
| 28 | SDASP* | 39 | Drive Active/Drive Present – This signal is time-multiplexed and indicates the secondary drive is present and active. If a compact flash is connected to the baseboard, this signal must be routed to the SDASP pin of any other device connected to the Secondary IDE channel. Can also used for Master/Slave negotiation on the Secondary IDE channel. |
| GND | 40 | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
# Ethernet Port Interface
The Ethernet solution is provided by an Intel 82551QM Fast Ethernet PCI controller chip, which consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551QM is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82551QM to perform high-speed data transfers over the PCI bus. The 82551QM bus master capabilities enable the component to process high-level commands and perform multiple operations, thereby off-loading communication tasks from the system CPU.
• Routed to J4 connector
• Low power 3.3 V device
• Backward software compatible to the 82559, 82558, and 82557
• Chained memory structure
• Supports full duplex or half-duplex operation
• Supports full duplex operation at 10 Mbps and 100 Mbps
• Supports half-duplex mode with enhanced performance by a proprietary collision reduction mechanism
• Provides IEEE 802.3 10BaseT/100BaseT compatible physical layer
• Supports data transmission with minimum interframe spacing (IFS).
• Supports IEEE 802.3u Auto-Negotiation
• Provides 3 KB transmit and 3 KB receive FIFOs (helps prevent data underflow and overflow)
• Provides IEEE 802.3x 100BASE-TX flow control
• Improved dynamic transmit chaining with multiple priorities transmit queues
• Supports an Ethernet port RJ-45 connector and the magnetics on the baseboard only
Table 3-19. Simplified Ethernet Port Pin/Signal Descriptions (J4)
| J4 Pin # | Signal | Description |
| 1, 2 | GND | Ground |
| 3 | 5V_SB | 5 volt Suspend – This control signal is sent to the ATX power supply for a suspended or standby state. |
| 4 | PWGIN | Power Good In – This active high input signal indicates to the ETX 802, the power is good and it can begin the boot process. |
| 5 | PS_ON | Power Supply On – This active-low output signal from the ETX 802 is sent to the ATX power supply from the to turn it on. |
| 6 | SPEAKER | Speaker – This PC speaker output signal must be connected to a speaker (piezoelectric or dynamic) on the baseboard to hear the output (beeps). |
| 7 | PWRBTN* | Power Button – This signal provides a ground temporally through an open collector driver to the ATX power supply to change states (turn it on). |
| 8 | BATT | Battery Voltage – This is the + battery connection to baseboard for +3 volt lithium backup battery used for RTC operation and CMOS non-volatile memory. |
| 9 | NC | Not Connected (KBINH) |
| 10 | LILED | Link Integrity LED – The LINK LED pin indicates link integrity. If the link is valid in either 10 or 100Mbps, the LED is on; if the link is invalid, the LED is off. |
| 11 | RSMRST* | Resume Reset – This signal is driven low by external circuitry to reset the power management logic on the ETX 802. |
| 12 | ACTLED | Activity LED – The Activity LED pin indicates either transmit or receive activity. When activity is present, the activity LED is on; when no activity is present, the activity LED is off. |
| 13 | NC | Not Connected (ROMKBCS*) |
| 14 | SPDLED | Speed LED – The speed LED pin indicates the speed. The speed LED will be on at 100 Mbps and off at 10 Mbps. |
| 15 | NC | Not Connected (EXT_PRG) |
| 16 | NC | Not Connected ( $I^{2}CLK$ ) |
| 17, 18 | VCC | DC Power – +5 volts +/-5% |
| 19 | OVCR* | Over Current Detect – This signal indicates a USB over-current condition. |
| 20 | NC | Not Connected (GPCS*) |
| 21 | EXTSMI* | Extern System Management Interrupt – This signal is provided by external circuitry to initiate an SMI event with the ETX 802. |
| 22 | NC | Not Connected ( $I^{2}DAT$ ) |
| 23 | SMBCLK | System Management Bus Clock – This signal is used to support internal and external SMBus devices, such as temperature and battery monitoring. |
| 24 | SMBDATA | System Management Bus Data – This signal is used to support internal and external SMBus devices, such as temperature and battery monitoring. |
| 25 | SIDE_CS3* | Secondary Chip Select 1 – Selects host-accessible Command Block Register. |
| 26 | SMBALRT* | System Management Bus Alert – This signal is used by SMBus devices to signal an event on the SMBus. |
| 27 | SIDE_CS1* | Secondary Chip Select 0 – Selects host-accessible Command Block Register. |
| 28 | SDASP | Drive Active/Drive Present – This signal is time-multiplexed and indicates the secondary drive is present and active. If a compact flash is connected to the baseboard, this signal must be routed to the SDASP pin of any another device connected to the Secondary IDE channel. May also be used for Master/Slave negotiation on the Secondary IDE channel. |
| 29 | SIDE_A2 | Secondary Drive Address Bus 2 – Used <0 to 2> to indicate which byte in the ATA command block or control block (register) is being accessed. |
| 30 | PIDE_CS3* | Primary Chip Select 1 – Selects host-accessible Command Block Register. |
| 31 | SIDE_A0 | Secondary Drive Address Bus 0 – Refer to J4, pin-29, for more information. |
| 32 | PIDE_CS1* | Primary Chip Select 0 – Selects host-accessible Command Block Register. |
| 33, 34 | GND | Ground |
| 35 | SPDIAG | Passed Diagnostics – This signal is used for Master/Slave negotiation on the Secondary IDE channel. It is asserted by the Slave to indicate to master that the slave has passed its internal Diagnostics command. If a compact flash is connected to the baseboard, this signal must be routed to the SDASP pin of any another device connected to the Secondary IDE channel.May also be used to detect the presence of an 80-conductor IDE cable, which is required for support of the DMA66 or DMA100 high-speed transfers. |
| 36 | PIDE_A2 | Primary Drive Address Bus 2 – Used <0 to 2> to indicate which byte in the ATA command block or control block (register) is being accessed. |
| 37 | SIDE_A1 | Secondary Drive Address Bus 1 – Refer to J4, pin-29, for more information. |
| 38 | PIDE_A0 | Primary Drive Address Bus 0 – Refer to J4, pin-36, for more information. |
| 39 | SIDE_INTRQ | Secondary Drive Interrupt Request (IRQ 15) – Asserted by drive when it has pending interrupt (PIO transfer of data to or from the drive to the host). |
| 40 | PIDE_A1 | Primary Drive Address Bus 1 – Refer to J4, pin-36, for more information. |
| 41 | BATLOW* | Battery Low – This external signal to the ETX 802 indicates when the external battery is low. |
| 42 | NC | Not Connected (GPE1*) |
| 43 | SIDE_AK* | Secondary DMA Channel Acknowledge – Used by the host to acknowledge data has been accepted or data is available. Used in response to SIDE_DMARQ when asserted. |
| 44 | PIDE_INTRQ | Primary Drive Interrupt Request (IRQ 14) – Asserted by drive when it has pending interrupt (PIO transfer of data to or from the drive to the host). |
| 45 | SIDE_RDY | Secondary I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 46 | PIDE_AK* | Primary DMA Channel Acknowledge – Used by the host to acknowledge data has been accepted or data is available. Used in response to PIDE_DMARQ when asserted. |
| 47 | SIDE_IOR* | Secondary Drive I/O Read – Secondary strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 48 | PIDE_RDY | Primary I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 49, 50 | VCC | DC Power – +5 volts +/-5% |
| 51 | SIDE_IOW* | Secondary Drive I/O Write – Secondary strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 52 | PIDE_IOR* | Primary Drive I/O Read – Primary strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 53 | SIDE_DRQ | Secondary DMA Request – Used for DMA transfers between host and drive (direction of transfer controlled by IOR* and IOW*). Also used in an asynchronous mode with ACK*. Drive asserts an IRQ when ready to transfer or receive data. |
| 54 | PIDE_IOW* | Primary Drive I/O Write – Primary strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 55 | SIDE_D15 | Secondary Disk Data 15 – These signals <0 to 15> provide the Secondary IDE disk data signals. |
| 56 | PIDE_DRQ | Primary DMA Request – Used for DMA transfers between host and drive (direction of transfer controlled by IOR* and IOW*). Also used in an asynchronous mode with ACK*. Drive asserts an IRQ when ready to transfer or receive data. |
| 57 | SIDE_D0 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 58 | PIDE_D15 | Primary Disk Data 15 – These signals (0 to 15) provide the Primary IDE disk data signals. |
| 59 | SIDE_D14 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 60 | PIDE_D0 | Primary Disk Data 0 – Refer to J4, pin-58 for more information. |
| 61 | SIDE_D1 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 62 | PIDE_D14 | Primary Disk Data 14 – Refer to J4, pin-58 for more information. |
| 63 | SIDE_D13 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 64 | PIDE_D1 | Primary Disk Data 1 – Refer to J4, pin-58 for more information. |
| 65, 66 | GND | Ground |
| 67 | SIDE_D2 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 68 | PIDE_D13 | Primary Disk Data 13 – Refer to J4, pin-58 for more information. |
| 69 | SIDE_D12 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 70 | PIDE_D2 | Primary Disk Data 2 – Refer to J4, pin-58 for more information. |
| 71 | SIDE_D3 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 72 | PIDE_D12 | Primary Disk Data 12 – Refer to J4, pin-58 for more information. |
| 73 | SIDE_D11 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 74 | PIDE_D3 | Primary Disk Data 3 – Refer to J4, pin-58 for more information. |
| 75 | SIDE_D4 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 76 | PIDE_D11 | Primary Disk Data 11 – Refer to J4, pin-58 for more information. |
| 77 | SIDE_D10 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 78 | PIDE_D4 | Primary Disk Data 4 – Refer to J4, pin-58 for more information. |
| 79 | SIDE_D5 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 80 | PIDE_D10 | Primary Disk Data 10 – Refer to J4, pin-58 for more information. |
| 81, 82 | VCC | DC Power – +5 volts +/-5% |
| 83 | SIDE_D9 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 84 | PIDE_D5 | Primary Disk Data 5 – Refer to J4, pin-58 for more information. |
| 85 | SIDE_D6 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 86 | PIDE_D9 | Primary Disk Data 9 – Refer to J4, pin-58 for more information. |
| 87 | SIDE_D8 | Secondary Disk Data 15 – Refer to pin-55 for more information. |
| 88 | PIDE_D6 | Primary Disk Data 6 – Refer to J4, pin-58 for more information. |
| 89 | NC | Not Connected (GPE2*) |
| 90 | PCBLID* | Primary Cable ID Select – Used to detects the presence of an 80 conductor IDE cable on the primary IDE channel. This allows BIOS or system software to determine if is necessary to enable the high-speed transfer modes (DMA66 or DMA100). |
| 91 | RXD- | Half of Ethernet Analog Twisted Pair Receive Differential Pair – This pin and pin-93 make up the Receive twisted pair and receive the serial bit stream on the Unshielded Twisted Pair Cable (UTP). |
| 92 | PIDE_D8 | Primary Disk Data 8 – Refer to J4, pin-58 for more information. |
| 93 | RXD+ | Part of Ethernet Analog Twisted Pair Receive Differential Pair – Refer to pin-91 for more information. |
| 94 | SIDE_D7 | Secondary Disk Data 15 – Refer to J4, pin-55 for more information. |
| 95 | TXD- | Half of Ethernet Analog Twisted Pair Transmit Differential Pair – This pin and pin-97 make up the Transmit twisted pair and transmit the serial bit stream on the Unshielded Twisted Pair Cable (UTP). |
| 96 | PIDE_D7 | Primary Disk Data 7 – Refer to J4, pin-58 for more information. |
| 97 | TXD+ | Part of Ethernet Analog Twisted Pair Transmit Differential Pair – Refer to pin-95 for more information. |
| 98 | HDRST* | Hard Reset – Low active hardware reset (RSTDRV inverted) |
| 99 | GND | Ground |
| 100 | GND | Ground |
Notes: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
# Miscellaneous
# Oops! Jumper (BIOS Recovery)
The Oops! jumper is provided in the event the BIOS settings you’ve selected prevent you from booting the system. By using the Oops! jumper you can prevent the current BIOS settings in the Flash memory from being loaded, forcing the use of the default settings. Connect the DTR pin to the RI pin on serial port 1 (COM 1) on the baseboard prior to boot up to prevent the present BIOS settings from loading. After booting with the Oops! jumper in place, remove the Oops! jumper from the baseboard connector and go into the BIOS Setup Utility. Change the desired BIOS settings, or select the default settings, and save changes before rebooting the system.
To convert a standard DB9 connector to a Oops! jumper for use on the custom baseboard, short together the DTR (4) and RI (9) pins on the rear of the connector as shown in Figure 3-1 on the Serial Port 1 DB9 connector.
Figure 3-1. Oops! Jumper Connection
# Serial Console (Remote Access)
The BIOS Setup Utility supports the serial console (or console redirection) feature, but refers to it as Remote Access. This I/O function can be accessed by an ANSI-compatible serial terminal, or the equivalent terminal emulation software running on another system. This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display (sometimes referred to as a headless system).
# Serial Console Setup
The serial console feature is implemented by connecting a standard null modem cable or a modified serial cable (or “Hot Cable”) between one of the serial ports, such as Serial 1 or Serial 2, and the serial terminal or a PC with communications software. The BIOS Setup Utility controls the serial console settings for the ETX 802. Refer to Accessing BIOS Setup Utility (Remote Access/Serial Console) and Advanced settings, in Chapter 4, BIOS Setup Utility for the Remote Access option to set the serial terminal, or PC with communications software.
# Hot (Serial) Cable
To convert a standard serial cable to a Hot Cable for use on the custom baseboard, two pins must be shorted together at the Serial port DB9 connector. Short together the RTS (7) and RI (9) pins on Serial port DB9 connector as shown in Figure 3-2.
Figure 3-2. Hot Cable Jumper
# Temperature Monitoring
The temperature monitoring function is preformed by Analog Devices, ADM1023 chip and it takes an input connection from the thermal diode in the Intel Celeron M or Pentium M CPU. The ADM1023 chip uses the two-wire SMBus interface to communicate with the other devices on the SMBus, including the I/O Hub (82801DBM).
# NOTE
The ETX 802 requires a heatsink for all Intel CPUs and the Memory Hub (Northbridge), but no fan, below +70° C. The 1.4 GHz Pentium M requires a fan for extended temperatures (+70° to +85° C).
# Watchdog Timer (WDT)
The watchdog timer (WDT) restarts the system if an error or mishap occurs, allowing the system to recover from the mishap, even though the error condition may still exist. Possible problems include failure to boot properly, loss of control by the application software, failure of an interface device, unexpected conditions on the bus, or other hardware or software malfunctions.
The WDT (watchdog timer) can be used both during the boot process and during normal system operation.
• During the Boot process – If the operating system fails to boot in the time interval set in the BIOS, the system will reset.
The watchdog timer (WDT) is enabled and configured in the Boot settings screen of the BIOS Setup Utility. Set the WDT for a time-out interval in seconds, between 1 and 255, in one second increments. Ensure you allow enough time for the operating system to boot. The OS or application must tickle (reset) the WDT before the timer expires. This can be done by accessing the hardware directly or through a BIOS call.
During System Operation – An application can set up the WDT hardware through a BIOS call, or by accessing the hardware directly. Some Ampro Board Support Packages provide an API interface to the WDT. The application must tickle (reset) the WDT before the timer expires or the system will be reset. The BIOS implements interrupt 15 function 0C3h to manipulate the WDT.
Watchdog Code examples – Ampro will provide code examples on the ETX 802 Doc & SW CD-ROM illustrating how to control the WDT in the final release.
# Power Interface
The ETX 802 draws its input voltage (+5V) through the four connectors (X1, X2, X3, X4) on the custom baseboard, which requires an external power supply, typically an ATX power supply or other power source as the application requires. The ETX 802 generates its own internal voltages onboard, including the CPU core voltages and requires the externally supplied +5 volts DC +/- 5%.
The –5V, –12V, +12V and +3.3V voltages used for the PCI and ISA buses and the LVDS video connector are supplied to the baseboard and ETX 802 module from the externally connected power supply, typically an ATX power supply.
# Optional CPU Fan (P1)
Table 3-23 lists the pins and signals of the optional CPU Fan and it has 3 pins, single row, with 0.100" pin spacing.
Table 3-23. CPU Fan (P1)