| Pin # | Signal | Input/Output | Description |
| 1 (A1) | GND/(Key) | | Key - Digital Ground |
| 2 (A2) | VI/O | | +5 volts ±5% power supply |
| 3 (A3) | AD05 | T/S | PCI Address and Data Bus Line 5 – There are 32 signal lines (address and data) and the signals on these lines are multiplexed. A bus transaction consists of an address followed by one or more data cycles. |
| 4 (A4) | C/BE0* | T/S | PCI Bus Command/Byte Enable 0 – This signal line is one of four signal lines. These signal lines are multiplexed, so that during the address cycle, the command is defined and during the data cycle, the byte enable is defined. |
| 5 (A5) | GND | | Digital Ground |
| 6 (A6) | AD11 | T/S | PCI Address and Data Bus Line 11 – Refer to Pin 3 for more information. |
| 7 (A7) | AD14 | T/S | PCI Address and Data Bus Line 14 – Refer to Pin 3 for more information. |
| 8 (A8) | +3.3V | | +3.3 volts ±5% power supply |
| 9 (A9) | SERR* | O/D | System Error – This signal is for reporting address parity errors. |
| 10 (A10) | GND | | Digital Ground |
| 11 (A11) | STOP* | S/T/S | Stop – This signal indicates the current selected device is requesting the master to stop the current transaction. |
| 12 (A12) | +3.3V | | +3.3 volts ±5% power supply |
| 13 (A13) | FRAME* | S/T/S | PCI bus Frame access – This signal is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle |
| 14 (A14) | GND | | Digital Ground |
| 15 (A15) | AD18 | T/S | PCI Address and Data Bus Line 18 – Refer to Pin 3 for more information. |
| 16 (A16) | AD21 | T/S | PCI Address and Data Bus Line 21 – Refer to Pin 3 for more information. |
| 17 (A17) | +3.3V | | +3.3 volts ±5% power supply |
| 18 (A18) | IDSEL0 | In | Initialization Device Select 0 – This signal line is one of four signal lines. These signals are used as the chip-select signals during configuration. |
| 19 (A19) | AD24 | T/S | PCI Address and Data Bus Line 24 – Refer to Pin 3 for more information. |
| 20 (A20) | GND | | Digital Ground |
| 21 (A21) | AD29 | T/S | PCI Address and Data Bus Line 29 – Refer to Pin 3 for more information. |
| 22 (A22) | +5V | | +5 volts ±5% power supply |
| 23 (A23) | REQ0* | T/S | Bus Request 0 – This signal line is one of four signal lines. These signals indicate the device desires use of the bus to the arbitrator. |
| 24 (A24) | GND | | Digital Ground |
| 25 (A25) | GNT1* | T/S | Grant 1 – This signal line is one of four signal lines. These signal lines indicate access has been granted to the requesting device (PCI Masters). |
| 26 (A26) | +5V | | +5 volts ±5% power supply |
| 27 (A27) | CLK2 | In | PCI clock 2 – This signal line is one of four signal lines. These clock signals provide the timing outputs for four external PCI devices and the timing for all transactions on the PCI bus. |
| 28 (A28) | GND | | Digital Ground |
| 29 (A29) | +12V | | +12 volts ±5% power supply |
| 30 (A30) | NC | | Not connected - Reserved |
| 31 (B1) | NC | | Not connected - Reserved |
| 32 (B2) | AD02 | T/S | PCI Address and Data Bus Line 2 – Refer to Pin 3 for more information. |
| 33 (B3) | GND | | Digital Ground |
| 34 (B4) | AD07 | T/S | PCI Address and Data Bus Line 7 – Refer to Pin 3 for more information. |
| 35 (B5) | AD09 | T/S | PCI Address and Data Bus Line 9 – Refer to Pin 3 for more information. |
| 36 (B6) | VI/O | | +5 volts ±5% power supply |
| 37 (B7) | AD13 | T/S | PCI Address and Data Bus Lines 13 – Refer to Pin 3 for more information. |
| 38 (B8) | C/BE1* | T/S | PCI Bus Command/Byte Enable 1 – Refer to Pin 4 for more information. |
| 39 (B9) | GND | | Digital Ground |
| 40 (B10) | PERR* | | Parity Error – This signal is for reporting data parity errors. |
| 41 (B11) | +3.3V | | +3.3 volts ±5% power supply |
| 42 (B12) | TRDY* | S/T/S | Target Ready – This signal indicates the selected device's ability to complete the current cycle of transaction. Both IRDY* and TRDY* must be asserted to terminate a data cycle. |
| 43 (B13) | GND | | Digital Ground |
| 44 (B14) | AD16 | T/S | PCI Address and Data Bus Line 16 – Refer to Pin 3 for more information. |
| 45 (B15) | +3.3V | | +3.3 volts ±5% power supply |
| 46 (B16) | AD20 | T/S | PCI Address and Data Bus Lines 20 – Refer to Pin 3 for more information. |
| 47 (B17) | AD23 | T/S | PCI Address and Data Bus Line 23 – Refer to Pin 3 for more information. |
| 48 (B18) | GND | | Digital Ground |
| 49 (B19) | C/BE3* | T/S | PCI Bus Command/Byte Enable 3 – Refer to Pin 4 for more information. |
| 50 (B20) | AD26 | T/S | PCI Address and Data Bus Line 26 – Refer to Pin 3 for more information. |
| 51 (B21) | +5V | | +5 volts ±5% power supply |
| 52 (B22) | AD30 | T/S | PCI Address and Data Bus Line 30 – Refer to Pin 3 for more information. |
| 53 (B23) | GND | | Digital Ground |
| 54 (B24) | REQ2* | T/S | Bus Request 2 – Refer to Pin 23 for more information. |
| 55 (B25) | VI/O | | +5 volts ±5% power supply |
| 56 (B26) | CLK0 | In | PCI clock 0– Refer to Pin 27 for more information. |
| 57 (B27) | +5V | | +5 volts ±5% power supply |
| 58 (B28) | INTD* | O/D | Interrupt D – This signal is used to request interrupts only for multi-function devices. |
| 59 (B29) | INTA* | O/D | Interrupt A – This signal is used to request an interrupt. |
| 60 (B30) | REQ3* | T/S | -Bus Request 3 – Refer to Pin 23 for more information. |
| 61 (C1) | +5 | | +5 volts ±5% power supply |
| 62 (C2) | AD01 | T/S | PCI Address and Data Bus Line 1 – Refer to Pin 3 for more information. |
| 63 (C3) | AD04 | T/S | PCI Address and Data Bus Lines 4 – Refer to Pin 3 for more information. |
| 64 (C4) | GND | | Digital Ground |
| 65 (C5) | AD08 | T/S | PCI Address and Data Bus Line 8 – Refer to Pin 3 for more information. |
| 66 (C6) | AD10 | T/S | PCI Address and Data Bus Line 10 – Refer to Pin 3 for more information. |
| 67 (C7) | GND | | Digital Ground |
| 68 (C8) | AD15 | T/S | PCI Address and Data Bus Line 15 – Refer to Pin 3 for more information. |
| 69 (C9) | NC | | Not connected (SB0* - Snoop Backoff) |
| 70 (C10) | +3.3V | | +3.3 volts ±5% power supply |
| 71 (C11) | NC | S/T/S | Not connected (Lock*) |
| 72 (C12) | GND | | Digital Ground |
| 73 (C13) | IRDY* | S/T/S | Initiator Ready – This signal indicates the master's ability to complete the current data cycle of the transaction. |
| 74 (C14) | +3.3V | | +3.3 volts ±5% power supply |
| 75 (C15) | AD17 | T/S | PCI Address and Data Bus Line 17 – Refer to Pin 3 for more information. |
| 76 (C16) | GND | | Digital Ground |
| 77 (C17) | AD22 | T/S | PCI Address and Data Bus Line 22 – Refer to Pin 3 for more information. |
| 78 (C18) | IDSEL1 | | Initialization Device Select 1 – Refer to Pin 18 for more information. |
| 79 (C19) | VI/O | NC | (+5V) Not connected |
| 80 (C20) | AD25 | T/S | PCI Address and Data Bus Line 25 – Refer to Pin 3 for more information. |
| 81 (C21) | AD28 | T/S | PCI Address and Data Bus Line 28 – Refer to Pin 3 for more information. |
| 82 (C22) | GND | | Digital Ground |
| 83 (C23) | REQ1* | T/S | Bus Request 1 – Refer to Pin 23 for more information. |
| 84 (C24) | +5V | | +5 volts ±5% power supply |
| 85 (C25) | GNT2* | T/S | Grant 2 – Refer to Pin 25 for more information. |
| 86 (C26) | GND | | Digital Ground |
| 87 (C27) | CLK3 | In | PCI clock 3 – Refer to Pin 27 for more information. |
| 88 (C28) | +5V | | +5 volts ±5% power supply |
| 89 (C29) | INTB* | O/D | Interrupt B – This signal is used to request interrupts only for multi-function devices. |
| 90 (C30) | GNT3* | T/S | Grant 3 – Refer to Pin 25 for more information. |
| 91 (D1) | AD00 | T/S | PCI Address and Data Bus Line 0 – Refer to Pin 3 for more information. |
| 92 (D2) | +5V | | +5 volts ±5% power supply |
| 93 (D3) | AD03 | T/S | PCI Address and Data Bus Lines 3 – Refer to Pin 3 for more information. |
| 94 (D4) | AD06 | T/S | PCI Address and Data Bus Lines 6 – Refer to Pin 3 for more information. |
| 95 (D5) | GND | | Digital Ground |
| 96 (D6) | NC | | Not connected (M66EN - 66MHz device enable) |
| 97 (D7) | AD12 | T/S | PCI Address and Data Bus Line 12 – Refer to Pin 3 for more information. |
| 98 (D8) | +3.3V | | +3.3 volts ±5% power supply |
| 99 (D9) | PAR | T/S | PCI bus Parity bit – This signal is the even parity bit on AD[31:0] and C/BE[3:0]* |
| 100 (D10) | NC | | Not connected (SDONE - Snoop Done) |
| 101 (D11) | GND | | Digital Ground |
| 102 (D12) | DEVSEL * | S/T/S | Device Select – This signal is driven by the target device when its address is decoded. |
| 103 (D13) | +3.3V | | +3.3 volts ±5% power supply |
| 104 (D14) | C/BE2* | | PCI Bus Command/Byte Enable 2 – Refer to Pin 4 for more information. |
| 105 (D15) | GND | | Digital Ground |
| 106 (D16) | AD19 | T/S | PCI Address and Data Bus Line 19 – Refer to Pin 3 for more information. |
| 107 (D17) | +3.3V | | +3.3 volts ±5% power supply |
| 108 (D18) | IDSEL2 | | Initialization Device Select 2 – Refer to Pin 18 for more information. |
| 109 (D19) | IDSEL3 | | Initialization Device Select 3 – Refer to Pin 18 for more information. |
| 110 (D20) | GND | | Digital Ground |
| 111 (D21) | AD27 | T/S | PCI Address and Data Bus Line 27 – Refer to Pin 3 for more information. |
| 112 (D22) | AD31 | T/S | PCI Address and Data Bus Line 31 – Refer to Pin 3 for more information. |
| 113 (D23) | VI/O | | +5 volts ±5% power supply |
| 114 (D24) | GNT0* | T/S | Grant 0 – Refer to Pin 25 for more information. |
| 115 (D25) | GND | | Digital Ground |
| 116 (D26) | CLK1 | In | PCI clock 1 – Refer to Pin 27 for more information. |
| 117 (D27) | GND | | Digital Ground |
| 118 (D28) | RST* | In | PCI bus reset – This signal is an output signal to reset the entire PCI Bus. This signal will be asserted during system reset. |
| 119 (D29) | INTC* | O/D | Interrupt C – This signal is used to request interrupts only for multi-function devices. |
| 120 (D30) | GND | | Digital Ground |
The Input/Output signals in this table refer to the input/output signals listed in the PCI Local Bus Manual, Revision 2.2, Chapter 2, paragraph 2.1, Signal definitions. The following terms or acronyms are used in this table:
• In – Input is standard input only signal
Out – Totem Pole output is a standard active driver
T/S – Tri-State is a bi-directional input output pin
S/T/S – Sustained Tri-State is an active low tri-state signal driven by one and only one agent at a time
O/D – Open Drain allows multiple devices to share as a wire-OR.
# Mini-PCI Interface (J3)
The Mini-PCI interface uses the standard Mini-PCI, 32-bit, 124-pin (62x2) socket interface. This Mini-PCI socket carries all of the appropriate PCI signals operating at clock speeds up to 33 MHz.
Table 5-2 provides the signals and descriptions for the Mini-PCI bus pin-outs for the 124-pin, 2 rows, odd/ even (A1, B1) connector.
Note: The shaded area denotes power or ground. The signals marked with \* indicate signal inversions.
Table 5-2. Mini-PCI Bus Slot Pin/Signal Definitions (J3)
| Pin # | Signal | Input/Output | Description |
| 1 (A1) | NC | | Not Connected (TIP) |
| 2 (A2) | NC | | Not Connected (Ring) |
| 3 (A3) | NC | | Not Connected (8PMJ_3) |
| 4 (A4) | NC | | Not Connected (8PMJ_1) |
| 5 (A5) | NC | | Not Connected (8PMJ_6) |
| 6 (A6) | NC | | Not Connected (8PMJ_2) |
| 7 (A7) | NC | | Not Connected (8PMJ_7) |
| 8 (A8) | NC | | Not Connected (8PMJ_4) |
| 9 (A9) | NC | | Not Connected (8PMJ_9) |
| 10 (A10) | NC | | Not Connected (8PMJ_5) |
| 11 (A11) | NC | | Not Connected (LED1_CRNP) |
| 12 (A12) | NC | | Not Connected (LED2_YELP) |
| 13 (A13) | NC | | Not Connected (LED1_CRNN) |
| 14 (A14) | NC | | Not Connected (LED1_YELN) |
| 15 (A15) | CHSGND | | Chassis Ground |
| 16 (A16) | NC | | Not Connected (Reserved 1) |
| 17 (A17) | INTB* | O/D | Interrupt B – This signal is used to request an interrupt and only has meaning on a multi-function device. |
| 18 (A18) | 5V_1 | | +5 volt power +/- 5% |
| 19 (A19) | +3.3V_5 | | +3.3 volt power +/- 5% |
| 20 (A20) | INTA* | | Interrupt A – This signal is used to request an interrupt. |
| 21 (A21) | NC | | Not Connected (Reserved 5) |
| 22 (A22) | NC | | Not Connected (Reserved 2) |
| 23 (A23) | GND1 | | Ground |
| 24 (A24) | 3.3VAUX | | +3.3 Volt Auxiliary – This voltage is an optional power source that delivers power to the PCI add-in card for generation of power management events when the main power to the card has been turned off by software. A system or add-in card that does not support PCI bus power management must treat the 3.3Vaux pin as reserved. |
| 25 (A25) | CLK | In | Clock – This signal provides timing for all transactions on the PCI bus and is an input to every PCI device. |
| 26 (A26) | RST* | | Reset – This signal is used to bring PCI-specific registers, sequencers, and signals to a consistent state. Anytime Reset is asserted, all PCI output signals must be driven to the benign state. |
| 27 (A27) | GND2 | | Ground |
| 28 (A28) | +3.3V_1 | | +3.3 volt power +/- 5% |
| 29 (A29) | REQ* | T/S | Request – This is a point-to-point signal and indicates to the arbiter that this agent desires use of the bus. Every master has its own Request, which must be tri-stated, while Reset is asserted. |
| 30 (A30) | GNT* | | Grant – This is a point-to-point signal and indicates to the agent that access to the bus has been granted. Every master has its own GNT, which must be ignored while RST is asserted. |
| 31 (A31) | +3.3V_6 | | +3.3 volt power +/- 5% |
| 32 (A32) | GND3 | | Ground |
| 33 (A33) | AD31 | | Address/Data bus 30 – These signals (AD31 – AD0) are multiplexed on the same PCI connector pins. During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31 – AD0 contain data. |
| 34 (A34) | NC | | Not Connected (PME* – Power Management Event) |
| 35 (A35) | AD29 | | Address/Data bus 29 – Refer to pin-33 (A33) for more information. |
| 36 (A36) | NC | | Not Connected (Reserved 3) |
| 37 (A37) | GND4 | | Ground |
| 38 (A38) | AD30 | | Address/Data bus 30 – Refer to pin-33 (A33) for more information. |
| 39 (A39) | AD27 | | Address/Data bus 27 – Refer to pin-33 (A33) for more information. |
| 40 (A40) | 3.3V_2 | | +3.3 volt power +/- 5% |
| 41 (A41) | AD25 | | Address/Data bus 25 – Refer to pin-33 (A33) for more information. |
| 42 (A42) | AD28 | | Address/Data bus 28 – Refer to pin-33 (A33) for more information. |
| 43 (A43) | NC | | Not Connected (Reserved 6) |
| 44 (A44) | AD26 | | Address/Data bus 26 – Refer to pin-33 (A33) for more information. |
| 45 (A45) | C/BE[3]* | T/S | Command/Byte Enable 3 – These signals (C/BE 0-3) are line multiplexed, so that during the address cycle, the command is defined and during the data cycle, the byte enable is defined. |
| 46 (A46) | AD24 | | Address/Data bus 24 – Refer to pin-33 (A33) for more information. |
| 47 (A47) | AD23 | | Address/Data bus 23 – Refer to pin-33 (A33) for more information. |
| 48 (A48) | IDSEL | | Initialization Device Select – This signal is used as a chip select during configuration read and write transactions. |
| 49 (A49) | GND5 | | Ground |
| 50 (A50) | GND6 | | Ground |
| 51 (A51) | AD21 | | Address/Data bus 21 – Refer to pin-33 (A33) for more information. |
| 52 (A52) | AD22 | | Address/Data bus 22 – Refer to pin-33 (A33) for more information. |
| 53 (A53) | AD19 | | Address/Data bus 19 – Refer to pin-33 (A33) for more information. |
| 54 (A54) | AD20 | | Address/Data bus 20 – Refer to pin-33 (A33) for more information. |
| 55 (A55) | GND7 | | Ground |
| 56 (A56) | PAR | T/S | Bus Parity bit – This signal is the even parity bit on AD[31:0] and C/BE[3:0]* |
| 57 (A57) | AD17 | | Address/Data bus 17 – Refer to pin-33 (A33) for more information. |
| 58 (A58) | AD18 | | Address/Data bus 18 – Refer to pin-33 (A33) for more information. |
| 59 (A59) | C/BE[2]* | | Command/Byte Enable 2 – Refer to Pin-45 (A45) for more information. |
| 60 (A60) | AD16 | | Address/Data bus 16 – Refer to pin-33 (A33) for more information. |
| 61 (A61) | IRDY* | S/T/S | Initiator Ready – This signal indicates the master’s ability to complete the current data cycle of the transaction. |
| 62 (A62) | GND8 | | Ground |
| 63 (B1) | 3.3V_7 | | +3.3 volt power +/- 5% |
| 64 (B2) | FRAME* | S/T/S | Frame access – This signal is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle. |
| 65 (B3) | CLKRUN* | | Clock Run |
| 66 (B4) | TRDY* | S/T/S | Target Ready – This signal indicates the selected device’s ability to complete the current cycle of transaction. Both IRDY* and TRDY* must be asserted to terminate a data cycle. |
| 67 (B5) | SERR* | O/D | System Error – This signal is for reporting address parity errors. |
| 68 (B6) | STOP* | S/T/S | Stop – This signal is driven by the current PCI target requesting the master stop the current transaction. |
| 69 (B7) | GND9 | | Ground |
| 70 (B8) | 3.3V_3 | | +3.3 volt power +/- 5% |
| 71 (B9) | PERR* | | Parity Error – This signal is driven by the PCI target during a write to indicate a data parity error has been detected. |
| 72 (B10) | DEVSEL* | S/T/S | Device Select – This signal is driven by the target device when its address is decoded. |
| 73 (B11) | C/BE[1]* | | Command/Byte Enable 1 – Refer to Pin-45 (A45) for more information. |
| 74 (B12) | GND10 | | Ground |
| 75 (B13) | AD14 | | Address/Data bus 14 – Refer to pin-33 (A33) for more information. |
| 76 (B14) | AD15 | | Address/Data bus 15 – Refer to pin-33 (A33) for more information. |
| 77 (B15) | GND11 | | Ground |
| 78 (B16) | AD13 | | Address/Data bus 13 – Refer to pin-33 (A33) for more information. |
| 79 (B17) | AD12 | | Address/Data bus 12 – Refer to pin-33 (A33) for more information. |
| 80 (B18) | AD11 | | Address/Data bus 11 – Refer to pin-33 (A33) for more information. |
| 81 (B19) | AD10 | | Address/Data bus 10 – Refer to pin-33 (A33) for more information. |
| 82 (B20) | GND12 | | Ground |
| 83 (B21) | GND13 | | Ground |
| 84 (B22) | AD9 | | Address/Data bus 9 – Refer to pin-33 (A33) for more information. |
| 85 (B23) | AD8 | | Address/Data bus 8 – Refer to pin-33 (A33) for more information. |
| 86 (B24) | C/BE[0]* | | Command/Byte Enable 0 – Refer to Pin-45 (A45) for more information. |
| 87 (B25) | AD7 | | Address/Data bus 7 – Refer to pin-33 (A33) for more information. |
| 88 (B26) | 3.3V_4 | | +3.3 volt power +/- 5% |
| 89 (B27) | 3.3V_8 | | +3.3 volt power +/- 5% |
| 90 (B28) | AD6 | | Address/Data bus 6 – Refer to pin-33 (A33) for more information. |
| 91 (B29) | AD5 | | Address/Data bus 5 – Refer to pin-33 (A33) for more information. |
| 92 (B30) | AD4 | | Address/Data bus 4 – Refer to pin-33 (A33) for more information. |
| 93 (B31) | NC | | Not Connected (Reserved 7) |
| 94 (B32) | AD2 | | Address/Data bus 2 – Refer to pin-33 (A33) for more information. |
| 95 (B33) | AD3 | | Address/Data bus 3 – Refer to pin-33 (A33) for more information. |
| 96 (B34) | AD0 | | Address/Data bus 0 – Refer to pin-33 (A33) for more information. |
| 97 (B35) | 5V_2 | | +5 volt power +/- 5% |
| 98 (B36) | NC | | Not Connected (RSV_WIP1) |
| 99 (B37) | AD1 | | Address/Data bus 29 – Refer to pin-33 (A33) for more information. |
| 100 (B38) | NC | | Not Connected (RSV_WIP2) |
| 101 (B39) | GND14 | | Ground |
| 102 (B40) | GND15 | | Ground |
| 103 (B41) | NC | | Not Connected (AC_SYNC) |
| 104 (B42) | M66EN | | Tied to ground |
| 105(B43) | NC | | Not Connected (AC_SDATA_IN) |
| 106(B44) | NC | | Not Connected (AC_SDATA_OUT) |
| 107(B45) | NC | | Not Connected (AC_BIT_CLK) |
| 108(B46) | NC | | Not Connected (AC_CODEC_ID0#) |
| 109(B47) | NC | | Not Connected (AC_CODEC_ID1#) |
| 111(B49) | NC | | Not Connected (MOD_AUDIO_MON) |
| 112(B50) | NC | | Not Connected (Reserved 4) |
| 113(B51) | NC | | Not Connected (AUDIO_GND) |
| 114(B52) | GND16 | | Ground |
| 115(B53) | NC | | Not Connected (SYS_AUDIO_OUT) |
| 116(B54) | NC | | Not Connected (SYS_AUDIO_IN) |
| 117(B55) | NC | | Not Connected (SYS_AUDIO_OUT_GND) |
| 118(B56) | NC | | Not Connected (SYS_AUDIO_IN_GND) |
| 119(B57) | NC | | Not Connected (AUDIO_GND2) |
| 120(B58) | NC | | Not Connected (AUDIO_GND1) |
| 121(B59) | NC | | Not Connected (RESERVED8) |
| 122(B60) | NC | | Not Connected (MPVISCT#) |
| 123(B61) | NC | | Not Connected (VCC5VA) |
| 124(B62) | 3.3AUX2 | | +3.3 Volt Auxiliary – Refer to pin-24 (A24) for more information. |
The Input/Output signals in this table refer to the input/output signals listed in the PCI Local Bus Manual, Revision 2.2, Chapter 2, paragraph 2.1, Signal definitions. The following terms or acronyms are used in this table:
In – Input is standard input only signal
Out – Totem Pole output is a standard active driver
T/S – Tri-State is a bi-directional input output pin
S/T/S – Sustained Tri-State is an active low tri-state signal driven by one and only one agent at a time
O/D – Open Drain allows multiple devices to share as a wire-OR.
# PC/104 Bus Interface (J2A,B,C,D)
The PC/104 Bus uses a 104-pin header interface. This interface header will carry all of the appropriate PC/ 104 signals operating at clock speeds up to 8 MHz. The interface header is located on both the top and bottom of the module.
Table 5-3. PC/104 Bus Interface Pin/Signal Descriptions (J2A)
| Pin # | Signal | Description (P1 Row A) |
| 1 (A1) | IOCHCHK* | I/O Channel Check – This signal may be activated by ISA boards to request that a non-maskable interrupt (NMI) be generated to the system processor. It is driven active to indicate an uncorrectable error has been detected. |
| 2 (A2) | SD7 | System Data 7 – This signal (0 to 19) provides a system data bit. |
| 3 (A3) | SD6 | System Data 6 – Refer to SD7, pin-A2, for more information. |
| 4 (A4) | SD5 | System Data 5 – Refer to SD7, pin-A2, for more information. |
| 5 (A5) | SD4 | System Data 4 – Refer to SD7, pin-A2, for more information. |
| 6 (A6) | SD3 | System Data 3 – Refer to SD7, pin-A2, for more information. |
| 7 (A7) | SD2 | System Data 2 – Refer to SD7, pin-A2, for more information. |
| 8 (A8) | SD1 | System Data 1 – Refer to SD7, pin-A2, for more information. |
| 9 (A9) | SD0 | System Data 0 – Refer to SD7, pin-A2, for more information. |
| 10 (A10) | IOCHRDY | I/O Channel Ready – This signal allows slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signal’s normal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read, or write command. The signal is released high when the device is ready to complete the cycle. |
| 11 (A11) | AEN | Address Enable – This signal is used to degate the system processor and other devices from the bus during DMA transfers. When this signal is active, the system DMA controller has control of the address, data, and read/write signals. This signal should be included as part of ISA board select decodes to prevent incorrect board selects during DMA cycles. |
| 12 (A12) | SA19 | System Address 19 – This signal (0 to 19) provides a system address bit. |
| 13 (A13) | SA18 | System Address 18 – Refer to SA19, pin-A12, for more information. |
| 14 (A14) | SA17 | System Address 17 – Refer to SA19, pin-A12, for more information. |
| 15 (A15) | SA16 | System Address 16 – Refer to SA19, pin-A12, for more information. |
| 16 (A16) | SA15 | System Address 15 – Refer to SA19, pin-A12, for more information. |
| 17 (A17) | SA14 | System Address 14 – Refer to SA19, pin-A12, for more information. |
| 18 (A18) | SA13 | System Address 13 – Refer to SA19, pin-A12, for more information. |
| 19 (A19) | SA12 | System Address 12– Refer to SA19, pin-A12, for more information. |
| 20 (A20) | SA11 | System Address 11 – Refer to SA19, pin-A12, for more information. |
| 21 (A21) | SA10 | System Address 10 – Refer to SA19, pin-A12, for more information. |
| 22 (A22) | SA9 | System Address 9 – Refer to SA19, pin-A12, for more information. |
Table 5-3. PC/104 Bus Interface Pin/Signal Descriptions (J2A)
| Pin # | Signal | Description (J2 Row B) |
| 33 (B1) | GND | Ground |
| 34 (B2) | RESETDRV | Reset Drive – This signal is used to reset or initialize system logic on power up or subsequent system reset. |
| 35 (B3) | +5V | +5 volt power ±10% |
| 36 (B4) | IRQ9 | Interrupt request 9 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 37 (B5) | NC | Not Connected (-5 volts) |
| 38 (B6) | DRQ2 | DMA Request 2 – Used by I/O resources to request DMA service, or to request ownership of the bus as a bus master device. Must be held high until associated DACK2 line is active. |
| 39 (B7) | NC | Not Connected (-12 volts) |
| 40 (B8) | SRDY** | Zero Wait State – This signal is driven low by a bus slave device to indicate it is capable of performing a bus cycle without inserting any additional wait states. To perform a 16-bit memory cycle without wait states, this signal is derived from an address decode. |
| 41 (B9) | +12V | +12 Volts |
| 42 (B10) | NC/Key | Not Connected/Key Plug |
| 43 (B11) | SMEMW* | System Memory Write – This signal is used by bus owner to request a memory device to store data currently on the data bus and only active for the lower 1MB. Used for legacy compatibility with 8-bit cards. |
| 44 (B12) | SMEMR* | System Memory Read – This signal is used by bus owner to request a memory device to drive data onto the data bus and only active for lower 1MB. Used for legacy compatibility with 8-bit cards. |
| 45 (B13) | IOW* | I/O Write – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to capture the write data on the data bus. |
| 46 (B14) | IOR* | I/O Read – This strobe signal is driven by the owner of the bus (ISA bus master or DMA controller) and instructs the selected I/O device to drive read data onto the data bus. |
| 47 (B15) | DACK3* | DMA Acknowledge 3 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 48 (B16) | DRQ3 | DMA Request 3 – Used by I/O resources to request DMA service. Must be held high until associated DACK3 line is active. |
| 49 (B17) | DACK1* | DMA Acknowledge 1 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 50 (B18) | DRQ1 | DMA Request 1 – Used by I/O resources to request DMA service. Must be held high until associated DACK1 line is active. |
| 51 (B19) | REFRESH* | Memory Refresh – This signal is driven low to indicate a memory refresh cycle is in progress. Memory is refreshed every 15.6 usec. |
| 52 (B20) | BCLK | System Clock – This is a free running clock typically in the 8MHz to 10MHz range, although its exact frequency is not guaranteed. |
| 53 (B21) | IRQ7 | Interrupt Request 7 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 54 (B22) | IRQ6 | Interrupt Request 6 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 55 (B23) | IRQ5 | Interrupt Request 5 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 56 (B24) | IRQ4 | Interrupt Request 4 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 57 (B25) | IRQ3 | Interrupt Request 3 – Asserted by a device when it has pending interrupt request. Only one device may use the request line at a time. |
| 58 (B26) | DACK2* | DMA Acknowledge 2 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 59 (B27) | TC | Terminal Count – This signal is a pulse to indicate a terminal count has been reached on a DMA channel operation. |
| 60 (B28) | BALE | Buffered Address Latch Enable – This signal is used to latch the LA23 to LA17 signals or decodes of these signals. Addresses are latched on the falling edge of BALE. It is forced high during DMA cycles. When used with AENx, it indicates a valid processor or DMA address. |
| 61 (B29) | +5V | +5 volt power ±10% |
| 62 (B30) | OSC | Oscillator – This clock signal operates at 14.3MHz. This signal is not synchronous with the system clock (SYSCLK). |
| 63 (B31) | GND | Ground |
| 64 (B32) | GND | Ground |
Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 5-5. PC/104 Bus Interface Pin/Signal Descriptions (J2C)
| Pin # | Signal | Description (J2 Row C) |
| 1 (C0) | GND | Ground |
| 2 (C1) | SBHE* | System Byte High Enable – This signal is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8). |
| 3 (C2) | LA23 | Latchable Address 23 – This signal must be latched by the resource if the line is required for the entire data cycle. |
| 4 (C3) | LA22 | Latchable Address 22 – Refer to LA23, pin-C2, for more information. |
| 5 (C4) | LA21 | Latchable Address 21 – Refer to LA23, pin-C2, for more information. |
| 6 (C5) | LA20 | Latchable Address 20 – Refer to LA23, pin-C2, for more information. |
| 7 (C6) | LA19 | Latchable Address 19 – Refer to LA23, pin-C2, for more information. |
| 8 (C7) | LA18 | Latchable Address 18 – Refer to LA23, pin-C2, for more information. |
| 9 (C8) | LA17 | Latchable Address 17 – Refer to LA23, pin-C2, for more information. |
| 10 (C9) | MEMR* | Memory Read – This signal instructs a selected memory device to drive data onto the data bus. It is active on all memory read cycles. |
| 11 (C10) | MEMW* | Memory Write – This signal instructs a selected memory device to store data currently on the data bus. It is active on all memory write cycles. |
| 12 (C11) | SD8 | System Data 8 – Refer to SD7, pin-A2, for more information. |
| 13 (C12) | SD9 | System Data 9 – Refer to SD7, pin-A2, for more information. |
| 14 (C13) | SD10 | System Data 10 – Refer to SD7, pin-A2, for more information. |
| 15 (C14) | SD11 | System Data 11 – Refer to SD7, pin-A2, for more information. |
| 16 (C15) | SD12 | System Data 12 – Refer to SD7, pin-A2, for more information. |
| 17 (C16) | SD13 | System Data 13 – Refer to SD7, pin-A2, for more information. |
| 18 (C17) | SD14 | System Data 14 – Refer to SD7, pin-A2, for more information. |
| 19 (C18) | SD15 | System Data 15 – Refer to SD7, pin-A2, for more information. |
| 20 (C19) | NC/Key | Not Connected/Key Plug |
Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 5-6. PC/104 Bus Interface Pin/Signal Descriptions (J2D)
| Pin # | Signal | Description (J2 Row D) |
| 21 (D0) | GND | Ground |
| 22 (D1) | MEMCS16* | Memory Chip Select 16 – This signal is driven low by a memory slave device to indicate it is capable of performing a 16-bit memory data transfer. This signal is driven from a decode of the LA23 to LA17 address lines. |
| 23 (D2) | IOCS16* | I/O Chip Select 16 – This signal is driven low by an I/O slave device to indicate it is capable of performing a 16-bit I/O data transfer. This signal is driven from a decode of the SA15 to SA0 address lines. |
| 24 (D3) | IRQ10 | Interrupt Request 10 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 25 (D4) | IRQ11 | Interrupt Request 11 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 26 (D5) | IRQ12 | Interrupt Request 12 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 27 (D6) | IRQ15 | Interrupt Request 15 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 28 (D7) | IRQ14 | Interrupt Request 14 – Asserted by a device when it has pending interrupt request. Only one device at a time may use the request line. |
| 29 (D8) | DACK0* | DMA Acknowledge 0 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 30 (D9) | DRQ0 | DMA Request 0 – Used by I/O resources to request DMA service. Must be held high until associated DACK0 line is active. |
| 31 (D10) | DACK5* | DMA Acknowledge 5 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 32 (D11) | DRQ5 | DMA Request 5 – Used by I/O resources to request DMA service. Must be held high until associated DACK5 line is active. |
| 33 (D12) | DACK6* | DMA Acknowledge 6 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 34 (D13) | DRQ6 | DMA Request 6 – Used by I/O resources to request DMA service. Must be held high until associated DACK6 line is active. |
| 35 (D14) | DACK7* | DMA Acknowledge 7 – Used by DMA controller to select the I/O resource requesting the bus, or to request ownership of the bus as a bus master device. Can also be used by the ISA bus master to gain control of the bus from the DMA controller. |
| 36 (D15) | DRQ7 | DMA Request 7 – Used by I/O resources to request DMA service. Must be held high until associated DACK7 line is active. |
| 37 (D16) | +5V | +5 volt power ±10% |
| 38 (D17) | MASTER* | Bus Master Assert – This signal is used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a device can pull -MASTER low which will allow it to control the system address, data, and control lines. After -MASTER is low, the device should wait one CLK period before driving the address and data lines, and two clock periods before issuing a read or write command. |
| 39 (D18) | GND | Ground |
| 40 (D19) | GND | Ground |
Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 5-7. IDE Interface Pin/Signal Descriptions (J4)
| Pin # | Signal | Description |
| 1 | RESET* | Reset – Low active hardware reset (RSTDRV inverted) |
| 2 | GND | Digital Ground |
| 3 | DD7 | Disk Data 7 – These signals (0 to 15) provide the disk data signals. |
| 4 | DD8 | Disk Data 8 – These signals (0 to 15) provide the disk data signals. |
| 5 | DD6 | Disk Data 6 – These signals (0 to 15) provide the disk data signals. |
| 6 | DD9 | Disk Data 9 – These signals (0 to 15) provide the disk data signals. |
| 7 | DD5 | Disk Data 5 – These signals (0 to 15) provide the disk data signals. |
| 8 | DD10 | Disk Data 10 – These signals (0 to 15) provide the disk data signals. |
| 9 | DD4 | Disk Data 4 – These signals (0 to 15) provide the disk data signals. |
| 10 | DD11 | Disk Data 11 – These signals (0 to 15) provide the disk data signals. |
| 11 | DD3 | Disk Data 3 – These signals (0 to 15) provide the disk data signals. |
| 12 | DD12 | Disk Data 12 – These signals (0 to 15) provide the disk data signals. |
| 13 | DD2 | Disk Data 2 – These signals (0 to 15) provide the disk data signals. |
| 14 | DD13 | Disk Data 13 – These signals (0 to 15) provide the disk data signals. |
| 15 | DD1 | Disk Data 1 – These signals (0 to 15) provide the disk data signals. |
| 16 | DD14 | Disk Data 14 – These signals (0 to 15) provide the disk data signals. |
| 17 | DD0 | Disk Data 0 – These signals (0 to 15) provide the disk data signals. |
| 18 | DD15 | Disk Data 15 – These signals (0 to 15) provide the disk data signals. |
| 19 | GND | Digital Ground |
| 20 | NC-Key | Not Connected - Key pin plug |
| 21 | DDREQ | Device DMA Channel Request – Used for DMA transfers between host and drive (direction of transfer controlled by DIOR* and DIOW*). Also used in an asynchronous mode with DMACK*. Drive asserts IDRQ0 when ready to transfer or receive data. |
| 22 | GND | Digital Ground |
| 23 | DIOW* | Device I/O Read/Write Strobe – Strobe signal for write functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 24 | GND | Digital Ground |
| 25 | DIOR* | I/O Read/Write Strobe – Strobe signal for read functions. Negative edge enables data from a register or data port of the drive onto the host data bus. Positive edge latches data at the host. |
| 26 | GND | Digital Ground |
| 27 | DIORDY | I/O Channel Ready – When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 28 | DCSEL | Cable Select – Used to configure IDE drives as device 0 or device 1 using a special cable. |
| 29 | DDACK* | DMA Channel Acknowledge – Used by the host to acknowledge data has been accepted or data is available. Used in response to DMARQ asserted. |
| 30 | GND | Digital Ground |
| 31 | IRQ14 | Interrupt Request 14 – Asserted by drive when it has pending interrupt (PIO transfer of data to or from the drive to the host). |
| 32 | NC | Not connected (IOCS16*) |
| 33 | DA1 | IDE ATA Disk Address (0 to 2). Used to indicate which byte in the ATA command block or control block is being accessed. |
| 34 | D33/66 | UDMA 33/66 Sense – Senses which DMA mode to use for IDE devices. |
| 35 | DA0 | IDE ATA Disk Address (0 to 2). Used to indicate which byte in the ATA command block or control block is being accessed. |
| 36 | DA2 | IDE ATA Disk Address (0 to 2). Used to indicate which byte in the ATA command block or control block is being accessed. |
| 37 | DCS1* | Slave/Master Chip Select 1 – Used to select the host-accessible Command Block Register. |
| 38 | DCS3* | Slave/Master Chip Select 3 – Used to select the host-accessible Command Block Register. |
| 39 | IDE LED1 | IDE Activity – Indicates IDE drive activity to yellow IDE LED (D4) on card edge. |
| 40 | GND | Digital Ground |
| 41 | +5V | +5 volt power ±10% |
| 42 | +5V | +5 volt power ±10% |
| 43 | GND | Digital Ground |
| 44 | NC | Not connected |
# Compact Flash Socket (J6)
The board provides a Type I or II Compact Flash card socket, which allows for the insertion of a Compact Flash card. The Compact Flash card acts as a standard IDE Drive and is connected to the Secondary IDE bus. If a Compact Flash card is installed, it is the only device using the secondary IDE bus. Jumpers are used to select the Master/Slave mode and voltage of the Compact Flash card. Refer to Table 4-3, Jumper Settings, for more information.
Note: The shaded area denotes power or ground. The signals marked with \* = Negative true logic.
Table 5-8. Compact Flash Interface Pin/Signal Descriptions (J6)
| Pin # | Signal | Description |
| 1 | GND | Digital Ground |
| 2 | DD3 | Disk Data 3 –These signals (D0-D15) carry the Data, Commands, and Status between the host and the controller. D0 is the LSB of the even Byte of the Word. D8 is the LSB of the Odd Byte of the Word. All Task File operations occur in byte mode on the low order bus D0-D7, while all data transfers are 16 bit using D0-D15 to provide the disk data signals. |
| 3 | DD4 | Disk Data 4 – Refer to SDD3 on pin-2 for more information. |
| 4 | DD5 | Disk Data 5 – Refer to SDD3 on pin-2 for more information. |
| 5 | DD6 | Disk Data 6 – Refer to SDD3 on pin-2 for more information. |
| 6 | DD7 | Disk Data 7 – Refer to SDD3 on pin-2 for more information. |
| 7 | DCS1* | Chip Select 1 – This signal, along with CE2*, is used to select the card and indicate to the card when a byte or word operation is being performed. This signal accesses the even byte or odd byte of the word depending on A0 and CE2*. |
| 8, 10 | NC | Not connected |
| 9 | GND | Digital Ground |
| 11, 12 | NC | Not connected |
| 13 | VCC | +5 volts +/-5% |
| 14, 15 | NC | Not connected |
| 16, 17 | NC | Not connected |
| 17 | NC | Not connected |
| 18 | DA2 | Address select 2 – One of three signals (0 – 2) used to select one of eight registers in the Task File. The host grounds all remaining address lines. |
| 19 | DA1 | Address select 1 – Refer to A2 on pin-18 for more information. |
| 20 | DA0 | Address select 0 – Refer to A2 on pin-18 for more information. |
| 21 | DD0 | Disk Data 0 – Refer to SDD3 on pin-2 for more information. |
| 22 | DD1 | Disk Data 1 – Refer to SDD3 on pin-2 for more information. |
| 23 | DD2 | Disk Data 2 – Refer to SDD3 on pin-2 for more information. |
| 24 | NC | Not connected (IOCS16*) |
| 25 | CFD2 | Connected through 4.7k ohm resistor to ground |
| 26 | CFD1 | Connected through 4.7k ohm resistor to ground |
| 27 | DD11 | Disk Data 11 – Refer to SDD3 on pin-2 for more information. |
| 28 | DD12 | Disk Data 12 – Refer to SDD3 on pin-2 for more information. |
| 29 | DD13 | Disk Data 13 – Refer to SDD3 on pin-2 for more information. |
| 30 | DD14 | Disk Data 14 – Refer to SDD3 on pin-2 for more information. |
| 31 | DD15 | Disk Data 15 – Refer to SDD3 on pin-2 for more information. |
| 32 | DCS3* | Slave/Master Chip Select – This signal, along with CE1*, is used to select the Compact Flash card and indicate to the card when a byte or word operation is being performed. This signal always accesses the odd byte of word. |
| 33 | NC | Not Connected (VS1*) |
| 34 | DIOR* | Device I/O Read/Write Strobe – This signal is generated by the host and gates the I/O data onto the bus from the Compact Flash card when the card is configured to use the I/O interface. |
| 35 | DIOW* | Device I/O Read/Write Strobe – This signal is generated by the host and clocks the I/O data on the Card Data bus into the Compact Flash card controller registers when the card is configured to use the I/O interface. The clock occurs on the negative to positive edge of the signal (trailing edge). |
| 36 | VCC | +5 volts +/-5% |
| 37 | IRQ15 | Interrupt Request 15 – IRQ 15 is asserted by drive (CF) when it has a pending interrupt (PIO transfer of data to or from the drive to the host). |
| 38 | VCC | +5 volts +/-5% |
| 39 | MASTER * | Master/Slave – This signal is determined by jumper JP3 and is used to configure this device as a Master or a Slave. When this pin is grounded (jumper inserted), this device is configured as Master. When this pin is open (jumper removed), this device is configured as Slave (Default). |
| 40 | NC | Not Connected (VS2*) |
| 41 | RSTIDE* | IDE Reset – This input signal is the active low hardware reset from the host. If this pin goes high, it is used as the reset signal. This pin is driven high at power-up, causing a reset, and if left high will cause another reset. |
| 42 | DIORDY | Device I/O-DMA Channel Ready – When negated, extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request. High impedance if asserted. |
| 43 | NC | Not Connected (InpAck) |
| 44 | VCC | +5 volts +/-5% |
| 45 | IDE LED2 | IDE Activity – Indicates CF activity to yellow IDE LED (D4) oncard edge. |
| 46 | SD33-66 | SD33/66 Sense – Senses which DMA mode to use for the Compact Flash card. |
| 47 | DD8 | Disk Data 8 – Refer to SDD3 on pin-2 for more information. |
| 48 | DD9 | Disk Data 9 – Refer to SDD3 on pin-2 for more information. |
| 49 | DD10 | Disk Data 10 – Refer to SDD3 on pin-2 for more information. |
| 50 | GND | Digital Ground |
# Auxiliary Power Interface (J5)
The MiniModule draws its power from the PC/104-Plus bus connector and requires +3.3 and +5 volt input power. If +12V power is required, it is provided by the Auxiliary Power connector (J5). The Auxiliary power connector uses a 10-pin header with 0.100" spacing. Though not recommended for use when the target board is powered directly, the Auxiliary Power connector (J5) supplies the following voltage directly to the module for external use:
Table 5-9 gives the signals for Power supply pin outs, and Table 5-10 provides the pin arrangement.
Table 5-9. Auxiliary Power Interface Pins/Signals Descriptions (J5)