# NuDAQ®

# ACL-7120A

Digital I/O & Timer/Counter Card

User’s Guide

Copyright 1995, 2003 ADLINK TECHNOLOGY INC.

All Rights Reserved.

Manual Rev. 1.00: May 30, 2003

Part No: 50-11031-100

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

NuDAQ, ACL-7120A is registered trademarks of ADLINK TECHNOLOGY INC.

Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you need any help or service, please contact us.

<table><tr><td colspan="4">ADLINK TECHNOLOGY INC.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">Service@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan</td></tr></table>

Please email or FAX your detailed information for prompt, satisfactory, and consistent service.

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# Table of Contents

# Chapter 1 Introduction .........

1.1 Features ..... 2
1.2 Applications ..... . 2
1.3 Specifications .... 3
1.4 Software Support.. 5

1.4.1 ACLS-DLL1... 5

1.4.2 ACLS-LVIEW . .5

# Chapter 2 Installation ......

2.1 What’s Included.. 7
2.2 Unpacking ... 8
2.3 ACL-7120A Layout.. 9
2.4 Jumper and DIP Switch Description.... .. 10
2.5 Base Address Setting..... . 11
2.6 Interrupt Settings .. . 13
2.7 Clock Frequency Settings . .. 15
2.8 ACL-7120A Software Library Installation .. . 16

# Chapter 3 Signal Connections.......... ..... 17

3.1 Connector Pin Assignment... .. 17
3.2 Timer/counter signal pads... . 21
3.3 Interrupt Trigger Source .. . 22
3.4 Clock Source Pads.. . 23
3.5 Latch Digital Inputs..... .. 24

# Chapter 4 Programming............ .... 25

4.1 I/O Registers Format .. . 25
4.2 Digital I/O Programming . .. 26
4.3 Programmable Interval Timer... . 28

4.3.1 The Intel (NEC) 8254 .. ..28
4.3.2 The Control Byte .. .28
4.3.3 Mode definition.. .30

# Warranty Policy ........ . 33

# How to Use This Guide

This manual is designed to assist users in understanding the ACL-7120A and describes how to modify settings to meet specific application requirements.

# Chapter 1 Introduction

Overview of product features, applications, and specifications.

# Chapter 2 Installation

Describes install procedures, layout, DIP switch settings, and jumper settings.

# Chapter 3 Signal Connection

Illustrates the connector pin assignments, timer/counter signal pad, and clock source.

# Chapter 4 Programming

Demonstrates how to program the ACL-7120A.

![1](.acl-7120a-6-manual-3/51f477ace719da97153e03ba5a34cd04d6c281224e3c9c1e911c6b1368877a92.jpg)

# Introduction

The ACL-7120A digital I/O and counter/timer card consists of 32 digital input, 32 digital output, and 4 timer/counter channels. All digital input/output channels are TTL/DTL compatible. The most outstanding feature of the ACL-7120A is that it is fully hardware and software compatible with both the ADLINK ACL-7120 and Advantech PCL-720 cards.

The ACL-7120A supports additional daughter boards like the ACLD-9182 and ACLD-9185 cards. The ACLD-9182 is a 16 channel opto-isolated digital board for inputting digital data to the ACL-7120A when ground isolation is required. The ACLD-9185 is a 16-channel relay output board that can be driven by digital outputs from the ACL-7120A.

Up to four programmable interval timers (8254) are provided to add timer and counter functionalities. To efficiently use the counter, three frequency sources (10kHz, 100kHz, and 1MHz) are supported for the input of each counter. In addition, the sources can also be doubled (X2), halved (1/2) or quartered (1/4) through jumper settings to give more flexibility for different frequency timer and counter applications.

An optional timer/counter chip is used to support a timer pacer that can generate periodic interrupts. Also, an event counter can be used for external event counting.

# 1.1 Features

• Fully compatible with ADLINK ACL-7120 and Advantech PCL-720
• 32 TTL digital input channels
• 32 TTL digital output channels
• High output driving and low input loading
• 3 independent programmable 16-bit down counter
• One 32-bit timer (two 16-bit counter cascaded together) with a 4MHz time base
• One 16-bit counter with 4MHz time base
• Crystal-based frequency source
• Breadboard area for customized circuits

# 1.2 Applications

• Industrial and laboratory ON/OFF control
• Energy management
• Annunciation
• Security controller
• Product test
• Period and pulse width measurement
• Event and frequency counting
• Waveform and pulse generation
• BCD interface driver

# 1.3 Specifications

♦ General Specification:

• Dimensions: 193.5 mm x 114 mm
• Bus: PC-AT bus
• I/O port address: Hex 200 - Hex 3FF
• Interrupt IRQ Level: IRQ3 - IRQ15

Digital Input:

• Input logic low voltage: Min. -0.5V, Max. 0.8V
• Input logic high voltage: Min. 2.0V, Max. 5.0V
• Input loading current: Max. 0.2 mA at 0.4V
• Input hysteresis: Typical 0.4V, Min. 0.2V

Digital Output:

• Output logic low voltage (Sink): Max. 0.5V at 24mA
• Output logic high voltage (Source): Min. 2V at –15mA
Driving Capacity: All inputs and outputs are TTL/DTL compatible. Outputs will drive 1 standard TTL load (74 series) or 4 LSTTL (74LS) loads
• Input hysteresis: Typical 0.4V, Min. 0.2V

♦ Programmable Counter:

• Frequency: 4MHz

• Counter:

<table><tr><td>Device</td><td>Number of counters</td></tr><tr><td>ACL-7120A/3</td><td>3</td></tr><tr><td>ACL-7120A/6</td><td>4</td></tr></table>

• Mode: 6 programmable modes
• Usable pins:

<table><tr><td>Device</td><td>Usable pins</td></tr><tr><td>ACL-7120A/3</td><td>CLK and GATE for counter 0 - counter 2</td></tr><tr><td>ACL-7120A/6</td><td>CLK and GATE for counter 0 - counter 3</td></tr></table>

• counter usage :

<table><tr><td>Device</td><td>Counter usage</td></tr><tr><td>ACL-7120A/3</td><td>Counters 0 - 2 are customizable</td></tr><tr><td>ACL-7120A/6</td><td>Counters 0 - 2 are customizableCounter 3 is used as the event counting interrupt source or is user definedCounters 4 and 5 are cascaded for timer pacer generation</td></tr></table>

• Breadboard Area: plated through hole:

hole size: 1.0 mm

pad size: 1.5 mm

• Operating temperature: 0 to 60°C
• Storage Temperature: -20° C to 80° C
• Humidity: 5 to 90%, non-condensing

# 1.4 Software Support

The ACL-7120A is programmable using simple 8-bit I/O port commands. Users can use high-level languages, such as BASIC, C, or PASCAL, or lowlevel language, such as assembly to program the board. To program under Windows or LabView, please contact an ADLINK dealer for information on the ACLS-DLL1 and ACLD-LVIEW.

# 1.4.1 ACLS-DLL1

The ACLS-DLL1 provides simple ACL-07120A board programming under a Windows 9x/NT/2000 environment using DLLs. With the ACLS-DLL1, users can use compilers such as VB, VC/C++, and Delphi.

# 1.4.2 ACLS-LVIEW

For an easy link between ACL-7120A and LabView, the ACLS-LVIEW includes VIs of the ACL-7120A for use under for Windows 3.1/9x/NT/2000/XP.

# 2

# Installation

This chapter describes how to install the ACL-7120A. Please carefully review the unpacking information before removing the product. The jumper and switch settings for the ACL-7120A base address, clock sources, interrupt IRQ level, and IRQ trigger sources are specified below.

# 2.1 What’s Included

In addition to this User's Manual, the package includes the following items:

♦ ACL-7120A Digital I/O and Timer/Counter Card
♦ ADLINK CD

If any of these items is missing or damaged, contact the dealer the product was purchased. Save the shipping materials and carton to ship or store the product in the future.

# 2.2 Unpacking

Your ACL-7120A card contains sensitive electronic components that can be easily damaged by static electricity.

Prepare a grounded anti-static mat. The operator should be wearing an antistatic wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling may cause damage to the module. Be sure there is no obvious damage due to shipping and handing by examining the shipping box.

After opening the card module carton, extract the system module and place it only on a grounded anti-static surface, component side up.

Again inspecting the module for damage. Press down on all the socketed IC's to make sure they are properly seated. Do this only with the module place on a firm flat surface.

Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

You are now ready to install your ACL-7120A.

# 2.3 ACL-7120A Layout

![CN1\nCN2\nCN3\nCN4\nJP3\nCount 1\nCount 0\nCN5\nJP1\nJP2](.acl-7120a-6-manual-3/3fa79d06dcb53c9ec1e173534db83139eb933840a76adb6095d9dc3572bef354.jpg)

Figure 2.1 7120A Layout

# 2.4 Jumper and DIP Switch Description

The ACL-7120A channels and base addresses can be changed through jumper settings and DIP switches on the card. The ACL-7120A is preconfigured at the factory and should not need to be changed under normal circumstances.

A jumper switch is closed or "shorted" with the plastic cap inserted over two pins of the jumper. A jumper is open when the plastic cap inserted over one or no pin(s) of the jumper.

# 2.5 Base Address Setting

The ACL-7120A requires eight consecutive address locations in the I/O address space. The base address of the ACL-7120A is restricted by the following conditions:

1. The base address must be within the range 200hex to 3FFhex.
2. The base address should not conflict with any PC I/O address.

The ACL-7120A default I/O port base address 0x2A0 is set by the 6 position DIP switch SW1 (refer to Figure 2.2). Possible address settings for I/O ports are from Hex 200 to Hex 3FE and are listed in Table 2.2.

Default Base Address = 0x2A0
![The image displays a diagram of a 6-position toggle switch.\n\n**Text:**\n*   Top: **A ( 9 8 7 6 5 4 )**\n*   Left: **ON**\n*   Bottom: **1 2 3 4 5 6**\n\n**Visuals:**\nInside a rectangular frame, there are six vertical columns. Black squares indicate the switch position in each column:\n*   Column 1: Square at the bottom.\n*   Column 2: Square at the top.\n*   Column 3: Square at the bottom.\n*   Column 4: Square at the top.\n*   Column 5: Square at the bottom.\n*   Column 6: Square at the top.\n\nThe 'ON' label aligns with the top row, indicating that the switches in columns 2, 4, and 6 are in the 'ON' position.](.acl-7120a-6-manual-3/87481b98da78473c55e5b4309ea66a2cdf1860447414c957d4afd9e5ded4b1c3.jpg)
Figure 2.2 Default Base Address Setting

<table><tr><td>I/O port address(hex)</td><td>1A9</td><td>2A8</td><td>3A7</td><td>4A6</td><td>5A5</td><td>6A4</td></tr><tr><td>200-20F</td><td>OFF</td><td>ON</td><td>ON</td><td>ON</td><td>ON</td><td>ON</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>2A0-2AF (*)</td><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td></tr><tr><td>2B0-2BF</td><td>OFF</td><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>3D0-3DF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>3E0-3E0</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>3F0-3FF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr></table>

\* Default setting
A9,...,A4 correspond to PC address lines

Table 2.1

# How to define the base address for the ACL-7120A?

DIP1 through DIP6 in the switch SW1 are one-to-one corresponding to the PC bus address line A8 to A4. A9 is always 1 and A0\~A3 are always 0. If you want to change the base address, you can only change the values of A8 to A4 (the shadowed area of the table below). The following table shows how to define the base address as Hex 2A0

Base Address: Hex 2A0

<table><tr><td colspan="2">2</td><td colspan="4">A</td><td colspan="4">0</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>A9</td><td>A8</td><td>A7</td><td>A6</td><td>A5</td><td>A4</td><td>A3</td><td>A2</td><td>A1</td><td>A0</td></tr></table>

# 2.6 Interrupt Settings

To use the interrupt function, a second counter chip (CNT 1) needs to be installed on the ACL-7120A/3. The additional CNT 1 counter chip is included with the ACL-7120A/6.

The ACL-7120A offers AT bus interrupt levels (IRQ3-IRQ15), and three interrupt trigger sources (timer pacer, event, and external). The IRQ level is set by JP2 and is used to define the interrupt IRQ level. The default setting is IRQ15.

Note : Ensure that the chosen IRQ level does not conflict with existing hardware or system settings.

![JP2\n* \n15\n12\n11\n10\n9\n7\n5\n4\n3](.acl-7120a-6-manual-3/35fe30b76ee1734401065d34f7c166851e14b755b5d5072b59912d0299bca0bf.jpg)

default setting : IRQ15
Figure 2.3

The interrupt trigger source is set by JP3. The default setting is “TME IRQ” and is shown below:

EXT IRQ: External source to trigger interrupt

EVT IRQ: Event counting to trigger interrupt

TME IRQ: Timer Pacer to trigger interrupt

![JP3 *\nEXT IRQ\nEVT IRQ\nTME IRQ](.acl-7120a-6-manual-3/814dcb49b032d3f1b6e55bbf6947a82986d2a845776320e9f6833d14a573638f.jpg)

default setting :TME IRQ

Figure 2.4

# 2.7 Clock Frequency Settings

The ACL-7120A board offers 3 frequency sources: 10kHz, 100kHz, and 1 MHz. These frequencies can be double, half or quartered by placing a jumper on position " X2," "X1/2," or "X1/4," of JP1. The default setting is “X1.”

![* \nJP1\nX2\nX1\nX1/2\nX1/4](.acl-7120a-6-manual-3/4b11b52e9cb6ca6b3f6a94cd6771d9a87f00935f0fdfbc1d848ef320d70c11ec.jpg)

\* : default setting

Figure 2.5

# 2.8 ACL-7120A Software Library Installation

The DOS software library is supplied with the ACL-7120A. Function prototypes and useful constants are defined in the header files in the LIB directory. The DOS library software includes a utility program, C language libraries, and demonstration programs to help reduce the programming work. Please refer to the ACLS-DLL1 function reference manual on ADLINK CD. The DOS functions are compatible with ACLS-DLL1 functions except those without a “W” prefix in function names.

To program in a Windows environment, please use ACLS-DLL1 (separate license required).

To install the DOS library software and utilities, please follow the following installation procedures:

1. Insert the ADLINK CD into the CD-ROM drive.
2. Type the following command in a DOS window to change to the card directory (X indicates the CD-ROM drive):
3. Execute the setup batch program to install the software: X:\NuDAQISA\7120>SETUP.

```batch
X:\>CD \NuDAQISA\7120
```

After installation, all files of the ACL-7120A Library & Utility for DOS are stored in the C:\ADLINK\7120\DOS sub-directory.

# 3

# Signal Connections

# 3.1 Connector Pin Assignment

The ACL-7120A comes equipped with five 20-pin insulation displacement connectors CN1-CN5. CN1 and CN2 are located at the rear plate. CN3, CN4, and CN5 are located on board. Each of these connectors can be connected to flat cables of the same type.

CN1 and CN3 are used for digital outputs, CN2 and CN4 are used for digital inputs, and CN5 is used for the timer/counter. The following diagrams below show the connector pin assignments:

Legend:

<table><tr><td>DO</td><td>Digital Output</td></tr><tr><td>DI</td><td>Digital Input</td></tr><tr><td>GND</td><td>Ground</td></tr><tr><td>CLK</td><td>Clock input for the 8254(8253)</td></tr><tr><td>GATE</td><td>Gate input for the 8254(8253)</td></tr><tr><td>OUT</td><td>Signal output for 8254(8253)</td></tr><tr><td>STROBE</td><td>External signal to latch DI data</td></tr></table>

CN1: Digital OUT (0-15)
![DO 0 —— 1 —— 2 —— DO 1\nDO 2 —— 3 —— 4 —— DO 3\nDO 4 —— 5 —— 6 —— DO 5\nDO 6 —— 7 —— 8 —— DO 7\nDO 8 —— 9 —— 10 —— DO 9\nDO 10 —— 11 —— 12 —— DO 11\nDO 12 —— 13 —— 14 —— DO 13\nDO 14 —— 15 —— 16 —— DO 15\nGND —— 17 —— 18 —— GND\n+5V —— 19 —— 20 —— +12V](.acl-7120a-6-manual-3/f2fc530047be572320d8bcc4dfa00bfacbc00106ee87d38cc847eb435d34e89a.jpg)

CN 2: Digital IN (0-15)

![DI 0\nDI 2\nDI 4\nDI 6\nDI 8\nDI 10\nDI 12\nDI 14\nGND\n+5V\n1 2\n3 4\n5 6\n7 8\n9 10\n11 12\n13 14\n15 16\n17 18\n19 20\nDI 1\nDI 3\nDI 5\nDI 7\nDI 9\nDI 11\nDI 13\nDI 15\nGND\nSTROBE0](.acl-7120a-6-manual-3/af196210a64ff599615fa5671ea11e496b3138839d8f132525334b58af80d70b.jpg)

CN 3: Digital OUT (16 - 31)
![DO 16 —— 1 —— 2\nDO 18 —— 3 —— 4\nDO 20 —— 5 —— 6\nDO 22 —— 7 —— 8\nDO 24 —— 9 —— 10\nDO 26 —— 11 —— 12\nDO 28 —— 13 —— 14\nDO 30 —— 15 —— 16\nGND —— 17 —— 18\n+5V —— 19 —— 20\nDO 17\nDO 19\nDO 21\nDO 23\nDO 25\nDO 27\nDO 29\nDO 31\nGND\n+12V](.acl-7120a-6-manual-3/5509c3d13d5ea2d8c8071644546db86b91d0616474ad183c321fac099f1acd98.jpg)

CN 4: Digital IN (16 - 31)

![DI 16\nDI 18\nDI 20\nDI 22\nDI 24\nDI 26\nDI 28\nDI 30\nGND\n+5V\n1 2\n3 4\n5 6\n7 8\n9 10\n11 12\n13 14\n15 16\n17 18\n19 20\nDI 17\nDI 19\nDI 21\nDI 23\nDI 25\nDI 27\nDI 29\nDI 31\nGND\nSTROBE1](.acl-7120a-6-manual-3/5fa1eae6f91b8baafd0c75a37c1cfc1848252875b599a0a2de67dd1c1296670b.jpg)

CN 5: COUNTER
![CLK 2\nOUT 2\nGATE 2\nEVENT\nGATE 3\nGATE 4\nEXT IRQ\nGND\n+5V\n1 2\n3 4\n5 6\n7 8\n9 10\n11 12\n13 14\n15 16\n17 18\n19 20\nCLK 1\nOUT 1\nGATE 1\nCLK 0\nOUT 0\nGATE 0\nGND](.acl-7120a-6-manual-3/253a5d034c6b23a5df7d76d7a5507d235e1ef069d25a18e03068c05b04aaabb0.jpg)

# 3.2 Timer/counter signal pads

![This block diagram depicts an **8254 Timer/Counter** system. Inside a main rectangular boundary, there are three distinct counter blocks arranged vertically: **Counter 0**, **Counter 1**, and **Counter 2**.\n\nThe connections for each block are as follows:\n\n*   **Counter 0**:\n    *   **CN5 Pin-8** connects to **CLK0**.\n    *   **CN5 Pin-12** connects to **GATE0**.\n    *   **OUT0** connects to **CN5 Pin-10**.\n\n*   **Counter 1**:\n    *   **CN5 Pin-2** connects to **CLK1**.\n    *   **CN5 Pin-6** connects to **GATE1**.\n    *   **OUT1** connects to **CN5 Pin-4**.\n\n*   **Counter 2**:\n    *   **CN5 Pin-1** connects to **CLK2**.\n    *   **CN5 Pin-5** connects to **GATE2**.\n    *   **OUT2** connects to **CN5 Pin-3**.](.acl-7120a-6-manual-3/d07fdc60b026afdac156c38bcaa17ea7050c7566afff3b3da4e64b8c162980e7.jpg)

Figure 3.1

The internal timer/counter 8254 (Counter 0-Counter 2) on the ACL-7120A is configured as above (figure 3.1). Users can utilize the capabilities of the 8254 through CN5.

CN5 also provides additional wiring to fully use the the 8254. Signal solder pads are located on the board for use with applications requiring direct access through these soldering pads (i.e. to circuits on the breadboard area). The signals of these pads are the same as the signals of CN5. The layout of signal pads is shown below.

![CLK0\nGATE0\nOUT0\nCLK1\nGATE1\nOUT1\nCLK2\nGATE2\nOUT2](.acl-7120a-6-manual-3/8a28c774677f359ff957f407ebc26e9b3095cd6d156102e69761d5c5df01b189.jpg)

Figure 3.2

# 3.3 Interrupt Trigger Source

The second interval timer/counter 8254 chip on the ACL-7120A is used to generate sources for interrupts. The block diagram of this chip is illustrated below (figure 3.3).

Counter 3 of the 8254 is used for event counting, it will accept event signals from CN5 pin-7 and its output will trigger an interrupt when the count value of Counter 3 is becomes 0.

Counters 4 and 5 are cascaded together for a timer pacer trigger interrupt. Its clock source is 4Mhz.

Note: The second internal timer/counter 8254 is installed on the ACL-7120A/6 only. Without it, the functions above will not work.

![This diagram illustrates the connections for an **8254 Timer/Counter** integrated circuit.\n\n**Blocks:**\n*   **8254 Timer/Counter**: The main block containing three internal counters.\n    *   **Counter 3**: Contains pins labeled **CLK3**, **GATE3**, and **OUT3**.\n    *   **Counter 4**: Contains pins labeled **CLK4**, **GATE4**, and **OUT4**.\n    *   **Counter 5**: Contains pins labeled **CLK5**, **GATE5**, and **OUT5**.\n\n**Connections:**\n*   **Inputs:**\n    *   **CN5 Pin-7 EVENT** connects to **CLK3**.\n    *   **CN5 Pin-9 GATE3** connects to **GATE3**.\n    *   **4MHz Oscillator** connects to **CLK4**.\n    *   **Vcc** (via a resistor symbol) connects to both **GATE4** and **GATE5**.\n\n*   **Outputs and Connector:**\n    *   **OUT3** connects to a header block. This header is also connected to **CN5 Pin-13 External IRQ**.\n    *   The header block has three output labels pointing to the right: **External IRQ**, **Event IRQ**, and **Timer Pacer IR**.\n    *   Based on the pin layout:\n        *   **OUT3** routes to **External IRQ** (and **CN5 Pin-13 External IRQ**).\n        *   **OUT4** routes to **Event IRQ**.\n        *   **OUT5** routes to **Timer Pacer IR**.](.acl-7120a-6-manual-3/69a581cd8fa1f874286adbcfd308e2cb9f35c56f899569b18a6d533a5ddfce2d.jpg)

Figure 3.3 Block Diagram of 8254 Timer/Counter

The pacer rate of above configuration is determined by the formula:

$$
\text { pacer   rate } = 4 \mathrm{MHz} / (\mathrm{C4} ^ {*} \mathrm{C5})
$$

The maximum pacer signal rate is 4MHz/1=4Mhz. The minimum signal rate is 4MHz / (65535\*65535)—an extremely slow frequency.

To get a pacer rate of 2.5kHz, users can set C1 = 40 and C2 = 40:

$$
2. 5 \mathrm{KHz} = 4 \mathrm{Mhz} / (4 0 * 4 0)
$$

# 3.4 Clock Source Pads

In addition to the clock signal pads, the frequency sources can also be wired through the soldering pads. The clock source links to the clock input of the 8254 timer/counter by soldering a wire between its corresponding pads.

# For example:

If counter 1 needs a 10kHz clock input, simply solder a wire between pads "10k" and "CLK1" and insert a jumper in the position "X1" of the JP1 as shown below:

![1M\n100K\n10K\n(Hz)\nX2\nX1\nX1/ 2\nX1/ 4\nJP1](.acl-7120a-6-manual-3/cfd942c85dea8ad64ec875d824407667fc7c7e38eda2d9e846829a10bc19f54c.jpg)

# 3.5 Latch Digital Inputs

The ACL-7120A offers a handy method to latch the input status for special applications. A latched input happens when the STROBE signal (20 pin of CN2 or CN4) is keep high. The data read from the input port will always reflect the current status. As the STROBE signal goes from High to Low, it will latch the input signal and store it in the input buffer. If STROBE is continually kept on Low, the data on input port is held as the same as the latched data. The current input signal will not be available until STROBE becomes High or open.

In most cases, the STROBE signal is always kept as High. The following table is used to describe the relationship between STROBE signal and input status.

<table><tr><td>STROBE SIGNAL</td><td>Digital Input Data</td></tr><tr><td>High</td><td>Transparent</td></tr><tr><td>High to Low</td><td>Latched</td></tr></table>

Two STROBE signals are offered in the ACL-7120A, one is on connector CN2 and the other is on CN4.

# 4

# Programming

# 4.1 I/O Registers Format

The ACL-7120A occupies 16 consecutive addresses in the PC I/O address space. Table 4.1 shows the I/O Map

<table><tr><td>Address</td><td>Write</td><td>Read</td></tr><tr><td>Base + 0</td><td>DO 0-7</td><td>DI 0-7</td></tr><tr><td>Base + 1</td><td>DO 8-15</td><td>DI 8-15</td></tr><tr><td>Base + 2</td><td>DO 16-23</td><td>DI 16-23</td></tr><tr><td>Base + 3</td><td>DO 24-31</td><td>DI 24-31</td></tr><tr><td>Base + 4</td><td colspan="2">LSB OR MSB OF COUNTER 0</td></tr><tr><td>Base + 5</td><td colspan="2">LSB OR MSB OF COUNTER 1</td></tr><tr><td>Base + 6</td><td colspan="2">LSB OR MSB OF COUNTER 2</td></tr><tr><td>Base + 7</td><td colspan="2">CONTROL BYTE CW0</td></tr><tr><td>Base + 8</td><td colspan="2">LSB OR MSB OF COUNTER 3</td></tr><tr><td>Base + 9</td><td colspan="2">LSB OR MSB OF COUNTER 4</td></tr><tr><td>Base + 10</td><td colspan="2">LSB OR MSB OF COUNTER 5</td></tr><tr><td>Base + 11</td><td colspan="2">CONTROL BYTE CW1</td></tr></table>

DO -- Digital Output

DI -- Digital Input

LSB -- Least Significant Byte

MSB -- Most Significant Byte

Table 4.1

# 4.2 Digital I/O Programming

The ACL 7120A provides 32 digital input channels and 32 digital output channels. Four I/O port address (Base+0, ..., Base+3) are reserved for these digital I/O channels. The relationship between I/O address and I/O channels are specified as following:

\*\* Digital Input Register Format:

Address: BASE + 0, BASE + 1, BASE + 2, BASE + 3

Attribute: Read for digital input

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Base + 0</td><td>DI7</td><td>DI6</td><td>DI5</td><td>DI4</td><td>DI3</td><td>DI2</td><td>DI1</td><td>DI0</td></tr><tr><td>Base + 1</td><td>DI15</td><td>DI14</td><td>DI13</td><td>DI12</td><td>DI11</td><td>DI10</td><td>DI9</td><td>DI8</td></tr><tr><td>Base + 2</td><td>DI23</td><td>DI22</td><td>DI21</td><td>DI20</td><td>DI19</td><td>DI18</td><td>DI17</td><td>DI16</td></tr><tr><td>Base + 3</td><td>DI31</td><td>DI30</td><td>DI29</td><td>DI28</td><td>DI27</td><td>DI26</td><td>DI25</td><td>DI24</td></tr></table>

\*\* Digital Output Register Format:

Address: BASE + 0, BASE + 1, BASE + 2, BASE + 3

Attribute: write for digital output

Data Format:

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Base + 0</td><td>DO7</td><td>DO6</td><td>DO5</td><td>DO4</td><td>DO3</td><td>DO2</td><td>DO1</td><td>DO0</td></tr><tr><td>Base + 1</td><td>DO15</td><td>DO14</td><td>DO13</td><td>DO12</td><td>DO11</td><td>DO10</td><td>DO9</td><td>DO8</td></tr><tr><td>Base + 2</td><td>DO23</td><td>DO22</td><td>DO21</td><td>DO20</td><td>DO19</td><td>DO18</td><td>DO17</td><td>DO16</td></tr><tr><td>Base + 3</td><td>DO31</td><td>DO30</td><td>DO29</td><td>DO28</td><td>DO27</td><td>DO26</td><td>DO25</td><td>DO24</td></tr></table>

# Digital Input Operation (Read):

The digital input states are read as a single byte from the port at address BASE+N (N= 0,1,2,3). For each of the 8 bits within the byte corresponding to particular digital input, a high bit (1) signifies the input is energized, a low bit (0) signifies the input is de-energized.

# For example:

In BASIC,

05 BASE=&H2A0

10 VALUE1 = INP(BASE + 0) ‘Read DO0 - DI 7

20 VALUE2 = INP(BASE + 2) ‘Read DO16 - DI 23

# ♦ Write operation:

The digital output states are written as 1 single byte to the port at address BASE+N (N=0,1,2,3). Data is written to all 8 bits as a single byte.

# For example:

In BASIC:

05 BASE=&H2A0
06 VALUE1% = &H3F
07 VALUE2% = &HF3

10 OUT(BASE + 0), VALUE1% ‘ the digital outputs (DO0-DO7) will’ be (00111111)

20 OUT(BASE + 2), VALUE2% ‘ the digital outputs (DO16 - DO23) will be (11110011)

# 4.3 Programmable Interval Timer

Note: The material of this section is adopted from

“Intel Microprocessor and Peripheral Handbook Vol. II --Peripheral”

# 4.3.1 The Intel (NEC) 8254

The 8254 contains three independent, programmable, and multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words. The most common uses for the 8254 in microprocessor-based systems are:

• Event counter
• Binary rate multiplier
• Real-time clock
• Digital one-shot
• Motor control

• Programmable baud rate generator

# 4.3.2 The Control Byte

The 8254 occupies 8 I/O address locations in the ACL-7120A I/O map, as shown below:

<table><tr><td>Base + 4</td><td>LSB OR MSB OF COUNTER 0</td></tr><tr><td>Base + 5</td><td>LSB OR MSB OF COUNTER 1</td></tr><tr><td>Base + 6</td><td>LSB OR MSB OF COUNTER 2</td></tr><tr><td>Base + 7</td><td>CONTROL BYTE for Chip 0</td></tr><tr><td>Base + 8</td><td>LSB OR MSB OF COUNTER 3</td></tr><tr><td>Base + 9</td><td>LSB OR MSB OF COUNTER 4</td></tr><tr><td>Base + 10</td><td>LSB OR MSB OF COUNTER 5</td></tr><tr><td>Base + 11</td><td>CONTROL BYTE for Chip 1</td></tr></table>

Before loading or reading any of these individual counters, the control byte (Base + 7, Base + 11) must be loaded first. The format of control byte is:

Control Byte: (Base + 7, Base + 11)

<table><tr><td>Bit</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td></td><td>SC1</td><td>SC0</td><td>RL1</td><td>RL0</td><td>M2</td><td>M1</td><td>M0</td><td>BCD</td></tr></table>

• SC1 & SC1 - Select Counter (Bit7 & Bit 6)

<table><tr><td>SC1</td><td>SC0</td><td>COUNTER</td></tr><tr><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>2</td></tr><tr><td>1</td><td>1</td><td>ILLEGAL</td></tr></table>

• RL1 & RL0 - Select Read/Load operation (Bit 5 & Bit 4)

<table><tr><td>RL1</td><td>RL0</td><td>OPERATION</td></tr><tr><td>0</td><td>0</td><td>COUNTER LATCH</td></tr><tr><td>0</td><td>1</td><td>READ/LOAD LSB</td></tr><tr><td>1</td><td>0</td><td>READ/LOAD MSB</td></tr><tr><td>1</td><td>1</td><td>READ/LOAD LSB FIRST, THEN MSB</td></tr></table>

• M2, M1 & M0 - Select Operating Mode (Bit 3, Bit 2, & Bit 1)

<table><tr><td>M2</td><td>M1</td><td>M0</td><td>MODE</td></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td></tr><tr><td>0</td><td>0</td><td>1</td><td>1</td></tr><tr><td>x</td><td>1</td><td>0</td><td>2</td></tr><tr><td>x</td><td>1</td><td>1</td><td>3</td></tr><tr><td>1</td><td>0</td><td>0</td><td>4</td></tr><tr><td>1</td><td>0</td><td>1</td><td>5</td></tr></table>

• BCD - Select Binary/BCD Counting ( Bit 0)

<table><tr><td>0</td><td>BINARY COUNTER 16-BITS</td></tr><tr><td>1</td><td>BINARY CODED DECIMAL (BCD) COUNTER (4 DECADES)</td></tr></table>

# Note:

1. The count of the binary counter is from 0 up to 65,535.
2. The count of the BCD counter is from 0 up to 99,999.

# 4.3.3 Mode definition

There are six different selectable operating modes in the 8254:

# Mode 0: Interrupt on terminal count

The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will begin counting. When terminal count is reached, the output will go high and remain high until the selected count register is reloaded with a mode or a new count is loaded. The counter continues to decrement after terminal count has been reached.

Rewriting a counter register during counting is done by:

(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.

# Mode 1: Programmable One-Shot

The output will go low on the count following the rising edge of the gate input. The output will go high on the terminal count. If a new count value is loaded while the output is low it will not affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at anytime without affecting the one-shot pulse.

The one-shot is re-triggerable, hence the output will remain low for the full count after any rising edge of the gate input.

# Mode 2: Rate Generator

A Divide by N counter. The output will be low for one period of the input clock. The period from one output pulse to the next equals the number of input counts in the count register. If the count register is reloaded between output pulses the present period will not be affected, but the subsequent period will reflect the new value.

The gate input, when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus, the gate input can be synchronized by software.

When this mode is set, the output will remain high until after the count register is loaded. The output can also be synchronized by software.

# Mode 3: Square Wave Rate Generator.

Similar to Mode 2 except that the output will remain high until one half of the count has been completed (or for even counts) and go low for the other half of the count. This is accomplished by decrementing the counter by two on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated.

If the count is odd and the output is high, the first clock pulse (after the count is loaded) decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After time-out, the output goes low and the full count is reloaded. The first clock pulse (following the reload) decrements the counter by 3. Subsequent clock pulses decrement the count by 2 until time-out. Then the whole process is repeated. In this way, if the count is odd, the output will be high for (N + 1)/2 counts and low for (N - 1)/2 counts.

In Modes 2 and 3, if a CLK source other then the system clock is used, GATE should be pulsed immediately following Way Rate of a new count value.

# Mode 4: Software Triggered Strobe.

After the mode is set, the output will be high. When the count is loaded, the counter will begin counting. On the terminal count, the output will go low for one input clock period, then high again.

If the count register is reloaded during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low.

# Mode 5: Hardware Triggered Strobe.

The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is re-triggerable. The output will not go low until the full count after the rising edge of any trigger.

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