# AmITX-AL-I User’s Manual

Thin Mini-ITX Embedded Motherboard with Intel® Atom™, Pentium®, and Celeron® SoCs

![Green printed circuit board with various electronic components and connectors (no visible text or labels)](.amitx-al-i-50-1j087-1000-10/1b0d250280f197af569e638b47fe86ecbd780b5c72d272ad7a067abe8e721237.jpg)

Manual Rev.: 1.0

Revision Date: October 17, 2018

Part Number: 50-1J087-1000

# Preface

# Copyright

Copyright 2018 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.amitx-al-i-50-1j087-1000-10/44428dcee82513c3f38fb1462ae95117cede082ed5bdaa97023c7fe32bca2607.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin with crossed lines indicating no waste or restriction (no text or symbols)](.amitx-al-i-50-1j087-1000-10/6c6d844cf9b17d0b9e74f022aa8b75966561399f126c428b07ddfa26779f073a.jpg)

![Li-ion](.amitx-al-i-50-1j087-1000-10/6d03aa5eaf879e6d0770cd1a705c92ceab7195f34c00859a39285b32e6046137.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.amitx-al-i-50-1j087-1000-10/b057749adb0bf1561742945a5f52f59df2ced82881f15847ce17809e02ded37f.jpg)

![廢電池請回收](.amitx-al-i-50-1j087-1000-10/3a930e7f9f7936371b0866399f9a4d2ca4bb9006237610fcd02aa9293ec9ee50.jpg)

# California Proposition 65 Warning

![This image features a standard warning sign consisting of a yellow equilateral triangle with a thick black border. Inside the triangle is a black exclamation point.](.amitx-al-i-50-1j087-1000-10/a1c233fd5ad46328c45e88052d95df4d3c7ec10bc73bcb1c1c6af038f282e0f4.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial Release</td><td>10-17-2018</td><td>DA</td></tr></table>

# Table of Contents

# Preface ...................

# List of Figures ........

# List of Tables.... .vi

# 1. Introduction....

1.1. Packing List.. 2
1.2. Optional Accessories.. 2

# 2. Specifications ...

2.1. Core System . 3
2.2. Rear I/O Connectors .. 3
2.3. Internal Headers and Connectors..
2.4. Form Factor...
2.5. SEMA Board Controller ..
2.6. Debug Header..
2.7. Video.. .5
2.8. Audio.. 5
2.9. LAN.. .5
2.10. Power Specification.. 5
2.11. Temperatures... .8
2.12. Environmental . .8
2.13. Operating Systems.. .8
2.14. Functional Block Diagram.. 9

# 3. Mechanical Layout .. .11

3.1. Connector Locations ... ..11
3.2. Mechanical Dimensions ..13

# 4. Connectors and Jumpers ...... .15

4.1. Rear IO Connectors . ..15
4.2. Internal Connectors.. ..18
4.3. Jumper and Switch Settings . ..30
4.4. Onboard Connector Information .. ..33

# 5. Smart Embedded Management Agent (SEMA) ........... .35

5.1. Board Specific SEMA Functions.. .35

# 6. System Resources ....... .39

6.1. System Memory Map ..... ..39
6.2. I/O Map .. ..39
6.3. Interrupt Request (IRQ) Lines . ..40
6.4. PCI Configuration Space Map . ..42
6.5. PCI Interrupt Routing Map.. ..43
6.6. SMBus Slave Address.. ..43

# 7. BIOS Setup..... .45

7.1. Menu Structure.. ..45
7.2. Main . ..46
7.3. Advanced .. ..48
7.4. Chipset.. ..59
7.5. Security .. ..66
7.6. Boot .. ..67
7.7. Save & Exit . ..67

# Safety Instructions............. ..69

# Getting Service..... .70

# List of Figures

Figure 1: AmITX-AL-I Functional Block Diagram . .9
Figure 2: AmITX-AL-I Rear I/O ... .11
Figure 3: AmITX-AL-I Component Side Connectors .. .11
Figure 4: AmITX-AL-I Solder Side Connectors . .12
Figure 5: AmITX-AL-I Mechanical Dimensions . ..13

# List of Tables

Table 1: AmITX-AL-I Processors.

Table 2: AmITX-AL-I Onboard Connector Information.. ..33

Table 3: SEMA Onboard Voltage Monitor .. ...35

Table 4: SEMA BMC Status ... ...36

Table 5: SEMA Exception Codes ... ...36

Table 6: SEMA BMC Flags. .37

Table 7: System Memory Map ..... ..39

Table 8: I/O Map ... ...39

Table 9: IRQ Lines PIC Mode .. ...40

Table 10: IRQ Lines APIC Mode . ..41

Table 11: PCI Configuration Space Map. ..42

Table 12: PCI Interrupt Routing Map... ..43

Table 13: SMBus Slave Address. ...43

# 1. Introduction

The AmITX-AL-I is a low-profile Thin Mini-ITX embedded motherboard supporting an Intel® Atom™ processor x7- E3900 series, Intel® Pentium® processor N4200, and Intel® Celeron® processor N3350 system-on-chip (SoC). The AmITX-AL-I is specifically designed for customers who need optimized processing and graphics performance with low power consumption in a long product life solution.

The Intel® Atom™ processor, Intel® Pentium® processor, and Intel® Celeron® processor support non-ECC type DDR3L dual-channel memory at 1600/1866 MHz to provide excellent overall performance. Integrated Intel® Gen9 LP Graphics includes features such as OpenGL 4.3, DirectX 12, OpenCL 2.0; and support for H.265/HEVC, H.264, MPEG2, VC1, VP9, MVC, JPEG/MJPEG hardware decode. Up to three independent displays are available from DDI ports supporting HDMI/DisplayPort, optional single/dual-channel 18/24-bit LVDS, and optional eDP.

The AmITX-AL-I supports dual stacked SODIMM sockets for up to 16 GB non-ECC type DDR3L memory, and graphics outputs include DisplayPort, HDMI, and optional eDP and optional dual-channel 18/24-bit LVDS. I/O features include HD Audio, dual Gigabit Ethernet port, 4x USB 3.0 ports and 3x USB 2.0 ports, 6x COM ports, PCIe x1 slot, Mini PCIe slot, mSATA slot, and 2x SATA 6 Gb/s ports. A feature connector provides 10 GPIOs, SMBus, and I2C, and optional SIM card slot and microSD card slot are available. The AmITX-AL-I is equipped with SPI AMI EFI BIOS, supporting embedded features such as hardware monitor and watchdog timer.

The Thin Mini-ITX form factor is the “premier standard for designing and assembling all-in-one PCs,” according to Intel. Measuring 170 mm square and less than 25 mm thick, Thin Mini-ITX fulfills requirements for applications in digital signage, infotainment, medical, and industrial automation that are running in limited-space environments. ADLINK’s thin Mini-ITX board also follows the Form, Fit, Function design principle to offer standardized pinout locations and is compatible with the Micro-ATX and regular ATX chassis. The AmITX-AL-I provides an easy and fast path to creating industrial computing solutions.

Table 1: AmITX-AL-I Processors

<table><tr><td>Model</td><td>Intel “Braswell” SoC</td><td>Core Speed (HFM/Burst)</td><td>Thermal Design Power (TDP)</td><td>Scenario Design Power (SDP)</td></tr><tr><td>AmITX-AL-I-E3950</td><td> $Atom^{TM}$  x7-E3950 (4 cores)</td><td>1.60/2.00 GHz</td><td>12W</td><td></td></tr><tr><td>AmITX-AL-I-E3940</td><td> $Atom^{TM}$  x5-E3940 (4 cores)</td><td>1.60/1.80 GHz</td><td>9.5W</td><td></td></tr><tr><td>AmITX-AL-I-E3930</td><td> $Atom^{TM}$  x5-E3930 (2 cores)</td><td>1.30/1.80 GHz</td><td>6.5W</td><td></td></tr><tr><td>AmITX-AL-I-N4200</td><td>Pentium® N4200 (4 cores)</td><td>1.10/2.50 GHz</td><td>6W</td><td>4W</td></tr><tr><td>AmITX-AL-I-N3350</td><td>Celeron® N3350 (2 cores)</td><td>1.10/2.40 GHz</td><td>6W</td><td>4W</td></tr></table>

Latest revision of the datasheet, user’s manual, BIOS, drivers, and board support packages, can be downloaded from the product webpage: http://www.adlinktech.com/PD/web/PD\_detail.php?cKind=&pid=1667#

# 1.1. Packing List

• AmITX-AL-I Thin Mini-ITX Embedded Board
• SATA dual power cable (P/N: 30-20875-0000)
• SATA cable (P/N: 30-10057-0600)
• Standard rear I/O shield (PN:34-25318-2000)

# 1.2. Optional Accessories

• COM port cable, 1 port (P/N: 30-20876-0000)
• PS/2 KB/MS cable (P/N: 30-20873-0000)
• USB 2.0 cable, 2 ports (P/N: 30-20874-1000)

# 2. Specifications

# 2.1. Core System

<table><tr><td>CPU</td><td>Dual or quad-core Intel® AtomTM, Pentium®, and Celeron® Processor SoCAtomTM x7-E3950 1.60/2.00 (Burst) GHz 12W (4C/1866)AtomTM x5-E3940 1.60/1.80 (Burst) GHz 9.5W (4C/1866)AtomTM x5-E3930 1.30/1.80 (Burst) GHz 6.5W (2C/1866)Pentium® N4200 1.10/2.50 (Burst) GHz 6W (4W SDP) (4C/1866)Celeron® N3350 1.10/2.40 (Burst) GHz, 6W (4W SDP) (2C/1866)Supportboth Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x)/Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)Notes:Availability of features may vary between processor SKUs and operating systemsOnly AtomTM SKUs can support extreme temperature operating range</td></tr><tr><td>Cache</td><td>2MB for all SKUs</td></tr><tr><td>Memory</td><td>Dual channel non-ECC 1600/1333 MHz DDR3L memory up to 16GB in dual stacked SODIMM sockets</td></tr><tr><td>Embedded BIOS</td><td>AMI EFI in 16MB SPI BIOS</td></tr></table>

# 2.2. Rear I/O Connectors

<table><tr><td>Display</td><td>1x DisplayPort (2x DisplayPort by build option, in place of HDMI), 1x HDMI (co-lay with DP)</td></tr><tr><td>LAN</td><td>Dual GbE RJ-45</td></tr><tr><td>USB</td><td>4x USB 3.0</td></tr><tr><td>Audio</td><td>Line-Out, Mic-In</td></tr><tr><td>Power</td><td>Screw Jack for 12V DC-in</td></tr></table>

# 2.3. Internal Headers and Connectors

<table><tr><td>PCI Express Slots</td><td>1x PCIe x1 slot2x Mini PCIe slots: one PCIe + USB; one mSATA (colay with SATA1)</td></tr><tr><td>USB</td><td>2x USB 2.0 via onboard header, 1x USB 2.0 via front panel connector</td></tr><tr><td>SATA</td><td>2x SATA 6Gb/s (SATA1, SATA2)SATA Power Connector</td></tr><tr><td>Serial</td><td>2x RS-232/422/485 headers with 0V/5V/12V power, 4x RS-232 headers</td></tr><tr><td>LVDS (optional)</td><td>Dual-channel 18/24-bit, switched from eDP (build option)</td></tr><tr><td>eDP (optional)</td><td>Build option, not available concurrently with LVDS</td></tr><tr><td>SIM Card Slot</td><td>Build option</td></tr><tr><td>microSD Card Slot</td><td>Build option</td></tr><tr><td>Other</td><td>Front Panel HeaderAudio HeaderFeature Connector HeaderPS/2 KB/MS ConnectorTPM HeaderSPI HeaderATX Power Connector (4-pin)</td></tr></table>

# 2.4. Form Factor

Mini-ITX: 170mm x 170mm

# 2.5. SEMA Board Controller

ADLINK Smart Embedded Management Agent (SEMA)

• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and Forensic information
• Flat Panel Control
• General Purpose I2C
• Failsafe BIOS (dual BIOS )
• Watchdog Timer and Fan Control

# 2.6. Debug Header

40-pin Multipurpose Flat Cable Connector: used in combination with DB-40 debug module providing BIOS POST code LED, BMC access, SPI BIOS flashing, Power Testpoints, Debug LEDs

# 2.7. Video

<table><tr><td>GPU Feature Support</td><td>Intel® 9th generation LP graphics core architecture with up to 18 execution units supporting three independent displays3D graphics hardware accelerationSupport for DirectX12/11.3/10/9.3, OCL 2.0, OGL ES 3.0, OGL 4.3Video decode hardware acceleration including support for H.265 (HEVC), H.264, MVC, MPEG-2, VC-1, WMV9, VP8/VP9, JPEG/MJPEG formatsVideo encode hardware acceleration including support for H.265 (HEVC), H.264, VP8/VP9, JPEG/MJPEG formatsSupports content protection using PAVP 2.0 and HDCP 1.4/2.0Note: Availability of features dependent on processor SKU and may vary between operating systems.</td></tr><tr><td>Display Interface Support</td><td>DisplayPort: Supports DP1.2, maximum resolution: 4096x2160 @ 24Hz (2x DisplayPort by build option, in place of HDMI)HDMI: Supports HDMI 1.4b, maximum resolution: 3840x2160 @ 30Hz (co-lay with DP)LVDS (optional): Supports single/dual channel 18/24-bit, up to 1920x1200 @ 60 HzeDP (optional): Supports eDP 1.3, maximum resolution: 3840x2160 @ 60HzNote: The configuration of triple display support is DP + HDMI + LVDS/eDP (2x DP + LVDS/eDP by build option)</td></tr></table>

# 2.8. Audio

Audio Codec: ALC888S

# 2.9. LAN

<table><tr><td>Intel MAC/PHY</td><td>Intel® i211AT (MAC/PHY) Ethernet Controller (Intel® i210 by build option for extreme operating temperature range support)</td></tr><tr><td>Interface</td><td>10/100/1000 GbE connection</td></tr></table>

# 2.10. Power Specification

<table><tr><td>Power Modes</td><td>AT and ATX mode (AT mode start controlled by BMC)</td></tr><tr><td>Standard Voltage Input</td><td>12VDC ±5%</td></tr><tr><td>Power Management</td><td>ACPI 4.0 compliant</td></tr><tr><td>Power States</td><td>Supports C0, C1, C1E, C6C, C6, C7, S0, S1, S3, S4, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5)</td></tr></table>

2.10.1. Power Consumption

<table><tr><td>Processor</td><td>Intel® AtomTM E3950 @ 1.60Ghz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3940 @ 1.60Ghz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3930 @ 1.30Ghz (4C 1.6GHz, 2x 1MB LK2)</td></tr><tr><td>Memory</td><td>Transcend TS512MSK64W6H 4GB DDR3 SO-DIMM PC3-12800U DDR3-1600</td><td>Transcend TS512MSK64W6H 4GB DDR3 SO-DIMM PC3-12800U DDR3-1600</td><td>Transcend TS512MSK64W6H 4GB DDR3 SO-DIMM PC3-12800U DDR3-1600</td></tr><tr><td>Graphics</td><td>Intel® HD Graphics 505</td><td>Intel® HD Graphics 500</td><td>Intel® HD Graphics 500</td></tr><tr><td>HDD</td><td>Micron SSD 2.5" CT250MX200SSD1 250GB</td><td>Micron SSD 2.5" CT250MX200SSD1 250GB</td><td>Micron SSD 2.5" CT250MX200SSD1 250GB</td></tr><tr><td>OS</td><td>Window 10 Enterprise (10.0.15063) 64bit V1703</td><td>Window 10 Enterprise (10.0.15063) 64bit V1703</td><td>Window 10 Enterprise (10.0.15063) 64bit V1703</td></tr><tr><td colspan="4">Windows Idle mode/Enable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>0.33</td><td>0.33</td><td>0.33</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>3.96</td><td>3.96</td><td>3.96</td></tr><tr><td colspan="4">Windows Idle mode/Disable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>0.34</td><td>0.34</td><td>0.34</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>4.08</td><td>4.08</td><td>4.08</td></tr><tr><td colspan="4">Windows typical mode/Enable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>1.3</td><td>1.1</td><td>0.9</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>15.6</td><td>13.2</td><td>10.8</td></tr><tr><td colspan="4">Windows typical mode/Disable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>1.2</td><td>1.05</td><td>0.8</td></tr><tr><td>Processor</td><td>Intel® AtomTM E3950 @ 1.60Ghz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3940 @ 1.60GHz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3930 @ 1.30GHz (4C 1.6GHz, 2x 1MB LK2)</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>14.4</td><td>12.84</td><td>9.6</td></tr><tr><td colspan="4">Windows MAX mode/Enable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>1.6</td><td>1.4</td><td>1.1</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>19.2</td><td>16.8</td><td>13.2</td></tr><tr><td colspan="4">Windows MAX mode/Disable EIST</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>1.45</td><td>1.3</td><td>1.0</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>17.4</td><td>15.6</td><td>12</td></tr><tr><td colspan="4">System S1 mode</td></tr><tr><td>3.3V(A)</td><td>No support</td><td>No support</td><td>No support</td></tr><tr><td>5V(A)</td><td>No support</td><td>No support</td><td>No support</td></tr><tr><td>12V(A)</td><td>No support</td><td>No support</td><td>No support</td></tr><tr><td>Power consumption(W)</td><td>Not Applicable</td><td>Not Applicable</td><td>Not Applicable</td></tr><tr><td colspan="4">System S3 mode</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>0.07</td><td>0.07</td><td>0.07</td></tr><tr><td>Power consumption(W)</td><td>0.84</td><td>0.84</td><td>0.84</td></tr><tr><td colspan="4">System S4 mode</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>0.05</td><td>0.05</td><td>0.05</td></tr><tr><td>Power consumption(W)</td><td>0.6</td><td>0.6</td><td>0.6</td></tr><tr><td colspan="4">S5 Mode with ECO Disable</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Processor</td><td>Intel® AtomTM E3950 @ 1.60Ghz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3940 @ 1.60Ghz (4C 1.6GHz, 2x 1MB LK2)</td><td>Intel® AtomTM E3930 @ 1.30Ghz (4C 1.6GHz, 2x 1MB LK2)</td></tr><tr><td>12V(A)</td><td>0.05</td><td>0.05</td><td>0.05</td></tr><tr><td>Power consumption(W)</td><td>0.6</td><td>0.6</td><td>0.6</td></tr><tr><td colspan="4">S5 Mode with ECO Enable</td></tr><tr><td>3.3V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>12V(A)</td><td>0.01</td><td>0.01</td><td>0.01</td></tr><tr><td>5VSB(A)</td><td>0</td><td>0</td><td>0</td></tr><tr><td>Power consumption(W)</td><td>0.12</td><td>0.12</td><td>0.12</td></tr></table>

# 2.11. Temperatures

<table><tr><td>Standard Operating Temperature</td><td>0°C to 60°C</td></tr><tr><td>Extreme Rugged Operating Temperature</td><td>-40°C to 85°C (build option, supported by AtomTM SKUs only)</td></tr></table>

# 2.12. Environmental

<table><tr><td>Humidity</td><td>10-90% RH operating, non-condensing</td></tr><tr><td>Shock and Vibration</td><td>MIL-STD-202G Method 214A, Table 214-I Condition D. MIL-STD-202G Method 213B, Table 213-I Condition A.</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr></table>

# 2.13. Operating Systems

<table><tr><td>Standard Support</td><td>Windows 10 Enterprise 64-bit, Linux 64-bit, (VxWorks 64-bit is TBD)</td></tr><tr><td>Extended Support (BSP)</td><td>Linux 64-bit, (VxWorks 64-bit is TBD)</td></tr></table>

2.14. Functional Block Diagram
![**Central Processor**\n*   **Intel® Atom™ Celeron® Pentium® SoC Processors (fomerly “Apollo Lake” “Apollo Lake-I”)**\n\n**Left Side Connections & Blocks**\n*   **Memory:**\n    *   'Horizontal SODIMM (Channel A) DDR3L at 1867/1600 MHz (non ECC)' connects to the SoC.\n    *   'Horizontal SODIMM (Channel B) DDR3L at 1867/1600 MHz (non ECC)' connects to the SoC.\n*   **Display/Video:**\n    *   SoC connects via 'DDI0' to 'HDMI DP (optional)'.\n    *   SoC connects via 'DDI1' to 'DP'.\n*   **Networking:**\n    *   SoC connects via 'PCIe x1 Port 3' to 'GbE Intel I211AT', which connects to 'RJ-45 10/100/1000'.\n    *   SoC connects via 'PCIe x1 Port 4' to 'GbE Intel I211AT', which connects to 'RJ45 10/100/1000'.\n*   **USB 3.0:**\n    *   SoC connects via 'USB 3.0 port 0/1' to two blocks labeled 'USB3.0'.\n    *   SoC connects via 'USB 3.0 port 2/3' to two blocks labeled 'USB3.0'.\n*   **Audio:**\n    *   SoC connects to 'HDA Codec ALC888S'.\n    *   'HDA Codec ALC888S' connects to 'Line Out Mic In' and 'Audio Header'.\n*   **Super I/O & Serial Ports:**\n    *   SoC connects via 'LPC' to 'Super I/O'.\n    *   'Super I/O' connects to 'COM1' and 'COM2' (labeled '2x RS-232/422/485 0/5/12V').\n    *   'Super I/O' connects to 'COM3', 'COM4', 'COM5', 'COM6' (labeled '4x RS-232').\n    *   'Super I/O' connects to 'PS/2 KB/MS' (labeled 'PS/2').\n    *   'Super I/O' connects via 'LPC' to 'TPM (optional)'.\n\n**Right Side Connections & Blocks**\n*   **Display (eDP/LVDS):**\n    *   SoC connects via 'eDP' (4 lanes) to 'eDP to LVDS' (labeled 'eDP (optional)').\n    *   'eDP to LVDS' connects to 'LVDS (eDP) Single/Dual Channel 18/24-bit' via 'DDC' and 'LVDS Dat/Ck'.\n    *   'LVDS Control' connects 'Brightness' to 'LVDS AUX Connector'.\n    *   'PWM switch' connects to 'eDP to LVDS' (labeled 'PWM from SEMA BMC').\n*   **PCIe:**\n    *   SoC connects via 'PCIe x1 port 1' to 'PCIe x1 slot'.\n    *   SoC connects via 'PCIe x1 port 2' to 'Mini PCIe full size'.\n    *   'Mini PCIe full size' connects to 'SIM card slot'.\n    *   There is a label 'USB 2.0' near the Mini PCIe connection.\n*   **SATA:**\n    *   SoC connects via 'SATA 0 6Gb/s' to 'SATA Switch'.\n    *   'SATA Switch' connects to 'mSATa full size' and 'SATA'.\n    *   SoC connects via 'SATA 1 6Gb/s' to 'SATA'.\n*   **USB 2.0:**\n    *   SoC connects via 'USB 2.0 port 1' to '1x USB 2.0 front panel Header'.\n    *   SoC connects via 'USB 2.0 port 2' and 'USB 2.0 port 3' to 'USB 2.0 header'.\n*   **Other Peripherals:**\n    *   SoC connects via a dashed line to 'microSD Card'.\n    *   SoC connects via 'SPI 0/1' to 'SPI Header' and 'SPI1 SPI0 Socket'.\n    *   SoC connects via 'SMBus' to 'SEMA BMC TI TM4C123'.\n    *   'SEMA BMC' connects to 'CPU FAN' and 'SYS FAN'.\n    *   'SEMA BMC' connects to 'Sensor LM73'.\n    *   'Sensor LM73' connects (dashed, optional) to 'Feature Connector'.\n    *   'SEMA BMC' connects to 'GPIO NXP PCA9535'.\n    *   'GPIO NXP PCA9535' connects to 'Feature Connector' (labeled 'GPIO').\n    *   SoC connects via 'System Signals' to 'Feature Connector'.\n    *   'Feature Connector' connects to 'Rear I/O' and 'Internal I/O'.](.amitx-al-i-50-1j087-1000-10/eede699caf3c75df0fbb091436f57f3f80058de835de8b265a533bac1222628a.jpg)

Figure 1: AmITX-AL-I Functional Block Diagram

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# 3. Mechanical Layout

# 3.1. Connector Locations

# 3.1.1. Rear I/O

![12V DC-in\nDual LAN\n4x USB 3.0\nDP\nDP\n(optional)\nHDMI\nLine-out (rt)\nMic-in (Ift)](.amitx-al-i-50-1j087-1000-10/a04be62de3f3675ca38884eb22c0e125d1c93d0b7aaaf76cd9e77a31d873a70f.jpg)

Figure 2: AmITX-AL-I Rear I/O

# 3.1.2. Component Side Connectors

![Battery\nCPU Fan\nFeature Connector\nFront Panel\nPCIe x1\nAudio\nFront Panel Auxiliary\nUSB\nSATA Power\nmSATA Slot\n2x SATA 3\n2 Stacked SODIMM\nMini PCIe\n12V DC-in\nSPI Header\nATX Power\nSPI Socket\neDP\nLVDS\n6x RS-232\nTPM Header\nPS/2 KB/MS\nSystem Fan](.amitx-al-i-50-1j087-1000-10/750f6292a457c04c01d362dddd9258cfff58ecf98bfef8af7487b1fc9f8faffa.jpg)

Figure 3: AmITX-AL-I Component Side Connectors

# 3.1.3. Solder Side Connectors

![E184671 4M\nWapro-XS ISK\n00:1C01\nmicroSD\nCard Slot\nDB40 Connector\nSIM Card\nSlot](.amitx-al-i-50-1j087-1000-10/a0fe22806da8723c6f064182cab434f649433cf118f6c4c0f98ba4752defe0ae.jpg)

Figure 4: AmITX-AL-I Solder Side Connectors

# 3.2. Mechanical Dimensions

![| Component | Value |\n| :--- | :--- |\n| Top View (W/O RTC battery) | 157.48 |\n| Top View (W/O RTC battery) | 154.94 |\n| Top View (W/O RTC battery) | 22.86 |\n| Top View (W/O RTC battery) | 3.50 |\n| Top View (W/O RTC battery) | 163.83 |\n| Top View (W/O RTC battery) | 157.48 |\n| Top View (W/O RTC battery) | 108.53 |\n| Top View (W/O RTC battery) | 57.53 |\n| Top View (W/O RTC battery) | 0 |\n| Top View (W/O RTC battery) | 6.35 |\n| Top View (W/O RTC battery) | 0 |\n| Top View (W/O RTC battery) | 10.16 |\n| Top View (W/O RTC battery) | 44.91 |\n| Top View (W/O RTC battery) | 95.91 |\n| Top View (W/O RTC battery) | 105.37 |\n| Top View (W/O RTC battery) | 118.77 |\n| Top View (W/O RTC battery) | 130.92 |\n| Top View (W/O RTC battery) | 140.90 |\n| Top View (W/O RTC battery) | 152.75 |\n| Top View (W/O RTC battery) | 160.02 |\n| Top View (W/O RTC battery) | 33.26 |\n| Top View (W/O RTC battery) | 32.29 |\n| Top View (W/O RTC battery) | 0.47 |\n| Top View (W/O RTC battery) | 1.73 |](.amitx-al-i-50-1j087-1000-10/0121aeeab73a05826c981881843caa6c0c5e11884163a73812ea3ae8e3bf38ef.jpg)

Side View (W/O RTC battery)
![18.30\n1.60](.amitx-al-i-50-1j087-1000-10/aa6694d6791dc4b32652646951be0b13770814b641e41c5e50a7b29802578649.jpg)

Dimensions: mm
Figure 5: AmITX-AL-I Mechanical Dimensions

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# 4. Connectors and Jumpers

See 3.1 Connector Locations on page 11 for connector locations.

# 4.1. Rear IO Connectors

# 4.1.1. DC Power Inlet

The AmITX-AL-I supports a screw-type external 12V DC-in power connector. Maximum current draw is 10A.

Note: Either the DC Power Inlet or the internal ATX Power Connector (ATX\_PWR) must be used to supply the motherboard with +12V ±5%.

![Close-up of a metallic threaded connector mounted on a green circuit board (no visible text or symbols)](.amitx-al-i-50-1j087-1000-10/d7ae2c45b675ca0ab9cdeb605f17ded7286d6decd86f79913398d4274faa182e.jpg)

![Close-up of a mechanical component with concentric circular features and a metallic housing (no visible text or symbols)](.amitx-al-i-50-1j087-1000-10/0b21042da5887aa51dbeabcb575c7113f4cae2a187c74e89fd22086fbf976e5d.jpg)

![JACK1\nVCC\n1\n3\nGND2\n2\nGND1\nPWR-JACK_P1](.amitx-al-i-50-1j087-1000-10/9f624078596aafdb638d122927c37de92277823fcd1027ddad860ec498fde86e.jpg)

![12.5±0.3\n3.0\n+0.1\nØ5.6-0\n+0.2\n2.6-0\n0.25t](.amitx-al-i-50-1j087-1000-10/cf3feaffdbb0eeb12a78d11c0da6df9e4098e855df39cfa7a72c1a12e9ae2ee8.jpg)

![The image displays a standard yellow triangular warning sign with a black border. Inside the triangle is a large, black exclamation point centered vertically and horizontally. The sign is set against a white background, flanked by thick black vertical bars on the left and right sides.](.amitx-al-i-50-1j087-1000-10/1e87019d4a5771408bccbd7f0183c682224d783b74c10eadd77709c0d11f8a37.jpg)

# Caution:

Hot-plugging the power supply is not supported. Doing so may damage the board.

Only connect ONE power supply to the board. Connecting power to both the 12V DC inlet and the internal ATX Power Connector, may damage the board.

# 4.1.2. DisplayPort

DisplayPort v1.2 specification ports up to 4096x2160 @ 24Hz (2x DisplayPort by build option, in place of HDMI)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>CN_DP0_P</td><td>2</td><td>Ground</td></tr><tr><td>3</td><td>CN_DP0_N</td><td>4</td><td>CN_DP1_P</td></tr><tr><td>5</td><td>Ground</td><td>6</td><td>CN_DP1_N</td></tr><tr><td>7</td><td>CN_DP2_P</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>CN_DP2_N</td><td>10</td><td>CN_DP3_P</td></tr><tr><td>11</td><td>Ground</td><td>12</td><td>CN_DP3_N</td></tr><tr><td>13</td><td>DDC_AUX_SEL</td><td>14</td><td>CN_CEC</td></tr><tr><td>15</td><td>CN_AUX_P</td><td>16</td><td>Ground</td></tr><tr><td>17</td><td>CN_AUX_N</td><td>18</td><td>DDP_HPD</td></tr><tr><td>19</td><td>Ground</td><td>20</td><td>P3V3</td></tr></table>

![This image displays a black and white technical line drawing of a rectangular connector housing. Inside the housing is a central, U-shaped channel running vertically. Along the inner vertical walls of this channel are rows of small rectangular contact pads. The numbers '1' and '2' are positioned near the top of the channel, while '19' and '20' are positioned near the bottom. Small rectangular notches line the inner walls of the channel, and small cutouts are visible on the outer left and right sides of the frame.](.amitx-al-i-50-1j087-1000-10/5337174811d5421464a2c9a15b43d4eb7f0b0426135df53a8db23ac20b4ff5ac.jpg)

# 4.1.3. HDMI Connector

Supports HDMI 1.4b, maximum resolution: 3840x2160 @ 30Hz (co-lay with DP)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2+</td><td>2</td><td>TMDS Data2 Shield</td></tr><tr><td>3</td><td>TMDS Data2-</td><td>4</td><td>TMDS Data1+</td></tr><tr><td>5</td><td>TMDS Data1Shield</td><td>6</td><td>TMDS Data1-</td></tr><tr><td>7</td><td>TMDS Data0+</td><td>8</td><td>TMDS Data0 Shield</td></tr><tr><td>9</td><td>TMDS Data0-</td><td>10</td><td>TMDS Clock+</td></tr><tr><td>11</td><td>TMDS ClockShield</td><td>12</td><td>TMDS Clock-</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>SCL</td><td>16</td><td>SDA</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>+5 V Power</td></tr><tr><td>19</td><td>Hot Plug Detect</td><td></td><td></td></tr></table>

![This image displays a schematic diagram of a rectangular connector housing with two rows of square pin holes. Small square notches are visible along the bottom edge. Numbers label specific pin locations:\n\n*   **Top Right:** The far right pin is labeled **1**, and the one to its left is labeled **3**.\n*   **Bottom Right:** The far right pin is labeled **2**, and the one to its left is labeled **4**.\n*   **Top Left:** The far left pin is labeled **19**, and the one to its right is labeled **17**.\n*   **Bottom Left:** The far left pin is labeled **18**.](.amitx-al-i-50-1j087-1000-10/c5abfcd7d60fcadad063133b8c69edd252ff4fbfef65fe472190f06fb3c0feb6.jpg)

# 4.1.4. Ethernet Connectors (LAN1, LAN2)

Intel® i211AT (MAC/PHY) Ethernet controller (Intel® i210 is build option for extreme temperature operating range support)

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_MDI0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_MDI0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_MDI1+</td></tr><tr><td>4</td><td>--</td><td>LAN_MDI1-</td></tr><tr><td>5</td><td>--</td><td>LAN_MDI2+</td></tr><tr><td>6</td><td>RX-</td><td>LAN_MDI2-</td></tr><tr><td>7</td><td>--</td><td>LAN_MDI3+</td></tr><tr><td>8</td><td>--</td><td>LAN_MDI3-</td></tr></table>

![The image displays a schematic diagram of an RJ45 connector. At the top, the text 'LED1' is on the left and 'LED2' is on the right. Below the connector outline at the bottom, the number '8' is on the left and the number '1' is on the right. Thin lines connect the bottom edge of the central connector shape to the numbers '8' and '1' respectively.](.amitx-al-i-50-1j087-1000-10/595362ff2c001b7fb2b12b1c909c098facacaa7d1aba320477a8bce973cec28b.jpg)

<table><tr><td colspan="2">LED1 (Speed)</td><td colspan="2">LED2 (Link/Activity)</td></tr><tr><td>Status</td><td>Description</td><td>Status</td><td>Description</td></tr><tr><td>Off</td><td>10 Mb connection</td><td>Off</td><td>No Link</td></tr><tr><td>Green</td><td>100 Mb connection</td><td>Green</td><td>Linked</td></tr><tr><td>Orange</td><td>1 Gb connection</td><td>Blinking</td><td>Data Activity</td></tr></table>

# 4.1.5. USB 3.0 Connectors (USB1-4)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.amitx-al-i-50-1j087-1000-10/9a4c59b8c5c5c83253dd20af03083c98c51b66eb4660884a9ea2f1ec72e4cbf2.jpg)

# 4.1.6. Audio Connectors (Line-out [green], Mic-in [pink])

Audio Codec: Realtek ALC888S

<table><tr><td>Jack</td><td>Contact</td><td>Signal</td></tr><tr><td rowspan="3">Line-out</td><td>Tip</td><td>FRONT-OUT-L</td></tr><tr><td>Ring</td><td>FRONT-OUT-R</td></tr><tr><td>Sleeve</td><td>GND</td></tr><tr><td rowspan="3">Mic-in</td><td>Tip</td><td>MIC1-L</td></tr><tr><td>Ring</td><td>MIC1-R</td></tr><tr><td>Sleeve</td><td>GND</td></tr></table>

Line Out (JACK - D, Green)

![The image displays a bright green ring centered on a white square background, which is enclosed by a thick black border.](.amitx-al-i-50-1j087-1000-10/5398ef778791afe8615971eb08507ea09def3138a0f5b8e9a2dbce8f2b3f277c.jpg)

![A thick black rectangular frame surrounds a white background. Centered inside is a solid, bright pink ring.](.amitx-al-i-50-1j087-1000-10/c5747b5ea073c6885c3fac19f034a490919ad78f9063e1be97894f78fbd4d1e4.jpg)

MIC In (JACK - B, Pink)

Note: Shared with onboard Audio Header; un-amplified codec output.

# 4.2. Internal Connectors

# 4.2.1. ATX Power Connector 4-pin (ATX\_PWR1)

AmITX-AL-I supports a proprietary internal ATX Power Connector (4-pin).

Note: Either the DC Power Inlet or the internal ATX Power Connector (4-pin) must be used to supply the motherboard with +12V ±5%.

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>+12V DC</td></tr><tr><td>4</td><td>+12V DC</td></tr></table>

![The image displays a schematic diagram featuring a central square divided into four quadrants. Inside each quadrant is a blue circle. The top-left and bottom-right quadrants are framed by squares, while the top-right and bottom-left quadrants are framed by hexagons. Two vertical blue lines extend from the top center of the central box. Red horizontal lines connect numbers to the quadrants: on the left side, the number '4' aligns with the top-left quadrant and '2' with the bottom-left; on the right side, the number '3' aligns with the top-right quadrant and '1' with the bottom-right.](.amitx-al-i-50-1j087-1000-10/f78c1f01d0a84b0c144596d8d9e5765ace468b1443020e6993c9cfc856e9049c.jpg)

![The image displays a standard warning sign. At the top is a yellow triangle with a black border containing a black exclamation point. Below the triangle, the word 'CAUTION' appears in large, black, bold capital letters on a white background.](.amitx-al-i-50-1j087-1000-10/fd6da9e40a1f8e6cf43de8942fa7254c186d710af0a16ce7b22a97933ac02cba.jpg)

Only connect ONE power supply to the board. Connecting power to both the 12V DC-inlet and the internal ATX Power Connector may damage the board.

# 4.2.2. SATA Connectors (SATA1, SATA2, CN22-23)

Two SATA ports are available on the AmITX-AL-I and support SATA Gen3 (6.0/3.0/1.5Gb/s).

Note: If mSATA is installed, SATA1 is disabled. See 4.3.3 SATA1/mSATA Select (JP11).

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TXP</td></tr><tr><td>3</td><td>TXN</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RXN</td></tr><tr><td>6</td><td>RXP</td></tr><tr><td>7</td><td>GND</td></tr></table>

![The image displays a black-and-white technical line drawing of a rectangular component. Inside the main rectangular outline is a narrower vertical slot. Running centrally through this slot is a thick vertical dashed line that passes through a column of small, square shapes. To the right of the object, the number '1' is positioned near the top, and the number '7' is positioned near the bottom.](.amitx-al-i-50-1j087-1000-10/a1ddecd40f4a05d74de231ed68c342005a22b8256d1f283adab33a0b82af2f15.jpg)

# 4.2.3. SATA Power Connector (ST\_PWR, CN24)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>12V</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>5V</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>3.3V</td></tr></table>

![The image is a black and white line drawing of an electronic component, likely an integrated circuit. At the top, the numbers **5 4 3 2 1** are written horizontally. Below the numbers is a large rectangle with a smaller inner rectangle drawn inside it. Within the inner rectangle are five small squares arranged in a horizontal row. Vertical lines extend downward from the bottom edge of the component, representing pins.](.amitx-al-i-50-1j087-1000-10/5a7271a5a531b728a630e942e9ce334cd6a57acf544bce7743716e55ea97bddf.jpg)

SATA Power Cable: ADLINK Part. No.: 30-20875-0000 (length 200 mm)

![Based on the provided image, here is an accurate and concise description of the flowchart and block diagram:\n\n**Labeled Blocks and Connections:**\n\n1.  **Left Block:** On the far left, there is a connector block. An arrow points to the left away from this block, labeled **'HDD/SSD Power'**.\n2.  **Top Right Block:** A connector block is positioned at the top right. Multiple parallel lines connect the left block to this block. To the right of this block is an arrow pointing right, labeled **'HDD/SSD Power'**.\n3.  **Bottom Right Block:** A smaller connector block is positioned below the top right block. Several parallel lines connect the left block to this block. To the right of this block is an arrow pointing right, labeled **'Motherboard SATA Power Connector'**.\n\n**Summary of Flow:**\nThe diagram shows a central connection point on the left branching out via wiring to two separate destinations on the right (the top right connector and the bottom right connector).](.amitx-al-i-50-1j087-1000-10/14d0c5356b2bb9fe601527662cbb5d9e28329117da48db90b838f846fe25fedb.jpg)

# 4.2.4. USB 2.0 Header (CN17)

5V/SB5V: 5V is supplied for external devices. SB5V is supplied during power down to allow wakeup on USB device activity during S3\~S4 state.

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>P5V_USB2_4</td><td>2</td><td>P5V_USB2_5</td></tr><tr><td>3</td><td>USB2_HUB4_N</td><td>4</td><td>USB2_HUB5_N</td></tr><tr><td>5</td><td>USB2_HUB4_P</td><td>6</td><td>USB2_HUB5_P</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>KEY</td><td>10</td><td>GND</td></tr></table>

![1\n2\n10](.amitx-al-i-50-1j087-1000-10/245a91bd6756b0341056717c31fcb558c6f5d168fb45208e7c34c98eeedb6263.jpg)

# USB Cable (optional):

USB 2.0 Header to 2x Female Type-A Cable (length 200mm), P/N: 30-20874-1000

![Diagram of two connected cable connectors with a central connector (no text or symbols)](.amitx-al-i-50-1j087-1000-10/8d0f9e69619e4d8f1693bd430a78f21da3cade70929cfd5346d387911a1d5462.jpg)

# 4.2.5. PS/2 Keyboard and Mouse Connector (CN19)

6 pin 2.0 pitch standard wafer connector. No support for PS/2 KB/MS wake function

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>MSCLK</td></tr><tr><td>2</td><td>V5S_S3</td></tr><tr><td>3</td><td>MSDATA</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>KBDATA</td></tr><tr><td>6</td><td>KBCLK</td></tr></table>

![The image displays a schematic line drawing of a rectangular connector or socket. Inside a large rectangular outline, there are two columns of small black-outlined squares representing contact points or pins. There are six rows of contacts, with six squares in the left column and six in the right column. On the right side of the connector, the numbers 1, 2, 3, 4, 5, and 6 are listed vertically in black text, aligned with the corresponding rows of contacts.](.amitx-al-i-50-1j087-1000-10/ad6a6a90db6c790a3be6817f2ced3cb0bbf19c2766af7fcabc1c354d93896c7c.jpg)

# KB/MS Cable (optional):

PS/2 KB/MS Cable (length 400mm), P/N: 30-20873-0000

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Blocks:**\n*   **Left Side:** A multi-pin connector block attached to a solid black rectangular block.\n*   **Middle:** Two small rectangular boxes. The top one is labeled **'K3'** and the bottom one is labeled **'MS'**.\n*   **Right Side:** Two identical valve or actuator components, positioned vertically aligned.\n\n**Connections:**\n*   Two lines diverge from the black block and connect to the box labeled **'K3'**. From this box, two lines extend to the top valve component.\n*   Two lines diverge from the black block and connect to the box labeled **'MS'**. From this box, two lines extend to the bottom valve component.](.amitx-al-i-50-1j087-1000-10/485d91a037d8e60a5c243dec404fc31c4fdcf6a684dd1d9050bda6282a075cf4.jpg)

# 4.2.6. Internal Audio Connector (CN16)

2x16-pin 2.0 pitch standard wafer connector.

Note: Signals shared with Audio Connector on Rear I/O.

<table><tr><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td></tr><tr><td>LFE_R</td><td>1</td><td>2</td><td>CEN_L</td></tr><tr><td>AGND_AU</td><td>3</td><td>4</td><td>AGND_AU</td></tr><tr><td>LOUT_L_CN</td><td>5</td><td>6</td><td>LOUT_R_CN</td></tr><tr><td>AGND_AU</td><td>7</td><td>8</td><td>AGND_AU</td></tr><tr><td>SURR_LO</td><td>9</td><td>10</td><td>SURR_RO</td></tr><tr><td>SIDE_L</td><td>11</td><td>12</td><td>SIDE_R</td></tr><tr><td>AGND_AU</td><td>13</td><td>14</td><td>AGND_AU</td></tr><tr><td>MICIN_L_CN</td><td>15</td><td>16</td><td>MICIN_R_CN</td></tr><tr><td>AGND_AU</td><td>17</td><td>18</td><td>AGND_AU</td></tr><tr><td>LIN_L</td><td>19</td><td>20</td><td>LIN_R</td></tr><tr><td>MUTE</td><td>21</td><td>22</td><td>AGND_AU</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>NC</td></tr><tr><td>SPDO</td><td>25</td><td>26</td><td>GND</td></tr><tr><td>LINE1_JD</td><td>27</td><td>28</td><td>CEN_JD</td></tr><tr><td>SURR_JD</td><td>29</td><td>30</td><td>FRONT_JD</td></tr><tr><td>MIC1_JD</td><td>31</td><td>32</td><td>SIDESURR_JD</td></tr></table>

![JACK-G LFE_R 1 CN16 2 CEN_L JACK-G\nJACK-D LOUT_L_CN 3 4\nJACK-A SURR_LO 5 6 LOUT_R_CN JACK-D\nJACK-H SIDE_L 7 8\nJACK-B MICIN_L_CN 9 10 SURR_RO JACK-A\nJACK-B 11 12 SIDE_R JACK-H\nJACK-C LIN_L 13 14\nJACK-C MUTE 15 16 MICIN_R_CN JACK-B\nSPDO 17 18 LIN_R JACK-C\nLINE1_JD 19 20\nSURR_JD 21 22\nMIC1_JD 23 24 NC\nAGND_AU AGND_AU CEN_JD FRONT_JD SIDESURR_JD](.amitx-al-i-50-1j087-1000-10/14d52040211e3cc2b65b39e2dce19795f08b30926a97616ac3f2cfe7cc9ad778.jpg)

# 4.2.7. CPU Fan and System Fan Connectors (CPU: CN36, SYS: CN37)

Pin 3 and 4 are connected (monitored and managed) by SEMA controller.

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>Fan Power (+12V)</td></tr><tr><td>3</td><td>Fan Sense</td></tr><tr><td>4</td><td>Fan Speed Control</td></tr></table>

4
![This is a black-and-white line drawing. It features a top section composed of a horizontal rectangle divided into a smaller vertical rectangle on the left and a larger, U-shaped area on the right. Below this is a long horizontal rectangle containing four small squares arranged in a single row. A thick, solid black bar runs along the very bottom edge of the image.](.amitx-al-i-50-1j087-1000-10/6cea9c38103110716900e6e3cb41516caf4d33c2a59a4a958b4924e46f75f02a.jpg)
1

# 4.2.8. Serial COM Port Connectors (CN29-CN34)

Four internal Serial Ports (COM1-6)

<table><tr><td>Serial Port</td><td>Functions</td></tr><tr><td>COM1</td><td>Supports RS-232/422/485, 0V5V/12V power support by jumper selectionSWS1M: Switch for mode selection of COM1 (default RS-232).</td></tr><tr><td>COM2</td><td>Supports RS-232/422/485, 0V/5V/12V power support by jumper selectionSWS2M: Switch for mode selection of COM2 (default RS-232).</td></tr><tr><td>COM3</td><td>Supports RS-232</td></tr><tr><td>COM4</td><td>Supports RS-232</td></tr><tr><td>COM5</td><td>Supports RS-232</td></tr><tr><td>COM6</td><td>Supports RS-232</td></tr></table>

![The image displays a schematic line drawing of a rectangular connector housing. The outline is a thick black rectangle with two vertical notches or gaps on the left side. Inside the rectangle, there are ten small squares arranged in two vertical columns of five squares each. The numbers '1' and '2' are positioned outside the top left and top right corners respectively, while the numbers '9' and '10' are positioned outside the bottom left and bottom right corners respectively.](.amitx-al-i-50-1j087-1000-10/1d9bda63e5bf3cc9139e384f3b513660940682b52120edb5d5b855d6bb379580.jpg)

RS-232 (COM1-6)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>DCD</td><td>2</td><td>DSR</td></tr><tr><td>3</td><td>RxD</td><td>4</td><td>RTS</td></tr><tr><td>5</td><td>TxD</td><td>6</td><td>CTS</td></tr><tr><td>7</td><td>DTR</td><td>8</td><td>RI</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

RS-422 (COM1-2 only)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>Tx-</td><td>2</td><td>—</td></tr><tr><td>3</td><td>Tx+</td><td>4</td><td>—</td></tr><tr><td>5</td><td>Rx+</td><td>6</td><td>—</td></tr><tr><td>7</td><td>Rx-</td><td>8</td><td>—</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

RS-485 (COM1-2 only)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>Tx/Rx-</td><td>2</td><td></td></tr><tr><td>3</td><td>Tx/Rx+</td><td>4</td><td>—</td></tr><tr><td>5</td><td>—</td><td>6</td><td>—</td></tr><tr><td>7</td><td>—</td><td>8</td><td>—</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

RS-232/422/485 Selection (COM1-2 only)

<table><tr><td colspan="4">SWS1M/SWS2M (RS-232/422/485 Mode Select)</td></tr><tr><td></td><td>RS-232 (default)</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td></tr></table>

COM1 Power Selection (JP7, JP8)

<table><tr><td colspan="2">JP7 COM1 PWR</td></tr><tr><td>1-2</td><td>+12V</td></tr><tr><td>3-4</td><td>+5V</td></tr></table>

<table><tr><td colspan="2">JP8 COM1 PWR</td></tr><tr><td>1-2</td><td>GND</td></tr><tr><td>3-4</td><td>RI (default)</td></tr></table>

COM2 Power Selection (JP9, JP10)

<table><tr><td colspan="2">JP9 COM2 PWR</td></tr><tr><td>1-2</td><td>+12V</td></tr><tr><td>3-4</td><td>+5V</td></tr></table>

<table><tr><td colspan="2">JP10 COM2 PWR</td></tr><tr><td>1-2</td><td>GND</td></tr><tr><td>3-4</td><td>RI (default)</td></tr></table>

![COM1_RI/12V/5V/0V\n4 3\n2 1\nJP7 PH_4_S2.0mm\n4 3\n2 1\nJP8 PH_4_S2.0mm\nCOM1_RI-L_CN\nC1223\n0.1uF_25V\n(50) COM2_RI/12V/5V/0V\n4 3\n2 1\nJP9 PH_4_S2.0mm\nC1222\n0.1uF_25V\nJP10\n4 3\n2 1\nCOM2_RI-L_CN (50)\nMINI JUMP-2P-2-H3D5 JP10 PH_4_S2.0mm](.amitx-al-i-50-1j087-1000-10/4046487bd04cf0f36417d61642da217be37b00e7a1c0c446fadfe2b3feb352d6.jpg)

# COM Cable (optional):

COM Port Cable (length 250mm), P/N: 30-20876-0000

![Technical line drawing of a USB connector with pin numbering and cable routing (no text or symbols)](.amitx-al-i-50-1j087-1000-10/7785b0e527edf2599f99e9b4cc307d25baab09230e1ea07f91c779b82948aa2b.jpg)

# 4.2.9. LVDS Connector (CN13)

FFC Connector: Female, 30pin, 1mm pitch. (JAE, FI-X30SSLA-HF) Supports non-EDID type LCD panels.

<table><tr><td>Signal</td><td>Description</td></tr><tr><td>LVDS A0..A3</td><td>LVDS A Channel data</td></tr><tr><td>LVDS ACLK</td><td>LVDS A Channel clock</td></tr><tr><td>LVDS B0..B3</td><td>LVDS B Channel data</td></tr><tr><td>LVDS BCLK</td><td>LVDS B Channel clock</td></tr><tr><td>VDD ENABLE</td><td>Output Display Enable.</td></tr><tr><td>LCDVCC</td><td>VCC supply to the display. Power-on/off sequencing depending on selected display type in the BIOS Setup. Switchable by jumper either 3.3V (default) ,5V or 12V Maximum load is 1A total for both voltages.</td></tr><tr><td>DDC CLK</td><td>DDC Channel Clock</td></tr><tr><td>DDC DAT</td><td>DDC Channel Data</td></tr></table>

<table><tr><td>Note</td><td>Type</td><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td><td>Type</td><td>Note</td></tr><tr><td>Max. 0.5A</td><td>PWR</td><td>POWER GND</td><td>1</td><td>17</td><td>LVDS B1+</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS A0-</td><td>2</td><td>18</td><td>POWER GND</td><td>PWR</td><td>Max. 0.5A</td></tr><tr><td></td><td>LVDS</td><td>LVDS A0+</td><td>3</td><td>19</td><td>LVDS B2-</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS A1-</td><td>4</td><td>20</td><td>LVDS B2+</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS A1+</td><td>5</td><td>21</td><td>LVDS BCLK-</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS A2-</td><td>6</td><td>22</td><td>LVDS BCLK+</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS A2+</td><td>7</td><td>23</td><td>LVDS B3-</td><td>LVDS</td><td></td></tr><tr><td>Max. 0.5A</td><td>PWR</td><td>POWER GND</td><td>8</td><td>24</td><td>LVDS B3+</td><td>LVDS</td><td></td></tr><tr><td></td><td>LVDS</td><td>LVDS ACLK-</td><td>9</td><td>25</td><td>POWER GND</td><td>PWR</td><td>Max. 0.5A</td></tr><tr><td></td><td>LVDS</td><td>LVDS ACLK+</td><td>10</td><td>26</td><td>DDC DATA</td><td>OT</td><td>PU 2K2Ω, 3.3V</td></tr><tr><td></td><td>LVDS</td><td>LVDS A3-</td><td>11</td><td>27</td><td>VDD ENABLE</td><td>OT</td><td>3.3V level</td></tr><tr><td></td><td>LVDS</td><td>LVDS A3+</td><td>12</td><td>28</td><td>DDC CLK</td><td>OT</td><td>PU 2K2Ω, 3.3V</td></tr><tr><td></td><td>LVDS</td><td>LVDS B0-</td><td>13</td><td>29</td><td>EDID POWER</td><td>PWR</td><td>Max 0.5A</td></tr></table>

![CN13\n1\n2\n3\n4\n5\n6\n7\n8\n9\n10\n11\n12\n13\n14\n15\n16\n17\n18\n19\n20\n21\n22\n23\n24\n25\n26\n27\n28\n29\n30\n31\n32](.amitx-al-i-50-1j087-1000-10/e8b05a2f854e8626a6394b07a5b2294db9479eaf6eb8c2c0ce1bf2d711fae24c.jpg)

<table><tr><td>Note</td><td>Type</td><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td><td>Type</td><td>Note</td></tr><tr><td></td><td>LVDS</td><td>LVDS B0+</td><td>14</td><td>30</td><td>PANEL POWER</td><td>PWR</td><td>Max 0.5A</td></tr><tr><td>Max. 0.5A</td><td>PWR</td><td>POWER GND</td><td>15</td><td>31</td><td>PANEL POWER</td><td>PWR</td><td>Max 0.5A</td></tr><tr><td></td><td>LVDS</td><td>LVDS B1-</td><td>16</td><td>32</td><td>POWER GND</td><td>PWR</td><td>Max. 0.5A</td></tr></table>

# 4.2.10. LVDS Auxiliary Connector (CN14)

Wafer 1x10 pin: 1.25 mm pitch (MOLEX, 53261-1071)

<table><tr><td>Pin</td><td>Type</td><td>Signal</td><td>Note</td></tr><tr><td>1</td><td>OT</td><td>BKLT_EN#</td><td>3.3V level</td></tr><tr><td>2</td><td>PWR</td><td>GND</td><td>Max. 0.5A</td></tr><tr><td>3</td><td>PWR</td><td>GND</td><td>Max. 0.5A</td></tr><tr><td>4</td><td>PWR</td><td>BKLT_PWR</td><td>Max. 0.5A</td></tr><tr><td>5</td><td>PWR</td><td>BKLT_PWR</td><td>Max. 0.5A</td></tr><tr><td>6</td><td>PWR</td><td>BKLT_PWR</td><td>Max. 0.5A</td></tr><tr><td>7</td><td>PWR</td><td>BKLT_PWR</td><td>Max. 0.5A</td></tr><tr><td>8</td><td>PWR</td><td>GND</td><td>Max. 0.5A</td></tr><tr><td>9</td><td>PWR</td><td>GND</td><td>Max. 0.5A</td></tr><tr><td>10</td><td>OT</td><td>BKLT_CTL</td><td>3.3V level</td></tr></table>

![The image displays a schematic symbol for an electronic connector. At the top, the text 'CN14' appears in blue. To the left, the numbers 1 through 10 are listed vertically in black. To the right of these numbers is a rectangular symbol outlined in blue. Inside the outline, there are two columns of blue circles arranged in a grid of two columns by ten rows. The left column of circles is aligned with the numbers 1 through 10. White rectangular shapes are visible inside the blue outline, aligned with the blue circles.](.amitx-al-i-50-1j087-1000-10/2ce0dc9fc02d87810115b8942af8f30035f6dd030a70420ec9f7e3b50db27460.jpg)

<table><tr><td>Signal</td><td>Description</td></tr><tr><td>BKLT_EN#</td><td>Backlight Enable signal (active low)Optional to invert this signal to active high BKLT_EN (by jumper)</td></tr><tr><td>BKLT_PWR</td><td>Backlight Power switchable by jumper either 5V (default) or 12V. Maximum 1A per pin for both voltages</td></tr><tr><td>BKLT_CTL</td><td>Backlight control, PWM signal to implement voltage in the range 0-3.3V</td></tr></table>

See Section 4.3 Jumper and Switch Settings for Backlight Power Selection (JP2), Backlight Enable Selection (JP4), and Panel Power Selection (JP3, JP5) settings.

# 4.2.11. Front Panel Header (CN27)

2x12-pin 2.0 pitch standard wafer header

The front panel header provides USB2.0, Audio MIC-In / Line-Out, ATX power switch, Reset, HDD LED, and SUS LED (System Power LED).

<table><tr><td>Pin #</td><td>Signal</td><td>Ioh/ lol</td><td>Type</td><td>Note</td><td>Pin #</td><td>Signal</td><td>Type</td><td>Ioh/ lol</td><td>Note</td></tr><tr><td>1</td><td>USB7_5V</td><td>-</td><td>PWR</td><td></td><td>2</td><td>USB7_5V</td><td>PWR</td><td>-</td><td></td></tr><tr><td>3</td><td>USB7-</td><td>-</td><td>S</td><td></td><td>4</td><td>MIC2_JD</td><td>S</td><td>-</td><td></td></tr><tr><td>5</td><td>USB7+</td><td>-</td><td>S</td><td></td><td>6</td><td>LINE2_JD</td><td>S</td><td>-</td><td></td></tr><tr><td>7</td><td>GND</td><td>-</td><td>PWR</td><td></td><td>8</td><td>GND</td><td>PWR</td><td>-</td><td></td></tr><tr><td>9</td><td>NC</td><td>-</td><td>NC</td><td></td><td>10</td><td>LINE2-L</td><td>S</td><td>-</td><td></td></tr><tr><td>11</td><td>+5V</td><td>-</td><td>PWR</td><td></td><td>12</td><td>+5V</td><td>PWR</td><td>-</td><td></td></tr><tr><td>13</td><td>SATA_LED#</td><td></td><td>O</td><td></td><td>14</td><td>SUS_LED</td><td>O</td><td></td><td>1</td></tr><tr><td>15</td><td>GND</td><td>-</td><td>PWR</td><td></td><td>16</td><td>PWRBTN_IN#</td><td>I</td><td></td><td></td></tr><tr><td>17</td><td>RSTIN#</td><td>-</td><td>I</td><td></td><td>18</td><td>GND</td><td>PWR</td><td>-</td><td></td></tr><tr><td>19</td><td>SB3V3</td><td>-</td><td>PWR</td><td></td><td>20</td><td>LINE2-R</td><td>S</td><td>-</td><td></td></tr><tr><td>21</td><td>AGND</td><td>-</td><td>PWR</td><td></td><td>22</td><td>AGND</td><td>PWR</td><td>-</td><td></td></tr><tr><td>23</td><td>MIC2-L</td><td>-</td><td>S</td><td></td><td>24</td><td>MIC2-R</td><td>S</td><td>-</td><td></td></tr></table>

![The image displays a technical line drawing of a rectangular electronic component, likely an integrated circuit package. The number '1' is positioned to the left of the component, and the number '2' is positioned to the right. Inside the rectangle, there are two vertical columns of twelve small black squares each. Along the left and right inner edges of the rectangle, there are small rectangular notches aligned with the squares.](.amitx-al-i-50-1j087-1000-10/4d399422cc6c0f8286acfe71f3f37419b38e667f5ce65eff0490130f1ee14448.jpg)

Note 1: Connect SUS\_LED (System Power LED) to the power status indicator on the chassis front panel. The LED is on when the system is operating. The LED keeps blinking when the system is in S1/S3 sleep state. The LED is off when the system is in S4 sleep state or powered off (S5).

# 4.2.12. Front Panel Auxiliary Headers (CN6401-CN6404)

2-Pin, 2.54 pitch headers

<table><tr><td colspan="3">CN6401</td><td colspan="3">CN6402</td></tr><tr><td>Pin #</td><td>Signal</td><td>Type</td><td>Pin #</td><td>Signal</td><td>Type</td></tr><tr><td>1</td><td>PWRBTN_IN#</td><td>I</td><td>1</td><td>RSTIN#</td><td>I</td></tr><tr><td>2</td><td>GND</td><td>PWR</td><td>2</td><td>GND</td><td>PWR</td></tr></table>

<table><tr><td colspan="4">CN6403</td></tr><tr><td>Pin #</td><td>Signal</td><td>Type</td><td>PU/PD</td></tr><tr><td>1</td><td>+3V</td><td>PWR</td><td>PU 330ohm</td></tr><tr><td>2</td><td>SATA_LED#</td><td>O</td><td></td></tr><tr><td colspan="4">CN6404</td></tr><tr><td>Pin #</td><td>Signal</td><td>Type</td><td>PU/PD</td></tr><tr><td>1</td><td>SB3V3</td><td>PWR</td><td>PU 330ohm</td></tr><tr><td>2</td><td>SUS_LED</td><td>O</td><td></td></tr></table>

# 4.2.13. Feature Connector (CN28)

2x14-pin 2.0 pitch standard wafer connector

The feature connector of AmITX-AL-I provides Case Open, I2C, SMBus, and GPIO (10pin).

<table><tr><td>Signal</td><td>Description</td></tr><tr><td>TEMPS</td><td>Analogue temp sensor, connect to analog input of BMC</td></tr><tr><td>EXT_BAT</td><td>Connect to RTC power</td></tr><tr><td>CASE_OPEN#</td><td>Any time case open occurs, system will notice/show case open alert in POST during the next boot.</td></tr><tr><td>I2CC / I2CD</td><td>Connect to BMC (I2C Master)</td></tr><tr><td>I2C</td><td>SEMA</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.amitx-al-i-50-1j087-1000-10/2eb6176c812af3c277195fe98b0902eea772cb59be98d58e9ea40c2cca988aee.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pull U/D</td><td>IOH/IOL</td><td>Type</td><td>Note</td><td>Pin #</td><td>Signal</td><td>Type</td><td>IOH/IOL</td><td>Pull U/D</td><td>Note</td></tr><tr><td>1</td><td>CASE_OPEN#</td><td>PU 2M</td><td>-</td><td>I</td><td></td><td>2</td><td>SMBC</td><td>OT</td><td>/4mA</td><td>PU 10K</td><td>1</td></tr><tr><td>3</td><td>GND</td><td>-</td><td>-</td><td>PWR</td><td></td><td>4</td><td>SMBD</td><td>OT</td><td>/4mA</td><td>PU 10K</td><td>1</td></tr><tr><td>5</td><td>N/A</td><td>-</td><td></td><td></td><td>2</td><td>6</td><td>I2CC</td><td>OT</td><td>-</td><td>PU 10K</td><td>1</td></tr><tr><td>7</td><td>EXT_BAT</td><td>-</td><td></td><td>PWR</td><td></td><td>8</td><td>I2CD</td><td>OT</td><td>-</td><td>PU 10K</td><td>1</td></tr><tr><td>9</td><td>SB3V3</td><td>-</td><td>-</td><td>PWR</td><td></td><td>10</td><td>SB5V</td><td>PWR</td><td>-</td><td>-</td><td></td></tr><tr><td>11</td><td>GND</td><td>-</td><td>-</td><td>PWR</td><td></td><td>12</td><td>GND</td><td>PWR</td><td>-</td><td>-</td><td></td></tr><tr><td>13</td><td>GPIO0</td><td>-</td><td>PU10K3V3</td><td>IOT</td><td></td><td>14</td><td>GPIO1</td><td>IOT</td><td></td><td>PU10K3V3</td><td></td></tr><tr><td>15</td><td>GPIO2</td><td>-</td><td>PU10K3V3</td><td>IOT</td><td></td><td>16</td><td>GPIO3</td><td>IOT</td><td></td><td>PU10K3V3</td><td></td></tr><tr><td>17</td><td>GPIO4</td><td>-</td><td>PU10K3V3</td><td>IOT</td><td></td><td>18</td><td>GPIO5</td><td>IOT</td><td></td><td>PU10K3V3</td><td></td></tr><tr><td>19</td><td>GPIO6</td><td>-</td><td>PU10K3V3</td><td>IOT</td><td></td><td>20</td><td>GPIO7</td><td>IOT</td><td></td><td>PU10K3V3</td><td></td></tr><tr><td>21</td><td>GPIO8</td><td></td><td>PU10K3V3</td><td>IOT</td><td></td><td>22</td><td>GPIO9</td><td>IOT</td><td></td><td>PU10K3V3</td><td></td></tr><tr><td>23</td><td>GND</td><td>-</td><td></td><td>PWR</td><td></td><td>24</td><td>SUS_S3#</td><td>O</td><td>25/25mA</td><td>-</td><td></td></tr><tr><td>25</td><td>12V</td><td>-</td><td>-</td><td>PWR</td><td></td><td>26</td><td>SUS_S4#</td><td>O</td><td>25/25mA</td><td>-</td><td></td></tr><tr><td>27</td><td>PWR_OK</td><td>-</td><td>25/25mA</td><td>O</td><td></td><td>28</td><td>SUS_S5#</td><td>O</td><td>25/25mA</td><td>-</td><td></td></tr></table>

Note 1: Pull-up to +3V3Dual (+3V3 or SB3V3).
Note 2: Input to SEMA.

# 4.2.14. SPI Header (CN40)

2x6-pin 2.0 pitch standard wafer connector

<table><tr><td>Type</td><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td><td>Type</td></tr><tr><td></td><td>CLK</td><td>1</td><td>2</td><td>SB3V3</td><td>PWR</td></tr><tr><td>I</td><td>CS0#</td><td>3</td><td>4</td><td>ADDIN</td><td>IO</td></tr><tr><td>I</td><td>CS1#</td><td>5</td><td>6</td><td>NC</td><td>-</td></tr><tr><td>I</td><td>MOSI</td><td>7</td><td>8</td><td>ISOLATE</td><td>IO</td></tr><tr><td>O</td><td>MISO</td><td>9</td><td>10</td><td>GND</td><td>PWR</td></tr><tr><td>IO</td><td>SPI_IO2_#WP</td><td>11</td><td>12</td><td>SPI_IO3_#HOLD</td><td>IO</td></tr></table>

![The image displays a schematic diagram labeled with the number '1' to the left and '2' to the right. In the center is a vertical rectangular object. Inside this rectangle is a central grid composed of black squares arranged in three columns and eight rows. Flanking this central grid on the left and right sides are irregular sections featuring vertical lines and zig-zag patterns.](.amitx-al-i-50-1j087-1000-10/19f6148cae3acf55ae3f1bc8961ed8850e2fbba2e8f4c9874858687cedbef122.jpg)

<table><tr><td>Signal</td><td>Description</td></tr><tr><td>CLK</td><td>Serial Clock</td></tr><tr><td>SB3V3</td><td>3.3V Standby Voltage power line. Normally output power, but when Motherboard is turned off then the on-board SPI Flash can be 3.3V power sourced via this pin.</td></tr><tr><td>CS0#</td><td>CS0# Chip Select 0, active low.</td></tr><tr><td>ADDIN</td><td>ADDIN input signal must be NC.</td></tr><tr><td>MOSI</td><td>Master Output, Slave Input</td></tr><tr><td>ISOLATE#</td><td>The ISOLATE# input, active low, is normally NC, but must be connected to GND when loading SPI flash. Power Supply to the Motherboard must be turned off when loading SPI flash. The pull up resistor is connected via diode to 5VSB.</td></tr><tr><td>MISO</td><td>Master Input, Slave Output</td></tr><tr><td>SPI_IO2_#WP</td><td>SPI Data I/O: A bidirectional signal used to support the new Dual IO Fast Read, Quad IO Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output Fast Read mode.</td></tr><tr><td>SPI_IO3_#HOLD</td><td>SPI Data I/O: A bidirectional signal used to support the new Dual IO Fast Read, Quad IO Fast Read and Quad Output Fast Read modes. This signal is not used in Dual Output Fast Read mode.</td></tr></table>

# 4.2.15. DB40 Debug Board Connector

FPC Connector Type: FCI 59GF Flex 10042867

![Close-up of a green circuit board with a black connector pin (no visible text or symbols)](.amitx-al-i-50-1j087-1000-10/d3fe78fd988797b230a8aa4fafcff7bbc8ee634192f55fe240c706985de40263.jpg)

40

<table><tr><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td></tr><tr><td>1</td><td rowspan="7">SPI Program interface</td><td>VCC_SPI_IN</td><td>SPI Power Input from flash tool to module. HW need add MOS FET to switch SPI power for SPI ROM</td><td>21</td><td rowspan="8">BMC Program interface (cont&#x27;d)</td><td>TXD6</td><td></td></tr><tr><td>2</td><td>GND</td><td></td><td>22</td><td>RXD6</td><td></td></tr><tr><td>3</td><td>SPI_BIOS_CS0#</td><td></td><td>23</td><td>FUMD0</td><td></td></tr><tr><td>4</td><td>SPI_BIOS_CS1#</td><td></td><td>24</td><td>RESET_IN#</td><td></td></tr><tr><td>5</td><td>SPI_BIOS_MISO</td><td></td><td>25</td><td>DATA</td><td></td></tr><tr><td>6</td><td>SPI_BIOS_MOSI</td><td></td><td>26</td><td>CLK</td><td></td></tr><tr><td>7</td><td>SPI_BIOS_CLK</td><td></td><td>27</td><td>OCD0A</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>8</td><td rowspan="10">LPC Bus</td><td>3V3_LPC</td><td>System power 3.3V provide from COM module</td><td>28</td><td>OCD0B</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>9</td><td>GND</td><td></td><td>29</td><td rowspan="7">Test points</td><td>PWRBTN#</td><td></td></tr><tr><td>10</td><td>CB_RESET#</td><td>Platform Reset</td><td>30</td><td>SYS_RESET#</td><td></td></tr><tr><td>11</td><td>RST#</td><td></td><td>31</td><td>CB_RESET#</td><td></td></tr><tr><td>12</td><td>CLK33_LPC</td><td></td><td>32</td><td>CB_PWROK</td><td></td></tr><tr><td>13</td><td>LPC_FRAME#</td><td></td><td>33</td><td>SUS_S3#</td><td></td></tr><tr><td>14</td><td>LPC_AD3</td><td></td><td>34</td><td>SUS_S4#</td><td></td></tr><tr><td>15</td><td>LPC_AD2</td><td></td><td>35</td><td>SUS_S5#</td><td></td></tr><tr><td>16</td><td>LPC_AD1</td><td>always power 3.3V provide from COM module</td><td>36</td><td rowspan="4">BMC Debug signals</td><td>POSTWDT_DIS#</td><td>Connect to Jumper for Debug</td></tr><tr><td>17</td><td>LPC_AD0</td><td></td><td>37</td><td>SEL_BIOS</td><td>Connect to Jumper for Debug</td></tr><tr><td>18</td><td rowspan="3">BMC Program interface</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td><td>38</td><td>BIOS_MODE</td><td>Connect to Jumper for Debug</td></tr><tr><td>19</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td><td>39</td><td>BMC_STATUS</td><td></td></tr><tr><td>20</td><td>GND</td><td></td><td>40</td><td>Reserved</td><td></td><td></td></tr></table>

Note: The pin description on the Debug Module is the inverse of that on the motherboard.

# 4.3. Jumper and Switch Settings

![Clear CMOS (JP6)\nSATA1/m SATA Select (JP11)\nLoad BIOS Default (SW2)\nBIOS Config (BSW1)\nRS-232/422/485 Select (SWS1M, SWS2M)\nATX/AT Mode Select (JP1)\nCOM Power (JP7-JP10)\nLVDS Backlight Power Select (JP2)\nLVDS Backlight Enable (JP4)\nLVDS Panel Power Select (JP3, JP5)](.amitx-al-i-50-1j087-1000-10/73d9ee445affc19fcbec2f07fd8dd522765ba2ef3fc5a17b1e778d01264697a2.jpg)

Figure 5: Jumper and Switch Locations

# 4.3.1. ATX/AT Mode Selection (JP1)

<table><tr><td>JP1</td><td>ATX/AT Mode</td></tr><tr><td>1-2</td><td>ATX (default)</td></tr><tr><td>2-3</td><td>AT</td></tr></table>

# 4.3.2. Clear CMOS (JP6)

<table><tr><td>JP6</td><td>Clear CMOS</td></tr><tr><td>1-2</td><td>Normal (default)</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr></table>

# 4.3.3. SATA1/mSATA Selection (JP11)

<table><tr><td>JP1</td><td>SATA1/mSATA Select</td></tr><tr><td>1-2</td><td>SATA2 (default)</td></tr><tr><td>2-3</td><td>mSATA</td></tr></table>

# 4.3.4. LVDS Backlight Power Selection (JP2)

<table><tr><td>JP2</td><td>Backlight Power</td></tr><tr><td>1-2</td><td>12V</td></tr><tr><td>2-3</td><td>5V (default)</td></tr></table>

# 4.3.5. LVDS Panel Power Selection (JP3, JP5)

<table><tr><td>JP3/JP5</td><td>Panel Power</td></tr><tr><td>1-2</td><td>5V</td></tr><tr><td>2-3</td><td>3.3V (default)</td></tr><tr><td>2-5</td><td>12V</td></tr></table>

Panel Power control:

JP3 & JP5 Jumper settings

![JP3 JP5\n1 4\n2 5\n3\nSet the LVDS panel as +3.3V\nJP3 JP5\n1 4\n2 5\n3\nSet the LVDS panel as +5V\nJP3 JP5\n1 4\n2 5\n3\nSet the LVDS panel as +12V](.amitx-al-i-50-1j087-1000-10/37d1f3c05cd191b3e1907b941c29416120d227bc6edd4ee3190c022eb9d5d773.jpg)

# 4.3.6. LVDS Backlight Enable Jumper Selection (JP4)

<table><tr><td>JP4</td><td>Backlight Power</td></tr><tr><td>1-2</td><td>Active High /Convert (default)</td></tr><tr><td>2-3</td><td>Active LowNormal</td></tr></table>

# 4.3.7. Serial Port Mode Switch Setting (SWS1M, SWS2M)

RS-232/422/485 Selection (COM1-2 only)

<table><tr><td colspan="4">SWS1M (SER1 MODE SEL)</td></tr><tr><td></td><td>RS-232 (default)</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td></tr></table>

<table><tr><td colspan="4">SWS2M (SER2 MODE SEL)</td></tr><tr><td></td><td>RS-232 (default)</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td></tr></table>

# 4.3.8. Serial Port Power Selection (JP7, JP8, JP9, JP10)

COM1 Power selection (JP7, JP8)

<table><tr><td colspan="2">JP7 COM1 PWR</td></tr><tr><td>1-2</td><td>+12V</td></tr><tr><td>3-4</td><td>+5V</td></tr></table>

<table><tr><td colspan="2">JP8 COM1 PWR</td></tr><tr><td>1-2</td><td>GND</td></tr><tr><td>3-4</td><td>RI(Default)</td></tr></table>

COM2 Power selection (JP9, JP10)

<table><tr><td colspan="2">JP9 COM1 PWR</td></tr><tr><td>1-2</td><td>+12V</td></tr><tr><td>3-4</td><td>+5V</td></tr></table>

<table><tr><td colspan="2">JP10 COM1 PWR</td></tr><tr><td>1-2</td><td>GND</td></tr><tr><td>3-4</td><td>RI(Default)</td></tr></table>

![COM1_RI/12V/5V/0V\n4 3\n2 1\nJP7 PH_4_S2.0mm\n4 3 COM1_RI-L_CN\n2 1\nJP8 PH_4_S2.0mm\n(50) COM2_RI/12V/5V/0V\n4 3\n2 1\nJP9 PH_4_S2.0mm\n4 3 COM2_RI-L_CN (50)\n2 1\nJP10 PH_4_S2.0mm\nMINI JUMP-2P-2-H3D5\nP_+5V_S0_COM P_+12V_S_COM\nC1223 0.1uF_25V\nC1222 0.1uF_25V](.amitx-al-i-50-1j087-1000-10/bacb7ed030708665a747de756a43bc1b114993ec6f27e041810461507cf077d7.jpg)

# 4.3.9. BIOS Switch Setting (BSW1)

<table><tr><td colspan="3">BSW1</td></tr><tr><td></td><td>ON</td><td>OFF</td></tr><tr><td>SEL BIOS (Pos. 1-4)</td><td>Boot from SPI0 (default)</td><td>Boot from SPI1</td></tr><tr><td>BIOS MODE (Pos. 2-3)</td><td>Normal BIOS</td><td>Failsafe BIOS (default)</td></tr></table>

![The image displays a schematic diagram of a switch enclosed in a square outline. Inside the square are two horizontal rectangular bars stacked vertically; each bar is colored blue on the left half and white on the right half. To the left of the square, the numbers '1' and '2' are arranged vertically, with red lines connecting them to the box. To the right of the square, the numbers '4' and '3' are arranged vertically, also connected by red lines. The text 'ON' appears to the right of the upper bar.](.amitx-al-i-50-1j087-1000-10/fe4d87aa973c8306f160931f2f709704b3de5a236401292455e2460afb014125.jpg)

# 4.4. Onboard Connector Information

Table 2: AmITX-AL-I Onboard Connector Information

<table><tr><td rowspan="2">Connector</td><td rowspan="2">CN#</td><td colspan="2">Onboard Connector</td><td colspan="2">Mating Connector</td><td rowspan="2">ADLINK Cable</td></tr><tr><td>Manufacturer</td><td>Part No.</td><td>Manufacturer</td><td>Part No.</td></tr><tr><td>COM Port</td><td>CN29-34</td><td>JVE</td><td>23N6850-10S10B-01G-B-01</td><td>YOUNG YAK</td><td>YY-1970H-2*5P (PH2.0)</td><td>30-20876-0000 (optional)</td></tr><tr><td>ATX power</td><td>ATX_PWR1</td><td>Alex</td><td>9359-04, NATURAL</td><td>E.C.I</td><td>E.C.I 5015H-2*7P (PH4.2)</td><td>30-20872-0000 (standard)</td></tr><tr><td>PS/2 KB/MS</td><td>CN19</td><td>JVE</td><td>24W1140-06S10-01T-3.4-CS01</td><td>E.C.I</td><td>E.C.I 2020 -06P (PH2.0)</td><td>30-20873-0000 (optional)</td></tr><tr><td>USB</td><td>CN40</td><td>JVE</td><td>23N6850-10S10B-01G-B-V9-01</td><td>YOUNG YAK</td><td>YY-1970H-2*5P (PH2.0)</td><td>30-20874-1000 (optional)</td></tr><tr><td>SATA Power</td><td>CN24</td><td>JVE</td><td>24W1170-05S10-01T-3.4-CS01</td><td>JWT</td><td>A2501H02-5P (PH2.5)YY-1970H-2*5P (PH2.0)</td><td>30-20875-0000 (standard)</td></tr><tr><td>SATA</td><td>CN22-23</td><td>WIN WIN</td><td>WATM-07ABN4B3B8UW4</td><td>JWT</td><td>A3811H0-5P (PH3.81)</td><td>30-20875-0000 (standard)</td></tr><tr><td>DB-40</td><td>CN8</td><td>Molex</td><td>502790-4091</td><td>CONN-TEK</td><td>MLCO.5-40x172-02</td><td>30-30016-0000 (optional)</td></tr><tr><td>LVDS</td><td>CN13</td><td>JVE</td><td>FI-X30SSLA-HF</td><td>WELL-LIN ENTERPRISE</td><td>WL1058-HL-30P (PH1.0)</td><td></td></tr><tr><td>LVDS Auxiliary</td><td>CN14</td><td>Molex</td><td>53261-1071</td><td>WELL-LIN ENTERPRISE</td><td>WL1025-H-10P (PH1.25)</td><td></td></tr><tr><td>Feature</td><td>CN28</td><td>JVE</td><td>23N6851-28S10B-01G-2.5-GR01, BLACK</td><td>JWT</td><td>JWT A2005H00-2C*14 (PH2.0)</td><td></td></tr><tr><td>Audio</td><td>CN16</td><td>MOLEX,</td><td>87831-3220, BLACK</td><td>JWT</td><td>JWT A2005H00-2CX13P (PH2.0)</td><td></td></tr><tr><td>Front Panel</td><td>CN27</td><td>JVE</td><td>23N6851-24S10B-01G-2.5-GR01</td><td>YY</td><td>YY-1970H-2*12P (PH2.0)</td><td></td></tr><tr><td>eDP</td><td>CN15</td><td>HIROSE</td><td>DF13E-20DP-1.25V</td><td>TBD</td><td>TBD</td><td></td></tr></table>

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# 5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality.

The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented.

• Total operating hours counter. Counts the number of hours the module has been run in minutes.
• On-time minutes counter. Counts the seconds since last system start.
• Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash.
• Power cycles counter
• Boot counter. Counts the number of boot attempts.
• Watchdog Timer (Type-II). Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up.
• System Restart Cause. Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset
• Fail-safe BIOS support. In case of a boot failure, hardware signals tell external logic to boot from fail-safe BIOS.
• Flash area. 1kB Flash area for customer data
• 128 Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
• Board Identify. Vendor / Board / Serial number / Production Date
• Main-current & voltage. Monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to the SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/PD/web/PD\_detail.php?cKind=&pid=1274

# 5.1. Board Specific SEMA Functions

# 5.1.1. Voltages

The BMC of the AmITX-AL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

Table 3: SEMA Onboard Voltage Monitor

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>CPU-Vcore</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>1</td><td>GFX-Vcore</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>2</td><td>Vmem</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>3</td><td>5VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>4</td><td>VIN(12V)</td><td>(MSB&lt;&lt;8 + LSB) x 6.000 x 3.3 / 1024</td></tr><tr><td>5</td><td>5V</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>6</td><td>3.3V</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>7</td><td>3.3VSB</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>8</td><td>RTC</td><td>(MSB&lt;&lt;8 + LSB) x 3.3 / 1024</td></tr><tr><td>9</td><td>Main Current</td><td></td></tr></table>

# 5.1.2. Main Current

The BMC of the AmITX-AL implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

Main Current = (MSB\_n&lt;&lt;8 + LSB\_n) x 8.06mA

# 5.1.3. BMC Status

Table 4: SEMA BMC Status

This register shows the status of BMC controlled signals on the AmITX-AL.

&lt;table&gt;<tr><td>Status Bit</td><td>Signal</td></tr><tr><td>0</td><td>WDTOUT</td></tr><tr><td>1</td><td>LVDS_VDDEN</td></tr><tr><td>2</td><td>LVDS_BKLTEN</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>POSTWDT_DISn</td></tr><tr><td>5</td><td>SEL_BIOS</td></tr></table>

# 5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

Table 5: SEMA Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td><td>Description</td></tr><tr><td>0</td><td>NOERROR</td><td></td></tr><tr><td>2</td><td>NO_SUSCLK</td><td>No connection to SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S4_S5</td><td>No signal for SLP_S4-S5</td></tr><tr><td>4</td><td>NO_SLP_S3</td><td>No signal for SLP_S3</td></tr><tr><td>5</td><td>BIOS_FAIL</td><td>BIOS failure</td></tr><tr><td>6</td><td>RESET_FAIL</td><td>Reset failure</td></tr><tr><td>7</td><td>RESETIN_FAIL</td><td>Reset In failure</td></tr><tr><td>8</td><td>NO_CB_PWRGD</td><td>No signal for CB Power Good</td></tr><tr><td>9</td><td>CRITICAL_TEMP</td><td>Critical temperature violation</td></tr><tr><td>10</td><td>POWER_FAIL</td><td>Power failure</td></tr><tr><td>11</td><td>VOLTAGE_FAIL</td><td>Voltage failure</td></tr><tr><td>12</td><td>NO_3V3_5V_A_PG</td><td>No signal for 3V3_5V_A Power Good</td></tr><tr><td>13</td><td>NO_VNN_PG</td><td>No signal for VNN Power Good</td></tr><tr><td>14</td><td>NO_1V24_A_PG</td><td>No signal for 1V24_A Power Good</td></tr><tr><td>15</td><td>NO_VDDQ_PG</td><td>No signal for VDDQ Power Good</td></tr><tr><td>16</td><td>NO_V1P05S_PG</td><td>No signal for V1P05S Power Good</td></tr><tr><td>17</td><td>NO_SYS_GD</td><td>No signal for System Good</td></tr><tr><td>18</td><td>NO_V12</td><td>No V12 input</td></tr><tr><td>19</td><td>MEMORY_ERROR</td><td>SDRAM error</td></tr><tr><td>20</td><td>NO_P3V3_A_READY</td><td>No signal for P3V3_A_READY</td></tr></table>

# 5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

Table 6: SEMA BMC Flags

<table><tr><td>Bit</td><td>Description</td></tr><tr><td>[0 ~ 4]</td><td>Exception Code</td></tr><tr><td>[6]</td><td>0 = AT mode1 = ATX mode</td></tr><tr><td>[7]</td><td>0 = Standard BIOS1 = Fail-safe BIOS</td></tr></table>

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# 6. System Resources

# 6.1. System Memory Map

Table 7: System Memory Map

<table><tr><td>Address Range (decimal)</td><td>Address Range (hex)</td><td>Size</td><td>Description</td></tr><tr><td>(4GB-2MB)</td><td>FFE00000 – FFFFFFFF</td><td>2 MB</td><td>High BIOS Area</td></tr><tr><td>(4GB-18MB) – (4GB-17MB-1)</td><td>FEE00000 – FEEFFFFF</td><td>1 MB</td><td>MSI Interrupts</td></tr><tr><td>(4GB-20MB) – (4GB-19MB-1)</td><td>FEC00000 – FECFFFFFF</td><td>1 MB</td><td>APIC Configuration Space</td></tr><tr><td>15MB – 16MB</td><td>F00000 – FFFFFFF</td><td>1 MB</td><td>ISA Hole</td></tr><tr><td>1MB -15MB</td><td>100000 - EFFFFF</td><td>14MB</td><td>Main Memory</td></tr><tr><td>0K –1MB</td><td>00000 – FFFFFFF</td><td>1MB</td><td>DOS Compatibility Memory</td></tr></table>

# 6.2. I/O Map

Table 8: I/O Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>020-02D and 030-03D</td><td>Interrupt controller 1, 8259 equivalent</td></tr><tr><td>02E-02F</td><td>Motherboard resource</td></tr><tr><td>040-043 and 050-053</td><td>System Timer</td></tr><tr><td>04E-04F</td><td>Motherboard resource</td></tr><tr><td>060, 064</td><td>8742 equivalent (keyboard)</td></tr><tr><td>061, 063, 065, 067</td><td>NMI control and status</td></tr><tr><td>070-077</td><td>Real Time Clock Controller (bit 7 -NMI mask)</td></tr><tr><td>092</td><td>Reset (Bit 0)/ Fast Gate A20 (Bit 1)</td></tr><tr><td>0A0-0B1 and 0B4-0BD</td><td>Interrupt controller 2, 8259 equivalent</td></tr><tr><td>0B2 and 0B3</td><td>Motherboard Resource</td></tr><tr><td>2E0-2E7</td><td>Serial Port 6</td></tr><tr><td>2F0-2F7</td><td>Serial Port 5</td></tr><tr><td>2E8-2EF</td><td>Serial Port 4</td></tr><tr><td>2F8-2FF</td><td>Serial Port 2</td></tr><tr><td>3E8-3EF</td><td>Serial Port 3</td></tr><tr><td>3F8-3FF</td><td>Serial Port 1</td></tr><tr><td>378-37F</td><td>Available</td></tr><tr><td>380-3AF</td><td>Available</td></tr><tr><td>400-47F</td><td>Motherboard Resource</td></tr><tr><td>4D0</td><td>Master PIC Edge/Level Trigger register</td></tr><tr><td>4D1</td><td>Slave PIC Edge/Level Trigger register</td></tr><tr><td>0500~0A2F</td><td>Motherboard Resource</td></tr><tr><td>CF8-CFB</td><td>PCI configuration address register (32 bit I/O only)</td></tr><tr><td>CF9</td><td>Reset Control register (8 bit I/O)</td></tr><tr><td>CFC-CFF</td><td>PCI configuration data register</td></tr><tr><td>D00-FFFF</td><td>PCI Express Root Complex</td></tr><tr><td>164E-164F</td><td>MotherBoard Resource</td></tr><tr><td>D000-EFFF</td><td>PCIE Root Port</td></tr><tr><td>F000-F03F</td><td>VGA</td></tr><tr><td>F040-F05F</td><td>SMBus controller</td></tr><tr><td>F060-F097</td><td>SATA controller</td></tr></table>

# 6.3. Interrupt Request (IRQ) Lines

# 6.3.1. IRQ Lines PIC Mode

Table 9: IRQ Lines PIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port3 (COM3)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>Serial Port5 (COM5)</td><td>IRQ6 via SERIRQ / PIRQ</td><td>No</td></tr><tr><td>7</td><td>Serial Port4 (COM4)</td><td>IRQ7 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>10</td><td>Serial Port6 (COM6)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>11</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Intel Serio IO GPIO Host Controller</td><td>N/A</td><td>Note (1)</td></tr></table>

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

# 6.3.2. IRQ Lines APIC Mode

Table 10: IRQ Lines APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>N/A</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port3 (COM3)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>Serial Port5 (COM5)</td><td>IRQ6 via SERIRQ / PIRQ</td><td>No</td></tr><tr><td>7</td><td>Serial Port4 (COM4)</td><td>IRQ7 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>Generic</td><td>N/A</td><td>Note (1)</td></tr><tr><td>10</td><td>Serial Port6 (COM6)</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>11</td><td>N/A</td><td>IRQ11 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Intel Serial IO GPIO Host Controller</td><td>N/A</td><td>Note (1)</td></tr><tr><td>15</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>25</td><td>High Definition Audio Controller</td><td>N/A</td><td></td></tr><tr><td>39</td><td>Intel SD Host Controller</td><td>N/A</td><td></td></tr><tr><td>54-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Note (1)</td></tr></table>

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

# 6.4. PCI Configuration Space Map

Table 11: PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel VGA Controller</td></tr><tr><td>00h</td><td>0Eh</td><td>00h</td><td>Internal</td><td>Intel HD Audio Device</td></tr><tr><td>00h</td><td>0Fh</td><td>00h</td><td>Internal</td><td>Intel Corporation Communication Device</td></tr><tr><td>00h</td><td>12h</td><td>00h</td><td>Internal</td><td>Intel SATA Controller</td></tr><tr><td>00h</td><td>13h</td><td>00h</td><td>Internal</td><td>Intel PCIE Root Port 1</td></tr><tr><td>00h</td><td>13h</td><td>01h</td><td>Internal</td><td>Intel PCIE Root Port 2</td></tr><tr><td>00h</td><td>13h</td><td>02h</td><td>Internal</td><td>Intel PCIE Root Port 3</td></tr><tr><td>00h</td><td>13h</td><td>03h</td><td>Internal</td><td>Intel PCIE Root Port 4</td></tr><tr><td>00h</td><td>15h</td><td>00h</td><td>Internal</td><td>Intel USB Controller</td></tr><tr><td>00h</td><td>1Bh</td><td>02h</td><td>Internal</td><td>Intel SD Card Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel ISA Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>01h</td><td>Internal</td><td>Intel SMBUS Controller</td></tr><tr><td>02h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller</td></tr><tr><td>03h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet Controller</td></tr></table>

Note (1): The bus number will be changed if the PEG/PCIE port has device.

# 6.5. PCI Interrupt Routing Map

Table 12: PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>Audio Controller</td><td>xHCI Controller</td><td>TXE Controller #1</td><td>PCIE Port 3</td><td>PCIE Port 4</td><td>PCIE Port 5</td></tr><tr><td>Int0</td><td>INTA:25</td><td>INTA:None</td><td>INTA:None</td><td>INTA:22</td><td>INTA:23</td><td>INTA:20</td></tr><tr><td>Int1</td><td></td><td></td><td></td><td>INTB:23</td><td>INTB:20</td><td>INTB:21</td></tr><tr><td>Int2</td><td></td><td></td><td></td><td>INTC:20</td><td>INTC:21</td><td>INTC:22</td></tr><tr><td>Int3</td><td></td><td></td><td></td><td>INTD:21</td><td>INTD:22</td><td>INTD:23</td></tr></table>

<table><tr><td>INT Line</td><td>PCIE Port 6</td><td>LPC Controller</td><td>SATA Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTA:21</td><td>INTA:None</td><td>INTA:None</td><td>INTB:None</td></tr><tr><td>Int1</td><td>INTB:22</td><td></td><td></td><td></td></tr><tr><td>Int2</td><td>INTC:23</td><td></td><td></td><td></td></tr><tr><td>Int3</td><td>INTD:20</td><td></td><td></td><td></td></tr></table>

# 6.6. SMBus Slave Address

Table 13: SMBus Slave Address

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DIMM A</td><td>A0h</td></tr><tr><td>DIMM B</td><td>A4h</td></tr><tr><td>BMC</td><td>58h</td></tr><tr><td>Extend GPIO</td><td>40h</td></tr></table>

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# 7. BIOS Setup

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information System Information Board Management ▶ System Date System Time</td><td>CPUConfiguration ▶ GraphicsConfiguration ▶ Power Management ▶ System Management ▶ Thermal Management ▶ Watchdog Timer ▶ CSM Configuration ▶ IT8783 Super IO Configuration ▶ Serial Console Redirection ▶ USB ▶ Network ▶ Miscellaneous ▶ Trusted Computing ▶ SDIO Configuration ▶</td><td>North Bridge ▶ South Bridge ▶ Uncore Configuration ▶ South Cluster Configuration ▶</td><td>Setup Administrator Password User Password Secure Boot menu ▶ HDD Security Configuration ▶</td><td>Boot Configuration ▶</td><td>Save Options ▶ Default Options ▶ Boot Override ▶</td></tr></table>

# Notes:

► indicates a submenu

Gray text indicates info only

# 7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.

7.2.1. BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>Vendor.</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Project BIOS Version</td></tr><tr><td>Build Data and Time</td><td>Info only</td><td>Data and Time</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Intel MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Intel GOP Version</td></tr><tr><td>TXE FW Version</td><td>Info only</td><td>Intel TXE FW Version</td></tr><tr><td>BIOS Boot Source</td><td>Info only</td><td>Display Platform Current Boot BIOS</td></tr></table>

7.2.2. System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Project Name.</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Project Board Version.</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>CPU Brand String Information.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>CPU Frequency Information.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Total memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Memory Frequency</td></tr><tr><td>SOC SKU</td><td>Info only</td><td>SOC SKU Information</td></tr></table>

# 7.2.3. Board Information

7.2.3.1. Board Information > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Number</td><td>Info only</td><td>Display System Serial Number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display Manufacturing Date</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display Last Repair Date</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display MAC ID</td></tr></table>

7.2.3.2. Board Information > Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The boot counter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.2.4. System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Set the Date. Use Tab to switch between Date elements.</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Set the Time. Use Tab to switch between Time elements.</td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Configuration</td><td colspan="2">Info only</td></tr><tr><td>Socket 0 CPU Information</td><td>Submenu</td><td>Display socket specific CPU Information</td></tr><tr><td>Speed</td><td>Info only</td><td>Display CPU Speed Frequency</td></tr><tr><td>64-bit</td><td>Info only</td><td>Display CPU 64-bit supported</td></tr><tr><td>CPU Power Management</td><td>Submenu</td><td>CPU Power Management options</td></tr><tr><td>Active Processor Cores</td><td>DisabledEnabled</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Intel Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>Enable/Disable CPU VT-d</td></tr><tr><td>Bi-direction PROCHOT</td><td>DisabledEnabled</td><td>When a processor thermal sensor trips (either core), the PROCHOT# will be driven. If bi-direction is enabled, external agents can drive PROCHOT# to throttle the processor.</td></tr><tr><td>Thermal Monitor</td><td>DisabledEnabled</td><td>Enable/Disable Thermal Monitor.</td></tr><tr><td>Monitor Mwait</td><td>DisabledEnabledAuto</td><td>Enable/Disable Monitor Mwait</td></tr><tr><td>P-STATE Coordination</td><td>HW_ALLSW_ALLSW_ONLY</td><td>Change P-State Coordination type.</td></tr><tr><td>DTS</td><td>DisabledEnabled</td><td>Enabled/Disabled Digital Thermal Sensor.</td></tr></table>

7.3.1.1. CPU Configuration > Socket 0 CPU Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Socket 0 CPU Information</td><td colspan="2">Info only</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU Signature</td></tr><tr><td>Microcode Patch</td><td>Info only</td><td>Display Microcode Patch</td></tr><tr><td>Max CPU Speed</td><td>Info only</td><td>Display Max CPU Speed</td></tr><tr><td>Min CPU Speed</td><td>Info only</td><td>Display Min CPU Speed</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display Processor Cores numbers</td></tr><tr><td>Intel HT Technology</td><td>Info only</td><td>Display Not Supported</td></tr><tr><td>Intel VT-x Technology</td><td>Info only</td><td>Display supported</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display L1 Data Cache</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display L1 Code Cache</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display L2 Cache</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display L3 Cache</td></tr></table>

7.3.1.2. CPU Configuration > CPU Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Power Management Configuration</td><td colspan="2">Info only</td></tr><tr><td>EIST</td><td>DisabledEnabled</td><td>Enable/Disable Intel SpeedStep</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Turbo Mode</td></tr><tr><td>Boot performance mode</td><td>Max PerformanceMax Battery</td><td>Select the performance state that the BIOS will set before OS handoff.</td></tr><tr><td>C-States</td><td>DisabledEnabled</td><td>Enable/Disable C States</td></tr><tr><td>Enhanced C-States</td><td>DisabledEnabled</td><td>Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>Max Package C State</td><td>PC2PC1C0</td><td>Controls the Max Package C State that the processor will Support.</td></tr><tr><td>Max Core C State</td><td>Fused ValueCore C10Core C9Core C8Core C7Core C6Core C1Unlimited</td><td>This option controls the Max Core C State that cores will support.</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Auto Un-Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Un-Demotion</td></tr><tr><td>Power Limit 1 Enable</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 1</td></tr><tr><td>Power Limit 1</td><td>Info Only</td><td>Display Power Limit 1 value</td></tr><tr><td>Power Limit 1 Clamp Mode</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 1 Clamp Mode</td></tr><tr><td>Power Limit 1 power</td><td>Auto678910111213141516171819202122232425</td><td>Power Limit 1 in Watts. Auto will program Power Limit 1 based on silicon default support value.</td></tr><tr><td>Power Limit 1 Time Window</td><td>Auto123456781012141620242832404856648096112128</td><td>Power Limit 1 Time Window value in Seconds. Auto will program Power Limit 1 Time Window based on silicon default support value.</td></tr></table>

# 7.3.2. Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS</td><td colspan="2">Info only</td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/VESA 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Single LVDS busDual LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>LVDS Backlight Brightness</td><td>Value Range</td><td>A change takes effect immediately. The Value range starts by 0 and ends of 255.</td></tr></table>

# 7.3.3. Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enable/Disable BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enable/Disable System ability to hibernate. This option may be not effective with some OS.</td></tr><tr><td>ACPI Sleep State</td><td>S3 only (Suspend to RAM)Suspend Disabled</td><td>Select ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>Emulation AT/ATX</td><td>Emulation ATATX</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. Win Windows XP, it will make OS show shutdown message during system shutdown.</td></tr><tr><td>Lock Legacy Resources</td><td>DisabledEnabled</td><td>Enables or Disables Lock of Legacy Resources</td></tr><tr><td>ECO Mode</td><td>DisabledEnabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td>Power Consumption</td></tr></table>

# 7.3.3.1. Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power</td></tr><tr><td>V-CORE</td><td>Read only</td><td>Display actual VCORE voltage</td></tr><tr><td>VGFX</td><td>Read only</td><td>Display actual VGFX voltage</td></tr><tr><td>VMEM</td><td>Read only</td><td>Display actual VMEM voltage</td></tr><tr><td>5VSB</td><td>Read only</td><td>Display actual 5VSB voltage</td></tr><tr><td>VIN(12V)</td><td>Read only</td><td>Display actual VIN(12V) voltage</td></tr><tr><td>5V</td><td>Read only</td><td>Display actual 5V voltage</td></tr><tr><td>3.3V</td><td>Read only</td><td>Display actual 3.3V voltage</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Display actual 3.3VSB voltage</td></tr></table>

7.3.4. System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td colspan="2">Info only</td></tr><tr><td>Version</td><td>Info only</td><td>Display Version.</td></tr><tr><td>SEMA Firmware</td><td>Read only</td><td>Display SEMA firmware.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SEMA firmware build date</td></tr><tr><td>SEMA Boot loader</td><td>Read only</td><td>Display SEMA boot loader.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SEMA boot loader build date.</td></tr><tr><td>SEMA Features</td><td>Submenu</td><td>SEMA Features information</td></tr><tr><td>Flags</td><td>Submenu</td><td>SEMA Flags information</td></tr></table>

7.3.4.1. System Management > SEMA Features

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Supported Features</td><td colspan="2">Info only</td></tr><tr><td>Uptime &amp; Power Cycles Counter</td><td colspan="2">Info only</td></tr><tr><td>System Reset Event</td><td colspan="2">Info only</td></tr><tr><td>1024 Bytes User-Flash</td><td colspan="2">Info only</td></tr><tr><td>Watchdog</td><td colspan="2">Info only</td></tr><tr><td>Temperatures</td><td colspan="2">Info only</td></tr><tr><td>Voltage Monitor</td><td colspan="2">Info only</td></tr><tr><td>Display Backlight control</td><td colspan="2">Info only</td></tr><tr><td>Power-Up Watchdog</td><td colspan="2">Info only</td></tr><tr><td>Power Monitor (current sense)</td><td colspan="2">Info only</td></tr><tr><td>Boot Counter</td><td colspan="2">Info only</td></tr><tr><td>Dual-BIOS</td><td colspan="2">Info only</td></tr><tr><td>I2C bus 1</td><td colspan="2">Info only</td></tr><tr><td>I2C bus 2</td><td colspan="2">Info only</td></tr><tr><td>Programmable CPU fan</td><td colspan="2">Info only</td></tr><tr><td>Programmable System fan</td><td colspan="2">Info only</td></tr><tr><td>AT/ATX mode</td><td colspan="2">Info only</td></tr><tr><td>ACPI Thermal Trigger</td><td colspan="2">Info only</td></tr><tr><td>Power-Up to last state</td><td colspan="2">Info only</td></tr><tr><td>Backlight restore</td><td colspan="2">Info only</td></tr><tr><td>DTS register available</td><td colspan="2">Info only</td></tr><tr><td>DTS offset registers programmable</td><td colspan="2">Info only</td></tr><tr><td>TIVA BMC</td><td colspan="2">Info only</td></tr><tr><td>PEC Control</td><td colspan="2">Info only</td></tr><tr><td>Reserved_34</td><td colspan="2">Info only</td></tr><tr><td>SEMA Error Log</td><td colspan="2">Info only</td></tr></table>

# 7.3.4.2. System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td>Display the selection of current BIOS ROM.</td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td>Display ATX/AT-Mode.</td></tr><tr><td>Exception Code</td><td>Read only</td><td>System exception reason.</td></tr></table>

# 7.3.5. Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td>Submenu</td><td>Temperatures and Fan Speed.</td></tr><tr><td>Smart Fan</td><td>Submenu</td><td>Smart Fan.</td></tr><tr><td>Critical Trip Point</td><td>EnabledDisabled</td><td>This value is the temperature threshold of the critical trip point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>EnabledDisabled</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr></table>

# 7.3.5.1. Thermal Management > Temperatures and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Temperature</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td>Display current board temperature</td></tr><tr><td>Board Temperatures</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td>Display board current. temperature</td></tr><tr><td>Startup</td><td>Read only</td><td>Display board startup. temperature</td></tr><tr><td>Min</td><td>Read only</td><td>Display board Min. temperature</td></tr><tr><td>Max</td><td>Read only</td><td>Display board Max. temperature</td></tr><tr><td>CPU Fan Speed</td><td>Read only</td><td>Display CPU Fan RPM</td></tr><tr><td>System Fan1 Speed</td><td>Read only</td><td>Display System Fan1 RPM</td></tr></table>

7.3.5.2. Thermal Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Smart Fan Temperature Source</td><td>CPU Sensor Board Sensor</td><td>CPU smart fan temperature source</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan) Fan Off Fan On</td><td>CPU fan mode</td></tr><tr><td>PWM Level</td><td>100</td><td>PWM level</td></tr><tr><td>System Smart Fan1Temperature Source</td><td>CPU Sensor Board Sensor</td><td>System Smart Fan1Temperature Source</td></tr><tr><td>System Fan1 Mode</td><td>AUTO (Smart Fan) Fan Off Fan On</td><td>System Fan1 Mode</td></tr><tr><td>Trigger Point 1</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>15</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>30</td><td>PWM level</td></tr><tr><td>Trigger Point 2</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>60</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>40</td><td>PWM level</td></tr><tr><td>Trigger Point 3</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>70</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>63</td><td>PWM level</td></tr><tr><td>Trigger Point 4</td><td>Read only</td><td></td></tr><tr><td>Trigger Temperature</td><td>80</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>100</td><td>PWM level</td></tr></table>

7.3.6. Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td colspan="2">Info only</td></tr><tr><td>Power Up watchdogAttention: F12 disables the Power Up Watchdog.</td><td>EnabledDisabled</td><td>The Power-Up Watchdog resets the system after a certain amount of time after power-up.Pressing F12 during start up disables the power up watchdog</td></tr></table>

7.3.7. CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Compatibility Support Module Configuration</td><td colspan="2">Info only</td></tr><tr><td>CSM Support</td><td>EnabledDisabled</td><td>Enable/Disable CSM Support</td></tr><tr><td>CSM16 Module Version</td><td>Read Only</td><td>Display CSM16 Module Version</td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB</td></tr><tr><td>Boot option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls Legacy/UEFI ROMs priority</td></tr><tr><td>Option ROM execution</td><td colspan="2">Info only</td></tr><tr><td>Network</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy PXE OpROM</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Storage OpROM</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Video OpROM</td></tr><tr><td>Other PCI device</td><td>Do not launchUEFILegacy</td><td>Determines OpROM execution policy for devices other than Network, Storage, or Video.</td></tr></table>

7.3.8. IT8783 Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IT8783F Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1.</td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 2.</td></tr><tr><td>Serial Port 3 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 3.</td></tr><tr><td>Serial Port 4 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 4.</td></tr><tr><td>Serial Port 5 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 5.</td></tr><tr><td>Serial Port 6 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 6.</td></tr></table>

7.3.8.1. Super IO > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM)</td></tr><tr><td>Device Setting</td><td colspan="2">Info only</td></tr><tr><td>Change Setting</td><td>AutoIO=3F8;IRQ=4;IO=3F8;IRQ=3,4,5,7,9,10,11,12IO=2F8;IRQ=3,4,5,7,9,10,11,12IO=3E8;IRQ=3,4,5,7,9,10,11,12IO=2E8;IRQ=3,4,5,7,9,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr><tr><td>RS485 Direction Control Enable</td><td>DisableEnable</td><td>Enable/Disable RTSN asserted for RS485 automatic direction control when transmitting data to or receiving data from RS485 transceiver.</td></tr></table>

7.3.9. Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port Console</td><td colspan="2">Info only</td></tr><tr><td>COM1</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM2</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM3</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM4</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>DisabledEnabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM5</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr><tr><td>COM6</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Console Redirection enable or disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

7.3.9.1. Serial Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.ANSI: Extended ASCII char set.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the remote computer. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Select data bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>Select parity.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Select number of stop bits.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Select flow control.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 combination key support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Legacy OS Redirection</td><td>80x2480x25</td><td>On legacy OSes, the number of rows and columns supported by redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select Function Key and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS Post</td><td>Always EnabledBootLoader</td><td>The Settings specify if BootLoader is selected, then legacy console redirection is disabled before booting to legacy OS.</td></tr></table>

7.3.10. USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module version</td><td colspan="2">Info only</td></tr><tr><td>USB Controllers:</td><td colspan="2">Info only</td></tr><tr><td>USB Devices:</td><td colspan="2">Info only</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabled</td><td>Enables Legacy USB support.</td></tr><tr><td>XHCI Hand-off</td><td>DisabledEnabled</td><td>This is a workaround for OSes without XHCI hand-off support.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>EnabledDisabled</td><td>Enable/Disable USB Mass Storage Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td colspan="2">PCH USB Configuration</td></tr><tr><td>USB transfer time-out</td><td>1 sec5 sec10 sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device start unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the host controller.</td></tr></table>

7.3.11. Network

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Onboard LAN Controller</td><td>DisabledEnabled</td><td>Enable/Disable onboard Intel I210LM LAN Controller..</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI Network Stack..</td></tr></table>

7.3.12. Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Chassis Intrusion Support</td><td>DisabledEnabled</td><td>Chassis Intrusion Support.</td></tr></table>

7.3.13. Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>DisabledEnabled</td><td>Enables or Disables BIOS support for security device. O.S. will not show security Device. TCG EFI protocol and INT1A interface will not be available</td></tr></table>

7.3.14. SDIO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SDIO Configuration</td><td colspan="2">Info only</td></tr><tr><td>SDIO Access Mode</td><td>AutoADMASDMAPIO</td><td>Auto Option: Access SD device in DMA mode if controller supports it, otherwise in PIO mode. DMAOption: Access SD device in DMA mode. PIO Option: Access SD device in PIO Mode.</td></tr></table>

7.4. Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>North Bridge</td><td>Submenu</td><td>North Bridge Parameters</td></tr><tr><td>South Bridge</td><td>Submenu</td><td>South Bridge Parameters</td></tr><tr><td>Uncore Configuration</td><td>Submenu</td><td>Uncore Configuration.</td></tr><tr><td>South Cluster Configuration</td><td>Submenu</td><td>South Cluster Configuration</td></tr></table>

7.4.1. North Bridge

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Information</td><td colspan="2">Info Only</td></tr><tr><td>Total memory</td><td>Read Only</td><td>Display Memory Size information</td></tr><tr><td>Memory Voltage</td><td>Read Only</td><td>Display Memory voltage</td></tr><tr><td>Memory Slot0</td><td>Read Only</td><td>Display Memory Slot0 information</td></tr><tr><td>Memory Slot1</td><td>Read Only</td><td>Display Memory Slot1 information</td></tr><tr><td>Max TOLUD</td><td>2 GB2.25 GB2.5 GB2.75 GB3 GB</td><td>Maximum Value of TOLUD</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>DisableEnable</td><td>Enable/Disable above 4GB memory mapped IO BIOS assignment. This is disable automatically when Aperture Size is set to 2048MB</td></tr><tr><td>PCIE VGA Workaround</td><td>Disable Enable</td><td>Enable it if your PCIe card cannot boot to DOS. This is for Test only.</td></tr></table>

7.4.2. South Bridge

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial IRQ Mode</td><td>QuietContinuous</td><td>Configure Serial IRQ Mode</td></tr><tr><td>SMBus Support</td><td>DisableEnable</td><td>Enable/Disable SMBus Support</td></tr><tr><td>OS Selection</td><td>WindowsAndroidWin7Intel Linux</td><td>Select the target OS.</td></tr><tr><td>PCI CLOCK RUN</td><td>DisableEnable</td><td>Enable CLKRUN# logic to stop PCI clocks.</td></tr><tr><td>Real Time Option</td><td>RT DisabledRT Enabled, Agent IDI1RT Enabled, AgentDisabled</td><td>Select Real-Time Enable and IDI Agent Real-Time traffic Mask Bits</td></tr></table>

# 7.4.3. Uncore Configuration

7.4.3.1. Uncore Configuration > GOP Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Active LFP Config</td><td>No LFPeDP</td><td>Active Local Flat Panel Config</td></tr><tr><td>LVDS Backlight Mode</td><td>GTT ModeBMC Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>DDI Port 1</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>DDI port 1 function choose to display Port or HDMI</td></tr><tr><td>DDI Port 2</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>DDI port 2 function choose to display Port or HDMI</td></tr><tr><td>LCD Panel Type</td><td>Auto640x480800x6001024x7681280x10241400x1050(RB) LVDS11400x1050 LVDS21600x1200 LVDS1366x768 LVDS1680x10501920x12001440x900 LVDS1600x900 LVDS1024x768 LVDS21280x8001920x1080 LVDS2048x1536 LVDS</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>GOP Brightness level</td><td>Value</td><td>Set GOP Brightness Level1; Value ranges from 0-255</td></tr></table>

7.4.3.2. Uncore Configuration > IGD Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IGD Configuration</td><td colspan="2">Info only</td></tr><tr><td>Integrated Graphics Device</td><td>EnabledDisabled</td><td>Enable: Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD</td></tr><tr><td>Primary Display</td><td>IGDPCIEHG</td><td>Select which of IGD/PCI Graphics device should be Primary Display.</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB</td><td>Select the Aperture Size.</td></tr><tr><td>DVMT Pre-Allocated</td><td>64MB96MB128MB160MB192MB224MB256MB288MB320MB352MB384MB416MB448MB480MB512MB</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

7.4.4. South Cluster Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD-Audio Configuration</td><td>Submenu</td><td>HD-Audio Configuration Settings</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td>PCI Express Configuration Settings</td></tr><tr><td>SATA Devices</td><td>Submenu</td><td>Press.to select the SATA Device Configuration Setup options.</td></tr><tr><td>SCC Configuration</td><td>Submenu</td><td>SCC Configuration Settings</td></tr><tr><td>USB Configuration</td><td>Submenu</td><td>USB Configuration Settings</td></tr><tr><td>Miscellaneous</td><td>Submenu</td><td>Enable/Disable Misc. Features</td></tr></table>

7.4.4.1. South Cluster Configuration > HD-Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD-Audio Configuration</td><td colspan="2">Info only</td></tr><tr><td>HD-Audio Support</td><td>DisabledEnabled</td><td>Enable/Disable HD-Audio Support</td></tr></table>

7.4.4.2. South Cluster Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Configuration</td><td colspan="2">Info only</td></tr><tr><td>Compliance Mode</td><td>DisabledEnabled</td><td>Compliance Mode Enable/Disable</td></tr><tr><td>PCIe Express Root Port3</td><td>Submenu</td><td>Control the PCI Express Root Port.Auto: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIE root portDisable: Disable PCIE root port</td></tr><tr><td>PCIe Express Root Port4</td><td>Submenu</td><td>Control the PCI Express Root Port.Auto: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIE root portDisable: Disable PCIE root port</td></tr><tr><td>PCIe Express Root Port5</td><td>Submenu</td><td>Control the PCI Express Root Port.Auto: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIE root portDisable: Disable PCIE root port</td></tr><tr><td>PCIe Express Root Port6</td><td>Submenu</td><td>Control the PCI Express Root Port.Auto: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIE root portDisable: Disable PCIE root port</td></tr></table>

7.4.4.3.
South Cluster Configuration > PCI Express Configuration > PCIe Express Root Port3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Express Root Port3</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.Auto: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIE root portDisable: Disable PCIE root port</td></tr><tr><td>ASPM</td><td>DisableL0sL1L0sL1Auto</td><td>PCI Express Active State Power Management settings.</td></tr><tr><td>L1 Substates</td><td>DisableL1.1L1.2L1.1 &amp; L1.2</td><td>PCI Express L1 Substates Settings</td></tr><tr><td>ACS</td><td>DisabledEnabled</td><td>Enable/Disable Access Control Services Extend Capability.</td></tr><tr><td>URR</td><td>DisabledEnabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable .</td></tr><tr><td>FER</td><td>DisabledEnabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable .</td></tr><tr><td>NFER</td><td>DisabledEnabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>DisabledEnabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable .</td></tr><tr><td>CTO</td><td>Default Setting16-55 ms65-210 ms260-900 ms1-3.5 sDisable</td><td>PCI Express Completion Timer To Enable/Disable</td></tr><tr><td>SEFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable .</td></tr><tr><td>SENFE</td><td>DisabledEnabled</td><td>Enable or disable Root PCI Express System Error on Non-Fatal Error.</td></tr><tr><td>SECE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>DisabledEnabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2</td><td>Configure PCIe Speed.</td></tr><tr><td>Transmitter Half Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory and Prefetchable memory (1-20MB) Range for this Root Bridge.</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/46K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIE LTR</td><td>DisabledEnabled</td><td>PCH PCIE Latency Reporting Enable/Disable.</td></tr><tr><td>Snoop Latency Override</td><td>DisableManualAuto</td><td>Snoop Latency Override for PCH PCIE.Disable: Disable override.Manual: Manually enter override valuesAuto (Default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>DisableManualAuto</td><td>Non Snoop Latency Override for PCH PCIE.Disable: Disable override.Manual: Manually enter override valuesAuto (Default): Maintain default BIOS flow.</td></tr><tr><td>PCIE LTR Lock</td><td>DisabledEnabled</td><td>PCIE LTR Configuration Lock.</td></tr><tr><td>PCIe Selectable De-emphasis</td><td>DisabledEnabled</td><td>When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b – 3.5 dB0b – 6 dB.</td></tr></table>

7.4.4.4. South Cluster Configuration > SATA Devices

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Drives</td><td colspan="2">Info only</td></tr><tr><td>Chipset-SATA Controller Configuration</td><td colspan="2">Info only</td></tr><tr><td>Chipset SATA</td><td>DisabledEnabled</td><td>Enable/Disable the Chipset SATA Controller. The Chipset SATA Controller supports 2 black internal SATA ports (up to 3Gb/s supported per port).</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA Controller(s) operate.</td></tr><tr><td>SATA Interface Speed</td><td>Gen1Gen2Gen3</td><td>Select SATA Interface Speed, CHV A1 always with Gen1 Speed.</td></tr><tr><td>SATA Test Mode</td><td>DisabledEnabled</td><td>Test mode Enabled / Disabled</td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Port Configuration</td><td>Submenu</td><td>SATA Device Options Settings.</td></tr><tr><td>SATA Port 0</td><td colspan="2">Info only</td></tr><tr><td>Software Preserve</td><td colspan="2">Info only</td></tr><tr><td>Port 0</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port.</td></tr><tr><td>SATA Port 0 Hot Plug Capability</td><td>DisabledEnabled</td><td>If enabled, SATA port will be reported as Hit Plug capable.</td></tr><tr><td>Configured as eSATA</td><td colspan="2">Info only</td></tr><tr><td>Mechanical Preserve Switch</td><td>DisabledEnabled</td><td>Controls reporting if this port has a Mechanical Preserve Switch.Note: Requires hardware support.</td></tr><tr><td>Spin Up Device</td><td>EnabledDisabled</td><td>If enable for any ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to solid state drive or Hard Disk drive</td></tr><tr><td>SATA port 0 DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 DevSlp. Board rework for LP needed before enable.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration.</td></tr><tr><td>DITO Value</td><td colspan="2">Read Only</td></tr><tr><td>DM Value</td><td colspan="2">Read Only</td></tr></table>

# 7.4.4.5. South Cluster Configuration > SCC Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SCC SD Card Support (D27:F0)</td><td>DisabledEnabled</td><td>Enable/Disable SCC SD Card Support</td></tr></table>

# 7.4.4.6. South Cluster Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Pre-Boot Driver</td><td>DisabledEnabled</td><td>Enable/Disable XHCI Pre-Boot Driver Support</td></tr><tr><td>XHCI Mode</td><td>DisabledEnabled</td><td>Once disable, XHCI controller would be function disabled, none of the USB devices are detectable and usable during boot and in OS. Do not disable it unless for debug purpose.</td></tr><tr><td>USB Port Disable Override</td><td>DisabledEnabled</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB Port #0</td><td>DisabledEnabled</td><td>Enable/Disable USB port. Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr></table>

7.4.4.7. South Cluster Configuration > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>High Precision Timer</td><td>DisabledEnabled</td><td>Enable or Disable the High Precision Event Timer</td></tr><tr><td>State After G3</td><td>S0 StateS5 StateLast State</td><td>Specify what state to go to when power is re-applied after a power failure (G3 State).S0 State: System will boot directly as soon as power applied.S5 State: System keeps in power-off state until power button is pressed.</td></tr><tr><td>Wake on LAN</td><td>DisabledEnabled</td><td>Enable or Disable the Wake on LAN</td></tr></table>

# 7.5. Security

7.5.1. Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Setup Administrator Password</td><td>Enter password</td><td></td></tr><tr><td>User Password</td><td>Enter password</td><td></td></tr><tr><td>Secure Boot menu</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr></table>

7.5.1.1. Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Boot</td><td colspan="2">Info Only</td></tr><tr><td>System Mode</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot Control</td><td>DisabledEnabled</td><td>Secure Boot can be enabled if:1. System running in User mode with enrolled Platform Key (PK)2. CSM function is disabled.</td></tr></table>

# 7.6. Boot

# 7.6.1. Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enable or Disable Quiet Boot option.</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enable or Disable Fast Boot features. Most probes are skipped to reduce time cost during boot..</td></tr><tr><td>New Boot Option Policy</td><td>DefaultPlace FirstPlace Last</td><td>Controls the placement of newly detected UEFI boot options</td></tr><tr><td>Boot Mode select</td><td>LegacyUEFI</td><td>Select boot mode LEGACY/UEFI</td></tr><tr><td>Boot Option #1~ #8</td><td>Hard DiskCD/DVDUSB Hard DiskUSB CD/DVDUSB KeyUSB FloppyUSB LANNetworkDisabled</td><td>Set the system boot order</td></tr></table>

# 7.7. Save & Exit

# 7.7.1. Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>Yes/No</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>Yes/No</td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>Yes/No</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Yes/No</td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Changes</td><td>Yes/No</td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>Yes/No</td><td>Discard Changes done so far to any of the setup options.</td></tr></table>

# 7.7.2. Default Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Restores Defaults</td><td>Yes/No</td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Default</td><td>Yes/No</td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>Yes/No</td><td>Restore the User Defaults to all the setup options.</td></tr></table>

# 7.7.3. Boot Override

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>UEFI: Built-in EFI Shell</td><td></td><td>Launches built-in EFI Shell</td></tr><tr><td>Launch EFI Shell from file system device</td><td></td><td>Launches EFI Shell from file system device</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

• Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources.
 Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
 Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

<table><tr><td>Address:</td><td>9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan</td></tr><tr><td>Tel:</td><td>+886-2-8226-5877</td></tr><tr><td>Fax:</td><td>+886-2-8226-5717</td></tr><tr><td>Email:</td><td>service@adlinktech.com</td></tr></table>

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

+1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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