# AMSTX-CF Series User’s Manual Embedded Motherboard supporting MXM Graphics Module with 8th/9th Generation Intel® Core™ i7/i5/i3 in LGA1151 Socket ![Close-up of a computer motherboard with visible CPU socket, RAM slots, and connectors (no readable text or symbols)](.amstx-cf-50m-7a106-1020-12/c3fd56250468e40d068b82f51e803b6f82080595b32a5494d99614a1e070d91b.jpg) Manual Rev.: 1.2 Revision Date: November 14, 2025 Part Number: 50M-7A106-1020 # Preface # Copyright Copyright © 2025 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![Symbol of a trash bin with crossed lines indicating no waste or restriction, and a solid rectangle below (no text or labels)](.amstx-cf-50m-7a106-1020-12/d25b21bbf9c3362e757d57413d10a254dfd98c654752828e26abfbd42ed368ae.jpg) Battery Labels (for products with battery) ![Li-ion\nRECYCLE\nRBRC\nLi-ion\n廢電池請回收](.amstx-cf-50m-7a106-1020-12/a869f45c5af168d0811478b3dffd22741abb1831048e9fde0c00de4ab2fb3012.jpg) # California Proposition 65 Warning ![The image displays a standard triangular warning sign. It has a bright yellow background enclosed by a thick black border. In the center is a large black exclamation point.](.amstx-cf-50m-7a106-1020-12/a08dfa3a03d813b1445e83c8c12dfea91ed34e16fb30eaa65ac413daaad33cd3.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. Revision History

Revision	Description	Date	By
1.0	Initial release	2020-12-21	JC
1.1	Add new models (EGX-MXM-RTX3000 and EGX-MXM-RTX5000); add MXM cooler for RTX5000 and 500W power supply; update specifications; update block diagrams; add mating connector list; update DisplayPort BIOS settings	2021-04-20	JC
1.2	Connector pinouts updated	2025-11-14	AL

# Table of Contents Preface... List of Figures ....... ..vi List of Tables...... ..vii 1 Introduction........ 1.1 Packing List .. 1.2 Available Models.. 1.3 Optional Accessories . 2 Specifications .......... 2.1 Core System . .3 2.2 I/O Interface .. ..3 2.3 Video . .4 2.4 Audio .4 2.5 Power Supply... .4 2.6 Temperatures . .4 2.7 Humidity... .4 2.8 Certificate (EMC) . .5 2.9 Form Factor . .5 2.10 Operating Systems .... .5 3 Functional Block Diagram .... 4 Mechanical Layout .............. 4.1 Connector Locations .. .9 4.2 Mechanical Dimensions . ...12 5 Connector Pinouts ..... .13 5.1 LEDs.. ..13 5.2 Internal Connectors.. ..14 5.3 Jumper and Switch Settings. ..23 6 Driver Installation .. .27 7 System Resources .... .29 7.1 System Memory Map ..... ..29 7.2 I/O Map ... ..29 7.3 Interrupt Request (IRQ) Lines . ..30 7.4 PCI/PCIe Device. .32 7.5 SMBus Slave Addresses.. .33 # 8 Digital Input/Output Function Library ........ ..35 8.1 DI/O with Windows API. ..35 # 9 DisplayPort BIOS Settings.... .37 9.1 MXM P1000/P2000/T1000/RTX3000/ RTX5000 .. ..37 9.2 MXM P3000/P5000.. ..37 # 10 BIOS Setup..... ..39 10.1 Menu Structure . ..40 10.2 Main. ..41 10.3 Advanced.. ..44 10.4 Chipset .. ..58 10.5 Security.... ..63 10.6 Boot .. ..64 10.7 Save & Exit . ..65 # Safety Instructions... .66 # Getting Service...... ..67 # List of Figures Figure 1: Functional Block Diagram.. Figure 2: IO Panel Connector Locations. 9 Figure 3: Onboard Connector Locations- Top Side . ..10 Figure 4: Onboard Connector Locations - Bottom Side. ..11 Figure 5: Mechanical Dimensions - Top View... ..12 # List of Tables Table 1: IO Panel Connector Definitions .9 Table 2: Onboard Connector Definitions - Top Side. ..10 Table 3: Onboard Connector Definitions - Bottom Side. .11 Table 4: System Memory Map.. ..29 Table 5: IO Map... .29 Table 6: IRQ Lines PIC Mode.. ..30 Table 7 IRQ Lines APIC Mode . .30 Table 8 PCI Configuration Space Map .. ..32 Table 9 PCI Interrupt Routing Map.. .33 Table 10 SMBus Slave Addresses . ..33 This page intentionally left blank. # 1 Introduction Embedded graphics enable system developers to boost the performance of a wide range of workloads, including medical imaging, image analysis, compute acceleration, and artificial intelligence (AI). Leveraging graphics processing units (GPUs), embedded graphics can be used to increase application speed and accuracy, as well as decrease latency. Many embedded system developers use embedded graphics solutions in real-world applications from the medical and manufacturing industries, to traffic management. System developers, OEMs, and system integrators can more easily deploy embedded graphics with support from ADLINK’s large portfolio of computing products designed in a wide range of form factors. The AMSTX-CF Series Micro-STX motherboard features a socket-type CPU and support for Scalable Graphics Processing Ranging from Pascal to Turing GPUs in a compact form factor. Combining its strong expertise serving embedded developers and its close relationship with NVIDIA, ADLINK is delivering high-performance, long-life embedded graphics solutions for a variety of market segments. # 1.1 Packing List • AMSTX-CF embedded motherboard CPU cooler bracket (P/N: 32-50015-0100-A0) • M3 screw, P-head, L4, Ni for M.2 E/B/M Key (P/N: 33-03013-0040) (3 for Q370, 2 for H310) 2x M3 screw, I-head, L4, Nylok for MXM (P/N: 33-03306-0040) # 1.2 Available Models

Model	AMSTX-CFP12-Q370	AMSTX-CFP35-Q370	AMSTX-CFP12-H310	AMSTX-CFP35-H310
MXM Support	EGX-MXM-P1000EGX-MXM-P2000/EGX-MXM-T1000EGX-MXM-RTX3000EGX-MXM-RTX5000	EGX-MXM-P3000EGX-MXM-P5000	EGX-MXM-P1000EGX-MXM-P2000EGX-MXM-1000EGX-MXM-RTX3000EGX-MXM-RTX5000	EGX-MXM-P3000EGX-MXM-P5000
Chipset	Intel® Q370 Chipset		Intel® H310 Chipset

# 1.3 Optional Accessories 65W CPU cooler (P/N: 32-20495-0000) • 35W CPU cooler (P/N: 32-20378-0000-A0) MXM cooler for P1000/P2000 (P/N: 32-20797-0200-A0) MXM cooler for P3000/P5000 (P/N: 32-20823-0020-A0) MXM cooler for T1000 (P/N: 32-20830-0200-A0) • MXM cooler for RTX3000 (P/N: 32-20823-1100-A0) MXM cooler for RTX5000 (P/N: 32-20839-1000-A0) 12V/240W adaptor (P/N: 31-62164-0010-A0) 500W power supply (12V/41.7A) (P/N: 91-95296-000E) • Wi-Fi Kit Intel® Wireless-AC 9260 non-vPRO (P/N: 91-95266-0020) • AMSTX/DLAP-3000 CPU cooler bracket (included by default) (PN: 32-50015-0100-A0) This page intentionally left blank. # 2 Specifications # 2.1 Core System  CPU: Desktop 8th/9th Generation Intel® Core™ i7/i5/i3 Processor, LGA1151 socket • Intel® Core™ i7-9700E, 2.6GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (8C/8T) • Intel® Core™ i7-9700TE, 1.8GHz, 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (8C/8T) • Intel® Core™ i5-9500E, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T) • Intel® Core™ i5-9500TE, 2.2GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T) • Intel® Core™ i3-9100E, 3.1GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support (4C/4T) • Intel® Core™ i3-9100TE, 2.2GHz, 6M Cache, 35W TDP, LGA1151, DDR4 2400MHz support (4C/4T) • Intel® Core™ i7-8700, 3.2GHz, 12M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/12T) • Intel® Core™ i7-8700T, 2.4GHz 12M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/12T) • Intel® Core™ i5-8500, 3.0GHz, 9M Cache, 65W TDP, LGA1151, DDR4 2666MHz support (6C/6T) • Intel® Core™ i5-8500T, 2.1GHz, 9M Cache, 35W TDP, LGA1151, DDR4 2666MHz support (6C/6T) • Intel® Core™ i3-8100, 3.6GHz, 6M Cache, 65W TDP, LGA1151, DDR4 2400MHz support (4C/4T) • Intel® Celeron® G4900, 3.1GHz, 2M Cache, 54W TDP, LGA1151, DDR4 2400MHz support (2C/2T) • Intel® Celeron® G4900T, 2.9GHz, 2M Cache, 35W TDP, LGA1151, DDR4 2400MHz support (2C/2T) Chipset: Intel® Q370 or H310 Chipset TPM: TPM 2.0 (optional)  Memory: Non-ECC DDR4 2666/2400 MHz, 2x SODIMM, up to 64 GB (dependent on CPU)  BIOS: AMI® UEFI BIOS, 256 Mb (Q370) or 128 Mb (H310) SPI flash memory MXM Graphics Module Support: AMSTX-CFP12-Q370/H310: EGX-MXM-P1000, EGX-MXM-P2000, EGX-MXM-T1000, EGX-MXM-RTX3000, EGX-MXM-RTX5000 • AMSTX-CFP35-Q370/H310: EGX-MXM-P3000, EGX-MXM-P5000 # 2.2 I/O Interface  PCB Edge Connector: Q370 SKU: 1x PCIe x8 PCB edge connector (data is from 2x PCIe Gen3 x4 root ports, one set of clocks, up to 50W), one PCIe power connector up to 12V@3.5A / 5V@4A H310 SKU: 1x PCIe x8 PCB edge connector (data is from 1x PCIe Gen2 x1 root ports, one set of clocks, up to 50W), one PCIe power connector up to 12V@3.5A / 5V@4A  LAN: 1x GbE (Intel® i219-LM), 3x GbE (Intel® i210-AT)  SATA: Q370 SKU: 2x SATA 6Gb/s, one SATA power connector 2x SATA 6Gb/s signals via M.2 M & B key connector, Intel® RST RAID Support • H310 SKU: 2x SATA 6Gb/s, one SATA power connector 1x SATA 6Gb/s signal via M.2 B key connector USB: • Q370 SKU: 4x USB 3.2 Gen1 x1 ports, 2x USB 2.0 pin headers, 2x USB 3.2 Gen1 x1 pin headers H310 SKU: 4x USB 3.2 Gen1 x1 ports, 4x USB 2.0 pin headers DIO: 1x 10-pin/2.0mm wafer: DI/DO: 4 in and 4 out  COM: 1x RS-232/422/485 pin header, 1x RS-232 pin header (CCtalk supported by jumper setting) #  M.2: Q370 SKU: 1x M.2 E key supporting 1630 or 2230 for Wi-Fi/BT module, 1x M.2 B key supporting 2242 or 2280 for SATA storage module, 1x M.2 M key supporting 2242 or 2280 for SATA/PCIe x4 storage module H310 SKU: 1x M.2 E key supporting 1630 or 2230 for Wi-Fi /BT module, 1x M.2 B key supporting 2242 or 2280 for SATA storage module # 2.3 Video # Graphics Engine: Integrated Intel® HD Graphics series (based on CPU, Q370 SKU supports three independent display and H310 SKU supports two independent display) • ADLINK MXM module (optional) # Interfaces: . From Intel® HD Graphics:  2x DP connector, resolution up to 4096 x 2304 @ 60 Hz, and DP++ support  1x HDMI connector (vertical type on PCB), resolution up to 4096 x 2160 @ 24 Hz  1x LVDS (optional, default is WO/LVDS), dual channel 24-bit or 18-bit up to 1920 x 1200 Hz From MXM:  4x DP connectors, signal from MXM module, resolution based on MXM module, DP++ support # 2.4 Audio  Audio Codec: Realtek® ALC262-VC2-GR or ALC888S-VD2-GR Interfaces:  Default: 1x 10-pin wafer (box header) for Mic-in/Line out/Line in, connector via additional audio module Optional 1: Mic in / 6W speaker\_out\_L+6W speaker\_out\_R. (onboard 10-pin wafer, connector via additional audio module) Optional 2: Line in / 6W speaker\_out\_L+6W speaker\_out\_R. (onboard 10-pin wafer, connector via additional audio module) # 2.5 Power Supply DC input: DC 12V input (Molex DC-in jack) AC input: Optional: 240W (12V @20A) AC/DC adapter Optional: 500W (12V @41.7A) AC/DC power supply # 2.6 Temperatures Operating Temperature: 0°C to 60°C (w/o MXM) $0 ^ { \circ } \mathsf { C }$ to $5 5 ^ { \circ } \mathrm { C }$ (w/MXM, excluding EGX-MXM-RTX5000) $0 ^ { \circ } \mathsf { C }$ to 45°C (EGX-MXM-RTX5000) Storage Temperature: $\angle 4 0 ^ { \circ } \mathsf { C }$ to $8 5 ^ { \circ } \mathsf { C }$ # 2.7 Humidity 5% to 95%, non-condensing # 2.8 Certificate (EMC)  EN55032/35, EN61000-6-2/-4, CE, FCC Part 15B Class B # 2.9 Form Factor 197.72 x 167.32 mm (W x L)  ADLINK proprietary mounting hole locations, ADLINK proprietary CPU cooler bracket # 2.10 Operating Systems Microsoft® Windows® 10 64-bit Ubuntu 18.04.10 LTS 64-bit This page intentionally left blank. # 3 Functional Block Diagram ![Based on the provided flowchart, here is the accurate and concise description of the blocks and their connections:\n\n**Top Section (Processor & Memory)**\n* **SODIMM 1** (DDR4 non-ECC Socket) connects via **Channel A** to the **8th/9th Gen Intel® Core™ Processor (Coffee Lake-S)**.\n* **SODIMM 2** (DDR4 non-ECC Socket) connects via **Channel B** to the **8th/9th Gen Intel® Core™ Processor (Coffee Lake-S)**.\n* **LVDS CN** connects via **DUAL 24/18bits** to **DP to LVDS PTN3460IBS_NXP**, which connects via **eDP(2-Lanes)** to the Processor.\n* The Processor connects via **DDI 1 (PORT B): DP** and **DDI 2 (PORT C): DP** to two **DP CN** blocks.\n* The Processor connects via **DDI 3 (PORT D): HDMI** to an **HDMI CN** block.\n* The Processor connects via **PCI Express x16 (GEN3)** to an **MXM3.1 slot**.\n* The **MXM3.1 slot** connects via **Port A**, **Port B**, **Port C**, and **Port D** to four separate **DP CN** blocks.\n* The Processor connects via **DMI** to the **Intel® PCH Q370/H310 Chipset**.\n\n**Left Side (Chipset Peripherals & Connectivity)**\n* The **Intel® PCH Q370/H310 Chipset** connects via **USB3.2 Gen1x1** and **USB2.0** to the **USB3.2 Gen1x1 *4 + RJ45 x1 CN *2** block.\n* The Chipset connects via **LAN** to **GbE LAN1 i219LM_Intel**.\n* The Chipset connects via **PCIe1** to **LAN2 i210_Intel**.\n* The Chipset connects via **USB3.2 Gen1x1** and **USB2.0** to the **USB3.2 Gen1x1 *2(Q370)/USB2.0 *2(H310)** block.\n* The Chipset connects via **USB3.2 Gen1x1** to a **SW PI3DBS12212A_Diodes** block, which connects to the **M.2_B_key CNx1 2280 size (default)** block.\n* The Chipset connects via **PCIe1** to a middle **SW PI3DBS12212A_Diodes** block.\n * This SW block connects to **RJ45 CN** and a **BOM Option** block.\n * The **RJ45 CN** connects to **LAN4 i210_Intel** (Default) and **LAN3 i210_Intel** (Default).\n * Both **LAN4** and **LAN3** connect to separate **BOM Option** blocks, which connect to **PCIe1** going to the Chipset.\n* The Chipset connects via **SATA** to a bottom **SW PI3DBS12212A_Diodes** block.\n * This SW block connects to **USB2.0x2** via **USB2.0**.\n * The **USB2.0x2** block connects to the Chipset via **USB2.0**.\n* The Chipset connects via **PCIe4 or SATA** to the **M.2_M_key CNX1 2280 size (Q370 only)** block.\n* The Chipset connects via **PCIe1 *2** and **USB2.0** to the **M.2_E_key CNx1 2230 size (default)** block.\n\n**Right Side (Chipset I/O & Peripherals)**\n* The Chipset connects via **HDA** to the **Audio Codec**.\n * The Audio Codec connects to a text box describing **Line In** and **Mic In** options (Default, Option 1, Option 2).\n * The Audio Codec connects via **Line Out** to the **AMP TPA3132D2_TI** block.\n * The AMP connects to a text box describing **Speaker Out** options.\n* The Chipset connects via **SATA** to the **SATA CN x2** block.\n* The Chipset connects via **SPI** to the **BIOS** block.\n* The Chipset connects via **LPC bus** to the **SUPER I/O F81866AD_FINTEK** block.\n * The SUPER I/O connects via **UART** to **SP339E_EXAR**, which connects to **RS-232/422/485**.\n * The SUPER I/O connects via **UART** to **ADM213EA_ADI**, which connects to **RS-232**.\n* The Chipset connects via **LPC bus** to the **TPM 2.0 SLB9665_Infineon** block.\n* The Chipset connects via **JTAG** to the **DB40** block.\n* The Chipset connects via **SMBUS** to the **Lite BMC STM32L071RBT6_ST** block.\n * The Lite BMC connects to **CPU FAN**, **GPU FAN**, and **System FAN** blocks.\n* The Chipset connects via **GPIO** to the **DIO 10 pins Wafer x1** block.\n* The Chipset connects to a bottom-right text box detailing connector options:\n * **For Q370 SKU:** 1x PCIe x8 PCB edge connector (data is from 2x PCIe Gen3 x4 root ports, one set of clocks, up to 50W)\n * **For H310 SKU:** 1x PCIe x8 PCB edge connector (data is from 1x PCIe Gen2 x8 root ports, one set of clocks, up to 50W)](.amstx-cf-50m-7a106-1020-12/19f56713d659828c8288bd5a59fc71bce4b1f53e4602b4cb18c23933bfbdcc5d.jpg) Figure 1: Functional Block Diagram This page intentionally left blank. # 4 Mechanical Layout # 4.1 Connector Locations ![A\nB\nC\nD\nG\nH\nI\nJ\nE\nF](.amstx-cf-50m-7a106-1020-12/42e48785271300ac42390cbc3d411924c1d30d260aed741f4b8f1f3c0bb68a1a.jpg) Figure 2: IO Panel Connector Locations Table 1: IO Panel Connector Definitions

Item	Description	Remarks
A	DisplayPort (from CPU)	CN1
B	LAN (I210-AT)	RJ453
C	LAN (I210-AT)	CN24
D	LAN (I219-LM)	CN23
E	2x USB 3.2 Gen1 x1	CN24
F	2x USB 3.2 Gen1 x1	CN23
G	HDMI (from CPU)	HDMI1
H	DisplayPort (from MXM)	U13
I	DisplayPort (from MXM)	U27
J	12V DC-in connector	CN3

![F G H I J K\nE C L M\nD B\ne f\nA\nLGA1151 REMOVE\ng\nS\nd c b a Z Y X T\nU V W](.amstx-cf-50m-7a106-1020-12/de19ece4431bacd795fa7174096dca46d9d66a5a5dcf1f3ca8a8d81c6d3dd6ba.jpg) Figure 3: Onboard Connector Locations- Top Side Table 2: Onboard Connector Definitions - Top Side

Item	Description	Item	Description
A	CPU socket	R	Panel backlight power and resolution jumper (CN13)
B	DRAM socket for DIMM1	S	MXM connector (CN5)
C	DRAM socket for DIMM2	T	PCB edge connector
D	CPU Fan connector	U	RTC battery connector (CN16)
E	System fan connector	V	GPU fan connector
F	2x USB2.0 pin header (CN22)	W	12V DC in connector (CN3)
G	RS-232 pin header for COM1 (CN7)	X	Display port C and Display port D from MXM
H	RS-232/422/485 pin header for COM2 (CN8)	Y	Display port A and Display port B from MXM
I	2x USB 3.2 Gen1 x1 pin headers (Q370)2x USB 2.0 pin headers (H310)	Z	HDMI from CPU
J	Multi-purpose connector (CN6)	a	LAN1 and USB 3.2 Gen1 x1 ports 1/2
K	Audio pin header (CN9)	b	LAN4 and USB 3.2 Gen1 x1 ports 3/4
L	PCIe power connector (CN10)	c	LAN2 and LAN3
M	SATA connector (SATA1)	d	Display port 1 and Display port 2 from CPU
N	SATA connector (SATA2)	e	BMC status LED (LED2, Blue)
O	SATA power connector (CN14)	f	BMC watchdog LED (LED3, Red)
P	Power on module connector (CN12)	g	Data format and Color Depth selection for LVDS (SW1)
Q	DIO connector (CN11)

![A F G\nH B C D I\nK J\nE](.amstx-cf-50m-7a106-1020-12/137fbd421e872a0db0422f51b26e47b8997c89e38aa7b8d2c54f9d36d6cd5cc8.jpg) Figure 4: Onboard Connector Locations - Bottom Side Table 3: Onboard Connector Definitions - Bottom Side

Item	Description
A	DB40 connector (CN19)
B	M.2_B Key connector (CN17)
C	M.2_M Key connector (CN20)
D	M.2_E Key connector (CN15)
E	LVDS (CN21)
F	Multi-IO voltage selection (SW9)
G	RI#,5V,12V selection (SW7)
H	HSIO Selection (SW5)
I	LVDS Channel selection (SW2)
J	DIO voltage selection (SW8)
K	LVDS VDD selection (SW6)

# 4.2 Mechanical Dimensions Dimensions: mm Top View ![Ø4\nØ7.60\n167.32\n162.32\n162.32\n23.50\n5\n12.90\n34.93\n55.92\n77.62\n116.87\n132.35\n147.86\n169.80\n183.72\n197.72\n5](.amstx-cf-50m-7a106-1020-12/ab2cc3158a863cf40571b3ca08671c473d7f8d1f7aff94b67ada777144061b70.jpg) Figure 5: Mechanical Dimensions - Top View Side View ![31.05\n1.60\n8.50](.amstx-cf-50m-7a106-1020-12/6584530ced10054f31379f27e6fbe404350cb6ac82d9d5ab4bf79961fe4c3939.jpg) # 5 Connector Pinouts See 3.1 Connector Locations on page 9 for connector locations. # 5.1 LEDs # 5.1.1 BMC Status LED and WDT LED # 5.1.1.1 Status LED (Blue, LED2) The Status LED is controlled by SEMA. The Status LED will signal system state changes and power up failures including HW-Reset, SW-Reset, Power-Up, Power-Down, Reset-Button and Power-Button activity. Power-up failures can be caused by a corrupted BIOS or failures at the onboard power supply. When the system is in an S3 state, the Status LED will blink to indicate the type of failure.

LED Blink Code	Status
0	NOERROR
2	NO_SUSCLK
3	NO_SLP_S5
4	NO_RSMRST
5	NO_SLP_S3
7	PLTRST_FAIL
8	NO_SYS_PWRGD
10	CRITICAL_TEMP
11	NO_VIN
12	NO_VRTC

# 5.1.1.2 WDT LED (Red, LED3) The WDT LED is driven by SEMA and will light when a watchdog timeout occurs. It stays on until it is cleared by software or by pressing the reset button. # 5.1.2 Ethernet Connectors LEDs 5.1.2.1 Active/Link LED Indicators

LED Color	Status	Description
Orange	OFF	Ethernet port is disconnected
	ON	Ethernet port is connected with no activity
	Flashing	Ethernet port is connected and active

5.1.2.2 Speed LED Indicators

LED Color	Status	Description
Green/Orange	OFF	10 Mbps
	Green	100 Mbps
	Orange	1000 Mbps

# 5.2 Internal Connectors # 5.2.1 USB 2.0 Pin Header (CN22)

Pin	Signal
1	P5V_USB1
2	P5V_USB2
3	CN_U2_USB9_N
4	CN_U2_USB14_N
5	CN_U2_USB9_P
6	CN_U2_USB14_P
7	GND
8	GND
9	NC
10	GND

![The image displays a vertical rectangular diagram. Inside the rectangle, there are eight small black squares arranged in two columns of four. Four small rectangles are located at the four corners of the inner area. The number '1' is positioned to the left of the top section, and the number '10' is positioned to the right of the bottom section.](.amstx-cf-50m-7a106-1020-12/f17013e0b4337420f2a2b2b4e3698ea6657882e971dc047fdcdc2bf4695bcef0.jpg) # 5.2.2 USB 3.2 Gen1 x1 Pin Header (CN4)

Pin	Signal	Pin	Signal
1	NC	11	P5V_USB56
2	CN_U3_USB6_T_P	12	CN_U2_USB5_N
3	CN_U3_USB6_T_N	13	CN_U2_USB5_P
4	GND	14	GND
5	CN_U3_USB6_R_P	15	CN_U3_USB5_R_N
6	CN_U3_USB6_R_N	16	CN_U3_USB5_R_P
7	GND	17	GND
8	CN_U2_USB6_P	18	CN_U3_USB5_T_N
9	CN_U2_USB6_N	19	CN_U3_USB5_T_P
10	P5V_USB56	20	NC

![Pure diagram of a rectangular panel with internal slots and numbered labels (1 and 20), no text or symbols beyond labels.](.amstx-cf-50m-7a106-1020-12/5ea31b5e400c5556fe04842bd3e3b0a17797e8d7316d374dbdec5af0dfabf33e.jpg) Note: An adapter cable is available to convert the USB 3.2 signals to USB 2.0. Contact your ADLINK representative for more information. # 5.2.3 PCIe Power Connector Pin Header (CN10)

Pin	Signal
1	P_+12V_S
2	P_+12V_S
3	P_+5V0_S
4	P_+5V0_S
5	GND

![This image displays a technical line drawing featuring a vertical rectangular structure. On the far left, a series of three small stacked rectangles is attached to the side of a larger, double-outlined rectangle. Inside this larger rectangle, five small squares are arranged in a vertical column. To the right of the drawing is the number 1.](.amstx-cf-50m-7a106-1020-12/469cf44b56ee20f07f3b4e2a17df9712ca59aeebd429fc29096019f749bb6187.jpg) # 5.2.4 SATA Power Connector Pin Header (CN14)

Pin	Signal
1	P_+5V0_S
2	P_+5V0_S
3	P_+5V0_S
4	GND
5	GND
6	GND

![A black-and-white technical illustration depicts a vertical connector, likely a DB-25 type, with two rows of pins on its left side and metal brackets at the top and bottom. To the right of the connector is a vertical line followed by the number 1.](.amstx-cf-50m-7a106-1020-12/549c21305f907066bf9c088a441af899212ac80c94b8e08d6924971fdcf0ffd5.jpg) # 5.2.5 COM Pin Headers (CN7)

Pin	Signal Name
Pin	RS-232	CC Talk mode
1	DCD#	N/A
2	DSR#	N/A
3	RxD	RS232_RX_ccTalk
4	RTS#	N/A
5	TxD	RS232_TX_ccTalk
6	CTS#	N/A
7	DTR#	N/A
8	RI#/5V/12V	5V / 12V
9	GND	GND
10	NC	NC

![The image displays a schematic diagram of a dual inline package (DIP) integrated circuit, specifically a 12-pin configuration. It features a thick black rectangular outline. Inside the outline, there are two vertical columns of small squares, arranged in six rows. The number '1' is positioned at the top left, and '2' is at the top right. The number '9' is positioned to the left of the fifth row, and '10' is to the right of the fifth row.](.amstx-cf-50m-7a106-1020-12/084c55e15cc85c4b4b65d430551840ad6f061a7f00a02abb3d759ee6c37652e2.jpg) # 5.2.6 COM Pin Headers (CN8)

Pin	Signal Name
Pin	RS-232	RS-422	RS-485
1	DCD#	Tx-	Tx/Rx-
2	DSR#	N/A	N/A
3	RxD	Tx+	Tx/Rx+
4	RTS#	N/A	N /A
5	TxD	Rx+	N /A
6	CTS#	N /A	N /A
7	DTR#	Rx-	N /A
8	RI#	N /A	N /A
9	GND	GND	GND

![The image displays a schematic diagram of a 10-pin dual in-line connector. It features a vertical rectangle with a thick black border and a gap on the left side. Inside the rectangle, ten small squares are arranged in two columns of five. The text '1' is positioned at the top left, '2' at the top right, '9' at the bottom left, and '10' at the bottom right.](.amstx-cf-50m-7a106-1020-12/b60ad061eba27d0b08a1fcf30bbbbe1f541305ac27500496f54a29035b33b094.jpg) # 5.2.7 CPU Fan and System Fan

Pin	Signal
1	FAN_GND
2	P_+12V_FAN
3	FAN_IN
4	FAN_OUT

![A simple line drawing of a rectangular device, resembling a remote control. It features a horizontal rectangular area at the top, a row of four square buttons in the middle, and the number 1 in the bottom right corner.](.amstx-cf-50m-7a106-1020-12/09aad2ab15553d461cb13f6e0467f43a0b7dc478929f5fea71d0696a0ca1be9d.jpg) # 5.2.8 GPU Fan

Pin	Signal
1	FAN_OUT
2	FAN_IN
3	P_+12V_FAN
4	FAN_GND

![A black and white line drawing depicting a connector assembly. The top section shows a rectangular housing, likely a plug shell. Below it, a vertical rectangular body represents the connector socket. Inside this body, there are two columns of small rectangular contacts: a left column with five contacts stacked vertically and a right column with three contacts stacked vertically. A large number '1' is centered within the connector body. A bracket shape is visible in the bottom right corner.](.amstx-cf-50m-7a106-1020-12/9bc7cade30b291aef4dc3c1ce569a6174b7648df99a2ebbe41de92716d0fa9be.jpg) # 5.2.9 Audio Pin Header (CN9)

Pin	Signal
1	AUDIO_Sense
2	SPK_RP
3	A_L_IN_L
4	SPK_RN
5	A_L_IN_R
6	GND_AUD
7	A_MIC_IN_L
8	SPK_LP
9	A_MIC_IN_R
10	SPK_LN

1 ![Pure electrical circuit lines without any symbols](.amstx-cf-50m-7a106-1020-12/8ac13b99a17a42370526a310a7828c0c66b9714c91d4500660dbc992a5ae1571.jpg) # 5.2.10 Power On Module Connector (CN12)

Pin	Signal
1	P_+5V0_A
2	P_+3V3_A
3	PWR_BTN#
4	LED_STANDBY
5	RST_BTN#
6	POWER_ON
7	RESET_BUTTON_ALARM#
8	PCH_SATS-L
9	LED_TEMP_ALARM
10	GND
11	LED_FAN_ALARM
12	GND
13	P_+12V_A
14	GND
15	BEEP_TEMP_ALARM
16	GND

1 ![The image displays a schematic diagram of a vertical rectangular connector. Inside the connector outline is a grid of 18 black squares arranged in 3 columns and 6 rows. To the right of the diagram is the number '2'.](.amstx-cf-50m-7a106-1020-12/6ca295265927b244844649fcb23c62f2e5b550ef67e352a425305d3a141df02e.jpg) # 5.2.11 DIO Connector (CN11)

Pin	Signal
1	5V_12V_S
2	GND
3	DI0
4	DI1
5	DI2
6	DI3
7	DO0
8	DO1
9	DO2
10	DO3

![The image displays a black and white line drawing of a vertical rectangular shape, resembling a schematic symbol for an electronic component. The shape has small rectangular protrusions at the very top and bottom. Inside the rectangle, there is a central vertical dashed line running down the middle. To the left of this central line is a column of small horizontal dashes, and to the right of the central line is a column of vertical dashes. To the right of the entire shape, the number '1' is visible.](.amstx-cf-50m-7a106-1020-12/5c18be9bff6c67ca6957396707adc504fd78566cba17aada4e98470b074c8dfb.jpg) # 5.2.12 12V DC-in Connector (CN3)

Pin	Signal
1	GND
2	DCIN
3	GND
4	DCIN
5	GND
6	DCIN
7	GND
8	DCIN

![The image shows a ten-frame grid (2 rows by 5 columns) containing nine filled squares, each featuring a central dot. The bottom-right square is empty. To the right of the grid, the number 2 is stacked directly above the number 1.](.amstx-cf-50m-7a106-1020-12/f29e25269be9f3293b45e6f9529ea6a827433401ba968b92f3940df6a4c269c7.jpg) # 5.2.13 PCB Edge Connector

Pin	Signal	Pin	Signal
A1 (pin 1 on bottom)	GND	B1 (pin 1 at top)	P_+12V_S
A2	P_+12V_S	B2	P_+12V_S
A3	P_+12V_S	B3	P_+12V_S
A4	GND	B4	GND
A5	JTAGE_CLK(NC)	B5	PCH_SMB_CLK_A
A6	JTAGE_DI(NC)	B6	PCH_SMB_DAT_A
A7	JTAGE_DO(NC)	B7	GND
A8	JTAGE_MS(NC)	B8	P_+3V3_S
A9	P_+3V3_S	B9	JTAGE_RST(NC)
A10	P_+3V3_S	B10	P_+3V3_A
A11	PCH_PLTRST-L_BUF	B11	X_PCIE_WAKE-L
A12	GND	B12	NC

![Diagram of a vertical spring scale with a separate circular component, labeled '1' (no text or symbols on the diagram itself)](.amstx-cf-50m-7a106-1020-12/625ac43d023ae07ba739a62d676a9c3657a98b3df2675ccf172a3eb6d34a129b.jpg)

Pin	Signal	Pin	Signal
A13	CLKOUT_PCIE_P7	B13	GND
A14	CLKOUT_PCIE_N7	B14	GF_PCIEX5_21_TX_P
A15	GND	B15	GF_PCIEX5_21_TX_N
A16	GF_PCIEX21_RX_P	B16	GND
A17	GF_PCIEX21_RX_N	B17	PCH_CLK_REQ7-L
A18	GND	B18	GND
A19	NC	B19	GF_PCIEX22_TX_P
A20	GND	B20	GF_PCIEX22_TX_N
A21	GF_PCIEX22_RX_P	B21	GND
A22	GF_PCIEX22_RX_N	B22	GND
A23	GND	B23	GF_PCIEX23_TX_P
A24	GND	B24	GF_PCIEX23_TX_N
A25	GF_PCIEX23_RX_P	B25	GND
A26	GF_PCIEX23_RX_N	B26	GND
A27	GND	B27	GF_PCIEX24_TX_P
A28	GND	B28	GF_PCIEX24_TX_N
A29	GF_PCIEX24_RX_P	B29	GND
A30	GF_PCIEX24_RX_N	B30	NC
A31	GND	B31	PCH_CLK_REQ7-L
A32	NC	B32	GND
A33	NC	B33	GF_PCIEX1_TX_P
A34	GND	B34	GF_PCIEX1_TX_N
A35	GF_PCIEX1_RX_P	B35	GND
A36	GF_PCIEX1_RX_N	B36	GND
A37	GND	B37	GF_PCIEX2_TX_P
A38	GND	B38	GF_PCIEX2_TX_N
A39	GF_PCIEX2_RX_P	B39	GND
A40	GF_PCIEX2_RX_N	B40	GND
A41	GND	B41	GF_PCIEX3_TX_P
A42	GND	B42	GF_PCIEX3_TX_N
A43	GF_PCIEX3_RX_P	B43	GND
A44	GF_PCIEX3_RX_N	B44	GND
A45	GND	B45	GF_PCIEX4_TX_P
A46	GND	B46	GF_PCIEX4_TX_N
A47	GF_PCIEX4_RX_P	B47	GND
A48	GF_PCIEX4_RX_N	B48	PCH_CLK_REQ7-L
A49	GND	B49	GND

# 5.2.14 DB40 Connector (CN18)

Pin	Signal	Pin	Signal
1	VCC_SPI_IN	21	TXD6
2	GND	22	RXD6
3	SPI_BIOS_CS0#	23	FUMD0
4	SPI_BIOS_CS1#	24	RESET_IN#
5	SPI_BIOS_MISO	25	DATA
6	SPI_BIOS_MOSI	26	CLK
7	SPI_BIOS_CLK	27	OCD0A
8	3V3_LPC	28	OCD0B
9	GND	29	PWRBTN#
10	BIOS_DIS0	30	SYS_RESET#
11	RST#	31	CB_RESET#
12	CLK33_LPC	32	CB_PWROK
13	LPC_FRAME#	33	SUS_S3#
14	LPC_AD3	34	SUS_S4#
15	LPC_AD2	35	SUS_S5#
16	LPC_AD1	36	POSTWDT_DIS#
17	LPC_AD0	37	SEL_BIOS
18	3.3V_SMC	38	BIOS_MODE
19	3.3V_A	39	SMC_STATUS
20	GND	40	RSVD

![Pure electrical connector pinout diagram without any text or symbols](.amstx-cf-50m-7a106-1020-12/22ace031a23df99c15c4f8eac099b159f467c053b4cc72d6d7470371e4537739.jpg) 5.2.15 LVDS Connector (CN21)

Pin	Signal	Pin	Signal
1	BLPWR_12V_5V	27	GND
2	BLPWR_12V_5V	28	LVDS_A2P_1
3	BLPWR_12V_5V	29	LVDS_A2N_1
4	BLPWR_12V_5V	30	GND
5	LVDS_BKLT_CTRL	31	LVDS_A1P_1
6	LVDS_BKLT_EN	32	LVDS_A1N_1
7	GND	33	GND
8	GND	34	LVDS_A0P_1
9	GND	35	LVDS_A0N_1
10	GND	36	GND
11	N/C	37	LVDS_B3P_1
12	N/C	38	LVDS_B3N_1
13	LCD_SEL68_CN	39	GND
14	LVDS_I2C_CLK_CN	40	LVDS_BCKP_1
15	LVDS_I2C_DAT_CN	41	LVDS_BCKN_1
16	PNLPWR_5V_3V	42	GND
17	PNLPWR_5V_3V	43	LVDS_B2P_1
18	GND	44	LVDS_B2N_1
19	PNLPWR_5V_3V	45	GND
20	PNLPWR_5V_3V	46	LVDS_B1P_1
21	GND	47	LVDS_B1N_1
22	LVDS_A3P_1	48	GND
23	LVDS_A3N_1	49	LVDS_B0P_1
24	GND	50	LVDS_B0N_1
25	LVDS_ACKP_1	51	GND
26	LVDS_ACKN_1

![Pure electrical connector diagram without any text, numbers, or symbols](.amstx-cf-50m-7a106-1020-12/87fcd68e6575ba02a4de2ea649de870511979d0d4f05127f5d655410e6dee70b.jpg) 5.2.16 Onboard Connector Information

Internal Connector			Cable ConnectorManufacturer Part No.
Signal	Connector No.	Manufacturer Part No.	Cable ConnectorManufacturer Part No.
USB 2.0 Pin Header	CN22	JVE, 23N6850-10S10B-01G-B-V9-01, black	EVERCONN 2032H-2x5P-3(2.0mm pitch)
USB 3.2 Gen1 x1 Pin Header	CN4	LOTES, ABA-USB-050-K08, blue	Shenzhen XINERCHANG Electronic Co. Ltd. USB3.0 2x10P(JCN-1D20FCHXXX)
PCIe Power Connector Pin Header	CN10	JVE, 24W1170-05S10-01T-3.4-CS01, white	EVERCONN 2530-1x5P(2.5mm pitch)
SATA Power Connector Pin Header	CN14	JVE, 24W1125A-06S10-01T-0.5-CF01, beige	JWT A1251H02-5P
COM Pin Headers	CN7/CN8	JVE, 23N6850-10S10B-01G-B-01, black	JWT A2005H00-2Cx5P(2.0mm pitch)
12V DC-in Connector	CN3	MOLEX, 39-30-0080, natural	MOLEX MOLEX, 39012085
Audio Pin Header	CN9	MOLEX, 87832-1006, black	MOLEX: 511101060 2x5P(2.0mm pitch)
Power On Module Connector	CN12	JVE, 23N6851-16M10B-01G-6-C-GR01-*R, black	JWT A2005H00-2DX8P(2.0mm pitch)
DIO Connector	CN11	JVE, 24W1125A-10S10-01T-0.5-C-CF01-*R, beige	JWT A1251H02-1x10P(1.25mm pitch)
LVDS Connector	CN21	JAE, FI-RE51S-HF-R1500	JAE Electronics FI-RE51HL

# 5.3 Jumper and Switch Settings # 5.3.1 Panel Backlight Power 5V/12 Selection (CN13)

Panel Power
2-4	5V
4-6	12V (default)

# 5.3.2 Panel Resolution Selection (CN13)

Panel Resolution
1-3	8-bit (default)
3-5	6-bit

![Pure electrical connector pinout diagram without any text or symbols](.amstx-cf-50m-7a106-1020-12/f3ff6875b8c888c4189c93c8cacf317b0f08ca26ff9359259a87f8087aa55c46.jpg) # 5.3.3 Case Open (CN6)

Case open
13-14	Function ON
N/A	Undo (default)

# 5.3.4 ME Lock (CN6)

ME Lock
15-16	Lock
N/A	Undo (default)

# 5.3.5 Clear CMOS (CN6)

Clear CMOS
17-18	Clear CMOS
N/A	Undo (default)

# 5.3.6 BIOS WP (CN6)

BIOS WP
19-20	BIOS WP
N/A	Undo (default)

# Multi-purpose Connector (CN6) ![Pure electrical connector pinout diagram without any text or symbols](.amstx-cf-50m-7a106-1020-12/9a0b2793da101e82acc1b86e8eb35dd2adac49499b6c10bcef2c337ecece1f87.jpg) # Notes: S3 and S4 not supported under operating system IAMT not supported while pairing with Q370 BIOS menu ME version information shows “zero” • Do not install an operating system when BIOS WP is enabled Intel GbE LAN cannot update MAC address Special PN/process needed if default setting is Write Protect Enabled for shipment # 5.3.7 RS-232/CCtalk Selection (CN6)

RS-232/CCtalk
1-3	RS-232 (default)
2-4
7-9
8-10
3-5	CCtalk
4-6
9-11
10-12

# 5.3.8 Data Format and Color Depth Selection (SW1)

Data Format and Color Depth
1-4_ON	18bpp
2-3_ON	VESA 24bpp
1-4,2-3 OFF	JEIDA 24bpp (default)

# 5.3.9 LVDS Channel Selection (SW2)

LVDS Channel
1-4_ON	VESA (default)
1-4_OFF	JEIDA
2-3_ON	Signal (default)
2-3_OFF	Dual

# 5.3.10 HSIO Selection (SW5)

HSIO selection
1-8_ON	CN24 lower connector support USB3.0 (Default)
1-8_OFF	M.2 B key support USB 3.0
2-7_ON	M.2 B key support SATA (Default)
2-7_OFF	M.2 B key support PCIe (BOM optional)
3-6 ON	M.2 B key support USB 3.0 (Default)
3-6 OFF	M.2 B key support PCIe (BOM optional)

# 5.3.11 LVDS VDD Selection (SW6)

LVDS VDD Selection
1-4_ON, 2-3_OFF	5V
1-4_OFF, 2-3_ON	3.3V (Default)

# 5.3.12 RI#, 5V, 12V Selection (SW7)

RI#, 5V, 12V Selection
1-8_ON, 2-7_OFF,3-6 OFF	5V
1-8_OFF, 2-7_ON,3-6 OFF	12V
1-8_OFF, 2-7_OFF,3-6 ON	RI# (default)

# 5.3.13 DIO Voltage Selection (SW8)

DIO Voltage Selection
1-4_ON, 2-3_OFF	5V
1-4_OFF, 2-3_ON	12V
1-4_OFF, 2-3_OFF	No power (Default)

# 5.3.14 Multi-IO Voltage Selection (SW9)

Multi-IO Voltage Selection
1-4_ON, 2-3_OFF	3.3V
1-4_OFF, 2-3_ON	5V
1-4_OFF, 2-3_OFF	No power (Default)

This page intentionally left blank. # 6 Driver Installation Download the drivers for your system from the AMSTX-CF product page at: https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/MicroSTX\_Motherboard/AMSTX-CF\_Series This page intentionally left blank. # 7 System Resources # 7.1 System Memory Map Table 4: System Memory Map

Address Range (Decimal)	Address Range (Hex)	Size	Description
(4GB – 2MB)	FFE00000 – FFFFFFFF	2 MB	High BIOS Area
(4GB – 18MB) – (4GB –17MB – 1)	FEE00000 – FEEFFFFFF	1 MB	MSI Interrupt
(4GB – 20MB) – (4GB – 19MB – 1)	FEC00000 – FECFFFFFF	1 MB	APIC Configuration Space
15MB – 16MB	F00000 – FFFFFFF	1 MB	ISA Hole
1MB – 15MB	100000 – EFFFFFF	14 MB	Main Memory
0K – 1MB	00000 – FFFFF	1 MB	DOS Compatibility Memory

# 7.2 I/O Map Table 5: IO Map

I/O Range (Hex)	Device
020h – 02Dh & 030h – 03Dh	Interrupt controller 1, 8259 equivalent
02Eh – 02Fh	Motherboard resource
040h – 043h & 050h – 053h	System Timer
04Eh – 04Fh	Motherboard resource
060h, 062h, 064h, 066h, 068h – 06Fh	8042 equivalent (keyboard)
061h, 063h, 065h, 067h	NMI control and status
070h – 077h	Real Time Clock Controller (bit 7 – NMI mask)
092h	Reset (Bit 0) / Fast Gate A20 (Bit 1)
0A0h – 0B1h & 0B4h – 0BDh	Interrupt Controller 2, 8259 equivalent
0B2h and 0B3h	APM control and status port respectively
0E0h – 0EFh	Available
0F0h	Co-processor error register
2F8h – 2FFh	Serial Port 2
3F8h – 3FFh	Serial Port 1
378h – 37Fh	Available
380h – 3AFh	Available
4D0h	Master PIC Edge/Level Trigger register
4D1h	Slave PIC Edge/Level Trigger register
0A00h – 0A2Fh	Reserved for SIO functions base address (e.g. PME/GPIO)
0CF8h – 0CFBh	PCI configuration address register (32-bit I/O only)
0CF9h	Reset Controller register (8-bit I/O)
0CFCh – 0CFFh	PCI configuration data register
1800h	PM (ACPI) Base Address for SB

# 7.3 Interrupt Request (IRQ) Lines # 7.3.1 IRQ Lines PIC Mode Table 6: IRQ Lines PIC Mode Note: Table lists IRQ lines mapping when APIC mode is disabled.

IRQ #	Typical Interrupt Resource	Connected to Pin	Available
0	Counter 0	N/A	No
1	Keyboard Controller	N/A	No
2	Cascade Interrupt from slave PIC	N/A	No
3	Serial Port 2 (COM2)	IRQ3 via SERIRQ/PIRQ	Note
4	Serial Port 1 (COM1)	IRQ4 via SERIRQ/PIRQ	Note
5	N/A	IRQ5 via SERIRQ/PIRQ	Note
6	N/A	IRQ6 via SERIRQ/PIRQ	Note
7	N/A	IRQ7 via SERIRQ/PIRQ	Note
8	Real-Time clock	N/A	No
9	Generic	N/A	No
10	N/A	IRQ10 via SERIRQ/PIRQ	Note
11	N/A	IRQ11 via SERIRQ/PIRQ	Note
12	N/A	IRQ12 via SERIRQ/PIRQ	No
13	Math Processor	N/A	No
14	Generic	N/A	No
15	N/A	N/A	Note

# 7.3.2 IRQ Lines APIC Mode Table 7 IRQ Lines APIC Mode Note: Table lists IRQ lines mapping when APIC mode is enabled.

IRQ #	Typical Interrupt Resource	Connected to Pin	Available
0	Counter 0	N/A	No
1	Keyboard Controller	N/A	No
2	Cascade Interrupt from slave PIC	N/A	No
3	Serial Port 2 (COM2)	IRQ3 via SERIRQ/PIRQ	No
4	Serial Port 1 (COM1)	IRQ4 via SERIRQ/PIRQ	No
5	N/A	IRQ5 via SERIRQ/PIRQ	No
6	N/A	IRQ6 via SERIRQ/PIRQ	No
7	N/A	IRQ7 via SERIRQ/PIRQ	No
8	Real-Time clock	N/A	No
9	Generic	N/A	No
10	N/A	IRQ10 via SERIRQ/PIRQ	No
11	N/A	IRQ11 via SERIRQ/PIRQ	No
12	N/A	IRQ12 via SERIRQ/PIRQ	No
13	Math Processor	N/A	No
14	Generic	N/A	No
15	N/A	N/A	No
16-511	Microsoft ACPI-Compliant System	N/A	Yes

# 7.4 PCI/PCIe Device # 7.4.1 PCI Configuration Space Map Table 8 PCI Configuration Space Map NOTE: The bus number changes when the PEG/PCIe port has a bridge device connected.

Bus Number	Device Number	Function Number	Routing	Description
0	0x00	0	N/A	Intel HOST Bridge - 6 Cores/Desktop
0	0x02	0	Internal	IGFX - GT2/6 or 8 Cores/Desktop
0	0x01	0	Internal	PEG Root Port D1F0
0	0x12	0	Internal	Thermal Subsystem
0	0x14	0	Internal	USB 3.1 xHCI HC
0	0x14	2	Internal	Shared SRAM
0	0x15	0	Internal	I2C Controller #0
0	0x15	1	Internal	I2C Controller #1
0	0x16	0	Internal	HECI #1
0	0x17	0	Internal	SATA Controller (AHCI)
0	0x1C	0	Internal	PCI Express* Root Port #1
0	0x1D	0	Internal	PCI Express* Root Port #9
0	0x1D	3	Internal	PCI Express* Root Port #12
0	0x1E	0	Internal	UART #0
0	0x1F	0	Internal	LPC Controller
0	0x1F	3	Internal	Intel® High Definition Audio Interface
0	0x1F	4	Internal	SMBus Controller
0	0x1F	5	Internal	SPI (flash) Controller
0	0x1F	6	Internal	GbE Controller

# 7.4.2 PCI Interrupt Routing Map Table 9 PCI Interrupt Routing Map

INT Line	Audio Controller	xHCI Controller	TXE Controller #1	LPC Controller	SATA Controller	SMBus Controller
Int0	INTA: 16	INTA: 16	INTA: 16	INTA: 16	INTA: 16	INTA: 16
Int1		INTB: 17	INTB: 17	INTB: 17
Int2		INTC: 18	INTC: 18	INTC: 18
Int3		INTD: 19	INTD: 19	INTD: 19

INT Line	PCIe Port 1	PCIe Port 5	PCIe Port 6	PCIe Port 11	PCIe Port 17	PCIe Port 21
Int0	INTA: 16	INTA: 16	INTB: 17	INTC: 18	INTA: 16	INTA: 16
Int1	INTB: 17	INTB: 17	INTC: 18	INTD: 19	INTB: 17	INTB: 17
Int2	INTC: 18	INTC: 18	INTD: 19	INTA: 16	INTC: 18	INTC: 18
Int3	INTD: 19	INTD: 19	INTA: 16	INTB: 17	INTD: 19	INTD: 19

# 7.5 SMBus Slave Addresses Table 10 SMBus Slave Addresses

Device	Address
DIMM A	0A0h
DIMM B	0A4h
BMC	050h
NXP	0C0h

This page intentionally left blank. # 8 Digital Input/Output Function Library DI/O provides input/output to support inter-device communications. Simple programming guides allow easy transmission of digital signals between the system and attached peripherals. # 8.1 DI/O with Windows API AMSTX-CF DI/O API library files and a demo program (including source code) can be downloaded from https://www.adlinktech.com/Products/Industrial\_Motherboards\_SBCs/MicroSTX\_Motherboard/AMSTX-CF\_Series To use the DI/O function library for the AMSTX-CF series, include the GpioLib.h header file and GpioLib.lib linkage library in the C++ project. DI/O functions are as follows. # GPIO\_Init This API checks if the GPIO driver handle is valid. char GPIO\_Init () # Return value: GPIO\_OK on success. GPIO\_ERROR on failure. # GPI\_Read This API reads the digital input (DI) pin status: char GPI\_Read(UCHAR GpioNum, PUCHAR data) # Argument: GpioNum: The number of a digital input pin (0-3) data: The digital input pin status will be copied to this address # Return value: GPIO\_OK on success. GPIO\_ERROR on failure. # GPO\_Write This API writes the new state of a digital output (DO): char GPO\_Write(UCHAR GpioNum,UCHAR GpioPortVal) # Argument: GpioNum: The number of a digital output pin (4-7). GpioPortVal: A new output state of 0 or 1. # Return value: GPIO\_OK on success. GPIO\_ERROR on failure # RegisterInterruptEvent This API is used to register the event when there is a change in the state of a digital input pin. char RegisterInterruptEvent(HANDLE Event, UCHAR Pin) # Argument: Event: Handle of the event waiting for interrupt notification. Pin: The number of an input pin. # Return value: GPIO\_OK on success. GPIO\_ERROR on failure # 9 DisplayPort BIOS Settings 9.1 MXM P1000/P2000/T1000/RTX3000/ RTX5000

BIOS Setting			DisplayPort
Primary Display	Internal Graphics	LVDS	Post Stage		Windows 10
Primary Display	Internal Graphics	LVDS	DP port from CPU	DP port from MXM	DP port from CPU	DP port from MXM
IGFX	Enable	Enable	Yes	No	Yes	Yes
PEG	Enable	Enable	No	Yes	No	Yes
Auto	Enable	Enable	No	Yes	No	Yes
IGFX	Disable	Enable	No	No	No	Yes
PEG	Disable	Enable	No	Yes	No	Yes
Auto	Disable	Enable	No	Yes	No	Yes
IGFX	Auto	Enable	Yes	No	Yes	Yes
PEG	Auto	Enable	No	Yes	No	Yes
Auto	Auto	Enable	No	Yes	No	Yes
IGFX	Enable	Disable	Yes	No	Yes	Yes
PEG	Enable	Disable	No	Yes	Yes	Yes
Auto	Enable	Disable	No	Yes	Yes	Yes
IGFX	Disable	Disable	No	No	No	Yes
PEG	Disable	Disable	No	Yes	No	Yes
Auto	Disable	Disable	No	Yes	No	Yes
IGFX	Auto	Disable	Yes	No	Yes	Yes
PEG	Auto	Disable	No	Yes	No	Yes
Auto	Auto	Disable	No	Yes	No	Yes

# 9.2 MXM P3000/P5000 (For four DP displays: use vBIOS 86.04.70.00.3D for P3000, and vBIOS 86.04.70.00.3C for P5000)

BIOS Setting			DisplayPort
Primary Display	Internal Graphics	LVDS	Post Stage		Windows 10
Primary Display	Internal Graphics	LVDS	DP port from CPU	DP port from MXM	DP port from CPU	DP port from MXM
IGFX	Enable	Enable	Yes	No	Yes	Yes
PEG	Enable	Enable	No	Yes	No	Yes
Auto	Enable	Enable	No	Yes	No	Yes
IGFX	Disable	Enable	No	Yes	No	Yes
PEG	Disable	Enable	No	Yes	No	Yes
Auto	Disable	Enable	No	Yes	No	Yes
IGFX	Auto	Enable	Yes	No	Yes	Yes
PEG	Auto	Enable	No	Yes	No	Yes
Auto	Auto	Enable	No	Yes	No	Yes
IGFX	Enable	Disable	Yes	No	Yes	Yes
PEG	Enable	Disable	No	Yes	Yes	Yes
Auto	Enable	Disable	No	Yes	Yes	Yes
IGFX	Disable	Disable	No	Yes	No	Yes
PEG	Disable	Disable	No	Yes	No	Yes
Auto	Disable	Disable	No	Yes	No	Yes
IGFX	Auto	Disable	Yes	No	Yes	Yes
PEG	Auto	Disable	No	Yes	Yes	Yes
Auto	Auto	Disable	No	Yes	Yes	Yes

# 10 BIOS Setup The Basic Input/Output System (BIOS) is a program that provides a basic level of communication between the processor and peripherals. In addition, the BIOS also contains codes for various advanced features applied to the AMSTX-CF Series. The BIOS setup program includes menus for configuring settings and enabling features of the AMSTX-CF Series. Most users do not need to use the BIOS setup program, as the AMSTX-CF Series ships with default settings that work well for most configurations. Enter BIOS setup by selecting DEL when the system is powered on the POST (Power On Self Test) message is displayed. The AMSTX-CF Series controller supports one-time Boot Menu allowing selection of boot device. Enter the Boot Menu by selecting F7 at POST. # NOTES: BIOS options listed are for reference only. Different configurations can affect BIOS behavior. Displayed material may reflect only the BIOS version corresponding to the initial release and may differ from that of the purchased motherboard. # 10.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

Main	Advanced	Chipset	Security
- BIOS Information- System Information- Processor Information- Memory Information- PCH Information- Board Information▶- System Date- System Time- Access level	- CPU Configuration ▶- Graphics Configuration ▶- Power Management ▶- System Management ▶- Thermal Management ▶- Watchdog Timer ▶- Super IO Configuration ▶- Serial Console Redirection ▶- Trusted Computing ▶- S5 RTC Wake Settings ▶- NVMe Configuration ▶- Network Stack Configuration ▶- RAM Disk Configuration ▶- Network Configuration ▶	- System Agent (SA)Configuration ▶- PCH-IO Configuration ▶	- Password Description- Administrator Password- User Password- Secure Boot menu ▶
Boot	Save & Exit
- Boot Configuration- Setup Prompt Timeout- Bootup NumLock State- Quiet Boot- Fast Boot- Boot Order	- Save Changes and Exit- Discard Changes and Exit- Save Changes and Reset- Discard Changes and Reset- Save Changes- Discard Changes- Restore Defaults- Save as User Defaults- Restore User Defaults- Boot Override

# Notes: ► indicates a submenu Gray text indicates info only # 10.2 Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings. 10.2.1 Main > BIOS Information

Feature	Options	Description
BIOS Information	Info only
BIOS Vendor	Info only	BIOS Vendor
BIOS Version	Info only	BIOS Version.
Build Date	Info only	BIOS build date
MRC Version	Info only	MRC Version
GOP Version	Info only	GOP Version
ME FW Version	Info only	ME FW Version

10.2.2 Main > System Information

Feature	Options	Description
System Information	Info only
Project Name	Info only	Project Name.

10.2.3 Main > Processor Information

Feature	Options	Description
CPU Board Version	Info only	CPU Board Version.
CPU Brand String	Info only	CPU Brand String.
Stepping	Info only	CPU Stepping.
GT Info	Info only	GT Info.
CPU Frequency	Info only	CPU Frequency.

10.2.4 Main > Memory Information

Feature	Options	Description
Total Memory	Info only	Total Memory
Memory Frequency	Info only	Memory Frequency

10.2.5 Main > PCH Information

Feature	Options	Description
PCH SKU	Info only	PCH SKU
Stepping	Info only	PCH Stepping

10.2.6 Main > Board Information > Board Information

Feature	Options	Description
Board Information	Info only
Serial Number	Info only	Serial Number
Manufacturing Date	Info only	Manufacturing Date
Last Repair Date	Info only	Last Repair Date
MAC ID	Info only	MAC ID

10.2.7 Main > Board Information > Runtime Statistics

Feature	Options	Description
Runtime Statistics	Info only
Total Runtime	Info only	Total Runtime
Current Runtime	Info only	Current Runtime
Power Cycles	Info only	Power Cycles
Boot Cycles	Info only	Boot Cycles
Boot Reason	Info only	Boot Reason

10.2.8 Main > System Data & Time

Feature	Options	Description
System Date	Weekday, MM/DD/YYYY	Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)
System Time	HH/MM/SS	Presented as a 24-hour clock setting in hours, minutes, and seconds

10.2.9 Main > Access level

Feature	Options	Description
Access	Level	Administrator / User

# 10.3 Advanced This menu contains the settings for most of the user interfaces in the system. 10.3.1 Advanced > CPU Configuration

Feature	Options	Description
CPU Configuration	Info only
Type	Info only	Displays the Processor Type
Package	Info only	Displays the Processor Package
Stepping	Info only	Displays the Processor Stepping.
Number of Processors	Info only	Displays number of CPU cores.
CPUID	Info only	Displays the Processor ID.
Microcode Revision	Info only	CPU Microcode Revision
Speed	Info only	Displays the Processor Speed.
L1 Data Cache	Info only	Displays the Processor L1 Data Cache size.
L1 Instruction Cache	Info only	Displays the Processor L1 Instruction Cache size.
L2 Cache	Info only	Displays the Processor L2 Cache size.
L3 Cache	Info only	Displays the Processor L3 Cache size.
L4 Cache	Info only	Displays the Processor L4 eDRAM size.
VMX	Info only	VMX Supported or Not
SMX/TXT	Info only	SMX/TXT Supported or Not
Active Processor Cores	All123	Number of cores to enable in each processor package.
Intel (VMX) Virtualization Technology	DisabledEnabled	When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.
Intel Trusted Execution Technology	DisabledEnabled	Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology.
Intel(R) SpeedStep(tm)	DisabledEnabled	Allows more than two frequency ranges to be supported.
Intel(R) Speed Shift Technology	DisabledEnabled	Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.
Turbo Mode	DisabledEnabled	Enable/Disable processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled).
C states	DisabledEnabled	Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.
C-State Auto Demotion	DisabledC1C3C1 and C3	Configure C-State Auto Demotion
C-State Un-demotion	DisabledC1C3C1 and C3	Configure C-State Un-demotion
Package C-State Demotion	DisabledEnabled	Package C-State Demotion
Package C-State Un-demotion	DisabledEnabled	Package C-State Un-demotion
Package C State Limit	C0/C1C2C3C6C7C7SC8C9C10Cpu DefaultAuto	Maximum Package C State Limit Setting. CpuDefault: Leaves to Factory default value.Auto:Initializes to deepest available Package C State Limit.
Tcc Activation Offset	0-63Default: 1	Offset from factory set Tcc activation temprature at which the Thermal Control Circuit must be activated.Tcc will be activated at: Tcc Activation Temp - Tcc Activation Offset. Tcc Activation Offset range is 0 to 63.

10.3.2 Advanced > Graphics Configuration

Feature	Options	Description
Graphics Configuration	Info only
LVDS	Info only
eDP/LVDS	DisabledEnabled	Enable/Disable eDP/LVDS
LFP Panel Type	VBIOS Default640x480800x6001024x7681280x10241400x10501266x7681600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536	Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.
Spreading depth	No Spreading0.5%1.0%1.5%2.0%2.5%	Clock frequency center spreading depth.
Data format and Color Depth	VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp	Data format and Color Depth select
LVDS Output Mode	Dual LVDS busSingle LVDS bus	Single/Dual mode select
DE Polarity	Active HighActive Low	DE Polarity select
Vsync Polarity	Active HighActive Low	Vsync Polarity select
Hsync Polarity	Active HighActive Low	Hsync Polarity select
LVDS Backlight Mode	BMC ModeGTT Mode	Select LVDS Backlight control function.
LVDS Backlight Brightness	BMC Mode: 0-255Default: 255	Set LVDS Backlight Brightness Percentage.A change takes effect immediately.
LVDS Backlight Brightness	GTT Mode: 0-100Default: 100

10.3.3 Advanced > Power Consumption

Feature	Options	Description
Power Consumption	Info only
Enable ACPI Auto Configuration	DisabledEnabled	Enables or Disables BIOS ACPI Auto Configuration.
Enable Hibernation	DisabledEnabled	Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.
ACPI Sleep State	Suspend Disabled S3 (Suspend to RAM)	Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.
Lock Legacy Resources	DisabledEnabled	Enables or Disables Lock of Legacy Resources
Restore AC Power Loss	Power OnPower OffLast State	Select AC power state when power is re-applied after a power failure.
Power Supply Unit	Emulate AT ModeATX Mode	ATX: OS will turn off system power when shutdown.NOTE: AT mode will not support S3 & S4, so it will change Power Loss State to Power On
PCI Express Wake	DisabledEnabled	Disable/Enable PCI Express Wake ping for PCIe device wake function
Power Consumption ▶	Sub-Menu	Power Consumption

# 10.3.4 Advanced > Power Consumption > Power Consumption

Feature	Options	Description
Power Consumption	Info only
Current Input Current	Info only	Current Input Current
Current Input Power	Info only	Current Input Power
VIN	Info only	VIN
VCORE	Info only	VCORE
RTC	Info only	RTC

# 10.3.5 Advanced > System Management

Feature	Options	Description
System Management	Info only
Version	Info only
SEMA Firmware	Info only	Version of SEMA Firmware
Build Date	Info only	Build Date of SEMA Firmware
SEMA Bootloader	Info only	Version of SEMA Bootloader
Build Date	Info only	Build Date of SEMA Bootloader
SEMA Features ▶	Sub-Menu	SEMA Features
Flags ▶	Sub-Menu	Flags
SPI ROM WP ▶	Sub-Menu	SPI ROM write protect
BIOS Post Update Menu	Sub-Menu	An update BIOS interface

10.3.6 Advanced > System Management > SEMA Features

Feature	Options	Description
SEMA Features	Info only
Uptime & Power Cycles Counter	Info only	Uptime & Power Cycles Counter
System Restart Event	Info only	System Restart Event
1024 Bytes User-Flash	Info only	1024 Bytes User-Flash
Watchdog	Info only	Watchdog
Temperatures	Info only	Temperatures
Voltage Monitor	Info only	Voltage Monitor
Display Backlight control	Info only	Display Backlight control
Power-Up Watchdog	Info only	Power-Up Watchdog
Power Monitor (current sense)	Info only	Power Monitor (current sense)
Boot Counter	Info only	Boot Counter
5V Input-Voltage	Info only	5V Input-Voltage
4mR Rsense for Input-Voltage	Info only	4mR Rsense for Input-Voltage
CPU Fan	Info only	CPU Fan
System Fan 1	Info only	System Fan 1
AT/ATX mode	Info only	AT/ATX mode
ACPI Thermal Trigger	Info only	ACPI Thermal Trigger
Backlight restore	Info only	Backlight restore
DTS register available	Info only	DTS register available
System Fan 2	Info only	System Fan 2
TIVA BMC	Info only	TIVA BMC
Board2 Temperature	Info only	Board2 Temperature
SEMA Error Log	Info only	SEMA Error Log
Soft Fan	Info only	Soft Fan

10.3.7 Advanced > System Management > Flags

Feature	Options	Description
Flags	Info only
BMC Flags	Info only	BMC Flags
BIOS Select	Info only	BIOS Select
ATX/AT-Mode	Info only	ATX/AT-Mode
Exception Code	Info only	Exception Code

10.3.8 Advanced > System Management > SPI ROM WP

Feature	Options	Description
SPI ROM Write Protect	DisabledEnabled	Enable/Disable SPI ROM Write Protect

10.3.9 Advanced > System Management > BIOS Post Update Menu

Feature	Options	Description
BIOS Post Update Menu	An update BIOS interface.
Choose BIOS Image	An interface let user to choose BIOS image in local storage device.
Start Flash	Start to flash BIOS

10.3.10Advanced > Thermal Management

Feature	Options	Description
Thermal Management	Info only
CPU Temperature	Info only
Current	Info only	Current of CPU temperature
Startup	Info only	Startup of CPU temperature
Min	Info only	Min of CPU temperature
Max	Info only	Max of CPU temperature
Board Temperatures	Info only
Current	Info only	Current of Board temperature
Startup	Info only	Startup of Board temperature
Min	Info only	Min of Board temperature
Max	Info only	Max of Board temperature
GPU Temperatures	Info only
Current	Info only	Current of GPU temperature
Startup	Info only	Startup of GPU temperature
Min	Info only	Min of GPU temperature
Max	Info only	Max of GPU temperature
CPU Fan Speed	Info only	CPU Fan Speed
System Fan Speed	Info only	System Fan Speed
GPU Fan Speed	Info only	GPU Fan Speed
Smart Fan ▶	Sub-Menu	Smart Fan
Critical Trip Point	Disabled80 C90 C95 C	This value is the temperature threshold of the Critical Trip Point.
Passive Cooling Trip Point	Disabled70 C80 C90 C99 C	This value is the temperature threshold of the Passive Cooling Trip Point.

10.3.11Advanced > Thermal Management > Smart Fan

Feature	Options	Description
Smart Fan	Info only
CPU Smart FanTemperature Source	CPU Sensor	CPU Smart FanTemperature Source
CPU Fan Mode	AUTO (Smart Fan)Fan OffFan On	CPU Fan Mode
Trigger Point 1	Info only
Trigger Temperature	0-100Default: 0	Trigger Temperature
PWM Level	0-100Default: 30	PWM Level
Trigger Point 2	Info only
Trigger Temperature	0-100Default: 65	Trigger Temperature
PWM Level	0-100Default: 55	PWM Level
Trigger Point 3	Info only
Trigger Temperature	0-100Default: 85	Trigger Temperature
PWM Level	0-100Default: 80	PWM Level
Trigger Point 4	Info only
Trigger Temperature	0-100Default: 92	Trigger Temperature
PWM Level	0-100Default: 100	PWM Level
System Smart FanTemperature Source	CPU Sensor	System Smart FanTemperature Source
System Fan Mode	AUTO (Smart Fan)Fan OffFan On	System Fan Mode
Trigger Point 1	Info only
Trigger Temperature	0-100Default: 0	Trigger Temperature
PWM Level	0-100Default: 30	PWM Level
Trigger Point 2	Info only
Trigger Temperature	0-100Default: 50	Trigger Temperature
PWM Level	0-100Default: 45	PWM Level
Trigger Point 3	Info only
Trigger Temperature	0-100Default: 65	Trigger Temperature
PWM Level	0-100Default: 65	PWM Level
Trigger Point 4	Info only
Trigger Temperature	0-100Default: 85	Trigger Temperature
PWM Level	0-100Default: 100	PWM Level
GPU Smart FanTemperature Source	GPU Sensor	GPU Smart FanTemperature Source
GPU Fan Mode	AUTO (Smart Fan)Fan OffFan On	GPU Fan Mode
Trigger Point 1	Info only
Trigger Temperature	0-100Default: 0	Trigger Temperature
PWM Level	0-100Default: 25	PWM Level
Trigger Point 2	Info only
Trigger Temperature	0-100Default: 45	Trigger Temperature
PWM Level	0-100Default: 50	PWM Level
Trigger Point 3	Info only
Trigger Temperature	0-100Default: 60	Trigger Temperature
PWM Level	0-100Default: 75	PWM Level
Trigger Point 4	Info only
Trigger Temperature	0-100Default: 80	Trigger Temperature
PWM Level	0-100Default: 100	PWM Level

10.3.12Advanced > Watchdog Timer

Feature	Options	Description
Watchdog Timer	Info only
Power-Up Watchdog	DisabledEnabled	The Power Up Watchdog resets the system after a certain amount of time after power up.
Timeout	0-65535Default: 65535	Here you can enter the time the Power Up Watchdog should wait until it resets the system.
ATTENTION: Pressing F12 during start up disables the Power Up Watchdog.	Info only
RunTime Watchdog	DisabledEnabled	The RunTime Watchdog resets the system after a certain amount of time after power up.
Timeout	0-65535Default: 24	Here you can enter the time the Power Up Watchdog should wait until it resets the system.
Watchdog ACPI Event Shutdown	DisabledEnabled	Watchdog ACPI Event Shutdown Enabled/Disabled

10.3.13Advanced > Super IO Configuration

Feature	Options	Description
Super IO Configuration	Info only
COM1 Device Settings	Info only	IO=3F8h; IRQ=4;
COM1 Control	RS232	Select COM1 mode. RS232 only
Ring1 Wake	DisabledEnabled	Disable/Enable RI ping for Wake On Ring function(PCH PME# signal)
COM2 Device Settings	Info only	IO=2F8; IRQ=3;
COM2 Control	RS232RS422RS485	Select COM2 mode. RS232, RS422 or RS485
Ring2 Wake	DisabledEnabled	Disable/Enable RI ping for Wake On Ring function(PCH PME# signal)

# 10.3.14Advanced > Serial Console Redirection

Feature	Options	Description
Serial Console Redirection	Info only
COM1	Info only
Console Redirection	DisabledEnabled	Console Redirection enable or disable.
Console Redirection Settings ▶	Submenu	The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.
COM2	Info only
Console Redirection	DisabledEnabled	Console Redirection enable or disable.
Console Redirection Settings ▶	Submenu	As above.

# 10.3.15Advanced > Console Redirection Settings [COM1-2]

Feature	Options	Description
COM[1-2]Console Redirection Settings	Info only
Terminal Type	VT100VT100+VT-UTF8ANSI	Emulation: ANSI: Extended ASCII char set. VT100:ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second	9600192003840057600115200	Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits	78	Data Bits.
Parity	NoneEvenOddMarkSpace	A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.
Stop Bits	12	Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow Control	NoneHardware RTS/CTS	Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop
VT-UTF8 Combo Key Support	DisabledEnable	Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode	DisabledEnable	With this mode enabled only text will be sent. This is to capture Terminal data.
Resolution 100x31	DisabledEnable	Enables or disables extended terminal resolution
Putty KeyPad	VT100LINUXXTERMR6SCOESCNVT400	Select FunctionKey and KeyPad on Putty.

10.3.16 Advanced > Trusted Computing [TPM 2.0 Configuration]

Feature	Options	Description
Configuration	Info only
Security Device Support	Disable Enable	Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.
TPM 2.0 Configuration	Info only
TPM20 Device Found	Info only
Firmware Version:	Info only
Vendor:	Info only
Security Device Support	Disable Enable	Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.
Active PCR banks	Info only
Available PCR banks	Info only
SHA-1 PCR Bank	DisabledEnabled	Enable or Disable SHA-1 PCR Bank
SHA256 PCR Bank	DisabledEnabled	Enable or Disable SHA256 PCR Bank
Pending operation	NoneTPM Clear	Schedule an Operation for the Security Device.NOTE: Your Computer will reboot during restart in order to change State of Security Device.
Platform Hierarchy	DisabledEnabled	Enable or Disable Platform Hierarchy
Storage Hierarchy	DisabledEnabled	Enable or Disable Storage Hierarchy
Endorsement Hierarchy	DisabledEnabled	Enable or Disable Endorsement Hierarchy
TPM2.0 UEFI Spec Version	TCG_1_2TCG_2	Select the TCG2 Spec Version Support
Physical Presence Spec Version	1.21.3	Select to Tell O.S. to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.
PH Randomization	DisabledEnabled	Enables or Disables Platform Hierarchy randomization. DO NOT ENABLE THIS QUESTION IN PRODUCTION PLATFORMS. THIS IS FOR DEVELOPMENT TESTING. OVERRIDE ChangePlatformAuth ELINK for production platforms supporting TXT.

10.3.17Advanced > S5 RTC Wake Settings

Feature	Options	Description
RTC Wake system from S5	DisabledFixed TimeDynamic Time	Enable or disable System wake on alarm event.Select FixedTime, system will wake on the hr::min::sec specified. Select DynamicTime, System will wake on the current time + Increase minute(s)
Wake up hour	0-23Default: 0	Range: 0-23 hrFor example enter 3 for 3am and 15 for 3pm
Wake up minute	0-59Default: 0	Range: 0-59 min
Wake up second	0-59Default: 0	Range: 0-59 sec
Wake up minute increase	1-5Default: 1	Range: 1-5 min

10.3.18Advanced > NVMe Configuration

Feature	Options	Description
NVMe Configuration	Info only
List NVMe Device	Info only

10.3.19Advanced > Network Stack Configuration

Feature	Options	Description
Network Stack	DisableEnable	Enable/Disable UEFI Network Stack
Ipv4 PXE Support	DisableEnable	Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.
Ipv4 HTTP Support	DisableEnable	Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.
Ipv6 PXE Support	DisableEnable	Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.
Ipv6 HTTP Support	DisableEnable	Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.
IPSEC Certificate	DisableEnable	Support to Enable/Disable IPSEC certificate for Ikev.
PXE boot wait time	0-5Default: 0	Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.
Media detect count	1-50Default: 1	Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.

10.3.20Advanced > [Network Name] Network Configuration

Feature	Options	Description
This sub-menu provided by device firmware, please refer to the actual layout.

10.3.21Advanced > RAM Disk Configuration

Feature	Options	Description
Disk Memory Type:	Boot Service Data Reserved	Specifies type of memory to use from available memory pool in system to create a disk.
Create raw ▶	Sub-Menu	Create a raw RAM disk.
Create from file ▶	Sub-Menu	Create a RAM disk from a given file.
Created RAM disk list:	Info only
Remove selected RAM disk(s)	Remove selected RAM disk(s)

10.3.22Advanced > RAM Disk Configuration > Create raw

Feature	Options	Description
Size (Hex):	Number	The valid RAM disk size should be multiples of the RAM disk block size.
Create & Exit	Yes	Create a new RAM disk with the given starting and ending address.
Discard & Exit	Yes	Discard and exit.

10.3.23Advanced > RAM Disk Configuration > Create from file

Feature	Options	Description
Create from file	Select file	Create a RAM disk from a given file.

# 10.4 Chipset 10.4.1 Chipset > System Agent (SA) Configuration

Feature	Options	Description
System Agent (SA) Configuration	Info only
SA PCIe Code Version	Info only	SA PCIe Code Version
VT-d	Info only	Supported or not
Memory Configuration ▶	Sub-Menu	Memory Configuration Parameters
Graphics Configuration ▶	Sub-Menu	Graphics Configuration
PEG Port Configuration ▶	Sub-Menu	PEG Port Options
VT-d	Disable Enable	VT-d capability
Above 4GB MMIO BIOS assignment	Disable Enable	Enable/Disable above 4GB MemoryMappedIO BIOS assignment

10.4.2 Chipset > System Agent (SA) Configuration > Memory Configuration

Feature	Options	Description
Memory Configuration	Info only
Memory RC Version	Info only	Memory RC Version
Memory Frequency	Info only	Memory Frequency
Memory Timings (tCL-tRCD-tRP-tRAS)	Info only	Memory Timings (tCL-tRCD-tRP-tRAS)
DIMM 1	Info only	DIMM 1 info
Size	Info only	Size of DIMM 1
Number of Ranks	Info only	Number of Ranks of DIMM 1
Manufacturer	Info only	Manufacturer of DIMM 1
DIMM 2	Info only	DIMM 2 info
Size	Info only	Size of DIMM 2
Number of Ranks	Info only	Number of Ranks of DIMM 2
Manufacturer	Info only	Manufacturer of DIMM 2
Memory Remap	Disable Enable	Enable/Disable Memory Remap above 4GB
Fast Boot	Disable Enable	Enable/Disable fast path thru the MRC

10.4.3 Chipset > System Agent (SA) Configuration > Graphics Configuration

Feature	Options	Description
Graphics Configuration	Info only
Graphics Turbo IMON Current	14-31Default: 31	Graphics turbo IMON current values supported (14-31)
Primary Display	AutoIGFXPEG	Select which of IGFX/PEG Graphics device should be Primary Display.
Internal Graphics	AutoDisabledEnabled	Keep IGFX enabled based on the setup options.
GTT Size	2MB4MB8MB	Select the GTT Size
DVMT Total Gfx Mem	128M256MMAX	Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.

10.4.4 Chipset > System Agent (SA) Configuration > PEG Port Configuration

Feature	Options	Description
PEG Port Configuration	Info only
PEG[Bus, Dev, Fun]	Info only	PEG location and info
Enable Root Port	DisabledEnabledAuto	Enable or Disable the Root Port
Max Link Speed	AutoGen1Gen2Gen3	Configure PEG[Bus, Dev, Fun] Max Speed
PCIe Spread Spectrum Clocking	DisableEnable	Allows disableing Spread Spectrum Clocking for compliance testing

10.4.5 Chipset > PCH-IO Configuration

Feature	Options	Description
PCH-IO Configuration	Info only
PCI Express Configuration ▶	Sub-Menu	PCI Express Configuration settings
SATA Configuration ▶	Sub-Menu	SATA Device Options Settings
USB Configuration ▶	Sub-Menu	USB Configuration settings
Security Configuration ▶	Sub-Menu	Security Configuration settings
HD Audio Configuration ▶	Sub-Menu	HD Audio Subsystem Configuration Settings
PCH digital I/O device	DisabledEnabled	Disable/Enable PCH digital I/O device
SPD Write Disable	TRUEFALSE	Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.

10.4.6 Chipset > PCH-IO Configuration > PCI Express Configuration

Feature	Options	Description
PCI Express Configuration	Info only
PCI Express Clock Gating	DisabledEnabled	Enabled PCI Express Clock Gating Enable/Disable for each root port.
Pcie PII SSC	Auto0.0%0.1%0.2%0.3%0.4%0.5%0.6%0.7%0.8%0.9%1.0%1.1%1.2%1.3%1.4%1.5%1.6%1.7%1.8%1.9%2.0%	Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.

10.4.7 Chipset > PCH-IO Configuration > SATA Configuration

Feature	Options	Description
SATA Configuration	Info only
SATA Mode Selection	AHCIIntel RST PremiumWith Intel OptaneSystem Acceleration	Determines how SATA controller(s) operate.
Serial ATA Port 0	Info only	SATA device info
Serial ATA Port 2	Info only	SATA device info
Serial ATA Port 3	Info only	SATA device info
Serial ATA Port 4	Info only	SATA device info

10.4.8 Chipset > PCH-IO Configuration > USB Configuration

Feature	Options	Description
USB Configuration	Info only
USB Overcurrent	DisabledEnabled	Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.
USB Overcurrent Lock	DisabledEnabled	Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data
USB Port Disable Override	Disable LinkSelect Per-Pin	Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.
U3_USB1_TX_P (EXTERNAL USB)	DisabledEnabled	Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.
U3_USB2_TX_P (EXTERNAL USB)	DisabledEnabled
U3_USB3_TX_P (EXTERNAL USB)	DisabledEnabled
U3_USB4_TX_P (EXTERNAL USB)	DisabledEnabled
U3_USB5_TX_P (PIN HEADER USB)	DisabledEnabled
U3_USB6_TX_P (PIN HEADER USB)	DisabledEnabled
U2_USB1_P (EXTRENAL USB)	DisabledEnabled
U2_USB2_P (EXTRENAL USB)	DisabledEnabled
U2_USB3_P (EXTRENAL USB)	DisabledEnabled
U2_USB4_P (EXTRENAL USB)	DisabledEnabled
U2_USB5_P (PIN HEADER USB)	DisabledEnabled
U2_USB6_P (PIN HEADER USB)	DisabledEnabled
U2_USB7_P (M.2 Key_B)	DisabledEnabled
U2_USB8_P (M.2 Key_E)	DisabledEnabled
U2_USB9_P (INTERNAL USB)	DisabledEnabled
U2_USB14_P (INTERNAL USB)	DisabledEnabled

# 10.4.9 Chipset > PCH-IO Configuration > Security Configuration

Feature	Options	Description
Security Configuration	Info only
BIOS Lock	DisabledEnabled	Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.

# 10.4.10Chipset > PCH-IO Configuration > HD Audio Configuration

Feature	Options	Description
HD Audio Configuration	Info only
HD Audio	DisabledEnabled	Control Detection of the HD-Audio device.

# 10.5 Security # 10.5.1 Security > Password Description

Feature	Options	Description
Password Description	Info only
Administrator Password	Enter password	Set Administrator Password
User Password	Enter password	Set User Password
Secure Boot menu ▶	Submenu	Secure Boot configuration

# 10.5.2 Security > Secure Boot menu

Feature	Options	Description
Secure Boot	Info only
System Mode	Info only	Setup / User / Audit / Deployed
Secure Boot	Info only	Active / Not Active
Vendor Keys	Info only	Valid / Modified
Secure Boot Control	DisabledEnabled	Secure Boot feature is Active if Secure Boot is Enabled,Platform Key(PK) is enrolled and the System is in User mode.The mode change requires platform reset
Secure Boot Mode	StandardCustom	Secure Boot mode options:Standard or Custom.In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication
Key Management ▶	Sub-Menu	Enables expert users to modify Secure Boot Policy variables without full authentication

# 10.5.3 Security > Secure Boot menu > Key Management

Feature	Options	Description
This sub-menu provided by AMI, please refer to the actual layout.

# 10.6 Boot # 10.6.1 Boot > Boot Configuration

Feature	Options	Description
Boot Configuration	Info only
Setup Prompt Timeout	1	Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.
Bootup NumLock State	On Off	Select the keyboard NumLock state.
Quiet Boot	Disabled Enabled	Enable or disables Quiet Boot option.
Fast Boot	Disabled Enabled	Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.
Boot Configuration	Info only
Boot Option #1	Hard Disk CD/DVD USB Hard Disk USB CD/DVD USB Key USB Floppy USB Lan Network Disabled	Hard Disk	Sets the system boot order
Boot Option #2		CD/DVD
Boot Option #3		USB Hard Disk
Boot Option #4		USB CD/DVD
Boot Option #5		USB Key
Boot Option #6		USB Floppy
Boot Option #7		USB Lan
Boot Option #8		Network
UEFI [Device] BBS Priorities ▶	Sub-Menu	Specifies the Boot Device Priority sequence from available UEFI device

# 10.6.2 Boot > Boot Configuration > UEFI [Device] BBS Priorities

Feature	Options	Description
Boot Option #[Num]	[Device]Disable	Sets the system boot order

10.7 Save & Exit

Feature	Options	Description
Save Changes and Exit	Yes No	Exit system setup after saving the changes.
Discard Changes and Exit	Yes No	Exit system setup without saving any changes.
Save Changes and Reset	Yes No	Reset the system after saving the changes.
Discard Changes and Reset	Yes No	Reset system setup without saving any changes.
Save Options	Info only
Save Changes	Yes No	Save Changes done so far to any of the setup options.
Discard Changes	Yes No	Discard Changes done so far to any of the setup options.
Restore Defaults	Yes No	Restore/Load Default values for all the setup options.
Save as User Defaults	Yes No	Save the changes done so far as User Defaults.
Restore User Defaults	Yes No	Restore the User Defaults to all the setup options.
Boot Override	Info only
Boot options	Do one time boot override to boot selected boot option.

# Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. Please keep this User‘s Manual for later reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables. • To avoid electrical shock and/or damage to equipment:  Keep equipment away from water or liquid sources. Keep equipment away from high heat or high humidity.  Keep equipment properly ventilated (do not block or cover ventilation openings). Make sure to use recommended voltage and power source settings.  Always install and operate equipment near an easily accessible electrical socket-outlet. Secure the power cord (do not place any object on/over the power cord).  Only install/attach and operate equipment on stable surfaces and/or recommended mountings.  If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. • Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. # Getting Service Ask an Expert: https://www.adlinktech.com/en/askanexpert # ADLINK Technology, Inc.

Address:	9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan
Tel:	+886-2-8226-5877
Fax:	+886-2-8226-5717
Email:	service@adlinktech.com

# Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd.

Address:	300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China
Tel:	+86-21-5132-8988
Fax:	+86-21-5132-3588
Email:	market@adlinktech.com

# ADLINK Technology GmbH

Address:	Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany
Tel:	+49-621-43214-0
Fax:	+49-621 43214-30
Email:	emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. [🔗 Link to the original document](.amstx-cf-50m-7a106-1020-12/amstx-cf-50m-7a106-1020-12.pdf)