# aTCA-6890

Intel® Xeon-based

AdvancedTCA Processor Blade

User's Manual

Manual Rev. 2.03

Revision Date: November 22, 2006

Part No: 50-1G001-1010

![The image features the universal recycling symbol in white against a black background. The symbol consists of three curved arrows arranged in a triangular loop, pointing in a clockwise direction.](.atca-6890-manual-10/2349ebe587dd816505c068ebfe74bae02d611c30874f99770e46d11229cddf46.jpg)
Recycled Paper

Copyright 2005 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance.

# ADLINK TECHNOLOGY INC.

Web Site: http://www.adlinktech.com

Sales & Service: Service@adlinktech.com

TEL: +886-2-82265877

FAX: +886-2-82265717

Address: 9F, No. 166, Jian Yi Road, Chungho City,

Taipei, 235 Taiwan

Please email or FAX this completed service form for prompt and satisfactory service.

<table><tr><td colspan="2">Company Information</td></tr><tr><td>Company/Organization</td><td></td></tr><tr><td>Contact Person</td><td></td></tr><tr><td>E-mail Address</td><td></td></tr><tr><td>Address</td><td></td></tr><tr><td>Country</td><td></td></tr><tr><td>TEL</td><td>FAX:</td></tr><tr><td>Web Site</td><td></td></tr><tr><td colspan="2">Product Information</td></tr><tr><td>Product Model</td><td></td></tr><tr><td>Environment</td><td>OS:M/B: CPU:Chipset: BIOS:</td></tr></table>

Please give a detailed description of the problem(s):

# Table of Contents

# Table of Contents...... i

# List of Tables...... iv

# List of Figures ...... v

# 1 Introduction ...... 1

1.1 Product Overview 1
1.2 Features.... 3
1.3 Main Functions 5

Processor 5
Memory Interface 5
PCI Express 7
Fabric Interface 7
Base Interface 8
PMC 8
Video 8
10/100/1000Mbit Ethernet Maintenance Port 8
Serial ATA Interface 8
USB 2.0 Interfaces 9
Serial Ports 9
Super I/O 9
IPMI Controller 9
EIDE Interface 9
CMOS Battery 10

1.4 aTCA-6890 Mechanical Layout 11

aTCA-6890 Board Layout 11
Front Panel LED Indicators and Reset 12

1.5 Unpacking Checklist 13

# 2 Connectors and Jumpers.... 15

2.1 Connector Pin Assignments 15

Serial Port (COM1)) 15
LAN RJ-45 Connector (LAN1, LAN2) 16
USB Connector (Port 0, Port 1) 16
VGA Connector (Front Panel) 17
SATA 0 (CN1) 17
IDE Connectors (CN2, CN3) 18

Zone 1 Connector .... 19

Zone 2-J23 Pin Assignment (PICMG 3.1 Option1) ..... 20

Zone 3 Pin Assignment 22

PMC Connectors 23

2.2 Jumper Settings 27

Clear CMOS Jumper (SWZ1) 27

# 3 Getting Started.... 29

3.1 CPU Installation 29

3.2 Memory Installation.... 32

3.3 Hard Drive Installation.... 34

3.4 Heat Sink Installation 35

3.5 CF Card Installation 41

3.6 aTCA Module Installation & Removal 42

3.7 Operating System Installation 47

# 4 Device Driver Installation.... 49

4.1 Intel® E7520 MCH/6300ESB ICH Chipset 49

4.2 VGA Driver Installation.... 50

4.3 LAN Driver Installation 51

# 5 Watchdog Timer.... 53

5.1 WDT Overview.... 53

5.2 Configuration Registers 55

Offset 10H: Base Address Register (BAR0) ..... 55

Preload Value 1 & 2 registers ....55

General Interrupt Status Register 55

Reload Register 56

Offset 60 - 61H: WDT Configuration Register ....56

Offset 68H: WDT Lock Register 56

5.3 GPIO Control Registers 57

WDT\_TOUT# Pin Selection 57

User LED Control 57

User LED Light 57

User LED Blink 57

5.4 WDT Programming Procedure.... 58

5.5 WDT Utilities 59

# 6 IPMC 61

6.1 IPMC Overview 61

6.2 FRU States 61

# 6 IPMC 61

6.1 IPMC Overview 61

6.2 FRU States 61

6.3 Accessing the IPMC 65

6.4 IPMI Command Set 67

6.5 Sensor Data Record List.... 69

6.6 FRU Storage Information.... 70

6.7 Firmware/FRU EEPROM Update 73

Update Procedures 73

6.8 Misc. Notes 76

# Warranty Policy.... 77

# List of Tables

Table 1-1: CPUs Validated for the ATCA-6890 5

Table 1-2: SMB Address Functionality 6

Table 1-3: PCI Express Configuration 7

Table 1-4: Fabric Interface Options 7

Table 1-5: LED Indicator Legend 12

Table 1-6: Base & Fabric Interface LEDs 12

Table 6-1: FRU States 63

Table 6-2: Supported IPMI Commands 67

Table 6-3: Discrete Based Sensors 69

# List of Figures

Figure 1-1: aTCA 6890 Functional Block Diagram ...... 2

Figure 1-2: aTCA-6890 Board Layout.... 11

Figure 1-3: Front Panel.... 12

Figure 3-1: Apply thermal grease to CPU(s).... 29

Figure 3-2: CPU Installation.... 30

Figure 3-3: Apply thermal pad to outside edge of the CPU ..... 31

Figure 3-4: Memory slot locations.... 32

Figure 3-5: Installing the Memory Modules.... 33

Figure 3-6: Hard Drive Installation 34

Figure 3-7: Pre-installation.... 35

Figure 3-8: Insulator.... 35

Figure 3-9: Dual processors.... 36

Figure 3-10: Heat Sink Installation.... 36

Figure 3-11: Heatsink Alignment.... 37

Figure 3-12: Screw Alignment.... 37

Figure 3-13: Tightening screws 38

Figure 3-14: Order of screws 38

Figure 3-15: Phase-Change Material.... 39

Figure 3-16: Thermal Grease.... 39

Figure 3-17: Clean CPU 40

Figure 3-18: Volume of Grease.... 40

Figure 3-19: Spread the Grease 40

Figure 3-20: Insert the aTCA module into chassis guide rails ..... 42

Figure 3-21: Ensure that catch hooks and alignment pins are correctly inserted.... 43

Figure 3-22: Incorrect alignment of the catch hook.... 44

Figure 3-23: Push the ejector handles into faceplate.... 45

Figure 3-24: Close the ejector handles 45

Figure 3-25: Lock the module 46

Figure 5-1: WDT Block Diagram 54

Figure 6-1: FRU State Transitions 62

Figure 6-2: ATCA System Management Architecture...... 66

# 1 Introduction

# 1.1 Product Overview

The aTCA-6890 is the dual 64bit Intel® LV-Xeon processor based AdvancedTCA blade. It supports Intel® EM64T 64-bit technology and dual channel DDR2-400 REG/ECC system memory up to 16GB capacity. For data transport connectivity, it features dual 1000BASE-T GbE Base Interface channels and field-configurable quad 1000BASE-BX GbE Fabric Interface ports compliant with PICMG 3.1 Option1 or 2.

The front panel I/O includes dual 64-bit 66/100/133MHz PCI/PCI-X PMC sites, USB 2.0 ports, 1000BASE-T GbE ports, one analog video and a serialconsole. On-board peripherals includes two ATA100 channels withon-board DMA-enabled CF slot and one SATA 2.5" HDD site.

Compatible Rear Transition Module (RTM) features RAID0/1 SATA 2.5" HDD and PMC I/O module (PIM, VITA36). The Serial-Attached-SCSI (SAS) and Encryption expansion modules are also available.

Please refer to the following block diagram for the aTCA-6890 architecture.

Block Diagram
![Based on the provided block diagram, here is the description of the labeled blocks and their connections:\n\n**Blocks:**\n*   **Memory/CPU:** 'Dual Channel PC3200', 'DDR2-400 REF/ECC' (4 instances), 'Intel® Xeon Processor' (2 instances).\n*   **Central Chipsets:** 'Intel® E7520 MCH', 'Intel® 6700PXH' (2 instances), 'Intel® 6300ESB ICH'.\n*   **Network/Interface:** 'Intel® 82546GB' (4 instances), 'SATA', 'FWH', 'Super I/O', 'PPS IPMC'.\n*   **Peripherals/IO:** 'FRONT PANEL' (containing 'PMC1', 'PMC2'), 'ATI® RageXL', 'WDT', 'ATA100' (2 instances), 'CF SKT'.\n*   **Zones:** 'ZONE 1', 'ZONE 2', 'ZONE 3'.\n\n**Connections:**\n*   **Top Section:** Four 'DDR2-400 REF/ECC' blocks (under 'Dual Channel PC3200') connect to the two 'Intel® Xeon Processor' blocks. Both processors connect to 'Intel® E7520 MCH' via a line labeled 'FSB-800M'. A dashed line labeled 'PCIE x4' connects the right Xeon processor to the right 'Intel® 6700PXH'.\n*   **Central Hub:** 'Intel® E7520 MCH' connects to the left 'Intel® 6700PXH' via 'PCIE x8' and to the right 'Intel® 6700PXH' via 'PCIE x8'. It connects downward to 'Intel® 6300ESB ICH' via 'HI v1.5'.\n*   **Left Side:** The left 'Intel® 6700PXH' connects to the 'FRONT PANEL' (specifically 'PMC1' and 'PMC2', labeled 'PIM') via 'PCI-X 64b/133M'. 'GbE 2x' connects an 'Intel® 82546GB' block to the ICH via 'PCI-X 64b/66M'. 'RGB' connects 'ATI® RageXL' to the ICH via 'PCI 32b/33M'. 'USB1/2, COM1' connects the 'FRONT PANEL' directly to the ICH.\n*   **Right Side (Top):** The right 'Intel® 6700PXH' connects to three 'Intel® 82546GB' blocks leading to 'ZONE 2'.\n    *   Top connection: Via 'PCI-X 64b/100M' through 'Fabric I/F'.\n    *   Middle connection: Through 'Fabric I/F'.\n    *   Bottom connection: Via 'PCI-X 64b/1133M' through 'Base I/F'.\n*   **Right Side (Bottom/Zone 3):** 'Intel® 6300ESB ICH' connects to a 'SATA' block via 'SATA 2x'. It also connects to 'ZONE 3' via dashed lines labeled 'PCIe x4', 'SATA 2x', 'USB 3/4', 'KB/MS', 'PIM 1x', and 'COM2'.\n*   **Bottom Section:** 'Intel® 6300ESB ICH' connects to 'WDT', two 'ATA100' blocks, and 'CF SKT'. It connects via 'LPC' to 'FWH' and 'Super I/O'. 'FWH' connects to 'Super I/O' via 'COM3'. 'Super I/O' connects to 'PPS IPMC' via 'KB/MS'. Finally, 'PPS IPMC' connects to 'ZONE 1' via 'IPMB0/1'.](.atca-6890-manual-10/a8b06190efeaff887976c35ebb234297c2c7b9375fbeaf9f8e7311bdb9d98f90.jpg)

Figure 1-1: aTCA 6890 Functional Block Diagram

# 1.2 Features

The features of the aTCA-6890 are as follows:

▶ 800MHz FSB
▶ 1MB L2 Cache
▶ Hyper-Threading Processors
Intel® EM64T 64-bit Extended Memory Technology
▶ Dual DDR2-400 REG/ECC Channels with 16GB Maximum Capacity
Intel® E7520/6300ESB/6700PXH Chipset
▶ Dual 64-bit 33/66/100/133MHz PCI/PCI-X PMC with PIM
▶ Quad 1000BASE-BX GbE Fabric Interface Channels
▶ Configurable PICMG 3.1 Option1/2 Compliant
▶ RAID 0/1 Enabled RTM
▶ CPU: Dual 64bit Intel LV-Xeon 800FSB 2.8GHz
▶ Chipset: Intel E7520 MCH, 6300ESB ICH, 6700PXH Bridge
▶ Memory: Four DDR2-400 REG/ECC 240pin DIMM slots, up to 16GB capacity
▶ Flash: Award BIOS with 4Mb flash memory supporting Intel PXE pre-boot and serial console redirection
▶ Graphics: ATI® RageXL with 8MB VRAM, up to QXGA (2048 x 1536) resolution
▶ PMC
▷ PMC1: PCI/PCI-X 64-bit 66/100/133MHz capable with PIM
▷ PMC2: PCI/PCI-X 64-bit 66/100/133MHz capable
▶ LAN: Intel® 82546EB (GB) PCI-X dual port Gigabit Ethernet controllers
▷ Dual 10/100/1000BASE-T Base interface channels
▶ Quad 1000BASE-BX fabric interface channels
▷ Dual 10/100/1000BASE-T front panel access
▶ Storage: Dual ATA-33/66/100 channels
On-board DMA-enabled CompactFlash socket
On-board 2.5" ATA/SATA HDD kits

▶ USB: Dual USB v2.0 ports
▶ Front Panel I/Os: PMC1/2, VGA, USB1/2, LAN1/2, COM1
▶ Standards
▷ PICMG 3.0 R2.0 ECN001
▷ PICMG 3.1 Ethernet over PICMG 3.0, R1.0 Option 1/2
▷ PICMG 3.0 R2.0 ECN001
▷ PICMG 3.1 Ethernet over PICMG 3.0, R1.0 Option 1/2

# 1.3 Main Functions

This section details the major functional blocks in the aTCA-6890. The user interconnects and options are detailed.

# Processor

The aTCA-6890 processor blade is designed for single Xeon™ or single/dual Low Voltage Xeon™ “Nocona” processors. Processors compatible with the aTCA-6890 are 90nm, 800MHz System Bus, 1MB of L2 cache and are in a 604 pin FCmPGA4 package. The processor used must be compatible with the E7520 MCH. Use of other Xeon processors might cause damage to the aTCA-6890 or processor. When using dual processors both processors must be the same S-Spec number. The aTCA-6890 is designed to be used with ADLINK’s thermal solution. Do not attempt to use the thermal solution provided in some of the boxed processor packages. The aTCA-6890 has been validated with the following long life processors:

<table><tr><td>Type</td><td>Speed</td><td>System Bus</td><td>Power</td><td>Max Temp</td><td>L2 Cache</td><td>Intel Part Number</td></tr><tr><td>Xeon</td><td>3.2GHz</td><td>800MHz</td><td>103W</td><td>80°C</td><td>1MB</td><td>RK80546KG0881M</td></tr><tr><td>LV Xeon</td><td>2.8GHz</td><td>800MHz</td><td>55W</td><td>86°C</td><td>1MB</td><td>RK80546KG0721M</td></tr></table>

Table 1-1: CPUs Validated for the ATCA-6890

# Memory Interface

The Intel® E7520 MCH chipset supports two channels of registered DDR-II 400 (stacked or unstacked) memory. Peak theoretical memory bandwidth is 6.4GB/s. The maximum memory configuration supported is 16GB. The memory controller supports: memory mirroring which keeps a duplicate copy of data in the memory subsystem; memory hot-swap that allows removal of a defective DIMM without bringing down the system (not of use in aTCA); DIMM sparing which allows for one DIMM per channel to be held in reserve and brought on line if another DIMM becomes defective (DIMM sparing and mirroring are mutually exclusive); hardware memory scrubbing; retry on uncorrectable memory errors; 4x SDDC for memory error detection and correction of any number of bit failures in a single x4 memory device.

The memory controller supports two channels of memory, Channel A and Channel B. Each channel contains two SIMM sockets for a total of 4 DIMM sockets. The aTCA-6890 can be populated with one, two or four DIMM modules. When only one DIMM is used, it can be populated on either DDRII-A2 or DDRII-B2 socket. In case of two DIMMs, they can be populated on either DDRII-A2 and DDRII-B2 (dual channel mode), DDRII-A1 and DDRII-A2 or DDRII-B1 and DDRII-B2 (single channel mode). To achieve maximum memory throughput, ensure that sockets A1 and B1 and/or A2 and B2 have identically configured DIMM modules.

The table below outlines the aTCA-6890's memory interface SMB address functionality:

<table><tr><td>SMB Address</td><td>Function</td></tr><tr><td>A4h</td><td>DDRII Channel A DIMM 1</td></tr><tr><td>A6h</td><td>DDRII Channel A DIMM 2</td></tr><tr><td>ACh</td><td>DDRII Channel B DIMM 1</td></tr><tr><td>AEh</td><td>DDRII Channel B DIMM 2</td></tr></table>

Table 1-2: SMB Address Functionality

# PCI Express

The E7520 MCH provides three x8 PCI Express interfaces. Each PCI-E interface can be configured as one x8 or two x4 links. Currently, two of the x8 ports are connected to two 6700PXH bridges, and the 3rd interface is configured as one x4 link to Zone 3 for future use.

<table><tr><td>PCI Express Port</td><td>Lower x4 Interface</td><td>Upper x4 Interface</td></tr><tr><td>A</td><td colspan="2">PXH</td></tr><tr><td>B</td><td>NC</td><td>RTM</td></tr><tr><td>C</td><td colspan="2">PXH</td></tr></table>

Table 1-3: PCI Express Configuration

# Fabric Interface

The aTCA-6890 (configured by SWY2-Pin4) provides 4 gigabit Ethernet interfaces to the Fabric Interface using 2 82546 dual gigabit Ethernet controllers. The Fabric Interface can be configured to run in two modes, PICMG 3.1, Option1 and Option2, configured by on-board DIP-switch SWY2-Pin4. In PICMG 3.1 Option1 mode, each GbE port is linked to Port0 of Fabric Interface Channel 1-4 (FCH[1:4]P0). The other mode complies with PICMG 3.1, Option 2, which configures the four GbE ports to Port0-1 of Fabric Interface Channel 1-2 (FCH[1:2]P[0:1]). As shipped, the aTCA-6890 is configured to operate in the PICMG 3.1 Option 1 mode. Refer to the table below for details.

<table><tr><td colspan="2"></td><td colspan="2">PICMG 3.1 Option</td></tr><tr><td>Ethernet Controller</td><td>Interface</td><td>Fabric Channel and Port (3.1 Option 1)</td><td>Fabric Channel and Port (3.1 Option 2)</td></tr><tr><td rowspan="2">1</td><td>A</td><td>FCH1P0</td><td>FCH1P0</td></tr><tr><td>B</td><td>FCH2P0</td><td>FCH2P0</td></tr><tr><td rowspan="2">2</td><td>A</td><td>FCH3P0</td><td>FCH1P1</td></tr><tr><td>B</td><td>FCH4P0</td><td>FCH2P1</td></tr></table>

Table 1-4: Fabric Interface Options

# Base Interface

The aTCA-6890 supports two Gigabit Ethernet connections to the Base Interface using a single 82546 dual channel Gigabit Ethernet controller.

# PMC

The aTCA-6890 contains 2 PMC sites. Both PMC sites are keyed for 3.3V V(I/O). Each PMC site sits on an independent PCI-X bus. Each PMC can run at 64 bit up to 133MHz PCI-X. The PMC sites are on independent busses so the use of a slow speed PMC on one site will not impact performance of the other PMC. The upper PMC supports rear I/O out the Zone 3 connector. Contact ADLINK for information on Rear Transition Modules compatible with the aTCA-6890.

# Video

The video interface is provided with a ATI Rage XL video controller. The video controller is on a 32 bit 33MHz PCI bus. Video memory of 8M bytes is available with resolutions up to QXGA (2048 x 1536). CRT signals are routed to the front panel only.

# 10/100/1000Mbit Ethernet Maintenance Port

Two 10/100/1000Mbit Ethernet ports are provided on the front panel.

# Serial ATA Interface

Two SATA 150MB/s interfaces are provided. The SATA controllers are completely software transparent with the IDE (ATA) interface while providing lower pin count, higher performance and software RAID 0/1 features are available in BIOS options to be enabled on the two SATA ports. The two SATA host controllers are capable of independent DMA operation. The 2.5" SATA HDD mounting kit for two 2.5" drives is available on RTM.

For users only need one SATA HDD on PMC1 site, please contact with ADLINK FAE for installation instructions.

# USB 2.0 Interfaces

Four USB 2.0 interfaces are provided by the ICH. Two of the USB 2.0 interfaces are routed to the front panel and the remaining two interfaces are routed to the Zone 3 connector.

# Serial Ports

One of the ICH serial port is designed to front panel in RJ-45 jack, and the other from ICH is routed to RTM I/O. The COM3 provided by SuperI/O is dedicated to IPMC payload port as the host interface. The ports are 16550 compatible and will support 16550 compatible operation up to 115 kilobaud. The serial ports are relocatable in ISA I/O memory Map. The serial ports are ESD protected to 15KV.

# Super I/O

The super I/O provides legacy controllers. It should be noted that the front board does not support PS/2 keyboard or mouse devices or parallel printer devices. These functions are intended to be provided using USB. Previous experiences have shown that some BIOS and operating software require that a keyboard controller register be present for proper operation. The SIO selected contains a keyboard controller but the keyboard port is not connected. The controller is provided for software compatibility reasons only. The PS/2 keyboard and mouse interfaces are routed to Zone 3 for use with the aTCA-6890 RTM.

# IPMI Controller

The IPMI controller is based on the Pigeon Point Systems IPMC. It is fully compliant with the aTCA specification. Please refer to the appendix A for more information about IPMC.

# EIDE Interface

Two optional 2.5" on-card ATA hard drive sites are available. The drives connect to ATA ports provided by the Intel® 6300ESB ICH. Each hard drive will take the space of one PMC site. We recommend using the upper PMC site for an optional on-board hard disk drive.

# CMOS Battery

The real time clock and CMOS backup battery are socketed. The battery circuite has a series resistor and diode to conform to industry safety requirements. The battery has an expected shelf life of at least five years.

# 1.4 aTCA-6890 Mechanical Layout

aTCA-6890 Board Layout
![Green printed circuit board with various electronic components and connectors (no readable text or symbols)](.atca-6890-manual-10/18c7aa836beb4621d7c2905b13546bdb748c7534b750369ec6986353162493b8.jpg)

Figure 1-2: aTCA-6890 Board Layout

# Front Panel LED Indicators and Reset

Front panel LEDs provide feedback to the user on the state of the aTCA-6890. A front panel reset switch is provided to allow a hard reset of the board.

<table><tr><td>LED</td><td>Color</td><td>Function</td></tr><tr><td>OOS</td><td>Red</td><td>Out Of Service:Indicates that the aTCA-6890 is not functional</td></tr><tr><td>HD</td><td>Green</td><td>Hard Disk: Indicates hard drive activity</td></tr><tr><td>USR</td><td>Amber</td><td>Indicates power on</td></tr><tr><td>HS</td><td>Blue</td><td>Hot Swap: Indicates that the board can be removed</td></tr></table>

Table 1-5: LED Indicator Legend

<table><tr><td colspan="2">&lt;img src="images/950474fbef7aa215c71a8c9ec2759507f18876bded6e6e0250ea6957deb31bab.jpg"/&gt;</td></tr><tr><td>BCH1</td><td>1. Link/Activity LED, amber2. Speed LED, 1Gbps-amber; 10/100Mbps-green</td></tr><tr><td>BCH2</td><td>Same as BCH1</td></tr><tr><td>Fabric I/F CH1</td><td>Fabric Interface Channel 1Link/Activity LED</td></tr><tr><td>Fabric I/F CH2</td><td>Same as FCH1</td></tr><tr><td>Fabric I/F CH3</td><td>Same as FCH1</td></tr><tr><td>Fabric I/F CH4</td><td>Same as FCH1</td></tr></table>

Table 1-6: Base & Fabric Interface LEDs

![ADLINK\nPMC1\nOSS HD USR\nVGA\nUSB\nLAN1\nLAN2\nCOM\nBCH1 BCH2\nFABRIC IF CH\nReset button HS\nVGA\nUSB\nLAN1\nLAN2\nCOM\nPMC2\nPMC1](.atca-6890-manual-10/d7939939266ea9a9e31a0e0ccdfbc604dd71fd0a7af678097a1148ec7f742bf6.jpg)

Figure 1-3: Front Panel

# 1.5 Unpacking Checklist

Check the shipping carton for any damage. If the shipping carton and contents are damaged, notify the dealer for a replacement. Retain the shipping carton and packing materials for inspection by the dealer. Obtain authorization before returning any product to ADLINK.

Check the following items are included in the package, if there are any items missing, please contact your dealer:

<table><tr><td>Included Items</td></tr><tr><td>aTCA-6890 processor blade (CPU, RAM, and hard drive specifications will differ depending on options selected)</td></tr><tr><td>Heat sink</td></tr><tr><td>IDE HDD mounting kit</td></tr><tr><td>SATA HDD mounting kit</td></tr><tr><td>COM port RJ45-to-DB9 adapter</td></tr><tr><td>ADLINK All-in-One CD</td></tr><tr><td>This user&#x27;s manual</td></tr></table>

# Note:

The packaging of the aTCA-6890 OEM version with non-standard configuration, functionality, or package may vary according to different configuration requests.

# CAUTION:

![The image displays a standard yellow triangular warning sign with a thick black border. Centered inside the triangle is a red exclamation mark. Above the triangle is a black horizontal bar.](.atca-6890-manual-10/a40c75b86b0dca4773b13dd46e405034ccf6fe1735eb36b1d8da9b65132e9e66.jpg)

The aTCA-6890 processor blade must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the board. Wear a grounded wrist strap when servicing.

# 2 Connectors and Jumpers

This chapter will familiarize the user with the connectors and jumpers on the aTCA-6890.

# 2.1 Connector Pin Assignments

Detailed descriptions and pin-outs for each connector are given in the following section. Please refer to Figure 1-2: aTCA-6890 Board Board Layout and Figure 1-3: aTCA-6890 Front Panel for connector locations.

# Serial Port (COM1))

![Pin 1\nPin 2\nPin 3\nPin 6](.atca-6890-manual-10/ee1021b8d088b4644ca02853516bb4dd7435fe84635d75be988336d0c9afc5d7.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>DCD#</td><td>Data Carrier Detect</td></tr><tr><td>2</td><td>RTS#</td><td>Request to Send</td></tr><tr><td>3</td><td>DSR#</td><td>Data Set Ready</td></tr><tr><td>4</td><td>TXD</td><td>Transmit Data</td></tr><tr><td>5</td><td>RXD</td><td>Receive Data</td></tr><tr><td>6</td><td>GND</td><td>Ground</td></tr><tr><td>7</td><td>CTS#</td><td>Clear to Send</td></tr><tr><td>8</td><td>DTR#</td><td>Data Terminal Ready</td></tr></table>

# Com Port Signal Definitions:

CTS Indicates that data set is ready to exchange data.

DCD Indicates data set has detected the data carrier.

DSR Indicates that data set is ready to establish a communications link.

DTR Indicates that a data set is ready to establish a communications link.

RI Indicates that a modem has received a telephoning signal.

RTS Indicates to data set that UART is ready to exchange data.

RX Receives serial data input from communications link.

TX Sends serial output to communications link.

# LAN RJ-45 Connector (LAN1, LAN2)

![green\nPin 1\nPin 2\nPin 3\nPin 6\nyellow](.atca-6890-manual-10/5ee48b7745074f29bc4149b5845952fb08bf701a686898462e6301746d35bf68.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>MDX0+</td><td rowspan="2">Pair 0</td></tr><tr><td>2</td><td>MDX0-</td></tr><tr><td>3</td><td>MDX1+</td><td rowspan="2">Pair 1</td></tr><tr><td>4</td><td>MDX1-</td></tr><tr><td>5</td><td>MDX2+</td><td rowspan="2">Pair 2</td></tr><tr><td>6</td><td>MDX2-</td></tr><tr><td>7</td><td>MDX3+</td><td rowspan="2">Pair 3</td></tr><tr><td>8</td><td>MDX3-</td></tr></table>

<table><tr><td>LED Color</td><td>Status</td><td>Function</td></tr><tr><td rowspan="2">Green (speed)</td><td>ON</td><td>1000Mbps</td></tr><tr><td>OFF</td><td>100Mbps</td></tr><tr><td rowspan="3">Yellow (link)</td><td>ON</td><td>Link</td></tr><tr><td>OFF</td><td>Link off</td></tr><tr><td>blinking</td><td>Data transfer in progress</td></tr></table>

# USB Connector (Port 0, Port 1)

![4\n3\n2\n1](.atca-6890-manual-10/3dc026f4ad18a0d9a92f573d294af45c7d06ad3f51c5df739238b031ffc5bf86.jpg)

<table><tr><td>PIN</td><td>SIGNAL</td></tr><tr><td>1</td><td>VCC</td></tr><tr><td>2</td><td>USB-</td></tr><tr><td>3</td><td>USB+</td></tr><tr><td>4</td><td>Ground</td></tr></table>

# VGA Connector (Front Panel)

![5\n10\n15\n11](.atca-6890-manual-10/ba534b65323c8e27ac34ed36b5af990cd057bea2165defc86d1e9c74dc2d4d22.jpg)

<table><tr><td>Pin</td><td>Signal Name</td><td>Pin</td><td>Signal Name</td></tr><tr><td>1</td><td>Red</td><td>9</td><td>+5V</td></tr><tr><td>2</td><td>Green</td><td>10</td><td>GND</td></tr><tr><td>3</td><td>Blue</td><td>11</td><td>NC</td></tr><tr><td>4</td><td>NC</td><td>12</td><td>DDCDAT</td></tr><tr><td>5</td><td>GND</td><td>13</td><td>HSYNC</td></tr><tr><td>6</td><td>GND</td><td>14</td><td>VSYNC</td></tr><tr><td>7</td><td>GND</td><td>15</td><td>DDCLK</td></tr><tr><td>8</td><td>GND</td><td>—</td><td>—</td></tr></table>

# Video Signal Definitions:

RED Red signal

GRN Green signal

BLU Blue signal

HSYNC Horizontal synchronization

VSYNC Vertical synchronization

DDCCLK Display Data Channel clock signal for DDC2 support

DDCDAT Display Data Channel data signal for DDC2 support

# SATA 0 (CN1)

![This image is a vertical schematic diagram enclosed within a thin rectangular border. Inside the border, the top-left and bottom-right corners are filled with diagonal hatching lines. A white circle is located in the top-right corner, and another white circle is in the bottom-left corner. In the center of the rectangle, there is a vertical column of six small black dots, with vertical dashed lines running through the column. To the right of the rectangle, the numbers 1, 2, 3, 4, 5, 6, and 7 are listed vertically.](.atca-6890-manual-10/ceb9dc3486ddf001f3cd09e79942a7eb4999ce2bb7e4180c6ace55120c18e7af.jpg)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>Tx+</td></tr><tr><td>3</td><td>Tx-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>Rx-</td></tr><tr><td>6</td><td>Rx+</td></tr><tr><td>7</td><td>GND</td></tr></table>

IDE Connectors (CN2, CN3)

<table><tr><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td></tr><tr><td>RESET#</td><td>1</td><td>2</td><td>Ground</td></tr><tr><td>DD7</td><td>3</td><td>4</td><td>DD8</td></tr><tr><td>DD6</td><td>5</td><td>6</td><td>DD9</td></tr><tr><td>DD5</td><td>7</td><td>8</td><td>DD10</td></tr><tr><td>DD4</td><td>9</td><td>10</td><td>DD11</td></tr><tr><td>DD3</td><td>11</td><td>12</td><td>DD12</td></tr><tr><td>DD2</td><td>13</td><td>14</td><td>DD13</td></tr><tr><td>DD1</td><td>15</td><td>16</td><td>DD14</td></tr><tr><td>DD0</td><td>17</td><td>18</td><td>DD15</td></tr><tr><td>Ground</td><td>19</td><td>20</td><td>N.C (key pin)</td></tr><tr><td>DMARQ</td><td>21</td><td>22</td><td>Ground</td></tr><tr><td>DIOW#</td><td>23</td><td>24</td><td>Ground</td></tr><tr><td>DIOR#</td><td>25</td><td>26</td><td>Ground</td></tr><tr><td>IORDY</td><td>27</td><td>28</td><td>CSEL</td></tr><tr><td>DMACK#</td><td>29</td><td>30</td><td>Ground</td></tr><tr><td>INTRQ</td><td>31</td><td>32</td><td>N/C</td></tr><tr><td>DA1</td><td>33</td><td>34</td><td>PDIAG#</td></tr><tr><td>DA0</td><td>35</td><td>36</td><td>DA2</td></tr><tr><td>CS0#</td><td>37</td><td>38</td><td>CS1#</td></tr><tr><td>DASP#</td><td>39</td><td>40</td><td>Ground</td></tr><tr><td>5V</td><td>41</td><td>42</td><td>5V</td></tr><tr><td>Ground</td><td>43</td><td>44</td><td>TYPE-</td></tr></table>

# Zone 1 Connector

The ATCA-6890 uses the standard PICMG 3.0 Zone 1 connector for power and system management.

<table><tr><td>Pin</td><td>Designation</td><td>Description</td><td>Pin</td><td>Designation</td><td>Description</td></tr><tr><td>1</td><td>Reserved</td><td>Reserved</td><td>18</td><td>MT2_TIP</td><td>Metallic Test #2 Tip</td></tr><tr><td>2</td><td>Reserved</td><td>Reserved</td><td>19</td><td>-RING_A</td><td>Ring generator A Neg</td></tr><tr><td>3</td><td>Reserved</td><td>Reserved</td><td>20</td><td>-RING_B</td><td>Ring generator B Neg</td></tr><tr><td>4</td><td>Reserved</td><td>Reserved</td><td>21</td><td>MT1_RING</td><td>Metallic Test #1 Ring</td></tr><tr><td>5</td><td>HA0</td><td>Hardware Address Bit 0</td><td>22</td><td>MT2_RING</td><td>Metallic Test #2 Ring</td></tr><tr><td>6</td><td>HA1</td><td>Hardware Address Bit 1</td><td>23</td><td>RRTN_A</td><td>Ring generator A Rtn</td></tr><tr><td>7</td><td>HA2</td><td>Hardware Address Bit 2</td><td>24</td><td>RRTN_B</td><td>Ring generator B Rtn</td></tr><tr><td>8</td><td>HA3</td><td>Hardware Address Bit 3</td><td>25</td><td>SHELF_GND</td><td>Shelf Ground</td></tr><tr><td>9</td><td>HA4</td><td>Hardware Address Bit 4</td><td>26</td><td>LOGIC_GND</td><td>Logic Ground</td></tr><tr><td>10</td><td>HA5</td><td>Hardware Address Bit 5</td><td>27</td><td>ENABLE_B</td><td>Enable B</td></tr><tr><td>11</td><td>HA6</td><td>Hardware Address Bit 6</td><td>28</td><td>VRTN_A</td><td>Voltage Return A</td></tr><tr><td>12</td><td>HA7/P</td><td>Hardware Address Bit 7 (Odd Parity Bit)</td><td>29</td><td>VRTN_B</td><td>Voltage Return B</td></tr><tr><td>13</td><td>SCL_A</td><td>IPMB clock Port A</td><td>30</td><td>EARLY_A</td><td>-48 Volt Early A</td></tr><tr><td>14</td><td>SDA_A</td><td>IPMB Data Port A</td><td>31</td><td>EARLY_B</td><td>-48 Volt Early B</td></tr><tr><td>15</td><td>SCL_B</td><td>IPMB clock Port B</td><td>32</td><td>ENABLE_A</td><td>Enable A</td></tr><tr><td>16</td><td>SDA_B</td><td>IPMB Data Port B</td><td>33</td><td>-48V_A</td><td>-48 Volt A</td></tr><tr><td>17</td><td>MT1_TIP</td><td>Metallic Test #1 Tip</td><td>34</td><td>-48V_B</td><td>-48 Volt B</td></tr></table>

Note: Shaded pins are not connected on the ATCA-6890

Zone 2-J23 Pin Assignment (PICMG 3.1 Option1)

<table><tr><td>Signal</td><td>Row</td><td colspan="2">AB</td><td colspan="2">CD</td><td colspan="2">EF</td><td colspan="2">GH</td></tr><tr><td rowspan="2">FCH2</td><td>1</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>2</td><td>F2_T0+</td><td>F2_T0-</td><td>F2_R0+</td><td>F2_R0-</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">FCH1</td><td>3</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>4</td><td>F1_T0+</td><td>F1_T0-</td><td>F1_R0+</td><td>F1_R0-</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>BCH1</td><td>5</td><td>BI_A0+</td><td>BI_A0-</td><td>BI_A1+</td><td>BI_A1-</td><td>BI_A2+</td><td>BI_A2-</td><td>BI_A3+</td><td>BI_A3-</td></tr><tr><td>BCH 2</td><td>6</td><td>BI_B0+</td><td>BI_B0-</td><td>BI_B1+</td><td>BI_B1-</td><td>BI_B2+</td><td>BI_B2-</td><td>BI_B3+</td><td>BI_B3-</td></tr><tr><td rowspan="4">NC</td><td>7</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

TERM\* means connect to the termination circuit on board.

Zone 2-J22 Pin Assignment (PICMG 3.1 Option1)

<table><tr><td>Signal</td><td>Row</td><td colspan="2">AB</td><td colspan="2">CD</td><td colspan="2">EF</td><td colspan="2">GH</td></tr><tr><td rowspan="2">NC</td><td>1</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>2</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>3</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>4</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>5</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>6</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">FCH4</td><td>7</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>8</td><td>F4_T0+</td><td>F4_T0-</td><td>F4_R0+</td><td>F4_R0-</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">FCH3</td><td>9</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>10</td><td>F3_T0+</td><td>F3_T0-</td><td>F3_R0+</td><td>F3_R0-</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr></table>

TERM\* means connect to the termination circuit on board.

Zone 2-J23 Pin Assignment (PICMG 3.1 Option2)

<table><tr><td>Signal</td><td>Row</td><td colspan="2">AB</td><td colspan="2">CD</td><td colspan="2">EF</td><td colspan="2">GH</td></tr><tr><td rowspan="2">FCH2</td><td>1</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>2</td><td>F2_T0+</td><td>F2_T0-</td><td>F2_R0+</td><td>F2_R0-</td><td>F2_T1+</td><td>F2_T1-</td><td>F2_R1+</td><td>F2_R1-</td></tr><tr><td rowspan="2">FCH1</td><td>3</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>4</td><td>F1_T0+</td><td>F1_T0-</td><td>F1_R0+</td><td>F1_R0-</td><td>F1_T1+</td><td>F1_T1-</td><td>F2_R1+</td><td>F2_R1-</td></tr><tr><td>BCH1</td><td>5</td><td>BI_A0+</td><td>BI_A0-</td><td>BI_A1+</td><td>BI_A1-</td><td>BI_A2+</td><td>BI_A2-</td><td>BI_A3+</td><td>BI_A3-</td></tr><tr><td>BCH2</td><td>6</td><td>BI_B0+</td><td>BI_B0-</td><td>BI_B1+</td><td>BI_B1-</td><td>BI_B2+</td><td>BI_B2-</td><td>BI_B3+</td><td>BI_B3-</td></tr><tr><td rowspan="4">NC</td><td>7</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

TERM\* means connect to the termination circuit on board.

Zone 2-J22 Pin Assignment (PICMG 3.1 Option2)

<table><tr><td>Signal</td><td>Row</td><td colspan="2">AB</td><td colspan="2">CD</td><td colspan="2">EF</td><td colspan="2">GH</td></tr><tr><td rowspan="2">NC</td><td>1</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>2</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>3</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>4</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>5</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>6</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>7</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>8</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td rowspan="2">NC</td><td>9</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr><tr><td>10</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td><td>NC</td><td>TERM*</td></tr></table>

TERM\* means connect to the termination circuit on board.

Zone 3 Pin Assignment

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td></tr><tr><td>25</td><td>PMC1/IO5</td><td>PMC1/IO4</td><td>PMC1/IO3</td><td>PMC1/IO2</td><td>PMC1/IO1</td></tr><tr><td>24</td><td>PMC1/IO10</td><td>PMC1/IO9</td><td>PMC1/IO8</td><td>PMC1/IO7</td><td>PMC1/IO6</td></tr><tr><td>23</td><td>PMC1/IO15</td><td>PMC1/IO14</td><td>PMC1/IO13</td><td>PMC1/IO12</td><td>PMC1/IO11</td></tr><tr><td>22</td><td>PMC1/IO20</td><td>PMC1/IO19</td><td>PMC1/IO18</td><td>PMC1/IO17</td><td>PMC1/IO16</td></tr><tr><td>21</td><td>PMC1/IO25</td><td>PMC1/IO24</td><td>PMC1/IO23</td><td>PMC1/IO22</td><td>PMC1/IO21</td></tr><tr><td>20</td><td>PMC1/IO30</td><td>PMC1/IO29</td><td>PMC1/IO28</td><td>PMC1/IO27</td><td>PMC1/IO26</td></tr><tr><td>19</td><td>PMC1/IO35</td><td>PMC1/IO34</td><td>PMC1/IO33</td><td>PMC1/IO32</td><td>PMC1/IO31</td></tr><tr><td>18</td><td>PMC1/IO40</td><td>PMC1/IO39</td><td>PMC1/IO38</td><td>PMC1/IO37</td><td>PMC1/IO36</td></tr><tr><td>17</td><td>PMC1/IO45</td><td>PMC1/IO44</td><td>PMC1/IO43</td><td>PMC1/IO42</td><td>PMC1/IO41</td></tr><tr><td>16</td><td>PMC1/IO50</td><td>PMC1/IO49</td><td>PMC1/IO48</td><td>PMC1/IO47</td><td>PMC1/IO46</td></tr><tr><td>15</td><td>PMC1/IO55</td><td>PMC1/IO54</td><td>PMC1/IO53</td><td>PMC1/IO52</td><td>PMC1/IO51</td></tr><tr><td>12-14</td><td colspan="5">—</td></tr><tr><td>11</td><td>PMC1/IO60</td><td>PMC1/IO59</td><td>PMC1/IO58</td><td>PMC1/IO57</td><td>PMC1/IO56</td></tr><tr><td>10</td><td>SM_CLK</td><td>PMC1/IO64</td><td>PMC1/IO63</td><td>PMC1/IO62</td><td>PMC1/IO61</td></tr><tr><td>9</td><td>SM_DAT</td><td>KBDAT</td><td>KBCLK</td><td>MSDAT</td><td>MSCLK</td></tr><tr><td>8</td><td>SATA0TXP</td><td>SATA0TXN</td><td>RST#</td><td>SATA0RXP</td><td>SATA0RXN</td></tr><tr><td>7</td><td>SATA1TXP</td><td>SATA1TXN</td><td>+12V</td><td>SATA1RXP</td><td>SATA1RXN</td></tr><tr><td>6</td><td>USB_P2P</td><td>USB_P2N</td><td>USBOC#2</td><td>USB_P3P</td><td>USB_P3N</td></tr><tr><td>5</td><td>CLK100_RPE</td><td>CLK100#_RPE</td><td>RTM_IN#</td><td>UART2_TXD</td><td>UART2_RXD</td></tr><tr><td>4</td><td>PE_B_RP6</td><td>PE_B_RN6</td><td>+5V</td><td>PE_B_RP7</td><td>PE_B_RN7</td></tr><tr><td>3</td><td>PE_B_RP4</td><td>PE_B_RN4</td><td>+5V</td><td>PE_B_RP5</td><td>PE_B_RN5</td></tr><tr><td>2</td><td>PE_B_TP6</td><td>PE_B_TN6</td><td>+5V</td><td>PE_B_TP7</td><td>PE_B_TN7</td></tr><tr><td>1</td><td>PE_B_TP4</td><td>PE_B_TN4</td><td>+5V</td><td>PE_B_TP5</td><td>PE_B_TN5</td></tr></table>

# PMC Connectors

PMC1: P4 connector implemented

<table><tr><td colspan="4">JN1</td><td colspan="4">JN2</td></tr><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>TCK</td><td>-12V</td><td>2</td><td>1</td><td>+12V</td><td>TRST-</td><td>2</td></tr><tr><td>3</td><td>Ground</td><td>INTA-</td><td>4</td><td>3</td><td>TMS</td><td>TDO</td><td>4</td></tr><tr><td>5</td><td>INTB-</td><td>INTC-</td><td>6</td><td>5</td><td>TDI</td><td>Ground</td><td>6</td></tr><tr><td>7</td><td>BUSMODE1-</td><td>+5V</td><td>8</td><td>7</td><td>Ground</td><td>PCI-RSVD*</td><td>8</td></tr><tr><td>9</td><td>INTD-</td><td>PCI-RSVD*</td><td>10</td><td>9</td><td>PCI-RSVD*</td><td>PCI-RSVD*</td><td>10</td></tr><tr><td>11</td><td>Ground</td><td>PCI-RSVD*</td><td>12</td><td>11</td><td>BUSMODE2-</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>CLK</td><td>Ground</td><td>14</td><td>13</td><td>RST-</td><td>BUSMODE3-</td><td>14</td></tr><tr><td>15</td><td>Ground</td><td>GNT-</td><td>16</td><td>15</td><td>+3.3V</td><td>BUSMODE4-</td><td>16</td></tr><tr><td>17</td><td>REQ-</td><td>+5V</td><td>18</td><td>17</td><td>PCI-RSVD*</td><td>Ground</td><td>18</td></tr><tr><td>19</td><td>V (I/O)</td><td>AD[31]</td><td>20</td><td>19</td><td>AD[30]</td><td>AD[29]</td><td>20</td></tr><tr><td>21</td><td>AD[28]</td><td>AD[27]</td><td>22</td><td>21</td><td>Ground</td><td>AD[26]</td><td>22</td></tr><tr><td>23</td><td>AD[25]</td><td>Ground</td><td>24</td><td>23</td><td>AD[24]</td><td>+3.3V</td><td>24</td></tr><tr><td>25</td><td>Ground</td><td>C/BE[3]-</td><td>26</td><td>25</td><td>IDSEL</td><td>AD[23]</td><td>26</td></tr><tr><td>27</td><td>AD[22]</td><td>AD[21]</td><td>28</td><td>27</td><td>+3.3V</td><td>AD[20]</td><td>28</td></tr><tr><td>29</td><td>AD[19]</td><td>+5V</td><td>30</td><td>29</td><td>AD[18]</td><td>Ground</td><td>30</td></tr><tr><td>31</td><td>V (I/O)</td><td>AD[17]</td><td>32</td><td>31</td><td>AD[16]</td><td>C/BE[2]-</td><td>32</td></tr><tr><td>33</td><td>FRAME-</td><td>Ground</td><td>34</td><td>33</td><td>Ground</td><td>PMC-RSVD</td><td>34</td></tr><tr><td>35</td><td>Ground</td><td>IRDY-</td><td>36</td><td>35</td><td>TRDY-</td><td>+3.3V</td><td>36</td></tr><tr><td>37</td><td>DEVSEL-</td><td>+5V</td><td>38</td><td>37</td><td>Ground</td><td>STOP-</td><td>38</td></tr><tr><td>39</td><td>PCIXCAP</td><td>LOCK-</td><td>40</td><td>39</td><td>PERR-</td><td>Ground</td><td>40</td></tr><tr><td>41</td><td>SDONE-</td><td>SBO-</td><td>42</td><td>41</td><td>+3.3V</td><td>SERR-</td><td>42</td></tr><tr><td>43</td><td>PAR</td><td>Ground</td><td>44</td><td>43</td><td>C/BE[1]-</td><td>Ground</td><td>44</td></tr><tr><td>45</td><td>V (I/O)</td><td>AD[15]</td><td>46</td><td>45</td><td>AD[14]</td><td>AD[13]</td><td>46</td></tr><tr><td>47</td><td>AD[12]</td><td>AD[11]</td><td>48</td><td>47</td><td>M66EN</td><td>AD[10]</td><td>48</td></tr><tr><td>49</td><td>AD[09]</td><td>+5V</td><td>50</td><td>49</td><td>AD[08]</td><td>+3.3V</td><td>50</td></tr><tr><td>51</td><td>Ground</td><td>C/BE[0]-</td><td>52</td><td>51</td><td>AD[07]</td><td>PMC-RSVD</td><td>52</td></tr><tr><td>53</td><td>AD[06]</td><td>AD[05]</td><td>54</td><td>53</td><td>+3.3V</td><td>PMC-RSVD</td><td>54</td></tr><tr><td>55</td><td>AD[04]</td><td>Ground</td><td>56</td><td>55</td><td>PMC-RSVD</td><td>Ground</td><td>56</td></tr><tr><td>57</td><td>V (I/O)</td><td>AD[03]</td><td>58</td><td>57</td><td>PMC-RSVD</td><td>PMC-RSVD</td><td>58</td></tr><tr><td>59</td><td>AD[02]</td><td>AD[01]</td><td>60</td><td>59</td><td>Ground</td><td>PMC-RSVD</td><td>60</td></tr><tr><td>61</td><td>AD[00]</td><td>+5V</td><td>62</td><td>61</td><td>ACK64-</td><td>+3.3V</td><td>62</td></tr><tr><td>63</td><td>Ground</td><td>REQ64-</td><td>64</td><td>63</td><td>Ground</td><td>PMC-RSVD</td><td>64</td></tr><tr><td colspan="4">JN3</td><td colspan="4">JN4</td></tr><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>RESERVED</td><td>GND</td><td>2</td><td>1</td><td>+12V</td><td>TRST-</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>CBE7#</td><td>4</td><td>3</td><td>TMS</td><td>TDO</td><td>4</td></tr><tr><td>5</td><td>CEB6#</td><td>CBE5#</td><td>6</td><td>5</td><td>TDI</td><td>Ground</td><td>6</td></tr><tr><td>7</td><td>CEB4#</td><td>GND</td><td>8</td><td>7</td><td>Ground</td><td>PCI-RSVD*</td><td>8</td></tr><tr><td>9</td><td>VIO</td><td>PAR64</td><td>10</td><td>9</td><td>PCI-RSVD*</td><td>PCI-RSVD*</td><td>10</td></tr><tr><td>11</td><td>AD63</td><td>AD62</td><td>12</td><td>11</td><td>BUSMODE2-</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>AD61</td><td>GND</td><td>14</td><td>13</td><td>RST-</td><td>BUSMODE3-</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>AD60</td><td>16</td><td>15</td><td>+3.3V</td><td>BUSMODE4-</td><td>16</td></tr><tr><td>17</td><td>AD59</td><td>AD58</td><td>18</td><td>17</td><td>PCI-RSVD*</td><td>Ground</td><td>18</td></tr><tr><td>19</td><td>AD57</td><td>GND</td><td>20</td><td>19</td><td>AD[30]</td><td>AD[29]</td><td>20</td></tr><tr><td>21</td><td>VIO</td><td>AD56</td><td>22</td><td>21</td><td>Ground</td><td>AD[26]</td><td>22</td></tr><tr><td>23</td><td>AD55</td><td>AD54</td><td>24</td><td>23</td><td>AD[24]</td><td>+3.3V</td><td>24</td></tr><tr><td>25</td><td>AD53</td><td>GND</td><td>26</td><td>25</td><td>IDSEL</td><td>AD[23]</td><td>26</td></tr><tr><td>27</td><td>GND</td><td>AD52</td><td>28</td><td>27</td><td>+3.3V</td><td>AD[20]</td><td>28</td></tr><tr><td>29</td><td>AD51</td><td>AD50</td><td>30</td><td>29</td><td>AD[18]</td><td>Ground</td><td>30</td></tr><tr><td>31</td><td>AD49</td><td>GND</td><td>32</td><td>31</td><td>AD[16]</td><td>C/BE[2]-</td><td>32</td></tr><tr><td>33</td><td>GND</td><td>AD48</td><td>34</td><td>33</td><td>Ground</td><td>PMC-RSVD</td><td>34</td></tr><tr><td>35</td><td>AD47</td><td>AD46</td><td>36</td><td>35</td><td>TRDY-</td><td>+3.3V</td><td>36</td></tr><tr><td>37</td><td>AD45</td><td>GND</td><td>38</td><td>37</td><td>Ground</td><td>STOP-</td><td>38</td></tr><tr><td>39</td><td>VIO</td><td>AD44</td><td>40</td><td>39</td><td>PERR-</td><td>Ground</td><td>40</td></tr><tr><td>41</td><td>AD43</td><td>AD42</td><td>42</td><td>41</td><td>+3.3V</td><td>SERR-</td><td>42</td></tr><tr><td>43</td><td>AD41</td><td>GND</td><td>44</td><td>43</td><td>C/BE[1]-</td><td>Ground</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>AD40</td><td>46</td><td>45</td><td>AD[14]</td><td>AD[13]</td><td>46</td></tr><tr><td>47</td><td>AD39</td><td>AD38</td><td>48</td><td>47</td><td>Ground</td><td>AD[10]</td><td>48</td></tr><tr><td>49</td><td>AD37</td><td>GND</td><td>50</td><td>49</td><td>AD[08]</td><td>+3.3V</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>AD36</td><td>52</td><td>51</td><td>AD[07]</td><td>PMC-RSVD</td><td>52</td></tr><tr><td>53</td><td>AD35</td><td>AD34</td><td>54</td><td>53</td><td>+3.3V</td><td>PMC-RSVD</td><td>54</td></tr><tr><td>55</td><td>AD33</td><td>GND</td><td>56</td><td>55</td><td>PMC-RSVD</td><td>Ground</td><td>56</td></tr><tr><td>57</td><td>VIO</td><td>AD32</td><td>58</td><td>57</td><td>PMC-RSVD</td><td>PMC-RSVD</td><td>58</td></tr><tr><td>59</td><td>RESERVED</td><td>RESERVED</td><td>60</td><td>59</td><td>Ground</td><td>PMC-RSVD</td><td>60</td></tr><tr><td>61</td><td>RESERVED</td><td>GND</td><td>62</td><td>61</td><td>ACK64-</td><td>+3.3V</td><td>62</td></tr><tr><td>63</td><td>GND</td><td>RESERVED</td><td>64</td><td>63</td><td>Ground</td><td>PMC-RSVD</td><td>64</td></tr></table>

PMC2: P4 connector NOT implemented

<table><tr><td colspan="4">JN5</td><td colspan="4">JN6</td></tr><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>TCK</td><td>-12V</td><td>2</td><td>1</td><td>+12V</td><td>TRST-</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>PCIIRQ4#</td><td>4</td><td>3</td><td>TMS</td><td>TDO</td><td>4</td></tr><tr><td>5</td><td>PCIIRQ5#</td><td>PCIIRQ4#</td><td>6</td><td>5</td><td>TDI</td><td>Ground</td><td>6</td></tr><tr><td>7</td><td>BUSMODE1#</td><td>+5V</td><td>8</td><td>7</td><td>Ground</td><td>PCI-RSVD*</td><td>8</td></tr><tr><td>9</td><td>PCIIRQ5#</td><td>RESERVED</td><td>10</td><td>9</td><td>PCI-RSVD*</td><td>PCI-RSVD*</td><td>10</td></tr><tr><td>11</td><td>GND</td><td>+3.3V</td><td>12</td><td>11</td><td>BUSMODE2-</td><td>+3.3V</td><td>12</td></tr><tr><td>13</td><td>CLOCK</td><td>GND</td><td>14</td><td>13</td><td>RST-</td><td>BUSMODE3-</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>GNT2#</td><td>16</td><td>15</td><td>+3.3V</td><td>BUSMODE4-</td><td>16</td></tr><tr><td>17</td><td>REQ2#</td><td>+5V</td><td>18</td><td>17</td><td>PCI-RSVD*</td><td>Ground</td><td>18</td></tr><tr><td>19</td><td>PMCVIO</td><td>AD[31]</td><td>20</td><td>19</td><td>AD[30]</td><td>AD[29]</td><td>20</td></tr><tr><td>21</td><td>AD[28]</td><td>AD[27]</td><td>22</td><td>21</td><td>Ground</td><td>AD[26]</td><td>22</td></tr><tr><td>23</td><td>AD[25]</td><td>GND</td><td>24</td><td>23</td><td>AD[24]</td><td>+3.3V</td><td>24</td></tr><tr><td>25</td><td>GND</td><td>C/BEJ[3]#</td><td>26</td><td>25</td><td>IDSEL</td><td>AD[23]</td><td>26</td></tr><tr><td>27</td><td>AD[22]</td><td>AD[21]</td><td>28</td><td>27</td><td>+3.3V</td><td>AD[20]</td><td>28</td></tr><tr><td>29</td><td>AD[19]</td><td>+5V</td><td>30</td><td>29</td><td>AD[18]</td><td>Ground</td><td>30</td></tr><tr><td>31</td><td>PMCVIO</td><td>AD[17]</td><td>32</td><td>31</td><td>AD[16]</td><td>C/BE[2]-</td><td>32</td></tr><tr><td>33</td><td>FRAME#</td><td>GND</td><td>34</td><td>33</td><td>Ground</td><td>PMC-RSVD</td><td>34</td></tr><tr><td>35</td><td>GND</td><td>IRDY#</td><td>36</td><td>35</td><td>TRDY-</td><td>+3.3V</td><td>36</td></tr><tr><td>37</td><td>DEVSEL#</td><td>+5V</td><td>38</td><td>37</td><td>Ground</td><td>STOP-</td><td>38</td></tr><tr><td>39</td><td>PCIXCAP</td><td>LCOK#</td><td>40</td><td>39</td><td>PERR-</td><td>Ground</td><td>40</td></tr><tr><td>41</td><td>RESERVED</td><td>RESERVED</td><td>42</td><td>41</td><td>+3.3V</td><td>SERR-</td><td>42</td></tr><tr><td>43</td><td>PAR</td><td>GND</td><td>44</td><td>43</td><td>C/BE[1]-</td><td>Ground</td><td>44</td></tr><tr><td>45</td><td>PMCVIO</td><td>AD[15]</td><td>46</td><td>45</td><td>AD[14]</td><td>AD[13]</td><td>46</td></tr><tr><td>47</td><td>AD[12]</td><td>AD[11]</td><td>48</td><td>47</td><td>M66EN</td><td>AD[10]</td><td>48</td></tr><tr><td>49</td><td>AD[9]</td><td>+5V</td><td>50</td><td>49</td><td>AD[08]</td><td>+3.3V</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>C/BEJ[0]#</td><td>52</td><td>51</td><td>AD[07]</td><td>PMC-RSVD</td><td>52</td></tr><tr><td>53</td><td>AD[6]</td><td>AD[5]</td><td>54</td><td>53</td><td>+3.3V</td><td>PMC-RSVD</td><td>54</td></tr><tr><td>55</td><td>AD[4]</td><td>GND</td><td>56</td><td>55</td><td>PMC-RSVD</td><td>Ground</td><td>56</td></tr><tr><td>57</td><td>PMCVIO</td><td>AD[3]</td><td>58</td><td>57</td><td>PMC-RSVD</td><td>PMC-RSVD</td><td>58</td></tr><tr><td>59</td><td>AD[2]</td><td>AD[1]</td><td>60</td><td>59</td><td>Ground</td><td>PMC-RSVD</td><td>60</td></tr><tr><td>61</td><td>AD[0]</td><td>+5V</td><td>62</td><td>61</td><td>ACK64-</td><td>+3.3V</td><td>62</td></tr><tr><td>63</td><td>GND</td><td>REQ64 #</td><td>64</td><td>63</td><td>Ground</td><td>PMC-RSVD</td><td>64</td></tr><tr><td colspan="4">JN7</td><td colspan="4">JN8</td></tr><tr><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td><td>Signal</td><td>Pin</td></tr><tr><td>1</td><td>RESERVED</td><td>GND</td><td>2</td><td>1</td><td>—</td><td>—</td><td>2</td></tr><tr><td>3</td><td>GND</td><td>CBE7#</td><td>4</td><td>3</td><td>—</td><td>—</td><td>4</td></tr><tr><td>5</td><td>CEB6#</td><td>CBE5#</td><td>6</td><td>5</td><td>—</td><td>—</td><td>6</td></tr><tr><td>7</td><td>CEB4#</td><td>GND</td><td>8</td><td>7</td><td>—</td><td>—</td><td>8</td></tr><tr><td>9</td><td>VIO</td><td>PAR64</td><td>10</td><td>9</td><td>—</td><td>—</td><td>10</td></tr><tr><td>11</td><td>AD63</td><td>AD62</td><td>12</td><td>11</td><td>—</td><td>—</td><td>12</td></tr><tr><td>13</td><td>AD61</td><td>GND</td><td>14</td><td>13</td><td>—</td><td>—</td><td>14</td></tr><tr><td>15</td><td>GND</td><td>AD60</td><td>16</td><td>15</td><td>—</td><td>—</td><td>16</td></tr><tr><td>17</td><td>AD59</td><td>AD58</td><td>18</td><td>17</td><td>—</td><td>—</td><td>18</td></tr><tr><td>19</td><td>AD57</td><td>GND</td><td>20</td><td>19</td><td>—</td><td>—</td><td>20</td></tr><tr><td>21</td><td>VIO</td><td>AD56</td><td>22</td><td>21</td><td>—</td><td>—</td><td>22</td></tr><tr><td>23</td><td>AD55</td><td>AD54</td><td>24</td><td>23</td><td>—</td><td>—</td><td>24</td></tr><tr><td>25</td><td>AD53</td><td>GND</td><td>26</td><td>25</td><td>—</td><td>—</td><td>26</td></tr><tr><td>27</td><td>GND</td><td>AD52</td><td>28</td><td>27</td><td>—</td><td>—</td><td>28</td></tr><tr><td>29</td><td>AD51</td><td>AD50</td><td>30</td><td>29</td><td>—</td><td>—</td><td>30</td></tr><tr><td>31</td><td>AD49</td><td>GND</td><td>32</td><td>31</td><td>—</td><td>—</td><td>32</td></tr><tr><td>33</td><td>GND</td><td>AD48</td><td>34</td><td>33</td><td>—</td><td>—</td><td>34</td></tr><tr><td>35</td><td>AD47</td><td>AD46</td><td>36</td><td>35</td><td>—</td><td>—</td><td>36</td></tr><tr><td>37</td><td>AD45</td><td>GND</td><td>38</td><td>37</td><td>—</td><td>—</td><td>38</td></tr><tr><td>39</td><td>VIO</td><td>AD44</td><td>40</td><td>39</td><td>—</td><td>—</td><td>40</td></tr><tr><td>41</td><td>AD43</td><td>AD42</td><td>42</td><td>41</td><td>—</td><td>—</td><td>42</td></tr><tr><td>43</td><td>AD41</td><td>GND</td><td>44</td><td>43</td><td>—</td><td>—</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>AD40</td><td>46</td><td>45</td><td>—</td><td>—</td><td>46</td></tr><tr><td>47</td><td>AD39</td><td>AD38</td><td>48</td><td>47</td><td>—</td><td>—</td><td>48</td></tr><tr><td>49</td><td>AD37</td><td>GND</td><td>50</td><td>49</td><td>—</td><td>—</td><td>50</td></tr><tr><td>51</td><td>GND</td><td>AD36</td><td>52</td><td>51</td><td>—</td><td>—</td><td>52</td></tr><tr><td>53</td><td>AD35</td><td>AD34</td><td>54</td><td>53</td><td>—</td><td>—</td><td>54</td></tr><tr><td>55</td><td>AD33</td><td>GND</td><td>56</td><td>55</td><td>—</td><td>—</td><td>56</td></tr><tr><td>57</td><td>VIO</td><td>AD32</td><td>58</td><td>57</td><td>—</td><td>—</td><td>58</td></tr><tr><td>59</td><td>RESERVED</td><td>RESERVED</td><td>60</td><td>59</td><td>—</td><td>—</td><td>60</td></tr><tr><td>61</td><td>RESERVED</td><td>GND</td><td>62</td><td>61</td><td>—</td><td>—</td><td>62</td></tr><tr><td>63</td><td>GND</td><td>RESERVED</td><td>64</td><td>63</td><td>—</td><td>—</td><td>64</td></tr></table>

# 2.2 Jumper Settings

# Clear CMOS Jumper (SWZ1)

The ATCA-6890 has a clear CMOS jumper located near the CMOS battery to allow the user to clear CMOS values to default values if necessary (please refer to the following figure to clear CMOS values by pressing SWZ1.)

![SWZ1\nBC68\nBC81\nSWZ1\nBC61\nR124\n1065\n137\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n1065\n106](.atca-6890-manual-10/1ff86c6bb6b37913d3b10921d5a94638920b9331185ce386928bb81b1740d879.jpg)

# 3 Getting Started

This chapter described the procedures for installing the CPUs, memory modules and additional hardware installation on the aTCA-6890. Note that the aTCA-6890 may be shipped with CPU, and RAM preinstalled, depending on the options your processor blade is ordered with.

# 3.1 CPU Installation

The aTCA-6890 supports up to two Intel® Xeon™ processors. Remove the CPU(s) from its packaging. Before installing, apply a small quantity of thermal grease to the top side of the CPU by carefully squeezing it out of the syringe. Smooth out the grease with the plastic film as shown below. This will allow the CPU to make efficient thermal contact with the heat sink.

![thermal grease\nCPU\nplastic film](.atca-6890-manual-10/3d2d179305665fc48317274f10847c2cc692921fd13c39b75b43fa646844687e.jpg)

![thermal grease\napplied to CPU](.atca-6890-manual-10/11c37951a43346154037cd30ee7d9a4afeedb79b3a4b31ebe0cccf665f383cf1.jpg)

![spread grease evenly](.atca-6890-manual-10/e2b973b48f84d8e7c43e6885c9de78efb7072d49ac63dfac9ff3dbc3a1b0263c.jpg)

Figure 3-1: Apply thermal grease to CPU(s)

The CPU sockets are located on the aTCA-6890 as shown in Figure 1-2: aTCA-6890 Board Layout. Fully raise the CPU locking lever as far as it will go as shown in the R-hand socket in Figure 3-2: CPU Installation below. Carefully place the CPU (with thermal grease applied as described above) into the CPU socket. Be sure to align the gold triangle on the corner of the chip with the triangular cut-out in the corner of the socket. Press down gently on the chip to ensure that it is securely in place, and then press the lever down to lock the CPU into position. Repeat if required for the second CPU

Note: If you are only installing one CPU, it must be installed in the CPU0 socket.

![CPU0\nCPU1\ntriangle\nlocked\nopen](.atca-6890-manual-10/3f5b9c231a025e98e708892ec15786f30e62289df4649670adfb4f39409010a7.jpg)

Figure 3-2: CPU Installation

Next, apply a pre-cut piece of thermal pad to the outside edge of the CPU as shown below.

![Two views of a green circuit board with square components, one showing internal structure and the other showing a close-up view (no text or symbols visible)](.atca-6890-manual-10/3042d66600acfd3c9e5e134e77c3b27bbf4a18ab326a759a33b8ea47ef3645f3.jpg)

Figure 3-3: Apply thermal pad to outside edge of the CPU

# 3.2 Memory Installation

The aTCA-6890 CPU Module supports four DDR-II 400 240-pin DIMMs up to a maximum of 16GB. The aTCA-6890 can be populated with one, two, or four DIMM modules. The first module must be installed in slot 2 of either Channel A or B. The second module can be installed in the remaining DIMM 2 slot, or in slot 1 corresponding to the channel of the first memory module (see Figure 3-4 below for slot locations). Refer to Section 1.3 Main Functions, Memory Interface for more detailed information on memory functionality.

![The image displays a block diagram overlaid on a circuit board, illustrating connections between channels and memory slots.\n\n**Labeled Blocks:**\n*   **Channel A2**\n*   **Channel A1**\n*   **Channel B2**\n*   **Channel B1**\n*   **Back of Module**\n\n**Connections:**\nThere are four horizontal rows of slots on the board. The connections are as follows:\n*   **Channel A2**: An arrow points downward from this block to the second row of slots.\n*   **Channel A1**: An arrow points downward from this block to the first (topmost) row of slots.\n*   **Channel B2**: An arrow points upward from this block to the fourth (bottommost) row of slots.\n*   **Channel B1**: An arrow points upward from this block to the third row of slots.\n*   **Back of Module**: An arrow points downward from this block, indicating a connection or reference to the back of the module.](.atca-6890-manual-10/f01760f762e48f6122c6705d05ea4789901f84e6bfeb2d9adbe32ce95f183fee.jpg)

Figure 3-4: Memory slot locations

# Installing the Memory Modules

Pull the ejector clips of the DIMM slot outwards. Align the notch in the memory module with the key in the DIMM slot and insert. Firmly push the memory module into the slot as shown in Figure 3-5: Installing the Memory Modules below, until the ejector clips pop in and lock the module in place. Repeat for the remaining memory modules.

![notch\nejector\nclip\nkey\nejector\nclip](.atca-6890-manual-10/84f3ef7aef46a4b54ef71afb23c4f4b9db2632fdb6cba839828f1efd6314f973.jpg)

Figure 3-5: Installing the Memory Modules

# 3.3 Hard Drive Installation

The aTCA-6890 has two 2.5" on-card hard drive sites, each of which takes the space of one PMC site (we recommend using the upper PMC site). To install a hard drive, attach the hard drive brackets to each side of the hard drive as shown below in Figure 3-6: Hard Drive Installation using the screws provided. Then secure the hard drive/bracket assembly to the aTCA-6890 board with four screws from the back side of the board as shown.

![HD bracket\nIDE cable\n2.5' HD](.atca-6890-manual-10/0cbea4859f12c93dae8d44afac686efa183a63e8784257632715ebafd5fda7da.jpg)

Figure 3-6: Hard Drive Installation

Connect the drive to either an IDE or SATA ribbon cable as appropriate. Plug the board end of the cable into the respective IDE (or SATA) connector on the aTCA-6890. Make sure pin 1 of the ribbon cable connector is aligned with pin 1 of the device connector.

# 3.4 Heat Sink Installation

Make sure you have all the required materials needed for this installation before you begin:

Heatsink x1
▶ Spring-loaded Screw x8
▶ Insulator x2

![Electronic component with multiple square and circular components, including a transparent plastic case and screws, displayed on a plain surface (no text or symbols visible)](.atca-6890-manual-10/c38729a944c183e8043c76596dd60959b0289322e89bdeda305c37a1d3d98ee4.jpg)

Figure 3-7: Pre-installation

Next, apply a pre-cut piece of insulator to the outside edge of the CPU or, for the uni-processors, the CPU0 as well. Please refer to the figure below for details.

![Close-up of a finger pressing a component on a green circuit board (no visible text or symbols)](.atca-6890-manual-10/c8b7798b4d299c61afdf6372a9f14bac1f117cde266b02ecfbf84466487e736c.jpg)

Figure 3-8: Insulator

For dual processors, repeat the prior procedure on the second CPU.

![Close-up of a green printed circuit board with multiple electronic components and traces (no visible text or symbols)](.atca-6890-manual-10/37e099ea7fab26bf0697806ac563846b20eb55aa915f81d2d19b21153fb00d29.jpg)

Figure 3-9: Dual processors

Remove the transparent plastic protectors from the three thermal pads circled in red on the underside of the heat sink.

![Close-up of a hand holding a white rectangular object on a metallic surface, with no visible text or symbols.](.atca-6890-manual-10/4a1b152092d3d381f7e84edc3b010ec468145bb6ca2b915337e64feccb8fa3df.jpg)

![Metallic electronic component with three square cutouts and red-circled highlights (no text or symbols)](.atca-6890-manual-10/67b6f1d502f218467ad301df0087dfbe88dcd958507b71ab0f3b24d518b8f865.jpg)

Figure 3-10: Heat Sink Installation

Gently place the heatsink on the board as shown in the figure below.

![Close-up of a copper-colored electronic circuit board with visible components and wiring (no text or symbols)](.atca-6890-manual-10/da2f2552b162e61871a704f02914f4b3e8a60d5d2a082358e80af3c2f2b8905b.jpg)

Figure 3-11: Heatsink Alignment

Make sure all the screws holes are well aligned to the stand-offs.

![Close-up of a green circuit board with visible components and a metallic heat sink (no readable text or symbols)](.atca-6890-manual-10/445baf48fc863289c4132d834d998c11246301bf01414a707460e5a5a14e05bb.jpg)

Figure 3-12: Screw Alignment

Install the heat sink on the aTCA-6890 board with eight screws from the top of the board. Be careful to screw them on straight and tighten the crews to only approximately 30% in depth in the initial installation. Wait until all the screws are securely seated before tightening screws 100% in depth.

![Close-up of a green circuit board with a precision tool inserted into a soldering iron, no visible text or symbols.](.atca-6890-manual-10/8ceafe067dbe718029d5a31dd15ee5088e3ba601066b84d021f34971ed009ab3.jpg)

Figure 3-13: Tightening screws

For balance reasons, tighten the screws in the following order: 1-8, as shown in the figure below.

![Labeled diagram of a computer motherboard showing numbered components including heatsink, cooling elements, and power supply unit.](.atca-6890-manual-10/4e867d834a65b218823fb5049d456964afe4d75c484270c8f8a419415d0459c1.jpg)

Figure 3-14: Order of screws

When disassembling the CPU heatsink, sometimes the PCM may be torn. In the base of a torn PCM, follow these procedures in order to fix this problem.

![Close-up of a translucent octagonal object with a square base, placed on a metallic surface (no visible text or symbols)](.atca-6890-manual-10/9914279dcc3696bc58c8ea0c9cc2448030512972289066b145894b8d8260b1f2.jpg)

Figure 3-15: Phase-Change Material

Please contact ADLINK to apply for thermal grease. DO NOT USE OFF-THE-SELF SUBSTITUES. Proceed only when you have these items:

▶ Thermal grease from ADLINK
▶ Plastic peice

![Close-up of a syringe with red cap and black handle, placed on a plain surface (no text or symbols visible)](.atca-6890-manual-10/da45950e9e4541607de824b6a8b4211555886ec2670f02e59f56179e20af8af8.jpg)

Figure 3-16: Thermal Grease

Be careful to thoroughly clean each CPU surface, as shown in the figure below.

![Close-up of a microprocessor on a circuit board (no visible text or symbols)](.atca-6890-manual-10/522414daabcfc11ba66de87eac93fc8f6c96ae111e746985c541a7986cf89df9.jpg)

Figure 3-17: Clean CPU

Once you have cleaned each CPU surface, squeeze 1/5th - 1/4th of the tube of grease on each surface.

![Close-up of a microchip mounted on a circuit board with visible traces and components (no text or symbols)](.atca-6890-manual-10/933395ad8442664b1f81d4d550198cf8d6eb74833e6eb15654c2a1136127d6b0.jpg)

Figure 3-18: Volume of Grease

Use a plastic peice to spread the grease evenly on each CPU surface as shown in the figure below.

![Close-up of a green electronic component with a metallic top, placed on a circuit board (no visible text or symbols)](.atca-6890-manual-10/7e2b8095e1d00de1f154efa8cdba408ea3637728c2c914fe84586ba5df6c6452.jpg)

Figure 3-19: Spread the Grease

Now that this procedure is complete, the heatsink must be installed again. For instruction for installation the heatsink, refer to the step with Figure 3-11: Heatsink Alignment in the above procedures, to start where you must gently place the heatsink on the board.

# 3.5 CF Card Installation

To insert a CF card into the aTCA-6890, locate the cut-out for the CF card slot on the back side of the aTCA-6890 board behind the upper PMC site. Insert the CF card by placing it into the slot and pushing it firmly into place. To remove the CF card, grab it by the top edge and pull it out of the slot.

# 3.6 aTCA Module Installation & Removal

To install the aTCA-6890 module, follow these steps:

1. Carefully align the board edges with the chassis guide rails and insert the module into the chassis.

![chassis guide rail\ninsert module](.atca-6890-manual-10/79c0a796ef6ba1959183dac588f9d7b36d6f15d4ddfadf12a6fba96c45e43f44.jpg)

Figure 3-20: Insert the aTCA module into chassis guide rails

2. Check that the catch hooks and alignment pins at either end of the module are correctly inserted into the proper openings. Push inwards on the handles until the module is firmly seated in the chassis. (Do not force the handles if there is resistance as this may damage the connectors and/or backplane.)

![alignment pin\nProper Alignment\ncatch hook](.atca-6890-manual-10/86782c1eb162bf96be017d8ec8277f33caf10e4a4f0a110c4702d87906028a58.jpg)

Figure 3-21: Ensure that catch hooks and alignment pins are correctly inserted

![alignment pin\ncatch hook\nImproper Alignment](.atca-6890-manual-10/692d3c3fbb10564a7b766c944da1ed8f1b6dfd0f4c8d0b3f086ca85cb4aea2bd.jpg)

Figure 3-22: Incorrect alignment of the catch hook

3. Push the ejector handles into the faceplate.

![Close-up of a hand using tweezers to adjust a microcontroller board with visible traces and components (no readable text or symbols)](.atca-6890-manual-10/4c96e28d510cf5daf54f7c85d2fad4847bb55f70f91988208c2bcf6949d9176c.jpg)

Figure 3-23: Push the ejector handles into faceplate

4. Close the ejectors handle

![Close-up of a mechanical device with visible labels including 'PMC1' and 'ACLINK', showing internal components and part numbers.](.atca-6890-manual-10/308f5548472c502d3be5c1c798e1b6d5c83f1d1fe184f46ad52110ae17d52ea5.jpg)

Figure 3-24: Close the ejector handles

# 5. Lock the module by turning the captive screws

![ADLINK\nPMC1](.atca-6890-manual-10/5f7ecd752f1b01ad80bf58bdbc2d37a27dcc111652329c1bbc77835cc500bf38.jpg)

Figure 3-25: Lock the module

To remove the aTCA-6890 module, undo the captive screws, pinch the ejector handle release mechanisms and pull outwards on the ejector handles to eject the module from the backplane. Pull the module towards you until it is free of the chassis.

# 3.7 Operating System Installation

For more detailed information about your operating system, refer to the documentation provided by the operating system vendor.

Installing peripheral devices: Peripheral devices are automatically configured by the BIOS during the boot sequence.

Most operating systems require initial installation on a hard drive from a floppy or CDROM drive. These devices should be configured, installed, and tested with the supplied drivers before attempting to load the new operating system.

Read the release notes and installation documentation provided by the operating system vendor. Be sure to read any README files or documents provided on the distribution disks, as these typically note documentation discrepancies or compatibility problems.

Select the appropriate boot device order in the BIOS Setup Utility boot menu depending on the OS installation media used. For example, if the OS includes a bootable installation floppy, select Floppy as the first boot device and reboot the system with the installation floppy installed in the floppy drive. (Note that if the installation requires a non-bootable CD-ROM, it is necessary to boot an OS with the proper CD-ROM drivers in order to access the CD-ROM drive).

Proceed with the OS installation as directed. Be sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of ADLINK products.

When installation is complete, reboot the system and set the boot device order in the Setup Utility boot menu appropriately.

# 4 Device Driver Installation

To install drivers for the aTCA-6890, refer to the installation information in this chapter. Basic driver installation information for Windows XP/2000 Professional is outlined in this section. The drivers are located in the following directories of the CD-Rom:

<table><tr><td>Chipset driver</td><td>X:\ATCA\ATCA-6890\chipset\</td></tr><tr><td>VGA driver</td><td>X:\ATCA\ATCA-6890\VGA\</td></tr><tr><td>LAN</td><td>X:\ATCA\ATCA-6890\LAN\</td></tr></table>

For information regarding BSP support for VXWorks and Montivista operating systems, please contact ADLINK.

# 4.1 Intel® E7520 MCH/6300ESB ICH Chipset

This section describes the installation procedure for the Intel® E7520 MCH/6300ESB ICH chipset device driver under Windows XP/2000 Professional.

# System Requirements

One of the following operating systems must be fully installed on the system before installing any other driver, utilities, or software:

▶ Windows 2000 Professional
▶ Windows XP Professional

# Intel® Chipset Software Installation Utility

This section describes how to install the Intel® Chipset Software Installation Utility on a system running Windows XP/2000 Professional.

1. Check the System Requirements. Windows 2000/XP must be fully installed and running on the system prior to running this software.
2. Close any running applications.
3. Place the ADLINK CD into the CD-ROM drive. Run infinst\_autol\_6.2.1.1001.exe under X:\ATCA\ATCA-6890\chipset, where X is the CD drive letter.

4. Click Next on the Welcome screen to read and agree to the license agreement. Click Yes if you agree to continue. NOTE: If you click No, the program will terminate.
5. Click Next on the Readme Information screen to install the INF files.
6. Click Finish to restart the system when prompted to do so.
7. Follow the screen instructions and use the default settings to complete setup when Windows XP/2000 Professional restarts. Upon restart, Windows may display that it has found new hardware and is installing drivers for them. Select Yes, if prompted to restart Windows XP/2000 Professional. This completes the installation of the Intel® Chipset Software Installation Utility.

# 4.2 VGA Driver Installation

Windows XP/2000 Professional will attempt to install a standard VGA driver automatically. To guarantee compatibility, manually install the most up-to-date VGA driver, which is provided on the ADLINK CD. After installing Windows XP/2000 Professional, install the most up-to-date driver by following these steps (note: different drivers for Windows XP and 2000 Professional):

1. Boot Windows XP/2000 Professional, then run the program w2k-ragexl-5-0-2195-5012.exe if running Windows 2000, or wxp-ragexl-5-10-2600-6009.exe if running Windows XP, under the directory X:\ATCA\ATCA-6890\VGA\, where X is the CD drive letter.
2. The VGA driver will automatically be installed onto the system.
3. Restart the system.

# 4.3 LAN Driver Installation

# Note:

Before installing the LAN driver, the Intel® E7520 MCH/6300ESB ICH chipset device driver must first be installed as described in Section 4.1 above.

This section describes the LAN driver installation process for the Intel® 82546GB Gigabit Ethernet Controllers under Windows XP/2000 Professional. The Intel® software utilities package include a Diagnostics Utility, Makedisk Utility, and the 10/100/1000Mbps Ethernet device drivers. All drivers and utilities are stored in the ADLINK CD under the directory: X:\ATCA\ATCA-6890\LAN, where X is the CD drive letter. For driver installations under other operating systems, please refer to the the ADLINK CD.

During Windows XP/2000 Professional installation, the operating system will install a LAN driver automatically. To guarantee compatibility, manually install the most up-to-date driver, which is provided on the ADLINK CD. After installing the OS, update the driver by following these steps:

1. Run the self-extracting file pro2kxpm\_9.1.exe in the following directory:X:\ATCA\ATCA-6890\LAN.
2. Click through the subsequent pages to extract the files to the default location c:\Intel9.1.
3. Click Install Software to install the Intel® PRO Network Connections drivers.

# 5 Watchdog Timer

# 5.1 WDT Overview

The primary function of the Watchdog Timer is to monitor the aTCA-6890's operation and to generate an IRQ or to reset the system should the software fail to function as programmed. The major features of the Watchdog Timer are:

▶ Enabled and disabled through software control
▶ Armed and strobed through software control

The aTCA-6890's custom Watchdog Timer circuit is integrated into the south bridge 6300ESB and supports multiple modes: WDT and free-running. Free-running mode is a one stage timer and it will toggle WDT\_TOUT# after a programmable time. WDT mode is a two stage timer and its operation is described as follows:

# WDT Mode:

The two-stage Watchdog Timer (WDT) provides a resolution ranging from 1 micro second to 10 minutes. The timer uses a 35-bit down-counter. The counter is loaded with the value from the first Preload register. The timer is then enabled and starts counting down. The time at which the WDT first starts counting down is called the first stage. If the host fails to reload the WDT before the 35-bit down counter reaches zero the WDT generates an internal interrupt. After the interrupt is generated, the WDT loads the value from the second Preload register into the WDT's 35-bit down-counter and starts counting down. The WDT is now in the second stage. If the host still fails to reload the WDT before the second timeout, the WDT drives the WDT\_TOUT# pin low. The WDT\_TOUT# pin is held low until the system is reset.

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   PCI\n*   PCI Configuration Registers\n*   Preload Value 1\n*   Preload Value 2\n*   Down - Counter\n*   Reset/Interrupt Control Logic\n*   WDT_TOUT# (External)\n*   IRQ/SMI (Internal)\n\n**Connections:**\n*   **PCI** and **PCI Configuration Registers** are connected via a bidirectional arrow.\n*   **PCI Configuration Registers** connects to **Preload Value 1** and **Preload Value 2** via arrows pointing downward (from a shared horizontal line).\n*   **Preload Value 1** and **Preload Value 2** connect back to **PCI Configuration Registers** via arrows pointing leftward (from the same horizontal line).\n*   **Preload Value 1** and **Preload Value 2** connect to **Down - Counter** via arrows pointing downward.\n*   **PCI Configuration Registers** connects to **Down - Counter** via an arrow originating from the bottom of the registers and pointing into the counter.\n*   **Down - Counter** connects to **Reset/Interrupt Control Logic** via an arrow pointing downward.\n*   **Reset/Interrupt Control Logic** connects to **PCI Configuration Registers** via an arrow originating from the left side of the logic block and pointing upward into the bottom of the registers.\n*   **Reset/Interrupt Control Logic** connects to **WDT_TOUT# (External)** via an arrow pointing downward and to the left.\n*   **Reset/Interrupt Control Logic** connects to **IRQ/SMI (Internal)** via an arrow pointing downward and to the right.](.atca-6890-manual-10/2c94524cc720187128757c65d2af284a9708d920f8a98bbd842dca4d99d6624e.jpg)

Figure 5-1: WDT Block Diagram

# 5.2 Configuration Registers

The Intel® 6300ESB ICH WDT, appears to BIOS as PCI Bus 0, Device 29, Function 4, and has the standard set of PCI Configuration register. The following describes the configuration registers.

# Offset 10H: Base Address Register (BAR0)

This register determines the memory base for WDT down-counter setting. It will be used to set Preload value 1 register, Preload value 2 register, General Interrupt Status register and Reload register.

# Preload Value 1 & 2 registers

These two registers are used to hold the preload value for the WDT timer. Its value will be automatically transferred into the down-counter every time the WDT enters the first and second stage. Preload Value 1 register is located at Base + 00H and Pre-load Value 2 register is located at Base + 04H. Only bit [19:0] are settable.

The register unlocking sequence is necessary whenever writing to the Preload registers. Instructions for writing a value into preload value 1 & 2 registers are as follows:

1. Write 80H to offset BAR0 + 0CH.
2. Write 86H to offset BAR0 + 0CH.
3. Write desired value to preload register. (BAR0 + 00H or BAR0 + 04H)

# General Interrupt Status Register

This register is at Base + 08H. Bit 0 is set when the first stage of down-counter reaches zero.

Bit 0 = 0 - No Interrupt

Bit 1 = 1 - Interrupt Active

NOTE: This bit is not set in free running mode.

# Reload Register

This register is at Base + 0CH. Write 1 to bit 8 will reload the down-counter's value. Following is the procedure of how to prevent a timeout.

1. Write 80H to offset BAR0 + 0CH
2. Write 86H to offset BAR0 + 0CH
3. Write a '1' to RELOAD[8] of the reload register

# Offset 60 - 61H: WDT Configuration Register

Bit 5 indicates whether or not the WDT will toggle the WDT\_TOUT# pin when WDT times out. (0 = Enabled, 1 = Disabled)

Bit 2 provides two options for prescaling the main down-counter. (0 = 1ms - 10min, 1 = 1us - 1sec)

Bit [1:0] allows the user to choose the type of interrupt desired when the WDT reached the end of the first stage without being reset. (00 = IRQ, 01 = reserved, 10 = SMI, 11 = Disabled)

NOTE: The WDT does not support SMI now. IRQ uses APIC 1, INT 10 and it is active low, level triggered.

# Offset 68H: WDT Lock Register

Bit 2 is used to choose the functionality of the timer. (0 = Watchdog Timer mode, 1 = Free running mode) The free-running mode ignores the first stage and only uses Preload Value 2. In free-running mode it is not necessary to reload the timer as it is done automatically every time the down-counter reaches zero.

Bit 1 enables or disables the WDT. (0 = Disabled, 1 = Enabled)

Bit 0 will lock the values of this register until a hard reset occurs or power is cycled. (0 = unlocked, 1 = locked). The default is Unlocked.

# 5.3 GPIO Control Registers

There are three GPIOs on aTCA-6890 related to watchdog timer. They are listed as follows. The GPIO control base port is 480H.

# WDT\_TOUT# Pin Selection

WDT\_TOUT# signal is multiplexed with GPIO32. When using WDT, this signal must be switched to WDT\_TOUT# function. It uses bit 0 of GPIOBASE + 30H to set WDT\_TOUT function. (0 = WDT\_TOUT#, 1 = GPIO32)

# User LED Control

GPO25 of 6300ESB is designed to control User LED. Two features of User LED are supported on aTCA-6890. User LED lights or blinks.

The user can program this GPIO when running WDT configuration.

# User LED Light

Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE + 0CH determines the state of User LED. (0=dark, 1=light)

# User LED Blink

Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE + 18H enables User LED blinking function. (0=function normally, 1=enable blinking) The high and low times have approximately 0.5 seconds each.

# 5.4 WDT Programming Procedure

1. Make sure WDT\_TOUT# signal is enabled (not GPIO[32] function).
2. Set WDT output enable, prescaler and interrupt type into the WDT configuration register.
3. Get control base from the Base Address register.
4. Program Preload register's value according to unlocking sequence.
5. Set WDT timer mode into WDT Lock Register.
6. Enable WDT from WDT Lock register and program the functionality of the User LED.

To keep the timer from causing an interrupt or driving WDT\_TOUT#, the timer must be reloaded periodically. The frequency of reloads required is dependent on the value of the preload values. To reload the down-counter, the register unlocking sequence must be performed.

To disable WDT, set bit 1 of WDT Lock Register to 0.

# 5.5 WDT Utilities

ADLINK provides a demo DOS utility, hrwdt.exe, to assist the user in using the Watchdog Timer. It is included on the All-in-One CD under the directory:

# X:\ATCA\ATCA-6890\WDT

Under DOS, run "hrwdt /?" to access the onscreen help for the utility.

# 6 IPMC

# 6.1 IPMC Overview

The aTCA-6890 features a Pigeon Point Systems® powered BMR-AVRTM based IPM Controller (IPMC), which supports PICMG 3.0 R2.0 and IPMI 1.5 revision 1.1 specifications. The IPMC acts as a system level supervisor upon the aTCA-6890 blade, which is referred as Payload or FRU in this document. Including hot-swap behaviors, board-level cooling request, power budget allocation, and data transport E-keying exchange are all controlled by IPMC. This is a quick “HOW-TO...” guide to help users to access the payload state, to communicate with IPMC with supported IPM commands, to monitored sensor list, to read FRU EEPROM information, and to update the IPMC firmware in the field.

# 6.2 FRU States

ATCA specification defines two types of FRU that are visible to and controlled through the IPMI infrastructure:

7. Intelligent FRU, which physically include an IPM Controller.
8. Managed FRU, which are either Intelligent FRUs or represented by an Intelligent FRU and visible to the IPMI infrastructure.

Any FRU that enters an ATCA Shelf goes through a series of states to become active. The aTCA-6890 blade is defined as an Intelligent FRU to the ATCA shelf, so that its FRU states and state transitions are well defined as in Table-1: FRU States and Figure-1: FRU State Transitions.

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **M0**: FRU Not Installed\n*   **M1**: FRU Inactive\n*   **M2**: FRU Activation Request\n*   **M3**: FRU Activation In Progress\n*   **M4**: FRU Active\n*   **M5**: FRU Deactivation Request\n*   **M6**: FRU Deactivation In Progress\n\n**Connections:**\n*   **M1** to **M2**: 'Insertion Criteria Met'\n*   **M2** to **M1**: 'Extraction Criteria Met (e.g. Eyebone open)'\n*   **M1** to **M0**: 'Normal Insertion'\n*   **M0** to **M1**: 'Normal Extraction'\n*   **M2** to **M3**: 'Set FRU Activation (Activate FRU)'\n*   **M3** to **M4**: 'Activation Complete (i.e. Power Budget Granted, possibly E-Keys set)'\n*   **M3** to **M6**: 'Set FRU Activation (Deactivate FRU) or Extraction Criteria Met'\n*   **M4** to **M5**: 'Extraction Criteria Met'\n*   **M5** to **M4**: 'Set FRU Activation (Activate FRU)'\n*   **M5** to **M4**: 'Insertion Criteria Met'\n*   **M6** to **M4**: 'Set FRU Activation (Activate FRU) or Unexpected Deactivation'\n*   **M5** to **M6**: 'Set FRU Activation (Deactivate FRU)'\n*   **M6** to **M1**: 'Deactivation Complete (i.e. power no longer used, E-Keyed interfaces are not in use)'](.atca-6890-manual-10/9460a1db5da449ed8b941772a357688f93a125e3801d24c7aa5ba5d181cef105.jpg)

Figure 6-1: FRU State Transitions

<table><tr><td>State #</td><td>State name</td><td>Additional information</td><td>FRU Events generated</td><td>Notable commands received</td><td>BLUE LED</td></tr><tr><td>M0</td><td>FRU Not Installed</td><td>The FRU is not installed. Outputs and inputs to/from the FRU are fully disabled including all power.</td><td>HotSwap Event</td><td></td><td>off</td></tr><tr><td>M1</td><td>FRU Inactive</td><td>The FRU is installed and IPM Controller is operational, but Payload is not powered. Outputs and inputs to/from FRU Payload are fully disabled. FRU may be extracted safely.</td><td>HotSwap Event (State changed to M1 from M0 (optional), M2, or M6)</td><td>Set FRU Activation Policy</td><td>on</td></tr><tr><td>M2</td><td>FRU Activation Request</td><td>The FRU is ready to attempt activation. Outputs and inputs to/from FRU are fully disabled including Payload power. The FRU waits in M2 for the Shelf Manager to send the “Set FRU Activation” command. The Shelf Manager queries the FRU for important SDRs to expose to the System Manager.</td><td>HotSwap Event (State changed to M2 from M1)</td><td>SDR Repository related commands. Set FRU Activation (Activate FRU)</td><td>long blink</td></tr><tr><td>M3</td><td>FRU Activation in Process</td><td>The FRU is preparing to become active. The FRU cannot be extracted safely while in this state. The Shelf Manager negotiates with the FRU to allocate its power budget. Once granted a power budget, the Payload begins powering up and may perform initialization and/or self-tests during this time. The FRU automatically transitions to M4 at its discretion when it determines that activation is complete and the FRU is operational.</td><td>HotSwapEvent (State changed to M3 from M2)</td><td>Power and Cooling commands. E-keying Commands Set FRU Activation (Deactivate FRU)</td><td>off</td></tr><tr><td>M4</td><td>FRU Active</td><td>Normal operational state. Power has been applied, and the FRU cannot be extracted safely. The FRU may be reset and remain in this state. The FRU can initiate a deactivation request (i.e., move to M5) when Extraction Criteria Met occurs. Alternatively, the Shelf Manager can move the FRU to M6 by sending a “Set FRU Activation (Deactivate FRU)&quot;.</td><td>HotSwapEvent (State changed to M4 from M3 or M5)</td><td>Set FRU Activation (Deactivate FRU)</td><td>off</td></tr></table>

Table 6-1: FRU States

<table><tr><td>State #</td><td>State name</td><td>Additional information</td><td>FRU Events generated</td><td>Notable commands received</td><td>BLUE LED</td></tr><tr><td>M5</td><td>FRU Deactivation Request</td><td>The FRU is requesting deactivation permission from the Shelf Manager. The FRU cannot yet be extracted safely. From the Payload&#x27;s perspective, this is equivalent to M4.</td><td>HotSwapEvent (State changed to M5 from M4)</td><td>Set FRU Activation (Deactivate FRU | Activate FRU)</td><td>short blink</td></tr><tr><td>M6</td><td>FRU Deactivation In Progress</td><td>The FRU is closing down its application and preparing to be deactivated. I/O connections are being closed. The FRU cannot yet be extracted safely. The power to the FRU&#x27;s Payload is turned off before leaving this state. The FRU automatically transitions to M1 when it determines that deactivation is complete and it can be safely extracted.</td><td>HotSwapEvent (State changed to M6 from M3, M4, or M5)</td><td></td><td>short blink</td></tr><tr><td>M7</td><td>Comm. Lost</td><td>This is an abnormal state and is described in Section 3.2.4.4Activation (Deactivate FRU)&quot;.</td><td></td><td></td><td>same as before M7 entry</td></tr></table>

Table 6-1: FRU States

# 6.3 Accessing the IPMC

There are three methods to access IPMC:

1. Shelf Management Controller (ShMC)

ShMC can issue IPM commands via IPMB buses between ShMC and payload on the backplane.

2. Payload Port

Payload can issue IPM commands via the serial port COM3 to the IPMC, with 9600 Baud rate. Please refer to the FIRMWARE /FRU EEPROM UPDATE section for more details.

3. IPMC Debug Port

Users can set on-board DIP switch SWY1 to configure front panel COM1 directly connected to IPMC serial debug port. Please refer to the FIRMWARE /FRU EEPROM UPDATE section for more details.

Users can get IPMC firmware revision, operating mode, FRU state, debug messages, and alerts by one of the three access methods.

![**Key**\nA legend at the top left titled 'Key' defines the color coding:\n*   **Blue:** 'IPM Controller (IPMC)'\n*   **Grey:** 'Shelf Management Controller (ShMC)'\n*   **Pink:** 'AdvancedTCA Board'\n*   **Red:** 'Shelf Manager w/ Dedicated ShMC'\n*   **White:** 'Other Field Replaceable Unit (FRU)'\n\n**Left-Side Components**\n*   A cloud shape labeled **'Shelf-External System Manager'** is connected to two red blocks below it:\n    *   **'Shelf Manager (Active)'**\n    *   **'Shelf Manager (Backup)'**\n    *   Inside each red 'Shelf Manager' block is a smaller grey box labeled **'ShMC'**.\n*   To the right of the Shelf Managers is a large white block labeled **'Fan Tray'**.\n*   Connected to the Fan Tray area are two white blocks labeled **'Power Entry Module'**.\n*   A dashed line labeled **'Implementation Dependent Connection'** connects the Power Entry Modules to a small blue block labeled **'IPMC'**.\n\n**Central Bus**\nA thick black vertical line connects all components on the left to the components on the right. It has two labels:\n*   **'2x Redundant Radial Internet-Protocol-Capable Transport'** (along the lower section).\n*   **'2x Redundant, Bussed or Radial, IPMB-0'** (along the upper section).\n\n**Right-Side Components**\nA column of eight identical pink blocks labeled **'ATCA Board'** connects to the central bus. Inside each pink 'ATCA Board' block is a small blue box labeled **'IPMC'**.](.atca-6890-manual-10/482422c640890d58c2056deb8cb3c225c35a99f25626173628f5063c00994d4c.jpg)

Figure 6-2: ATCA System Management Architecture

# 6.4 IPMI Command Set

The IPMC firmware is fully compliant with PICM 3.0 R2.0 and relevant ECN. Please refer to Table-2 for the commands supported:

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>IPM Controller Req</td></tr><tr><td colspan="5">IPM Device “Global” Commands</td></tr><tr><td>Get Device ID</td><td>17.1</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td>Cold Reset</td><td>17.2</td><td>App</td><td>02h</td><td>Optional</td></tr><tr><td>Warm Reset</td><td>17.3</td><td>App</td><td>03h</td><td>Optional</td></tr><tr><td>Get Self Test Results</td><td>17.4</td><td>App</td><td>04h</td><td>Mandatory</td></tr><tr><td>Get Device GUID</td><td>17.8</td><td>App</td><td>08h</td><td>Optional</td></tr><tr><td>Broadcast “Get Device ID”</td><td>17.9</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td colspan="5">IPMI Messaging Support Commands</td></tr><tr><td>Send Message</td><td>18.7</td><td>App</td><td>34h</td><td>Optional</td></tr><tr><td colspan="5">BMC Watchdog Timer</td></tr><tr><td>Reset Watchdog Timer</td><td>21.5</td><td>App</td><td>22h</td><td>Mandatory</td></tr><tr><td>Set Watchdog Timer</td><td>21.6</td><td>App</td><td>24h</td><td>Mandatory</td></tr><tr><td>Get Watchdog Timer</td><td>21.7</td><td>App</td><td>25h</td><td>Mandatory</td></tr><tr><td colspan="5">Event Commands</td></tr><tr><td>Set Event Receiver</td><td>23.1</td><td>S/E</td><td>00h</td><td>Mandatory</td></tr><tr><td>Get Event Receiver</td><td>23.2</td><td>S/E</td><td>01h</td><td>Mandatory</td></tr><tr><td>Platform Event (a.k.a. “Event Message”)</td><td>23.3</td><td>S/E</td><td>02h</td><td>Mandatory</td></tr><tr><td colspan="5">Sensor Device Commands</td></tr><tr><td>Get Device SDR Info</td><td>29.2</td><td>S/E</td><td>20h</td><td>Mandatory</td></tr><tr><td>Get Device SDR</td><td>29.3</td><td>S/E</td><td>21h</td><td>Mandatory</td></tr><tr><td>Reserve Device SDR Repository</td><td>29.4</td><td>S/E</td><td>22h</td><td>Mandatory</td></tr><tr><td>Get Sensor Reading Factors</td><td>29.5</td><td>S/E</td><td>23h</td><td>Optional</td></tr><tr><td>Set Sensor Hysteresis</td><td>29.6</td><td>S/E</td><td>24h</td><td>Optional</td></tr><tr><td>Get Sensor Hysteresis</td><td>29.7</td><td>S/E</td><td>25h</td><td>Optional</td></tr><tr><td>Set Sensor Threshold</td><td>29.8</td><td>S/E</td><td>26h</td><td>Optional</td></tr><tr><td>Get Sensor Threshold</td><td>29.9</td><td>S/E</td><td>27h</td><td>Optional</td></tr><tr><td>Set Sensor Event Enable</td><td>29.10</td><td>S/E</td><td>28h</td><td>Optional</td></tr><tr><td>Get Sensor Event Enable</td><td>29.11</td><td>S/E</td><td>29h</td><td>Optional</td></tr><tr><td>Rearm Sensor Events</td><td>29.12</td><td>S/E</td><td>2Ah</td><td>Optional</td></tr></table>

Table 6-2: Supported IPMI Commands

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>IPM Controller Req</td></tr><tr><td>Get Sensor Event Status</td><td>29.13</td><td>S/E</td><td>2Bh</td><td>Optional</td></tr><tr><td>Get Sensor Reading</td><td>29.14</td><td>S/E</td><td>2Dh</td><td>Mandatory</td></tr><tr><td colspan="5">FRU Device Commands</td></tr><tr><td>Get FRU Inventory Area Info</td><td>28.1</td><td>Storage</td><td>10h</td><td>Mandatory</td></tr><tr><td>Read FRU Data</td><td>28.2</td><td>Storage</td><td>11h</td><td>Mandatory</td></tr><tr><td>Write FRU Data</td><td>28.3</td><td>Storage</td><td>12h</td><td>Mandatory</td></tr><tr><td colspan="5"> $AdvancedTCA^{TM}$ </td></tr><tr><td>Get PICMG Properties Command</td><td>3-9</td><td>PICMG</td><td>00h</td><td>Mandatory</td></tr><tr><td>Get Address Info</td><td>3-8</td><td>PICMG</td><td>01h</td><td>Optional</td></tr><tr><td>FRU Control Command</td><td>3-21</td><td>PICMG</td><td>04h</td><td>Mandatory</td></tr><tr><td>Get FRU LED Properties Command</td><td>3-23</td><td>PICMG</td><td>05h</td><td>Mandatory</td></tr><tr><td>Get LED Color Capabilities Command</td><td>3-24</td><td>PICMG</td><td>06h</td><td>Mandatory</td></tr><tr><td>Set FRU LED State</td><td>3-25</td><td>PICMG</td><td>07h</td><td>Mandatory</td></tr><tr><td>Get FRU LED State</td><td>3-26</td><td>PICMG</td><td>08h</td><td>Mandatory</td></tr><tr><td>Set IPMB State Command</td><td>3-47</td><td>PICMG</td><td>09h</td><td>Mandatory</td></tr><tr><td>Set FRU Activation Policy Command</td><td>3-16</td><td>PICMG</td><td>0Ah</td><td>Mandatory</td></tr><tr><td>Get FRU Activation Policy Command</td><td>3-17</td><td>PICMG</td><td>0Bh</td><td>Mandatory</td></tr><tr><td>Set FRU Activation Command</td><td>3-15</td><td>PICMG</td><td>0Ch</td><td>Mandatory</td></tr><tr><td>Get Device Locator Record ID Com-mand</td><td>3-28</td><td>PICMG</td><td>0Dh</td><td>Mandatory</td></tr><tr><td>Get Port State</td><td>3-40</td><td>PICMG</td><td>0Eh</td><td>Mandatory</td></tr><tr><td>Set Port State</td><td>3-41</td><td>PICMG</td><td>0Fh</td><td>Mandatory</td></tr><tr><td>Compute Power Properties</td><td>3-56</td><td>PICMG</td><td>10h</td><td>Mandatory</td></tr><tr><td>Set Power Level</td><td>3-58</td><td>PICMG</td><td>11h</td><td>Mandatory</td></tr><tr><td>Get Power Level</td><td>3-57</td><td>PICMG</td><td>12h</td><td>Mandatory</td></tr><tr><td>Get Fan Speed Properties</td><td>3-59</td><td>PICMG</td><td>14h</td><td>Mandatory</td></tr><tr><td>Get Fan Level</td><td>3-60</td><td>PICMG</td><td>16h</td><td>Optional</td></tr><tr><td>Set Fan Level</td><td>3-61</td><td>PICMG</td><td>15h</td><td>Optional</td></tr><tr><td>Bused Resource Control (Release, Query, Force, Bus Free)</td><td>3-43</td><td>PICMG</td><td>17h</td><td>Mandatory</td></tr></table>

Table 6-2: Supported IPMI Commands

# 6.5 Sensor Data Record List

This section lists all sensor parameters in Sensor Data Record (SDR) and are organized according to type for easy reference. For threshold sensors, all threshold value and asset/dessert events are listed. For discrete sensors, only the name and type are listed. Detailed type and offset codes can be found in the IPMI and the ATCA specification.

<table><tr><td>No.</td><td>Name</td><td>Type</td></tr><tr><td>1</td><td>Hot Swap Hot</td><td>Swap</td></tr><tr><td>2</td><td>IPMB Physical</td><td>IPMB Link</td></tr><tr><td>3</td><td>BMC Watchdog</td><td>Watchdog2</td></tr><tr><td>4</td><td>W83784 system temp</td><td></td></tr><tr><td>5</td><td>CPU#0 temp</td><td></td></tr><tr><td>6</td><td>CPU#1 temp</td><td></td></tr><tr><td>7</td><td>+3.3V</td><td></td></tr><tr><td>8</td><td>+1.8V</td><td></td></tr><tr><td>9</td><td>+1.5V</td><td></td></tr><tr><td>10</td><td>+5.0V</td><td></td></tr><tr><td>11</td><td>HW Monitor SMI</td><td></td></tr><tr><td>12</td><td>HW Monitor Over Temperature</td><td></td></tr><tr><td>13</td><td>HW Monitor WatchDog Time-out</td><td></td></tr><tr><td>14</td><td>ICH WatchDog Time-out</td><td></td></tr><tr><td>15</td><td>CPU FERR</td><td></td></tr><tr><td>16</td><td>CPU IERR</td><td></td></tr><tr><td>17</td><td>MCH/PXH OverTemperature</td><td></td></tr><tr><td>18</td><td>Payload System Sleep State 5 (SLPS5#)</td><td></td></tr><tr><td>19</td><td>Payload Power OK</td><td></td></tr><tr><td>20</td><td>BIOS POST OK</td><td></td></tr></table>

Table 6-3: Discrete Based Sensors

# 6.6 FRU Storage Information

FRU Storage holds text and static properties for this board. Here is a brief description of the FRU fields. Detailed access methods can be found in the IPMI Platform Management FRU Information Storage Definition V1.0, Document Revision 1.1.

# For Option 1:

[Common Header]

Version = 1

[Board Info]

Version = 1

Language Code = en

Mfg Date/Time = 03/07/2005

Manufacturer = ADLINK Technology

Product Name = ATCA-6890

Serial Number = 0000000000

Part Number = ATCA-6890

FRU Programmer File ID = fru16-opt2.inf

[Product Info]

Version = 1

Language Code = en

Manufacturer = ADLINK Technology

Product Name = ATCA-6890 (board)

Part/Model Number = ATCA-6890

Product Version = Rev 1.6

Serial Number = 0000000000

Asset Tag = N/A

FRU File ID = fru16-opt2.inf

[Board Connectivity]

Base, 1, 0 = Base, 0

Base,2,0 = Base,0

Fabric, 1, 0 = Ethernet, 0

Fabric,2,0 = Ethernet,0

Fabric, 1, 1 = Ethernet, 0

Fabric,2,1 = Ethernet,0

# For Option 2:

[Common Header]

Version = 1

[Board Info]

Version = 1

Language Code = en

Mfg Date/Time = 05/02/2005

Manufacturer = ADLINK Technology

Product Name = ATCA-6890

Serial Number = 0000000000

Part Number = ATCA-6890

FRU Programmer File ID = fru17-opt2.inf

[Product Info]

Version = 1

Language Code = en

Manufacturer = ADLINK Technology

Product Name = ATCA-6890 (board)

Part/Model Number = ATCA-6890

Product Version = Rev 1.7

Serial Number = 0000000000

Asset Tag = N/A

FRU File ID = fru17-opt2.inf

[Board Connectivity]

Base, 1, 0 = Base, 0

Base,2,0 = Base,0

Fabric, 1,0 = Ethernet,0

Fabric,2,0 = Ethernet,0

Fabric, 1, 1 = Ethernet, 0

Fabric,2,1 = Ethernet,0

Fabric, 1,0 1 = Ethernet, 0

Fabric,2,0 1 = Ethernet,0

# 6.7 Firmware/FRU EEPROM Update

As mentioned in the previous ACCESS IPMC section, there are three methods to update IPMC firmware and FRU EEPROM.

1. ShMC access. Users will need the update utilities to run on ShMC. The IPMC firmware / FRU EEPROM update utilities will be dependent and provided by the ShMC provider.
2. IPMC debug port. Users will need another system with at least one serial port cross-over linked to aTCA-6890 IPMC debug port. Contact ADLINK for the update utilities.
3. IPMC payload port. Users will only need ADLINK utilities to run on aTCA-6890 by IPMC payload port (COM3).

Note: The payload (aTCA-6890) will be reset by IPMC after firmware update completed.

# Update Procedures

1. Decide which method to proceed

2. When IPMC debug port is used:

1. Tap on-board SWY1 (1,4:OFF; 2,3:ON) to switch IPMC debug port linked to COM1 connector.
2. Apply the RJ-45 to DB-9 male adapter on front panel COM1, and then use a cross-over DB-9 to DB-9 female cable connected after the adapter linking to the serial port of another Service system.
3. Power up the CPU blade and Service system. Run ADLINK IPMC firmware update utilities on the Service system, with the following syntax:

upgradefw -s &lt;device&gt;:&lt;baud rate&gt; &lt;image filename&gt;

where &lt;device&gt;= serial port on Service system (COM1/2/3 etc.) &lt;baud rate&gt;=9600 only.

For Windows OS, use the following command in a DOS prompt: upgradefw -s COM1:9600,N,8,1 upgrade.img

For Linux OS, use the following command in a terminal shell: upgradefw -s /dev/ttyS0:9600,N,8,1 upgrade.img

4. The following messages will be shown as update completed.

BMR-AVR firmware upgrade utility. Pigeon Point Systems © 2004

Upgrade interface: serial, device: /dev/ttyS0, options:

Firmware upgrade image: upgrade.img

Preparing Master AVR for programming ...... OK

Programming 43183 bytes to Master AVR at 000000 ... 100%

Preparing Slave AVR for programming ... OK

Programming 8161 bytes to Slave AVR at 000000 ... 100%

3. When IPMC payload port is used:

1. Prepare a DOS-bootable device, e.g. an USB flash.

2. Contact ADLINK for IPMC payload port utilities.

3. Power up the CPU blade and boot into DOS with utilities and updated images.

4. Run ADLINK IPMC payload port firmware update utilities on the CPU blade, with the following syntax:

# bmrupd -s COM3:9600 &lt;image filename&gt;

5. The following messages will be shown as update completed.

BMR-AVR firmware upgrade utility. Pigeon Point Systems (c) 2004.

DOS version 1.1 ported by ADLINK 2004/11/14.

Upgrade interface: serial, device: COM3, options: 9600

Firmware upgrade image: fw163o2.img

Preparing Master AVR for programming ...... OK

Programming 45945 bytes to Master AVR at 000000 ... 100%

Preparing Slave AVR for programming ... OK

Programming 7201 bytes to Slave AVR at 000000 ... 100%

# 4. FRU EEPROM update, use IPMC payload port:

1. Prepare as 3.1 to 3.3
2. Run ADLINK IPMC payload FRU EEP update utility on the CPU blade, with the following syntax:

fruupd -s COM3:9600 -f &lt;fru\_image\_filename&gt;

3. The following messages will be shown as update completed.

FRU UPDATE UTILITY v 1.1 11/14/2005 - BMR-AVR
FRU update tool

Copyright(c) 2005, ADLINK Technology. All Rights Reserved

Opening port: COM3:9600

Opening file: fru18o2.bin

Sending data...Reading data... .....

Sending data...Reading data... .....

Sending data...Reading data... .....

Sending data...Reading data... .....

Sending data...Reading data... .....

frutool: done!

# 6.8 Misc. Notes

# SEL (System Event Log):

There is no local SEL. Events are sent to the shelf manager, and the payload is notified over the payload serial interface.

# OOS LED (Out of Service):

OOS LED is ON when any of the following conditions is true:

▶ System power instable, (SYS\_PWROK alarm), or
▶ System POST is not completed (POSTOK alarm), or
▶ CPU Internal Errors (CPU\_FERR#, CPU\_IERR# alarms), or
▶ System goes into SOFTOFF state (PM\_SLPS5# alarm)

# Ejector Handle and Power Button:

On detecting the lower handle opened, IPMC will issue a POWER BUTTON (PWRBTN#) event to notify system into SOFTOFF state (PM\_SLPS5#)

# Sleep S5:

When the payload enters the SOFTOFF state, its FRU state will deactivate and transition to M1. IPMC will turn off payload power, and turn on the blue HS LED.

If user shutdown the OS by commands, the lock bit will be enabled and caused the payload to enter SOFTOFF state, even the lower handle is closed. Users will need to open and close the handle to power-up the payload again and transition back to M4.

# Shutdown:

The shutdown timeout is 25.5 second. The payload will be powered off after PM\_SLPS5# is asserted or after the timeout expires. The blue LED will short blink while waiting to shutdown.

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/.

2. All ADLINK products come with a limited two-year guarantee, one year for products bought in China:

The warranty period starts on the day the product is shipped from ADLINK's factory.

▶Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.

▶For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for loss of data.

▶Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.

▶For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's guarantee in the following situations:

▶Damage caused by not following instructions in the User's Manual.

▶Damage caused by carelessness on the user's part during product transportation.

▶Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.

▶Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).

▶Damage caused by leakage of battery fluid during or after change of batteries by customer/user.

▶Damage from improper repair by unauthorized ADLINK technicians.

▶Products with altered and/or damaged serial numbers are not entitled to our service.

▶This warranty is not transferable or extendible.

▶Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport damaged products to our company or sales office.

If you have any further questions, please email our FAE staff: service@adlinktech.com.
[🔗 Link to the original document](.atca-6890-manual-10/atca-6890-manual-10.pdf)