| Standards | PICMG 3.0 R2.0 AdvancedTCAPICMG 3.1 option 1/9 Ethernet over AdvancedTCAAMC.0 Advanced Mezzanine Card R2.0AMC.1 PCI Express® R1.0AMC.2 Gigabit Ethernet R1.0AMC.3 Storage R1.0 |
| Gigabit Ethernet | Intel® 82571EB PCI-Express Gigabit Ethernet controllersFour 10/100/1000BASE-T ports on face plate and Base Interface channels 1-2 |
| Serial ATA | Four Serial ATA II ports from ICH9R, two to AMC, two to RTMIntel Matrix Storage Driver RAID 0/1/5 |
| Serial Attached SCSI | Four SAS ports from LSISAS1064E, two to AMC, two to RTM |
| Display | ATI ES1000 graphics controller with 2D acceleratorDDR2-533 64MB memoryAnalog RGB up to 1600x1200@75Hz refresh rate |
| USB | Three USB v2.0 ports |
| Serial | One RJ-45 RS-232 port |
| Storage | On-board 4GB USB NAND FlashAMC.3 SATA/SASTwo SATA and two SAS ports on RTM |
| Front panel I/O | 1x VGA port (DB-15)3x USB 2.0 port (Type-A)1x RS-232 port (RJ45)2x GbE ports (RJ45)LEDs: OOS, Media, Power and HotswapRecessed reset button |
| Rear I/O | PCI-E x4 from 5100MCH2x GbE ports from BCM563124x USB 2.0 ports2x SATA ports from ICH9R2x SAS/SATA ports from LSISAS1064ERear IO signals from AMC#1 |
# 2.3 Software
| Form factor | • 322.25mm x 280mm x 30.48mm (6HP) |
| Operating temperature | • Standard: 0°C to 45°C• NEBS short-term: 0°C to 55°C |
| Storage temperature | • -40°C to 85°C |
| Humidity | • 5% to 90% non-condensing |
| Shock | • 15G peak-to-peak, 11ms duration, non-operation |
| Vibration | • Non-operating: 1.88G rms, 5 to 500 Hz, each axis• Operating: 0.5G rms. 5 to 500Hz, each axis |
| Compliance | • CE, FCC Class A, CUL, NEBS Level 3 (design) |
# 2.5 Power Consumption
This section provides information on the power consumption of aTCA-6900.
# System Configuration
▶ Memory: Transcend 2G DDR2 667 REG-D CL5
▶ Graphics: ATI ES1000
▶ AMC Bay: ADLINKTECH aDB-7000 rev.A1
▶ Power Supply: SUNPOWER SPS-600P-48
▶ CPU:
Intel® Quad-Core Xeon® processor L5408
Intel® Dual-Core Xeon® processor LV 5138
The following table describes power consumption of the aTCA-6900 using real applications with a 48V power rail under various operating systems.
| BASE Channel and Fabric Channel LED |
| BCH2 Speed and Link100 Mbps: Green1Gbps: Amber | <img src="images/2ea491b9c13edce56eb2ba9166ce90987d94f25e1902a2756de023053c32b6e7.jpg"/> | Fabric 2 Speed and Link1Gbps - Green10Gbps - Amber |
| BCH2 ACTBlink when accessingEthernet I/O | Fabric 2 ACTBlink when accessingEthernet I/O |
| BCH1 Speed and Link100 Mbps: Green1Gbps: Amber | Fabric 1 Speed and Link1Gbps - Green10Gbps - Amber |
| BCH1 ACTBlink when accessingEthernet I/O | Fabric 1 ACTBlink when accessingEthernet I/O |
GbE LED
# 2.9 Compliance
The aTCA-6900 conforms to the following specifications:
▶ PCIMG 3.0 R2.0 ECN0001 AdvancedTCA
▶ PICMG 3.1 Ethernet over AdvancedTCA option 1 and 9
▶ AMC.0 Advanced Mezzanine Card R2.0 Midsize
▶ AMC.1 PCI Express R1.0
▶ AMC.2 E2 / Type 3
▶ AMC.3 Storage R1.0
This page intentionally left blank.
# 3 Functional Description
# 3.1 CPU, Memory and Chipset
CPU
# Two Dual-Core Intel® LV 5138 Processors
The aTCA-6900 supports two Dual-Core Intel® LV-5138 processors at 2.13GHz with 1066MHz FSB and 4MB L2 cache. The Dual-Core Intel® Xeon® Processor 5100 Series are 64-bit server processors utilizing two Intel microarchitecture cores. These processors are based on Intel's 65 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. Some key features include on-die, 32 KB Level 1 instruction and data caches and 4 MB Level 2 cache with Advanced Transfer Cache Architecture. The processors' Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible.
Enhanced thermal and power management capabilities are implemented including Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. These technologies are targeted for dual processor in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep® Technology provides power management capabilities to servers and workstations.
The Dual-Core Intel® Xeon® Processor LV-5138 features include Advanced Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. It also supports Intel® Extended Memory 64 Technology (Intel® EM64T) as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology.
# Two Quad-Core Intel® L5408 Processors
In addition to two Dual-Core LV-5138 processors, the aTCA-6900 also supports two Quad-Core Intel L5408 Xeon processors. The Quad-Core Intel® Xeon® Processor L5408 is a server processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel's 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. Some key features include on-die, primary 32-kB instruction cache and 32-kB write-back data cache in each core and 12 MB (2 x 6MB) Level 2 cache with Intel® Advanced Smart Cache Architecture. The processors' Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced effective bus latency and improved performance. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible.
Enhanced thermal and power management capabilities are implemented including Intel® Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. These technologies are targeted for dual processor configurations in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations.
Quad-Core Intel® Xeon® Processor L5408 features include Intel® Wide Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Streaming SIMD Extensions 4.1 (SSE4.1). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations.
It also supports Intel® 64 Architecture as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology.
# Supported Processors, Maximum Power Dissipation
The following tables describe the processors supported on the aTCA-6900 and their maximum power dissipation.
| ICH9R | I/O | Signal | Description |
| GPI[0] | Input | LPC_PME-L | LPC power management event |
| GPI[8] | Input | ICH_GPIO8 | Debug from MCH ERR-L1 |
| GPI[10] | Input | ICH_GPIO10 | Debug from MCH ERR-L2 |
| GPO[15] | Output | PCI_STOP-L | PCI stop to clock generator |
| GPI[19] | Input | 3255_INT_REQ1 | Interrupt request 1 from IDT82V3255 |
| GPI[21] | Input | 3255_INT_REQ2 | Interrupt request 2 from IDT82V3255 |
| GPI[22] | Input | LPC_SMI-L | LPC system management interrupt from IPMC |
| CPO[25] | Output | CLK_CPU_STOP-L | CPU stop to clock generator |
| GPO[32] | Output | POSTOK-L | POST OK to IPMC |
| GPO[34] | Output | USERLED | User defined LED, default = Power LED |
| GPI[38] | Input | ICH_GPIO38 | Debug from MCH ERR-L10 |
| GPO[39] | Output | ICH_CPU0_FORCEPR-L | CPU0 forced protection |
| GPO[48] | Output | ICH_CPU1_FORCEPR-L | CPU1 forced protection |
| GPI[57] | Input | W83627_OVT-L | W83627 over-temperature event |
| GPO[58] | Output | 3255_CS-L2 | Chip select to IDT82V3255 |
# 3.3 I/O Interfaces
# USB
The aTCA-6900 supports eight USB 2.0 ports:
▶ three Type-A ports on front panel
▶ four ports routed to RTM
▶ one channel for 4GB on-board NAND flash
On the USB 2.0 front panel port, a USB cable with up to 5 meters in length can be used.
On the USB 2.0 Rear I/O ports, it is strongly recommended to use a cable below 3 meters in length for USB 2.0 devices.
The USB 2.0 ports are high-speed, full-speed, and low-speed capable. Hi-speed USB 2.0 allows data transfers of up to 480 Mb/s, 40 times faster than a full-speed USB (USB 1.1). One USB peripheral may be connected to each port.
Front Panel USB Connector (CN9-11)
| Item | Sensor Name | Sensor Address | Description |
| (1) | Hotswap | (0x0) | FRU Hotswap Sensor. Please refer to section 4.2.1 |
| (2) | Shelf FRU Hotswap | (0x1) | FRU Hotswap Sensor. Please refer to section 4.2.1 |
| (3) | Hot Swap AMC 1 | (0x2) | AMC#1 Hotswap Sensor. Please refer to section 4.2.1 |
| (4) | Hot Swap AMC 2 | (0x3) | AMC#2 Hotswap Sensor. Please refer to section 4.2.1 |
| (5) | Hot Swap AMC 3 | (0x4) | RTM Hotswap Sensor. Please refer to section 4.2.1 |
| (6) | +5.0V | (0x5) | Voltage Sensor. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 5.5 VoltsUpper Critical Threshold = 5.4 VoltsUpper Non-Critical Threshold = 5.3 VoltsLower Non-Critical Threshold = 4.7 VoltsLower Critical Threshold = 4.6 VoltsLower Non-Recoverable Threshold = 4.5 Volts |
| (7) | +3.3V | (0x6) | Voltage Sensor. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 3.63 VoltsUpper Critical Threshold = 3.564 VoltsUpper Non-Critical Threshold = 3.498 VoltsLower Non-Critical Threshold = 3.102 VoltsLower Critical Threshold = 3.036 VoltsLower Non-Recoverable Threshold = 2.97 Volts |
| (8) | +1.8V | (0x7) | Voltage Sensor. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 1.98 VoltsUpper Critical Threshold = 1.944 VoltsUpper Non-Critical Threshold = 1.908 VoltsLower Non-Critical Threshold = 1.692 VoltsLower Critical Threshold = 1.656 VoltsLower Non-Recoverable Threshold = 1.62 Volts |
| (9) | +1.5V | (0x8) | Voltage Sensor. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 1.65 VoltsUpper Critical Threshold = 1.62 VoltsUpper Non-Critical Threshold = 1.59 VoltsLower Non-Critical Threshold = 1.41 VoltsLower Critical Threshold = 1.38 VoltsLower Non-Recoverable Threshold = 1.35 Volts |
| (10) | +1.2V | (0x9) | Voltage Sensor. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 1.32 VoltsUpper Critical Threshold = 1.296 VoltsUpper Non-Critical Threshold = 1.272 VoltsLower Non-Critical Threshold = 1.034 VoltsLower Critical Threshold = 1.012 VoltsLower Non-Recoverable Threshold = 0.99 Volts |
| (11) | IPMB Physical | (0xa) | Physical IPMB Sensor. Please refer to section 4.2.2 |
| (12) | W83627 OVT | (0xb) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)OVT#/SMI#: Can create interrupts that depend on the temperatures measured by SYSTIN and CPUTIN. This mode is enabled by setting THYST (Temperature Hysteresis) to 127°C. |
| (13) | SIO THERM | (0xc) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)Same as W83627 OVT. |
| (14) | SIO WDT | (0xd) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)Watchdog timer output signal. The time-out counter ranges from 1 to 255 minutes in the minute mode, or 1 to 255 seconds in the second mode. |
| (15) | ICH THRM | (0xe) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)Thermal Alarm: Active low signal generated by external hardware to generate an SMI# or SCI. |
| (16) | CPU THERMTRIP | (0xf) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor. |
| (17) | FSB FERR | (0x10) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)FERR# (floating-point error) is qualified by STPCLK#. When STPCLK# is not asserted, FERR# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR# indicates that the processor has a pending break event waiting for service. The assertion of FERR# indicates that the processor should be returned to the Normal state. |
| Item | Sensor Name | Sensor Address | Description |
| (18) | FSB IERR | (0x11) | Discrete Sensor(Normal:0x0001, Abnormal:0x0002)IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. |
| (19) | SYS PWROK | (0x12) | Discrete Sensor(Normal:0x0002, Abnormal:0x0001)PWROK is asserted by a processor as the result of a power fail. |
| (20) | BMC Watchdog | (0x14) | Watchdog Timer Sensor. Please refer to section 4.2.3 |
| (21) | Version change | (0x15) | Version Change Sensor. Please refer to section 4.2.4 |
| (22) | LM75 SYS Temp | (0x16) | System Temperature. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 95 °CUpper Critical Threshold = 75 °CUpper Non-Critical Threshold = 60 °C |
| (23) | CPU0 Temp | (0x17) | CPU Temperature. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 100 °CUpper Critical Threshold = 80 °CUpper Non-Critical Threshold = 65 °C |
| (24) | CPU1 Temp | (0x18) | CPU Temperature. Please refer to section 4.2.5Upper Non-Recoverable Threshold = 100 °CUpper Critical Threshold = 80 °CUpper Non-Critical Threshold = 65 °C |
Table 4-1: aTCA-6900 IPMI Sensors
# 4.2.1 Get Sensor Reading (FRU Hotswap Sensor)
| Byte | Data field |
| Request data | 1 | Sensor Number (FFh = reserved) |
| Response data | 1 | Completion Code |
| 2 | Sensor Reading.[7:0] - Not used. Write as 00h. |
| 3 | Standard IPMI byte (See “Get Sensor Reading” in IPMI specification): [7] - 0b = All Event Messages disabled from this sensor [6] - 0b = sensor scanning disabled [5] - 1b = initial update in progress. This bit is set to indicate that a “Re-arm Sensor Events” or “Set Event Receiver” command has been used to request an update of the sensor status, and that update has not occurred yet. Software should use this bit to avoid getting an incorrect status while the first sensor update is in progress. This bit is only required if it is possible for the IPM Controller to receive and process a “Get Sensor Reading or Get Sensor Event Status” command for the sensor before the update has completed. This is most likely to be the case for sensors, such as fan RPM sensors, that may require seconds to accumulate the first reading after a re-arm.[4:0] – reserved. Ignore on read. |
| 4 | Current State Mask[7] – 1b = FRU Operational State M7 - Communication Lost [6] – 1b = FRU Operational State M6 - FRU Deactivation In Progress [5] – 1b = FRU Operational State M5 - FRU Deactivation Request [4] – 1b = FRU Operational State M4 - FRU Active [3] – 1b = FRU Operational State M3 - FRU Activation in Progress [2] – 1b = FRU Operational State M2 - FRU Activation Request [1] – 1b = FRU Operational State M1 - FRU Inactive [0] – 1b = FRU Operational State M0 - FRU Not Installed |
| 5 | [7:0] – Optional/Reserved. If provided, write as 80h (IPMI restriction). Ignore on read. |
Table 4-2: Get Sensor Reading (FRU Hotswap Sensor)
# 4.2.2 Get Sensor Reading (Physical IPMB-0 Sensor)
| Byte | Data field |
| Request data | 1 | Sensor Number (FFh = reserved) |
| Response data | 1 | Completion Code |
| 2 | Sensor Reading.[7:0] - Not used. Write as 00h. |
| 3 | Standard IPMI byte (See “Get Sensor Reading” in IPMI specification):[7] - 0b = All Event Messages disabled from this sensor[6] - 0b = sensor scanning disabled[5] - 1b = initial update in progress. This bit is set to indicate that a “Re-arm Sensor Events” or “Set Event Receiver” command has been used to request an update of the sensor status, and that update has not occurred yet. Software should use this bit to avoid getting an incorrect status while the first sensor update is in progress. This bit is only required if it is possible for the IPM Controller to receive and process a “Get Sensor Reading or Get Sensor Event Status” command for the sensor before the update has completed. This is most likely to be the case for sensors, such as fan RPM sensors, that may require seconds to accumulate the first reading after a re-arm.[4:0] – reserved. Ignore on read. |
| 4 | Current State Mask[7] – 1b = FRU Operational State M7 - Communication Lost[6] – 1b = FRU Operational State M6 - FRU Deactivation In Progress[5] – 1b = FRU Operational State M5 - FRU Deactivation Request[4] – 1b = FRU Operational State M4 - FRU Active[3] – 1b = FRU Operational State M3 - FRU Activation in Progress[2] – 1b = FRU Operational State M2 - FRU Activation Request[1] – 1b = FRU Operational State M1 - FRU Inactive[0] – 1b = FRU Operational State M0 - FRU Not Installed |
| 5 | [7:0] – Optional/Reserved. If provided, write as 80h (IPMI restriction). Ignore on read. |
Table 4-3: Get Sensor Reading (Physical IPMB-0 Sensor)
# 4.2.3 Watchdog Timer Sensor
| Sensor Type | Sensor Type Code | Sensor Specific Offset | Event |
| Version Change | 2Bh | 00h | 00h Hardware change detected with associated Entity. Informational. This offset does not imply whether the hardware change was successful or not. Only that a change occurred. |
| 01h | 01h Firmware or software change detected with associated Entity.Informational. Success or failure not implied. |
| 02h | 02h Hardware incompatibility detected with associated Entity. |
| 03h | 03h Firmware or software incompatibility detected with associated Entity. |
| 04h | 04h Entity is of an invalid or unsupported hardware version. |
| 05h | 05h Entity contains an invalid or unsupported firmware or software version. |
| 06h | 06h Hardware Change detected with associated Entity was successful.(deassertion event means ‘unsuccessful’). |
| 07h | 07h Software or F/W Change detected with associated Entity was successful.(deassertion event means ‘unsuccessful’) |
| Event data 2 can be used for additional event information on the type of version change - see definition below |
Table 4-5: Version Change Sensor
# Event Data 2
# 7:0 Version change type
▶ 00h unspecified
▶ 01h management controller device ID (change in one or more fields from ‘Get Device ID’)
▶ 02h management controller firmware revision
▶ 03h management controller device revision
▶ 04h management controller manufacturer ID
▶ 05h management controller IPMI version
▶ 06h management controller auxiliary firmware ID
▶ 07h management controller firmware boot block
▶ 08h other management controller firmware
▶ 09h system firmware (EFI / BIOS) change
▶ 0Ah SMBIOS change
▶ 0Bh operating system change
▶ 0Ch operating system loader change
▶ 0Dh service or diagnostic partition change
▶ 0Eh management software agent change
▶ 0Fh management software application change
▶ 10h management software middleware change
▶ 11h programmable hardware change (e.g. FPGA)
▶ 12h board/FRU module change (change of a module plugged into associated entity)
▶ 13h board/FRU component change (addition or removal of a replaceable component on the board/FRU that is not tracked as a FRU)
▶ 14h board/FRU replaced with equivalent version
▶ 15h board/FRU replaced with newer version
▶ 16h board/FRU replaced with older version
▶ 17h board/FRU hardware configuration change (e.g. strap, jumper, cable change, etc.)
# 4.2.5 Get Sensor Reading Command
| BIOS SETUP UTILITY
Advanced |
| Configure Win627UHG Super IO Chipset |
| UART1 to FRONT PANEL [Enabled]
UART2 to IPMC [Enabled]
UART3 to ZONE2 [Enabled]
UART4 to TELECOM [Enabled] | Allows USER to Select Serial Ports.
RESOURCE:
UART1 - 0x3F8,IRQ4
UART2 - 0x3E8,IRQ3
UART3 - 0x2F8,IRQ10
UART4 - 0x2E8,IRQ11 |
| ← Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit |
| v02.61 (C) Copyright 1985-2006, American Megatrends, Inc. |
# UART1 to FRONT PANEL, UART2 to IPMC, UART3 to ZONE2, UART4 to TELECOM
These items are for enabling/disabling the serial port to front panel, IPMC, ZONE2, and TELECOM. Detailed resources for these serial ports are listed in the help field of the setup screen.
# 8.3.4 Hardware Health Configuration
This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. The options are Enabled and Disabled.