# cExpress-AL User's Manual COM Express Compact Size Type 6 Module with Intel Atom®, Pentium®, Celeron® SoC ![ADLINK\nTECHNOLOGY INC.\nAMD-Aptio®\nDT 6 2006\nFY 50\n9.962\nOE164671-4M Z 000\n2:13 WLS4V-0\nADLINK\nTECHNOLOGY INC.\nS172814-0010\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH12\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH14\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH15\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16\nH16](.cexpress-al-50-1j068-1020-12/e0da08934ba33bd88f2529640153daf5e93f9221cad8bffd1e7434bece5bae53.jpg) ![COM\nExpress®](.cexpress-al-50-1j068-1020-12/f7005dbf94063c1d2665b390a07297e1cd8af863c893fc225a1d4f4e5d46efbf.jpg) Manual Rev.: 1.2 Revision Date: December 6, 2019 Part Number: 50-1J068-1020 # Preface # Copyright Copyright © 2017-2019 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.cexpress-al-50-1j068-1020-12/f7bc49dfe54942cfb0c4dbbcf1a14469eb7283c3a32198aafa06af4eb9d36f85.jpg) Battery Labels (for products with battery) ![Simple line drawing of a trash bin with crossed lines indicating no waste or prohibition (no text or symbols)](.cexpress-al-50-1j068-1020-12/b8132a65515387c6bde18b6146ae51c3903ecf21f7553dccb16942d2acc530f4.jpg) ![Li-ion](.cexpress-al-50-1j068-1020-12/ef28de648807fc19f77b9a37201287661580a03050f03f0d4ba1254824d669e6.jpg) ![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cexpress-al-50-1j068-1020-12/49076e2e6b2ce343d2e69712c8d65c5c7c318232a3804a1f6d8c83b15a2ba95f.jpg) ![廢電池請回收](.cexpress-al-50-1j068-1020-12/7aa5036e08ff9ab489c31a6bb8d59189ae4619969c85025a79133e1ea6781ccf.jpg) # California Proposition 65 Warning ![A yellow triangular warning sign with a thick black border featuring a black exclamation mark in the center.](.cexpress-al-50-1j068-1020-12/c52408742cf207d64b3a183f64b4df8185df51c60432e748d8699eb571a59221.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. Revision History
RevisionDescriptionDateBy
1.0Initial release2017-12-04JC
1.1Update specifications, PCIe port options, BIOS setup menu2018-04-23JC
1.2Update dual BIOS to “build option”; update Ethernet controller temperature support2019-12-06JC
# Table of Contents Preface....ii List of Figures ......vii List of Tables......viii 1. Introduction......1 2. Specifications ....3 2.1. Core System....3 2.2. Expansion Busses .... 3 2.3. Video....4 2.4. Audio....4 2.5. LAN 4 2.6. Multi I/O and Storage....4 2.7. Serial I/O....5 2.8. SEMA Board Controller 5 2.9. Debug 5 2.10. Trusted Platform Module (TPM) 5 2.11. Power Specifications 6 2.12. Operating Temperatures ...... 6 2.13. Environmental 6 2.14. Specification Compliance 6 2.15. Operating Systems....6 2.16. Functional Diagram 7 2.17. Mechanical Drawing 8 3. Pinouts and Signal Descriptions....9 3.1. AB/CD Pin Definitions....9 3.2. Signal Description Terminology....12 3.3. AB Signal Descriptions .... 13 3.3.1. Audio Signals 13 3.3.2. Analog VGA (build option) 13 3.3.3. LVDS/eDP 14 3.3.4. Gigabit Ethernet 15 3.3.5. SATA.... 15 3.3.6. PCI Express 16 3.3.7. LPC Bus 16 3.3.8. USB 17 3.3.9. USB Root Segmentation.... 18 3.3.10. SPI (BIOS only).... 19 3.3.11. Miscellaneous 19 3.3.12. SMBus.... 20 3.3.13. I2C Bus 20 3.3.14. General Purpose I/O (GPIO).... 20 3.3.15. Serial Interface Signals 21 3.3.16. Power And System Management 21 3.3.17. Power and Ground 22 # 3.4. CD Signal Descriptions....23 3.4.1. USB 3.0 extension 23 3.4.2. PCI Express x1 23 3.4.3. DDI Channels.... 24 3.4.4. DDI to DP/HDMI/SDVO Mapping.... 26 3.4.5. PCI Express Graphics x16 (not supported) 27 3.4.6. Module Type Definition 28 3.4.7. Power and Ground 28 # 4. Module Interfaces....31 4.1. Connector, Switch and LED Locations 31 4.2. 40-pin Debug Connector....32 4.3. Status LEDs....33 4.4. MIPI60 Debug Header (build option) 34 4.5. Fan Connector 35 4.6. BIOS Setup Defaults Reset Button....36 4.7. Switch Settings 37 # 5. Smart Embedded Management Agent (SEMA) 39 5.1. Board Specific SEMA Functions....40 5.1.1. Voltages 40 5.1.2. Main Current 40 5.1.3. BMC Status 40 5.1.4.Exception Codes 41 5.1.5. BMC Flags 41 # 6. System Resources ....43 6.1. System Memory Map....43 6.2. I/O Map 43 6.3. Interrupt Request (IRQ) Lines....45 6.4. PCI Configuration Space Map 47 6.5. PCI Interrupt Routing Map 49 6.6. SMBus Address Table....50 # 7. BIOS Setup....51 7.1. Menu Structure 51 7.2. Main....52 7.2.1. Main > BIOS Information 52 7.2.2. Main > System Information 52 7.2.3. Main > Board Information 52 7.2.4. Main >System Date/Time 53 7.2.5. Main >Access Level 53 7.3. Advanced....54 7.3.1. Advanced > CPU Configuration.... 54 7.3.2. Advanced > Graphics Configuration 56 7.3.3. Advanced > Power Management.... 57 7.3.4. Advanced > System Management.... 57 7.3.5. Advanced > Thermal Management.... 58 7.3.6. Advanced > Watchdog Timer 59 7.3.7. Advanced > CSM Configuration 59 7.3.8. Advanced > Super IO Configuration 59 7.3.9. Advanced > Serial Console Redirection 61 7.3.10. Advanced > USB....66 7.3.11. Advanced > Network....67 7.3.12. Advanced > Miscellaneous 67 7.3.13. Advanced > Driver Health 67 7.3.14. Advanced > Trusted Computing 67 7.3.15. Advanced > AMI Graphic Output Protocol Policy 68 7.3.16. Advanced > SDIO Configuration.... 68 7.4. Chipset....69 7.4.1. Chipset > North Bridge 69 7.4.2. Chipset > South Bridge 69 7.4.3. Chipset > Uncore Configuration.... 69 7.4.4. Chipset > South Cluster Configuration 71 7.5. Security Menu....80 7.5.1. Security > Password Description 80 7.6. Boot Menu 80 7.6.1. Boot > Boot Configuration....80 7.6.2. Boot > FIXED BOOT ORDER Priorities.... 80 7.7. Save & Exit Menu 81 7.7.1. Save and Exit 81 8.1. Status Code Ranges....84 8.2. Standard Status Codes....84 8.2.1. SEC Phase.... 84 8.2.2. SEC Beep Codes 85 8.2.3. PEI Phase 85 8.2.4. PEI Beep Codes 87 8.2.5. DXE Status Codes 88 8.2.6. DXE Beep Codes 90 8.2.7. ACPI/ASL Checkpoint 90 8.3. OEM-Reserved Checkpoint Ranges....91 # 9. Mechanical Information....93 9.1. Board-to-Board Connectors....93 9.2. Thermal Solution....94 9.2.1. Heat Spreaders.... 94 9.2.2. Heat Sinks.... 94 9.2.3. Installation 94 9.3. Mounting Methods 97 9.4. Standoff Types....98 # Safety Instructions....99 # Getting Service....100 # List of Figures Figure 1: cExpress-AL Functional Block Diagram....7 Figure 2: cExpress-AL Mechanical Drawing ....8 Figure 3: cExpress-AL Connector, Switch and LED Locations 31 Figure 4: cExpress-AL and the DB40 Debug Module 31 Figure 5: cExpress-AL Switch Locations.... 37 Figure 6: COM Express Mounting Methods....97 Figure 7: COM Express Standoff Types....98 # List of Tables Table 1: cExpress-AL AB/CD Pin Definitions....9 Table 2: 40-pin Debug Connector Pin Definition.... 32 Table 3: cExpress-AL LED Descriptions ...... 33 Table 4: MIPI60 Debug Header Pin Definition .... 34 Table 5: Fan Connector Pin Definition ...... 35 Table 6: BIOS Select and Mode Configuration Switch Settings.... 37 Table 7: SEMA Onboard Voltage Monitor 40 Table 8: SEMA BMC Status 40 Table 9: SEMA Exception Codes....41 Table 10: SEMA BMC Flags....41 # 1. Introduction The cExpress-AL is a COM Express COM.0 R3.0 Type 6 module supporting the Intel Atom® processor, Intel® Pentium® processor and Intel® Celeron® processor system-on-chip (SoC). The cExpress-AL is specifically designed for customers who need optimized processing and graphics performance with low power consumption in a long product life solution. The Intel Atom® processor, Intel® Pentium® processor and Intel® Celeron® processor and support non-ECC type DDR3L dual-channel memory at 1600/1867 MHz to provide excellent overall performance. Integrated Intel® Gen9 LP Graphics includes features such as OpenGL 4.3, DirectX 12, OpenCL 2.0; and support for H.265/HEVC, H.264, MPEG2, VC1, VP9, MVC, JPEG/MJPEG hardware decode. Up to three independent displays are available from DDI ports supporting HDMI/DVI/DisplayPort, optional VGA, single/dual-channel 18/24-bit LVDS and optional eDP. The cExpress-AL is specifically designed for customers with balanced performance/power consumption requirements who want to outsource the custom core logic of their systems for reduced development time. The cExpress-AL has dual stacked SODIMM sockets for up to 8 GB non-ECC type DDR3L memory. Featured IO include a single Gigabit Ethernet port (IEEE 1588 support), USB 3.0 ports and USB 2.0 ports, SATA 6 Gb/s ports, and up to 5 PCIe x1 lanes. In addition, SD signals are muxed with GPIO. Support is provided for SMBus and I²C. The module is equipped with SPI AMI EFI BIOS (dual BIOS by build option), supporting embedded features such as remote console, CMOS backup, hardware monitor, and watchdog timer. An optional eMMC 5.0 (8/16/32 GB) is supported. This page intentionally left blank. # 2. Specifications # 2.1. Core System
CPUDual or quad-core Intel Atom®, Pentium® or Celeron® Processor SoCAtomTM E3950 1.6/2.0GHz (Turbo), 400-650MHz (graphics), 12W (4C/1866)AtomTM E3940 1.6/1.8GHz (Turbo), 400-600MHz (graphics), 9W (4C/1866)AtomTM E3930 1.3/1.8GHz (Turbo), 400-550MHz (graphics), 6W (2C/1866)Pentium® N4200 1.1/2.5GHz (Turbo), 200-750MHz (graphics), 6W (4C/1866)Celeron® N3350 1.1/2.4GHz (Turbo), 200-650MHz (graphics), 6W (2C/1866)Supports: Dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x, Intel® VT-d, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture, Intel® Turbo Boost Technology 2.0, Intel AES-NI, Intel® TXT, PCLMULQDQ instruction DRNGNotes: Availability of features may vary between processor SKUs and operating systems.Only AtomTM SKUs can support extreme temperature operating range.Pentium®, Celeron® SKUs are supported by project basis.
Cache2MB for all SKUs
MemoryDual channel non-ECC 1600/1867 MHz DDR3L memory up to 8GB in dual stacked SODIMM sockets (lower slot must be populated)Notes: maximum by 2pcs 4GB or 1pcs 8GB SODIMM
BIOSAMI EFI with CMOS backup in 16MB SPI BIOS (dual BIOS by build option)
# 2.2. Expansion Busses
PCI Express3 PCIe x1 (AB) by default: ports 0/1/2 (direct from SoC)5 PCIe x1 (AB) are supported by build option with a PCIe bridge IC (ports 2/3/4 from PCIe bridge IC support x1 only, see 2.16 Functional Diagram below).
OtherLPC busSMBus (system) $I^{2}C$ (user)
# 2.3. Video
Integrated on ProcessorIntel® 9th generation LP graphics core architecture with up to 18 execution units supporting three independent displays
GPU Feature Support3D graphics hardware accelerationSupport for DirectX12/11.3/10/9.3, OCL 2.0, OGL ES 3.0, OGL 4.3Video decode hardware acceleration including support for H.265 (HEVC), H.264, MVC, MPEG-2, VC-1, WMV9, VP8/VP9, JPEG/MJPEG formatsVideo encode hardware acceleration including support for H.265 (HEVC), H.264, VP8/VP9, JPEG/MJPEG formatsSupports content protection using PAVP 2.0 and HDCP 1.4/2.0Note: Availability of features may vary between operating systems.
Display TypesDual/single channel 18/24-bit LVDS, supports DE mode and H/V-Sync mode displayeDP x4 lanes (eDP 1.3, by build option in place of LVDS)DDI1/2 support DisplayPort (DP 1.2), HDMI (1.4b), DVIVGA (via DP-to-VGA IC, by build option in place of DDI2)Note: Only two simultaneous HDMI/DVI outputs supported.
# 2.4. Audio
IntegratedIntel® HD Audio integrated on SoC
CodecLocated on carrier Express-BASE6 (ALC886 standard support)
# 2.5. LAN
MAC/PHYIntel® Ethernet Controller I210 (Extreme Rugged operating temperature range) Intel® Ethernet Controller I211 (standard operating temperature range)
Interface10/100/1000 Mbit/s connection, IEEE 1588 support
Note: Supports GBE0\_SDP on A49 pin. # 2.6. Multi I/O and Storage
USB3x USB 3.0/2.0/1.1 (USB 0/1/2)5x USB 2.0/1.1 (USB 3/4/5/6/7)Note: USB port 0 supports USB 2.0 OTG on Yocto Linux OS
SATA2x SATA 6Gb/s (SATA0, SATA1)
GPIO4 GPO and 4 GPINote: GPI with interrupt supported on Linux.
eMMC 5.0 (build option)8/16/32 GB (boot device support may vary between operating systems)*
SDSD 3.0 signal is muxed with GPIO, switching controlled by BIOS setting (boot device support may vary between operating systems)*Note: Supports 3.3V SD cards only.
Note: See table below for detailed boot device support information. Boot Device Support
Windows 10 EnterpriseLinux (Yocto)
Storage onlyeMMC 5.0YesYes
SDYesYes
OS InstallationeMMC 5.0YesYes
SDNoNo
Note: eMMC and SD functionality as an OS installation device may change dependent on Intel updates. Please contact your local sales representative for more information. # 2.7. Serial I/O \- Ports: 2x UART ports COM 1/2 (COM 1/2 supports console redirection), baud rate up to 115.2 kbps
PortDescriptionIRQAddressConsole Redirection Support
COM 1Supported by module (SER0, A98/A99), via NCT5104D100x240Yes
COM 2Supported by module (SER1, A101/A102), via NCT5104D110x248Yes
COM 3Supported by Super I/O (W83627DHG) on carrier board40x3F8Yes
COM 4Supported by Super I/O (W83627DHG) on carrier board30x2F8Yes
# 2.8. SEMA Board Controller ● Type: ADLINK Smart Embedded Management Agent (SEMA) - Functions: • Voltage/Current monitoring • Power sequence debug support • AT/ATX mode control • Logistics and forensic information - Flat panel control - General purpose I2C • Failsafe BIOS (dual BIOS by build option) • Watchdog timer and fan control # 2.9. Debug ● 40-pin flat cable connector to be used with DB-40 debug module Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs ● MIPI60 60-pin header for debug of SoC (build option) # 2.10. Trusted Platform Module (TPM) - Chipset: Infineon (build option) - Type: TPM 2.0 2.11. Power Specifications
Power ModesAT and ATX mode (AT mode startup controlled by SEMA Board Controller)
Standard Voltage InputATX: 12V ±5% / 5Vsb ±5% or AT = 12V ±5%
Wide Voltage InputATX: 4.75-20 V / 5Vsb ±5% or AT = 4.75-20 V
Power ManagementACPI 5.0 compliant, Smart Battery support
Power StatesSupports C0, C1, C1E, C6L, C6, S0, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)
ECO ModeSupports deep S5 for 5Vsb power saving
Please contact your ADLINK representative for the document "COM Express Module Power Consumption". 2.12. Operating Temperatures
Standard Operating Temperature0°C to +60°C (Wide Voltage Input)Storage: -20°C to +70°C
Extreme Rugged Operating Temperature (optional)-40°C to +85°C (Standard Voltage Input only, build option supported by AtomTM SKUs only)Storage: -40°C to +85°C
2.13. Environmental
HumidityOperating: 5-90% RH, non-condensingStorage: 5-95% RH (and operating with conformal coating)
Shock and VibrationIEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D
HALTThermal Stress, Vibration Stress, Thermal Shock and Combined Test
# 2.14. Specification Compliance \- PICMG COM.0: Rev. 3.0 Type 6, Compact size 95 x 95 mm 2.15. Operating Systems
Standard Support• Windows 10 Enterprise 64-bit• Linux 64-bit• VxWorks 64-bit
Extended Support (BSP)• Linux (64-bit)
2.16. Functional Diagram ![**Central Processor Block:**\n* 'Intel Atom®'\n* 'Intel® Pentium®'\n* 'Intel® Celeron®'\n* ''Apollo Lake''\n\n**Left Column (AB) Blocks & Connections:**\n* **LVDS:** 'single/dual channel 18/24-bit LVDS' connects to 'LVDS eDP to LVDS', which connects to 'eDP' on the central block. A dashed line labeled 'eDP x4 lanes (build option)' is nearby.\n* **VGA:** 'VGA DP to VGA (build option)' connects to the central block via dashed lines.\n* **USB:** '8x USB 2.0/1.0 (ports 0-7) (OTG on port 0, OS dependent)' connects bidirectionally to the central block.\n* **PCIe:**\n * 'PCIe x1 (port0)' connects bidirectionally.\n * Text '3 PCI x1 (0/1/2) default (other config. by request)' appears between port0 and port2.\n * 'PCIe x1 (port1)' connects bidirectionally.\n * 'PCIe x1 (port2)' connects bidirectionally.\n * 'PCIe Bridge (build option)' connects via dashed lines to ports 2, 3, and 4.\n * 'PCIe x1 (port3)' connects bidirectionally.\n * 'PCIe x1 (port4)' connects bidirectionally.\n* **GbE:** 'GBE0_SDP' connects to 'GbE', which connects bidirectionally to the central block.\n* **SATA:** '2x SATA 6Gb/s (port 0/1)' connects bidirectionally.\n* **Audio:** 'HD Audio' connects bidirectionally.\n* **LPC/UART:** 'UART0 UART1' connects to 'LPC to UART'. This block connects to the central block via the 'LPC bus'.\n* **TPM:** 'TPM 2.0 (build option)' connects via dashed lines to the 'LPC bus'.\n* **Bus/IO:**\n * 'SMBus' connects bidirectionally to the central block.\n * 'GPIO' connects to the 'LPC bus'.\n * Bottom labels include '4x GPI, 4x GPO (SD)', 'GP I2C', 'MUX', 'DDC I2C', 'SPI_CS#', and 'SPI'.\n\n**Right Column (CD) Blocks & Connections:**\n* **Memory:** Two blocks of 'SODIMM 1867/1600 MHz 2-8 GB DDR3L non-ECC' connect bidirectionally. Text below reads 'Note: max. capacity is 8GB (2x 4GB or 1x 8GB)'.\n* **Display:** 'DDI1 (4 lanes) DP/HDMI' and 'DDI2 (4 lanes) DP/HDMI' connect bidirectionally.\n* **USB:** '3x USB 3.0 upgrade (ports 0/1/2)' connects bidirectionally.\n* **MIPI/eMMC:** 'MIPI60 60-pin (build option)' and 'eMMC 5.0 8/16/32GB (build option)' connect bidirectionally via dashed lines.\n\n**Bottom Right Blocks & Connections:**\n* **SEMA BMC:** Connects to 'SD' and 'I2C' pins on the central block.\n* **BIOS/Temp:** 'SEMA BMC' connects to 'SPI 0 BIOS', 'SPI 1 BIOS' (via dashed lines), and 'LM73'.\n* **SPI Bus:** 'SPI 0 BIOS' and 'SPI 1 BIOS' are connected to the 'SPI' and 'SPI_CS#' lines.](.cexpress-al-50-1j068-1020-12/313990ac925e95b05ed66d1478e4809f53ceb6457b664ffa0274fd044036fb99.jpg) Figure 1: cExpress-AL Functional Block Diagram # 2.17. Mechanical Drawing ![95\n80\n74.2\n16.5\n40\n4\n0\n4\n6\n18\nconnector on bottom side\nTop View\n82.93\n91\nØ 6\nØ 2.7\n42\n88.9\n91\n95\n91\n88.34\n74.54\n42\n0\n95\n91\n95](.cexpress-al-50-1j068-1020-12/2abeaab015dbf1a396498b4ac5baeee92a1d3788356b3b1611e9d10a2766ea9a.jpg) ![Side View\n9.2\n5.2\n2\n3.25](.cexpress-al-50-1j068-1020-12/84594c702844405bc7b6f5180b62969ee9269bc48911482e3e7851e0dd03086e.jpg) All are dimensions shown in millimeters. Tolerances should be $\pm$ 0.25mm, unless otherwise noted. The tolerances of the module connector locating peg holes (16.50, 6.00] and [16.50, 18.00]) should be $\pm$ 0.10mm. Figure 2: cExpress-AL Mechanical Drawing # 3. Pinouts and Signal Descriptions # 3.1. AB/CD Pin Definitions The cExpress-AL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector. All pins in the COM Express specification are described, including those not supported on the cExpress-AL. Those not supported on the cExpress-AL module are crossed out. Table 1: cExpress-AL AB/CD Pin Definitions
Row ARow BRow CRow D
PinNamePinNamePinNamePinName
A1GND (FIXED)B1GND (FIXED)C1GND FIXED)D1GND FIXED)
A2GBE0_MDI3-B2GBE0_ACT#C2GNDD2GND
A3GBE0_MDI3+B3LPC_FRAME#C3USB_SSRX0-D3USB_SSTX0-
A4GBE0_LINK100#B4LPC_AD0C4USB_SSRX0+D4USB_SSTX0+
A5GBE0_LINK1000#B5LPC_AD1C5GNDD5GND
A6GBE0_MDI2-B6LPC_AD2C6USB_SSRX1-D6USB_SSTX1-
A7GBE0_MDI2+B7LPC_AD3C7USB_SSRX1+D7USB_SSTX1+
A8GBE0_LINK#B8LPC_DRQ0#C8GNDD8GND
A9GBE0_MDI1-B9LPC_DRQ1#C9USB_SSRX2-D9USB_SSTX2-
A10GBE0_MDI1+B10LPC_CLKC10USB_SSRX2+D10USB_SSTX2+
A11GND (fixed)B11GND (fixed)C11GND (fixed)D11GND (fixed)
A12GBE0_MDI0-B12PWRBTN#C12USB_SSRX3-D12USB_SSTX3-
A13GBE0_MDI0+B13SMB_CKC13USB_SSRX3+D13USB_SSTX3+
A14GBE0_CTREFB14SMB_DATC14GNDD14GND
A15SUS_S3#B15SMB_ALERT#C15DDI1_PAIR6+D15DDI1_CTRLCLK_AUX+
A16SATA0_TX+B16SATA1_TX+C16DDI1_PAIR6-D16DDI1_CTRLDATA_AUX
A17SATA0_TX-B17SATA1_TX-C17RSVDD17RSVD
A18SUS_S4#B18SUS_STAT#C18RSVDD18RSVD
A19SATA0_RX+B19SATA1_RX+C19PCIE_RX6+D19PCIE_TX6+
A20SATA0_RX-B20SATA1_RX-C20PCIE_RX6-D20PCIE_TX6-
A21GND (fixed)B21GND (fixed)C21GND (fixed)D21GND (fixed)
A22SATA2_TX+B22SATA3_TX+C22PCIE_RX7+D22PCIE_TX7+
A23SATA2_TX-B23SATA3_TX-C23PCIE_RX7-D23PCIE_TX7-
A24SUS_S5#B24PWR_OKC24DDI1_HPDD24RSVD
A25SATA2_RX+B25SATA3_RX+C25DDI1_PAIR4+D25RSVD
A26SATA2_RX-B26SATA3_RX-C26DDI1_PAIR4-D26DDI1_PAIR0+
A27BATLOW#B27WDTC27RSVDD27DDI1_PAIR0-
A28(S)ATA_ACT#B28HDA_SDIN2C28RSVDD28RSVD
A29HDA_SYNCB29HDA_SDIN1C29DDI1_PAIR5+D29DDI1_PAIR1+
A30HDA_RST#B30HDA_SDINOC30DDI1_PAIR5-D30DDI1_PAIR1-
A31GND (fixed)B31GND (fixed)C31GND (fixed)D31GND (fixed)
A32HDA_BITCLKB32SPKRC32DDI2_CTRLCLK_AUX+D32DDI1_PAIR2+
A33HDA_SDOUTB33I2C_CKC33DDI2_CTRLDATA_AUX-D33DDI1_PAIR2-
A34BIOS_DISO#B34I2C_DATC34DDI2_DDC_AUX_SELD34DDI1_DDC_AUX_SEL
A35THRMTRIP#B35THRM#C35RSVDD35RSVD
Row A Row B Row C Row D
PinNamePinNamePinNamePinName
A36USB6-B36USB7-C36DDI3_CTRLCLK_AUX+D36DDI1_PAIR3+
A37USB6+B37USB7+C37DDI3_CTRLDATA_AUXD37DDI1_PAIR3-
A38USB_6_7_OC#B38USB_4_5_OC#C38DDI3_DDC_AUX_SELD38RSVD
A39USB4-B39USB5-C39DDI3_PAIR0+D39DDI2_PAIR0+
A40USB4+B40USB5+C40DDI3_PAIR0-D40DDI2_PAIR0-
A41GND (fixed)B41GND (fixed)C41GND (fixed)D41GND (fixed)
A42USB2-B42USB3-C42DDI3_PAIR1+D42DDI2_PAIR1+
A43USB2+B43USB3+C43DDI3_PAIR1-D43DDI2_PAIR1-
A44USB_2_3_OC#B44USB_0_1_OC#C44DDI3_HPDD44DDI2_HPD
A45USBO-B45USB1-C45RSVDD45RSVD
A46USBO+B46USB1+C46DDI3_PAIR2+D46DDI2_PAIR2+
A47VCC_RTCB47ESPI_EN#C47DDI3_PAIR2-D47DDI2_PAIR2-
A48RSVDB48USBO_HOST_PRSNTC48RSVDD48RSVD
A49GBEO_SDPB49SYS_RESET#C49DDI3_PAIR3+D49DDI2_PAIR3+
A50LPC_SERIRQB50CB_RESET#C50DDI3_PAIR3-D50DDI2_PAIR3-
A51GND (fixed)B51GND (fixed)C51GND (fixed)D51GND (fixed)
A52PCIE_TX5+B52PCIE_RX5+C52PEG_RX0+D52PEG_TX0+
A53PCIE_TX5-B53PCIE_RX5-C53PEG_RX0-D53PEG_TX0-
A54GPIOB54GPO1C54TYPE0#D54PEG_LANE_RV#
A55PCIE_TX4+ *B55PCIE_RX4+ *C55PEG_RX1+D55PEG_TX1+
A56PCIE_TX4 - *B56PCIE_RX4 - *C56PEG_RX1-D56PEG_TX1-
A57GNDB57GPO2C57TYPE1#D57TYPE2#
A58PCIE_TX3+ *B58PCIE_RX3+ *C58PEG_RX2+D58PEG_TX2+
A59PCIE_TX3 - *B59PCIE_RX3 - *C59PEG_RX2-D59PEG_TX2-
A60GND (fixed)B60GND (fixed)C60GND (fixed)D60GND (fixed)
A61PCIE_TX2+B61PCIE_RX2+C61PEG_RX3+D61PEG_TX3+
A62PCIE_TX2-B62PCIE_RX2-C62PEG_RX3-D62PEG_TX3-
A63GPI1B63GPO3C63RSVDD63RSVD
A64PCIE_TX1+B64PCIE_RX1+C64RSVDD64RSVD
A65PCIE_TX1-B65PCIE_RX1-C65PEG_RX4+D65PEG_TX4+
A66GNDB66WAKEO#C66PEG_RX4-D66PEG_TX4-
A67GPI2B67WAKE1#C67RAPID_SHUTDOWND67GND
A68PCIE_TX0+B68PCIE_RX0+C68PEG_RX5+D68PEG_TX5+
A69PCIE_TX0-B69PCIE_RX0-C69PEG_RX5-D69PEG_TX5-
A70GND (fixed)B70GND (fixed)C70GND (fixed)D70GND (fixed)
A71LVDS_A0+B71LVDS_B0+C71PEG_RX6+D71PEG_TX6+
A72LVDS_A0-B72LVDS_B0-C72PEG_RX6-D72PEG_TX6-
A73LVDS_A1+B73LVDS_B1+C73GNDD73GND
A74LVDS_A1-B74LVDS_B1-C74PEG_RX7+D74PEG_TX7+
A75LVDS_A2+B75LVDS_B2+C75PEG_RX7-D75PEG_TX7-
A76LVDS_A2-B76LVDS_B2-C76GNDD76GND
A77LVDS_VDD_ENB77LVDS_B3+C77RSVDD77RSVD
A78LVDS_A3+B78LVDS_B3-C78PEG_RX8+D78PEG_TX8+
A79LVDS_A3-B79LVDS_BKLT_ENC79PEG_RX8-D79PEG_TX8-
Row ARow BRow CRow D
PinNamePinNamePinNamePinName
A80GND (FIXED)B80GND (FIXED)C80GND (FIXED)D80GND (FIXED)
A81LVDS_A_CK+B81LVDS_B_CK+C81PEG_RX9+D81PEG_TX9+
A82LVDS_A_CK-B82LVDS_B_CK-C82PEG_RX9-D82PEG_TX9-
A83LVDS_I2C_CKB83LVDS_BKLT_CTRLC83RSVDD83RSVD
A84LVDS_I2C_DATB84VCC_5V_SBYC84GNDD84GND
A85GPI3B85VCC_5V_SBYC85PEG_RX10+D85PEG_TX10+
A86RSVDB86VCC_5V_SBYC86PEG_RX10-D86PEG_TX10-
A87eDP_HPDB87VCC_5V_SBYC87GNDD87GND
A88PCIEO_CK_REF+B88BIOS_DIS1#C88PEG_RX11+D88PEG_TX11+
A89PCIEO_CK_REF-B89VGA_RED*C89PEG_RX11-D89PEG_TX11-
A90GND (fixed)B90GND (fixed)C90GND (fixed)D90GND (fixed)
A91SPI_POWERB91VGA_GRN*C91PEG_RX12+D91PEG_TX12+
A92SPI_MISOB92VGA_BLU*C92PEG_RX12-D92PEG_TX12-
A93GPOOB93VGA_HSYNC*C93GNDD93GND
A94SPI_CLKB94VGA_VSYNC*C94PEG_RX13+D94PEG_TX13+
A95SPI_MOSIB95VGA_I2C_CK*C95PEG_RX13-D95PEG_TX13-
A96TPM_PPB96VGA_I2C_DAT*C96GNDD96GND
A97TYPE10#B97SPI_CS#C97RSVDD97RSVD
A98SERO_TXB98RSVDC98PEG_RX14+D98PEG_TX14+
A99SERO_RXB99RSVDC99PEG_RX14-D99PEG_TX14-
A100GND (fixed)B100GND (fixed)C100GND (fixed)D100GND (fixed)
A101SER1_TXB101FAN_PWMOUTC101PEG_RX15+D101PEG_TX15+
A102SER1_RXB102FAN_TACHINC102PEG_RX15-D102PEG_TX15-
A103LID#B103SLEEP#C103GNDD103GND
A104VCC_12VB104VCC_12VC104VCC_12VD104VCC_12V
A105VCC_12VB105VCC_12VC105VCC_12VD105VCC_12V
A106VCC_12VB106VCC_12VC106VCC_12VD106VCC_12V
A107VCC_12VB107VCC_12VC107VCC_12VD107VCC_12V
A108VCC_12VB108VCC_12VC108VCC_12VD108VCC_12V
A109VCC_12VB109VCC_12VC109VCC_12VD109VCC_12V
A110GND (FIXED)B110GND (FIXED)C110GND (FIXED)D110GND (FIXED)
# Notes: - LID# and SLEEP# signals are not natively supported on the SoC. They instead connect to GPIO pins simulating their behaviour. • \*VGA is by build option, in place of DDI2 • eDP x4 lanes is by build option, in place of LVDS - SD signal is muxed with GPIO, switching controlled by BIOS setting (see section 3.3.14) - PCIe bridge IC is by build option to support 5 PCIe x1 # 3.2. Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. I Input to the Module O Output from the Module I/O Bi-directional input/output signal OD Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant O 3.3V Output 3.3V signal level O 5V Output 5V signal level I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I/O 3.3Vsb Input 3.3V tolerant active in standby state P Power Input/Output REF Reference voltage output that may be sourced from a module power plane. PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected. The signal is used to indicate the PICMG module type to the Carrier Board. PU ADLINK implemented pull-up resistor on module PD ADLINK implemented pull-down resistor on module # 3.3. AB Signal Descriptions # 3.3.1. Audio Signals
SignalPinDescriptionI/OPU/PDComment
HDA_RST#A30Reset output to CODEC, active low.O 3.3V
HDA_SYNCA29Sample-synchronization signal to the CODEC(s).O 3.3V
HDA_BITCLKA32Serial data clock generated by the external CODEC(s).I/O 3.3V
HDA_SDOUTA33Serial TDM data output to the CODEC.O 3.3V
HDA_SDIN[2:0]B28B30Serial TDM data inputs from up to 3 CODECs.I/O 3.3VPD 680 ohmOnly supports HDA_SDIN0.PD 680 ohm, based on SoC vendor guidance.
# 3.3.2. Analog VGA (build option)
SignalPinDescriptionI/OPU/PDComment
VGA_REDB89Red for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.O AnalogPD 150RVGA is by build option, in place of DDI 2
VGA_GRNB91Green for monitorAnalog DAC output, designed to drive a 37.5-Ohm equivalent load.O AnalogPD 150R
VGA_BLUB92Blue for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.O AnalogPD 150R
VGA_HSYNCB93Horizontal sync output to VGA monitorO 3.3V
VGA_VSYNCB94Vertical sync output to VGA monitorO 3.3V
VGA_I2C_CKB95DDC clock line (I2C port dedicated to identify VGA monitor capabilities)I/O OD 3.3VPU 2k23.3V
VGA_I2C_DATB96DDC data line.I/O OD 3.3VPU 2k23.3V
# 3.3.3. LVDS/eDP LVDS
SignalPinDescriptionI/OPU/PDComment
LVDS_A0+A71LVDS Channel A differential pairsO LVDSLVDS is default. (through eDP to LVDS bridge)Note: eDP support available by build option
LVDS_A0-A72
LVDS_A1+A73
LVDS_A1-A74
LVDS_A2+A75
LVDS_A2-A76
LVDS_A3+A78
LVDS_A3-A79
LVDS_A_CK+A81LVDS Channel A differential clockO LVDS
LVDS_A_CK-A82
LVDS_B0+B71LVDS Channel B differential pairsO LVDS
LVDS_B0-B72
LVDS_B1+B73
LVDS_B1-B74
LVDS_B2+B75
LVDS_B2-B76
LVDS_B3+B77
LVDS_B3-B78
LVDS_B_CK+B81LVDS Channel B differential clockO LVDS
LVDS_B_CK-B82
LVDS_VDD_ENA77LVDS panel power enableO 3.3VPD 10k
LVDS_BKLT_ENB79LVDS panel backlight enableO 3.3V
LVDS_BKLT_CTRLB83LVDS panel backlight brightness controlO 3.3VPD 100kePD to LVDS requirement
LVDS_I2C_CKA83DDC lines used for flat panel detection and control.O 3.3VPU 2k2 3.3V
LVDS_I2C_DATA84DDC lines used for flat panel detection and control.I/O 3.3VPU 2k2 3.3V
eDP (build option)
SignalPinDescriptionI/OPU/PDComment
eDP_TX2+A71eDP differential pairsO PCIEAC coupled off module
eDP_TX2-A72
eDP_TX1+A73
eDP_TX1-A74
eDP_TX0+A75
eDP_TX0--A76
eDP_TX3+A81eDP differential pairsO PCIEAC coupled off module
eDP_TX3--A82
eDP_VDD_ENA77eDP power enableO 3.3VPD 10k
eDP_BKLT_ENB79eDP backlight enableO 3.3V
eDP_BKLT_CTRLB83eDP backlight brightness controlO 3.3VPD 100k
eDP_AUX+A83eDP AUX+I/O PCIEAC coupled off module
eDP_AUX-A84eDP AUX-I/O PCIEAC coupled off module
eDP_HPDA87Detection of Hot Plug / Unplug and notification of the link layerI 3.3VPD 100k
3.3.4. Gigabit Ethernet
Gigabit EthernetPinDescriptionI/OPU/PDComment
GBE0_MDI0+GBE0_MDI0-GBE0_MDI1+GBE0_MDI1-GBE0_MDI2+GBE0_MDI2-GBE0_MDI3+GBE0_MDI3-A13A11A10A9A7A6A3A2Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following: $\underline{\underline{1000}}$ $\underline{\underline{100}}$ $\underline{\underline{10}}$ $\underline{\underline{MDI[0]+/-}}$ $\underline{\underline{B1_DA+/-}}$ $\underline{\underline{TX+/-}}$ $\underline{\underline{TX+/-}}$ $\underline{\underline{MDI[1]+/-}}$ $\underline{\underline{B1_DB+/-}}$ $\underline{\underline{RX+/-}}$ $\underline{\underline{RX+/-}}$ $\underline{\underline{MDI[2]+/-}}$ $\underline{\underline{B1_DC+/-}}$ $\underline{\underline{MDI[3]+/-}}$ $\underline{\underline{B1_DD+/-}}$ I/OAnalogTwisted pair signals for external transformer.
GBE0_ACT#B2Gigabit Ethernet Controller 0 activity indicator, active low.O 3.3VSB
GBE0_LINK#A8Gigabit Ethernet Controller 0 link indicator, active low.O 3.3VSB
GBE0_LINK100#A4Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.O 3.3VSB
GBE0_LINK1000#A5Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.O 3.3VSB
GBE0_CTREFA14Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.GND min3.3V maxNot supported (NC pin)
GBE0_SDPA49Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as a 1pps signal.
3.3.5. SATA
SignalPinDescriptionI/OPU/PDComment
SATA0_TX+SATA0_TX-A16A17Serial ATA channel 0, Transmit Output differential pair.O SATAAC coupled on Module
SATA0_RX+SATA0_RX-A19A20Serial ATA channel 0, Receive Input differential pair.I SATAAC coupled on Module
SATA1_TX+SATA1_TX-B16B17Serial ATA channel 1, Transmit Output differential pair.O SATAAC coupled on Module
SATA1_RX+SATA1_RX-B19B20Serial ATA channel 1, Receive Input differential pair.I SATAAC coupled on Module
SATA2_TX+SATA2_TX-A22A23Serial ATA channel 2, Transmit Output differential pair.O SATANot supported
SATA2_RX+SATA2_RX-A25A26Serial ATA channel 2, Receive Input differential pair.I SATANot supported
SATA3_TX+SATA3_TX-B22B23Serial ATA channel 3, Transmit Output differential pair.O SATANot supported
SATA3_RX+SATA3_RX-B25B26Serial ATA channel 3, Receive Input differential pair.I SATANot supported
(S)ATA_ACT#A28ATA (parallel and serial) or SAS activity indicator, active low.O 3.3VPU 10k 3.3V
# 3.3.6. PCI Express
SignalPinDescriptionI/OPU/PDComment
PCIE_TX0+PCIE_TX0-A68A69PCI Express channel 0, Transmit Output differential pair.OPCIEAC coupled on module
PCIE_RX0+PCIE_RX0-B68B69PCI Express channel 0, Receive Input differential pair.IPCIEAC coupled off module
PCIE_TX1+PCIE_TX1-A64A65PCI Express channel 1, Transmit Output differential pair.OPCIEAC coupled on module
PCIE_RX1+PCIE_RX1-B64B65PCI Express channel 1, Receive Input differential pair.IPCIEAC coupled off module
PCIE_TX2+PCIE_TX2-A61A62PCI Express channel 2, Transmit Output differential pair.OPCIEAC coupled on module
PCIE_RX2+PCIE_RX2-B61B62PCI Express channel 2, Receive Input differential pair.IPCIEAC coupled off module
PCIE_TX3+PCIE_TX3-A58A59PCI Express channel 3, Transmit Output differential pair.OPCIEAC coupled on module, PCIe port 3 is by build option
PCIE_RX3+PCIE_RX3-B58B59PCI Express channel 3, Receive Input differential pair.IPCIEAC coupled on module, PCIe port 3 is by build option
PCIE_TX4+PCIE_TX4-A55A56PCI Express channel 4, Transmit Output differential pair.OPCIEAC coupled on module. PCIe port 4 is by build option, by PCIe bridge IC
PCIE_RX4+PCIE_RX4-B55B56PCI Express channel 4, Receive Input differential pair.IPCIEAC coupled off module. PCIe port 4 is by build option, by PCIe bridge IC
PCIE_TX5+PCIE_TX5-A52A53PCI Express channel 5, Transmit Output differential pair.OPCIEAC coupled on module. PCIe port 5 is by build option, in place of GbE
PCIE_RX5+PCIE_RX5-B52B53PCI Express channel 5, Receive Input differential pair.IPCIEAC coupled off module. PCIe port 5 is by build option, in place of GbE
PCIE_CLK_REF+PCIE_CLK_REF-A88A89PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.OPCIE
Note: PCIe bridge IC is by build option to support 5 PCIe x1. # 3.3.7. LPC Bus
SignalPinDescriptionI/OPU/PDComment
LPC_AD[0:3]B4-B7LPC multiplexed address, command and data busI/O 3.3V
LPC_FRAME#B3LPC frame indicates the start of an LPC cycleO 3.3V
LPC_DRQ0#LPC_DRQ1#B8B9LPC serial DMA requestI 3.3VNC.Not supported by Apollo Lake
LPC_SERIRQA50LPC serial interruptI/O 3.3VPU 8k23.3V
LPC_CLKB10LPC clock output -33MHz nominalO 3.3VThe LPC_CLK frequency is 25MHz
3.3.8. USB
SignalPinDescriptionI/OPU/PDComment
USB0+USB0-A46A45USB differential data pairs for Port 0I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB1+USB1-B46B45USB differential data pairs for Port 1I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB2+USB2-A43A42USB differential data pairs for Port 1I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB3+USB3-B43B42USB differential data pairs for Port 2I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB4+USB4-A40A39USB differential data pairs for Port 3I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB5+USB5-B40B39USB differential data pairs for Port 4I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB6+USB6-A37A36USB differential data pairs for Port 5I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB7+USB7-B37B37USB differential data pairs for Port 6I/O 3.3VSBUSB 1.1/ 2.0 compliant
USB_0_1_OC#B44USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.I 3.3VSBPU 10k3.3VSBDo not pull high on carrier
USB_2_3_OC#A44USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .I 3.3VSBPU 10k3.3VSBDo not pull high on carrier
USB_4_5_OC#B38USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.I 3.3VSBPU 10k3.3VSBDo not pull high on carrier
USB_6_7_OC#A38USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.I 3.3VSBPU 10k3.3VSBDo not pull high on carrier
USB0_HOST_PRSNTB48Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.I/O 3.3VSBPD 100kOTG support depends on OS
# 3.3.9. USB Root Segmentation ![**Blocks:**\n\n**SoC (Left Section):**\n* **xHCI Engine:** Contains 14 blocks alternating between 'USB 2.0' (white) and 'USB 3.0' (yellow).\n* **PHY:** Contains 14 blocks corresponding to the xHCI Engine.\n * Rows 1, 2, 3, 5, 7, 9, 11, 13: 'USB 2.0 PHY'.\n * Rows 4, 6, 8, 10: 'USB 3.0 PHY' (yellow) marked with an 'X'.\n * Rows 12, 14: 'USB 3.0 PHY' (yellow).\n\n**Middle Column:**\n* 'USB 2.0 Port 7'\n* 'USB 2.0 Port 6'\n* 'USB 2.0 Port 5'\n* 'USB 2.0 Port 4'\n* 'USB 2.0 Port 3'\n* 'USB 2.0 Port 2'\n* 'USB 3.0/2 Port 1'\n* 'USB 3.0/2 Port 0 (Host/Device Mode)'\n\n**Right Section (Blue Background):**\n* **ROW CD (Top):** Contains 'USB 3.0 Upgrade Port 3', 'USB 3.0 Upgrade Port 2', 'USB 3.0 Upgrade Port 1', and 'USB 3.0 Upgrade Port 0'.\n* **ROW AB (Bottom):** Contains 'USB 2.0 Port 7', 'USB 2.0 Port 6', 'USB 2.0 Port 5', 'USB 2.0 Port 4', 'USB 2.0 Port 3', 'USB 2.0 Port 2', 'USB 2.0 Port 1', and 'USB 2.0 Port 0 (Host/Device)'.\n\n**Connections:**\n\n**Within SoC:**\n* Blocks in the **xHCI Engine** column connect horizontally to their corresponding blocks in the **PHY** column.\n\n**From PHY to Middle Column & ROW CD:**\n* The top three **'USB 2.0 PHY'** blocks connect to **'USB 2.0 Port 7'**, **'USB 2.0 Port 6'**, and **'USB 2.0 Port 5'** respectively. Each of these PHYs also has a connection extending upwards to **'USB 3.0 Upgrade Port 3'**, **'USB 3.0 Upgrade Port 2'**, and **'USB 3.0 Upgrade Port 1'** respectively.\n* The fifth, seventh, and ninth **'USB 2.0 PHY'** blocks connect to **'USB 2.0 Port 4'**, **'USB 2.0 Port 3'**, and **'USB 2.0 Port 2'** respectively.\n* The eleventh **'USB 2.0 PHY'** and the twelfth **'USB 3.0 PHY'** connect to **'USB 3.0/2 Port 1'**.\n* The thirteenth **'USB 2.0 PHY'** and the fourteenth **'USB 3.0 PHY'** connect to **'USB 3.0/2 Port 0 (Host/Device Mode)'**. The fourteenth **'USB 3.0 PHY'** also connects to **'USB 3.0 Upgrade Port 0'**.\n* The **'USB 3.0 PHY'** blocks marked with an 'X' (rows 4, 6, 8, 10) have no outgoing connections.\n\n**From Middle Column to ROW AB:**\n* **'USB 2.0 Port 7'**, **'USB 2.0 Port 6'**, **'USB 2.0 Port 5'**, **'USB 2.0 Port 4'**, **'USB 2.0 Port 3'**, and **'USB 2.0 Port 2'** connect horizontally to their corresponding numbered ports in **ROW AB**.\n* **'USB 3.0/2 Port 1'** connects to **'USB 2.0 Port 1'**.\n* **'USB 3.0/2 Port 0 (Host/Device Mode)'** connects to **'USB 2.0 Port 0 (Host/Device)'**.](.cexpress-al-50-1j068-1020-12/5889ccae4d2c7617d57df1e5b2dfe1955ae9508a429eaad2f48fc9ea41ed4c43.jpg) 3.3.10. SPI (BIOS only)
SignalPinDescriptionI/OPU/PDComment
SPI_CS#B97Chip select for Carrier Board SPI BIOS Flash.O 3.3VSBPU 10k3.3VSBOnly supports CS0
SPI_MISOA92Data in to module from carrier board SPI BIOS flash.I 3.3VSB
SPI_MOSIA95Data out from module to carrier board SPI BIOS flash.O 3.3VSB
SPI_CLKA94Clock from module to carrier board SPI BIOS flash.O 3.3VSB
SPI_POWERA91Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER.SPI_POWER shall only be used to power SPI devices on the CarrierOP3.3VSB
BIOS_DIS0#A34Selection strap to determine the BIOS boot device.IPU 10k3.3VSBCarrier shall pull to GND or leave not-connected.
BIOS_DIS1#B88Selection strap to determine the BIOS boot device.IPU 10k3.3VSBCarrier shall pull to GND or leave not-connected
3.3.11. Miscellaneous
SignalPinDescriptionI/OPU/PDComment
SPKRB32Output for audio enunciator, the “speaker” in PC-AT systemsO 3.3VPU 10k 3.3V
WDTB27Output indicating that a watchdog time-out event has occurred.O 3.3V
THRM#B35Input from off-module temp sensor indicating an over-temp situation.I 3.3VRecommend to add PU on carrier board
THRMTRIP#A35Active low output indicating that the CPU has entered thermal shutdown.O 3.3V
FAN_PWMOUTB101Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.O OD 3.3VPU 2.2k 3.3VThere shall be PD on carrier board
FAN_TACHINB102Fan tachometer input for a fan with a two pulse output.I OD 3.3VPU 10k 3.3V
TPM_PPA96Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.I 3.3VPD only when TPM on module
RAPID_SHUTDOWNC67Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source impedance for ≥ 20 μs.I 5.0VSBNot supported
3.3.12. SMBus
SignalPinDescriptionI/OPU/PDComment
SMB_CKB13System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.I/O OD3.3VSBPU 8k23.3VSB
SMB_DAT#B14System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.I/O OD3.3VSBPU 8k23.3VSB
SMB_ALERT#B15System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.I 3.3VSBPU 10k3.3VSB
3.3.13. I2C Bus
SignalPinDescriptionI/OPU/PDComment
I2C_CKB33General purpose I2C port clock output/inputI/O OD 3.3VSBPU 2k2 3.3VSBSource SEMA BMC or Braswell SoC as alternative. (BMC by default)
I2C_DATB34General purpose I2C port data I/O lineI/O OD 3.3VSBPU 2k2 3.3VSBSource SEMA BMC or Braswell SoC as alternative. (BMC by default)
3.3.14. General Purpose I/O (GPIO)
SignalPinDescriptionI/OPU/PDComment
GPO[0]A93General purpose output pins.O 3.3VPD 10kAfter hardware RESET output low
GPO[1]B54General purpose output pins.O 3.3VPD 10kAfter hardware RESET output low
GPO[2]B57General purpose output pins.O 3.3VPD 10kAfter hardware RESET output low
GPO[3]B63General purpose output pins.O 3.3VPD 10kAfter hardware RESET output low
GPI[0]A54General purpose input pins. Pulled high internally on the module.I 3.3VPU 10k 3.3V
GPI[1]A63General purpose input pins. Pulled high internally on the module.I 3.3VPU 10k 3.3V
GPI[2]A67General purpose input pins. Pulled high internally on the module.I 3.3VPU 10k 3.3V
GPI[3]A85General purpose input pins. Pulled high internally on the module.I 3.3VPU 10k 3.3V
Notes: GPO[0:3], PU 10k 3.3V is by build option for programming these pins to be GPI. GPI[0:3], PD 10k is by build option for programming these pins to be GPO. cExpress-AL supports an SD/GPIO muxed design, controlled by BIOS setting. See the table below for pin mapping. SD/GPIO Pin Mapping
GPIO SignalSD SignalNote
GPI0SD_DATA0Bidirectional signal
GPI1SD_DATA1Bidirectional signal
GPI2SD_DATA2Bidirectional signal
GPI3SD_DATA3Bidirectional signal
GPO0SD_CLKOutput from COM Express, input to SD
GPO1SD_CMDOutput from COM Express, input to SD
GPO2SD_WPInput to COM Express when used as SD_WP
GPO3SD_CD#Input to COM Express when used as SD_CD#
3.3.15. Serial Interface Signals
SignalPinDescriptionI/OPU/PDComment
SER0_TXA98General purpose serial port transmitter (TTL level output)O CMOSPU 1k 5VPower rail tolerance 5V/12VThere shall be PD on carrier board
SER0_RXA99General purpose serial port receiver (TTL level input)I CMOSPU 4.7k 5VPower rail tolerance 5V/12V
SER1_TXA101General purpose serial port transmitter (TTL level output)O CMOSPU 1k 5VPower rail tolerance 5V/12VThere shall be PD on carrier board
SER1_RXA102General purpose serial port receiver (TTL level input)I CMOSPU 4.7k 5VPower rail tolerance 5V/12V
\*Note: PU 47K 3.3VSB supported by project basis, Please contact your local representataive. 3.3.16. Power And System Management
SignalPinDescriptionI/OPU/PDComment
PWRBTN#B12Power button to bring system out of S5 (soft off), active on falling edge.I 3.3VSBPU 10k 3.3VSB
SYS_RESET#B49Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.I 3.3VSBPU 10k 3.3VSB
CB_RESET#B50Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.O 3.3VSB
PWR_OKB24Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.I 3.3VPU 10k 3.3V
SUS_STAT#B18Indicates imminent suspend operation; used to notify LPC devices.O 3.3VSB
SUS_S3#A15Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.O 3.3VSB
SUS_S4#A18Indicates system is in Suspend to Disk state. Active low output.O 3.3VSB
SUS_S5#A24Indicates system is in Soft Off state.O 3.3VSBNot supported. connected to SUS_S4#
WAKE0#B66PCI Express wake up signal.I 3.3VSBPU 10k 3.3VSB
WAKE1#B67General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.I 3.3VSBNot supported. Connected to WAKE0#
BATLOW#A27Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.I 3.3VSBPU 10k 3.3VSB
LID#A103LID button. Low active signal used by the ACPI operating system for a LID switch.I OD 3.3VSBPU 10k 3.3VSB*Emulated on GPIO (BIOS)
SLEEP#B103Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.I OD 3.3VSBPU 10k 3.3VSB*Emulated on GPIO (BIOS)
3.3.17. Power and Ground
SignalPinDescriptionI/OPU/PDComment
VCC_12VA104-A109B104-B109Primary power input: +12V nominal (wide range 5 ~ 20V). All available VCC_12V pins on the connector(s) shall be used.P4.75-20 V
VCC_5V_S BYB84-B87Standby power input: +5.0V nominal. See Section 7 “Electrical Specifications” for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.P5Vsb ±5%
VCC_RTCA47Real-time clock circuit-power input. Nominally +3.0V.P
GNDA1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21,B31, B41, B51, B60, B70, B80, B90, B100, B110Ground - DC power and signal and AC signal return path.P
# 3.4. CD Signal Descriptions # 3.4.1. USB 3.0 extension
SignalPinDescriptionI/OPU/PDComment
USB_SSRX0-USB_SSRX0+C3C4Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0I PCIEAC coupled off Module
USB_SSTX0-USB_SSTX0+D3D4Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0O PCIEAC coupled on Module
USB_SSRX1-USB_SSRX1+C6C7Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1I PCIEAC coupled off Module
USB_SSTX1-USB_SSTX1+D6D7Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1O PCIEAC coupled on Module
USB_SSRX2-USB_SSRX2+C9C10Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2I PCIEAC coupled off Module
USB_SSTX2-USB_SSTX2+D9D10Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2O PCIEAC coupled on Module
USB_SSRX3-USB_SSRX3+C12C13Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3I PCIENot supported
USB_SSTX3-USB_SSTX3+D12D13Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3O PCIENot supported
# 3.4.2. PCI Express x1
SignalPin #DescriptionI/OPU/PDComment
PCIE_TX6+PCIE_TX6-D19D20PCI Express channel 6, Transmit Output differential pair.OPCIENot supported
PCIE_RX6+PCIE_RX6-C19C20PCI Express channel 6, Receive Input differential pair.IPCIENot supported
PCIE_TX7+PCIE_TX7-D22D23PCI Express channel 7, Transmit Output differential pair.OPCIENot supported
PCIE_RX7+PCIE_RX7-C22C23PCI Express channel 7, Receive Input differential pair.IPCIENot supported
# 3.4.3. DDI Channels DDI 1
SignalPinDescriptionI/OPU/PDComment
DDI1_PAIR0+D26Digital Display Interface1 differential pairsO PCIEPair 4 to Pair 6 are NOT supported
DDI1_PAIR0-D27
DDI1_PAIR1+D29
DDI1_PAIR1-D30
DDI1_PAIR2+D32
DDI1_PAIR2-D33
DDI1_PAIR3+D36
DDI1_PAIR3-D37
DDI1_PAIR4+C25
DDI1_PAIR4-C26
DDI1_PAIR5+C29
DDI1_PAIR5-C30
DDI1_PAIR6+C15
DDI1_PAIR6-C16
DDI1_HPDC24Digital Display Interface Hot-Plug DetectI PCIEPD 100K
DDI1_CTRLCLK_AUX+D15IF DDI1_DDC_AUX_SEL is floatingI/O PCIePD 100KDP1_AUX+AC coupled on Module
IF DDI1_DDC_AUX_SEL pulled highI/O OD 3.3VHDMI1_CTRLCLK PU 10k 3.3V
DDI1_CTRLDATA_AUX-D16IF DDI1_DDC_AUX_SEL is floatingI/O PCIePU 100K 3.3VDP1_AUX-AC coupled on Module
IF DDI1_DDC_AUX_SEL pulled highI/O OD 3.3VHDMI1_CTRLDATA PU 10k 3.3V
DDI1_DDC_AUX_SELD34Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.I/O OD 3.3VPD 1M
DDI 2
SignalPinDescriptionI/OPU/PDComment
DDI2_PAIR0+D39Digital Display Interface2 differential pairs
DDI2_PAIR0-D40
DDI2_PAIR1+D42
DDI2_PAIR1-D43
DDI2_PAIR2+D46
DDI2_PAIR2-D47
DDI2_PAIR3+D49
DDI2_PAIR3-D50
DDI2_HPDD44PD100K
DDI2_CTRLCLK_AUX+C32IF DDI2_DDC_AUX_SEL is floatingI/O PCIePD100KDP2_AUX+AC coupled on Module
IF DDI2_DDC_AUX_SEL pulled highI/O OD3.3VHDMI2_CTRLCLKPU 10k 3.3V
DDI2_CTRLDATA_AUX-C33IF DDI2_DDC_AUX_SEL is floatingI/O PCIePU100K3.3VDP2_AUX-AC coupled on Module
IF DDI2_DDC_AUX_SEL pulled highI/O OD3.3VHDMI2_CTRLDATAPU 10k 3.3V
DDI2_DDC_AUX_SELC34Selects the function ofDDI2_CTRLCLK_AUX+ andDDI2_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/-signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATAsignals.PD 1M
DDI 3 (not supported on this product)
SignalPinDescriptionI/OPU/PDComment
DDI3_PAIR0+C39Digital Display Interface3 differential pairs
DDI3_PAIR0-C40
DDI3_PAIR1+C42
DDI3_PAIR1-C43
DDI3_PAIR2+C46
DDI3_PAIR2-C47
DDI3_PAIR3+C49
DDI3_PAIR3-C50
DDI3_HPDC44PD 100K
DDI3_CTRLCLK_AUX+C36IF DDI3_DDC_AUX_SEL is floatingI/O PCIePD 100KDP3_AUX+; AC coupled on Module
IF DDI3_DDC_AUX_SEL pulled highI/O OD 3.3VHDMI3_CTRLCLK; PU 10k 3.3V
DDI3_CTRLDATA_AUX-C37IF DDI3_DDC_AUX_SEL is floatingI/O PCIePU 100K 3.3VDP3_AUX-; AC coupled on Module
IF DDI3_DDC_AUX_SEL pulled highI/O OD 3.3VHDMI3_CTRLDATA; PU 10k 3.3V
DDI3_DDC_AUX_SELC38Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.PD 1M
3.4.4. DDI to DP/HDMI/SDVO Mapping
PinPin NameDPHDMI \ DVI
D26DDI1_PAIR0+DP1_LANE0+TMDS1_DATA2+
D27DDI1_PAIR0-DP1_LANE0-TMDS1_DATA2-
D29DDI1_PAIR1+DP1_LANE1+TMDS1_DATA1+
D30DDI1_PAIR1-DP1_LANE1-TMDS1_DATA1-
D32DDI1_PAIR2+DP1_LANE2+TMDS1_DATA0+
D33DDI1_PAIR2-DP1_LANE2-TMDS1_DATA0-
D36DDI1_PAIR3+DP1_LANE3+TMDS1_CLK+
D37DDI1_PAIR3-DP1_LANE3-TMDS1_CLK-
C25DDI1_PAIR4+
C26DDI1_PAIR4-
C29DDI1_PAIR5+
C30DDI1_PAIR5-
C15DDI1_PAIR6+
C16DDI1_PAIR6-
C24DDI1_HPDDP1_HPDHDMI1_HPD
D15DDI1_CTRLCLK_AUX+DP1_AUX+HMDI1_CTRLCLK
D16DDI1_CTRLDATA_AUX-DP1_AUX-HMDI1_CTRLDATA
D34DDI1_DDC_AUX_SEL
D39DDI2_PAIR0+DP2_LANE0+TMDS2_DATA2+
D40DDI2_PAIR0-DP2_LANE0-TMDS2_DATA2-
D42DDI2_PAIR1+DP2_LANE1+TMDS2_DATA1+
D43DDI2_PAIR1-DP2_LANE1-TMDS2_DATA1-
D46DDI2_PAIR2+DP2_LANE2+TMDS2_DATA0+
D47DDI2_PAIR2-DP2_LANE2-TMDS2_DATA0-
D49DDI2_PAIR3+DP2_LANE3+TMDS2_CLK+
D50DDI2_PAIR3-DP2_LANE3-TMDS2_CLK-
D44DDI2_HPDDP2_HPDHDMI2_HPD
C32DDI2_CTRLCLK_AUX+DP2_AUX+HDMI2_CTRLCLK
C33DDI2_CTRLDATA_AUX-DP2_AUX-HDMI2_CTRLDATA
C34DDI2_DDC_AUX_SEL
C39DDI3_PAIR0+DP3_LANE0+TMDS3_DATA2+
C40DDI3_PAIR0-DP3_LANE0-TMDS3_DATA2-
C42DDI3_PAIR1+DP3_LANE1+TMDS3_DATA1+
C43DDI3_PAIR1-DP3_LANE1-TMDS3_DATA1-
C46DDI3_PAIR2+DP3_LANE2+TMDS3_DATA0+
C47DDI3_PAIR2-DP3_LANE2-TMDS3_DATA0-
C49DDI3_PAIR3+DP3_LANE3+TMDS3_CLK+
C50DDI3_PAIR3-DP3_LANE3-TMDS3_CLK-
C44DDI3_HPDDP3_HPDHDMI3_HPD
C36DDI3_CTRLCLK_AUX+DP3_AUX+HDMI3_CTRLCLK
C37DDI3_CTRLDATA_AUX-DP3_AUX-HDMI3_CTRLDATA
C38DDI3_DDC_AUX_SEL
3.4.5. PCI Express Graphics x16 (not supported)
SignalPinDescriptionI/OPU/PDComment
PEG_RX0+C52PCI Express Graphics transmit differential pairs.I PCIENot supported
PEG_RX0-C53
PEG_RX1+C55
PEG_RX1-C56
PEG_RX2+C58
PEG_RX2-C59
PEG_RX3+C61
PEG_RX3-C62
PEG_RX4+C65
PEG_RX4-C66
PEG_RX5+C68
PEG_RX5-C69
PEG_RX6+C71
PEG_RX6-C72
PEG_RX7+C74
PEG_RX7-C75
PEG_RX8+C78
PEG_RX8-C79
PEG_RX9+C81
PEG_RX9-C82
PEG_RX10+C85
PEG_RX10-C86
PEG_RX11+C88
PEG_RX11-C89
PEG_RX12+C91
PEG_RX12-C92
PEG_RX13+C94
PEG_RX13-C95
PEG_RX14+C98
PEG_RX14-C99
PEG_RX15+C101
PEG_RX15C102
PEG_TX0+D52PCI Express Graphics receive differential pairs.O PCIENot supported
PEG_TX0-D53
PEG_TX1+D55
PEG_TX1-D56
PEG_TX2+D58
PEG_TX2-D57
PEG_TX3+D61
PEG_TX3-D62
PEG_TX4+D65
PEG_TX4-D66
PEG_TX5+D68
PEG_TX5-D69
PEG_TX6+D71
PEG_TX6-D72
PEG_TX7+D74
PEG_TX7-D75
PEG_TX8+D78
PEG_TX8-D79
PEG_TX9+D81
PEG_TX9-D82
PEG_TX10+D85
PEG_TX10-D86
PEG_TX11+D88
PEG_TX11-D89
PEG_TX12+D91
PEG_TX12-D92
PEG_TX13+D94
PEG_TX13-D95
PEG_TX14+D98
PEG_TX14-D99
PEG_TX15+D101
PEG_TX15-D102
PEG_LANE_RV#D54PCI Express Graphics lane reversal input strap.Pull low on the Carrier board to reverse lane order.I 1.05VNot supported
# 3.4.6. Module Type Definition
SignalPin #DescriptionI/OComment
TYPE0#C54The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don't care (X).Type 6
TYPE1#C57
TYPE2#D57TYPE2# TYPE1# TYPE0#
X X X Pinout Type 1
NC NC NC Pinout Type 2
NC NC GND Pinout Type 3 (no IDE)
NC GND NC Pinout Type 4 (no PCI)
NC GND GND Pinout Type 5 (no IDE, no PCI)
GND NC NC Pinout Type 6 (no IDE, no PCI)
The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.
# 3.4.7. Power and Ground
SignalPin #DescriptionI/OPU/PDComment
VCC_12VC104-C109D104-D109Primary power input: +12V nominal (wide range 5 ~ 20V).All available VCC_12V pins on the connector(s) shall be usedP4.75 - 20V
GNDC1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110Ground - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to carrier board GND plane.P
This page intentionally left blank. # 4. Module Interfaces This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification # 4.1. Connector, Switch and LED Locations ![MIPI60\n60-pin\nto CPU\nAB\n40-pin\nDebug Connector\nLED3\nLED2\nLED1\n4-pin\nFan\nCD\nK\nF\nBIO S Defaults\nRESET Switch](.cexpress-al-50-1j068-1020-12/cfb16f6380fa48521a2db22147e5ee88e6a35e9e51009b8869b35b8c389740ba.jpg) Figure 3: cExpress-AL Connector, Switch and LED Locations # cExpress-AL and the DB40 Debug Module For illustration purposes only ![Two electronic circuit boards connected via a cable, one showing internal components and the other with connectors (no visible text or symbols)](.cexpress-al-50-1j068-1020-12/a84c961e3ed0510f69111a288a5757b2c567d81daeef5ced4e2a9938559fb756.jpg) Figure 4: cExpress-AL and the DB40 Debug Module # 4.2. 40-pin Debug Connector FPC Connector Type: FCI 59GF Flex 10042867 Pin Orientation ![Close-up of a green printed circuit board with a black connector and gold contacts, labeled with numbers 1 and 40 (no readable text beyond labels)](.cexpress-al-50-1j068-1020-12/a87d175d4154a50b251d01b9ea498798efbd473b5bd9b0734ebb13c99f95cf62.jpg) 40-pin Debug Connector Pin Definition on the COM Express Module
PinInterfaceSignalRemark
1SPI Program interfaceVCC_SPI_INSPI Power Input from flash tool to module. HW need add MOS FET to switch SPI power for SPI ROM
2GND
3SPI_BIOS_CS0#
4SPI_BIOS_CS1#
5SPI_BIOS_MISO
6SPI_BIOS_MOSI
7SPI_BIOS_CLK
8LPC Bus3V3_LPCSystem power 3.3V provide from COM module
9GND
10BIOS_DIS0
11RST#
12CLK33_LPC
13LPC_FRAME#
14LPC_AD3
15LPC_AD2
16LPC_AD1always power 3.3V provide from COM module
17LPC_AD0
18BMC Program interface3.3V_BMCalways power 3.3V provide from COM module
193.3V_BMCalways power 3.3V provide from COM module
20GND
PinInterfaceSignalRemark
21BMC Program interface (cont'd)TXD6
22RXD6
23FUMD0
24RESET_IN#
25DATA
26CLK
27OCD0AInclude a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC
28OCD0BInclude a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC
29Test pointsPWRBTN#
30SYS_RESET#
31CB_RESET#
32CB_PWROK
33SUS_S3#
34SUS_S4#
35SUS_S5#
36BMC Debug signalsPOSTWDT_DIS#Connect to Jumper for Debug
37SEL_BIOSConnect to Jumper for Debug
38BIOS_MODEConnect to Jumper for Debug
39BMC_STATUS
40Reserved
Table 2: 40-pin Debug Connector Pin Definition Note: The pin definition on the debug module is the inverse of that on the COM Express module. # 4.3. Status LEDs To facilitate easier maintenance, status LED's are mounted on the board. ![Close-up of a green printed circuit board with integrated circuits and connectors (no visible text or symbols)](.cexpress-al-50-1j068-1020-12/925e05085969fe04a7fe78fc03cd5ab4289c4f2513ae08f60b239da94ffc0f35.jpg) LED1 LED2 LED3 LED Descriptions
NameColorConnectionFunction
LED1BlueBMC outputPower Sequence Status Code (BMC)Power Changes, RESET(see 5.1.4 Exception Codes)
LED2GreenPower Source 3VccS0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3RedBMC output and same signal as WDT (B27) on BtB connectorModule power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFF
Table 3: cExpress-AL LED Descriptions # 4.4. MIPI60 Debug Header (build option) Not all pins of the Intel® MIPI60 connector are connected to the CombiProbe Intel x86/x64 MIPI60-C.
PinSignal
1VREF_DEBUG
3TCK0
5TDI
7Reset In
9TRST_N
11PRDY_N
13PTI_0_CLK
15GND
17No Connect
19PTI_0_DATA[0]
21PTI_0_DATA[1]
23PTI_0_DATA[2]
25PTI_0_DATA[3]
27PTI_0_DATA[4]
29PTI_0_DATA[5]
31PTI_0_DATA[6]
33PTI_0_DATA[7]
35No Connect
37No Connect
39No Connect
41No Connect
43No Connect
45No Connect
47No Connect
49No Connect
51No Connect
53No Connect
55No Connect
57GND
59No Connect
PinXDP Signal
2TMS
4TDO
6Open Drain Reset Out
8No Connect
10PREQ_N
12VREF_TRACE
14PTI_1_CLK
16GND
18PTI_1_DATA[0]
20PTI_1_DATA[1]
22PTI_1_DATA[2]
24PTI_1_DATA[3]
26No Connect
28No Connect
30No Connect
32No Connect
34Reset Out
36Boot Stall
38CPU Boot Stall
40Power Button
42PWRGOOD
44No Connect
46No Connect
48I2C_SCL
50I2C_SDA
52No Connect
54DBG_UART_TX
56DBG_UART_RX
58GND
60No Connect
Table 4: MIPI60 Debug Header Pin Definition # 4.5. Fan Connector Connector Type: JVE 24W1125A-04M00 Pin Orientation ![Close-up of a green printed circuit board with electronic components and a circular connector (no visible text or symbols)](.cexpress-al-50-1j068-1020-12/842ef7786731f98234f362d2b7be5b6e9229623dbce3a8515f8ca20401834ff4.jpg) Pin Assignment
NameSignal
1FAN_PWMOUT
2FAN_TACHIN
3Ground
45V
Table 5: Fan Connector Pin Definition # 4.6. BIOS Setup Defaults Reset Button ![Close-up of a green printed circuit board with visible components and a red arrow pointing to a component (no readable text or symbols)](.cexpress-al-50-1j068-1020-12/2a67e1e650d0da975cd329d7880ad6c87b45889ef70bf272e6ad9a82ca1de4b1.jpg) To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.cexpress-al-50-1j068-1020-12/9faf9dea2903fd4d03bca096356f46f7430dcc62e1e9698e75af2f8503711a85.jpg) # 4.7. Switch Settings # Switch Locations ![BIOS Select and Mode\nConfiguration Switch](.cexpress-al-50-1j068-1020-12/b14918f0080a215fc896c49ec18e5c5258ce43f5407c9bceef02803484d8e605.jpg) Figure 5: cExpress-AL Switch Locations # BIOS Select and Mode Configuration Switch The module has two BIOS chips and BIOS operation can be configured to "PICMG" or dual-BIOS "Failsafe" modes using the BIOS Select and Mode Configuration Switch, Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, BIOS Select and Mode Configuration Switch, Pin 1 is used to select whether to boot from SPI0 or SPI1.
ModePin 1Pin 2
Boot from SPI0 (default)On—
Boot from SPI1Off—
Set BIOS to PICMG mode—On
Set BIOS to Failsafe BIOS mode (default)—Off
Table 6: BIOS Select and Mode Configuration Switch Settings This page intentionally left blank. # 5. Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: • Total operating hours counter. Counts the number of hours the module has been run in minutes. - On-time minutes counter. Counts the seconds since last system start. - Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash. • Power cycles counter - Boot counter. Counts the number of boot attempts. - Watchdog Timer. Set/Reset/Disable Watchdog Timer. Features auto-reload at power-up. • System Restart Cause. Power loss/BIOS Fail/Watchdog/Internal Reset/External Reset - Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS. • Flash area. 1kB Flash area for customer data • 2K Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region. • Board Identify. Vendor/Board/Serial number/Production Date • Main-current & voltage. Monitors drawn current and main voltages For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/sema/. Note: Due to limitations of the Intel “Apollo Lake” platform, SEMA can only obtain CPU temperature readings when the OS is running. # 5.1. Board Specific SEMA Functions # 5.1.1. Voltages The BMC of the cExpress-AL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).
ADC ChannelVoltage NameVoltage Formula [V]
0VCC_CORE(MSB<<8 + LSB) x 3.3 / 1024
1VGFX(MSB<<8 + LSB) x 3.3 / 1024
2VMEM(MSB<<8 + LSB) x 3.3 / 1024
35VSB(MSB<<8 + LSB) x 1.8 x 3.3 / 1024
4VIN (12V)(MSB<<8 + LSB) x 6 x 3.3 / 1024
55V(MSB<<8 + LSB) x 1.8 x 3.3 / 1024
63.3V(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
73.3VSB(MSB<<8 + LSB) x 1.1 x 3.3 / 1024
8RTC (build option support)(MSB<<8 + LSB) x 3.3 / 1024
Table 7: SEMA Onboard Voltage Monitor # 5.1.2. Main Current The BMC of the cExpress-AL implements a current monitor. The current can be read by calling the SEMA function "Get Main Current". The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access. $$ \text { Main Current } = (\text { MSB\_n } < < 8 + \text { LSB\_n }) \times 8. 0 6 \mathrm{mA} $$ # 5.1.3. BMC Status This register shows the status of BMC controlled signals on the cExpress-AL. <table>Status BitSignal0WDT_OUT1LVDS_VDDEN2LVDS_BKLTEN3BIOS_MODE4POSTWDT_DISn5SEL_BIOS6BIOS_DIS0n7BIOS_DIS1n Table 8: SEMA BMC Status # 5.1.4. Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.
Exception CodeError Message
0NOERROR
2NO_SUSCLK
3NO_SLP_S4_S5
4NO_SLP_S3
5BIOS_FAIL
6RESET_FAIL
7RESETIN_FAIL
8NO_CB_PWRGD
9CRITICAL_TEMP
10POWER_FAIL
11VOLTAGE_FAIL
12NO_3V3_5V_A_PG
13NO_VNN_PG
14NO_1V24_A_PG
15NO_VDDQ_PG
16NO_V1P05S_PG
17NO_SYS_GD
18NO_V12
19MEMORY_ERROR
20NO_P3V3_A_READY
Table 9: SEMA Exception Codes # 5.1.5. BMC Flags The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.
BitDescription
[0 ~ 4]Exception Code
[6]0 = AT mode1 = ATX mode
[7]0 = Standard BIOS1 = Fail-safe BIOS.
Table 10: SEMA BMC Flags This page intentionally left blank. # 6. System Resources # 6.1. System Memory Map
Address Range (hex)Description
FF00_0000 - FFFF_FFFFIFAW (BIOS)
FED0_0000 - FEDF_33FFHPET
FEC0_0000 - FECF_FFFFIOAPIC
0K -1MBDOS DRAM
# 6.2. I/O Map
I/O AddressIOSF Primary TargetIOSF SB Target
000h-01FhP2SBTerminate
020h-021hP2SBITSS (interrupt)
024h-025hP2SBITSS (interrupt)
028h-029hP2SBITSS (interrupt)
02Ch-02DhP2SBITSS (interrupt)
02Eh-02FhP2SBLPC/eSPI
030h-031hP2SBITSS (interrupt)
034h-035hP2SBITSS (interrupt)
038h-039hP2SBITSS (interrupt)
03Ch-03DhP2SBITSS (interrupt)
040hP2SBITSS (Timer 0 Register)
041hP2SBTerminate
042hP2SBITSS (Timer 2 Register)
043hP2SBITSS (Timer Control Word Register)
04Eh-04FhLPC/eSPILPC/eSPI
050hP2SBITSS (alias of 040h)
051hP2SBTerminate
052hP2SBITSS (alias of 042h)
053hP2SBITSS (alias of 043h)
060hP2SBLPC/eSPI
061hP2SBITSS (CPU I/F)
062hP2SBLPC/eSPI
063hP2SBITSS (CPU I/F)
064hP2SBLPC/eSPI
065hP2SBITSS (CPU I/F)
066hP2SBLPC/eSPI
067hP2SBITSS (CPU I/F)
070hP2SBITSS (CPU I/F), RTC, PMC
071hP2SBRTC, PMC
072h–073hP2SBRTC, PMC
073hP2SBRTC, PMC
074hP2SBRTC, PMC
075hP2SBRTC, PMC
076h–077hP2SBRTC, PMC
080hP2SBLPC/eSPI or PMC
081h–083hP2SBTerminate
084h–086hP2SBLPC/eSPI or PMC
087hP2SBTerminate
088hP2SBLPC/eSPI or PMC
089h–08BhP2SBTerminate
08Ch–08EhP2SBLPC/eSPI or PMC
08FhP2SBTerminate
090hP2SBLPC/eSPI
091hP2SBTerminate
092hP2SBITSS (CPU I/F)
093hP2SBTerminate
094h–096hP2SBLPC/eSPI or PMC
097hP2SBTerminate
098hP2SBLPC/eSPI or PMC
099h–09BhP2SBTerminate
09Ch–09EhP2SBLPC/eSPI or PMC
09FhP2SBTerminate
0A0h–0A1hP2SBITSS (interrupt)
0A4h–0A5hP2SBITSS (interrupt)
0A8h–0A9hP2SBITSS (interrupt)
0ACh–0ADhP2SBITSS (interrupt)
0B0h–0B1hP2SBITSS (interrupt)
0B2h–0B3hP2SBPMC
0B4h–0B5hP2SBITSS (interrupt)
0B8h–0B9hP2SBITSS (interrupt)
0BCh–0BDhP2SBITSS (interrupt)
0C0h-0DFhP2SBTerminate
0F0hP2SBTerminate
170h-177hP2SBTerminate
2F8h-2FFhP2SBSerial Port
240h-24FhP2SBSerial Port
2F8h-2FFhP2SBSerial Port
376hP2SBTerminate
3F6hP2SBTerminate
3F8h-3FFhP2SBSerial Port
4D0h-4D1hP2SBITSS (interrupt)
CF9hP2SBITSS (CPU I/F)
# 6.3. Interrupt Request (IRQ) Lines # APIC Mode The following table describes the APIC interrupt mapping. In The Apollo Lake platform has 120 IRQs in total.
IO APIC PinRouting
08259 Apollo Lake
1PS2 Keyboard
28254 Counter 0, HPET #0 (legacy mode)
3Serial Port 3
4Serial Port 4
5NA
6NA
7NA
8RTC, HPET #1 (legacy mode)
9Option for configurable sources including internal ACPI/PCI devices, SCI and TCO
10Serial Port 1
11Serial Port 2
12PS2 Mouse
13xDCI
14Option for configurable sources including GPIO, internal ACPI/PCI devices
15Option for configurable sources including internal ACPI/PCI devices
16Option for configurable sources including internal PIRQA, internal ACPI/PCI devices
17PIRQB (xHCI)
18Option for configurable sources including internal PIRQC, internal ACPI/PCI devices
19Option for configurable sources including internal PIRQD, internal ACPI/PCI devices
20Option for configurable sources including internal PIRQE, SCI, TCO, internal ACPI/PCI devices and HPET
21Option for configurable sources including internal PIRQF, SCI, TCO, internal ACPI/PCI devices and HPET
22Option for configurable sources including internal PIRQG, SCI, TCO, internal ACPI/PCI devices and HPET
23Option for configurable sources including internal PIRQH, SCI, TCO, internal ACPI/PCI devices and HPET
24Punit (DPTF)
25Audio
26ISH
27I2C 0
28I2C 1
29I2C 2
30I2C 3
31I2C 4
32I2C 5
33I2C 6
34I2C 7
35SPI 0
36SPI 1
37SPI 2
38UFS
39EMMC
40PMC IPC
41PMC PMIC
42SDIO
43reserved
44reserved
45reserved
46reserved
47reserved
48reserved
49reserved
50 - 119GPIO (Not for end user)
6.4. PCI Configuration Space Map
Logical FunctionBusDeviceFunction
Host Bridge000
DPTF (Camarillo)001
NPK002
NPK (PSF ghost)005
GMM003
Gen020
lunit030
Reserved (CSE)70
P2SB0130
PMC0131
SPI0132
Shared SRAM0133
Audio0140
CSE-HECI10150
CSE-HECI20151
CSE-HECI30152
CSE-fTPM (PSF ghost)0157
CSE-HOFFL0160
ISH0170
SATA0180
PCIe-A 10190
PCIe-A 20191
PCIe-A 30192
PCIe-B 1 (multiplexed with USB 3.0 port)0193
PCIe-B 2 (connect to onboard LAN)0200
PCIe-A 10201
USB-Host (xHCI)0210
USB-Device (xDCI)0211
I2C 00220
I2C 10221
I2C 20222
I2C 30223
CSE I2C 6/7 access0226
CSE SSRAM access0227
I2C 40230
I2C 50231
I2C 60232
I2C 70233
UART 00240
UART 10241
UART 20242
UART 30243
SPI 00250
SPI 10251
SPI 20252
PWM0260
SD Card0270
eMMC0280
UFS0290
SDIO0300
LPC0310
SMBUS0311
# 6.5. PCI Interrupt Routing Map
INT LinePCIE port1PCIE port 2PCIE port 3PCIE port 4PCIE Port 5PCIE Onboard LAN i210Mobile IGFXPUNIT Device
Int0INTA:22INTB:23INTC:22INTD:23INTA:20INTB:21NTD:19
Int1INTB:23INTC:20INTD:23INTA:20INTB:21INTC:22INTF:24
Int2INTC:20INTD:21INTA:20INTB:21INTC:22INTD:23
Int3INTD:21INTA:22INTB:21INTC:22INTD:23INTA:20
INT LineSMBus ControllerNPK DeviceIUNTPMCHD AudioCESISHSATA ControllerXHCIXDCI
Int0INTA:16INTF:21INTA:40INTA:25INTE:20INTE:26INTA:19INTB:17
Int1INTE:20INTC:13
Int2
Int3
INT LineI2C0I2C1I2C2I2C3I2C4I2C5I2C6I2C7SPI1
Int0INTA:27INTF:31INTA:35
Int1INTB:28INTB:32
Int2INTC:29INTC:33
Int3INTD:30INTD:34
INT LineSPI3SPI3SD Host #0SD Host #1SD Host #2SD Host #3
Int0INTC:15INTD:39INTH:38INTB:37
Int1INTB:36
Int2INTC:37
Int3
# 6.6. SMBus Address Table
DeviceAddress
DIMMAA0h
DIMMBA4h
BMC50h
Extend GPIO40h
I21049h
USB2514BI58h
LM7392h
PEX8605B7h,C1h
NXP(eDP to LVDS transmitter)C0h
# 7. BIOS Setup # 7.1. Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
MainAdvancedChipsetSecurityBootSave & Exit
BIOS Information System Information Board Information System Date and Time Access LevelCPU Configuration Graphics Configuration Power Management System Management Thermal Management Watchdog Timer CSM Configuration Super IO Configuration Serial Console Redirection USB Network Miscellaneous Driver Health Trusted Computing AMI Graphic Output Protocol Policy SDIO ConfigurationNorth Bridge South Bridge Uncoe Configuration South Cluster ConfigurationSetup Administrator Password User Password Secure BootBoot Configuration FIXED BOOT ORDER Priorities UEFI USB Key Drive BBS PrioritiesSave Change and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Options Boot Override
# 7.2. Main # 7.2.1. Main > BIOS Information
FeatureOptionsDescription
BIOS VenderInfo onlyAmerican Megatrends
BIOS VersionInfo onlyADLINK BIOS version
Build DateInfo onlyADLINK BIOS Build Date
MRC VersionInfo onlyDisplay MRC Version
GOP VersionInfo onlyDisplay GOP Version
TXE FW VersionInfo onlyDisplay TXE FW Version
BIOS Boot SourceInfo onlyDisplay BIOS Boot Source
# 7.2.2. Main > System Information
FeatureOptionsDescription
Project NameInfo onlyDisplay Project Name.
CPU Board versionInfo onlyDisplay CPU Board Version.
CPU Board StringInfo onlyDisplay CPU Board String.
CPU FrequencyInfo onlyDisplay CPU Frequency.
Total MemoryInfo onlyDisplay Installed Memory Size.
Memory FrequencyInfo onlyDisplay Memory Frequency.
SOC SKUInfo onlyDisplay SOC SKU Version
# 7.2.3. Main > Board Information
FeatureOptionsDescription
Board InformationSubmenu
Board InformationInfo only
Serial NumberInfo onlyDisplay SEMA serial Number.
Manufacturing DateInfo onlyDisplay SEMA manufacturing date.
Last Repair DateInfo onlyDisplay SEMA last repair date.
MAC IDInfo onlyDisplay SEMA MAC ID.
Runtime StatisticsInfo only
Total RuntimeInfo onlyThe returned value specifies the total time in minutes the system is running in S0 state.
Current RuntimeInfo onlyThe returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.
Power CyclesInfo onlyThe returned value specifies the number of times the external power supply has been shut down
Boot CyclesInfo onlyThe Boot counter is increased after a HW- or SW-Reset or after a successful power-up.
Boot ReasonInfo onlyThe boot reason is the event which causes the reboot of the system.
# 7.2.4. Main >System Date/Time
FeatureOptionsDescription
System DateInfo only
System TimeInfo only
# 7.2.5. Main >Access Level
FeatureOptionsDescription
Access LevelInfo only
# 7.3. Advanced This menu contains the settings for most of the user interfaces in the system. 7.3.1. Advanced > CPU Configuration
FeatureOptionsDescription
CPU ConfigurationInfo only
Socket 0 CPU InformationSubmenuSocket Specific CPU Information.
Stocket 0 CPU informationInfo only
CPU SignatureInfo onlyDisplay CPU Signature.
Microcode PatchInfo onlyDisplay Microcode Patch.
Max CPU SpeedInfo onlyDisplay Max CPU speed.
Min CPU speedInfo onlyDisplay Min CPU speed.
Processor CoresInfo onlyDisplay Processor Cores.
Intel HT TechnologyInfo onlyDisplay Intel HT Technology support or not.
Intel VT-x TechnologyInfo onlyDisplay Intel VT-x Technology support or not.
L1 Data CacheInfo onlyDisplay cache info.
L1 Code CacheInfo onlyDisplay cache info.
L2 CacheInfo onlyDisplay cache info.
L3 CacheInf o onlyDisplay cache info.
SpeedInfo onlyDisplay CPU Speed.
64-bitInfo onlyDisplay 64-bit Support.
CPU Power ManagementSubmenuCPU Power Management options.
CPU Power Management ConfigurationInfo only
EISTDisabled EnabledEnable / Disable Intel SpeedStep
Burst ModeDisabled EnabledEnable / Disable Burst mode.
Boot performance modeMax Performance Max BatterySelect the performance state that the BIOS will set before OS handoff.
C-StatesDisabled EnabledEnable / Disable C Sates.
Enhanced C-statesDisabled EnabledEnable / Disable C1E. When enabled, CPU will switch to minimum speed when all core enter C-States.
Max Package C StatePC2 PC1 C0Controls the Max Package C State that the processor will support.
Max Core C StateFused value Core C10Core C9Core C8Core C7Core C6Core C1UnlimitedThis option controls the Max Core C State that cores will Support.
C-State Auto DemotionDisabledC1Configure C-State Auto Demotion
C-State Un-demotionDisabledC1Configure C-State Auto Un-demotion
Power Limit 1 EnableDisabledEnabledEnable / Disable Power Limit 1
Power Limit 1Info OnlyDisplay Power Limit 1 Power Watts.
Power Limit 1 Clamp ModeDisabledEnabledEnable / Disable Power Limit 1 Clamp Mode.
Power Limit 1 PowerAuto678910111213141516171819202122232425Power Limit 1 in Watts.Auto will program Power Limit 1 based on silicon default support value.
Power Limit 1 Time WindowsAuto123456781012141620242832404856648096112128Power Limit 1 Time Windows Value in Seconds.Auto will program Power Limit 1 Time Windows base on silicon default support value.
Active Processor CoresDisabledEnabledNumber of cores to enable in each processor package.
Intel Virtualization TechnologyDisabledEnabledWhen enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.
VT-dDisabledEnabledEnable / Disable CPU VT-d
Bi-directional PROCHOTDisabledEnabledWhen a processor thermal sensor trips (either core), the PROCHOT# will be driven.If bi-direction is enabled, external agents can drive PROCHOT# to throttle the processor.
Thermal MonitorDisabledEnabledEnable / Disable Thermal Monitor.
Monitor MwaitDisabledEnabledAutoEnable / Disable Monitor Mwait.
P-STATE CoordinationHW_ALLSW_ALLSW_ANYChange P-STATE Coordination type.
DTSDisabledEnabledEnable / Disable Digital Thermal Sensor.
# 7.3.2. Advanced > Graphics Configuration
FeatureOptionsDescription
Graphics ConfigurationInfo only
LVDSInfo only
Data format and Color DepthVESA 24 bppJEIDA 24 bbpJEIDA/vesa 18 bppData format and Color Depth select
LVDS Output ModeDual LVDS busSignal LVDS busSignal / Dual mode select
DE PolaarityActive HighActive LowDE Polaarity Select
Vsync PolarityActive HighActive LowVsync Polarity select
Hsync PolarityActive HighActive LowHsync Polarity select
LVDS Backlight Brightness0 - 255LVDS Backlight Brightness adjust.A change takes effect immediately.
7.3.3. Advanced > Power Management
FeatureOptionsDescription
Power ManagementInfo only
Enable ACPI Auto ConfigurationDisabled EnabledEnables or Disables BIOS ACPI Auto Configuration.
Enable HibernationDisabled EnabledEnable or Disable System ability to Hibernate (OS/S4 Sleep State).This option maybe not effective with some OS.
ACPI Sleep StateSuspend Disable S3 (Suspend to RAM)Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.
Emulation AT/ATXEmulation AT ATXSelect Emulation AT or ATX function.If this option set to [Emulation AT], BIOS will report no suspend functions to ACPI OS.In windows XP, it will make OS show shutdown message during system shutdown.
Lock Legacy ResourcesDisabled EnabledEnables or Disables Lock of Legacy Resources.
LID FunctionDisabled EnabledEnable / Disable LID Function.
ECO ModeDisabled EnabledReduces the power consumption of the system, but after a shutdown, you have to wait at least 5 seconds before you can restart the system.
Power ConsumptionSubmenuPower Consumption.
7.3.3.1. Advanced > Power Management > Power Consumption
FeatureOptionsDescription
Power ConsumptionInfo Only
Current Input CurrentInfo OnlyDisplay Current Input Current
Current Input PowerInfo OnlyDisplay Current Input Power
VCOREInfo OnlyDisplay VCORE Voltage
VGFXInfo OnlyDisplay VGFX Voltage
VMEMInfo OnlyDisplay VMEM Voltage
5VSBInfo OnlyDisplay 5VSB Voltage
VINInfo OnlyDisplay VIN Voltage
5VInfo OnlyDisplay 5V Voltage
3.3VInfo OnlyDisplay 3.3V Voltage
3.3VSBInfo OnlyDisplay 3.3VSB Voltage
7.3.4. Advanced > System Management
FeatureOptionsDescription
System ManagementInfo Only
VersionInfo OnlyDisplay SEMA Module Version.
SEMA FirmwareInfo OnlyDisplay SEMA Firmware Version.
Build DateInfo OnlyDisplay SEMA Firmware Build Date.
SEMA BootloaderInfo OnlyDisplay SEMA Bootloader Version.
Build DateInfo OnlyDisplay SEMA Bootloader Build Date.
SEMA FeaturesSubmenuDisplay SEMA Supported Features
SEMA Supported FeaturesInfo onlyDisplay SEMA Supported Features
FlagsSubmenuFlag
FlagsInfo only
BMC FlagsInfo Only
BIOS SelectInfo Only
ATX/AT-ModeInfo Only
Exception CodeInfo Only
7.3.5. Advanced > Thermal Management
FeatureOptionsDescription
Thermal Configuration ParametersInfo Only
Thermal and Fan SpeedSubmenu
Smart FanSubmenu
Critical Trip PointDisabled80 C90 C95 C105 CThe value is the temperature threshold of the Critical Trip Point.
Passive Cooling Trip PointDisabled70 C80 C90 C100 CThe value is the temperature threshold of the Passive Cooling Trip Point.
7.3.5.1. Advanced > Thermal Management > Thermal and Fan Speed
FeatureOptionsDescription
Temperatures and Fan SpeedInfo Only
CPU TemperatureInfo Only
CurrentInfo OnlyDisplay Current CPU Temperature
Board TemperatureInfo Only
CurrentInfo OnlyDisplay Current Board Temperature
StartupInfo OnlyDisplay Startup Board Temperature
MinInfo OnlyDisplay Min Board Temperature
MaxInfo OnlyDisplay Max Board Temperature
CPU Fan SpeedInfo OnlyDisplay CPU Fan Speed
7.3.5.2. Advanced > Thermal Management > Smart Fan
FeatureOptionsDescription
Smart FanInfo Only
CPU Smart Fan Temperature SourceCPU Sensor Board SensorCPU Smart Fan Temperature Source
CPU Fan ModeAUTO (Smart Fan) Fan Off Fan OnCPU Fan Mode
PWM Level0 - 100Control PWM Level
7.3.6. Advanced > Watchdog Timer
FeatureOptionsDescription
Watchdog TimerInfo only
RunTime WatchdogDisabledEnabledThe RunTime Watchdog resets the system after a certain amount of time after power up.
7.3.7. Advanced > CSM Configuration
FeatureOptionsDescription
Compatibility Support Module ConfigurationInfo only
CSM SupportDisabled EnabledEnabled / Disabled CSM Support.
7.3.8. Advanced > Super IO Configuration
FeatureOptionsDescription
NCT5104DInfo only
Serial Port 1 ConfigurationSubmenuSet Parameters of Serial Port 1 (COMA).
Serial Port 2 ConfigurationSubmenuSet Parameters of Serial Port 2 (COMB).
W83627DHGInfo Only
Serial Port 1 ConfigurationSubmenuSet Parameters of Serial Port 1 (COMA).
Serial Port 2 ConfigurationSubmenuSet Parameters of Serial Port 2 (COMB).
7.3.8.1. Advanced > Super IO Configuration > Serial Port 1 Configuration (NCT5104D)
FeatureOptionsDescription
NCT5104DInfo only
Serial Port 1 ConfigurationSubmenuSet Parameters of Serial Port 1 (COMA).
Serial Port 1 ConfigurationInfo only
Serial PortDisabledEnabledEnable or Disable Serial Port (COM).
Device SettingsInfo OnlyDisplay IO / IRQ information of COM Port.
Change SettingsAutoIO=240h; IRQ=10;IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12Select an optimal setting for Super IO Device.
7.3.8.2. Advanced > Super IO Configuration > Serial Port 2 Configuration (NCT5104D)
FeatureOptionsDescription
Serial Port 2 ConfigurationSubmenuSet Parameters of Serial Port 2 (COMB).
Serial Port 2 ConfigurationInfo only
Serial PortDisabledEnabledEnable or Disable Serial Port (COM).
Device SettingsInfo OnlyDisplay IO / IRQ information of COM Port.
Change SettingsAutoIO=248h; IRQ=11;IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12Select an optimal setting for Super IO Device.
7.3.8.3. Advanced > Super IO Configuration > Serial Port 1 Configuration (W83627DHG)
FeatureOptionsDescription
Serial Port 1 ConfigurationSubmenuSet Parameters of Serial Port 1 (COMA).
Serial Port 1 ConfigurationInfo only
Serial PortDisabledEnabledEnable or Disable Serial Port (COM).
Device SettingsInfo OnlyDisplay IO / IRQ information of COM Port.
Change SettingsAutoIO=3F8h; IRQ=4;IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12Select an optimal setting for Super IO Device.
7.3.8.4. Advanced > Super IO Configuration > Serial Port 2 Configuration (W83627DHG)
FeatureOptionsDescription
Serial Port 2 ConfigurationSubmenuSet Parameters of Serial Port 2 (COMB).
Serial Port 2 ConfigurationInfo only
Serial PortDisabledEnabledEnable or Disable Serial Port (COM).
Device SettingsInfo OnlyDisplay IO / IRQ information of COM Port.
Change SettingsAutoIO=2F8h; IRQ=3;IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12Select an optimal setting for Super IO Device.
7.3.9. Advanced > Serial Console Redirection
FeatureOptionsDescription
COM1Info only
Console RedirectionEnabledDisabledConsole Redirection Enable or Disable.
Console Redirection SettingsSubmenuThe settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM2Info only
Console RedirectionEnabledDisabledConsole Redirection Enable or Disable.
Console Redirection SettingsSubmenuThe settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM3Info only
Console RedirectionEnabledDisabledConsole Redirection Enable or Disable.
Console Redirection SettingsSubmenuThe settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
COM4Info only
Console RedirectionEnabledDisabledConsole Redirection Enable or Disable.
Console Redirection SettingsSubmenuThe settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.
Legacy Console RedirectionInfo only
Legacy Console Redirection SettingsSubmenuLegacy Console Redirection Settings
7.3.9.1. Advanced > Serial Console Redirection > Console Redirection Settings (if COM1 enabled)
FeatureOptionsDescription
COM1Info only
Console Redirection SettingsInfo only
Teriminal TypeVT100VT100+VT-UTF8ANSIEmulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second9600192003840057600115200Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits78Data Bits
ParityNoneEvenOddMarkSpaceA parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits12Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow ControlNoneHardware RTS/CTSFlow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key SupportEnabledDisabledEnable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder ModeDisabledEnabledWith this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31EnabledDisabledOn Legacy OS, the Number of Rows and Columns supported redirection
Legacy OS Redirection Resolution80x2480x25On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPadVT100Intel LinuxXTERMR6SCOESCNVT400Select FunctionKey and KeyPad on Putty.
Redirection After BIOS POSTAlways EnableBootLoaderWhen Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS.When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.
7.3.9.2. Advanced > Serial Console Redirection > Console Redirection Settings (if COM2 enabled)
FeatureOptionsDescription
COM2Info only
Console Redirection SettingsInfo only
Teriminal TypeVT100VT100+VT-UTF8ANSIEmulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second9600192003840057600115200Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits78Data Bits
ParityNoneEvenOddMarkSpaceA parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits12Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow ControlNoneHardware RTS/CTSFlow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key SupportEnabledDisabledEnable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder ModeDisabledEnabledWith this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31EnabledDisabledOn Legacy OS, the Number of Rows and Columns supported redirection
Legacy OS Redirection Resolution80x2480x25On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPadVT100Intel LinuxXTERMR6SCOESCNVT400Select FunctionKey and KeyPad on Putty.
Redirection After BIOS POSTAlways EnableBootLoaderWhen Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS.When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.
7.3.9.3. Advanced > Serial Console Redirection > Console Redirection Settings (if COM3 enabled)
FeatureOptionsDescription
COM3Info only
Console Redirection SettingsInfo only
Teriminal TypeVT100VT100+VT-UTF8ANSIEmulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second9600192003840057600115200Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits78Data Bits
ParityNoneEvenOddMarkSpaceA parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits12Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow ControlNoneHardware RTS/CTSFlow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the dataflow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key SupportEnabledDisabledEnable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder ModeDisabledEnabledWith this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31EnabledDisabledOn Legacy OS, the Number of Rows and Columns supported redirection
Legacy OS Redirection Resolution80x2480x25On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPadVT100Intel LinuxXTERMR6SCOESCNVT400Select FunctionKey and KeyPad on Putty.
Redirection After BIOS POSTAlways EnableBootLoaderWhen Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS.When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.
7.3.9.4. Advanced > Serial Console Redirection > Console Redirection Settings (if COM4 enabled)
FeatureOptionsDescription
COM4Info only
Console Redirection SettingsInfo only
Teriminal TypeVT100VT100+VT-UTF8ANSIEmulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
Bits per second9600192003840057600115200Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.
Data Bits78Data Bits
ParityNoneEvenOddMarkSpaceA parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.They can be used as an additional data bit.
Stop Bits12Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Flow ControlNoneHardware RTS/CTSFlow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.
VT-UTF8 Combo Key SupportEnabledDisabledEnable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder ModeDisabledEnabledWith this mode enabled only text will be sent.This is to capture Terminal data.
Resolution 100x31EnabledDisabledOn Legacy OS, the Number of Rows and Columns supported redirection
Legacy OS Redirection Resolution80x2480x25On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPadVT100Intel LinuxXTERMR6SCOESCNVT400Select FunctionKey and KeyPad on Putty.
Redirection After BIOS POSTAlways EnableBootLoaderWhen Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.
7.3.9.5. Advanced > Serial Console Redirection > Legacy Console Redirection Settings
FeatureOptionsDescription
Legacy Serial Redirection PortCOM1COM2COM3COM4Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages
7.3.10. Advanced > USB
FeatureOptionsDescription
USBInfo Only
USB Module VersionInfo OnlyDisplay USB Module Version
USB Controllers:Info OnlyDisplay USB Controllers is XHCI or EHCI.
USB Devices:Info OnlyDisplay attatcment USB deviecs.
Legacy USB SupportEnabledDisabledAutoEnables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.
XHCI Hand-offEnabledDisabledThis is a workaround for Oses without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.
USB Mass Storage Driver SupportDisabledEnabledEnable / Disable USB Mass Storge Driver Support.
USB hardware delays and time-outs:Info Only
USB transfer rime-out1 sec5sec10sec20 secThe time-out value for Control, Bulk, and Interrupt transfers.
Device reset time-out10 sec20 sec30 sec40 secUSB mass storage device Start Unit command time-out.
Device power-up delayAutoManualMaximum time the device will take before it properly reports itself to the Hot Controller.'Auto' uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.
# 7.3.11. Advanced > Network
FeatureOptionsDescription
Onboard LAN ControllerDisable EnableEnable / Disable Onboard Intel I210LM Lan controller.
Network StackDisable EnableEnable / Disable UEFI Network Stack.
# 7.3.12. Advanced > Miscellaneous
FeatureOptionsDescription
MiscellaneousInfo OnlyControl the PCI Express Root Port.
Smart Battery FunctionDisable EnableEnable / Disable Battery Function
# 7.3.13. Advanced > Driver Health
FeatureOptionsDescription
Driver NameInfo onlyProvides Health Status for the Drivers / Controllers.
# 7.3.14. Advanced > Trusted Computing
FeatureOptionsDescription
TPM20 Device FoundInfo Only
Security Device SupportDisable EnableEnables or Disable BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.
Active PCR banksInfo Only
Available PCR banksInfo Only
Pending operationNone TPM ClearSchedule an Operation for the Security Device.NOTE: Your Computer will reboot during restart in order to change State of Security Device.
Platform hierarchyDisable EnableEnable or Disable Platform Hierarchy
Storage HierarchyDisable EnableEnable or Disable Storage Hierarchy
Endorsement HierarchyDisable EnableEnable or Disable Endorsement Hierarchy
TPM2.0 UEFI Spec VersionTCG_1_2 TCG_2Select the TCG2 Spec Version Support, TCG_1_2: the Compatible mode for Win8/Win10, TCG_2: Support new TCG2 protocol and event format for Win10 or later
Physical Presence Spec Version1.2 1.3Select to Tell O.S. to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.
TPM 20 Interface TypeInfo only
# 7.3.15. Advanced > AMI Graphic Output Protocol Policy
FeatureOptionsDescription
Intel (R) Graphics ControllerInfo Only
Intel (R) GOP DriverInfo Only
Output SelectDVIOutput Interface
# 7.3.16. Advanced > SDIO Configuration
FeatureOptionsDescription
SDIO ConfigurationInfo Only
SD Card/GPIO MODEGPIO SD CardSelect SD Card or GPIO function.
SDIO Access ModeAuto ADMA SDMA PIOAuto Option: Access SD device in DMA mode if controller supports it,otherwise in PIO mode.DMA Option: Access SD device in DMA mode.PIO Option: Access SD device in PIO mode.
Mass Storage Devices:Info Only
Sdio Device 1 Details:Info Only
Bus 0 Dev 1c Func 0Info Only
MMC - xxxx(xx.xGB)Auto Floppy Forced FDD Hard DiskMass storage device emulation type. 'AUTO' enumerates devices less than 530MB as floppies. Forced FDD option can be used to force HDD formatted drive to boot as FDD.
# 7.4. Chipset # 7.4.1. Chipset > North Bridge
FeatureOptionsDescription
Memory InformationInfo only
Total MemoryInfo onlyDisplay Total Memory Size.
Memory VlotageInfo onlyDisplay Memory Vlotage.
Memory Slot0Info onlyDisplay Installed Memory Slot0 Information.
Memory Slot1Info onlyDisplay Installed Memory Slot1 Information.
Max TOLUD2 GB2.25 GB2.5 GB2.75 GB3 GBMaximum Value of TOLUD.
PCIE VGA WorkaroundDisable EnableEnable it if your PCIe card cannot boot to DOS. This is for Test only.
# 7.4.2. Chipset > South Bridge
FeatureOptionsDescription
Serial IRQ ModeQuietContinuousConfigure Serial IRQ Mode.
SMBus SupportDisableEnableEnable / Disable SMBus Support.
OS SelectionWindowsAndroidWin7Intel LinuxSelect the target OS.
PCI CLOCK RUNDisableEnableEnables CLKRUN# logic to stop PCI clocks.
# 7.4.3. Chipset > Uncore Configuration
FeatureOptionsDescription
GOP ConfigurationInfo only
Active LFP ConfigNo LFP eDP/LVDSActive Local Flat Panel Config.
LVDS Backlight ModeGTT Mode BMC ModeSelect LVDS Backlight control function.
DDI port 1No Device Display Port HDMI DisplayPort with HDMI/DVI CompatibleDDI port 1 function choose to Display Port or HDMI.
DDI port 2No Device Display Port HDMI DisplayPort with HDMI/DVI CompatibleDDI port 2 function choose to Display Port or HDMI.
LFP Panel TypeAuto640x480800x6001024x7681280x10241400x10501600x12001366x7681680x10501920x12001440x9001600x9001280x8001920x10802048x1536Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.
GOP Brightness Level20406080100120140160180200220240255Set GOP Brightness Level.
IGD ConfigurationInfo only
Integrated Graphics DevicesDisableEnableEnable: Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor.Disable: Always disable IGD.
Primary DisplayIGDPCIeHGSelect which of IGD / PCI Graphics device should be Primary Display.
Aperture Size128MB256MB512MBSelect the Aperture Size.
DVMT Pre-Allocated64M96M128M160M192M224M256M288M320M352M384M416M448M480M512MSelect DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device
DVMT Total Gfx Mem128M256MMAXSelect DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device
# 7.4.4. Chipset > South Cluster Configuration
FeatureOptionsDescription
HD-Audio ConfigurationSubmenuHD-Audio Configuration Setting.
PCI Express ConfigurationSubmenuPCI Express Configuration Setting.
SATA DrivesSubmenuPressto select the SATA Device Configuration Setup option.
SSC ConfigurationSubmenuSSC Configuration Settings.
USB ConfigurationSubmenuUSB Configuration Settings.
Miscellaneous ConfigurationSubmenuEnable / Disable Misc. Feature.
# 7.4.4.1. Chipset > South Cluster Configuration > HD-Audio Configuration
FeatureOptionsDescription
HD-Audio ConfigurationInfo only
HD-Audio SupportDisable EnableSelect the target OS.
# 7.4.4.2. Chipset > South Cluster Configuration > PCI Express Configuration
FeatureOptionsDescription
PCI Express ConfigurationInfo only
PCIE Port assigned to LANInfo onlyDisplay PCIE Port assigned to LAN Information.
Complicace ModeDisable EnableComplicace Mode Enable / Disable.
PCIE Port 1-4 Configuration3 x1 PortNote: Default configuration for the lanes is 3 x1. Other configurations (1 x2, 2 x1 / 2 x2 / 4 x1) require a customized BIOS.
PCI ExpressRoot Port 1SubmenuControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port
PCI ExpressRoot Port 2SubmenuControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port
PCI ExpressRoot Port 3SubmenuControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port
PCI ExpressRoot Port 4SubmenuControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root portDisable: Disable PCIe root port
Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 1
FeatureOptionsDescription
PCI Express Root Port 1DisableEnableAutoControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.
ASPMDisableEnablePCI Express Active State Power Management settings
L1 SubstatesDisableL1.1L1.2L1.1 & L1.2PCI Express L1 Substates settings.
ACSDisableEnableEnable/Disable Access Control Services Extended Capability
URRDisableEnableCI Express Unsupported Request Reporting Enable/Disable
FERDisableEnablePCI Express Device Fatal Error Reporting Enable/Disable
NFERDisableEnablePCI Express Device Non-Fatal Error Reporting Enable/Disable
CERDisableEnablePCI Express Device Correctable Error Reporting Enable/Disable
CTODefault Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisablePCI Express Completion Timer TO Enable/Disable.
SEFEDisableEnableRoot PCI Express System Error on Fatal Error Enable/Disable
SENFEDisableEnableRoot PCI Express System Error on Non-Fatal Error Enable/Disable
SECEDisableEnableRoot PCI Express System Error on Correctable Error Enable/Disable
PME SCIDisableEnablePCI Express PME SCI Enable/Disable
Hot PlugDisableEnablePCI Express Hot Plug Enable/Disable
PCIe SpeedAutoGen1Gen2Configure PCIe Speed
Transmitter Half SwingDisableEnableTransmitter Half Swing Enable/Disable.
Extra Bus Reserved0Extra Bus Reserved (0-7) for bridges behind this Root Bridge
Reserved Memory10Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge
Reserved I/O4Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge
PCH PCIe LTR ConfigurationInfo only
PCH PCIE LTRDisableEnablePCH PCIE Latency Reporting Enable/Disable
Snoop Latency OverrideDisabledManualAutoSnoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.
Non Snoop Latency OverrideDisabledManualAutoNon Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow
PCIE LTR LockDisableEnablePCIE LTR Configuration Lock
PCIe Selection De0emphasisDisableEnableWhen the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB
Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 2
FeatureOptionsDescription
PCI Express Root Port 2DisableEnableAutoControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.
ASPMDisableEnablePCI Express Active State Power Management settings
L1 SubstatesDisableL1.1L1.2L1.1 & L1.2PCI Express L1 Substates settings.
ACSDisableEnableEnable/Disable Access Control Services Extended Capability
URRDisableEnableCI Express Unsupported Request Reporting Enable/Disable
FERDisableEnablePCI Express Device Fatal Error Reporting Enable/Disable
NFERDisableEnablePCI Express Device Non-Fatal Error Reporting Enable/Disable
CERDisableEnablePCI Express Device Correctable Error Reporting Enable/Disable
CTODefault Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisablePCI Express Completion Timer TO Enable/Disable.
SEFEDisableEnableRoot PCI Express System Error on Fatal Error Enable/Disable
SENFEDisableEnableRoot PCI Express System Error on Non-Fatal Error Enable/Disable
SECEDisableEnableRoot PCI Express System Error on Correctable Error Enable/Disable
PME SCIDisableEnablePCI Express PME SCI Enable/Disable
Hot PlugDisableEnablePCI Express Hot Plug Enable/Disable
PCIe SpeedAutoGen1Gen2Configure PCIe Speed
Transmitter Half SwingDisableEnableTransmitter Half Swing Enable/Disable.
Extra Bus Reserved0Extra Bus Reserved (0-7) for bridges behind this Root Bridge
Reserved Memory10Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge
Reserved I/O4Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge
PCH PCIe LTR ConfigurationInfo only
PCH PCIE LTRDisableEnablePCH PCIE Latency Reporting Enable/Disable
Snoop Latency OverrideDisabledManualAutoSnoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.
Non Snoop Latency OverrideDisabledManualAutoNon Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow
PCIE LTR LockDisableEnablePCIE LTR Configuration Lock
PCIe Selection De0emphasisDisableEnableWhen the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB
Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 3
FeatureOptionsDescription
PCI Express Root Port 3DisableEnableAutoControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.
ASPMDisableEnablePCI Express Active State Power Management settings
L1 SubstatesDisableL1.1L1.2L1.1 & L1.2PCI Express L1 Substates settings.
ACSDisableEnableEnable/Disable Access Control Services Extended Capability
URRDisableEnableCI Express Unsupported Request Reporting Enable/Disable
FERDisableEnablePCI Express Device Fatal Error Reporting Enable/Disable
NFERDisableEnablePCI Express Device Non-Fatal Error Reporting Enable/Disable
CERDisableEnablePCI Express Device Correctable Error Reporting Enable/Disable
CTODefault Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisablePCI Express Completion Timer TO Enable/Disable.
SEFEDisableEnableRoot PCI Express System Error on Fatal Error Enable/Disable
SENFEDisableEnableRoot PCI Express System Error on Non-Fatal Error Enable/Disable
SECEDisableEnableRoot PCI Express System Error on Correctable Error Enable/Disable
PME SCIDisableEnablePCI Express PME SCI Enable/Disable
Hot PlugDisableEnablePCI Express Hot Plug Enable/Disable
PCIe SpeedAutoGen1Gen2Configure PCIe Speed
Transmitter Half SwingDisableEnableTransmitter Half Swing Enable/Disable.
Extra Bus Reserved0Extra Bus Reserved (0-7) for bridges behind this Root Bridge
Reserved Memory10Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge
Reserved I/O4Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge
PCH PCIe LTR ConfigurationInfo only
PCH PCIE LTRDisableEnablePCH PCIE Latency Reporting Enable/Disable
Snoop Latency OverrideDisabledManualAutoSnoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.
Non Snoop Latency OverrideDisabledManualAutoNon Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow
PCIE LTR LockDisableEnablePCIE LTR Configuration Lock
PCIe Selection De0emphasisDisableEnableWhen the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB
Chipset > South Cluster Configuration > PCI Express Configuration > PCI Express Root Port 4
FeatureOptionsDescription
PCI Express Root Port 4DisableEnableAutoControl the PCI Express Root Port.AUTO: To disable unused root port automatically for the most optimum power savings.Enable: Enable PCIe root port.Disable: Disable PCIe root port.
ASPMDisableEnablePCI Express Active State Power Management settings
L1 SubstatesDisableL1.1L1.2L1.1 & L1.2PCI Express L1 Substates settings.
ACSDisableEnableEnable/Disable Access Control Services Extended Capability
URRDisableEnableCI Express Unsupported Request Reporting Enable/Disable
FERDisableEnablePCI Express Device Fatal Error Reporting Enable/Disable
NFERDisableEnablePCI Express Device Non-Fatal Error Reporting Enable/Disable
CERDisableEnablePCI Express Device Correctable Error Reporting Enable/Disable
CTODefault Setting16-15 ms65-210 ms260-900 ms1-3.5 sDisablePCI Express Completion Timer TO Enable/Disable.
SEFEDisableEnableRoot PCI Express System Error on Fatal Error Enable/Disable
SENFEDisableEnableRoot PCI Express System Error on Non-Fatal Error Enable/Disable
SECEDisableEnableRoot PCI Express System Error on Correctable Error Enable/Disable
PME SCIDisableEnablePCI Express PME SCI Enable/Disable
Hot PlugDisableEnablePCI Express Hot Plug Enable/Disable
PCIe SpeedAutoGen1Gen2Configure PCIe Speed
Transmitter Half SwingDisableEnableTransmitter Half Swing Enable/Disable.
Extra Bus Reserved0Extra Bus Reserved (0-7) for bridges behind this Root Bridge
Reserved Memory10Reserved Memory and Prefetchable Memory (1-20MB) Range for this Root Bridge
Reserved I/O4Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge
PCH PCIe LTR ConfigurationInfo only
PCH PCIE LTRDisableEnablePCH PCIE Latency Reporting Enable/Disable
Snoop Latency OverrideDisabledManualAutoSnoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.
Non Snoop Latency OverrideDisabledManualAutoNon Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow
PCIE LTR LockDisableEnablePCIE LTR Configuration Lock
PCIe Selection De0emphasisDisableEnableWhen the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.1b -3.5 dB0b -6 dB
7.4.4.3. Chipset > South Cluster Configuration > SATA Drives
FeatureOptionsDescription
SATA DrivesInfo only
Chipset- SATA Controller ConfigurationInfo only
Chipset SATADisable EnableEnables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port).
SATA Mode SelectionAHCIDetermines how SATA controller(s) operate.
SATA Interface SpeedGen1 Gen2 Gen3Select SATA Interface Speed, CHV A1 always with Gen Speed.
SATA Test ModeDisable EnableTest Mode Enable / Disable.
Aggressive LPM SupportDisable EnableEnable PCH to Aggressively enter link power state.
SATA0Info only
Software PreserveInfo only
Port 0Disabled EnabledEnable / Disable SATA Port
SATA Port 0 Hot Plug CapabilityDisabled EnabledIf enabled, SATA port will be reported as Hot Plug capable.
Configured as eSATAInfo onlyDisplay Configured as eSATA support.
Mechanical Presence SwitchDisabled EnabledControls reporting if this port has a Mechanical Presence Switch. Note. Request Hardware support.
Spin Up DeviceDisabled EnabledIf enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.
SATA Device TypeHard Disk Drive Solid State DriveIdentify the SATA port is connected to Solid State Drive or Hard Disk Drive.
SATA Port 0 DevSlpDisabled EnabledEnable/Disable SATA Port 0 DevSlp. Board rework for LP needed before enable.
DITO ConfigurationDisabled EnabledEnable/Disable DITO Configuration
DITO Value625DITO Value. Note. DITO Value can be accessed if DITO Configuration item must enable.
DM Value15DM Value. Note. DM Value can be accessed if DITO Configuration item must enable.
SATA1Info only
Software PreserveInfo only
Port 1Disabled EnabledEnable / Disable SATA Port
SATA Port 1 Hot Plug CapabilityDisabled EnabledIf enabled, SATA port will be reported as Hot Plug capable.
Configured as eSATAInfo onlyDisplay Configured as eSATA support.
Mechanical Presence SwitchDisabled EnabledControls reporting if this port has a Mechanical Presence Switch. Note. Request Hardware support.
Spin Up DeviceDisabled EnabledIf enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.
SATA Device TypeHard Disk Drive Solid State DriveIdentify the SATA port is connected to Solid State Drive or Hard Disk Drive.
SATA Port 1 DevSlpDisabled EnabledEnable/Disable SATA Port 1 DevSlp. Board rework for LP needed before enable.
DITO ConfigurationDisabled EnabledEnable/Disable DITO Configuration
DITO Value625DITO Value. Note. DITO Value can be accessed if DITO Configuration item must enable.
DM Value15DM Value. Note. DM Value can be accessed if DITO Configuration item must enable.
7.4.4.4. Chipset > South Cluster Configuration > SSC Configuration
FeatureOptionsDescription
SSC SD Card Support (D27:F0)DisabledEnabledEnable / Disable SCC SD Card Support.
SCC eMMC Support (D28:F0)DisabledEnabledEnable / Disable SCC eMMC Support.
eMMC Max SpeedHS400HS200DDR50Select the eMMC max Speed allowed.
SCC UFS Support (D29:F0)DisabledEnabledEnable / Disable UFS SDIO Support.
SCC SDIO Support (D30:F0)DisabledEnabledEnable / Disable SCC SDIO Support.
SD Card/GPIO ModeGPIO SD CardSelect SD Card or GPIO function.
7.4.4.5. Chipset > South Cluster Configuration > USB Configuration
FeatureOptionsDescription
XHCI Pre-Boot DriverDisabledEnabledEnable / Disable XHCI Pre-Boot Driver support.
XHCI ModeDisabledEnabledOnce disabled, XHCI controller would be function disabled, none of the USB devices are detectable and usable during boot and in OS. Do not disable it unless for debug purpose.
USB Port Disable OverrideDisabledEnabledSelectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.
7.4.4.6. Chipset > South Cluster Configuration > Miscellaneous Configuration
FeatureOptionsDescription
Miscellaneous ConfigurationInfo only
State After G3S0 StateS5 StateLast StateSpecify what state to go to when power is re-applied after a power failure (G3 state).S0 State: System will boot directly as soon as power applied.S5 State: System keeps in power-off state until power button is pressed.
Wake On LanDisabledEnabledEnable or Disable the Wake on Lan.
Spread Spectrum Clocking ConfigurationInfo only
DDR SSCInfo only
DDR SSC Selection TableInfo only
DDR Clock Bending Selection TableInfo only
HighSpeed SerialIO SSCInfo only
# 7.5. Security Menu # 7.5.1. Security > Password Description
FeatureOptionsDescription
Password DescriptionInfo only
Setup Administrator PasswordEnter PasswordSet Setup Administrator Password
User PasswordEnter PasswordSet User Password
Secure BootSubmenuCustomizable Secure Boot settings.
System ModeInfo only
Secure BootInfo only
Secure Boot ControlDisabledEnabledSecure Boot activated when Platform Key(PK) is enrolled, System mode is User / Deployed, and CSM function is disabled
# 7.6. Boot Menu # 7.6.1. Boot > Boot Configuration
FeatureOptionsDescription
Boot ConfigurationInfo only
Setup Prompt Timeout1Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.
Bootup NumLock StateOn OffSelect the keyboard Number state.
Ouiet BootDisabled EnabledSelect the keyboard NumLock state.
Fast BootDisabled EnabledEnable or Disable FastBoot features. Most probes are skipped to reduce time cost during boot.
New Boot Option PolicyDefault Place First Place LastControls the placement of newly detected UEFI boot option.
Boot Mode selectLEGACY UEFISelect boot mode LEGACY/UEFI
# 7.6.2. Boot > FIXED BOOT ORDER Priorities
FeatureOptionsDescription
Boot Option #1HardwareSet the system boot order.
Boot Option #2CD/DVDSet the system boot order.
Boot Option #3USB Hard DiskSet the system boot order.
Boot Option #4USB CD/DVDSet the system boot order.
Boot Option #5USB KeySet the system boot order.
Boot Option #6USB FloppySet the system boot order.
Boot Option #7USB LanSet the system boot order.
Boot Option #8NetworkSet the system boot order.
# 7.7. Save & Exit Menu # 7.7.1. Save and Exit
FeatureOptionsDescription
Save Changes and ExitExit system setup after saving the changes.
Discard Changes and ExitExit system setup without saving any changes.
Save Change and ResetReset the system after saving the changes.
Discard Changes and ResetReset system setup without saving any changes.
Save OptionsInfo only
Save ChangesSave Changes done so far to any of the setup options.
Save as User DefaultsSave the changes done so far as User Defaults.
Restore User DefaultsRestore the User Defaults to all the setup options.
Boot OverrideInfo only
This page intentionally left blank. # 8. BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Aptio Boot Flow While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions: • Security (SEC) – initial low-level initialization - Pre-EFI Initialization (PEI) – memory initialization $^{1}$ - Driver Execution Environment (DXE) – main hardware initialization $^{2}$ - Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, ...) # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints. $^{1}$ Analogous to “bootblock” functionality of legacy BIOS $^{2}$ Analogous to “POST” functionality in legacy BIOS # 8.1. Status Code Ranges
Status Code RangeDescription
0x01 – 0x0BSEC execution
0x0C – 0x0FSEC errors
0x10 – 0x2FPEI execution up to and including memory detection
0x30 – 0x4FPEI execution after memory detection
0x50 – 0x5FPEI errors
0x60 – 0x8FDXE execution up to BDS
0x90 – 0xCFBDS execution
0xD0 – 0xDFDXE errors
0xE0 – 0xE8S3 Resume (PEI)
0xE9 – 0xEFS3 Resume errors (PEI)
0xF0 – 0xF8Recovery (PEI)
0xF9 – 0xFFRecovery errors (PEI)
# 8.2. Standard Status Codes # 8.2.1. SEC Phase
Status CodeDescription
0x00Not used
Progress Codes
0x01Power on. Reset type detection (soft/hard).
0x02AP initialization before microcode loading
0x03North Bridge initialization before microcode loading
0x04South Bridge initialization before microcode loading
0x05OEM initialization before microcode loading
0x06Microcode loading
0x07AP initialization after microcode loading
0x08North Bridge initialization after microcode loading
0x09South Bridge initialization after microcode loading
0x0AOEM initialization after microcode loading
0x0BCache initialization
SEC Error Codes
0x0C – 0x0DReserved for future AMI SEC error codes
0x0EMicrocode not found
0x0FMicrocode not loaded
# 8.2.2. SEC Beep Codes None # 8.2.3. PEI Phase
Status CodeDescription
Progress Codes
0x10PEI Core is started
0x11Pre-memory CPU initialization is started
0x12Pre-memory CPU initialization (CPU module specific)
0x13Pre-memory CPU initialization (CPU module specific)
0x14Pre-memory CPU initialization (CPU module specific)
0x15Pre-memory North Bridge initialization is started
0x16Pre-Memory North Bridge initialization (North Bridge module specific)
0x17Pre-Memory North Bridge initialization (North Bridge module specific)
0x18Pre-Memory North Bridge initialization (North Bridge module specific)
0x19Pre-memory South Bridge initialization is started
0x1APre-memory South Bridge initialization (South Bridge module specific)
0x1BPre-memory South Bridge initialization (South Bridge module specific)
0x1CPre-memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2AOEM pre-memory initialization codes
0x2BMemory initialization. Serial Presence Detect (SPD) data reading
0x2CMemory initialization. Memory presence detection
0x2DMemory initialization. Programming memory timing information
0x2EMemory initialization. Configuring memory
0x2FMemory initialization (other).
0x30Reserved for ASL (see ASL Status Codes section below)
0x31Memory Installed
0x32CPU post-memory initialization is started
0x33CPU post-memory initialization. Cache initialization
0x34CPU post-memory initialization. Application Processor(s) (AP) initialization
0x35CPU post-memory initialization. Boot Strap Processor (BSP) selection
0x36CPU post-memory initialization. System Management Mode (SMM) initialization
0x37Post-Memory North Bridge initialization is started
0x38Post-Memory North Bridge initialization (North Bridge module specific)
0x39Post-Memory North Bridge initialization (North Bridge module specific)
0x3APost-Memory North Bridge initialization (North Bridge module specific)
0x3BPost-Memory South Bridge initialization is started
0x3CPost-Memory South Bridge initialization (South Bridge module specific)
0x3DPost-Memory South Bridge initialization (South Bridge module specific)
0x3EPost-Memory South Bridge initialization (South Bridge module specific)
0x3F-0x4EOEM post memory initialization codes
0x4FDXE IPL is started
PEI Error Codes
0x50Memory initialization error. Invalid memory type or incompatible memory speed
0x51Memory initialization error. SPD reading has failed
0x52Memory initialization error. Invalid memory size or memory modules do not match.
0x53Memory initialization error. No usable memory detected
0x54Unspecified memory initialization error.
0x55Memory not installed
0x56Invalid CPU type or Speed
0x57CPU mismatch
0x58CPU self test failed or possible CPU cache error
0x59CPU micro-code is not found or micro-code update is failed
0x5AInternal CPU error
0x5Breset PPI is not available
0x5C-0x5FReserved for future AMI error codes
S3 Resume Progress Codes
0xE0S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
0xE1S3 Boot Script execution
0xE2Video repost
0xE3OS S3 wake vector call
0xE4-0xE7Reserved for future AMI progress codes
S3 Resume Error Codes
0xE8S3 Resume Failed
0xE9S3 Resume PPI not Found
0xEAS3 Resume Boot Script Error
0xEBS3 OS Wake Error
0xEC-0xEFReserved for future AMI error codes
Recovery Progress Codes
0xF0Recovery condition triggered by firmware (Auto recovery)
0xF1Recovery condition triggered by user (Forced recovery)
0xF2Recovery process started
0xF3Recovery firmware image is found
0xF4Recovery firmware image is loaded
0xF5-0xF7Reserved for future AMI progress codes
Recovery Error Codes
0xF8Recovery PPI is not available
0xF9Recovery capsule is not found
0xFAInvalid recovery capsule
0xFB – 0xFFReserved for future AMI error codes
8.2.4. PEI Beep Codes
# of BeepsDescription
1Memory not Installed
1Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
2Recovery started
3DXEIPL was not found
3DXE Core Firmware Volume was not found
4Recovery failed
4S3 Resume failed
7Reset PPI is not available
# 8.2.5. DXE Status Codes
Status CodeDescription
0x60DXE Core is started
0x61NVRAM initialization
0x62Installation of the South Bridge Runtime Services
0x63CPU DXE initialization is started
0x64CPU DXE initialization (CPU module specific)
0x65CPU DXE initialization (CPU module specific)
0x66CPU DXE initialization (CPU module specific)
0x67CPU DXE initialization (CPU module specific)
0x68PCI host bridge initialization
0x69North Bridge DXE initialization is started
0x6ANorth Bridge DXE SMM initialization is started
0x6BNorth Bridge DXE initialization (North Bridge module specific)
0x6CNorth Bridge DXE initialization (North Bridge module specific)
0x6DNorth Bridge DXE initialization (North Bridge module specific)
0x6ENorth Bridge DXE initialization (North Bridge module specific)
0x6FNorth Bridge DXE initialization (North Bridge module specific)
0x70South Bridge DXE initialization is started
0x71South Bridge DXE SMM initialization is started
0x72South Bridge devices initialization
0x73South Bridge DXE Initialization (South Bridge module specific)
0x74South Bridge DXE Initialization (South Bridge module specific)
0x75South Bridge DXE Initialization (South Bridge module specific)
0x76South Bridge DXE Initialization (South Bridge module specific)
0x77South Bridge DXE Initialization (South Bridge module specific)
0x78ACPI module initialization
0x79CSM initialization
0x7A – 0x7FReserved for future AMI DXE codes
0x80 – 0x8FOEM DXE initialization codes
0x90Boot Device Selection (BDS) phase is started
0x91Driver connecting is started
0x92PCI Bus initialization is started
0x93PCI Bus Hot Plug Controller Initialization
0x94PCI Bus Enumeration
0x95PCI Bus Request Resources
0x96PCI Bus Assign Resources
0x97Console Output devices connect
0x98Console input devices connect
0x99Super IO Initialization
0x9AUSB initialization is started
0x9BUSB Reset
0x9CUSB Detect
0x9DUSB Enable
0x9E – 0x9FReserved for future AMI codes
0xA0IDE initialization is started
0xA1IDE Reset
0xA2IDE Detect
0xA3IDE Enable
0xA4SCSI initialization is started
0xA5SCSI Reset
0xA6SCSI Detect
0xA7SCSI Enable
0xA8Setup Verifying Password
0xA9Start of Setup
0xAAReserved for ASL (see ASL Status Codes section below)
0xABSetup Input Wait
0xACReserved for ASL (see ASL Status Codes section below)
0xADReady To Boot event
0xAELegacy Boot event
0xAFExit Boot Services event
0xB0Runtime Set Virtual Address MAP Begin
0xB1Runtime Set Virtual Address MAP End
0xB2Legacy Option ROM Initialization
0xB3System Reset
0xB4USB hot plug
0xB5PCI bus hot plug
0xB6Clean-up of NVRAM
0xB7Configuration Reset (reset of NVRAM settings)
0xB8 – 0xBFReserved for future AMI codes
0xC0 – 0xCFOEM BDS initialization codes
DXE Error Codes
0xD0CPU initialization error
0xD1North Bridge initialization error
0xD2South Bridge initialization error
0xD3Some of the Architectural Protocols are not available
0xD4PCI resource allocation error. Out of Resources
0xD5No Space for Legacy Option ROM
0xD6No Console Output Devices are found
0xD7No Console Input Devices are found
0xD8Invalid password
0xD9Error loading Boot Option (LoadImage returned error)
0xDABoot Option is failed (StartImage returned error)
0xDBFlash update is failed
0xDCReset protocol is not available
# 8.2.6. DXE Beep Codes
# of BeepsDescription
1Invalid password
4Some of the Architectural Protocols are not available
5No Console Output Devices are found
5No Console Input Devices are found
6Flash update is failed
7Reset protocol is not available
8Platform PCI resource requirements cannot be met
# 8.2.7. ACPI/ASL Checkpoint
Status CodeDescription
0x01System is entering S1 sleep state
0x02System is entering S2 sleep state
0x03System is entering S3 sleep state
0x04System is entering S4 sleep state
0x05System is entering S5 sleep state
0x10System is waking up from the S1 sleep state
0x20System is waking up from the S2 sleep state
0x30System is waking up from the S3 sleep state
0x40System is waking up from the S4 sleep state
0xACSystem has transitioned into ACPI mode. Interrupt controller is in PIC mode.
0xAASystem has transitioned into ACPI mode. Interrupt controller is in APIC mode.
# 8.3. OEM-Reserved Checkpoint Ranges
Status CodeDescription
0x05OEM SEC initialization before microcode loading
0x0AOEM SEC initialization after microcode loading
0x1D – 0x2AOEM pre-memory initialization codes
0x3F – 0x4EOEM PEI post memory initialization codes
0x80 – 0x8FOEM DXE initialization codes
0xC0 – 0xCFOEM BDS initialization codes
This page intentionally left blank. # 9. Mechanical Information # 9.1. Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components. # Tyco 3-1827253-6 # Foxconn QT002206-2131-3H - 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm. - This connector can be used with 5 mm through-hole standoffs (SMT type). ![Exterior view of a multi-pin electronic component with metallic pins and slots (no text or symbols visible)](.cexpress-al-50-1j068-1020-12/41edd329e09e2e90b931897874037d5b6f268a8958b393763e0de3e58d79d285.jpg) # Tyco 3-6318491-6 # Foxconn QT002206-4141-3H - 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm. - This connector can be used with 8 mm through-hole standoffs (SMT type). ![Exterior view of a rectangular electronic component with multiple slots and mounting holes (no text or symbols visible)](.cexpress-al-50-1j068-1020-12/ed0457809d40072a5bced07de73ef798d190ce729705b0d0a7f037475e281ed5.jpg) # Common Specifications • Current capacity: 0.5A per pin • Rated voltage: 50 VAC • Insulation resistance: 100M or greater @ 500 VDC • Temperature rating: $-40^{\circ}C \sim 85^{\circ}C$ • UL certification (ECBT2.E28476) • Copper alloy (contacts) • Housing: thermo-plastic molded compound (L.C.P.) # 9.2. Thermal Solution # 9.2.1. Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules. # 9.2.2. Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements. # 9.2.3. Installation Install a heat spreader or heat sink using the following instructions. Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module. ![Close-up of hands installing a green printed circuit board with multiple microcontroller chips (no visible text or symbols)](.cexpress-al-50-1j068-1020-12/92a8a892e952527ddf8dbf91691acee20686ac91e05f487178432606780ad834.jpg) Step 2: Remove the protective membranes from the thermal pads. ![Close-up of a green leaf being sampled from tweezers into a white rectangular sample (no text or symbols visible)](.cexpress-al-50-1j068-1020-12/18eefb3fac8ff3408823b07bfe5616470ae06d459cde9fc883dffd3917fc4f8c.jpg) Step 3: Assemble the heatsink onto the COM Express module. Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. ![Close-up of a green printed circuit board with soldering and a red-circled component, no visible text or symbols.](.cexpress-al-50-1j068-1020-12/0f2619031f87ec7756c2ac338de1148c89dde3b727359395009c2efae599e27e.jpg) Step 4: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. ![Close-up of gloved hands installing a green printed circuit board with visible components and connectors (no text or symbols)](.cexpress-al-50-1j068-1020-12/61bcd5276775c9c89513f08da738389a679f9206b0785b230f833f312a8718b3.jpg) Then press down on the module until it is firmly seated on the carrier board. Step 5: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side. ![Close-up of a green printed circuit board with visible traces and solder points, no text or symbols present.](.cexpress-al-50-1j068-1020-12/7fec0a134c6706d9581383b3e6a742eb865f4f0887d39f751d6ac81d430d41ad.jpg) Step 6: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown. ![Close-up of a computer motherboard with a hand holding a CPU socket and cooling fan (no visible text or symbols)](.cexpress-al-50-1j068-1020-12/0ae95d7c452ff16282ac51af35f8413b2abe3ed5f03b0ab2f087e23b13a6d722.jpg) # 9.3. Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs. Top Mounting with 5 mm connectors ![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n5 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.cexpress-al-50-1j068-1020-12/b85a1b2f631267c051449062086bde49b63ee4cbb5731c9d47de16c2141c55bf.jpg) Bottom Mounting with 5 mm connectors ![2 mm heatspreader with\n9 mm threaded standoffs\nM2.5\nØ50\nØ27\nCOM Express Module ~ 2 mm\nØ27\nØ55\nØ38\n5 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 14 mm\nwith spring / washer](.cexpress-al-50-1j068-1020-12/ed3b9c0cad04c594a1d699bdaa6e0fabe3fa2bacf2e6fc9f67871bbd32b5d60a.jpg) Top Mounting with 8 mm connectors ![M2.5 : 18 mm\nwith spring / washer\n2 mm heatsprader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n8 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm](.cexpress-al-50-1j068-1020-12/a0a8238551b8d97040182a88d6785812007615057f4a190804544fd92a6229dd.jpg) Bottom Mounting with 8 mm connectors ![2 mm heatsprader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n8 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 16 mm\nwith spring / washer](.cexpress-al-50-1j068-1020-12/72214cb431615561f080817405dbfc302db042d7a0f41818ddec55e5d5c32599.jpg) Figure 6: COM Express Mounting Methods # 9.4. Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.
5mm through-hole standoff (SMT type)P/N: 33-72000-0050<img src="images/219cf5c717dfb3fe6c678729702fd1d06a89fc936075124a05dd4444057d9ff6.jpg"/>5mm threaded standoff (DIP type)P/N: 33-72016-0050<img src="images/67bc22fa21d1074b5eafd2c3a1b4f7fe4ea1a0e14703a0e9aedb47c94ac17dfd.jpg"/>
8mm through-hole standoff (SMT type)P/N: 33-72000-0080<img src="images/d27b160b8f4e2ebb1de2231d985d42b2f083d7439e652e6288b4822656574599.jpg"/>8mm threaded standoff (DIP type)P/N: 33-72015-0050<img src="images/c77f216b9ddae710390fc3b9ccbfe323e3b1da08b7e780847935bf288d170330.jpg"/>
Figure 7: COM Express Standoff Types # Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. - Please read these safety instructions carefully. - Please keep this User's Manual for later reference. - Read the specifications section of this manual for detailed information on the operating environment of this equipment. - When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables. • To avoid electrical shock and/or damage to equipment: - Keep equipment away from water or liquid sources. - Keep equipment away from high heat or high humidity. - Keep equipment properly ventilated (do not block or cover ventilation openings). ■ Make sure to use recommended voltage and power source settings. ■ Always install and operate equipment near an easily accessible electrical socket-outlet. - Secure the power cord (do not place any object on/over the power cord). - Only install/attach and operate equipment on stable surfaces and/or recommended mountings. - If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. \- Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. # Getting Service Ask an Expert: http://askanexpert.adlinktech.com # ADLINK Technology, Inc.
Address:9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan
Tel:+886-2-8226-5877
Fax:+886-2-8226-5717
Email:service@adlinktech.com
# Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Straße 11 D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: germany@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. [🔗 Link to the original document](.cexpress-al-50-1j068-1020-12/cexpress-al-50-1j068-1020-12.pdf)