# c Exp ress-AR U se r’ s G u i d e AMDD ![Close-up of a green printed circuit board with visible components and gold contacts (no readable text or symbols)](.cexpress-ar-50m-00014-1020-12/303dbe618705a6f12b3813514dce4ee231fe37049ef8daec7412f84e587eaabc.jpg) Revisio n H isto ry

Revision	Description	Date	Author
1.0	Initial release	2021-05-17
1.1	Update specifications, AB/CD Connector Signal Descriptions	2021-08-03
1.2	Remove Yocto Linux support	2021-08-31

# Preface # D isc l a i m e r I n fo rm at i o n i n t h i s d o c u m e nt i s p rovi d ed i n co n n ect i o n wit h A D LI N K p ro d u cts . N o l i ce n se, ex p ress o r i m p l i ed , by esto p p e l o r ot h e rwi se, to a ny i nte l l ect u a l p ro p e rty ri g hts i s g ra nted by t h i s d o c u m e nt. Exce pt a s p rovi d ed i n A D LI N K´s Te rm s a n d C o n d it i o n s of Sa l e fo r s u c h p rod u cts, A D LI N K a ss u m es n o l i a b i l ity wh atso eve r, a n d A D LI N K d i sc l a i m s a ny ex p res s o r i m p l i ed wa rra nty, re l at i n g to sa l e a n d/o r u se of A D LI N K p ro d u cts i n c l u d i n g l i a b i l i ty o r wa r ra n t i e s re l a t i n g to fi t n e s s fo r a p a rt i c u l a r p u r p o s e, m e rc h a n ta b i l i ty, o r i n fr i n g e m e n t of a n y p a te n t, c o py r i g h t o r ot h e r i n te l l e ct u a l p ro p e rty ri g ht. If yo u i nte n d to u se A D LI N K p ro d u cts i n o r a s m ed i ca l d evi ces, yo u a re so l e ly res p o n s i b l e fo r a l l req u i red reg u l ato ry co m p l i a n ce, i n c l u d i n g , wit h o u t l i m itati o n, Tit l e 2 1 of t h e C F R (U S), D i rective 2 007/47/EC ( E U), a n d ISO 1 348 5 & 1497 1, if a ny. A D LI N K m ay m a ke c h a n g es to s pec ifi cati o n s a n d p rod u ct d e s c ri pt i o n s a t a ny t i m e, wi t h o u t n ot i c e . # Envi ron menta l Responsi bi l ity A D LI N K i s c o m m i tte d to fu l fi l i ts s o c i a l re s p o n s i b i l i ty to g l o b a l e nvi ro n m e n ta l p re s e rva t i o n t h ro u g h c o m p l i a n c e w i t h t h e E u ro p ea n U n i o n ' s Re st ri ct i o n of H aza rd o u s S u b sta n ces ( Ro H S) d i rect ive a n d Wa ste E l ect ri ca l a n d E l ect ro n i c Eq u i p m e nt (W E E E) d i rect ive . E nvi ro n m e nta l p rotect i o n i s a to p p ri o rity fo r A D LI N K. We h ave e n fo rced m ea s u res to e n s u re t h at o u r p ro d u cts, m a n u fa ct u ri n g p ro cesses, co m p o n e nts, a n d raw m ate ri a l s h ave a s l itt l e i m pa ct o n t h e e nvi ro n m e nt a s p o ss i b l e . Wh e n p ro d u cts a re at t h e i r e n d of l ife, o u r c u sto m e rs a re e n co u ra g ed to d i s p o se of t h e m i n a cco rd a n ce wit h t h e p ro d u ct d i s po sa l a n d/o r recove ry p rog ra m s p resc ri bed by t h e i r n ati o n o r co m pa ny. ![This image displays a standard caution symbol: a yellow equilateral triangle with a thick black outline. Centered inside the triangle is a black exclamation point. The background surrounding the symbol is white.](.cexpress-ar-50m-00014-1020-12/0251382bf0aa0a0f373cc4f5de262face2cce0a70f151ead4c1bb6907e4ece85.jpg) Ca l ifo rn ia Pro positio n 6 5 Wa rn i n g : T h i s p rod u ct ca n expo se yo u to c h e m i ca l s i n c l u d i n g a c ryl a m i d e, a rse n i c, be nze n e, ca d m i u m, T ri s (1, 3 - d i c h l o ro - 2 - p ro pyl) p h os p h ate (T DC P P), 1,4 - D i oxa n e, fo rm a l d e hyd e, l ea d, D E H P, styre n e, DI N P, B B P, PVC, a n d vi nyl m ate ri a l s, wh i c h a re kn own to t h e State of Ca l ifo rn i a to ca u se ca n ce r, a n d a c ryl a m i d e, be nze n e, ca d m i u m, l ea d , m e rc u ry, p ht h a l ates, to l u e n e, D E H P, DI D P, D n H P, D B P, B B P, PVC, a n d vi nyl m ate ri a l s, wh i c h a re kn own to t h e Sta te of C a l i fo rn i a to ca u se b i rt h d efects o r ot h e r re p ro d u ct ive h a rm . Fo r m o re i nfo rm ati o n g o to www. P6 5Wa rn i n g s. ca . g ov. ![The image displays a black and white line drawing of a wheeled trash bin with a lid. A large, thick 'X' is superimposed over the bin, crossing it out. Below the bin, there is a solid black rectangular block.](.cexpress-ar-50m-00014-1020-12/203b14a8fee79d1ed0a3f5cff5ada06abfeb83726fc2d83a31db142fe3c2027b.jpg) # Tradema rks P rod u ct n a m es m e nti o n ed h e re i n a re u sed fo r i d e ntifi cati o n p u rpo ses o n ly a n d m ay be t ra d e m a rks / reg i ste red t ra d e m a rks of res pective co m pa n i es. # Copyrig ht © 202 1 ADLIN K Tech nology Incorporated T h i s d oc u m e nt co nta i n s p ro p ri eta ry i nfo rm ati o n p rotected by co pyri g ht. Al l ri g hts a re rese rved . N o pa rt of t h i s m a n u a l m ay be re p rod u ced by a ny m ec h a n i ca l , e l ect ro n i c, o r ot h e r m ea n s i n a ny fo r m wit h o u t p ri o r writte n p e rm i ss i o n of t h e m a n u fa ct u re r. # Safety Instru ctio ns Fo r u se r sa fety, p l ea se rea d a n d fo l l ow a l l I n st ru ct i o n s, Wa rn i ng s, Ca utio n s, a n d N otes m a rked i n t h i s m a n u a l a n d o n t h e a sso c i ated eq u i p m e nt b efo re h a n d l i n g/o pe rati n g t h e eq u i p m e nt. Re a d t h e s e s a fety i n st ru ct i o n s c a refu l l y. Kee p t h i s m a n u a l fo r fu t u re refe re n ce . • Rea d t h e s p ec ifi cat i o n s sect i o n of t h i s m a n u a l fo r d eta i l ed i n fo rm at i o n o n t h e o p e rat i n g e nvi ro n m e nt of t h i s eq u i p m e nt. • Tu rn off powe r a n d u n p l u g a ny powe r co rd s/ca b l es wh e n i n sta l l i n g/m o u nti n g o r u n - i n sta l l i n g/re m ovi n g eq u i p m e nt. • To avo i d e l ect ri ca l s h oc k a n d/o r d a m a g e to eq u i p m e nt: Kee p eq u i p m e nt away fro m wate r o r l i q u i d so u rces; Kee p eq u i p m e nt away fro m h i g h h eat o r h i g h h u m i d ity; • Kee p eq u i p m e nt p ro pe rly ve nti l ated (d o n ot b l oc k o r cove r ve nti l ati o n o pe n i n g s); • M a ke s u re to u se reco m m e n d ed vo l ta g e a n d powe r so u rce setti n g s; • Always i n sta l l a n d o p e rate eq u i p m e nt n ea r a n ea s i ly a ccess i b l e e l ect ri ca l so c ket o u t l et; • Sec u re t h e powe r co rd (d o n ot p l a ce a ny o bj ect o n/ove r t h e powe r co rd); • O n ly i n sta l l/atta c h a n d o pe rate eq u i p m e nt o n sta b l e s u rfa ces a n d/o r reco m m e n d ed m o u nti n g s; • If t h e eq u i p m e nt wi l l n ot be u sed fo r l o n g pe ri od s of ti m e, tu rn off t h e p owe r so u rce a n d u n p l u g t h e eq u i p m e nt. # Conventions T h e fo l l owi n g co nve nti o n s m ay be u sed t h ro u g h o u t t h i s m a n u a l , d e n oti n g s pec i a l l eve l s of i nfo rm ati o n ![The image shows a simple icon of a red document. It features a thick red outline of a rectangular page with a slightly curled bottom-right corner. Inside the outline, there are two horizontal red bars of different lengths, centered to represent lines of text.](.cexpress-ar-50m-00014-1020-12/ffccac95c4071a7983c23c93830f64ff44333dbf17b6a5d47050906f952ec15b.jpg) N ote : T h i s i n fo r m a t i o n a d d s c l a ri ty o r s p e c i fi c s to text a n d i l l u st ra t i o n s . ![The image displays a standard warning symbol. It consists of a yellow triangle with a thick black outline. Inside the triangle, centered, is a black exclamation point.](.cexpress-ar-50m-00014-1020-12/80bfb0776d28817e70b262ba6916ad397104dd2efe129e5cbc241d207f468ce5.jpg) Ca utio n : T h i s i n fo rm at i o n i n d i cates t h e p o s s i b i l ity of m i n o r p hys i ca l i nj u ry, co m p o n e nt d a m a g e, d ata l o ss, a n d/o r p ro g ra m co rru pt i o n . ![The image displays a red triangular warning symbol with rounded corners. Inside the triangle is a white exclamation point. The background is white.](.cexpress-ar-50m-00014-1020-12/1cc0e8bb4445a7086171b819805343f93da44ad84a4229952b3a8406a3cf90f4.jpg) Wa rn i ng : T h i s i nfo rm ati o n wa rn s of po ss i b l e se ri o u s p hys i ca l i nj u ry, co m po n e nt d a m a g e, d ata l o ss, a n d/o r p rog ra m co rru pti o n . # Getti ng Service Ask a n Expert: htt p ://a s ka n expe rt.a d l i n ktec h .co m # ADLIN K Tech nology, Inc. N o . 66, H u aya 1 st Rd ., G u i s h a n D i st ri ct, Ta oyu a n C ity 3 3 34 1 1, Ta iwa n Te l : + 886 - 3 - 2 1 6 - 5088 Fax: + 886 - 3 - 3 2 8 - 5706 E m a i l : se rvi ce @ a d l i n ktec h .co m # Am pro ADLIN K Tech nology, Inc. 64 5 0 Vi a De l O ro Sa n J ose CA 9 5 1 19 - 1208 U SA Te l : + 1 -408 - 3 60 -0200 To l l F ree: + 1 - 800 - 9 66 - 5 2 00 (U SA o n ly) Fax: + 1 -408 - 600 - 1 189 E m a i l : i nfo @ a d l i n ktec h . co m # AD LIN K Tech nology (Chi na) Co., Ltd. 3 00 Fa n g C h u n Rd ., Zh a n gj i a n g H i -Tec h Pa rk, P u d o n g N ew Area, S h a n g h a i, 2 0 1 2 0 3, C h i n a Te l : + 86 - 2 1 - 5 1 3 2 - 8988 Fax: + 8 6 - 2 1 - 5 1 3 2 - 3 5 88 E m a i l : m a rket @ a d l i n ktec h .co m # ADLIN K Technology GmbH H a n s -T h o m a - St ra sse 1 1, D - 68 1 6 3 M a n n h e i m, G e rm a ny Te l : + 49 - 62 1 -43 2 14-0 Fax: + 49 - 62 1 43 2 14- 3 0 E m a i l : e m ea @ a d l i n ktec h .co m P l ea se vi s it t h e C o nta ct pa g e at www. a d l i n ktec h . co m fo r i n fo rm at i o n o n h ow to co nta ct t h e A D LI N K reg i o n a l offi ce n ea rest yo u . # Ta ble of Contents Revi s i o n H i sto ry. . . . P refa c e . . L i st of F i g u re s . . 9 1 . I n t ro d u ct i o n . . . 10 2 . S p e c i fi ca t i o n s . . 1 2 . 1 . C o re Syste m . . 1 1 2 . 2 . V i d e o . . . . . . . 1 2 2 . 2 . 1 D i s p l ay I n te rfa c e S u p p o rt . . . 1 2 2 . 3 . A u d i o . . . . . . 1 3 2 .4. Expa n s i o n B u s ses . . . 1 3 2 . 5 . Et h e r n et . . . 1 3 2 . 6 . M u l t i I/O a n d S t o ra g e . . . 14 2 . 7 . T ru sted P l atfo rm M o d u l e (T P M ) . . 1 5 2 . 8 . S E M A B oa rd co n t ro l l e r . . . . . 1 5 2 .9 . De b u g . . . 1 5 2 . 1 0 . P owe r . . . . . . . 1 5 2 . 1 1 . M ec h a n i ca l a n d E nvi ro n m e nta l . . 1 6 3 . B l oc k D i a g ra m . . 17 4 . P i n o u t a n d S i g n a l D e s c r i pt i o n s . . . . . . . . . 1 8 4. 1 . P i n S u m m a ry . . . . 1 8 4. 2 . S i g n a l Te rm i n o l o gy D esc ri pt i o n s . . . 2 3 4. 3 . A B C o n n ecto r S i g n a l Desc ri pt i o n s . . . . 2 4 4 . 3 . 1 A u d i o . . . 24 4. 3 . 2 An a l og VGA. . . . 2 5 4 . 3 . 3 LV D S o r e D P . . . . . 2 6 4. 3 .4 G i g a b i t Et h e r n et . . . . 2 9 4. 3 . 5 SATA . . . . . . 3 0 4 . 3 . 6 P CI Ex p re s s . . 3 1 4 . 3 . 7 L P C b u s . . . 3 3 4. 3 . 8 U S B . . . 34 4. 3 .9 S PI B u s ( BIO S o n l y) . . . 3 6 4 . 3 . 1 0 M i s c e l l a n e o u s . . . . . 3 7 4. 3 . 1 1 S M B u s . . . . 3 8 4. 3 . 12 I2 C b u s . . 4. 3 . 1 3 G e n e ra l P u rpose I/O (G PIO) . . . 3 9 4 . 3 . 14 S e ri a l I n te rfa c e S i g n a l s . . . . 3 9 4. 3 . 1 5 Powe r a n d Syste m M a n a g e m e nt . . . . . . 4 0 4. 3 . 1 6 Powe r a n d G ro u n d . . . . 4 1 4.4. C D C o n n ecto r S i g n a l Desc ri pt i o n s . . . . . . 4 2 4.4. 1 U S B 3 . 0 Exte n s i o n s . . . . . . 4 2 4 .4 . 2 P CI Ex p re s s . . . . . . 4 3 4 .4 . 3 D D I 1 P o rt . . . . . . . 4 5 4 .4 .4 D D I 2 P o rt . . . . . . . 4 8 4 .4 . 5 D DI 3 P o rt . . 5 1 4.4. 6 PCIe G ra p h i cs Po rt ( P EG) . . 54 4.4.7 M od u l e Type Defi n iti o n . . . 5 6 4.4. 8 Powe r a n d G ro u n d . . 5 7 5 . Ad d i t i o n a l F e a t u re s . . . . . . . . . 5 8 5 . 1 . De b u g Co n n ecto r . . . 5 9 5 . 2 . Sta t u s L E D s . . . 60 5 . 3 . Exce pti o n C od es . . . 6 1 5 .4. Fa n C o n n ecto r . . . . . . 6 2 5 . 5 . BIO S D efa u l t Reset B u tto n . . . 6 3 5 . 6 . BIO S B o ot S e l ect. . . 64 6. BIO S C h ec kpo i nts, Bee p Cod es . . . 6 5 7 . S o ftwa re S u p p o rt . . . . . . . . . . . . . 6 6 7 . 1 . O p e ra t i n g Syste m s . . . 66 8 . M ec h a n i ca l a n d Th e rm a l . . . . 6 7 8 . 1 . M od u l e D i m e n s i o n s . . 67 8 . 2 . T h e rm a l S o l u t i o n s . . 68 8 . 2 . 1 H eats p rea d e r: H TS . . 68 8 . 2 . 2 H eats i n k: T H S . . . . . . . 6 9 8 . 2 . 3 H eats i n k H i g h P rofi l e: T H S H . . 70 8 . 2 .4 H eats i n k wit h Fa n : T H S F . . . . 7 1 # List of F ig u res F i g u re 1 – M od u l e fu n ct i o n d i a g ra m . . . . . 17 F i g u re 2 - M o d u l e re a r s i d e row a n d p i n n u m b e r i n g . . . . . . . . . . . . . 1 8 F i g u re 3 – M o d u l e fea t u re l o ca t i o n s . . . . . 5 8 F i g u re 4 – c Exp ress -AR a n d De b u g M od u l e . . . 5 9 F i g u re 5 – M od u l e m ec h a n i ca l d i m e n s i o n s . . . . 6 7 F i g u re 6 – H eats p rea d e r H TS . . . 68 F i g u re 7 – H eats i n k T H S . . . 69 F i g u re 8 – H ea ts i n k H i g h P rofi l e : T H S H . . . . 7 0 F i g u re 9 – H ea ts i n k wit h Fa n : T H S F . . . 7 1 # 1. Introd uction ![The image displays a red triangular warning sign with a white exclamation mark in the center.](.cexpress-ar-50m-00014-1020-12/a3fd58b4a1ee99e07016dacf7550facf4407cec50a3475399b14d9f4fdf33972.jpg) Wa rn i ng : t h i s i s a n EA (ea rly ava i l a b l e) e n g i n ee ri n g m a n u a l , m ea n i n g co nte nts m ay n ot p ro p e rly refl ect t h e a ct u a l o r fi n a l ve rs i o n of t h i s p rod u ct Th e c Exp ress -AR i s t h e fi rst CO M Exp ress ® CO M .0 R3 .0 Co m pa ct S ize Type 6 m od u l e ba sed o n Octa - co re (8 co re) AM D ® N ew G e n e rati o n Ryze n ™ E m bed d ed V- Se ri es SoC (fo rm e rly “ Ryze n V2 000”) wit h u p to 1 6 t h rea d s a n d a n i m p ress ive tu rbo boost u p to 4.2 5 G H z. Co m pa red to ea rl i e r g e n e rati o n, t h e a d d it i o n a l co res co m b i n ed wit h A M D ’ s Ze n 2 a rc h itect u re res u l t i n d o u b l e t h e p e rfo rm a n ce - p e r-watt effi c i e n cy. T h e c Ex p res s -A R a l s o feat u re a u pg ra d e h i g h pe rfo rm a n ce g ra p h i cs co re ca l l ed A M D ® Ra d eo n ™ wit h fa ste r freq u e n cy a n d c l oc ki n g . Typ i ca l i n d u st ri es, i n n eed of s u c h h i g h pe rfo rm a n ce c h a ra cte ri sti cs, a re u l t ra so u n d i m a g e p rocess i n g , 4 K h i g h s peed vi d eo e n cod i n g a n d st rea m i n g , g a m i n g , AI i nfe re n c i n g at t h e Ed g e. Th e c Exp ress -A R s u p po rts m axi m u m 64G B D D R4 3 2 00 M T/s m e m o ry ca pa c ity a n d s u p po rt ECC m e m o ry e rro r co rrecti o n ba sed o n se l ected S KU s. C o m b i n ed wit h a co n fi g u ra b l e T D P to 1 0 watts wh i l e st i l l s u p p o rt 8 - co re/6 - co re m a ke fa n l ess d es i g n a c h i eva b l e a n d we l l s u ited fo r m i ss i o n c rit i ca l o r ru g g ed a p p l i cat i o n s . I nteg rated u pg ra d e A M D ® Ra d eo n ™ G ra p h i cs i n c l u d es featu res s u c h a s O pe n G L 4. 6 a n d E S 3 .x, D i rectX 1 2, O pe n C L 2 . 1/2 .0/1 . 2, n ew g e n e rati o n m u lti m ed i a e n g i n e, VC N 2 .2, s u p po rts fo r H .2 6 5/H EVC 10 - b it h a rdwa re e n cod e/d ecod e, VP9 10 - b it h a rdwa re d ecod e. I n a d d iti o n, n ew g e n e rati o n d i s p l ay e n g i n e, DC N 2 . 1, s u p po rt m axi m u m fo u r i n d e pe n d e nt d i s p l ay o ut p uts i n c l u d e LVD S a n d t h ree D DI po rts s u p po rti n g H D M I/DVI/D i s p l ay Po rt a n d e D P/VGA a s a b u i l d o pti o n . I n p u t/o u t p u t featu res i n c l u d e u p to e i g ht PCIe G e n 3 l a n es (t h ro u g h a PCIe switc h, p roj ect ba s i s s u p po rt) a n d o n e PCIe G e n 3 x8 l a n es t h at ca n be u sed fo r N V M e S S D, a l l owi n g a p p l i cat i o n s a cces s to t h e h i g h est s p eed sto ra g e so l u t i o n s, a s we l l a s a s i n g l e o n b oa rd u p to 2 . 5 G i g a b it Et h e rn et p o rt s u p po rti n g Ti m e Se n s itive N etwo rk (TS N ), fo u r U S B 3 .2 po rts, fo u r U S B 2 .0 po rts, two SATA 6 G b/s po rts. S u p po rt i s p rovi d ed fo r S M B u s a n d I2 C . Th e m od u l e i s eq u i p ped wit h S PI A M I E FI BIO S wit h C M O S ba c ku p, s u p po rti n g e m bed d ed featu res s u c h a s re m ote co n so l e, h a rdwa re m o n ito r, a n d watc h d og t i m e r. # 2. Specifications # 2 . 1. Co re System # C PU AM D ® Ryze n™ E m bed d ed V2000 p rocesso r fa m i ly, 7 n m p rocess AM D ® V2 748 2 .9/4.2 5 G H z, 4 M B L2, 3 5 - 54W (8C/7C U) A M D ® V2 546 3 .0/3 .9 5 G H z, 3 M B L2, 3 5 - 54W (6C/6C U) A M D ® V2 7 1 8 1 .7/4. 1 5 G H z, 4 M B L2, 10 - 2 5W (8C/7C U) A M D ® V2 5 1 6 2 . 1/3 .9 5 G H z, 3 M B L2, 10 - 2 5W (6C/7C U) # Memory U p to 64G B 3 2 00 M T/s D D R4 i n two SO DI M M soc kets, m ax. 3 2 G B pe r soc ket EC C, n o n - EC C s u p p o rt # Cache L2 Ca c h e 4 M B fo r V2 748 V2 7 1 8 3 M B fo r V2 546 V2 5 1 6 # Em bedded BIOS A M I Apti o V U E FI wit h C M O S ba c ku p i n 1 6 M B S PI BIO S (d u a l BIO S by b u i l d o pt i o n, p roj ect ba s i s) # 2.2. Video # G PU A M D ® Ra d eo n ™ G ra p h i cs co re a rc h itectu re # G PU Featu re Su pport 4 i n d e pe n d e nt a n d s i m u l ta n eo u s co m b i n ati o n s of D i s p l ay Po rt/H D M I/LV D S g ra p h i cs o ut p uts (u p to 4x 4 K60) . (e D P o pt i o n a l i n p l a ce of LV D S, VGA o pt i o n a l i n p l a ce of D DI 3 .) H EVC/H .2 6 5 8/10 b, H .2 64 8 b, VP9 8/10 b, J P EG HW d ecod e H EVC/H .2 6 5 8/10 b, H .2 64 8 b HW e n cod e D i re ctX u p t o 1 2 O pe n G L u p to 4. 6 a n d E S 3 .x s u p po rt O pe n C L u p to 2 . 1 s u p po rt ![The image shows a red icon on a white background. It depicts a document outline with a folded top-right corner. Inside the outline are two horizontal red lines centered vertically, symbolizing text.](.cexpress-ar-50m-00014-1020-12/77f206923aa8dd769cc8eceb62cdee7099bc946ea51ba21f58ea986df28b9ad2.jpg) N ote: Ava i l a b i l ity of feat u res d e pe n d e nt o n o pe rati n g syste m (Wi n d ows 1 0 64 - b it, Li n ux 64 - b it) . # 2.2. 1 Disp lay Interface Su p po rt LVDS: S i n g l e/d u a l c h a n n e l 1 8/24 - b it LVD S t h ro u g h e D P to LVD S IC, s u p po rts D E m od e a n d H syn c/Vsyn c m od e. M ax. reso l u ti o n i s 1 92 0x1 2 00 @ 60 H z i n d u a l m od e. P ixe l c l oc k freq u e n cy u p to 1 1 2 M H z. V E SA a n d J EI DA pa n e l d ata fo rm ats s u p po rted . e D P: e D P 1 . 3 u p to 4 l a n e s u p po rt, i n p l a ce of LV D S ( BO M o pti o n), m ax. reso l u ti o n i s 409 6x2 1 60 @ 60 H z, 3 0 b p p D DI x 3 : D i g i ta l D i s p l ay P o rts ( D DI) s u p p o rt D i s p l ay P o rt 1 .4a , H D M I 2 . 1 o r DVI, m a x. re s o l u t i o n of D i s p l ay P o rt 40 9 6x2 1 6 0 @ 6 0 H z, m a x. re s o l u t i o n of H D M I 4096x2 1 60 @ 60 Hz VGA: VGA BO M o pti o n s u p po rt, i n p l a ce of D DI 3 . M ax. reso l u ti o n i s 1 92 0x1 2 00 @ 60 H z ![The image displays a simple graphic icon featuring a red outline of a document or page with a folded top-right corner. Inside the outline, there are two horizontal red lines centered within the space.](.cexpress-ar-50m-00014-1020-12/b506e7ae039399b23f999b1d41db4eb7212fa7c0c77beec13e9152ec58cb6eb0.jpg) N ote: Th e a c h i eva b l e m axi m u m reso l uti o n d e pe n d e nt o n ca rri e r d es i g n . # 2 . 3 . Au d i o I nte l ® Au d i o C o - p ro cesso r i nteg rated Lo cated o n ca rri e r Ex p ress - BAS E 6 (A LC 8 8 6 sta n d a rd s u p p o rt) # 2.4. Expa nsion Busses 6 PCI Exp ress x1 G e n 3 : La n es 0, 1, 2, 3 (co n fi g u ra b l e to x1, x2, x4) a n d La n es 4, 5 (x1 o r x2) A PCIe swi tc h i s H W B O M o pt i o n by p roj e ct b a s i s to offe r m o re x 1 l a n e s vi a La n e s 6, 7 1 PCI Exp ress x8 G e n 3 : La n es 1 6 - 2 3 (co nfi g u ra b l e to 1 x8 o r 2 x4) Ot h e r: S M B u s (syste m) , I2 C (u s e r) , L P C ![The image displays a simple icon representing a document. It features a white shape with a thick red outline, resembling a piece of paper with the bottom-right corner folded upward. Inside the shape, there are two horizontal red lines centered vertically.](.cexpress-ar-50m-00014-1020-12/e2bfca7520d4b1fb41c61cbf961fdfbcea76b4ce9748c699e959d10334c7995a.jpg) N ote: G e n e ra l P u rp o se Po rts G P P 2 - 9 ca n s u p p o rt u p to 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce), refe r to F u n ct i o n a l D i a g ra m fo r d eta i l s . # 2. 5. Ethernet I n t e l ® 2 . 5 G i g a b i t Et h e r n et C o n t ro l l e r i 2 2 5 s e r i e s (V o r IT ve rs i o n ) S u p po rts u p to 2 . 5 G b its a n d 1000/100/10 M b it/s co n n ecti o n V ve rs i o n s u p p o rts u p to 2 . 5 G b i ts IT ve rs i o n s u p p o rts u p to 2 . 5 G b i ts (s u p p o rts TS N o n L i n u x, by p roj e ct b a s i s, T B C) ![The image displays a red icon of a document with a folded bottom-right corner. Inside the outline are three horizontal red lines, with the top line being shorter than the middle and bottom lines.](.cexpress-ar-50m-00014-1020-12/df66fca008830c6289c2613fe7fcd8dfeca34b0c27073263164d63868ca54534.jpg) N ote: G e n e ra l P u rpo se Po rts G P P 2 - 9 ca n s u p po rt u p to 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce), refe r to F u n cti o n a l D i a g ra m fo r d eta i l s . # 2.6. M u lti I/O a nd Storage # U S B 4x U S B 3 . 2/2 .0/1 . 1 (U S B 0, 1, 2, 3), 4x U S B 2 .0/1 . 1 (U S B 4, 5, 6, 7) S u pe rS peed P l u s, S u pe rS peed, H i g h - S peed, F u l l - S peed a n d Low- S peed U S B s i g n a l l i n g ![The image features a red icon on a white background. It depicts a stylized document or paper outline with the top-right corner folded down. Inside the outline, there are three horizontal red lines stacked vertically, resembling text or a list.](.cexpress-ar-50m-00014-1020-12/3b56f470404f59f06cc08d2736e8936bb31049436816713acc695878b789b560.jpg) N otes: Ca rri e r boa rd m u st be d es i g n ed fo r G e n 2 o pe rati o n . U S B 3 . 2 u pg ra d e s i g n a l l a n es 1, 2, 3 a re fro m U S B H u b . # UART Two UART i nte rfa ces S E R0 a n d S E R1 RX/TX o n m od u l e Co n so l e Red i recti o n CO M 1 o r CO M 2 se l ecta b l e i n BIOS U p to 4 s e ri a l p o rts a re s u p p o rte d i n sta n d a rd BIO S i n c l u d i n g S u p e r I/O o n t h e c a r ri e r

COM Port	Description	IRQ	Address	Console Redirection Support
COM 1	Supported by module (SER0, A98/A99), via embedded controller	4	0x3F8	Yes
COM 2	Supported by module (SER1, A101/A102), via embedded controller	3	0x2F8	Yes
COM 3	Supported by Super I/O (W83627DHG) on carrier board	5	0x240	Yes
COM 4	Supported by Super I/O (W83627DHG) on carrier board	7	0x248	Yes

S E R0, S E R1 fro m SoC H S UA RT a re B O M o pti o n s u p po rt by p roj ect ba s i s # G PIO or S D 4 G P O a n d 4 G PI (G PI w i t h i n t e r r u pt) # SATA 2x SATA 6G b/s (SATA 0, 1) ![The image displays a red icon of a document. It features a rectangular shape with rounded corners and a folded top-right corner (a 'dog-ear'). Inside the outline, there are two horizontal red lines centered vertically, representing text.](.cexpress-ar-50m-00014-1020-12/1e5eabe134678745a7d92c1160da35b87e9a1404f57118830d6ecdbd98c1eed0.jpg) N ote: G e n e ra l P u rpo se Po rts G P P 2 - 9 ca n s u p po rt u p to 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce), refe r to F u n cti o n a l D i a g ra m fo r d eta i l s . # 2.7. Trusted Platform Mod u le (TPM) C h i p s et: I n fi n e o n s o l u t i o n Type: T P M 2 .0 (L PC b u s ba sed) T P M c h i p i s BO M o pti o n # 2.8. SEMA Boa rd control ler S u p po rts: Vo l ta g e/c u rre nt m o n ito ri n g , powe r seq u e n ce d e b u g s u p po rt, AT/ATX m od e co nt ro l , l og i sti cs a n d fo re n s i c i nfo rm ati o n, fl at pa n e l co nt ro l , g e n e ra l p u rp o se I2 C, fa i l sa fe BIO S (d u a l BIO S, o pt. s u p p o rt), watc h d o g t i m e r a n d fa n co nt ro l # 2.9. Debug 3 0 - p i n fl at ca b l e co n n ecto r fo r u se wit h D B - 3 0 x8 6 d e b u g m od u l e S u p p o rts BIO S PO ST co d e L E D, e m b ed d ed co nt ro l l e r a ccess, S PI BIO S fl a s h i n g , i nte rn a l p owe r ra i l test p o i nts, d e b u g L E D s # 2. 10. Power Powe r M od es: AT a n d ATX m od e (AT m od e sta rtu p co nt ro l l ed by S E M A Boa rd Co nt ro l l e r) Sta n d a rd Vo l ta g e I n p u t: ATX: 12V ± 5% / 5Vs b ± 5% o r AT: 12V ± 5% Wi d e Vo lta g e I n p ut: ATX: 8 5 -20V 5Vs b ± 5% o r AT: 8. 5 - 2 0V Powe r M a n a g e m e nt: AC PI 5 .0 co m p l i a nt, S m a rt B atte ry s u p po rt Powe r States: C 1 - C 6, S0, S 1, S 3, S4, S 5, S 5 ECO m od e (Wa ke - o n - U S B S 3/S4, Wo L S 3/S4/S 5) ECO M od e s u p po rt fo r d ee p S 5 fo r 5Vs b powe r savi n g # Power Consu m ption P l ea se co nta ct yo u r A D LI N K re p rese ntative fo r t h e d oc u m e nt “CO M Exp ress M od u l e Powe r Co n s u m pti o n ” . # 2. 1 1. M echa nica l a nd Envi ron menta l # Form Facto r a nd specification PIC M G CO M Exp ress Rev 3 .0 (CO M .0 R3 .0), Type 6, Co m pa ct s ize 9 5 x 9 5 m m # Operating Tem peratu re Sta n d a rd 0°C to + 60°C (Wi d e Vo l ta g e I n p u t) Sto ra g e: - 2 0 ° C to + 80° C # H u m id ity 5 - 90% RH o pe rati n g , n o n - co n d e n s i n g , 5 - 9 5 % RH sto ra g e (a n d o pe rati n g wit h co nfo rm a l coat i n g) # Shock a nd Vi bration I EC 60068 - 2 - 64 a n d I EC - 60068 - 2 - 27 M I L- ST D - 2 02 F, M et h od 2 1 3 B, Ta b l e 2 1 3 -I, Co n d iti o n A a n d M et h od 2 14A, Ta b l e 2 14 -I, Co n d iti o n D # HALT tested T h e rm a l St ress, Vi b rati o n St ress, T h e rm a l S h oc k a n d Co m b i n ed Test # 3 . Block Diag ra m ![The flowchart centers on a large red block labeled **'AMD Ryzen™ Embedded'** and **'V2000 Series'**.\n\n**Left-Side Connections:**\n* **VGA**: Connects via a dashed line to a dashed box labeled **'build option'** and **'DP to VGA'**.\n* **eDP/LVDS**: Connects to a blue box labeled **'eDP to LVDS'**, which connects to **'DP 0'** on the central chip. A dashed line labeled **'build option, eDP 4 lanes'** connects **eDP/LVDS** to **'DP 3'**.\n* **USB 2.0 Lane 0-7**: Connects directly to the left side of the central chip.\n* **SATA Port 0-1**: Connects directly to the left side.\n* **SATA Port 2-3**: Connects directly to the left side.\n* **PCIe Lane 0-3**: Connects to the label **'GPP 4, 5, 6, 7'** on the chip. Text nearby reads **'4 x1, 2 x2, 1 x4'**.\n* **PCIe Lane 4-5**: Connects to **'GPP 2-3'** on the chip. A dashed box labeled **'Gen3/2 switch'** connects this line to the right-side PCIe lanes.\n* **2.5GbE/GbE**: Connects to a blue box labeled **'LAN'** and **'I225 V/IT'**, which connects to **'GPP 0'** on the chip.\n* **HDA**: Connects directly to the left side.\n* **SPI**: Connects to a blue box labeled **'BIOS Flash'** and a dashed box labeled **'BIOS Flash'**, with text **'build option'** below.\n* **SMBus**: Connects directly to the left side.\n* **I2C**: Connects to a blue box labeled **'Embedded Controller'**.\n* **GPIO/SDIO**: Connects to the **'Embedded Controller'**.\n* **UART/CAN**: Connects to the **'Embedded Controller'**.\n* **LPC/eSPI**: Connects to the **'Embedded Controller'**.\n\n**Right-Side Connections:**\n* **DDI 1**: Connects to a line originating from **'DP 0'** on the chip. It also connects to the **'build option'** / **'DP to VGA'** dashed box.\n* **DDI 2**: Connects to **'DP 1'** on the chip.\n* **DDI 3**: Connects to **'DP 2'** on the chip.\n* **USB 3.0 Lane 0, 1, 2, 3**: Connect to a blue box labeled **'USB Hub'**. The hub connects to the chip area labeled **'USB 3.2 (10Gbps)'**.\n* **PCIe Lane 6** and **PCIe Lane 7**: Connect via dashed lines to the **'Gen3/2 switch'** dashed box.\n* **PEG Port PCIe 16-23**: Connects to **'GFX (0:7)'** on the chip. Text nearby reads **'1 x8, 2 x4'**.\n* **PCIe-24-27**: Connects to the bottom right of the chip.\n* **PCIe-28-31**: Connects to the bottom right of the chip.\n\n**Internal and Bottom Connections:**\n* The central chip contains labels: **'DP 0'**, **'DP 1'**, **'DP 2'**, **'DP 3'**, **'GPP 8, 9'**, **'GPP 4, 5, 6, 7'**, **'GPP 2-3'**, **'GPP 0'**, **'USB 3.2 (10Gbps)'**, **'GFX (0:7)'**, **'UART'**, and **'LPC'**.\n* **DDR4 SODIMM (top side) 3200 MT/s, non-ECC/ECC** and **DDR4 SODIMM (bottom side) 3200 MT/s, non-ECC/ECC** connect to the bottom of the central chip.\n* The **'Embedded Controller'** (blue box) connects to a small blue box labeled **'TM102'** and **'(board)'**.\n* A dashed box labeled **'TPM 2.0'** is located near **'LPC'**.](.cexpress-ar-50m-00014-1020-12/c19b503e1b647b0dfba30514fc00cb21c783719811ab96ff3952b8b3832a29a3.jpg) Fig u re 1 – Mod u le fu nction d iag ra m # 4 Pi nout a nd Sig na l Descri ptions # 4. 1. Pi n Su m ma ry T h e ta b l e be l ow i s a co m p re h e n s i b l e l i st of a l l s i g n a l p i n s s u p po rted o n t h e d u a l 2 2 0 - p i n CO M Exp ress co n n ecto rs a s d efi n ed fo r Type 6 i n t h e PIC M G C O M .0 R3 .0 s pec ifi cat i o n . S i g n a l s d es c ri bed i n t h e s pec ifi cat i o n b u t n ot s u p po rted o n t h e c Exp ress -A R a re st ri ket h ro u g h ST RI KET H RO U G H . ![D1\nCD\nC1\nB1\nAB\nA110\nA1](.cexpress-ar-50m-00014-1020-12/3a876a1dc2df903cfe9ea5916ec69a25dde1117d4e5e3ba9611a31aa923eec1a.jpg) Fig u re 2 - Mod u le rea r side row a nd pin nu m bering

Row A		Row B		Row C		Row D
A1	GND (FIXED)	B1	GND (FIXED)	C1	GND FIXED)	D1	GND FIXED)
A2	GBE0_MDI3-	B2	GBE0_ACT#	C2	GND	D2	GND
A3	GBE0_MDI3+	B3	LPC_FRAME#/ESPI_CS0#	C3	USB_SSRX0-	D3	USB_SSTX0-
A4	GBE0_LINK100#	B4	LPC_AD0/ESPI_IO_0	C4	USB_SSRX0+	D4	USB_SSTX0+
A5	GBE0_LINK1000#	B5	LPC_AD1/ESPI_IO_1	C5	GND	D5	GND
A6	GBE0_MDI2-	B6	LPC_AD2/ESPI_IO_2	C6	USB_SSRX1-	D6	USB_SSTX1-
A7	GBE0_MDI2+	B7	LPC_AD3/ESPI_IO_3	C7	USB_SSRX1+	D7	USB_SSTX1+
A8	GBE0_LINK#	B8	LPC_DRQ0#/ESPI_ALERT0#	C8	GND	D8	GND
A9	GBE0_MDI1-	B9	LPC_DRQ1#/ESPI_ALERT1#	C9	USB_SSRX2-	D9	USB_SSTX2-
A10	GBE0_MDI1+	B10	LPC_CLK/ESPI_CK	C10	USB_SSRX2+	D10	USB_SSTX2+
A11	GND (FIXED)	B11	GND (FIXED)	C11	GND (FIXED)	D11	GND (FIXED)
A12	GBE0_MDI0-	B12	PWRBTN#	C12	USB_SSRX3-	D12	USB_SSTX3-
A13	GBE0_MDI0+	B13	SMB_CK	C13	USB_SSRX3+	D13	USB_SSTX3+
A14	GBE0_CTREF	B14	SMB_DAT	C14	GND	D14	GND
A15	SUS_S3#	B15	SMB_ALERT#	C15	DDI1_PAIR6+	D15	DDI1_CTRLCLK_AUX+
A16	SATAO_TX+	B16	SATA1_TX+	C16	DDI1_PAIR6-	D16	DDI1_CTRLDATA_AUX-
A17	SATAO_TX-	B17	SATA1_TX-	C17	RSVD	D17	RSVD
A18	SUS_S4#	B18	SUS_STAT#/ESPI_RESET#	C18	RSVD	D18	RSVD
A19	SATAO_RX+	B19	SATA1_RX+	C19	PCIE_RX6+ *	D19	PCIE_TX6+ *
A20	SATAO_RX-	B20	SATA1_RX-	C20	PCIE_RX6- *	D20	PCIE_TX6- *
A21	GND (FIXED)	B21	GND (FIXED)	C21	GND (FIXED)	D21	GND (FIXED)
A22	SATA2_TX+	B22	SATA3_TX+	C22	PCIE_RX7+ *	D22	PCIE_TX7+ *
A23	SATA2_TX-	B23	SATA3_TX-	C23	PCIE_RX7- *	D23	PCIE_TX7- *
A24	SUS_S5#	B24	PWR_OK	C24	DDI1_HPD	D24	RSVD
A25	SATA2_RX+	B25	SATA3_RX+	C25	DDI1_PAIR4+	D25	RSVD
A26	SATA2_RX-	B26	SATA3_RX-	C26	DDI1_PAIR4-	D26	DDI1_PAIR0+
A27	BATLOW#	B27	WDT	C27	RSVD	D27	DDI1_PAIR0-
A28	(S)ATA_ACT#	B28	AC/HDA_SDIN2	C28	RSVD	D28	RSVD
A29	AC/HDA_SYNC	B29	AC/HDA_SDIN1	C29	DDI1_PAIR5+	D29	DDI1_PAIR1+
A30	AC/HDA_RST#	B30	AC/HDA_SDIN0	C30	DDI1_PAIR5-	D30	DDI1_PAIR1-
A31	GND (FIXED)	B31	GND (FIXED)	C31	GND (FIXED)	D31	GND (FIXED)
A32	AC/HDA_BITCLK	B32	SPKR	C32	DDI2_CTRLCLK_AUX+	D32	DDI1_PAIR2+
A33	AC/HDA_SDOUT	B33	I2C_CK	C33	DDI2_CTRLDATA_AUX-	D33	DDI1_PAIR2-
A34	BIOS_DIS0#/ESPI_SAFS	B34	I2C_DAT	C34	DDI2_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL
A35	THRMTRIP#	B35	THRM#	C35	RSVD	D35	RSVD
A36	USB6-	B36	USB7-	C36	DDI3_CTRLCLK_AUX+	D36	DDI1_PAIR3+
A37	USB6+	B37	USB7+	C37	DDI3_CTRLDATA_AUX-	D37	DDI1_PAIR3-
A38	USB_6_7_OC#	B38	USB_4_5_OC#	C38	DDI3_DDC_AUX_SEL	D38	RSVD
A39	USB4-	B39	USB5-	C39	DDI3_PAIR0+	D39	DDI2_PAIR0+
A40	USB4+	B40	USB5+	C40	DDI3_PAIR0-	D40	DDI2_PAIR0-
A41	GND (FIXED)	B41	GND (FIXED)	C41	GND (FIXED)	D41	GND (FIXED)
A42	USB2-	B42	USB3-	C42	DDI3_PAIR1+	D42	DDI2_PAIR1+
A43	USB2+	B43	USB3+	C43	DDI3_PAIR1-	D43	DDI2_PAIR1-
A44	USB_2_3_OC#	B44	USB_0_1_OC#	C44	DDI3_HPD	D44	DDI2_HPD
A45	USB0-	B45	USB1-	C45	RSVD	D45	RSVD
A46	USB0+	B46	USB1+	C46	DDI3_PAIR2+	D46	DDI2_PAIR2+
A47	VCC_RTC	B47	ESPL_EN#	C47	DDI3_PAIR2-	D47	DDI2_PAIR2-
A48	RSVD	B48	USB0_HOST_PRSNT	C48	RSVD	D48	RSVD
A49	GBE0_SDP	B49	SYS_RESET#	C49	DDI3_PAIR3+	D49	DDI2_PAIR3+
A50	LPC_SERIRQ/ESPI_CS1#	B50	CB_RESET#	C50	DDI3_PAIR3-	D50	DDI2_PAIR3-
A51	GND (FIXED)	B51	GND (FIXED)	C51	GND (FIXED)	D51	GND (FIXED)
A52	PCIE_TX5+	B52	PCIE_RX5+	C52	PEG_RX0+	D52	PEG_TX0+
A53	PCIE_TX5-	B53	PCIE_RX5-	C53	PEG_RX0-	D53	PEG_TX0-
A54	GPIO	B54	GPO1	C54	TYPE0#	D54	PEG_LANE_RV#
A55	PCIE_TX4+	B55	PCIE_RX4+	C55	PEG_RX1+	D55	PEG_TX1+
A56	PCIE_TX4-	B56	PCIE_RX4-	C56	PEG_RX1-	D56	PEG_TX1-
A57	GND	B57	GPO2	C57	TYPE1#	D57	TYPE2#
A58	PCIE_TX3+	B58	PCIE_RX3+	C58	PEG_RX2+	D58	PEG_TX2+
A59	PCIE_TX3-	B59	PCIE_RX3-	C59	PEG_RX2-	D59	PEG_TX2-
A60	GND (FIXED)	B60	GND (FIXED)	C60	GND (FIXED)	D60	GND (FIXED)
A61	PCIE_TX2+	B61	PCIE_RX2+	C61	PEG_RX3+	D61	PEG_TX3+
A62	PCIE_TX2-	B62	PCIE_RX2-	C62	PEG_RX3-	D62	PEG_TX3-
A63	GPI1	B63	GPO3	C63	RSVD	D63	RSVD
A64	PCIE_TX1+	B64	PCIE_RX1+	C64	RSVD	D64	RSVD
A65	PCIE_TX1-	B65	PCIE_RX1-	C65	PEG_RX4+	D65	PEG_TX4+
A66	GND	B66	WAKE0#	C66	PEG_RX4-	D66	PEG_TX4-
A67	GPI2	B67	WAKE1#	C67	RAPID_SHUTDOWN	D67	GND
A68	PCIE_TX0+	B68	PCIE_RX0+	C68	PEG_RX5+	D68	PEG_TX5+
A69	PCIE_TX0-	B69	PCIE_RX0-	C69	PEG_RX5-	D69	PEG_TX5-
A70	GND (FIXED)	B70	GND (FIXED)	C70	GND (FIXED)	D70	GND (FIXED)
A71	LVDS_A0+ / eDP_TX2+	B71	LVDS_B0+	C71	PEG_RX6+	D71	PEG_TX6+
A72	LVDS_A0- / eDP_TX2-	B72	LVDS_B0-	C72	PEG_RX6-	D72	PEG_TX6-
A73	LVDS_A1+ / eDP_TX1+	B73	LVDS_B1+	C73	GND	D73	GND
A74	LVDS_A1- / eDP_TX1-	B74	LVDS_B1-	C74	PEG_RX7+	D74	PEG_TX7+
A75	LVDS_A2+ / eDP_TX0+	B75	LVDS_B2+	C75	PEG_RX7-	D75	PEG_TX7-
A76	LVDS_A2- / eDP_TX0-	B76	LVDS_B2-	C76	GND	D76	GND
A77	LVDS_VDD_EN / eDP_VDD_EN	B77	LVDS_B3+	C77	RSVD	D77	RSVD
A78	LVDS_A3+	B78	LVDS_B3-	C78	PEG_RX8+	D78	PEG_TX8+
A79	LVDS_A3-	B79	LVDS_BKLT_EN	C79	PEG_RX8-	D79	PEG_TX8-
A80	GND (FIXED)	B80	GND (FIXED)	C80	GND (FIXED)	D80	GND (FIXED)
A81	LVDS_A_CK+ / eDP_TX3+	B81	LVDS_B_CK+	C81	PEG_RX9+	D81	PEG_TX9+
A82	LVDS_A_CK- / eDP_TX3-	B82	LVDS_B_CK-	C82	PEG_RX9-	D82	PEG_TX9-
A83	LVDS_I2C_CK / eDP_AUX+	B83	LVDS_BKLT_CTRL / eDP_BKLT_CTRL	C83	RSVD	D83	RSVD
A84	LVDS_I2C_DAT / eDP_AUX-	B84	VCC_5V_SBY	C84	GND	D84	GND
A85	GPI3	B85	VCC_5V_SBY	C85	PEG_RX10+	D85	PEG_TX10+
A86	RSVD	B86	VCC_5V_SBY	C86	PEG_RX10-	D86	PEG_TX10-
A87	eDP_HPD	B87	VCC_5V_SBY	C87	GND	D87	GND
A88	PCIE0_CK_REF+	B88	BIOS_DIS1#	C88	PEG_RX11+	D88	PEG_TX11+
A89	PCIE0_CK_REF-	B89	VGA_RED *	C89	PEG_RX11-	D89	PEG_TX11-
A90	GND (FIXED)	B90	GND (FIXED)	C90	GND (FIXED)	D90	GND (FIXED)
A91	SPI_POWER	B91	VGA_GRN *	C91	PEG_RX12+	D91	PEG_TX12+
A92	SPI_MISO	B92	VGA_BLU *	C92	PEG_RX12-	D92	PEG_TX12-
A93	GPO0	B93	VGA_HSYNC *	C93	GND	D93	GND
A94	SPI_CLK	B94	VGA_VSYNC *	C94	PEG_RX13+	D94	PEG_TX13+
A95	SPI_MOSI	B95	VGA_I2C_CK *	C95	PEG_RX13-	D95	PEG_TX13-
A96	TPM_PP	B96	VGA_I2C_DAT *	C96	GND	D96	GND
A97	TYPE10#	B97	SPI_CS#	C97	RSVD	D97	RSVD
A98	SER0_TX	B98	RSVD	C98	PEG_RX14+	D98	PEG_TX14+
A99	SER0_RX	B99	RSVD	C99	PEG_RX14-	D99	PEG_TX14-
A100	GND (FIXED)	B100	GND (FIXED)	C100	GND (FIXED)	D100	GND (FIXED)
A101	SER1_TX/CAN_TX	B101	FAN_PWMOUT	C101	PEG_RX15+	D101	PEG_TX15+
A102	SER1_RX/CAN_RX	B102	FAN_TACHIN	C102	PEG_RX15-	D102	PEG_TX15-
A103	LID#	B103	SLEEP#	C103	GND	D103	GND
A104	VCC_12V	B104	VCC_12V	C104	VCC_12V	D104	VCC_12V
A105	VCC_12V	B105	VCC_12V	C105	VCC_12V	D105	VCC_12V
A106	VCC_12V	B106	VCC_12V	C106	VCC_12V	D106	VCC_12V
A107	VCC_12V	B107	VCC_12V	C107	VCC_12V	D107	VCC_12V
A108	VCC_12V	B108	VCC_12V	C108	VCC_12V	D108	VCC_12V
A109	VCC_12V	B109	VCC_12V	C109	VCC_12V	D109	VCC_12V
A110	GND (FIXED)	B110	GND (FIXED)	C110	GND (FIXED)	D110	GND (FIXED)

![The image displays a red icon on a white background. It features a red outline resembling a square document or page with a folded bottom-right corner (a 'dog-ear'). Inside the outline, there are two horizontal red lines centered vertically, resembling an equals sign.](.cexpress-ar-50m-00014-1020-12/afa1e5bf3b214b50e3ed6221605d984dd0b9863d29f31f0cd7d24a475b9fbb6f.jpg) N otes: ST RI KET H RO U G H e nt ri es a re n ot s u p po rted fu n cti o n s o n t h i s p rod u ct. PCIe l a n e 6, 7 a re B O M o pt i o n s u p p o rt (t h ro u g h a PCIe switc h) by p roj ect ba s i s . e D P (i n p l a ce of LV D S) a n d VGA (i n p l a ce of D DI 3) a re B O M o pt i o n s u p p o rt by p roj ect ba s i s . G e n e ra l P u rpose Po rts G P P 2 - 9 ca n s u p po rt u p to a m axi m u m of 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce) . # 4 2 Sig na l Term i nology Descri ptions M e a n i n g of t h e te r m s u s e d fo r s i g n a l d e s c ri pt i o n ta b l e s .

Term	Description
I	Input to the module
O	Output from the module
I/O	Bi-directional Input / Output
OD	Open drain output from the module

I 3.3V	Input 3.3V tolerant
I 5V	Input 5V tolerant
O 3.3V	Output 3.3V signal level
O 5V	Output 5V signal level
I/O 3.3V	Bi-directional signal 3.3V tolerant
I/O 5V	Bi-directional signal 5V tolerant
I/O $3.3V_{SB}$	Input or output 3.3V tolerant active in standby state

DDC	Display Data Channel
PCIE	PCI Express compatible differential signal
PEG	PCI Express Graphics
SATA	Serial ATA specification Revision 2.6 and 3
LVDS	Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal

P	Power Input / Output
REF	Reference voltage output. May be sourced from a Module power plane.
PDS	Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.

PU	PU (pull-up) resistor on module
PD	PD (pull-down) resistor on module

# 4. 3 . AB Con nector Sig na l Descri ptions 4. 3. 1 Audio

Name	Pin #	Description	I/O	PU / PD	Comment

AC_RST# / HDA_RST#	A30	Reset output to CODEC, active low.	O 3.3VSB
AC_SYNC / HDA_SYNC	A29	Sample-synchronization signal to the CODEC(s).	O 3.3V
AC_BITCLK / HDA_BITCLK	A32	Serial data clock generated by the external CODEC(s).	I/O 3.3V
AC_SDOUT / HDA_SDOUT	A33	Serial TDM data output to the CODEC.	O 3.3V
AC_SDIN[2:0] / HDA_SDIN[2:0]	B28- B30	Serial TDM data inputs from up to 3 CODECs.	I/O 3.3VSB

# 4. 3.2 Ana log VGA

Name	Pin #	Description	I/O	PU / PD	Comment

VGA_RED	B89	Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R	Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector
VGA_GRN	B91	Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R	Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector
VGA_BLU	B92	Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.	O Analog	PD 150R	Shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector
VGA_HSYNC	B93	Horizontal sync output to VGA monitor	O 3.3V
VGA_VSYNC	B94	Vertical sync output to VGA monitor	O 3.3V
VGA_I2C_CK	B95	DDC clock line (I2C port dedicated to identifying VGA monitor capabilities)	I/O OD 3.3V	PU 2k2 3.3V
VGA_I2C_DAT	B96	DDC data line.	I/O OD 3.3V	PU 2k2 3.3V

![The image displays a graphic icon featuring a red square with rounded corners. Inside the red square is a white shape resembling a piece of paper with a folded bottom-right corner (a 'dog-ear'). Two horizontal white lines are positioned in the center of the white shape, resembling lines of text. This is the logo for the Facebook Paper app.](.cexpress-ar-50m-00014-1020-12/dc26a4daec4cd5076253d48d19c834f3b8523563d3036bda7c18a4ced7b865e7.jpg) N ote: VGA i s B O M o pt i o n s u p p o rt (i n p l a c e of D DI 3) by p roj e ct b a s i s . # 4. 3. 3 LVDS or eDP T h e m od u l e d efa u l t s u p po rts a s i n g l e o r d u a l c h a n n e l LV D S d i s p l ay pa n e l wit h u p to 24 - b it co l o u rs. T h e re i s a BO M o pti o n t h at re m oves t h e e D P to LV D S b ri d g e IC a n d o u t p u ts t h e e D P s i g n a l s d i rect ly. e D P vs LV D S p i n m a p p i n g i s d esc ri bed be l ow.

Pin #	LVDS mode	eDP mode
A71	LVDS_A0+	eDP_TX2+
A72	LVDS_A0-	eDP_TX2-
A73	LVDS_A1+	eDP_TX1+
A74	LVDS_A1-	eDP_TX1-
A75	LVDS_A2+	eDP_TX0+
A76	LVDS_A2-	eDP_TX0-
A78	LVDS_A3+	-
A79	LVDS_A3-	-
A81	LVDS_A_CK+	eDP_TX3+
A82	LVDS_A_CK-	eDP_TX3-
B71	LVDS_B0+	-
B72	LVDS_B0-	-
B73	LVDS_B1+	-
B74	LVDS_B1-	-
B75	LVDS_B2+	-
B76	LVDS_B2-	-
B77	LVDS_B3+	-
B78	LVDS_B3-	-
B81	LVDS_B_CK+	-
B82	LVDS_B_CK-	-
A77	LVDS_VDD_EN	eDP_VDD_EN
B79	LVDS_BKLT_EN	eDP_BKLT_EN
B83	LVDS_BKLT_CTRL	eDP_BKLT_CTRL
A83	LVDS_I2C_CK	eDP_AUX+
A84	LVDS_I2C_DAT	eDP_AUX-
A87	-	eDP_HPD

![The image features a red icon of a document page with a folded bottom-right corner and two horizontal lines in the center.](.cexpress-ar-50m-00014-1020-12/8c869a81652a2428c205bb114318a86ffd7313dfbd3c4ddfb84ffcdefdfe9670.jpg) N ote: LVD S i s d efa u l t m od e a n d e D P i s a BO M o pti o n 4. 3. 3. 1. Si ng le/Dua l Cha n nel LVDS (defa u lt)

Name	Pin #	Description	I/O	PU / PD	Comment

LVDS_A0+	A71	LVDS Channel A differential pairs	O LVDS
LVDS_A0-	A72
LVDS_A1+	A73
LVDS_A1-	A74
LVDS_A2+	A75
LVDS_A2-	A76
LVDS_A3+	A78
LVDS_A3-	A79
LVDS_A_CK+	A81	LVDS Channel A differential clock	O LVDS
LVDS_A_CK-	A82
LVDS_B0+	B71	LVDS Channel B differential pairs	O LVDS
LVDS_B0-	B72
LVDS_B1+	B73
LVDS_B1-	B74
LVDS_B2+	B75
LVDS_B2-	B76
LVDS_B3+	B77
LVDS_B3-	B78
LVDS_B_CK+	B81	LVDS Channel B differential clock	O LVDS
LVDS_B_CK-	B82
LVDS_VDD_EN	A77	LVDS panel power enable	O 3.3V	PD 100K
LVDS_BKLT_EN	B79	LVDS panel backlight enable	O 3.3V	PD 100K
LVDS_BKLT_CTRL	B83	LVDS panel backlight brightness control	O 3.3V	PD 100K
LVDS_I2C_CK	A83	DDC lines used for flat panel detection and control.	I/O OD 3.3V	PU 2.2K 3.3V
LVDS_I2C_DAT	A84	DDC lines used for flat panel detection and control.	I/O OD 3.3V	PU 2.2K 3.3V

4. 3. 3.2. 4- la ne eD P

Name	Pin #	Description	I/O	PU / PD	Comment

eDP_TX3+	A81	eDP differential pairs	O PCIE		AC coupled off module
eDP_TX3-	A82
eDP_TX2+	A71
eDP_TX2-	A72
eDP_TX1+	A73
eDP_TX1-	A74
eDP_TX0+	A75
eDP_TX0-	A76
eDP_VDD_EN	A77	eDP power enable	O 3.3V	PD 100K
eDP_BKLT_EN	B79	eDP backlight enable	O 3.3V	PD 100K
eDP_BKLT_CTRL	B83	eDP backlight brightness control	O 3.3V	PD 100K
eDP_AUX+	A83	eDP AUX+	I/O PCIE		AC coupled off module
eDP_AUX-	A84	eDP AUX-	I/O PCIE		AC coupled off module
eDP_HPD	A87	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	PD 100K on this pin when eDP is supported

4. 3.4 G ig a b it Eth e rn et

Name	Pin #	Description				I/O	PU / PD	Comment

GBE0_MDI0+	A13	Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:				I/O Analog		Twisted pair signals for external transformer.
GBE0_MDI0-	A12
GBE0_MDI1+	A10
GBE0_MDI1-	A9	1000		100	10
GBE0_MDI2+	A7	MDI[0]+/-	B1_DA+/-	TX+/-	TX+/-
GBE0_MDI2-	A6	MDI[1]+/-	B1_DB+/-	RX+/-	RX+/-
GBE0_MDI3+	A3	MDI[2]+/-	B1_DC+/-
GBE0_MDI3-	A2	MDI[3]+/-	B1_DD+/-
GBE0_ACT#	B2	Gigabit Ethernet Controller 0 activity indicator, active low.				OD 3.3VSB		LED behaviour is TBC
GBE0_LINK#	A8	Gigabit Ethernet Controller 0 link indicator, active low.				OD 3.3VSB		LED behaviour is TBC
GBE0_LINK100#	A4	Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.				OD 3.3VSB		LED behaviour is TBC
GBE0_LINK1000#	A5	Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.				OD 3.3VSB		LED behaviour is TBC
GBE0_CTREF	A14	Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.				REF GND min 3.3V max		Not supported
GBE0_SDP	A49	Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.				IO 3.3VSB

![The image displays a red icon resembling a square document with a folded bottom-right corner. Inside the red border is a white background. Centered within the white area is a red symbol consisting of a single horizontal line positioned directly above an equals sign (two horizontal lines).](.cexpress-ar-50m-00014-1020-12/464c4bf8a7ea155d7484782c10542e2e45b127f0d7e22cdb3a20e0613bb872fa.jpg) N ote: LAN L E D be h avi o u r i s T BC . # 4. 3. 5 SATA

Name	Pin #	Description	I/O	PU / PD	Comment

SATA0_TX+SATA0_TX-	A16A17	Serial ATA channel 0, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA0_RX+SATA0_RX-	A19A20	Serial ATA channel 0, Receive Input differential pair.	I SATA		AC coupled on Module
SATA1_TX+SATA1_TX-	B16B17	Serial ATA channel 1, Transmit Output differential pair.	O SATA		AC coupled on Module
SATA1_RX+SATA1_RX-	B19B20	Serial ATA channel 1, Receive Input differential pair.	I SATA		AC coupled on Module
SATA2_TX+SATA2_TX-	A22A23	Serial ATA channel 2, Transmit Output differential pair.	O SATA		Not supported
SATA2_RX+SATA2_RX-	A25A26	Serial ATA channel 2, Receive Input differential pair.	I SATA		Not supported
SATA3_TX+SATA3_TX-	B22B23	Serial ATA channel 3, Transmit Output differential pair.	O SATA		Not supported
SATA3_RX+SATA3_RX-	B25B26	Serial ATA channel 3, Receive Input differential pair.	I SATA		Not supported
(S)ATA_ACT#	A28	ATA (parallel and serial) or SAS activity indicator, active low.	O 3.3V	PU 10K 3.3V

# 4. 3. 5. 1. PC H H SIO La ne Assig n ments (SATA)

Name	HSIO name on SOC	Comment
SATA0	GPP 8
SATA1	GPP 9
SATA2	N/A	Not supported
SATA3	N/A	Not supported

![The image shows a simple icon of a document or page with a red outline. The bottom-right corner is folded up (a 'dog-ear'). Inside the white space, there are two horizontal red lines centered vertically.](.cexpress-ar-50m-00014-1020-12/d313f0590a025686d52d2f4b8dcad4a91f8d25297bd985100ebd38cd3904d19a.jpg) N ote: G e n e ra l P u rpose Po rts G P P 2 - 9 ca n s u p po rt u p to a m axi m u m of 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce) . 4 3 6 PCI Exp ress

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX0+PCIE_TX0-	A68A69	PCI Express channel 0, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX0+PCIE_RX0-	B68B69	PCI Express channel 0, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX1+PCIE_TX1-	A64A65	PCI Express channel 1, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX1+PCIE_RX1-	B64B65	PCI Express channel 1, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX2+PCIE_TX2-	A61A62	PCI Express channel 2, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX2+PCIE_RX2-	B61B62	PCI Express channel 2, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX3+PCIE_TX3-	A58A59	PCI Express channel 3, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX3+PCIE_RX3-	B58B59	PCI Express channel 3, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX4+PCIE_TX4-	A55A56	PCI Express channel 4, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX4+PCIE_RX4-	B55B56	PCI Express channel 4, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_TX5+PCIE_TX5-	A52A53	PCI Express channel 5, Transmit Output differential pair.	O PCIE		AC coupled on Module
PCIE_RX5+PCIE_RX5-	B52B53	PCI Express channel 5, Receive Input differential pair.	I PCIE		AC coupled off Module
PCIE_CLK_REF+PCIE_CLK_REF-	A88A89	PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.	O PCIE

![The image displays a red icon resembling a document or note. It features a thick red outline of a page with the top-right corner folded down (a 'dog-ear'). Inside the white interior of the page, two horizontal red lines are centered, representing text.](.cexpress-ar-50m-00014-1020-12/ade0d9d8d33fe5688d41a3e070bc5964ee1d583598bc5625be98ad44e3654a95.jpg) N ote: PCIe La n e 6, 7 a re s u p p o rted by PCIe switc h, by p roj ect ba s i s . 4. 3.6. 1. PC H H SIO La ne Assig n ments (PCI Express)

Name	HSIO name on SOC	Comment

PCIE0	GPP 4
PCIE1	GPP 5
PCIE2	GPP 6
PCIE3	GPP 7
PCIE4	GPP 2
PCIE5	GPP 3
PCIE6	N/A	BOM option support by project basis through a PCIe switch
PCIE7	N/A	BOM option support by project basis through a PCIe switch

![The image shows a digital icon of a document or note. It features a red outline in the shape of a square with rounded corners and a folded bottom-right corner (a 'dog-ear'). Inside the red border, there are three horizontal red lines stacked vertically in the center, resembling lines of text. The background is white.](.cexpress-ar-50m-00014-1020-12/d5cec15a0792788a0ccc91927396404685502c3ac9ddc07671aa56f927bb5c42.jpg) N otes: G e n e ra l P u rpo se Po rts G P P 2 - 9 ca n s u p po rt u p to a m axi m u m of 6 d evi ces (SATA 0/1 co u nt a s o n e d evi ce) . PCIe 0 - 3 ca n be x4, x2 o r x1, PCIe 4 - 5 ca n be x2 o r x1 . 4. 3.7 LPC bus

Name	Pin #	Description	I/O	PU / PD	Comment

LPC_AD0	B4	LPC multiplexed address, command and data bus	I/O 3.3V		Chipset has internal PU, 50K ±30%
LPC_AD1	B5
LPC_AD2	B6
LPC_AD3	B7
LPC_FRAME#	B3	LPC frame indicates the start of an LPC cycle	O 3.3V		Chipset has internal termination, 50K ±30%
LPC_DRQ0#	B8	LPC serial DMA request	I 3.3V		LPC_DRQ1 is not connected
LPC_DRQ1#	B9
LPC_SERIRQ	A50	LPC serial interrupt	I/O 3.3V		Chipset has internal PU, 50K ±30%
LPC_CLK	B10	LPC clock output -33MHz nominal	O 3.3V		The LPC_CLK frequency is 33MHz on this platform

4. 3.8 USB

Name	Pin #	Description	I/O	PU / PD	Comment

USB0+USB0-	A46A45	USB differential data pairs for Port 0	I/O 3.3VSB		USB 1.1/2.0 compliant
USB1+USB1-	B46B45	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/2.0 compliant
USB2+USB2-	A43A42	USB differential data pairs for Port 1	I/O 3.3VSB		USB 1.1/2.0 compliant
USB3+USB3-	B43B42	USB differential data pairs for Port 2	I/O 3.3VSB		USB 1.1/2.0 compliant
USB4+USB4-	A40A39	USB differential data pairs for Port 3	I/O 3.3VSB		USB 1.1/2.0 compliant
USB5+USB5-	B40B39	USB differential data pairs for Port 4	I/O 3.3VSB		USB 1.1/2.0 compliant
USB6+USB6-	A37A36	USB differential data pairs for Port 5	I/O 3.3VSB		USB 1.1/2.0 compliant
USB7+USB7-	B37B37	USB differential data pairs for Port 6	I/O 3.3VSB		USB 1.1/2.0 compliant
USB_0_1_OC#	B44	USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.	I 3.3VSB	PU 10K3.3VSB
USB_2_3_OC#	A44	USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .	I 3.3VSB	PU 10K3.3VSB
USB_4_5_OC#	B38	USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.	I 3.3VSB	PU 10K3.3VSB
USB_6_7_OC#	A38	USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.	I 3.3VSB	PU 10K3.3VSB
USB0_HOST_PRSNT	B48	Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.	I 3.3VSB		Not supported

4. 3 .9 S PI B u s (BIOS o n ly)

Name	Pin #	Description	I/O	PU / PD	Comment
SPI_CS#	B97	Chip select for Carrier Board SPI BIOS Flash.	O 3.3VSB
SPI_MISO	A92	Data in to module from carrier board SPI BIOS flash.	I 3.3VSB
SPI_MOSI	A95	Data out from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_CLK	A94	Clock from module to carrier board SPI BIOS flash.	O 3.3VSB
SPI_POWER	A91	Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier	O P 3.3VSB
BIOS_DIS0#	A34	Selection strap to determine the BIOS boot device.	I	PU 10K 3.3VSB	Carrier shall pull to GND or leave not- connected.
BIOS_DIS1#	B88	Selection strap to determine the BIOS boot device.	I	PU 10K 3.3VSB	Carrier shall pull to GND or leave not- connected

4. 3. 10 M iscel la neous

Name	Pin #	Description	I/O	PU / PD	Comment
SPKR	B32	Output for audio enunciator, the "speaker" in PC-AT systems	O 3.3V
WDT	B27	Output indicating that a watchdog time-out event has occurred.	O 3.3V
THRM#	B35	Input from off-module temp sensor indicating an over-temp situation.	I 3.3VSB
THRMTRIP#	A35	Active low output indicating that the CPU has entered thermal shutdown.	O 3.3V	PU 1K 3.3V
FAN_PWMOUT	B101	Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM.	O OD 3.3V		There shall be PD on carrier board
FAN_TACHIN	B102	Fan tachometer input for a fan with a two-pulse output.	I OD 3.3V	PU 47K 3.3V
TPM_PP	A96	Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.	I 3.3V	PD 100K

4. 3. 1 1 S M Bus

Name	Pin #	Description	I/O	PU / PD	Comment

SMB_CK	B13	System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 8.2K3.3VSB
SMB_DAT#	B14	System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.	I/O OD3.3VSB	PU 8.2K3.3VSB
SMB_ALERT#	B15	System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.	I 3.3VSB

![The image displays a red outline icon of a document or note. It features a rounded rectangular shape with the bottom right corner folded over. Inside the shape, there are two horizontal parallel lines centered vertically.](.cexpress-ar-50m-00014-1020-12/78c250524a69b85a3b632478ffa40413d4b2a22ff3fd1f97353fceac18c07404.jpg) N ote: S M B u s fro m E C i s b u i l d o pt i o n s u p p o rt, by p roj e ct b a s i s . 4. 3. 12 I2C bus

Name	Pin #	Description	I/O	PU / PD	Comment

I2C_CK	B33	General purpose I2C port clock output/input	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)
I2C_DAT	B34	General purpose I2C port data I/O line	I/O OD 3.3VSB	PU 2.2K 3.3VSB	Source SEMA BMC as default (chipset by BOM option)

![The image displays a simple icon resembling a document or note. It features a white square shape with rounded corners and a thick red border. Inside the square, there are two horizontal red lines centered in the upper portion. The bottom right corner of the square is slightly curled or folded, giving it the appearance of a piece of paper.](.cexpress-ar-50m-00014-1020-12/e1cf6edb442173b661232c53c45b9f13418dedfa4789918006a37856b118485e.jpg) N ote: I2 C d efa u l t fro m E C . I2 C fro m S o C i s b u i l d o pt i o n s u p p o rt, by p roj e ct b a s i s . 4. 3. 1 3 Genera l Pu rpose I/O (G PIO)

Name	Pin #	Description	I/O	PU / PD	Comment
GPO[0]	A93	General purpose output pins.	O 3.3V	PD 10K 3.3V	After hardware RESET output low
GPO[1]	B54	General purpose output pins.	O 3.3V	PD 10K 3.3V	After hardware RESET output low
GPO[2]	B57	General purpose output pins.	O 3.3V	PD 10K 3.3V	After hardware RESET output low
GPO[3]	B63	General purpose output pins.	O 3.3V	PD 10K 3.3V	After hardware RESET output low
GPI[0]	A54	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[1]	A63	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[2]	A67	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V
GPI[3]	A85	General purpose input pins. Pulled high internally on the module.	I 3.3V	PU 10K 3.3V

4. 3 . 14 Seria l Interface Sig na l s

Name	Pin #	Description	I/O	PU / PD	Comment

SER0_TX	A98	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SER0_RX	A99	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V
SER1_TX	A101	General purpose serial port transmitter	O CMOS3.3V		Power rail tolerance 5V, 12VThere shall be PD on carrier board
SER1_RX	A102	General purpose serial port receiver	I CMOS3.3V	PU 10K 3.3V	Power rail tolerance 5V, 12V

4.3. 1 5 Power a nd System Ma nagement

Name	Pin #	Description	I/O	PU / PD	Comment
PWRBTN#	B12	Power button to bring system out of S5 (soft off), active on falling edge.	I 3.3VSB	PU 10K 3.3VSB
SYS_RESET#	B49	Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.	I 3.3VSB	PU 10K 3.3VSB
CB_RESET#	B50	Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.	O 3.3V
PWR_OK	B24	Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.	I 3.3VSB	PU 10K 3.3VSB	Should have weak pull up.
SUS_STAT#	B18	Indicates imminent suspend operation; used to notify LPC devices.	O 3.3VSB
SUS_S3#	A15	Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.	O 3.3VSB
SUS_S4#	A18	Indicates system is in Suspend to Disk state. Active low output.	O 3.3VSB
SUS_S5#	A24	Indicates system is in Soft Off state.	O 3.3VSB
WAKE0#	B66	PCI Express wake up signal.	I 3.3VSB	PU 8.2K 3.3VSB
WAKE1#	B67	General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.	I 3.3VSB	PU 8.2K 3.3VSB	Connect to WAKE 0#
BATLOW#	A27	Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.	I 3.3VSB	PU 10K 3.3VSB
LID#	A103	LID button. Low active signal used by the ACPI operating system for a LID switch.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
SLEEP#	B103	Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.	I OD 3.3VSB	PU 47K 3.3VSB	Emulated on GPIO (BIOS)
RAPID_SHUTDOWN	C67	Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source impedance for ≥20 μs.	I CMOS 5VSB		Not supported

4.3. 16 Power a nd Grou nd

Name	Pin #	Description	I/O	PU / PD	Comment
VCC_12V	A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109	Primary power input supports wide range 5~20V inputAll available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
VCC_5V_SBY	B84, B85, B86, B87	Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.	P		5Vsb ±5%
VCC_RTC	A47	Real-time clock circuit-power input. Nominally +3.0V.	P
GND	A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110	Ground - DC power and signal and AC signal return path.	P

# 4 4 C D Con nector Sig na l Descri ptions 4.4. 1 U S B 3.0 Extensions

Name	Pin #	Description	I/O	PU / PD	Comment

USB_SSRX0-USB_SSRX0+	C3C4	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0	I PCIE		AC coupled on module
USB_SSTX0-USB_SSTX0+	D3D4	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0	O PCIE		AC coupled on module
USB_SSRX1-USB_SSRX1+	C6C7	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1	I PCIE		AC coupled on module
USB_SSTX1-USB_SSTX1+	D6D7	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1	O PCIE		AC coupled on module
USB_SSRX2-USB_SSRX2+	C9C10	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2	I PCIE		AC coupled on module
USB_SSTX2-USB_SSTX2+	D9D10	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2	O PCIE		AC coupled on module
USB_SSRX3-USB_SSRX3+	C12C13	Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3	I PCIE		AC coupled on module
USB_SSTX3-USB_SSTX3+	D12D13	Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3	O PCIE		AC coupled on module

4.4. 1. 1. U SB Root Seg mentation

Name	HSIO name on SOC	Comment

USB 0	USB Port 1
USB 1	-	From a USB Hub, USB Hub connect to SoC's USB Port 5
USB 2	-	From a USB Hub, USB Hub connect to SoC's USB Port 5
USB 3	-	From a USB Hub, USB Hub connect to SoC's USB Port 5

4 4 2 PCI Exp ress

Name	Pin #	Description	I/O	PU / PD	Comment

PCIE_TX6+PCIE_TX6-	D19D20	PCI Express channel 6, Transmit Output differential pair.	O PCIE		AC coupled on ModuleBy a PCIe switch, project basis
PCIE_RX6+PCIE_RX6-	C19C20	PCI Express channel 6, Receive Input differential pair.	I PCIE		AC coupled off ModuleBy a PCIe switch, project basis
PCIE_TX7+PCIE_TX7-	D22D23	PCI Express channel 7, Transmit Output differential pair.	O PCIE		AC coupled on ModuleBy a PCIe switch, project basis
PCIE_RX7+PCIE_RX7-	C22C23	PCI Express channel 7, Receive Input differential pair.	I PCIE		AC coupled off ModuleBy a PCIe switch, project basis

![The image displays a digital icon representing a document. It features a white square shape with rounded corners and a thick red border. The top-right corner is folded down, resembling a 'dog-ear.' Inside the white area, there are two horizontal red bars centered vertically, resembling lines of text. This is the logo for Google Docs.](.cexpress-ar-50m-00014-1020-12/2e94d7ba058e7f9d1bda9685a1d4433bb04ef6a657f5649030aa737b44288eb4.jpg) N ote: PCIe La n e 6, 7 a re s u p p o rted by PCIe switc h, by p roj ect ba s i s . 4.4.2. 1. PC H H SIO La ne Assig n ments (PCI Express)

Name	HSIO name on SOC	Comment

PCIE0	GPP 4
PCIE1	GPP 5
PCIE2	GPP 6
PCIE3	GPP 7
PCIE4	GPP 2
PCIE5	GPP 3
PCIE6	N/A	BOM option support by project basis through a PCIe switch
PCIE7	N/A	BOM option support by project basis through a PCIe switch

# 4.4. 3 DDI1 Port

Name	Pin #	DisplayPort (DP)	HDMI

DDI1_PAIR0+	D26	DP1_LANE0+	TMDS1_DATA2+
DDI1_PAIR0-	D27	DP1_LANE0-	TMDS1_DATA2-
DDI1_PAIR1+	D29	DP1_LANE1+	TMDS1_DATA1+
DDI1_PAIR1-	D30	DP1_LANE1-	TMDS1_DATA1-
DDI1_PAIR2+	D32	DP1_LANE2+	TMDS1_DATA0+
DDI1_PAIR2-	D33	DP1_LANE2-	TMDS1_DATA0-
DDI1_PAIR3+	D36	DP1_LANE3+	TMDS1_CLK+
DDI1_PAIR3-	D37	DP1_LANE3-	TMDS1_CLK-
DDI1_PAIR4+	C25	-	-
DDI1_PAIR4-	C26
DDI1_PAIR5+	C29	-	-
DDI1_PAIR5-	C30
DDI1_PAIR6+	C15	-	-
DDI1_PAIR6-	C16
DDI1_HPD	C24	DP1_HPD	HDMI1_HPD
DDI1_CTRLCLK_AUX+	D15	DP1_AUX+	HMDI1_CTRLCLK
DDI1_CTRLCLK_AUX-	D16	DP1_AUX-	HMDI1_CTRLDATA
DDI1_DDC_AUX_SEL	D34	DDI1_DDC_AUX_SEL	DDI1_DDC_AUX_SEL

![The image displays a red icon representing a document or file. It features a square outline with a folded top-right corner. Inside the shape, two horizontal lines are positioned to resemble text on a page.](.cexpress-ar-50m-00014-1020-12/5b88d5e519315aa60ad67dacf2772c25727bc292e7033d70eac0d1e495ffd4d7.jpg) N ote: D u a l M od e ( H D M I a n d D i s p l ay Po rt o n t h e sa m e p i n s) i m p l e m e ntati o n s m ay be rea l ized . T h i s i s d es i ra b l e fo r SOC s t h at n ative ly i m p l e m e nt t h i s ca pa b i l ity. Wit h s u c h SOC s, t h e p ri m a ry D u a l M od e i m p l e m e ntati o n c h a l l e n g e i s t h at t h e H D M I CT RL DAT a n d H D M I CT RL C K l i n es a re DC co u p l ed , b u t t h e D P\_A U X + /- pa i r m u st b e AC co u p l ed . A set of F ET switc h es i s u s u a l ly u sed to so rt t h i s o u t. T h e F ET g ates ca n b e co nt ro l l ed by t h e AUX\_S E L p i n fu n cti o n . 4.4. 3 . 1. Disp layPo rt (D P) M od e (D DI 1)

Name	Pin #	Description	I/O	PU / PD	Comment

DP1_LANE0+	D26	DP Port 1, differential pair data lines	O PCIE		AC coupled off Module
DP1_LANE0-	D27				100 nF DC blocking capacitors shall be placed on the Carrier
DP1_LANE1+	D29
DP1_LANE1-	D30
DP1_LANE2+	D32
DP1_LANE2-	D33
DP1_LANE3+	D36
DP1_LANE3-	D37
DP1_HPD	C24	DP Port 1, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP1_AUX+	D15	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP1_AUX-	D16	DP Port 1, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K 3.3V	AC coupled on Module
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.3.2. H DMI Mode (DDI1)

Name	Pin #	Description	I/O	PU / PD	Comment

TMDS1_DATA2+	D26	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS1_DATA2-	D27
TMDS1_DATA1+	D29
TMDS1_DATA1-	D30
TMDS1_DATA0+	D32
TMDS1_DATA0-	D33
TMDS1_CLK+	D36	HDMI Port, Differential Pair Clock Lines
TMDS1_CLK-	D37	HDMI Port, Differential Pair Clock Lines
HDMI_HPD	C24	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI1_CTRLCLK	D15	I2C_CLK Line for HDMI	I/O ODCMOS
HDMI1_CTRLDATA	D16	I2C_DAT Line for HDMI	I/O ODCMOS
DDI1_DDC_AUX_SEL	D34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Levethis signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.4 DDI2 Port

Name	Pin #	DisplayPort (DP)	HDMI
DDI2_PAIR0+	D39	DP2_LANE0+	TMDS2_DATA2+
DDI2_PAIR0-	D40	DP2_LANE0-	TMDS2_DATA2-
DDI2_PAIR1+	D42	DP2_LANE1+	TMDS2_DATA1+
DDI2_PAIR1-	D43	DP2_LANE1-	TMDS2_DATA1-
DDI2_PAIR2+	D46	DP2_LANE2+	TMDS2_DATA0+
DDI2_PAIR2-	D47	DP2_LANE2-	TMDS2_DATA0-
DDI2_PAIR3+	D49	DP2_LANE3+	TMDS2_CLK+
DDI2_PAIR3-	D50	DP2_LANE3-	TMDS2_CLK-
DDI2_HPD	D44	DP2_HPD	HDMI2_HPD
DDI2_CTRLCLK_AUX+	C32	DP2_AUX+	HMDI2_CTRLCLK
DDI2_CTRLCLK_AUX-	C33	DP2_AUX-	HMDI2_CTRLDATA
DDI2_DDC_AUX_SEL	C34	DDI2_DDC_AUX_SEL	DDI2_DDC_AUX_SEL

![The image displays a simple red icon representing a document or file. It features a red outline of a rectangular page with a folded corner at the top right. Inside the outline, there are two thick, horizontal red lines centered vertically, resembling lines of text.](.cexpress-ar-50m-00014-1020-12/d1c986e670ef6b4dc83366b95b93030d273339f8017cf96c36d38709e76bdf35.jpg) N ote: D u a l M od e ( H D M I a n d D i s p l ay Po rt o n t h e sa m e p i n s) i m p l e m e ntati o n s m ay be rea l ized . T h i s i s d es i ra b l e fo r SOC s t h at n ative ly i m p l e m e nt t h i s ca pa b i l ity. Wit h s u c h SOC s, t h e p ri m a ry D u a l M od e i m p l e m e ntati o n c h a l l e n g e i s t h at t h e H D M I\_CT RL\_DAT a n d H D M I\_CT RL\_C K l i n es a re DC co u p l ed , b u t t h e D P\_A U X + /- pa i r m u st b e AC co u p l ed . A set of F ET switc h es i s u s u a l ly u sed to so rt t h i s o u t. T h e F ET g ates ca n b e co nt ro l l ed by t h e AUX\_S E L p i n fu n cti o n . 4.4.4. 1. Disp layPo rt (D P) M od e (D DI2)

Name	Pin #	Description	I/O	PU / PD	Comment

DP2_LANE0+	D39	DP Port 2, differential pair data lines	O PCIE		AC coupled off Module
DP2_LANE0-	D40				100 nF DC blocking capacitors shall be placed on the Carrier
DP2_LANE1+	D42
DP2_LANE1-	D43
DP2_LANE2+	D46
DP2_LANE2-	D47
DP2_LANE3+	D49
DP2_LANE3-	D50
DP2_HPD	D44	DP Port 2, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP2_AUX+	C32	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP2_AUX-	C33	DP Port 2, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K 3.3V	AC coupled on Module
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1M	DP mode enabled

4.4.4.2. H DMI Mode (DDI1)

Name	Pin #	Description	I/O	PU / PD	Comment

TMDS2_DATA2+	D39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS2_DATA2-	D40
TMDS2_DATA1+	D42
TMDS2_DATA1-	D43
TMDS2_DATA0+	D46
TMDS2DATA0-	D47
TMDS2_CLK+	D49	HDMI Port, Differential Pair Clock Lines
TMDS2_CLK-	D50	HDMI Port, Differential Pair Clock Lines
HDM2_HPD	D44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI2_CTRLCLK	C32	I2C_CLK Line for HDMI	I/O ODCMOS
HDMI2_CTRLDATA	C33	I2C_DAT Line for HDMI	I/O ODCMOS
DDI2_DDC_AUX_SEL	C34	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Levethis signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4. 5 D DI 3 Po rt

Name	Pin #	DisplayPort (DP)	HDMI
DDI3_PAIR0+	C39	DP3_LANE0+	TMDS3_DATA2+
DDI3_PAIR0-	C40	DP3_LANE0-	TMDS3_DATA2-
DDI3_PAIR1+	C42	DP3_LANE1+	TMDS3_DATA1+
DDI3_PAIR1-	C43	DP3_LANE1-	TMDS3_DATA1-
DDI3_PAIR2+	C46	DP3_LANE2+	TMDS3_DATA0+
DDI3_PAIR2-	C47	DP3_LANE2-	TMDS3_DATA0-
DDI3_PAIR3+	C49	DP3_LANE3+	TMDS3_CLK+
DDI3_PAIR3-	C50	DP3_LANE3-	TMDS3_CLK-
DDI3_HPD	C44	DP3_HPD	HDMI3_HPD
DDI3_CTRLCLK_AUX+	C36	DP3_AUX+	HMDI3_CTRLCLK
DDI3_CTRLCLK_AUX-	C37	DP3_AUX-	HMDI3_CTRLDATA
DDI3_DDC_AUX_SEL	C38	DDI3_DDC_AUX_SEL	DDI3_DDC_AUX_SEL

![The image displays a red icon resembling a document or memo. It features a rectangular outline with a curled bottom-right corner. Inside the shape, there are two horizontal lines stacked vertically and centered.](.cexpress-ar-50m-00014-1020-12/23b110952e4ec026aa21c307d231385f149fa3679954dc2174d823e417d8f97a.jpg) N ote: D u a l M od e ( H D M I a n d D i s p l ay Po rt o n t h e sa m e p i n s) i m p l e m e ntati o n s m ay be rea l ized . T h i s i s d es i ra b l e fo r SOC s t h at n ative ly i m p l e m e nt t h i s ca pa b i l ity. Wit h s u c h SOC s, t h e p ri m a ry D u a l M od e i m p l e m e ntati o n c h a l l e n g e i s t h at t h e H D M I\_CT RL\_DAT a n d H D M I\_CT RL\_C K l i n es a re DC co u p l ed , b u t t h e D P\_A U X + /- pa i r m u st b e AC co u p l ed . A set of F ET switc h es i s u s u a l ly u sed to so rt t h i s o u t. T h e F ET g ates ca n b e co nt ro l l ed by t h e AUX\_S E L p i n fu n cti o n . 4.4. 5 . 1. Disp layPo rt (D P) M od e (D DI3)

Name	Pin #	Description	I/O	PU / PD	Comment

DP3_LANE0+	C39	DP Port 3, differential pair data lines	O PCIE		AC coupled off Module
DP3_LANE0-	C40				100 nF DC blocking capacitors shall be placed on the Carrier
DP3_LANE1+	C42
DP3_LANE1-	C43
DP3_LANE2+	C46
DP3_LANE2-	C47
DP3_LANE3+	C49
DP3_LANE3-	C50
DP3_HPD	C44	DP Port 3, detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K	Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.
DP3_AUX+	C36	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PD 100K	AC coupled on Module
DP3_AUX-	C37	DP Port 3, Bidirectional Channel used for Link Management and Device Control	I/O PCIE	PU 100K 3.3V	AC coupled on Module
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode	I 3.3V	PD 1,	DP mode enabled

4.4. 5.2. H DMI Mode (DDI3)

Name	Pin #	Description	I/O	PU / PD	Comment

TMDS3_DATA2+	C39	HDMI / DVI Port, Differential Pair Data Lines	O PCIE		AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier
TMDS3_DATA2-	C40
TMDS3_DATA1+	C42
TMDS3_DATA1-	C43
TMDS3_DATA0+	C46
TMDS3_DATA0-	C47
TMDS3_CLK+	C49	HDMI Port, Differential Pair Clock Lines
TMDS3_CLK-	C50	HDMI Port, Differential Pair Clock Lines
HDM3_HPD	C44	Detection of Hot Plug / Unplug and notification of the link layer	I 3.3V	PD 100K
HDMI3_CTRLCLK	C36	I2C_CLK Line for HDMI	I/O ODCMOS
HDMI3_CTRLDATA	C37	I2C_DAT Line for HDMI	I/O ODCMOS
DDI3_DDC_AUX_SEL	C38	Strapping Signal to select HDMI or DP output1M pull-down to logic ground enables HDMI Levethis signal floating enables DisplayPort mode	I 3.3V	PD 1M	HDMI mode enabled

4.4.6 PCIe G ra p h ics Po rt (P EG)

Name	Pin #	Description	I/O	PU / PD	Comment
PEG_TX0+PEG_TX0-	D52D53	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX0+PEG_RX0-	C52C53	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX1+PEG_TX1-	D55D56	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX1+PEG_RX1-	C55C56	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX2+PEG_TX2-	D58D59	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX2+PEG_RX2-	C58C59	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX3+PEG_TX3-	D61D62	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX3+PEG_RX3-	C61C62	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX4+PEG_TX4-	D65D66	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX4+PEG_RX4-	C65C66	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX5+PEG_TX5-	D68D69	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX5+PEG_RX5-	C68C69	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX6+PEG_TX6-	D71D72	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX6+PEG_RX6-	C71C72	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_TX7+PEG_TX7-	D74D75	PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	O PCIE		AC coupled on Module
PEG_RX7+PEG_RX7-	C74C75	PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6	I PCIE		AC coupled off Module
PEG_LANE_RV#	D54	PCI Express Graphics lane reversal input strap. Pull low on the Carrier Board to reverse lane order.	I 3.3V		Not supported

![The image displays a small, pixelated icon of a document or page. It features a thick red outline with the top-right corner folded downward. Inside the red border, there are two horizontal red lines centered vertically, representing text. The background is white.](.cexpress-ar-50m-00014-1020-12/40ed0fc78e804c1f514ccc657e89ebbea1529da2936847078292e3465fbc09cd.jpg) N ote: O n ly l a n es 0 - 7 fro m t h e 1 6 l a n es of t h e P EG po rt a re s u p po rted . T h e ava i l a b l e co nfi g u rati o n s a re o n e x8 o r two x4. 4.4.7 Mod u le Type Definition

Name	Pin #	Description	I/O	PU / PD	Comment

TYPE0#	C54	The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC).	???	???	Type 6
TYPE1#	C57
TYPE2#	D57
		For Pin-out Type 1 and Type 10 that lack a CD connector, these pins are not present (X)
		TYPE2# TYPE1# TYPE0#
		X X X Pinout Type 1
		X X X Pinout Type 10
		NC NC NC Pinout Type 2
		NC NC GND Pinout Type 3
		NC GND NC Pinout Type 4
		NC GND GND Pinout Type 5
		GND NC NC Pinout Type 6
		GND NC GND Pinout Type 7
		The Carrier Boardshouldimplement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.
TYPE10#	A97	In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.			Not Connected

4.4.8 Power a nd Grou nd

Name	Pin #	Description	I/O	PU / PD	Comment
VCC_12V	C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109	Primary power input supports wide range 5~20V input. All available VCC_12V pins on the connector(s) shall be used.	P		8.5-20 V
GND	C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110	Ground - DC power and signal and AC signal return path.	P

# 5. Add itiona l Featu res T h i s c h a pte r d esc ri b es co n n ecto rs, L E D s, switc h es a n d a d d it i o n a l ite m s l o cated o n t h e m o d u l e a n d n ot n ecessa ri ly i n c l u d ed i n t h e PIC M G sta n d a rd s p ec - i fi c a t i o n . T h e l o c a t i o n s of t h e s e i te m s i s a s b e l ow: ![Status LEDs\nFan 12V\n30-pin debug connector\nBIOS default Reset\nBIOS Boot Select\nADLINK](.cexpress-ar-50m-00014-1020-12/e34e38f11462bd70684c68df9717babd1069ac831b407b09d5a71b3f43953f66.jpg) Fig u re 3 – M od u le featu re locations # 5. 1. Debug Con nector T h i s c o n n e cto r i s p a rt i c u l a r u s efu l d u ri n g c a r ri e r d e s i g n a n d b r i n g u p p h a s e . It offe rs a c c e s s to t h e fo l l owi n g c ri t i c a l p a rts of t h e m o d u l e : z Te st p o i n ts m e a s u re m e n t of i n te r n a l p owe r ra i l s z I2 C b u s fo r BIO S PO ST cod e rea d o ut z S PI BIO S p rog ra m m i n g i nte rfa ce z E m bed d ed Co nt ro l l e r p rog ra m m i n g i nte rfa ce ![Two electronic circuit boards: one with a green PCI and connected to a cable, the other with a gray fiber optic cable (no visible text or symbols)](.cexpress-ar-50m-00014-1020-12/17583921e5c109696e7a02c31e19b8c91d5d12529c0f8c0b4354062034113397.jpg) Figu re 4 – cExpress-AR a nd Debug Mod u le # 5 . 2 . Statu s LE Ds Stat u s L E D ’ s a re m o u nted o n t h e m o d u l e to fa c i l itate ea s i e r m a i nte n a n ce . L E D 1 L E D2 L E D 3 ![Close-up of a green printed circuit board with integrated circuits and a circular component (no visible text or symbols)](.cexpress-ar-50m-00014-1020-12/0599d76cb63aed3e73af8857216fc4b5f7cbdef102baa4c54b9aae0e111c9146.jpg)

Name	Color	Connection	Function
LED1	Blue	BMC output	Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes Table below)
LED2	Green	Power Source 3Vcc	S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3	Red	BMC output and same signal as WDT (B27) on BtB connector	Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)

# 5. 3. Exception Codes

Exception Code	Error Message
0	NOERROR
2	NO_SUSCLK
3	NO_SLP_S5
4	NO_SLP_S4
5	NO_SLP_S3
6	BIOS_FAIL
7	RESET_FAIL
8	RESETIN_FAIL
9	NO_CB_PWROK
10	CRITICAL_TEMP
11	POWER_FAIL
12	VOLTAGE_FAIL
13	RFID_MEMFAIL (No Used)
14	NO_VDDQ_PG
15	NO_V1P05A_PG
16	NO_VCORE_PG
17	NO_SYS_GD
18	NO_V5SBY
19	NO_V3P3A
20	NO_V5_DUAL
21	NO_PWRSRC_GD
22	NO_P_5V_3V3_S0_PG
23	NO_SAME_CHANNEL
24	NO_1V2A_PG

# 5.4. Fa n Con nector Co n n ecto r type: JVE 24W1 12 5A-04 M 00 ![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.cexpress-ar-50m-00014-1020-12/5559a7fa276c4db3b5c0ca8c5d4ed98134cf86845fb09c333af7c9a4551b7dae.jpg)

Name	Description
1	FAN_PWMOUT
2	FAN_TACHIN
3	GND
4	12V

# 5 . 5 . BIOS Defa u lt Reset Butto n ![The image displays a close-up of a green printed circuit board (PCB). A red arrow points from the left towards a square white component on the edge of the board. The text 'P1' is printed in white on the board, located just below the arrow and the square component. Various small surface-mount electronic components are visible, along with a large gold-plated ring at the bottom.](.cexpress-ar-50m-00014-1020-12/4547687e72e42d268c4671981c5bb3f713780f0b450fe609b946a60d78065939.jpg) To p e rfo r m a h a rd wa re re s et of BIO S d efa u l t s ett i n g s, p e rfo r m t h e fo l l ow i n g ste p s : 1 . S h u t d ow n t h e syste m . 2 . Kee p t h e BIO S Setu p Defa u lts Reset B utto n p ressed a n d boot u p t h e syste m . Yo u ca n re l ea se t h e b utto n wh e n t h e BIO S p ro m pt sc ree n a p pea rs 3 . T h e BIO S p ro m pt sc ree n wi l l d i s p l ay a co nfi rm ati o n t h at BIO S d efa u l ts h ave bee n reset a n d req u est t h at yo u re boot t h e syste m . ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.cexpress-ar-50m-00014-1020-12/e4740bd15ca4ab8af661a87973d982c0ae1cc49408a5bf4af344feae67f82d20.jpg) # 5 .6. BIOS Boot Sel ect T h e m od u l e h a s two BIO S c h i ps ( BO M o pt i o n) a n d BIO S o pe rati o n ca n b e co nfi g u red to " PIC M G " a n d d u a l - BIO S " Fa i l sa fe " m od es u s i n g BIO S Se l ect a n d M od e C o n fi g u rat i o n Switc h, P i n 2 . Setti n g t h e m od u l e to PIC M G m od e wi l l co nfi g u re t h e BIO S c h i ps o n t h e m od u l e a s S PI0 a n d S PI 1 . I n PIC M G m od e, a BIO S c h i p ca n n ot be p l a ced i n t h e S PI0 s l ot o n t h e c a r r i e r. I n d u a l - BIO S Fa i l safe m od e, bot h BIO S c h i p s o n t h e m od u l e a re co nfi g u red a s S PI 1 . O n ly o n e of t h e two i s co n n ected to t h e S PI b u s at a ny g ive n ti m e. I n ca se of fa i l u re of t h e p ri m a ry S PI 1 BIO S, t h e syste m wi l l re b o ot a n d switc h to t h e se co n d a ry S PI 1 BIO S o n t h e m o d u l e . I n Fa i l sa fe m o d e, t h e S PI0 BIO S so c ket o n t h e ca rri e r ca n b e p o p u l ated . I n e it h e r m od e, BIO S Se l ect a n d M od e C o n fi g u rat i o n Switc h P i n 1 i s u sed to se l ect w h et h e r to boot fro m S PI0 o r S PI 1 .

Mode	Pin 1	Pin 2
Boot from SPI0 (default)	On	-
Boot from SPI1	Off	-
Set BIOS to PICMG mode (default)	-	On
Set BIOS to Failsafe BIOS mode	-	Off

# 6 BIOS Checkpoints, Beep Codes A sta t u s c o d e i s a d a ta va l u e u s e d to p rovi d e d i a g n o st i c i n fo r m a t i o n a b o u t t h e b o ot p ro c e s s . P ro g re s s c o d e s a re sta t u s c o d e s t h a t s i g n i fy s u c c e s sfu l p ro g re s s i o n to a fo l l owi n g i n i t i a l i za t i o n ste p . E r ro r c o d e s s i g n i fy e r ro r c o n d i t i o n s e n c o u n te re d i n t h e p ro c e s s of syste m i n i t i a l i za t i o n . T h e A pt i o 5 .x c o re ca n b e co n fi g u red to se n d stat u s co d es to a va ri ety of so u rces . T h e two m o st co m m o n ly u sed typ es of stat u s co d es a re c h ec kp o i nt co d es a n d b ee p cod es. C h ec kpo i nt cod es a re byte l e n g t h d ata va l u es. C h ec kpo i nts a re typ i ca l ly o u t p u t to I/O po rt 80 h, b u t t h e Apti o 5 .x co re ca n be co nfi g u red to se n d c h ec kp o i nts to a va ri ety of so u rces . T h e Apt i o 5 .x co re o u t p u ts c h ec kp o i nts t h ro u g h o u t t h e b o ot p ro cess to i n d i cate t h e ta s k t h e syste m i s c u rre nt ly exec u ti n g . C h ec kpo i nts a re ve ry u sefu l i n a i d i n g softwa re d eve l o pe rs o r tec h n i c i a n s i n d e b u g g i n g p ro b l e m s t h at occ u r d u ri n g t h e p re - boot p rocess o n p ro d u ct i o n h a rdwa re . A b ee p co d e i s a se ri es of s h o rt so u n d s i g n a l s . B ee p co d es a re typ i ca l ly e rro r co d es t h at d o n ot o cc u r d u ri n g n o rm a l b o ot p ro cess . ![The image displays a red icon resembling a document or memo. It features a thick red outline in the shape of a piece of paper with the bottom-right corner curled upward. Inside the outline, there are three horizontal red bars stacked vertically, centered within the shape, resembling text lines.](.cexpress-ar-50m-00014-1020-12/6a29a37505381d9d6529fea7e3f392e461f95dc2342887ebc3fd094090367062.jpg) N ote: Bee p cod es a re n ot t h e o n ly so u n d s g e n e rated d u ri n g t h e boot p rocess. So m e fi rmwa re co m po n e nts m ay u se so u n d s to n otify t h e u se r a bo u t ot h e r eve nts s u c h a s d etecti o n of a h ot- p l u g g a b l e d evi ce. T h ese so u n d s a re typ i ca l ly g e n e rated u s i n g a freq u e n cy t h at i s d iffe re nt fro m t h e freq u e n cy of t h e bee p cod es # Viewing Checkpoints C h ec kpo i nts g e n e rated by t h e Apti o fi rmwa re ca n be vi ewed u s i n g a PCI c h ec kpo i nt ca rd , a l so refe rred to a s a “ PO ST Ca rd ” o r “ PO ST D i a g n osti c Ca rd ” . T h ese PCI a d d - o n ca rd s s h ow t h e va l u e of I/O p o rt 80 h o n a n L E D d i s p l ay. # Aptio V Checkpoint and Beep Codes Down l oa d t h e Apti o V C h ec kpo i nt a n d Bee p Cod es fro m t h e A M I we bs ite at: www.a m i .co m/d own l oa d/a pti o -v- c h ec kpo i nt- a n d - bee p - cod es # 7. Softwa re Su p port # 7. 1. O perati ng Systems Wi n d ows 1 0 IOT E n te r p ri s e 64 - b i t Wi n d ows 10 64 - b it • U b u ntu 2 0.04 (p l a n n i n g) # 8. Mecha nica l a nd Therma l 8. 1. M od u le Di mensions ![95 80 75 74.2 19 16.5 4 0\n4\nConnector on bottom side\n0\n4\n6\n18\n35\nTop View\n53.7\n91\n91\n91\n95\n4](.cexpress-ar-50m-00014-1020-12/7b7e567ac7579f4991c536e80e9bcaaee5d9cf16acdf69aaa25dfc78304b974f.jpg) ![Pure architectural floor plan lines without any text, numbers, or symbols](.cexpress-ar-50m-00014-1020-12/021400819a1c155fd98437ec046fc3f23fc3f4297ac10c4fd18068f15203ab83.jpg) R i g h t V i ew ![0\n4\n16.5\n19\n74.2\n75\n80\n95\n0\n4\n6\n18\n35\n4\n53.7\n56.9\nBottom Side SODIMM\nKeep-out Zone\n91\n95\n4\n12.7\n87.7\n91\nBottom View](.cexpress-ar-50m-00014-1020-12/f912af8391795137fee54326014a46b59185e15582c932d43442c946c8019314.jpg) ![Side View\n5.3\n4\n2](.cexpress-ar-50m-00014-1020-12/e3a13a3160c63fc77293e9baf63d2092afad188d55293a5a7da37e485c40fae5.jpg) Al l d i m e n s i o n s a re s h own i n m i l l i m ete rs . To l e ra n ces s h o u l d b e ± 0 . 2 5 m m, u n l es s ot h e rwi se n oted . Th e to l e ra n ces o n t h e m od u l e co n n ecto r l ocati n g peg h o l es (d i m e n s i o n s [ 1 6. 5 0, 6.00] & [ 1 6. 5 0, 1 8 .00] ) s h o u l d b e ± 0. 10 m m . Fig u re 5 – Mod u le mecha nica l d i mensions # 8. 2 . Therma l So l utio ns # 8.2. 1 Heatspreader: HTS ![11.00 5.00\n6.00\nM2.5*2PCS\nM2.5*4PCS](.cexpress-ar-50m-00014-1020-12/0ec286aa31e66874feabad11e5cf7046dd8e1306e507d74d2a9393433465f40e.jpg) ![95.00±0.5\n95.00±0.5\n65.00\n87.00\n4.00 87.00\n76.00\n15.00\n4.00 87.00\n6-M2.5*P0.45\nEffective screw holes depth 6.0mm](.cexpress-ar-50m-00014-1020-12/209bbf6613b5b7418b95fa66f92aa18d969a5e84a8b0eb024f65660fca80e93a.jpg) D i m e n s i o n s: m m Fig u re 6 – H eatspreader HTS # 8.2.2 Heatsin k: TH S ![M2.5*2pcs\n16.2\n5\n6\nM2.5*4pcs](.cexpress-ar-50m-00014-1020-12/01a4f0680bd864d6ea2c6af4127bf656d0bf7ef3a65727eaa9071934f8aab909.jpg) ![95\n95](.cexpress-ar-50m-00014-1020-12/1d99d04c049d94eba25c5632884a62df0bfb105ac57f17b4b83feef154166b92.jpg) ![87\n76\n4\n87](.cexpress-ar-50m-00014-1020-12/32ff509e43c2925b87998870c26c79e6e8cabf0f293c96bf98e8148e2494b98a.jpg) D i m e n s i o n s: m m Fig u re 7 – H eatsi n k TH S # 8.2. 3 Heatsin k H ig h Profile: TH SH ![This image is a technical engineering drawing of a heat sink assembly, displaying five orthographic and isometric projections with dimension callouts.\n\n**Top Left (Side Profile):**\nShows the cross-section of the fins and mounting tabs.\n* Dimensions: '35.20' (total height), '5.00' (height of the top plate above the fins), and '6.00' (width of the mounting tab).\n\n**Top Right (Isometric View):**\nShows a 3D perspective of the unit with heat pipes and mounting posts.\n* Callout 1: 'M2.5*2PCS' pointing to the heat pipe mounting points.\n* Callout 2: 'M2.5*4PCS' pointing to the four corner mounting posts.\n\n**Bottom Left (Front View):**\nShows the full face of the fin stack.\n* Dimensions: '95.00±0.5' for both width and height. Four mounting holes are visible at the corners.\n\n**Center (Side Profile):**\nA thin cross-sectional view of the fin stack.\n\n**Bottom Right (Top View):**\nShows the layout of the heat pipes and mounting holes.\n* Dimensions: '4.00' (distance from edge), '87.00' (horizontal spacing), '76.00' (vertical spacing), '4.00' (horizontal offset), and '15.00' (vertical offset).\n* Text Callout: '6-M2.5*P0.45' pointing to the screw holes.\n* Text Below Callout: 'Effective screw holes depth 6.0mm'](.cexpress-ar-50m-00014-1020-12/148e2893f470fe916ade7c469f8447681513ec8a04ba3c3f7c764cf02cb10c4c.jpg) D i m e n s i o n s: m m Fig u re 8 – H eatsi n k H ig h Profi le: TH S H # 8.2.4 Heatsin k with Fa n: TH SF ![6\n37.7\n5](.cexpress-ar-50m-00014-1020-12/3175fe844ee8d9f19bd0458a5982aa29f17bc73248b5f54728d2f05979449e4d.jpg) ![3D CAD rendering of a CPU fan with visible blades and cooling fins (no text or symbols)](.cexpress-ar-50m-00014-1020-12/4d1165bca7b43bd493bb3c9afc8d1af737cd9e1affbea5aac4ea514987a1cf97.jpg) ![95\n95](.cexpress-ar-50m-00014-1020-12/d903787e6b066bb0a47b9ef5d55e7fc8f7245c86e81c5cddd672045e6b4398b7.jpg) ![M2.5*2pcs\nM2.5*4pcs\n76\n87\n4\n4\n87](.cexpress-ar-50m-00014-1020-12/acb9435918cafa9285e3f81cbbe37ea9e5b16a47139c36e774d9b0c521c4c91f.jpg) D i m e n s i o n s: m m Fig u re 9 – H eatsi n k with Fa n : TH S F [🔗 Link to the original document](.cexpress-ar-50m-00014-1020-12/cexpress-ar-50m-00014-1020-12.pdf)