# cExpress-ASL/ALN

User’s Guide

intel

![Close-up of a green printed circuit board with integrated circuits and gold contacts (no readable text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/66a6d88798084ec0b9eba05680a17f4feaed0cc6f11a8ec9acfce60de3640f76.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-02-05</td><td>AL</td></tr><tr><td>1.1</td><td>Software support updated</td><td>2025-07-10</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a yellow triangular warning sign with a thick black border. Centered inside the triangle is a black exclamation point. The sign is flanked by vertical black bars on the left and right sides.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/59a911f4870e2c10c107dae7d56e1c9bb5f0a8a66468d6aaf2fead21fe505bd5.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a line drawing of a wheeled trash bin that is crossed out by a large black 'X'. Below the crossed-out bin, there is a thin horizontal black line followed by a solid black rectangular block.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/2352ded3e1e20df7ff27005cf681d4b93e068bdc45e957eb6209cbfcf2b708d5.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a digital icon of a document or memo pad. It features a thick red outline forming a square shape with a folded corner at the bottom right. Inside the outline, two horizontal red lines are centered, representing lines of text or content.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/b13688a08a246efd0b7b4cf15382c35994df0b486bd7118f39c8c3daa0e62474.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow equilateral triangle pointing upwards, outlined by a thin white border. Inside the triangle is a black exclamation point centered vertically and horizontally. It is set against a plain white background.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/8472aa206d87aaa945c84b6153a6e655c9d850523f00ada4e89e5312a91a865b.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![A red triangle with a white exclamation point in the center.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/05d8ce7eb013c855558741ad1cc3087f74a153eb821dcd8d20d6f9c6be117efe.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

List of Figures ...

1. Introduction ... .12
2. Specifications.. .13

2.1 Core System... . 13

2.2 Video.... ... 14

2.2.1 Display Interface Support.. . 15

2.3 Audio ... ... 16

2.4 Expansion Bus ... ... 16

2.5 Ethernet ... ... 16

2.6 Multi I/O and Storage... . 17

2.7 Trusted Platform Module (TPM).. .. 18

2.8 SEMA Board Controller .. .. 18

2.9 Debug... ... 19

2.10 Power.... ... 19

2.11 Mechanical and Environmental .. . 20

3. Block Diagram .. ..21
4. Pinout and Signal Descriptions ... .22

4.1 Pin Summary .. . 22

4.2 Signal Terminology Descriptions... . 27

4.3 AB Connector Signal Descriptions .. . 28

4.3.1 Audio... ... 28

4.3.2 Analog VGA.. . 29

4.3.3 LVDS or eDP.... ... 30

4.3.4 Gigabit Ethernet... ... 33

4.3.5 SATA . . 34

4.3.6 PCI Express... ... 35

4.3.7 LPC Bus.. . 37

4.3.8 USB.. . 38

4.3.9 SPI Bus (BIOS only).. . 39

4.3.10 Miscellaneous.. .... 40

4.3.11 SMBus . . 41

4.3.12 I 2C Bus... . 41
4.3.13 General Purpose I/O (GPIO) .. . 42
4.3.14 Serial Interface Signals.. .... 42
4.3.15 Power and System Management . .... 43
4.3.16 Power and Ground .. ... 44

4.4 CD Connector Signal Descriptions.. . 45

4.4.1 USB 3.0 Extensions . ... 45
4.4.2 PCI Express.. .... 46
4.4.3 DDI1 Port... . 47
4.4.4 DDI2 Port... ... 50
4.4.5 DDI3 Port... . 53
4.4.6 PCIe Graphics Port (PEG)... . 53
4.4.7 Module Type Definition .. . 53
4.4.8 Power and Ground .. . 54

5. Additional Features ... ...55

5.1 Module Feature Locations .. . 55
5.2 Debug Connector... . 56
5.3 Status LEDs... . 57
5.4 Exception Codes.. . 58
5.5 Fan Connector... . 59
5.6 BIOS Default Reset Button... . 60
5.7 BIOS Boot Select... . 61

6. System Resources ... ..62

6.1 System Memory Map... . 62
6.2 I/O Map ... ... 66
6.3 Interrupt Request (IRQ) Lines .. . 68
6.4 PCI Configuration Space Map.. . 70
6.5 PCI Interrupt Routing Map ... . 71
6.6 SMBus Address Table .. . 71

7. BIOS Setup... ..72

7.1 Menu Structure... . 72
7.2 Main .... . 73

7.2.1 BIOS Information.. . 73
7.2.2 System Information.. . 74
7.2.3 Board Information . . 74
7.2.4 System Date and Time.. . 75
7.3 Advanced ... ... 76

7.3.1 CPU Configuration... . 76

7.3.2 Power & Performance Configuration... . 77

7.3.3 Intel® Time Coordinated Computing.. . 87

7.3.4 Graphic Configuration .. . 89

7.3.5 Power Management .. . 91

7.3.6 System Management . . 92

7.3.7 Thermal Management... . 93

7.3.8 Watchdog Timer... . 94

7.3.9 Super I/O Configuration.... . 95

7.3.10 Miscellaneous.. ... 96

7.3.11 USB Configuration.. . 97

7.3.12 NVMe Configuration .. . 98

7.3.13 AMI Graphics Output Protocol Policy .. ... 98

7.3.14 Serial Console Redirection .. ... 98

7.3.15 Network Stack Configuration... ...100

7.3.16 Trusted Computing ... ..100

7.4 Chipset .. ....101

7.4.1 System Agent (SA) Configuration .. ..101

7.4.2 PCH-I/O Configuration. ..106

7.5 Security .... ...114

7.5.1 Secure Boot menu .. ...114

7.6 Boot .... ..115

7.6.1 Boot Configuration.. ..115

7.7 Save & Exit.... ..116

8. BIOS Checkpoints, Beep Codes .... . 117

8.1 Status Code Ranges . ..118

8.2 Standard Status Codes.. ..119

8.2.1 SEC Phase.. ...119

8.2.2 SEC Beep Codes... ....120

8.2.3 PEI Phase.. ....120

8.2.4 PEI Beep Codes .. ..124

8.2.5 DXE Status Codes.. ..125

8.2.6 DXE Beep Codes.. ..129

8.2.7 ACPI/ASL Checkpoint .. ..130

8.3 OEM-Reserved Checkpoint Ranges.. ..131

9. Software Support ... . 132

9.1 Operation System... ..132

9.2 Other Software ... ...132

10.Mechanical and Thermal.. . 133

10.1 Module Dimensions – Top View .. ..133
10.2 Module Dimensions – Side View .. ..134
10.3 Height of Processor and Static Compressive Load ... ..134
10.4 Thermal Solutions . ..135

10.4.1 Heatspreader: HTS.. ...135

10.4.2 Heatsink: THS.... ...136

10.4.3 Heatsink High Profile: THSH.. .137

10.4.4 Heatsink with Fan: THSF.. ...138

10.5 Board to Board Connectors.. ..139
10.6 Mounting Method.. ...140
10.7 Standoff Types... ..141
10.8 Installation ... ....142

# List of Figures

Figure 1 – Module function diagram... ..21

Figure 2 - Module rear side row and pin numbering ....... ...22

Figure 3 – Module feature locations (top side) ... ..55

Figure 5 – cExpress-ASL and debug module.. .56

Figure 6 – Module mechanical dimensions ..... .. 134

Figure 7 – Heatspreader: HTS...... .. 135

Figure 8 – Heatsink: THS.... .. 136

Figure 9 – Heatsink high profile: THSH... .. 137

Figure 10 – Heatsink with fan: THSF ...... . 138

# 1 Introduction

The cExpress-ASL/ALN is a COM.0 R3.1-compliant COM Express® Compact Size Type 6 module powered by Intel® Atom® x7000 series processors (formerly “Amston Lake and Alder Lake N”). It features up to 8 Gracemont architecture cores, offering scalability from 2 to 8 cores with a thermal design power (TDP) range of 6-15W. The module integrates Intel® UHD Graphics Gen12 with up to 32 execution units (EUs), making it ideal for a wide range of IoT applications. Its low power consumption is excellent for industrial automation and robotics control, edge medical equipment, multi-function printers, and more.

The cExpress-ASL/ALN supports up to 16GB (2x 8GB) LPDDR5 memory with a maximum frequency of 4800 MT/s. With Intel’s real-time TCC/TSN features and extended longevity in its class, it is designed for mission-critical stationary and mobile edge applications.

The integrated Intel® UHD Graphics Gen12 includes support for OpenGL 4.6, DirectX 12, OpenCL 3.0, Vulkan 1.2, Intel® Clear Video HD Technology, and DirectX Video Acceleration (DXVA) for H.265/HEVC 4K60 10-bit, VP9 hardware codecs, and AV1 hardware decode. It also offers a High Dynamic Range for enhanced picture quality and has upgraded digital content protection to HDCP 2.2. Graphics outputs include LVDS and two DDI ports, which facilitate HDMI/DVI/DisplayPort and eDP/VGA, with a maximum 4K resolution. Additionally, an optional USB-C port that enables data transfer data and DisplayPort ALT Mode is available as an alternative to DDI 1, based on project requirements. The cExpress-ASL is specifically designed for customers needing essential graphics processing with different configurations, providing a solution to reduce development time by outsourcing custom core logic.

The cExpress-ASL/ALN additionally offers headless CPU SKUs with up to 8 cores at HFM of 2.4GHz. It is well-suited for compute-intensive workload applications, such as entry networks and edge equipment with software-defined network security.

Input/output capabilities include default five PCIe Gen3 lanes, with the option to expand to a maximum of eight PCIe Gen3 lanes based on project requirements. The module provides a single onboard 2.5 Gigabit Ethernet port with optional Time-Sensitive Network (TSN) support, up to 4x USB 3.2/2.0 ports via USB hub, 4x USB 2.0 ports, and up to 2x SATA 6 Gb/s ports. An optional onboard eMMC with a minimum capacity of 32GB is available based on project needs, as well as an additional FFC connector for one MIPI-CSI 4 lanes camera, also provided on a project basis. Support is provided for SMBus and I2C. The module features SPI AMI EFI BIOS with CMOS backup, supporting a remote console, a hardware monitor, and a watchdog timer.

# Specifications

# 2.1 Core System

# CPU

Intel® Atom® x7000 RE and C series Processor (formerly Amston Lake)

• Intel® Atom® x7835RE, 1.3(3.6) GHz, 12W, 8C/32EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7433RE, 1.5(3.4) GHz, 9W, 4C/32EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7213RE, 2.0(3.4) GHz, 9W, 2C/16EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7211RE, 1.0(3.2) GHz, 6W, 2C/16EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7809C, 2.4(3.6) GHz, 25W, 8C (IBECC, TCC/TSN capable) (no GPU/Headless)
• Intel® Atom® x7405C, 2.2(3.4) GHz, 12W, 4C (IBECC, TCC/TSN capable) (no GPU/Headless)
• Intel® Atom® x7203C, 2.0(3.2) GHz, 9W, 2C (IBECC, TCC/TSN capable) (no GPU/Headless)

Intel® Atom® x7000 E & N series Processor (formerly Alder Lake N)

• Intel® Atom® x7425E, 1.5(3.4) GHz, 12W, 4C/24EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7213E, 1.7(3.2) GHz, 10W, 2C/16EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7211E, 1.0(3.2) GHz, 6W, 2C/16EU (IBECC, TCC/TSN capable)
• Intel® Atom® x7211RE, 1.0(3.2) GHz, 6W, 2C/16EU (IBECC, TCC/TSN capable)
• Intel® Core® i3-N305, 1.8(3.8) GHz, 15W, 8C/32EU (IBECC capable)
• Intel® Processor® N200, 1.0(3.7) GHz, 6W, 4C/32EU (IBECC capable)
• Intel® Processor® N97, 2.0(3.6) GHz, 12W, 4C/24EU (IBECC capable)
• Intel® Processor® N50, 1.0(3.4) GHz, 6W, 2C/16EU (IBECC capable)

Supporting: Intel® VT (including VT-x, VT-d, VT-x with Extended Page Tables), Intel® SSE4.2, Intel® 64 Architecture, Intel® AVX2, Intel® OS Guard, Intel® Boot Guard, Mode-based Execute Control, Intel® AES-NI (availability of features may vary between processor SKUs)

![This is a digital icon featuring a red outline of a document or page with a folded top-right corner. Inside the red border, there are two horizontal red bars; the top bar is shorter and centered above a longer bottom bar.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/5b858b3778b9c17d2889e19957424b40f0129bf1565bbd8068888ebe6c865d05.jpg)

Note: TCC/TSN and IBECC capabilities and headless SKUs are available on a project basis. Please note that not all SKUs are standard in terms of features, they may vary based on specific requirements. For detailed ordering information, refer to the datasheet or contact your local ADLINK representative.

# Memory

Up to 16GB (2x 8GB) soldered down LPDDR5, maximum 4800 MT/s. Memory capacity ranges from 4GB, 8GB to 16GB. IBECC is supported on a project basis with specific BIOS and HW settings.

![The image displays a red icon resembling a document or memo. It features a square outline with a folded bottom-right corner. Inside the outline are three horizontal red lines of varying lengths, simulating lines of text.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/6674cec9e7814265f0aadca791a5a86007b75d486065630a17875484ea90dce8.jpg)

Note: Please contact your local ADLINK representative for the standard memory configuration.

# Embedded BIOS

AMI Aptio V UEFI with CMOS backup in 32 MB SPI BIOS, dual BIOS by build option

# 2.2 Video

# GPU

Gen12 Intel® UHD Graphics architecture with up to 32 execution units

# Supported Features

• 3 independent and simultaneous combinations of DisplayPort/HDMI/LVDS/eDP/VGA and display alternative mode through USB-C graphics outputs (4x 4K @60Hz)
• eDP optional in place of LVDS, VGA optional in place of DDI 2, USB-C optional in place of DDI 1 (build option required)
• DirectX Video Acceleration (DXVA) support for accelerated video processing
• 4K60 8b AVC, 4K60 10b HEVC/VP9/SCC, 4K60 10b AV1 HW decode

• 4K60 8b AVC, 4K60 10b HEVC/VP9/SCC HW encode
• DirectX up to 12
• OpenGL up to 4.6 support
• OpenCL up to 3.0 support
• Vulkan up to 1.2 support
Graphics HW Virtualization (SR-IOV) support
• HDCP 2.2 capable

![The image displays a simple icon featuring a red outline of a document or page. Inside the red border, there are two horizontal red lines centered vertically, representing text. The background is white.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/771fb75c1e7f18832ec0fa7f4e74d01ed7b8789044a6f06ced8e17f9e4349bed.jpg)

Note: Availability of features is dependent on the operating system used (Windows 10 LTSC 64-bit, Windows 11 LTSC 64-bit, Linux 64-bit).

# 2.2.1 Display Interface Support

LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, it supports DE mode and Hsync/Vsync mode.

Max. resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats are supported.

eDP: eDP 1.4b up to 4 lane support, in place of LVDS (build option)

DDI x2: Digital Display Ports (DDI) support DisplayPort 1.4, HDMI 2.0b or DVI

VGA: VGA support, in place of DDI 2; max. resolution 1920x1200@60Hz (build option)

USB-C DP Alternative mode: DP output through USB Type C connector, in place of DDI 1 (build option)

![The image displays a red icon on a white background. It depicts a square-shaped piece of paper with rounded corners and a curled bottom-right corner. Inside the red outline, there are two horizontal red lines centered near the top, resembling text or a list.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/b49a857e3b55fc49e3bff8a5e31c5856e7a3993aee8eed0cf3f5428cb1e60a66.jpg)

Note: USB-C is a build option (HW and BIOS) supported on a project basis in place of DDI 1 channels. USB-C support also requires specific carrier board design.

# 2.3 Audio

Intel® HD Audio integrated

Located on the carrier Express-BASE6 or Express-BASE6 R3.1 (ALC886 standard support)

# 2.4 Expansion Bus

# 5 PCI Express x1 Gen3 default, maximum 8 PCI Express Lanes:

Lane 0-1 (configurable to 2 x1 or 1 x2)

Lane 2-3 (configurable to 2 x1 or 1 x2)

Lane 4 (1 x1)

Lane 5-7 (3 x1) (build option, PCIe lane 5 muxed with SATA 1, PCIe lane 6 muxed with SATA 0, PCIe lane 7 muxed with GbE Ethernet)

Up to 5 PCIe based devices, including on-board i226 LAN controller

Other: SMBus (system), I2 C (user), LPC bus (via eSPI to LPC bridge IC), GSPI (build option)

I2C from CPU is supported by build option and project basis

SMBus from EC (embedded controller) is supported by build option and project basis

Additional GP\_SPI (general purpose SPI by project basis)

# 2.5 Ethernet

2.5GbE Intel® Ethernet Controller I226 Series (V, IT or LM version)

Supports up to 2.5GbE and 1000/100/10 Mbit/s connections

IT version supports the TSN feature on Linux OS. GbE0\_SDP is available if TSN support is enabled (build option, also paired with selected CPU SKU).

# 2.6 Multi I/O and Storage

# USB

2x USB 3.2/2.0/1.1 (USB 0,1), 6x USB 2.0/1.1 (USB 2,3,4,5,6,7)

Up to 4x USB 3.2/2.0/1.1 (USB 0,1,2,3) through a USB 3 hub (build option)

SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling

![The image displays a simple icon featuring a red outline of a document or page with the bottom right corner folded. Inside the outline, there are two horizontal red lines, suggesting text or a list.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/df7b421bc8f5e3933676df7fa3fdb4bf70f730aeed600c4514b4a793f3aacdc3.jpg)

Note: The carrier board must be designed for Gen2 operation. USB 0,1,2, and 3 are backward compatible with USB 2.0/1.1.

# USB Type-C

1x USB-C is supported as a build option, in place of DDI 1. HW and BIOS settings are required and it also depends on the carrier board design. Up to USB 3.2 speed data transmission and DP alternative mode.

# SATA

2x SATA 6Gb/s (SATA 0,1)

SATA 0 muxed with PCIe lane 6. SATA 1 muxed with PCIe lane 5.

![The image shows a red icon of a document or memo with a folded top-right corner. Inside the white interior, there are two horizontal red lines.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/9606f33ed41c64eef9ab75eed84ac2eae3d8454aea3c9d787aa4a7c8c130f5a0.jpg)

Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board

# GPIO or SD

4 GPO and 4 GPI (GPI with interrupt)

GPIO default from EC, build option from CPU

# On-board Storage

Soldered type eMMC 5.1, available capacities: 32GB to 128GB. Build option supported on a project basis.

# UART

Two UART interfaces SER0 and SER1 RX/TX on module

Console Redirection via COM 1 or COM 2 selectable in BIOS

Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via the embedded controller</td><td>4</td><td>0x3F8</td><td>Yes</td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via the embedded controller</td><td>3</td><td>0x2F8</td><td>Yes</td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on the carrier board</td><td>5</td><td>0x240</td><td>Yes</td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on the carrier board</td><td>7</td><td>0x248</td><td>Yes</td></tr></table>

![A red icon depicting a document with a folded bottom-right corner and two horizontal lines inside.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/598f3a3500931d4aaae3d41eb4e1ca369bfc4399c8cace8cb52de555206a9776.jpg)
Note: SER0 and SER1 from the SoC HSUART are build options supported on a project basis.

# 2.7 Trusted Platform Module (TPM)

Chipset: Infineon solution

Type: TPM 2.0 (SPI bus based)

# 2.8 SEMA Board Controller

Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general-purpose I2 C, failsafe BIOS (dual BIOS, build option support), watchdog timer, and fan control.

# 2.9 Debug

30-pin flat cable connector for use with DB-30 x86 debug module.

Supports embedded controller access, SPI BIOS flashing, internal power rail test points, and debug LEDs.

# 2.10 Power

Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)

Standard Voltage Input: ATX: 12V±5% / 5Vsb ±5% or AT: 12V±5%

Wide Voltage Input: ATX: 8.5-20V, 5Vsb ±5% or AT: 8.5-20V

Power Management: ACPI 5.0 compliant, Smart Battery support

Power States: C1-C6, S0, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)

ECO Mode support for deep S5 for 5Vsb power saving

# Power Consumption

Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.

# 2.11 Mechanical and Environmental

# Form Factor and specification

PICMG COM Express Rev 3.1 (COM.0 R3.1), Type 6, Compact size 95 x 95 mm

# Operating Temperature

Standard

0°C to 60°C (wide voltage input)

Storage: -20°C to 80°C

Extreme Rugged

-40°C to 85°C

Storage: -40°C to 85°C (extreme rugged, build option by project basis)

# Humidity

5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# HALT tested

Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

# 3. Block Diagram

![**Central Block:**\n*   **Intel Amston Lake Intel Alder Lake N** (Red block)\n\n**Memory Blocks (Top Left):**\n*   **LPDDR5 2/4/8GB** (Connected twice to the central block)\n\n**Left-Side Interfaces and Intermediaries:**\n*   **eDP/LVDS** connects to **eDP to LVDS**. (Note: **eDP x4** is labeled above this block).\n*   **VGA** connects to **DP to VGA** (Build option).\n*   **USB 2.0 (0:7)** connects directly.\n*   **Max. 2.5GbE** connects to **LAN Intel i226**.\n*   **PCIe (0:1)** connects via label **2 x1, 1 x2** to **HSIO(2:3)**.\n*   **PCIe (2:3)** connects via label **2 x1, 1 x2** to **HSIO(8:9)**.\n*   **SATA (0)** connects to **HSIO(10)**.\n*   **SATA (1)** connects to **HSIO(11)**.\n*   **PCIe (4)** connects to **HSIO(0)**.\n*   **PCIe (5)** connects via a dashed line.\n*   **HDA** connects directly.\n*   **LPC/eSPI** connects to **eSPI to LPC** (Build option).\n*   **UART (0:1)**, **SMBus**, **I2C**, **GSPI (OEM)**, and **SPI** connect to the **Embedded Controller**.\n\n**Right-Side Interfaces and Intermediaries:**\n*   **DDI1/USBC_1** and **DDI2** connect directly from the top right.\n*   **DDIA** connects to **eDP to LVDS**.\n*   **DDIB** connects to **DP to VGA**.\n*   **MIPI-CSI x4** connects to **FFC connector** and **eMMC 5.1 (32-128GB)** (Build option).\n*   **HSIO(6)** connects to **LAN Intel i226**.\n*   **USB3 (0)** and **USB3 (1)** connect directly.\n*   **USB3 (2:3)** connects via **USB3.2 Gen2 Hub** (Build option).\n*   **PCIe (6)** and **PCIe (7)** connect via dashed lines.\n\n**Bottom Section (Security and Management):**\n*   **SPI** and **GP_SPI** connect to **TPM 2.0**.\n*   **eSPI** connects to **BIOS Flash** (Build option) and the **Embedded Controller**.\n*   The **Embedded Controller** connects to **FAN connector** and **LM73**.\n\n**Internal Ports on Central Block:**\n*   **HSIO(0)**, **HSIO(2:3)**, **HSIO(6)**, **HSIO(8:9)**, **HSIO(10)**, **HSIO(11)**\n*   **HSUART**, **SMBus**, **I2C**\n*   **eSPI**, **SPI**, **GP_SPI**](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/d6e2bdbecdbfe748726e793faf94365553a2e62683163aedd1ff02aa514799dd.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# 4.1 Pin Summary

The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 6 in the PICMG COM.0 R3.1 specification. Signals described in the specification but not supported on the cExpress-ASL/ALN are marked with strikethrough.

![D1\nCD\nC1\nB1\nAB\nA110\nA1](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/86dda18a9f36713917e94bf2f3944f69d46e87a24780b04ebf28f6c6e9628644.jpg)

Figure 2 - Module rear side row and pin numbering

<table><tr><td colspan="2">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>GND (FIXED)</td><td>B1</td><td>GND (FIXED)</td><td>C1</td><td>GND FIXED)</td><td>D1</td><td>GND FIXED)</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td>B2</td><td>GBE0_ACT#</td><td>C2</td><td>GND</td><td>D2</td><td>GND</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td>B3</td><td>LPC_FRAME#/ESPI_CS0# $^{1}$ </td><td>C3</td><td>USB_SSRX0-</td><td>D3</td><td>USB_SSTX0-</td></tr><tr><td>A4</td><td>GBE0_LINK_MID#</td><td>B4</td><td>LPC_AD0/ESPI_IO_0 $^{1}$ </td><td>C4</td><td>USB_SSRX0+</td><td>D4</td><td>USB_SSTX0+</td></tr><tr><td>A5</td><td>GBE0_LINK_MAX#</td><td>B5</td><td>LPC_AD1/ESPI_IO_1 $^{1}$ </td><td>C5</td><td>GND</td><td>D5</td><td>GND</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td>B6</td><td>LPC_AD2/ESPI_IO_2 $^{1}$ </td><td>C6</td><td>USB_SSRX1-</td><td>D6</td><td>USB_SSTX1-</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td>B7</td><td>LPC_AD3/ESPI_IO_3 $^{1}$ </td><td>C7</td><td>USB_SSRX1+</td><td>D7</td><td>USB_SSTX1+</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td><td>C8</td><td>GND</td><td>D8</td><td>GND</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td><td>C9</td><td>USB_SSRX2-1</td><td>D9</td><td>USB_SSTX2-1</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td>B10</td><td>LPC_CLK/ESPI_CK $^{1}$ </td><td>C10</td><td>USB_SSRX2+1</td><td>D10</td><td>USB_SSTX2+1</td></tr><tr><td>A11</td><td>GND (FIXED)</td><td>B11</td><td>GND (FIXED)</td><td>C11</td><td>GND (FIXED)</td><td>D11</td><td>GND (FIXED)</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td>B12</td><td>PWRBTN#</td><td>C12</td><td>USB_SSRX3-1</td><td>D12</td><td>USB_SSTX3-1</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td>B13</td><td>SMB_CK</td><td>C13</td><td>USB_SSRX3+1</td><td>D13</td><td>USB_SSTX3+1</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td>B14</td><td>SMB_DAT</td><td>C14</td><td>GND</td><td>D14</td><td>GND</td></tr><tr><td>A15</td><td>SUS_S3#</td><td>B15</td><td>SMB_ALERT#</td><td>C15</td><td>USB4_1_LSTX $^{1}$ </td><td>D15</td><td>DDI1_CTRLCLK_AUX+/USB4_1_AUX+1</td></tr><tr><td>A16</td><td>SATA0_TX+</td><td>B16</td><td>SATA1_TX+</td><td>C16</td><td>USB4_1_LSRX $^{1}$ </td><td>D16</td><td>DDI1_CTRLDATA_AUX-/USB4_1_AUX-1</td></tr><tr><td>A17</td><td>SATA0_TX-</td><td>B17</td><td>SATA1_TX-</td><td>C17</td><td>USB4_RT_ENA $^{1}$ </td><td>D17</td><td>USB4_PD_I2C_ALERT# $^{1}$ </td></tr><tr><td>A18</td><td>SUS_S4#</td><td>B18</td><td>SUS_STAT#/ESPI_RESET# $^{1}$ </td><td>C18</td><td>GND</td><td>D18</td><td>PMCALERT# $^{1}$ </td></tr><tr><td>A19</td><td>SATA0_RX+</td><td>B19</td><td>SATA1_RX+</td><td>C19</td><td>PCIE_RX6+1</td><td>D19</td><td>PCIE_TX6+1</td></tr><tr><td>A20</td><td>SATA0_RX-</td><td>B20</td><td>SATA1_RX-</td><td>C20</td><td>PCIE_RX6-1</td><td>D20</td><td>PCIE_TX6-1</td></tr><tr><td>A21</td><td>GND (FIXED)</td><td>B21</td><td>GND (FIXED)</td><td>C21</td><td>GND (FIXED)</td><td>D21</td><td>GND (FIXED)</td></tr><tr><td>A22</td><td>SATA2_TX+</td><td>B22</td><td>SATA3_TX+</td><td>C22</td><td>PCIE_RX7+1</td><td>D22</td><td>PCIE_TX7+1</td></tr><tr><td>A23</td><td>SATA2_TX-</td><td>B23</td><td>SATA3_TX-</td><td>C23</td><td>PCIE_RX7-1</td><td>D23</td><td>PCIE_TX7-1</td></tr><tr><td>A24</td><td>SUS_S5#</td><td>B24</td><td>PWR_OK</td><td>C24</td><td>DDI1_HPD</td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>SATA2_RX+</td><td>B25</td><td>SATA3_RX+</td><td>C25</td><td>SML0_CLK $^{1}$ </td><td>D25</td><td>GND</td></tr><tr><td>A26</td><td>SATA2_RX-</td><td>B26</td><td>SATA3_RX-</td><td>C26</td><td>SML0_DAT $^{1}$ </td><td>D26</td><td>DDI1_PAIR0+/USB4_1_SSTX0+1</td></tr><tr><td>A27</td><td>BATLOW#</td><td>B27</td><td>WDT</td><td>C27</td><td>SML1_CLK $^{1}$ </td><td>D27</td><td>DDI1_PAIR0-/USB4_1_SSTX0-1</td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td>B28</td><td>HDA_SDIN2/SNDW0_CLK $^{2}$ </td><td>C28</td><td>SML1_DAT $^{1}$ </td><td>D28</td><td>GND</td></tr><tr><td>A29</td><td>HDA_SYNC</td><td>B29</td><td>HDA_SDIN1/SNDW0_DAT $^{2}$ </td><td>C29</td><td>USB4_PD_I2C_CLK $^{1}$ </td><td>D29</td><td>DDI1_PAIR1+/USB4_1_SSRX0+1</td></tr><tr><td>A30</td><td>HDA_RST#</td><td>B30</td><td>HDA_SDINO</td><td>C30</td><td>USB4_PD_I2C_DAT $^{1}$ </td><td>D30</td><td>DDI1_PAIR1-/USB4_1_SSRX0-1</td></tr><tr><td>A31</td><td>GND (FIXED)</td><td>B31</td><td>GND (FIXED)</td><td>C31</td><td>GND (FIXED)</td><td>D31</td><td>GND (FIXED)</td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td>B32</td><td>SPKR</td><td>C32</td><td>DDI2_CTRLCLK_AUX+/USB4_2_AUX+</td><td>D32</td><td>DDI1_PAIR2+/USB4_1_SSTX1+1</td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td>B33</td><td>I2C_CK</td><td>C33</td><td>DDI2_CTRLDATA_AUX-/USB4_2_AUX-</td><td>D33</td><td>DDI1_PAIR2-/USB4_1_SSTX1-1</td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS1</td><td>B34</td><td>I2C_DAT</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td>B35</td><td>THRM#</td><td>C35</td><td>USB4_2_LSTX1</td><td>D35</td><td>USB4_2_LSRX1</td></tr><tr><td>A36</td><td>USB6-</td><td>B36</td><td>USB7-</td><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td>D36</td><td>DDI1_PAIR3+/USB4_1_SSRX1+1</td></tr><tr><td>A37</td><td>USB6+</td><td>B37</td><td>USB7+</td><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td>D37</td><td>DDI1_PAIR3-/USB4_1_SSRX1-1</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td>B38</td><td>USB_4_5_OC#</td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td>D38</td><td>GND</td></tr><tr><td>A39</td><td>USB4-</td><td>B39</td><td>USB5-</td><td>C39</td><td>DDI3_PAIR0+</td><td>D39</td><td>DDI2_PAIR0+/USB4_2_SSTX0+</td></tr><tr><td>A40</td><td>USB4+</td><td>B40</td><td>USB5+</td><td>C40</td><td>DDI3_PAIR0-</td><td>D40</td><td>DDI2_PAIR0-/USB4_2_SSTX0-</td></tr><tr><td>A41</td><td>GND (FIXED)</td><td>B41</td><td>GND (FIXED)</td><td>C41</td><td>GND (FIXED)</td><td>D41</td><td>GND (FIXED)</td></tr><tr><td>A42</td><td>USB2-</td><td>B42</td><td>USB3-</td><td>C42</td><td>DDI3_PAIR1+</td><td>D42</td><td>DDI2_PAIR1+/USB4_2_SSRX0+</td></tr><tr><td>A43</td><td>USB2+</td><td>B43</td><td>USB3+</td><td>C43</td><td>DDI3_PAIR1-</td><td>D43</td><td>DDI2_PAIR1-/USB4_2_SSRX0-</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td>B44</td><td>USB_0_1_OC#</td><td>C44</td><td>DDI3_HPD</td><td>D44</td><td>DDI2_HPD</td></tr><tr><td>A45</td><td>USB0-</td><td>B45</td><td>USB1-</td><td>C45</td><td>GP_SPI_CS#2</td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>USB0+</td><td>B46</td><td>USB1+</td><td>C46</td><td>DDI3_PAIR2+</td><td>D46</td><td>DDI2_PAIR2+/USB4_2_SSTX1+</td></tr><tr><td>A47</td><td>VCC_RTC</td><td>B47</td><td>ESPI_EN#1</td><td>C47</td><td>DDI3_PAIR2-</td><td>D47</td><td>DDI2_PAIR2-/USB4_2_SSTX1-</td></tr><tr><td>A48</td><td>RSMRST_OUT#</td><td>B48</td><td>USB0_HOST_PRSNT</td><td>C48</td><td>RSVD</td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GBE0_SDP1</td><td>B49</td><td>SYS_RESET#</td><td>C49</td><td>DDI3_PAIR3+</td><td>D49</td><td>DDI2_PAIR3+/USB4_2_SSRX1+</td></tr><tr><td>A50</td><td>LPC_SERIRQ/ESPI_CS1#1</td><td>B50</td><td>CB_RESET#</td><td>C50</td><td>DDI3_PAIR3-</td><td>D50</td><td>DDI2_PAIR3-/USB4_2_SSRX1-</td></tr><tr><td>A51</td><td>GND (FIXED)</td><td>B51</td><td>GND (FIXED)</td><td>C51</td><td>GND (FIXED)</td><td>D51</td><td>GND (FIXED)</td></tr><tr><td>A52</td><td>PCIE_TX5+1</td><td>B52</td><td>PCIE_RX5+1</td><td>C52</td><td>PEG_RX0+</td><td>D52</td><td>PEG_TX0+</td></tr><tr><td>A53</td><td>PCIE_TX5-1</td><td>B53</td><td>PCIE_RX5-1</td><td>C53</td><td>PEG_RX0-</td><td>D53</td><td>PEG_TX0-</td></tr><tr><td>A54</td><td>GPIO</td><td>B54</td><td>GPO1</td><td>C54</td><td>TYPE0#</td><td>D54</td><td>PEG_LANE_RV#</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td>B55</td><td>PCIE_RX4+</td><td>C55</td><td>PEG_RX1+</td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td>B56</td><td>PCIE_RX4-</td><td>C56</td><td>PEG_RX1-</td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td>B57</td><td>GPO2</td><td>C57</td><td>TYPE1#</td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td>B58</td><td>PCIE_RX3+</td><td>C58</td><td>PEG_RX2+</td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td>B59</td><td>PCIE_RX3-</td><td>C59</td><td>PEG_RX2-</td><td>D59</td><td>PEG_TX2-</td></tr><tr><td>A60</td><td>GND (FIXED)</td><td>B60</td><td>GND (FIXED)</td><td>C60</td><td>GND (FIXED)</td><td>D60</td><td>GND (FIXED)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td>B61</td><td>PCIE_RX2+</td><td>C61</td><td>PEG_RX3+</td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td>B62</td><td>PCIE_RX2-</td><td>C62</td><td>PEG_RX3-</td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1</td><td>B63</td><td>GPO3</td><td>C63</td><td>GND</td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td>B64</td><td>PCIE_RX1+</td><td>C64</td><td>GND</td><td>D64</td><td>GND</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td>B65</td><td>PCIE_RX1-</td><td>C65</td><td>PEG_RX4+</td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td>B66</td><td>WAKE0#</td><td>C66</td><td>PEG_RX4-</td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2</td><td>B67</td><td>WAKE1#</td><td>C67</td><td>RAPID_SHUTDOWN</td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td>B68</td><td>PCIE_RX0+</td><td>C68</td><td>PEG_RX5+</td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td>B69</td><td>PCIE_RX0-</td><td>C69</td><td>PEG_RX5-</td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND (FIXED)</td><td>B70</td><td>GND (FIXED)</td><td>C70</td><td>GND (FIXED)</td><td>D70</td><td>GND (FIXED)</td></tr><tr><td>A71</td><td>LVDS_A0+/ eDP_TX2+ $^1$ </td><td>B71</td><td>LVDS_B0+</td><td>C71</td><td>PEG_RX6+</td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0-/ eDP_TX2- $^1$ </td><td>B72</td><td>LVDS_B0-</td><td>C72</td><td>PEG_RX6-</td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+/ eDP_TX1+ $^1$ </td><td>B73</td><td>LVDS_B1+</td><td>C73</td><td>GND</td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>LVDS_A1-/ eDP_TX1- $^1$ </td><td>B74</td><td>LVDS_B1-</td><td>C74</td><td>PEG_RX7+</td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+/ eDP_TX0+ $^1$ </td><td>B75</td><td>LVDS_B2+</td><td>C75</td><td>PEG_RX7-</td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2-/ eDP_TX0- $^1$ </td><td>B76</td><td>LVDS_B2-</td><td>C76</td><td>GND</td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN / eDP_VDD_EN $^1$ </td><td>B77</td><td>LVDS_B3+</td><td>C77</td><td>GND</td><td>D77</td><td>GND</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>B78</td><td>LVDS_B3-</td><td>C78</td><td>PEG_RX8+</td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>B79</td><td>LVDS_BKLT_EN</td><td>C79</td><td>PEG_RX8-</td><td>D79</td><td>PEG_TX8-</td></tr><tr><td>A80</td><td>GND (FIXED)</td><td>B80</td><td>GND (FIXED)</td><td>C80</td><td>GND (FIXED)</td><td>D80</td><td>GND (FIXED)</td></tr><tr><td>A81</td><td>LVDS_A_CK+/ eDP_TX3+ $^1$ </td><td>B81</td><td>LVDS_B_CK+</td><td>C81</td><td>PEG_RX9+</td><td>D81</td><td>PEG_TX9+</td></tr><tr><td>A82</td><td>LVDS_A_CK-/ eDP_TX3- $^1$ </td><td>B82</td><td>LVDS_B_CK-</td><td>C82</td><td>PEG_RX9-</td><td>D82</td><td>PEG_TX9-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK/ eDP_AUX+ $^1$ </td><td>B83</td><td>LVDS_BKLT_CTRL / eDP_BKLT_CTRL $^1$ </td><td>C83</td><td>GND</td><td>D83</td><td>GND</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT / eDP_AUX- $^1$ </td><td>B84</td><td>VCC_5V_SBY</td><td>C84</td><td>GND</td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3</td><td>B85</td><td>VCC_5V_SBY</td><td>C85</td><td>PEG_RX10+</td><td>D85</td><td>PEG_TX10+</td></tr><tr><td>A86</td><td>GP_SPI_MOSI $^2$ </td><td>B86</td><td>VCC_5V_SBY</td><td>C86</td><td>PEG_RX10-</td><td>D86</td><td>PEG_TX10-</td></tr><tr><td>A87</td><td>eDP_HPD</td><td>B87</td><td>VCC_5V_SBY</td><td>C87</td><td>GND</td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE_CK_REF+</td><td>B88</td><td>BIOS_DIS1#</td><td>C88</td><td>PEG_RX11+</td><td>D88</td><td>PEG_TX11+</td></tr><tr><td>A89</td><td>PCIE_CK_REF-</td><td>B89</td><td>VGA_RED $^1$ </td><td>C89</td><td>PEG_RX11-</td><td>D89</td><td>PEG_TX11-</td></tr><tr><td>A90</td><td>GND (FIXED)</td><td>B90</td><td>GND (FIXED)</td><td>C90</td><td>GND (FIXED)</td><td>D90</td><td>GND (FIXED)</td></tr><tr><td>A91</td><td>SPI_POWER</td><td>B91</td><td>VGA_GRN $^1$ </td><td>C91</td><td>PEG_RX12+</td><td>D91</td><td>PEG_TX12+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td>B92</td><td>VGA_BLU $^1$ </td><td>C92</td><td>PEG_RX12-</td><td>D92</td><td>PEG_TX12-</td></tr><tr><td>A93</td><td>GPO0</td><td>B93</td><td> $VGA_HSYNC^1$ </td><td>C93</td><td>GND</td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td>B94</td><td> $VGA_VSYNC^1$ </td><td>C94</td><td>PEG_RX13+</td><td>D94</td><td>PEG_TX13+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td>B95</td><td> $VGA_I2C_CK^1$ </td><td>C95</td><td>PEG_RX13-</td><td>D95</td><td>PEG_TX13-</td></tr><tr><td>A96</td><td>TPM_PP</td><td>B96</td><td> $VGA_I2C_DAT^1$ </td><td>C96</td><td>GND</td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td>B97</td><td>SPI_CS#</td><td>C97</td><td>GND</td><td>D97</td><td>GND</td></tr><tr><td>A98</td><td>SER0_TX</td><td>B98</td><td> $GP_SPI_MISO^2$ </td><td>C98</td><td>PEG_RX14+</td><td>D98</td><td>PEG_TX14+</td></tr><tr><td>A99</td><td>SER0_RX</td><td>B99</td><td> $GP_SPI_CK^2$ </td><td>C99</td><td>PEG_RX14-</td><td>D99</td><td>PEG_TX14-</td></tr><tr><td>A100</td><td>GND (FIXED)</td><td>B100</td><td>GND (FIXED)</td><td>C100</td><td>GND (FIXED)</td><td>D100</td><td>GND (FIXED)</td></tr><tr><td>A101</td><td>SER1_TX/CAN_TX</td><td>B101</td><td>FAN_PWMOUT</td><td>C101</td><td>PEG_RX15+</td><td>D101</td><td>PEG_TX15+</td></tr><tr><td>A102</td><td>SER1_RX/CAN_RX</td><td>B102</td><td>FAN_TACHIN</td><td>C102</td><td>PEG_RX15-</td><td>D102</td><td>PEG_TX15-</td></tr><tr><td>A103</td><td>LID#</td><td>B103</td><td>SLEEP#</td><td>C103</td><td>GND</td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td>B104</td><td>VCC_12V</td><td>C104</td><td>VCC_12V</td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td>B105</td><td>VCC_12V</td><td>C105</td><td>VCC_12V</td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td>B106</td><td>VCC_12V</td><td>C106</td><td>VCC_12V</td><td>D106</td><td> $VCC_{12V}^1$ </td></tr><tr><td>A107</td><td>VCC_12V</td><td>B107</td><td>VCC_12V</td><td>C107</td><td>VCC_12V</td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td>B108</td><td>VCC_12V</td><td>C108</td><td>VCC_12V</td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td>B109</td><td>VCC_12V</td><td>C109</td><td>VCC_12V</td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND (FIXED)</td><td>B110</td><td>GND (FIXED)</td><td>C110</td><td>GND (FIXED)</td><td>D110</td><td>GND (FIXED)</td></tr></table>

![A red outline icon of a document or page with a folded bottom-right corner, containing two horizontal lines inside.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/c2de276211e869c4ad184929ec27ac11392daeb5d51a31cd0bfdf153c2549b9c.jpg)

Note: Strike-through entries are not supported functions on this product.

1. eDP (in place of LVDS), VGA (in place of DDI 2), eSPI (in place of LPC), PCIe lanes 5-7 (muxed with SATA 1/0 and GbE Ethernet), USB4\_1 (in place of DDI 1, used as USB Type-C, not USB4), and GBE0\_SDP (for selected LAN controller versions) are build options supported on a project basis
2. GP\_SPI support is to be confirmed (TBC).

# 4.2 Signal Terminology Descriptions

Definitions of terms used for signal description tables

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional Input / Output</td></tr><tr><td>OD</td><td>Open drain output from the module</td></tr><tr><td></td><td></td></tr><tr><td>I 3.3V</td><td>Input 3.3V tolerant</td></tr><tr><td>I 5V</td><td>Input 5V tolerant</td></tr><tr><td>O 3.3V</td><td>Output 3.3V signal level</td></tr><tr><td>O 5V</td><td>Output 5V signal level</td></tr><tr><td>I/O 3.3V</td><td>Bi-directional signal 3.3V tolerant</td></tr><tr><td>I/O 5V</td><td>Bi-directional signal 5V tolerant</td></tr><tr><td>I/O  $3.3V_{SB}$ </td><td>Input or output 3.3V tolerant active in standby state</td></tr><tr><td></td><td></td></tr><tr><td>DDC</td><td>Display Data Channel</td></tr><tr><td>PCIE</td><td>PCI Express compatible differential signal</td></tr><tr><td>PEG</td><td>PCI Express Graphics</td></tr><tr><td>SATA</td><td>Serial ATA specification Revision 2.6 and 3</td></tr><tr><td>LVDS</td><td>Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal</td></tr><tr><td></td><td></td></tr><tr><td>P</td><td>Power Input / Output</td></tr><tr><td>REF</td><td>Reference voltage output. May be sourced from a Module power plane.</td></tr><tr><td>PDS</td><td>Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.</td></tr><tr><td></td><td></td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr></table>

# 4.3 AB Connector Signal Descriptions

4.3.1 Audio

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>AC_RST# / HDA_RST#</td><td>A30</td><td>Reset output to CODEC, active low.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>AC_SYNC / HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the CODEC(s).</td><td>O3.3VSB</td><td></td><td>PCH internal PD 20Kohm</td></tr><tr><td>AC_BITCLK / HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external CODEC(s).</td><td>I/O3.3VSB</td><td></td><td></td></tr><tr><td>AC_SDOUT / HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the CODEC.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>AC_SDIN[2:0] / HDA_SDIN[2:0]</td><td>B28B29B30</td><td>Serial TDM data inputs from up to 3 CODECs.</td><td>I/O3.3VSB</td><td></td><td>PCH internal PD 20KohmAC_SDNI2/HDA_SDIN2 not supported</td></tr></table>

4.3.2 Analog VGA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VGA_RED</td><td>B89</td><td>Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_GRN</td><td>B91</td><td>Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_BLU</td><td>B92</td><td>Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_HSYNC</td><td>B93</td><td>Horizontal sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_VSYNC</td><td>B94</td><td>Vertical sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_I2C_CK</td><td>B95</td><td>DDC clock line (I2C port dedicated to identifying VGA monitor capabilities)</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>VGA_I2C_DAT</td><td>B96</td><td>DDC data line.</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

![The image displays a red icon representing a document or file. It features a thick red outline of a rectangular piece of paper with a folded bottom-right corner (a 'dog-ear'). Inside the red border, there are two horizontal red lines centered vertically, simulating lines of text.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/d22b9e2596a11a7b97773dc1b9aec6104accf1dd9312127d75e4ab8ae994873d.jpg)
Note: VGA is a build option supported on a project basis (in place of DDI 2).

# 4.3.3 LVDS or eDP

The module default supports a single or dual channel LVDS display panel with up to 24-bit colors. A BOM option is available that removes the eDP to LVDS bridge IC and outputs the eDP signals directly. The pin mapping between eDP vs LVDS modes is described below.

<table><tr><td>Pin #</td><td>LVDS mode</td><td>eDP mode</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td>eDP_TX2+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td>eDP_TX2-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td>eDP_TX1+</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td>eDP_TX1-</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td>eDP_TX0+</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td>eDP_TX0-</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>-</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>-</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td>eDP_TX3+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td>eDP_TX3-</td></tr><tr><td>B71</td><td>LVDS_B0+</td><td>-</td></tr><tr><td>B72</td><td>LVDS_B0-</td><td>-</td></tr><tr><td>B73</td><td>LVDS_B1+</td><td>-</td></tr><tr><td>B74</td><td>LVDS_B1-</td><td>-</td></tr><tr><td>B75</td><td>LVDS_B2+</td><td>-</td></tr><tr><td>B76</td><td>LVDS_B2-</td><td>-</td></tr><tr><td>B77</td><td>LVDS_B3+</td><td>-</td></tr><tr><td>B78</td><td>LVDS_B3-</td><td>-</td></tr><tr><td>B81</td><td>LVDS_B_CK+</td><td>-</td></tr><tr><td>B82</td><td>LVDS_B_CK-</td><td>-</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td>eDP_VDD_EN</td></tr><tr><td>B79</td><td>LVDS_BKLT_EN</td><td>eDP_BKLT_EN</td></tr><tr><td>B83</td><td>LVDS_BKLT_CTRL</td><td>eDP_BKLT_CTRL</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td>eDP_AUX+</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td>eDP_AUX-</td></tr><tr><td>A87</td><td>-</td><td>eDP_HPD</td></tr></table>

![The image displays a square icon with a white background and a thick red border. The bottom-right corner of the border curls upward, resembling a folded page. Inside the red border, there are two horizontal red lines centered vertically.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/dbb3425226342f82c13be7e47b898d69adebbd4a9671ce409d058a4a89e9144d.jpg)
Note: LVDS is the default mode, and eDP is a build option.

4.3.3.1 Single/Dual Channel LVDS (default)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LVDS_A0+</td><td>A71</td><td>LVDS Channel A differential pairs</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A0-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3+</td><td>A78</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3-</td><td>A79</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A_CK+</td><td>A81</td><td>LVDS Channel A differential clock</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A_CK-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B0+</td><td>B71</td><td>LVDS Channel B differential pairs</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_B0-</td><td>B72</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B1+</td><td>B73</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B1-</td><td>B74</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B2+</td><td>B75</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B2-</td><td>B76</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B3+</td><td>B77</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B3-</td><td>B78</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B_CK+</td><td>B81</td><td>LVDS Channel B differential clock</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_B_CK-</td><td>B82</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_I2C_CK</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

4.3.3.2 4-lane eDP

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>eDP_TX3+</td><td>A81</td><td>eDP differential pairs</td><td>O PCIe</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_TX3-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2+</td><td>A71</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_VDD_EN</td><td>A77</td><td>eDP power enable function</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_EN</td><td>B79</td><td>eDP backlight enable function</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_CTRL</td><td>B83</td><td>eDP backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_AUX+</td><td>A83</td><td>eDP AUX+</td><td>I/O PCIe</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_AUX-</td><td>A84</td><td>eDP AUX-</td><td>I/O PCIe</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_HPD</td><td>A87</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>PD 100K on this pin when eDP is supported</td></tr></table>

4.3.4 Gigabit Ethernet

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GBE0_MD10+</td><td>A13</td><td rowspan="3">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="8">I/O Analog</td><td rowspan="8"></td><td rowspan="8">Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_MD10-</td><td>A12</td></tr><tr><td>GBE0_MD11+</td><td>A10</td></tr><tr><td>GBE0_MD11-</td><td>A9</td><td>1000 100 10</td></tr><tr><td>GBE0_MD12+</td><td>A7</td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td></tr><tr><td>GBE0_MD12-</td><td>A6</td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td></tr><tr><td>GBE0_MD13+</td><td>A3</td><td>MDI[2]+/- B1_DC+/-</td></tr><tr><td>GBE0_MD13-</td><td>A2</td><td>MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td>Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td>Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK_MID#</td><td>A4</td><td>Gigabit Ethernet Controller MID Speed Link indicator. Active low. If active, the link is established but at a speed lower than the maximum speed supported by the Ethernet controller. Note that, based on capabilities of the Ethernet controller used, this signal might not be active for all possible lower link speeds. This module pin should be capable of sinking up to 20 mA at a Voh of 0.4 max. It was GBE0_LINK100# in COM Express Rev. 3.0.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK_MAX#</td><td>A5</td><td>Gigabit Ethernet Controller MAX Speed Link Indicator. Active low. If active, the link is established at the maximum link speed supported by the controller. This module pin should be capable of sinking up to 20 mA at a Voh of 0.4 max. It was GBE0_LINK1000# in COM Express Rev. 3.0.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td>Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>REFGND min3.3V max</td><td></td><td>Not supported</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td>Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.</td><td>IO 3.3VSB</td><td>GBE0_SDP</td><td>Depends on the selection of LAN controller. i226-IT support this pin</td></tr></table>

![The image displays a red outline icon resembling a document or note with a folded bottom-right corner. Inside the shape, there are two horizontal parallel lines centered vertically, representing text or a list.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/836efaf50ead47fbb4fa3c71ea23162cadbdc4356f895b8ee9b94558e478082f.jpg)

Note: This product supports up to 2.5GbE. The LAN LED behavior is optimized for maximum 2.5GbE speed.

GBE0\_LINK\_MAX# will be active for 2.5GbE speed indication.

GBE0\_LINK\_MID# will be active for 1GbE speed indication or lower.

GBE0\_ACT# and GBE0\_LINK# share the same source from the LAN controller.

For 100Mbit/sec and 10Mbit/sec speed, the LAN LED will be OFF.

4.3.5 SATA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_TX+SATA2_TX-</td><td>A22A23</td><td>Serial ATA channel 2, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA2_RX+SATA2_RX-</td><td>A25A26</td><td>Serial ATA channel 2, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA3_TX+SATA3_TX-</td><td>B22B23</td><td>Serial ATA channel 3, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA3_RX+SATA3_RX-</td><td>B25B26</td><td>Serial ATA channel 3, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Not supported</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10K3.3V</td><td>AC coupled on Module</td></tr></table>

4.3.5.1 PCH HSIO Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SoC</td><td>Comment</td></tr><tr><td>SATA0</td><td>HSIO 10</td><td>SATA 0 muxed with PCIe lane 6. SATA is default</td></tr><tr><td>SATA1</td><td>HSIO 11</td><td>SATA 1 muxed with PCIe lane 5. SATA is default</td></tr><tr><td>SATA2</td><td></td><td>Not supported</td></tr><tr><td>SATA3</td><td></td><td>Not supported</td></tr></table>

4.3.6 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX4+PCIE_TX4-</td><td>A55A56</td><td>PCI Express channel 4, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX4+</td><td>B55</td><td>PCI Express channel 4, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_RX4-</td><td>B56</td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_TX5+PCIE_TX5-</td><td>A52A53</td><td>PCI Express channel 5, Transmit Output differential pair.</td><td>O PCIe</td><td></td><td>AC coupled on ModuleBuild option</td></tr><tr><td>PCIE_RX5+PCIE_RX5-</td><td>B52B53</td><td>PCI Express channel 5, Receive Input differential pair.</td><td>I PCIe</td><td></td><td>AC coupled off ModuleBuild option</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O PCIe</td><td></td><td></td></tr></table>

4.3.6.1 PCH HIS Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SoC / Switch IC</td><td>Comment</td></tr><tr><td>PCIE0</td><td>HSIO 2</td><td></td></tr><tr><td>PCIE1</td><td>HSIO 3</td><td></td></tr><tr><td>PCIE2</td><td>HSIO 8</td><td></td></tr><tr><td>PCIE3</td><td>HSIO 9</td><td></td></tr><tr><td>PCIE4</td><td>HSIO 0</td><td></td></tr><tr><td>PCIE5</td><td>HSIO 11</td><td>PCIe laned 5 muxed with SATA 1, SATA is default</td></tr><tr><td>PCIE6</td><td>HSIO 10</td><td>PCIe laned 6 muxed with SATA 0, SATA is default</td></tr><tr><td>PCIE7</td><td>HSIO 6</td><td>PCIe laned 7 muxed with GbE Ethernet, Ethernet is default</td></tr></table>

![The image features a red icon on a white background. It depicts a stylized document or memo with a folded bottom-right corner. Inside the red outline, there are two horizontal red lines centered within the shape.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/269f23e30b4f28fad743aa90a6860c668d8ba54c5cc7b48172a7e9f1c624fb63.jpg)
Note: Up to 5 PCIe devices can operate at the same time, including the on-board i226 LAN controller for the GbE Ethernet feature.

4.3.7 LPC Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LPC_AD0</td><td>B4</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_AD1</td><td>B5</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD2</td><td>B6</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD3</td><td>B7</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_DRQ0#</td><td>B8</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>Not connected</td></tr><tr><td>LPC_DRQ1#</td><td>B9</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O 3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3VSB</td><td></td><td>The LPC_CLK frequency is 24MHz on this platform</td></tr></table>

![The image shows a red icon on a white background. It depicts a stylized document or paper outline with a folded bottom-right corner. Inside the red border, there are two horizontal red lines of varying lengths, centered to represent text lines.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/14b96f9e219ea216cdd468ba78c5db2748cf2b14645e2321ae6ec299e0006f39.jpg)
Note: LPC Bus is supported by an eSPI to LPC bridge IC.

4.3.8 USB

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 2</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 3</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 4</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 5</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 6</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr></table>

![The image shows a red icon resembling a document or page with rounded corners. The bottom right corner is folded over. Inside the red border, there are two horizontal red lines centered vertically. The background is white.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/ac046d640168c189b354a5b11678c25dd3b81e9499c84628c66b316a460469ec.jpg)
\*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

4.3.9 SPI Bus (BIOS only)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>O P 3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not- connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not- connected</td></tr></table>

4.3.10 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the &quot;speaker&quot; in PC-AT systems</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3VSB</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>THRMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan&#x27;s RPM.</td><td>O OD 3.3V</td><td></td><td>There shall be PD on the carrier board.</td></tr><tr><td>FAN_TACHIN</td><td>B102</td><td>Fan tachometer input for a fan with a two-pulse output.</td><td>I OD 3.3V</td><td>PU 47K 3.3V</td><td></td></tr><tr><td>TPM_PP</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100K</td><td>PD is present only when TPM on the module. Modules implementing a TPM shall pull down the signal.</td></tr></table>

4.3.11 SMBus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power is sourced through the 3.3V standby rail and the main power rails.</td><td>I/O OD3.3VSB</td><td>PU 4.7K3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power is sourced through the 3.3V standby rail and the main power rails.</td><td>I/O OD3.3VSB</td><td>PU 4.7K3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – an active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power is sourced through the 3.3V standby rail and the main power rails.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr></table>

4.3.12 I2 C Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source EC as default (chipset by BOM option)</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source EC as default (chipset by BOM option)</td></tr></table>

4.3.13 General Purpose I/O (GPIO)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

4.3.14 Serial Interface Signals

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SERO_TX</td><td>A98</td><td>General purpose serial port transmitter</td><td>O CMOS3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SERO_RX</td><td>A99</td><td>General purpose serial port receiver</td><td>I CMOS3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter</td><td>O CMOS3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver</td><td>I CMOS3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr></table>

4.3.15 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring the system out of S5 (soft off), active on the falling edge.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. It may be falling edge sensitive. In situations where SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from the module to the carrier board. Active low. Issued by module chipset, it may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or it may be initiated by the module software.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from the main power supply. A high value indicates that the power is good. This signal can be used to delay module startup to allow carrier-based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Should have weak pull up.</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates an imminent suspend operation; used to notify LPC devices.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates the system is in the Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates the system is in the Suspend to Disk state. Active low output.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates the system is in the Soft Off state.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake-up signal.</td><td>I 3.3VSB</td><td>PU 8.2K 3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake-up signal. It may be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 8.2K 3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or it may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal is used by the ACPI operating system for a LID switch.</td><td>I OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal is used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>I OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>RAPID_SHUTDOWN</td><td>C67</td><td>Trigger for Rapid Shutdown. Must be driven to 5V though a &lt;=50 ohm source impedance for ≥20 μs.</td><td>I CMOS 5VSB</td><td></td><td>Not supported</td></tr></table>

4.3.16 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109</td><td>Primary power input supports a wide range input of 5 — 20V. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20 V</td></tr><tr><td>VCC_5V_SBY</td><td>B84, B85, B86, B87</td><td>Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 4.4 CD Connector Signal Descriptions

4.4.1 USB 3.0 Extensions

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>C3C4</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIe</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>D3D4</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIe</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>C6C7</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIe</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>D6D7</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIe</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX2-USB_SSRX2+</td><td>C9C10</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2</td><td>I PCIe</td><td></td><td>AC coupled off moduleBuild option through USB Hub</td></tr><tr><td>USB_SSTX2-USB_SSTX2+</td><td>D9D10</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2</td><td>O PCIe</td><td></td><td>AC coupled on moduleBuild option through USB Hub</td></tr><tr><td>USB_SSRX3-USB_SSRX3+</td><td>C12C13</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3</td><td>I PCIe</td><td></td><td>AC coupled off moduleBuild option through USB Hub</td></tr><tr><td>USB_SSTX3-USB_SSTX3+</td><td>D12D13</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3</td><td>O PCIe</td><td></td><td>AC coupled on moduleBuild option through USB Hub</td></tr></table>

# 4.4.1.1 USB Root Segmentation

All USB interfaces are derived from the xHCI controller.

4.4.2 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX6+</td><td>D19</td><td rowspan="2">PCI Express channel 6, Transmit Output differential pair.</td><td rowspan="2">O PCIe</td><td rowspan="2"></td><td rowspan="2">AC coupled on ModuleBuild option</td></tr><tr><td>PCIE_TX6-</td><td>D20</td></tr><tr><td>PCIE_RX6+</td><td>C19</td><td rowspan="2">PCI Express channel 6, Receive Input differential pair.</td><td rowspan="2">I PCIe</td><td rowspan="2"></td><td rowspan="2">AC coupled off ModuleBuild option</td></tr><tr><td>PCIE_RX6-</td><td>C20</td></tr><tr><td>PCIE_TX7+</td><td>D22</td><td rowspan="2">PCI Express channel 7, Transmit Output differential pair.</td><td rowspan="2">O PCIe</td><td rowspan="2"></td><td rowspan="2">AC coupled on ModuleBuild option</td></tr><tr><td>PCIE_TX7-</td><td>D23</td></tr><tr><td>PCIE_RX7+</td><td>C22</td><td rowspan="2">PCI Express channel 7, Receive Input differential pair.</td><td rowspan="2">I PCIe</td><td rowspan="2"></td><td rowspan="2">AC coupled off ModuleBuild option</td></tr><tr><td>PCIE_RX7-</td><td>C23</td></tr></table>

# 4.4.2.1 PCH HSIO Lane Assignments

Refer to section, 4.3.6.1 PCH HSIO Lane Assignments, on page 37.

# 4.4.3 DDI1 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI1_PAIR0+</td><td>D26</td><td>DP1_LANE0+</td><td>TMDS1_DATA2+</td></tr><tr><td>DDI1_PAIR0-</td><td>D27</td><td>DP1_LANE0-</td><td>TMDS1_DATA2-</td></tr><tr><td>DDI1_PAIR1+</td><td>D29</td><td>DP1_LANE1+</td><td>TMDS1_DATA1+</td></tr><tr><td>DDI1_PAIR1-</td><td>D30</td><td>DP1_LANE1-</td><td>TMDS1_DATA1-</td></tr><tr><td>DDI1_PAIR2+</td><td>D32</td><td>DP1_LANE2+</td><td>TMDS1_DATA0+</td></tr><tr><td>DDI1_PAIR2-</td><td>D33</td><td>DP1_LANE2-</td><td>TMDS1_DATA0-</td></tr><tr><td>DDI1_PAIR3+</td><td>D36</td><td>DP1_LANE3+</td><td>TMDS1_CLK+</td></tr><tr><td>DDI1_PAIR3-</td><td>D37</td><td>DP1_LANE3-</td><td>TMDS1_CLK-</td></tr><tr><td>DDI1_PAIR4+</td><td>C25</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR4-</td><td>C26</td><td></td><td></td></tr><tr><td>DDI1_PAIR5+</td><td>C29</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR5-</td><td>C30</td><td></td><td></td></tr><tr><td>DDI1_PAIR6+</td><td>C15</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR6-</td><td>C16</td><td></td><td></td></tr><tr><td>DDI1_HPD</td><td>C24</td><td>DP1_HPD</td><td>HDMI1_HPD</td></tr><tr><td>DDI1_CTRLCLK_AUX+</td><td>D15</td><td>DP1_AUX+</td><td>HMDI1_CTRLCLK</td></tr><tr><td>DDI1_CTRLCLK_AUX-</td><td>D16</td><td>DP1_AUX-</td><td>HMDI1_CTRLDATA</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td><td>DDI1_DDC_AUX_SEL</td></tr></table>

![The image displays a red icon on a white background. It depicts a rectangular shape resembling a document or page, featuring a thick red border. The bottom-right corner of the shape is folded upwards. Inside the border, there are two horizontal red lines positioned centrally.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/0feea88ed71bc907c444d2c6e8082238d3b353ea397377f49e38c6293796cb66.jpg)

Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SoCs that natively implement this capability. For such SoCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function.

4.4.3.1 DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>DP1_LANE0+</td><td>D26</td><td>DP Port 1, differential pair data lines</td><td>O PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP1_LANE0-</td><td>D27</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP1_LANE1+</td><td>D29</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE1-</td><td>D30</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE2+</td><td>D32</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE2-</td><td>D33</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE3+</td><td>D36</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE3-</td><td>D37</td><td></td><td></td><td></td></tr><tr><td>DP1_HPD</td><td>C24</td><td>DP Port 1, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>The module must tolerate a high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the module.</td></tr><tr><td>DP1_AUX+</td><td>D15</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIe</td><td>PD 100K</td><td>AC coupled on Module</td></tr><tr><td>DP1_AUX-</td><td>D16</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIe</td><td>PU 100K</td><td>AC coupled on Module</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and floating on the carrier that enables DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.4.3.2 HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>TMDS1_DATA2+</td><td>D26</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIe</td><td rowspan="6"></td><td rowspan="6">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>TMDS1_DATA2-</td><td>D27</td></tr><tr><td>TMDS1_DATA1+</td><td>D29</td></tr><tr><td>TMDS1_DATA1-</td><td>D30</td></tr><tr><td>TMDS1_DATA0+</td><td>D32</td></tr><tr><td>TMDS1_DATA0-</td><td>D33</td></tr><tr><td>TMDS1_CLK+</td><td>D36</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS1_CLK-</td><td>D37</td></tr><tr><td>HDMI_HPD</td><td>C24</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>HDMI1_CTRLCLK</td><td>D15</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIe</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>HDMI1_CTRLDATA</td><td>D16</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIe</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and floating on the carrier that enables DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

4.4.4 DDI2 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI2_PAIR0+</td><td>D39</td><td>DP2_LANE0+</td><td>TMDS2_DATA2+</td></tr><tr><td>DDI2_PAIR0-</td><td>D40</td><td>DP2_LANE0-</td><td>TMDS2_DATA2-</td></tr><tr><td>DDI2_PAIR1+</td><td>D42</td><td>DP2_LANE1+</td><td>TMDS2_DATA1+</td></tr><tr><td>DDI2_PAIR1-</td><td>D43</td><td>DP2_LANE1-</td><td>TMDS2_DATA1-</td></tr><tr><td>DDI2_PAIR2+</td><td>D46</td><td>DP2_LANE2+</td><td>TMDS2_DATA0+</td></tr><tr><td>DDI2_PAIR2-</td><td>D47</td><td>DP2_LANE2-</td><td>TMDS2_DATA0-</td></tr><tr><td>DDI2_PAIR3+</td><td>D49</td><td>DP2_LANE3+</td><td>TMDS2_CLK+</td></tr><tr><td>DDI2_PAIR3-</td><td>D50</td><td>DP2_LANE3-</td><td>TMDS2_CLK-</td></tr><tr><td>DDI2_HPD</td><td>D44</td><td>DP2_HPD</td><td>HDMI2_HPD</td></tr><tr><td>DDI2_CTRLCLK_AUX+</td><td>C32</td><td>DP2_AUX+</td><td>HMDI2_CTRLCLK</td></tr><tr><td>DDI2_CTRLCLK_AUX-</td><td>C33</td><td>DP2_AUX-</td><td>HMDI2_CTRLDATA</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>DDI2_DDC_AUX_SEL</td></tr></table>

![The image shows a red icon of a document or note. It features a red outline of a rectangular sheet of paper with a curled bottom-right corner. Inside the red border, there are two horizontal red lines centered on the page, resembling text or a list.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/e853a2ad83fc3b7bbe8a91e790c1a089a8aed6f23a4c6d3f08ea478bf4709caa.jpg)

# Note:

Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SoCs that natively implement this capability. For such SoCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DC coupled, but the DP\_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function.

4.4.4.1 DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>DP2_LANE0+</td><td>D39</td><td>DP Port 2, differential pair data lines</td><td>O PCIe</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP2_LANE0-</td><td>D40</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP2_LANE1+</td><td>D42</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE1-</td><td>D43</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE2+</td><td>D46</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE2-</td><td>D47</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE3+</td><td>D49</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE3-</td><td>D50</td><td></td><td></td><td></td></tr><tr><td>DP2_HPD</td><td>D44</td><td>DP Port 2, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>The module must tolerate a high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the module.</td></tr><tr><td>DP2_AUX+</td><td>C32</td><td>DP Port 2, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIe</td><td>PD 100K</td><td>AC coupled on Module</td></tr><tr><td>DP2_AUX-</td><td>C33</td><td>DP Port 2, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIe</td><td>PU 100K</td><td>AC coupled on Module</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and floating on the carrier that enables DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.4.4.2 HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>TMDS2_DATA2+</td><td>D39</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIe</td><td rowspan="6"></td><td rowspan="6">AC coupled off module100 nF DC blocking capacitors shall be placed on the carrier</td></tr><tr><td>TMDS2_DATA2-</td><td>D40</td></tr><tr><td>TMDS2_DATA1+</td><td>D42</td></tr><tr><td>TMDS2_DATA1-</td><td>D43</td></tr><tr><td>TMDS2_DATA0+</td><td>D46</td></tr><tr><td>TMDS2_DATA0-</td><td>D47</td></tr><tr><td>TMDS2_CLK+</td><td>D49</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS2_CLK-</td><td>D50</td></tr><tr><td>HDM2_HPD</td><td>D44</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>HDMI2_CTRLCLK</td><td>C32</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIe</td><td>PU 2.2K</td><td>AC couple on module</td></tr><tr><td>HDMI2_CTRLDATA</td><td>C33</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIe</td><td>PU 2.2K</td><td>AC couple on module</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and floating on the carrier that enables DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

# 4.4.5 DDI3 Port

Not supported

# 4.4.6 PCIe Graphics Port (PEG)

Not supported

4.4.7 Module Type Definition

<table><tr><td>Name</td><td>Pin #</td><td colspan="4">Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="9"></td></tr><tr><td>TYPE0#</td><td>C54</td><td colspan="4" rowspan="3">The TYPE pins indicate to the carrier board the Pin-out Type that is implemented on the module. The pins are tied to either ground (GND) or are left as no-connects (NC) on the module.</td><td rowspan="14"></td><td rowspan="14"></td><td rowspan="14">Type 6</td></tr><tr><td>TYPE1#</td><td>C57</td></tr><tr><td>TYPE2#</td><td>D57</td></tr><tr><td></td><td></td><td colspan="4">For Pin-out Type 1 and Type 10, which lack a CD connector, these pins are not present (X)</td></tr><tr><td></td><td></td><td>TYPE2#</td><td>TYPE1#</td><td>TYPE0#</td><td></td></tr><tr><td></td><td></td><td>X</td><td>X</td><td>X</td><td>Pinout Type 1</td></tr><tr><td></td><td></td><td>X</td><td>X</td><td>X</td><td>Pinout Type 10</td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>NC</td><td>Pinout Type 2</td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>GND</td><td>Pinout Type 3</td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>NC</td><td>Pinout Type 4</td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>GND</td><td>Pinout Type 5</td></tr><tr><td></td><td></td><td>GND</td><td>NC</td><td>NC</td><td>Pinout Type 6</td></tr><tr><td></td><td></td><td>GND</td><td>NC</td><td>GND</td><td>Pinout Type 7</td></tr><tr><td></td><td></td><td colspan="4">The carrier board should implement combinatorial logic to monitor the module TYPE pins and keep power off (e.g., deactivates the ATX_ON signal for an ATX</td></tr><tr><td></td><td></td><td>power supply) if an incompatible module pin-out type is detected. The carrier board logic may also implement a fault indicator, such as an LED.</td><td></td><td></td><td colspan="4"></td></tr><tr><td>TYPE10#</td><td>A97</td><td>In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.</td><td></td><td></td><td colspan="4">No PD</td></tr></table>

4.4.8 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>VCC_12V</td><td>C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109</td><td>Primary power input supports a wide input range of 5~20V. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20 V</td></tr><tr><td>GND</td><td>C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches, and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as illustrated below:

![5.1 Module Feature Locations\nStatus LEDs\nFAN\nBIOS Default Reset Button\n30-pin Debug Connector\nBIOS Boot Select\nCOM Express\nADLINK](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/52ea01306dcc3c271405786d33de588d1e392f30ab5510eab7fce2a217dc2599.jpg)

Figure 3 – Module feature locations (top side)

# 5.2 Debug Connector

This connector is particularly useful during the carrier design and bring up phase. It provides access to the following critical parts of the module:

• Test points measurement of internal power rails
• SPI BIOS programming interface
• I2C bus for BIOS Post Code readout
• Embedded Controller programming interface

Picture below is for illustration purposes only:

![Two electronic circuit boards: one with ADLINK chip and green PCB, the other with a gray flexible network cable (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/e88918308b73571ce8caf07928f2ce80a3ce6cd0eeb489b482f01cb85e885873.jpg)

Figure 4 – cExpress-ASL and debug module

# 5.3 Status LEDs

Status LEDs are mounted on the module to facilitate easier maintenance.

LED1 LED2 LED3

![The image displays a white background featuring three red lines. At the bottom, there are two parallel horizontal lines running across the width of the frame. Above these, starting from the left edge and angling upwards to the right, is a single diagonal red line.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/7c7972f6acce617fbc5b7ef4823cb9b2d7df6a90d6b81c9d1c8ba16677c23676.jpg)

![Close-up of a green printed circuit board with various electronic components and connectors (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/263aafa2ffe0617349733718fd6f2a922d7da012bf7e884cbf43b5597009f206.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>EC output</td><td>Power Sequence Status Code (EC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>EC output and same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

# 5.4 Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>7</td><td>RESET_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr></table>

# 5.5 Fan Connector

Connector type: JVE 24W1125A-04M00

4 3 2 1

![The image displays a red graphic against a white background. It consists of two thick red lines with rounded ends that meet at a vertex on the left side, forming an acute angle pointing to the right. One line is horizontal at the bottom, and the other is angled upwards. A thin black horizontal line runs along the very top edge of the image.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/773f7704c7aa43d27bea475f75fe14c7c7100edf7f536ab806cd4cdf40bbd630.jpg)

![Close-up of a green printed circuit board with various electronic components and connectors (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/00c246c3ed5635f7bc074ce104721ce679ee340cde37feee1fd8058354242c9d.jpg)

<table><tr><td>Name</td><td>Description</td></tr><tr><td colspan="2"></td></tr><tr><td>1</td><td>FAN_PWMOUT</td></tr><tr><td>2</td><td>FAN_TACHIN</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>12V</td></tr></table>

The on-board FAN connector is a mini 4-pin type. The reference heatsink with an active FAN uses a standard 4-pin connector.

# 5.6 BIOS Default Reset Button

![Close-up of a green printed circuit board with electronic components and a red arrow pointing to a component (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/9b660aa79ec1cf578926b244be4fb5ae7432ebb2b8a1a6c35ac98e84d6b294f7.jpg)

To perform a hardware reset of the BIOS default settings, perform the following steps:

1. Shut down the system.
2. Press and hold the BIOS Setup Defaults Reset Button, then boot up the system. You can release the button when the BIOS prompt screen appears.
3. The BIOS prompt screen will display a confirmation that the BIOS defaults have been reset and will request that you reboot the system.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/dcc60653186cc28e95d1999fa5bb76d47cd56d52b7f091a0a1b5c2281efc6eb6.jpg)

# 5.7 BIOS Boot Select

The module has two BIOS chips (BOM option), and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using the BIOS Select and Mode Configuration Switch, Pin 2.

Setting the module to PICMG mode configures the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.

In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (default)</td><td>On</td><td>-</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>-</td></tr><tr><td>Set BIOS to PICMG mode (default)</td><td>-</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode</td><td>-</td><td>Off</td></tr></table>

# 6. System Resources

6.1 System Memory Map

<table><tr><td>Memory Range</td><td>Target</td><td>Dependency/Comments</td></tr><tr><td>000A0000 – 000B FFFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>000E 0000 - 000F 3FFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>000E 4000 - 000F 7FFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>000E 8000 - 000F BFFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>000E C000 – 000E FFFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>000F 0000 - 000F FFFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>0080400000 – 00BFFFFFFF</td><td>PCIe port</td><td>PCIe root port</td></tr><tr><td>00C0000000- 00CFFFFFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FD690000 – 00FD69FFFF</td><td>Serial I/O GPIO Host Controller</td><td>Serial I/O GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6A0000 – 00FD6AFFFF</td><td>Serial I/O GPIO Host Controller</td><td>Serial I/O GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6D0000 – 00FD6DFFFF</td><td>Serial I/O GPIO Host Controller</td><td>Serial I/O GPIO Host Controller – INTC1057</td></tr><tr><td>00FD6E0000 – 00FD6EFFFF</td><td>Serial I/O GPIO Host Controller</td><td>Serial I/O GPIO Host Controller – INTC1057</td></tr><tr><td>00FE010000- 00FE010FFF</td><td>SPI Controller</td><td>SPI Controller – 54A4</td></tr><tr><td>00FED00000- 00FED003FF</td><td>High precision event timer</td><td></td></tr><tr><td>00FED20000-00FED7FFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FED45000-00FED8FFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FED90000-00FED93FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDA0000-00FEDA0FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDA1000-00FEDA1FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEDC0000-00FEDC7FFF</td><td>Motherboard resources</td><td></td></tr><tr><td>00FEE00000-00FEEFFFFF</td><td>Motherboard resources</td><td></td></tr><tr><td>004000000000 - 00 400FFFFFFF</td><td>Intel UHD Graphics</td><td></td></tr><tr><td>006000000000 - 00600FFFFFFF</td><td>Intel UHD Graphics</td><td></td></tr><tr><td>006001100000-00600110FFF</td><td>XHCI Controller</td><td>Intel USB3.0 XHCI Controller</td></tr><tr><td>006001118000-0060011180FF</td><td>SMBus</td><td>SMBus-54A3</td></tr><tr><td>00600111B000-00600111BFFF</td><td>Intel SD Host Controller</td><td></td></tr><tr><td>007FFEF3000-007FFEF3FFF</td><td>UART#0</td><td>Intel Serial I/O UART Host Controller - 54A8</td></tr><tr><td>007FFEF4000-007FFEF4FFF</td><td>UART#1</td><td>Intel Serial I/O UART Host Controller - 54C7</td></tr><tr><td>007FFEF5000-007FFEF5FFF</td><td>I2C#0</td><td>Intel Serial I/O I2C Host Controller - 54C6</td></tr><tr><td>007FFEF6000-007FFEF6FFF</td><td>I2C#1</td><td>Intel Serial I/O I2C Host Controller-54C5</td></tr><tr><td>007FFEF7000-007FFEF7FFF</td><td>Intel ME</td><td>Intel ME Interface #1</td></tr><tr><td>007FFEF8000-007FFEF8FFF</td><td>I2C#2</td><td>Intel Serial I/O I2C Host Controller-54E9</td></tr><tr><td>007FFFEF9000-007FFEF9FFF</td><td>I2C#3</td><td>Intel Serial I/O I2C Host Controller-54E8</td></tr><tr><td>007FFFEFA000-007FFEFAFFF</td><td>UART#2</td><td>Intel Serial I/O UART Host Controller - 54A9</td></tr><tr><td>007FFEFB000-007FFEFBFFF</td><td>GNA</td><td>Intel GNA Scoring Accelerator module</td></tr><tr><td>007FFEFC000-007FFEFCFFF</td><td>HDA</td><td>High Definition Audio Controller</td></tr><tr><td>007FFFF00000-007FFFFFFF</td><td>HDA</td><td>High Definition Audio Controller</td></tr><tr><td>128 KB anywhere in 4 GBrange</td><td>LAN Controller (CSRregisters)</td><td>Enable via standard PCI mechanism (Device 31:Function 6)</td></tr><tr><td>4 KB anywhere in 4 GBrange</td><td>LAN Controller (LAN space onFlash)</td><td>Enable via standard PCI mechanism (Device 31:Function 6)</td></tr><tr><td>64 KB anywhere in 64-bitaddress range</td><td>USB Host Controller</td><td>Enable via standard PCI mechanism (Device 20, Function 0)</td></tr><tr><td>2 MB anywhere in 4 GBrange</td><td>USB Device Controller</td><td>Enable via standard PCI mechanism (Device 20, Function 1)</td></tr><tr><td>24 KB anywhere in 4 GBrange</td><td>USB Device Controller</td><td>Enable via standard PCI mechanism (Device 20, Function 1)</td></tr><tr><td>16 KB anywhere in 64-bitaddressing space</td><td>Intel® HD Audio Subsystem</td><td>Enable via standard PCI mechanism (Device 31, Function 3)</td></tr><tr><td>4 KB anywhere in 64-bitaddressing space</td><td>Intel® HD Audio Subsystem</td><td>Enable via standard PCI mechanism (Device 31, Function 3)</td></tr><tr><td>64 KB anywhere in 64-bitaddressing space</td><td>Intel® HD Audio Subsystem</td><td>Enable via standard PCI mechanism (Device 31, Function 3)</td></tr><tr><td>32 Bytes anywhere in 64-bit address range</td><td>SMBus</td><td>Enable via standard PCI mechanism (Device 31: Function 4)</td></tr><tr><td>2 KB anywhere above 64KB to 4 GB range</td><td>SATA Host Controller</td><td>AHCI memory-mapped registers. Enable via standard PCImechanism (Device 23: Function 0)</td></tr><tr><td>Memory Base/Limit anywhere in 4 GB range</td><td>PCI Express* Root Ports 1-12</td><td>Enable via standard PCI mechanism</td></tr><tr><td>Prefetchable Memory Base/Limit anywhere in64-bit address range</td><td>PCI Express* Root Ports 1-12</td><td>Enable via standard PCI mechanism</td></tr><tr><td>16 Bytes anywhere in 64-bit address range</td><td>Intel® CSMEI #1, #2, #3, #4</td><td>Enable via standard PCI mechanism</td></tr><tr><td>4 KB anywhere in 4 GBrange</td><td>Intel® AMT Keyboard and Text</td><td>Enable via standard PCI mechanism (Device 22: Function 3)</td></tr><tr><td>16 MB anywhere in 64-bitaddress range</td><td>P2SB</td><td>Enable via standard PCI mechanism</td></tr><tr><td>Eight 4 KB slots anywherein 64-bit address range</td><td>UART, GPI and I2C controllers</td><td>Enable via standard PCI mechanism</td></tr><tr><td>1 MB (BAR0) or 4 KB (BAR1) in 4GB range</td><td>Integrated Sensor Hub</td><td>Enable via standard PCI mechanism (Device 19: Function 0)</td></tr><tr><td>8 KB slot anywhere in 4GB range</td><td>Integrated Wi-Fi*</td><td>Enable via standard PCI mechanism</td></tr><tr><td>8 KB slot and 4 KB slot anywhere in 4 GB range</td><td>PMC</td><td>Enable via standard PCI mechanism</td></tr><tr><td>8 KB slot and 4 KB slot anywhere in 4 GB range</td><td>Shared SRAM</td><td>Enable via standard PCI mechanism</td></tr></table>

# 6.2 I/O Map

Variable I/O Decode Ranges

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>ACPI</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>IDE Bus Master</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>SMBus</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>TCO</td></tr><tr><td>3 Ranges in 64K I/O Space</td><td>Parallel Port</td></tr><tr><td>8 Ranges in 64K I/O Space</td><td>Serial Port 1</td></tr><tr><td>8 Ranges in 64K I/O Space</td><td>Serial Port 2</td></tr><tr><td>8 Ranges in 64K I/O Space</td><td>Serial Port 3</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>I/O Trapping Ranges</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>Serial ATA Index/Data Pair</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>PCI Express* Root Ports</td></tr><tr><td>Anywhere in 64K I/O Space</td><td>Keyboard and Text(KT)</td></tr></table>

Fixed I/O Decode Ranges

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>020h – 02Dh &amp; 030h – 03Dh</td><td>Programmable interrupt controller</td></tr><tr><td>02Eh – 02Fh</td><td>Motherboard resource</td></tr><tr><td>040h – 043h &amp; 050h – 053h</td><td>System Timer</td></tr><tr><td>04Eh – 04Fh</td><td>Motherboard resource</td></tr><tr><td>062h, 066h</td><td>Microsoft ACPI-Compliant Embedded Controller</td></tr><tr><td>061h, 063h, 065h, 067h, 070h, 080h, 092h</td><td>Motherboard resource</td></tr><tr><td>0A0h – 0B1h &amp; 0B4h – 0BDh</td><td>Interrupt Controller</td></tr><tr><td>0B2h and 0B3h</td><td>Motherboard resource</td></tr><tr><td>0E0h – 0EFh</td><td>Available</td></tr><tr><td>0F0h</td><td>Co-processor error register</td></tr><tr><td>200h - 201h</td><td>SEMA Embedded Controller</td></tr><tr><td>2F8h – 2FFh</td><td>Serial Port 2</td></tr><tr><td>3F8h – 3FFh</td><td>Serial Port 1</td></tr><tr><td>378h – 37Fh</td><td>Available</td></tr><tr><td>380h – 3AFh</td><td>Available</td></tr><tr><td>4D0h-4D1h</td><td>Interrupt Controller</td></tr><tr><td>680h – 69Fh &amp; 0A00h – 0A6Fh &amp; 164Eh - 164Fh &amp; 1854h-1857h &amp; 2000h-20FEh</td><td>Motherboard resource</td></tr><tr><td>3000h-303Fh</td><td>Intel UHD Graphics</td></tr><tr><td>EFA0h- EFBFh</td><td>SMBus – 54A3</td></tr><tr><td>020h – 02Dh &amp; 030h – 03Dh</td><td>Programmable interrupt controller</td></tr><tr><td>02Eh – 02Fh</td><td>Motherboard resource</td></tr></table>

# 6.3 Interrupt Request (IRQ) Lines

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>System timer</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2 (COM2)</td><td>IRQ3 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>4</td><td>Serial Port 1 (COM1)</td><td>IRQ4 via SERIRQ/PIRQ</td><td>No</td></tr><tr><td>14</td><td>Intel Serial I/O GPIO Host Controller</td><td>N/A</td><td>No</td></tr><tr><td>16</td><td>Intel SD Host Controller</td><td>PCI Usage</td><td>No</td></tr><tr><td>16</td><td>Intel Serial I/O UART Host Controller-54A8</td><td>PCI Usage</td><td>No</td></tr><tr><td>17</td><td>Intel Serial I/O UART Host Controller-54A9</td><td>PCI Usage</td><td>No</td></tr><tr><td>19</td><td>High-Definition Audio Controller</td><td>PCI Usage</td><td>No</td></tr><tr><td>27</td><td>Intel Serial I/O I2C Host Controller-54E8</td><td>PCI Usage</td><td>No</td></tr><tr><td>31</td><td>Intel Serial I/O I2C Host Controller-54C5</td><td>PCI Usage</td><td>No</td></tr><tr><td>32</td><td>Intel Serial I/O I2C Host Controller-54C6</td><td>PCI Usage</td><td>No</td></tr><tr><td>36</td><td>Intel Serial I/O SPI Host Controller-54AA</td><td>PCI Usage</td><td>No</td></tr><tr><td>40</td><td>Intel Serial I/O I2C Host Controller-54E9</td><td>PCI Usage</td><td>No</td></tr><tr><td>42</td><td>Intel Serial I/O UART Host Controller-54C7</td><td>PCI Usage</td><td>No</td></tr><tr><td>43-511</td><td>Microsoft ACPI-Compliant System</td><td>N/A</td><td>Yes</td></tr></table>

![The image shows a red icon resembling a document or file. It consists of a thick red outline shaped like a piece of paper with a folded top-right corner. Inside the outline, there are two horizontal red lines.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/f157b70458ced559c78f237db24395e70838c7b8d3a4c0f7e6c7e4931c7159af.jpg)
Note: These IRQs can be used for PCI devices when onboard device is disabled.

6.4 PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel Corporation Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel VGA Controller</td></tr><tr><td>00h</td><td>08h</td><td>00h</td><td>Internal</td><td>Intel system device</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>USB xHCI Controller</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>RAM Controller</td></tr><tr><td>00h</td><td>15h</td><td>00h</td><td>Internal</td><td>I2C Controller #0</td></tr><tr><td>00h</td><td>15h</td><td>01h</td><td>Internal</td><td>I2C Controller #1</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel® CSME Interface #1</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Internal</td><td>I2C Controller #2</td></tr><tr><td>00h</td><td>19h</td><td>01h</td><td>Internal</td><td>I2C Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>02h</td><td>Internal</td><td>UART #0</td></tr><tr><td>00h</td><td>1Ah</td><td>00h</td><td>Internal</td><td>SD Host Controller</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port 4</td></tr><tr><td>00h</td><td>1Eh</td><td>00h</td><td>Internal</td><td>UART #1</td></tr><tr><td>00h</td><td>1Eh</td><td>01h</td><td>Internal</td><td>UART #2</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel ISA bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>HD Audio</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>SMBus Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>SPI Controller</td></tr><tr><td>01h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Ethernet controller I226-V</td></tr></table>

# 6.5 PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>Audio Controller</td><td>xHCI Controller</td><td>CSME Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTD: 16</td><td>INTA: 16</td><td>INTA: 16</td><td>INTA: 16</td></tr><tr><td>Int1</td><td></td><td>INTB: 17</td><td>INTB: 17</td><td></td></tr><tr><td>Int2</td><td></td><td>INTC: 18</td><td>INTC: 18</td><td></td></tr><tr><td>Int3</td><td></td><td>INTD: 19</td><td>INTD: 19</td><td></td></tr></table>

<table><tr><td>INT Line</td><td>PCIe Port 3</td><td>PCIe Port 4</td><td>PCIe Port 7</td><td>PCIe Port 9</td><td>PCIe Port 10</td></tr><tr><td>Int0</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td></tr><tr><td>Int1</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td></tr><tr><td>Int2</td><td>INTC: 18</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td></tr><tr><td>Int3</td><td>INTD: 19</td><td>INTA: 16</td><td>INTB: 17</td><td>INTC: 18</td><td>INTD: 19</td></tr></table>

# 6.6 SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>PTN3460</td><td>0C0h</td></tr></table>

# 7 BIOS Setup

# 7.1 Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. Subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information</td><td>CPU Configuration ▶</td><td>System Agent (SA) Configuration ▶</td><td>Password</td><td>Boot</td><td>Save Options</td></tr><tr><td>System Information</td><td>Power &amp; Performance ▶</td><td>PCH-I/O Configuration ▶</td><td>Description</td><td>Configuration</td><td>Boot Override</td></tr><tr><td>Board Information ▶</td><td>Inter(R) Time Coordinated Computing ▶</td><td></td><td>Secure Boot ▶</td><td></td><td></td></tr><tr><td>System Date</td><td>Power Management ▶</td><td></td><td></td><td></td><td></td></tr><tr><td>System Time</td><td>System Management ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Thermal Management ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Watchdog Timer ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Super I/O Configuration ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Miscellaneous ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>USB Configuration ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>NVMe Configuration ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>AMI Graphics Output Protocol Policy ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Serial Port Console Redirection ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Network Stack Configuration ▶</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Trusted Computing ▶</td><td></td><td></td><td></td><td></td></tr></table>

![The image displays a red icon on a white background. It features a rectangular shape resembling a piece of paper with the bottom-right corner folded upwards. Inside the document outline is a large red capital letter 'E'.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/f12e9baafe0fca3729a9d72f041b20c3b1fb83fae4063426226df7541a0ac78e.jpg)

Note: ► Indicates a submenu

Gray text indicates info only

# 7.2 Main

The Main Menu provides read-only information about your system and also allows you to set the system date and time. Refer to the tables below the screenshot of this menu for details of the submenus and settings.

7.2.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Displays core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays compliancy information</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Displays compliancy information</td></tr><tr><td>GOP Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr></table>

7.2.2 System Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Displays Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Displays CPU Signature</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Displays CPU Brand Name</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Displays CPU Frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Displays Installed Memory Size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays Memory Frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Displays PCH Information</td></tr><tr><td>Board Information</td><td>Submenu</td><td></td></tr></table>

7.2.3 Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Displays SMC serial number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Displays SMC manufacturing date</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Displays SMC last repair date</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Displays SMC MAC ID</td></tr><tr><td>MAC ID 2</td><td>Read only</td><td>Displays SMC MAC ID 2</td></tr><tr><td>UUID</td><td>Read only</td><td>Displays SMC UUID</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time, in minutes, that the system has been running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time, in seconds, that the system has been running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down.</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.2.4 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr><tr><td>Access Level</td><td>Read only</td><td>It shows what access level is used to enter the BIOS setup menu.</td></tr></table>

# 7.3 Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Efficient-core Information</td><td>submenu</td><td>Displays the E-core Information</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU information</td></tr><tr><td>Brand String</td><td>Info only</td><td>Display CPU information</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU Stepping</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel Virtualization Technology support or not.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled, Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Efficient-cores</td><td>All,1,0</td><td>Number of E-cores to enable in each processor package. Note: Number of Cores and E-cores are looked at together. When both are {0,0}, Pcode will enable all cores.</td></tr></table>

# 7.3.2 Power & Performance Configuration

7.3.2.1 Power & Performance Configuration > CPU - Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Performance Mode</td><td>Max Battery, Max Non-Turbo Performance, Turbo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled, Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Race To Halt (RTH)</td><td>Disabled, Enabled</td><td>Enable/Disable the Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled, Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Per Core P State OS control P-State</td><td>Disabled, Enabled</td><td>Enable/Disable Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.</td></tr><tr><td>HWP Autonomous Per Core P-State</td><td>Disabled, Enabled</td><td>Disable Autonomous PCPS (Bit 30 = 1, command 0x11) Autonomous will request the same value for all cores all the time. Enable PCPS (default Bit 30 = 0, command 0x11)</td></tr><tr><td>HWP Autonomous EPP Grouping</td><td>Disabled, Enabled</td><td>Enable EPP grouping (default Bit 29 =0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (Bit 29 =1, command 0x11) autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>Disabled, Enabled</td><td>Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b, subcommand 0x3 to 1. This will allow OOB EPB PECI override control</td></tr><tr><td>HWP Lock</td><td>Disabled, Enabled</td><td>Enable/Disable HWP Lock support in Miscellaneous Power Management MSR.</td></tr><tr><td>HDC Control</td><td>Disabled, Enabled</td><td>This option allows HDC configuration.</td></tr><tr><td>Turbo Mode</td><td>Disabled, Enabled</td><td>Enable/Disable processor Turbo Mode (requires EMTTM to be enabled). AUTO means enabled.</td></tr><tr><td>View/Configure Turbo Options</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Current Turbo Settings</td></tr><tr><td>Max Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Min Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Package TDP Limit</td><td>Info only</td><td></td></tr><tr><td>Power Limit 1</td><td>Info only</td><td></td></tr><tr><td>Power Limit 2</td><td>Info only</td><td></td></tr><tr><td>Turbo Ratio Limit Options</td><td>Submenu</td><td></td></tr><tr><td>Energy Efficient P-state</td><td>Disabled, Enabled</td><td>Enable/Disable the Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR 1B0h and CPUID Fun</td></tr><tr><td>Package Power Limit MSR Lock</td><td>Disabled, Enabled</td><td>Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.</td></tr><tr><td>Power Limit 1 Override</td><td>Disabled, Enabled</td><td>Enable/Disable Power Limit 1 override. If this option is disabled, BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.</td></tr><tr><td>Power Limit 2 Override</td><td>Disabled, Enabled</td><td>Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2.</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in milliwatts. BIOS will round to the nearest 1/8W when programming. If the value is 0, BIOS will program this value as 1.25* Processor Base Power (TDP). For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Energy Efficient Turbo</td><td>Disabled, Enabled</td><td>Enable/Disable the Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.</td></tr><tr><td>Config TDP Configurations</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Config TDP Configurations</td></tr><tr><td>Enable Configurable TDP</td><td>Applies to non-cTDP,Applies to cTDP</td><td>Applies TDP initialization settings based on non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and BIOS will bypass cTDP initialization flow</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal, Down2,Down1, Deactivate</td><td>Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>Configurable TDP Lock</td><td>Enabled,Disabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL.Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.</td></tr><tr><td>CTDP BIOS control</td><td>Enabled,Disabled</td><td></td></tr><tr><td>ConfigTDP Levels</td><td>2</td><td></td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>17 (Unlocked)</td><td></td></tr><tr><td>Power Limit 1</td><td>15.0W (MSR:15.0)</td><td></td></tr><tr><td>Power Limit 2</td><td>15.0W (MSR:15.0)</td><td></td></tr><tr><td colspan="3">Custom Settings Nominal</td></tr><tr><td>ConfigTDP Nominal</td><td>Ratio:18 TAR:1PL1:13.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in milliwatts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8,10, 12, 14, 16, 20, 24,28, 32, 40, 48, 56, 64,80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0xFF, 0x00, 0x01]</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td colspan="3">Custom Settings Nominal</td></tr><tr><td>ConfigTDP Nominal</td><td>Ratio:18 TAR:17PL1:15.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in milliwatts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>15000</td><td>Power Limit 2 value in milliwatts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>0</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td colspan="3">Custom Settings Level1</td></tr><tr><td>ConfigTDP Level1</td><td>Ratio:28 TAR:27PL1:1.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. The processor applies control policies to ensure that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>0</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td>CPU VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">CPU VR Settings</td></tr><tr><td>Current VccIn Aux Icc Max</td><td>108</td><td></td></tr><tr><td>PSYS Slope</td><td>0</td><td>PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9."</td></tr><tr><td>PSYS Offset</td><td>0</td><td>PSYS Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. PSYS Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>PSYS Prefix</td><td>+, -</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>PSYS PMax Power</td><td>0</td><td>PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.</td></tr><tr><td>Min Voltage Override</td><td>Disabled, Enabled</td><td>Min Voltage Override. Enable to override minimum voltage for runtime and for C8.</td></tr><tr><td>VccIn Aux Icc Max</td><td>0</td><td>Sets the Max Icc VccIn Aux value defined in 1/4A increments. Range is 0-512. For an IccMax 32A, enter 128(32*4).</td></tr><tr><td>VccIn Aux IMON Slope</td><td>111</td><td>VccIN Aux IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Offset</td><td>0</td><td>VccIN Aux IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Prefix</td><td>+.-</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>Vsys/Psys Critical</td><td>Disabled, PsysCritical,Vsys Critical</td><td>Vsys/Psys Critical enable or disable</td></tr><tr><td>Assertion Deglitch Mantissa</td><td>1</td><td>Assertion Deglitch Mantissa 0x4F[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>Assertion Deglitch Exponent</td><td>0</td><td>Assertion Deglitch Exponent 0x4F[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Mantissa</td><td>13</td><td>De Assertion Deglitch Mantissa 0x49[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Exponent</td><td>2</td><td>De Assertion Deglitch Exponent 0x49[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>VR Power Delivery Design</td><td>Auto</td><td>Specifies the ADL Desktop board design used for the VR settings override values. By default, BIOS will override the default Desktop VR settings based on the board design. A value of AUTO(0) will use the board ID to determine the board design. Any other value will override the board id logic to provide a custom VR Power Delivery Design value. This is intended primarily for validation.</td></tr><tr><td>Acoustic Noise Settings</td><td>Submenu</td><td></td></tr><tr><td>Acoustic Noise Mitigation</td><td>Disabled, Enabled</td><td>Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state</td></tr><tr><td>Pre Wake Time</td><td>0</td><td>Set the maximum Pre Wake randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation through Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Up Time</td><td>0</td><td>Set the maximum Ramp Up randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation through Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Down Time</td><td>0</td><td>Set the maximum Ramp Down randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation through Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td colspan="3">IA VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for IA Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during the deeper C state.</td></tr><tr><td>Slow Slew Rate for IA Domain</td><td>Fast/2, Fast/4, Fast/8, Fast/16</td><td>Set VR IA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise</td></tr><tr><td colspan="3">GT VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for GT Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during the deeper C state</td></tr><tr><td>Slow Slew Rate for GT Domain</td><td>Fast/2, Fast/4, Fast/8</td><td>Set VR GT Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled</td></tr><tr><td>Core/IA VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Core/IA VR Domain</td></tr><tr><td>VR Config Enable</td><td>Disabled, Enabled</td><td>VR Config Enable</td></tr><tr><td>Current AC Loadline</td><td>470</td><td></td></tr><tr><td>Current DC Loadline</td><td>470</td><td></td></tr><tr><td>Current Psi1 Threshold</td><td>16</td><td></td></tr><tr><td>Current Psi2 Threshold</td><td>8</td><td></td></tr><tr><td>Current Psi3 Threshold</td><td>4</td><td></td></tr><tr><td>Current Imon Slope</td><td>0</td><td></td></tr><tr><td>Current Imon Offset</td><td>1</td><td></td></tr><tr><td>Current VR Current Limit</td><td>212</td><td></td></tr><tr><td>Current Tdc Current Limit</td><td>272</td><td></td></tr><tr><td>Current Voltage Limit</td><td>1600</td><td></td></tr><tr><td>AC Loadline</td><td>0</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>0</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS Current Threshold1</td><td>16</td><td>PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold2</td><td>8</td><td>PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold3</td><td>4</td><td>PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS3 Enable</td><td>Disabled, Enabled</td><td>PS3 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS4 Enable</td><td>Disabled, Enabled</td><td>PS4 Enable/Disable. 0 - Disabled, 1 - Enabled.Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>0</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>0</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>+, -</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Current Limit</td><td>0</td><td>Voltage Regulator Current Limit (IccMax). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses BIOS VR mailbox command 0x6.</td></tr><tr><td>VR Voltage Limit</td><td>0</td><td>Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed at any given time. Range is 0 - 7999mV. Uses BIOS VR mailbox command 0x8.</td></tr><tr><td>TDC Enable</td><td>Disabled, Enabled</td><td>TDC Enable. 0- Disable, 1 - Enable</td></tr><tr><td>TDC Current Limit</td><td>0</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>1 sec</td><td>VR TDC Time Window, value in seconds. 1s is default. Range from 1s to 448s.</td></tr><tr><td>TDC Lock</td><td>Disabled, Enabled</td><td>TDC Lock</td></tr><tr><td>IRMS</td><td>Disabled, Enabled</td><td>Enable/Disable IRMS – Current root mean square</td></tr><tr><td>GT VR Settings</td><td>Submenu</td><td></td></tr><tr><td>RFI Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">RFI Domain</td></tr><tr><td>RFI Current Frequency</td><td>139.200MHz</td><td></td></tr><tr><td>RFI Frequency</td><td>0</td><td>Set desired RFI frequency, in increments of 100KHz. (For a frequency of 100.6MHz, enter 1006.)</td></tr><tr><td>FIVR Spread Spectrum</td><td>Disabled, Enabled</td><td>Enable or Disable the Spread Spectrum</td></tr><tr><td>RFI Spread Spectrum</td><td>0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%</td><td>Set the Spread Spectrum</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled, Enabled</td><td>Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>Disabled, Enabled</td><td>Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2.</td></tr><tr><td>Power Limit 4 Override</td><td>Disabled, Enabled</td><td>Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>Disabled, Enabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Thermal Monitor</td><td>Disabled, Enabled</td><td>Enable/Disable Thermal Monitor</td></tr><tr><td>Interrupt Redirection Mode Selection</td><td>Fixed Priority,Round robin,Hash Vector,No Change</td><td>Interrupt Redirection Mode Select for Logical Interrupts</td></tr><tr><td>Timed MWAIT</td><td>Disabled, Enabled</td><td>Enable/Disable Timed MWAIT Support</td></tr><tr><td>Custom P-state Table</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Custom P-state Table</td></tr><tr><td>Number of P-states</td><td>0</td><td>Sets the number of custom P-states. At lease 2 states must be present.</td></tr><tr><td>EC Turbo Control Mode</td><td>Disabled, Enabled</td><td>Enable/Disable EC Turbo Control mode</td></tr><tr><td>Energy Performance Gain</td><td>Disabled, Enabled</td><td>Enable/Disable Enerfy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>26</td><td></td></tr><tr><td>EPG DIMM ldd3P</td><td>11</td><td></td></tr><tr><td>Power Limit 3 Settings</td><td>Submenu</td><td></td></tr><tr><td>Power Limit 3 Override</td><td>Disabled, Enabled</td><td>Enable/DisablePower Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CPU Lock Configuration</td><td>Submenu</td><td>Enable/DisablePower Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CFG Lock</td><td>Disabled, Enabled</td><td>Configure MSR 0Xe2[15], CFG Lock bit</td></tr><tr><td>Overclocking Lock</td><td>Disabled, Enabled</td><td>Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR</td></tr></table>

7.3.2.2 Power & Performance Configuration > GT Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RC6(Render Standby)*</td><td>Disabled, Enabled</td><td>Check to enable render standby support.</td></tr><tr><td>Maximum GT frequency</td><td>Default MaxFrequency, 100Mhz, 150Mhz, 200Mhz, 250Mhz, 300Mhz, 350Mhz, 400Mhz, 450Mhz, 500Mhz, 550Mhz, 600Mhz, 650Mhz, 700Mhz, 750Mhz, 800Mhz, 850Mhz, 900Mhz, 950Mhz, 1000Mhz, 1050Mhz, 1100Mhz, 1150Mhz, 1200Mhz</td><td>Maximum GT frequency is limited by the user. Choose between 100MHz (RPN) and 1350MHz (RP0). Values beyond the range will be clipped to min/max supported by SKU</td></tr><tr><td>Disable Turbo GT frequency</td><td>Enabled, Disabled</td><td>Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited</td></tr></table>

7.3.3 Intel® Time Coordinated Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>#AC Split Lock*</td><td>Enabled, Disabled</td><td>Enable or disable Alignment Check Exception (#AC). When enabled, this will assert an #AC when any atomic operation has an operand that crosses two cache lines.</td></tr><tr><td>#GP Fault UC Lock</td><td>Enabled, Disabled</td><td>Enable or disable GP Fault Exception (GP#). When enabled, this will assert an GP# when encountering a Lock to un-cacheable memory before the bus is locked.</td></tr><tr><td>Intel(R) TCC Authentication*</td><td>OEM Enrolled Key</td><td>Intel(R) TCC Authentication determines the key to be used. OEM Enrolled Key is built in by OEM. Non-OEM Enrolled Key can be added by the user.</td></tr><tr><td>Intel(R) TCC Mode*</td><td>Enabled, Disabled</td><td>Enable or disable Intel(R) TCC Mode. When enabled, this will modify system settings to improve real-time performance. The full list of settings and their current state are displayed below when Intel(R) TCC mode is enabled.</td></tr><tr><td>Intel(R) TCC Mode Affected Settings</td><td></td><td></td></tr><tr><td>I/O Fabric Low Latency*</td><td>Disabled, Enabled</td><td>Enable or disable I/O Fabric Low Latency. This will turn off some power management features in the PCH IOfabrics. This option provides the most aggressive I/O Fabric performance settings. S3 state is NOT supported.</td></tr><tr><td>GT CLOS*</td><td>Disabled, Enabled</td><td>Enable or Disable Graphics Technology (GT) Class of Service. Enable will reduce Gfx LLC allocation to minimize impact of Gfx workload on LLC</td></tr><tr><td>C states*</td><td>Disabled, Enabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Intel(R) Speed Shift Technology*</td><td>Disabled, Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Intel(R) SpeedStep(tm)*</td><td>Disabled, Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>ACPI D3Cold Support*</td><td>Disabled, Enabled</td><td>Enable/Disable ACPI D3Cold support to be executed on D3 entry and exit</td></tr><tr><td>Low Power S0 Idle Capability*</td><td>Disabled, Enabled</td><td>This variable determines whether to enable ACPI Lower Power S0 Idle Capability (Mutually exclusive with Smart connect). When enabled, it also disables the 8254 timer for SLP_S0 support.</td></tr><tr><td>SA GV*</td><td>Disabled, Fixed to 1st Point, Fixed to 2nd Point, Fixed to 3rd Point, Fixed to 4th Point, Enabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency switching.</td></tr><tr><td>Page Close Idle Timeout*</td><td>Enabled, Disabled</td><td>Page Close Idle Timeout Control</td></tr><tr><td>Power Down Mode*</td><td>Auto, No Power Down, APD, PPD-DLLoff</td><td>CKE Power Down Mode Control</td></tr><tr><td>RC6(Render Standby) *</td><td>Disabled, Enabled</td><td>Check to enable render standby support.</td></tr><tr><td>DMI Link ASPM Control*</td><td>Disabled, L0s, L1, Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>Legacy I/O Low Latency*</td><td>Disabled, Enabled</td><td>Set to enable low latency of legacy I/O. Some systems require lower I/O latency irrespective of power consumption. This is a tradeoff between power usage and I/O latency.</td></tr><tr><td>CPU PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH PCI Express Configuration</td><td>Submenu</td><td></td></tr></table>

7.3.4 Graphic Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NXP configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>LVDS Backlight Mode</td><td>EC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight</td><td>Submenu</td><td></td></tr><tr><td>LVDS Backlight Brightness</td><td>Value Range(0-255)</td><td>A change takes effect immediately. The value range starts at 0 and ends at 255.</td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatibility</td><td>Choose between DisplayPort or HDMI for DDI port function</td></tr><tr><td>DDI port 2</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatibility</td><td>Choose between DisplayPort or HDMI for DDI port function</td></tr></table>

7.3.5 Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Disabled, Enabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Disabled, Enabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State*</td><td>Suspend Disabled, S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>LID Function</td><td>Disabled, Enabled</td><td>Enable/Disable LID Function</td></tr><tr><td>Sleep Function</td><td>Disabled, Enabled</td><td>Enable/Disable Sleep Button Function</td></tr><tr><td>ECO Mode*</td><td>Disabled, Enabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power-Up Mode*</td><td>Turn On, Remain Off, Last State</td><td>Turn On:</td></tr><tr><td colspan="3">ATTENTION: The Power-Up Mode only has effect, if the module is in ATX-Mode.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td></td></tr></table>

7.3.5.1 Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info only</td><td></td></tr><tr><td>Main Current</td><td>Read only</td><td>Displays input current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Displays input power.</td></tr><tr><td>RTC</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>5VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>VIN</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3V</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VMEM</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VCORE</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr></table>

# 7.3.6 System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info Only</td><td></td></tr><tr><td>Version</td><td>Info Only</td><td>Displays SEMA Module Version.</td></tr><tr><td>SEMA Firmware</td><td>Info Only</td><td>Displays SEMA Firmware Version.</td></tr><tr><td>SEMA Flags</td><td>Submenu</td><td>Displays SEMA Flags</td></tr><tr><td>SEMA Features</td><td>Info</td><td>Displays SEMA Supported Features</td></tr></table>

# 7.3.6.1 System Management > SEMA Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Flags</td><td>Info Only</td><td></td></tr><tr><td>BIOS Select</td><td>Info Only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Info Only</td><td></td></tr></table>

7.3.7 Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info Only</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C100 C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Active Cooling Trip Point</td><td>40C, 50C, 60C, 70C, Refer to BMC</td><td>This value is the temperature threshold of the active cooling trip point.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled</td></tr><tr><td>Temperature and Fan Speed</td><td>Submenu</td><td></td></tr></table>

7.3.7.1 Thermal Management-> Temperature and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Displays Current CPU Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Displays Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Displays Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Displays Max Board Temperature</td></tr><tr><td>Board Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Displays Current Board Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Displays Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Displays Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Displays Max Board Temperature</td></tr></table>

7.3.8 Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>Disabled Enabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up. Pressing F12 during start up disables the Power Up Watchdog</td></tr><tr><td>Timeout</td><td>65535</td><td>Here you can enter the time the Power Up Watchdog should wait until it resets the system. The value range starts at 24 and ends at 65535.</td></tr><tr><td>RunTime Watchdog</td><td>Disabled Enabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>24</td><td>Here you can enter the time the Runtime Watchdog should wait until it resets the system. The value range starts at 30 and ends at 65535.</td></tr></table>

7.3.9 Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super I/O Configuration</td><td>Info only</td><td></td></tr><tr><td>IT5121E Super I/O Configuration</td><td>Submenu</td><td>System Super I/O Chip Parameters.</td></tr><tr><td>W83627DHGSEC Super I/O Configuration</td><td>Submenu</td><td>System Super I/O Chip Parameters.</td></tr></table>

7.3.9.1 Super I/O Configuration > IT5121E Super I/O Configuration (W83627DHGSEC Super IO Configuration)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">IT5121E Super I/O Configuration (W83627DHGSEC Super I/O Configuration)</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr></table>

Submenu: Super I/O Configuration > Serial Port x Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Serial Port 1 Configuration</td></tr><tr><td>Serial Port 1 Configuration</td><td>Disabled, Enabled</td><td>Set Parameters of Serial Port 1</td></tr><tr><td>Device Settings</td><td>4;</td><td></td></tr><tr><td>Change Settings</td><td>Auto, IO=3F8h; IRQ=4; IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12;</td><td>Select an optimal setting for Super I/O Device</td></tr><tr><td>Change Settings</td><td>Normal, High Speed</td><td>Select an optimal setting for Super I/O Device</td></tr><tr><td colspan="3">Serial Port 2 Configuration</td></tr><tr><td>Serial Port 2 Configuration</td><td>Disabled, Enabled</td><td>Set Parameters of Serial Port 2</td></tr><tr><td>Device Settings</td><td>3;</td><td></td></tr><tr><td>Change Settings</td><td>Auto, IO=2F8h; IRQ=3;, IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12;, IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12;, Normal, High Speed</td><td>Select an optimal setting for Super IO Device</td></tr></table>

7.3.10 Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>Select the Emulation AT or ATX function. If this option is set to [Emulation AT], BIOS will report no suspend functions (S3 &amp; S4) to ACPI OS. In windows XP, the OS will show shutdown message during a system shutdown. ATX: OS will turn off system power during a shutdown.</td></tr><tr><td>I2C Speed Control</td><td>100 kbps400 kbps</td><td>I2C Speed Control</td></tr><tr><td>SMBUS Select Configuration</td><td>From EC,From PCH</td><td>SMBUS select configuration from PCH or EC.</td></tr><tr><td>WOL From S5</td><td>OFFON</td><td>This Config to control power on/off LAN in S5 State by SEMA(EC).</td></tr><tr><td>LID Function</td><td>DisabledEnabled</td><td>Enable/Disable LID function.</td></tr><tr><td>Sleep Function</td><td>DisabledEnabled</td><td>Enable/Disable Sleep Function.</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr></table>

7.3.11 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attachment USB devices.</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support.The XHCI ownership change should be claimed by the XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable/Disable USB Mass Storge Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.'Auto' uses default value: for a Root port it is 100ms., for a Hub port the delay is taken from the Hub descriptor.</td></tr><tr><td>Mass Storage Device</td><td>Info Only</td><td></td></tr></table>

# 7.3.12 NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVMe Configuration</td><td>Info Only</td><td></td></tr></table>

# 7.3.13 AMI Graphics Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Intel(R) Graphics Controller</td></tr><tr><td colspan="3">Intel(R) GOP Driver [21.0.10XX]</td></tr><tr><td>Output Select</td><td>Output Select</td><td>Output Select</td></tr></table>

# 7.3.14 Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>Disabled, Enabled</td><td>To enable or disable console redirection of COMx.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

7.3.14.1 Serial Console Redirection > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Configure the type of console emulation.Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects the serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require a lower speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Configure the number of data bits in each transmitted or received serial character for both serial ports.</td></tr><tr><td>Parity</td><td>NoneEvenOdd</td><td>Configures whether a parity bit is generated (transmit data) or checked.A parity bit can be sent with the data bits to detect some transmission errors.Even: The parity bit is 0 if the num of 1's in the data bits is even.Odd: The parity bit is 0 if num of 1's in the data bits is odd.Mark: The parity bit is always 1.Space: The parity bit is always 0.Mark and Space parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Configures the number of stop bits transmitted and received in each serial character for both serial ports.Stop bits indicate the end of a serial data packet (a start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareSoftware</td><td>Configures flow control for console redirection. Hardware flow control uses RTC/CTS. Software flow control uses XON/XOFF.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 combination key support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled, only text will be sent. This is to capture terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables or disables extended terminal resolution.</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select Function Keys and Key Pad on Putty.</td></tr></table>

7.3.15 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Disabled, Enabled</td><td>Enable/Disable UEFI Network Stack</td></tr><tr><td>IPv4 PXE Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv4 HTTP Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.</td></tr><tr><td>IPv6 PXE Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>IPv6 HTTP Support</td><td>Disabled, Enabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x05, 0x00, 0x01]</td><td>Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x32, 0x01, 0x01]</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

7.3.16 Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable, Enable</td><td>Enables or disables BIOS support for a security device. The O.S. will not show the security device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td colspan="3">NO Security Device Found</td></tr></table>

# 7.4 Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>submenu</td><td></td></tr></table>

7.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>submenu</td><td></td></tr><tr><td>Graphics Configuration</td><td>submenu</td><td></td></tr><tr><td>TCSS setup menu</td><td>submenu</td><td></td></tr><tr><td>Stop Grant Configuraion</td><td>Auto, Manual</td><td>Automatic/Manual stop grant configuration</td></tr><tr><td>VT-d</td><td>Enabled, Disabled</td><td>VT-d capability</td></tr><tr><td>Control Iommu Pre-boot Behavior</td><td>Disable IOMMU Enable IOMMU during boot</td><td>Enable IOMMU in Pre-boot environment (If DMAR table is installed in DXE and If VTD_INFO_PPI is installed in PEI.)</td></tr><tr><td>X2APIC Opt Out</td><td>Enabled, Disabled</td><td>Enable/Disable X2APIC_OPT_OUT bit</td></tr><tr><td>DMA Control Guarantee</td><td>Enabled, Disabled</td><td>Enable/Disable DMA_CONTROL_GUARANTEE bit</td></tr><tr><td>WRC Feature</td><td>Enabled, Disabled</td><td>Enable/Disable SA WRC (Write Cache) Feature of IOP. When enabled, supports I/O devices allocating onto the ring and into LLC.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enabled, Disabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment. This is enabled automatically when Aperture Size is set to 2048MB.</td></tr><tr><td>IPU Device (B0:D5:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU Device</td></tr><tr><td>IPU 1181 Dash Camera</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU 1181 Dash Camera support</td></tr></table>

7.4.1.1 System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info-only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info-only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info-only</td><td></td></tr><tr><td>Controller x Channel x Slot x</td><td>Info-only</td><td></td></tr><tr><td>Size</td><td>Info-only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info-only</td><td></td></tr><tr><td>Manufacturer</td><td>Info-only</td><td></td></tr><tr><td>Memory Test on Warm Boot</td><td>Enabled, Disabled</td><td>Enable Or Disable Base Memory Test Run on Warm Boot</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067133314001600180018672000213322002400260026672800293330003200......12800</td><td>Maximum Memory Frequency Selections in Mhz.</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIOlength of installed graphic controller</td></tr><tr><td>SA GV</td><td>Enabled, Disabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency swithing.</td></tr><tr><td>Controller 0, Channel X DIMM Control</td><td>Enabled, Disabled</td><td>Controller 0, Channel X DIMM Control Support - Enable or Disable Dimms on Controller 0, Channel X.</td></tr><tr><td>Controller 1, Channel X DIMM Control</td><td>Enabled, Disabled</td><td>Controller 1, Channel X DIMM Control Support - Enable or Disable Dimms on Controller 1, Channel X.</td></tr><tr><td>Force Single Rank</td><td>Disabled, Enabled</td><td>When enabled, only Rank 0 will be used in each DIMM</td></tr><tr><td>In-Band ECC Support (Industrial SKU only)</td><td>Enabled, Disabled</td><td>Enable/Disable In-Band ECC. Either the IBECC or the TME can be enabled.</td></tr></table>

# 7.4.1.2 System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scaning of External Gfx Card</td><td>Disabled, Enabled</td><td>If enabled, it will not scan for External Gfx Card on the PEG and PCH PCIe ports.</td></tr><tr><td>Primary Display</td><td>Auto, IGFX, PEG Slot, PCH PCI, HG</td><td>Select which of the IGFX/PEG/PCI Graphics devices should be the primary display or select HG for Hybrid Gfx.</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>submenu</td><td></td></tr><tr><td>Internal Graphics</td><td>Auto, Disabled, Enabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB, 4MB, 8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB, 256MB, 512MB,1024MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M, 32M, 64M, 96M, 128M, 160M, 4M, 8M, 12M, 16M, 20M, 24M, 28M, 32M/F7, 36M, 40M, 44M, 48M, 52M, 56M, 60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>Intel Graphics Pei Display Peim</td><td>Enabled, Disabled</td><td>Enable/Disable Pei (Early) Display</td></tr></table>

7.4.1.3 System Agent (SA) Configuration > TCSS setup menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IOM FW version:</td><td>Info-only</td><td></td></tr><tr><td>PHY FW version:</td><td>Info-only</td><td></td></tr><tr><td>TBT FW IMR Status:</td><td>Info-only</td><td></td></tr><tr><td>TBT FW version:</td><td>Info-only</td><td></td></tr><tr><td>Deepest TC state:</td><td>Info-only</td><td></td></tr><tr><td>TCSS xHCI Support</td><td>Disabled, Enabled</td><td>Enable/Disable TCSS xHCI</td></tr><tr><td>TCSS USB Configuration</td><td>submenu</td><td>SA TCSS USB Configuraion settings</td></tr><tr><td>VCCST status of IOM</td><td>Disabled, Enabled</td><td>Enables/Disables VCCST. Enable: Sends VCCST ON message to EC or PMC Disable: Sends VCCST OFF message to EC or PMC</td></tr><tr><td>D3 Cold Enable/Disable</td><td>Disabled, Enabled</td><td>Enables/Disables D3 Cold. Enable: D3 cold support for IOM is enabled. Disable: D3 cold support for IOM is Disabled</td></tr><tr><td>D3Hot</td><td>Disabled, Enabled</td><td>Enables/Disables D3 Hot. Enable: D3 Hot support for IOM is enabled. Disable: D3 Hot support for IOM is Disabled</td></tr><tr><td>Tc C-State Limit</td><td>Disable, 1, 2, 4, 5, 6, 7, 10</td><td>BIOS mailbox to limit deepest TCx state</td></tr><tr><td>TC Cold Power Saving Factor</td><td>Disabled, Enabled</td><td>TC Cold Power Saving Factor Switch</td></tr></table>

7.4.1.3.1 System Agent (SA) Configuration > TCSS setup menu > TCSS USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB CONNECT OVERRIDE</td><td>Disabled, Enabled</td><td>This option will allow VCCSTTPC to turn off even when there is a connection for a USB3 port.</td></tr><tr><td>TCSS xDCI Support</td><td>Disabled, Enabled</td><td>Enable/Disable TCSS xDCI</td></tr><tr><td>TCSS CPU USB PDO Programming</td><td>Disabled, Enabled</td><td>Select &#x27;Enabled&#x27; if the Port Disable Override functionality is used.</td></tr><tr><td>TCSS CPU USB Port Disable Override</td><td>Disabled, Select Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a device connection to the controller.</td></tr></table>

7.4.1.3.2 System Agent (SA) Configuration > MIPI Camera Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CVF Support</td><td>Disabled, Enabled</td><td>Disables/Enables CVF using either Native IOs or USB IOs expansion.</td></tr><tr><td>Control Logic 1</td><td>Disabled, Enabled</td><td>Control Logic 1</td></tr><tr><td>Control logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Control logic 2</td><td>Disabled, Enabled</td><td>Control logic 2</td></tr><tr><td>Control logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Camera1</td><td>Disabled, Enabled</td><td>Camera1</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr><tr><td>Camera2</td><td>Disabled, Enabled</td><td>Camera2</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr></table>

7.4.2 PCH-I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>Security Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial IO Configuration</td><td>Submenu</td><td></td></tr><tr><td>SCS Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN Controller</td><td>Info-Only</td><td>No GbE Region</td></tr><tr><td>Port 80h Redirection</td><td>Fixed setting- LPC Bus</td><td>Control where the Port 80h cycles are sent.</td></tr><tr><td>Enhance Port 80h LPC Decoding</td><td>Enabled, Disabled</td><td>Support the word/dword decoding of port 80h behind LPC</td></tr><tr><td>Enable TCO Timer</td><td>Disabled, Enabled</td><td>Enable/Disable TCO timer. When disabled, it disables the PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.</td></tr><tr><td>PCIe Ref PII SSC</td><td>Auto, 0.0%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, Disabled</td><td>PCIe PII SSC percentage. AUTO - Keeps hardware default, no BIOS override. Range is 0.0%-0.5%.</td></tr><tr><td>SPD Write Disable</td><td>TRUE, FALSE</td><td>Enable/Disable the SPD Write Disable setting. For security recommendations, the SPD write disable bit must be set.</td></tr></table>

7.4.2.1 PCH-I/O Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>DMI Link ASPM Control</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>Port8xh Decode</td><td>Disabled, Enabled</td><td>PCI Express Port8xh Decode Enable/Disable.</td></tr><tr><td>PCIe Ports 3-4 Configuration</td><td>2x1 Port, 1x2 Port</td><td>Notes:Please make sure to complete the system boots after changing the configuration.Do Not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.</td></tr><tr><td>PCIe Ports 9-10 Configuration</td><td>2x1 Port, 1x2 Port</td><td>Notes:Please make sure to complete the system boots after changing the configuration.Do Not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.</td></tr><tr><td>PCI Express Root Port 1</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 2</td><td>Info-Only</td><td></td></tr><tr><td>PCI Express Root Port 3 (COMe Lane 0)</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 4 (COMe Lane 1)</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 5</td><td>Info-Only</td><td></td></tr><tr><td>PCI Express Root Port 6</td><td>Info-Only</td><td></td></tr><tr><td>PCI Express Root Port 7</td><td>Submenu</td><td>.</td></tr><tr><td>PCI Express Root Port 8</td><td>Info-Only</td><td></td></tr><tr><td>PCI Express Root Port 9 (COMe Lane 2)</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 10 (COMe Lane 3)</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 11</td><td>Info-Only</td><td></td></tr><tr><td>PCI Express Root Port 12</td><td>Info-Only</td><td></td></tr></table>

7.4.2.2 PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port#

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port</td><td>DisabledEnable</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level.Force L0s - Force all links to L0s StateAuto - BIOS auto configure;Disabled - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>L1 Low</td><td>DisabledEnable</td><td>PCI Express L1 Low Substate Enable/Disable.</td></tr><tr><td>ACS</td><td>DisabledEnable</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>DisabledEnable</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>DisabledEnable</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>DisabledEnable</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>DisabledEnable</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>DisabledEnable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>DisabledEnable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>DisabledEnable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>CTO</td><td>DisabledEnable</td><td>PCI Express Completion Timer TO Enable/Disable</td></tr><tr><td>SEFE</td><td>DisabledEnable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>DisabledEnable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>DisabledEnable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>DisabledEnable</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>DisabledEnable</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>DisabledEnable</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PCIe Speed.</td></tr><tr><td>Transmitter Half Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Non-Compliance</td><td>DisabledEnable</td><td>Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assumingthere is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB.</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info only</td><td></td></tr><tr><td>LTR</td><td>Disabled Enable</td><td>PCH PCIe Latency Reporting Enable/Disable.</td></tr><tr><td>Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Snoop Latency Override for PCH PCIe. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow."</td></tr><tr><td>Non-Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Non-Snoop Latency Override for PCH PCIe. Disabled: Disable override. Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>LTR Lock</td><td>Disabled Enable</td><td>PCIe LTR Configuration Lock</td></tr></table>

7.4.2.3 PCH-I/O Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Disabled, Enabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Controller Speed</td><td>Default, Gen1, Gen2, Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Test Mode</td><td>Disabled, Enabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Aggressive LPM Support</td><td>Disabled, Enabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>Serial ATA Port X</td><td>Info-Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info-Only</td><td></td></tr><tr><td>Port X</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td>Info Only</td><td></td></tr><tr><td>External</td><td>Disabled, Enabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>Disabled, Enabled</td><td>If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive, Solid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td>Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2</td></tr><tr><td>SATA Port X DevSlp</td><td>Disabled, Enabled</td><td></td></tr><tr><td>DITO Configuration</td><td>Disabled, Enabled</td><td></td></tr><tr><td>DITO Value</td><td>625</td><td></td></tr><tr><td>DM Value</td><td>15</td><td></td></tr></table>

7.4.2.4 PCH-I/O Configuration >USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xDCI Support</td><td>Disabled, Enabled</td><td>Enable/Disable xDCI (USB OTG Device).</td></tr><tr><td>USB2 PHY Sus Well Power Gating</td><td>Disabled, Enabled</td><td>Select &#x27;Enabled&#x27; to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H</td></tr><tr><td>USB PDO Programming</td><td>Disabled, Enabled</td><td>Select &#x27;Enabled&#x27; if the Port Disable Override functionality is used.</td></tr><tr><td>USB Overcurrent</td><td>Disabled, Enabled</td><td>Select &#x27;Disabled&#x27; for the pin-based debug. If the pin-based debug is enabled but USB overcurrent is not disabled, USB DbC will not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>Disabled, Enabled</td><td>Select &#x27;Enabled&#x27; if the Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Audio Offload</td><td>Disabled, Enabled</td><td>Enable/Disable USB Audio Offload functionality</td></tr><tr><td>Enable HSII on xHCI</td><td>Disabled, Enabled</td><td>Enable/Disable the HSII feature. It may lead to increased power consumption.</td></tr><tr><td>USB3.1 Portx Speed Selection</td><td>0</td><td>Port Selection value in decimal for Gen1; Default - Gen2; Bit 0 corresponds to Port 0 and so on</td></tr><tr><td>USB Port Disable Override</td><td>Disabled, Select Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a device connection to the controller.</td></tr></table>

7.4.2.5 PCH-I/O Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Memory Lock</td><td>Disabled, Enabled</td><td>Enabling it will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>Disabled, Enabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure the SMM protection of flash.</td></tr><tr><td>Force unlock on all GPIO pads</td><td>Disabled, Enabled</td><td>If Enabled BIOS will force all GPIO pads to be in unlocked state</td></tr></table>

7.4.2.6 PCH-I/O Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device.</td></tr></table>

7.4.2.7 PCH-I/O Configuration > Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Serial IO Controller</td></tr><tr><td>I2C1 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables Serial IO Controller</td></tr><tr><td>SPI0 Controller</td><td>Disabled, Enabled</td><td>Enables/Disables SPI0 Controller</td></tr><tr><td>UART0 Controller</td><td>Disabled, Enabled, Communication port (COM)</td><td>Enables/Disables Serial IO Controller</td></tr><tr><td>UART1 Controller</td><td>Disabled, Enabled, Communication port (COM)</td><td>Enables/Disables Serial IO Controller</td></tr><tr><td>GPIO IRQ Route</td><td>IRQ14, IRQ15</td><td>Route all GPIOs to one of the IRQ.</td></tr></table>

7.4.2.8 PCH-I/O Configuration > SCS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>eMMC 5.1 Controller</td><td>Disabled, Enabled</td><td>Enable or Disable SCS eMMC 5.1 Controller</td></tr><tr><td>eMMC 5.1 HS400 Mode</td><td>Disabled, Enabled</td><td>Enable or Disable SCS eMMC 5.1 HS400 Mode</td></tr><tr><td>Enable HS400 software tuning</td><td>Disabled, Enabled</td><td>Software tuning should improve eMMC HS400 stability at the expense of boot time</td></tr><tr><td>Driver Strength</td><td>33 Ohm, 40 Ohm, 50 Ohm</td><td>Sets I/O driver strength</td></tr><tr><td>UFS 2.0 Controller 1</td><td>Disabled, Enabled,</td><td>Enable or Disable UFS 2.0 Controller</td></tr></table>

# 7.5 Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Administrator Password</td><td>Enter password</td><td></td></tr><tr><td>User Password</td><td>Enter password</td><td></td></tr><tr><td>Secure Boot menu</td><td>submenu</td><td></td></tr></table>

# 7.5.1 Secure Boot menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Boot</td><td>DisabledEnabled</td><td>The Secure Boot feature is Active if Secure Boot is Enabled, the platform Key(PK) is enrolled and the system is in User mode, The mode change requires a platform reset</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication</td></tr><tr><td>Restore Factory Keys</td><td></td><td>Force System to User Mode. Install factory default Secure Boot key databases</td></tr><tr><td>Reset To Setup Mode</td><td></td><td>Delete all Secure Boot Key databases from NVRAM.</td></tr><tr><td>Key Management</td><td>Submenu</td><td>Enables expert users to modify. Secure Boot Policy variables without variable authentication.</td></tr></table>

# 7.6 Boot

7.6.1 Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option.Has no effect for BBS boot option.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll Sata Devices</td><td>If Last Boot SATA Devices Only is selected, only the SATA device in the last boot will be available in POST. If All SATA devices is selected, all SATA devices will be available in the OS and Post.</td></tr><tr><td>VGA Support</td><td>AutoEFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. Efi driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>DisabledFull InitialPartial Initial</td><td>If disabled, all USB devices will NOT be available until after the OS boots. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before the OS boots. If enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>DisabledEnabled</td><td>If disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>DisabledEnabled</td><td>If disabled, NetWork Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>DisabledEnabled</td><td>If disabled, the Redirection function will be disabled.</td></tr><tr><td>Boot Mode select</td><td>UEFI LEGACY</td><td>Select boot mode LEGACY/UEFI</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Info only</td><td></td></tr><tr><td>UEFI Hard Disk Drive BBS Priorities</td><td>Submenu</td><td></td></tr><tr><td>UEFI Application Boot Priorities</td><td>Submenu</td><td></td></tr></table>

7.7 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Change and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save the changes done to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td></td></tr><tr><td>Restore Defaults</td><td></td><td></td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done as user defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

# 8. BIOS Checkpoints, Beep Codes

This section of this document lists the checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined here are inherent to the AMIBIOS generic core, and do not include any chipset or board-specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

Security (SEC) – initial low-level initialization
Pre-EFI Initialization (PEI) – memory initialization1
• Driver Execution Environment (DXE) – main hardware initialization2
• Boot Device Selection (BDS) – system setup, pre-OS user interface, and selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, and more)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a POST Card or POST Diagnostic Card. These are PCI addin cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. However, this display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

# 8.1 Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xFC</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2 Standard Status Codes

# 8.2.1 SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr></table>

<table><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2 SEC Beep Codes

None

8.2.3 PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self-test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4 PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5 DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

8.2.6 DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

8.2.7 ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

# 8.3 OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

# 9 Software Support

# 9.1 Operation System

Microsoft Windows 64-bit

Windows 10 IoT Enterprise LTSC 2021

Windows 11 IoT Enterprise LTSC 24H2

Canonical Ubuntu 64-bit

Ubuntu 20.04.4 LTSC (desktop version)

Yocto Project based on Linux 64-bit

https://github.com/ADLINK/meta-adlink-x86-64bit (TBC)

![This image displays a red icon of a document or file. It features a white square shape with a folded bottom-right corner. Inside the square, there are two horizontal red lines.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/fa335a496f377d41cb2f37272cbf4f34701592e9888d145d40e7a3dc64ef9445.jpg)

Note: Other OS might be supported by project basis. Please contact your local ADLINK representative for further discussion x7000C SKUs (Headless SKUs) support Linux only (TBC)

# 9.2 Other Software

SEMA Library

Support PICMG COM Express defined EAPI and ADLINK’s extensions for more embedded features. Get details in link below:

https://www.adlinktech.com/Products/DownloadMDownload?lang=en&pdNo=1274&MainCategory=Industrial\_IoT\_and\_Cloud\_solutions&kind=M

# 10. Mechanical and Thermal

All dimensions are shown in mm with a tolerance of +/- 0.25mm unless otherwise noted.

10.1 Module Dimensions – Top View
![| Dimension | Value  |\n| --------- | ------ |\n| Top Left   | 95     |\n| Top Right  | 80     |\n| Bottom Left| 74.2   |\n| Bottom Right| 16.5  |\n| Bottom Right| 4      |\n| Bottom Right| 0      |\n| Bottom Right| 4      |\n| Bottom Right| 6      |\n| Bottom Right| 18     |\n| Bottom Right| 33     |\n| Bottom Right| 53.016 |\n| Bottom Right| 91     |\n| Bottom Right| 91     |\n| Bottom Right| 95     |\n| Bottom Right| 81.424 |\n| Bottom Right| 21.4   |\n| Bottom Right| 4      |](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/5d2b532b3b645b25360e4b7ed96618795bbed129e69d49ae4f0fb30c29be0574.jpg)

# 10.2 Module Dimensions – Side View

![Technical line drawing of a mechanical component with a dimension label '2' (no text or symbols beyond the numeral)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/d6a442e3c944030980da79817a594b12a98b21058bfb7dc568a827f68ee20834.jpg)

# 10.3 Height of Processor and Static Compressive Load

# Processor Height Tolerance

The tolerance of the processor height is one of the key factors to consider when designing your thermal solution, as illustrated below. Please contact our ADLINK representative for further details.

![Die\nDie\nSubstrate\nModule PCB\nh](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/dbb8a94f2c890eb36df873f53d087a5d302115d58c7f604eb92f42ae8f610527.jpg)

<table><tr><td></td><td>Typical</td><td>Tolerance</td></tr><tr><td>h</td><td>1.345 mm</td><td>+/- 0.109mm</td></tr></table>

# Static Compressive Load

Another key factor to consider is the static compressive load. The cExpress-ASL/ALN module exhibits a maximum processor pressure die of 15 lbf.

Figure 5 – Module mechanical dimensions

# 10.4 Thermal Solutions

# 10.4.1 Heatspreader: HTS

![95\n95\n11\n76\n87\n65\n87\nM2.5x2\nM2.5x4](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/298e6fdc686956ff515e96ca575e9ceb346969ccebdef772cbc9510d534041ec.jpg)

Dimensions: mm

Figure 6 – Heatspreader: HTS

# 10.4.2 Heatsink: THS

![The image displays a technical drawing of a heatsink assembly featuring multiple orthographic and isometric views.\n\n**Top Left:** A front view of the finned heatsink block is shown with a vertical dimension of **95** and a horizontal dimension of **95**. Below this is a side profile view indicating a base thickness of **17.00**.\n\n**Top Right:** A view of the square mounting plate is shown with a horizontal dimension of **87** and a vertical dimension of **87**. A vertical dimension of **76** indicates the spacing of the mounting features.\n\n**Bottom:** Two isometric views are presented. The bottom left shows the heatsink fins. The bottom right shows the mounting base plate with cylindrical posts. Text labels point to these posts: **M2.5x4** points to a corner post, and **M2.5x2** points to an inner post.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/28bf695ca68faf7b2c6103a09bb6162c30069b340ff3d0ec7b37bd43208070ee.jpg)
Dimensions: mm

Figure 7 – Heatsink: THS

# 10.4.3 Heatsink High Profile: THSH

Dimensions: mm

![95\n95](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/5d2164541f9cde88a2c5c74eefe0723d5c75092742a23c66595495d0cb7d0967.jpg)

![Pure electrical circuit lines without any symbols](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/4f85c11e5e61a3995a19b440c948f86c4482c9f28142c720e1dcaa28da66ebdf.jpg)

![76\n87\n87](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/ec452abf9cd3787a4680959257a91edc1dccbe694518a523ed29e44ecfa02fa3.jpg)

![Technical drawing of a rectangular electronic component with a 36-unit height dimension labeled (no other text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/46b44739216a98bdfee1a757c92939b588d97008d592f0ca8c6ab7c18f19b9bb.jpg)

![M2.5x2\nM2.5x4](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/f25578b62448ea114c25cb01d4ae421b2941bd57f919d808b6aaf4ebfee90153.jpg)

Figure 8 – Heatsink high profile: THSH

# 10.4.4 Heatsink with Fan: THSF

![The image displays a technical engineering drawing of a CPU cooler featuring multiple orthographic and perspective views with dimensions.\n\n*   **Top Left:** A front view of the heatsink with a fan attached. Vertical and horizontal dimension lines are both labeled **'95'**.\n*   **Top Middle:** A side profile view showing the density of the cooling fins.\n*   **Top Right:** A top-down view of the mounting bracket/base plate. It is labeled with width and height dimensions of **'87'**, and a vertical mounting hole spacing dimension of **'76'**. The text **'Dimensio'** is partially visible in the top right corner.\n*   **Bottom Left:** A side view of the heatsink block itself, labeled with a height of **'36'**.\n*   **Bottom Center/Right:** Two 3D perspective views. The center view shows the fan installed on the fins. The right view shows the top plate with mounting posts, featuring callout lines labeled **'M2.5x2'** and **'M2.5x4'**.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/93d450bd796698abd3fd78c53808d839dce4ef7f4fff7ea6c17dccb855064d80.jpg)
Dimensions: mm

Figure 9 – Heatsink with fan: THSF

# 10.5 Board to Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

# 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm

This connector can be used with 5 mm through-hole standoffs (SMT type).

Tyco 3-1827253-6, Tyco 2357787-1
ept 401-51101-51, ept 401-51103-51
Foxconn QT002206-2141-3H, Foxconn QT5GB26-44703-3H

# 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm

This connector can be used with 8 mm through-hole standoffs (SMT type)

Tyco 3-6318491-6, Tyco 2357798-1
ept 401-55101-51, ept 401-55103-51
Foxconn QT002206-4141-3H, Foxconn QT5GB26-74703-3H

# Common Specifications

Current capacity: 0.5A per pin
Rated voltage: 50 VAC
Insulation resistance: 100M or greater @ 500 VDC
Temperature rating: -40°C \~ 85°C
UL certification (ECBT2.E28476)

Copper alloy (contacts)
Housing: thermo-plastic molded compound (L.C.P.)

# 10.6 Mounting Method

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. Apart from choosing 5 mm or 8mm board-to-board connectors, you can opt for either top and bottom mounting. In top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

![Top Mounting\nwith 5 mm connectors\nM2.5 : 18 mm\nwith spring / washer\n2 mm heatspreader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n5 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm\nBottom Mounting\nwith 5 mm connectors\nM2.5 : 14 mm\nwith spring / washer\n2 mm heatspreader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n5 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 16 mm\nwith spring / washer\nTop Mounting\nwith 8 mm connectors\nM2.5 : 18 mm\nwith spring / washer\n2 mm heatspreader with\n9 mm through-hole standoffs\nCOM Express Module ~ 2 mm\n8 mm threaded standoff (DIP)\nCarrier Board ~ 2 mm\nBottom Mounting\nwith 8 mm connectors\nM2.5 : 18 mm\nwith spring / washer\n2 mm heatspreader with\n9 mm threaded standoffs\nCOM Express Module ~ 2 mm\n8 mm through hole standoff (SMT)\nCarrier Board ~ 2 mm\nM2.5 : 16 mm\nwith spring / washer](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/e124d9cf1ee4809bc2084ad91b3068c53e840291081692002df17d577fd9d388.jpg)

# 10.7 Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type) P/N: 33-72000-0050
![Ø5.5\nØ2,8\n7\n5\n4.1](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/952209c786c0926f09042155295736805ba226d8120eb1c2bf3e08a14109baa3.jpg)

5mm threaded standoff (DIP type) P/N: 33-72016-0050
![M2.5\nØ5.5\n7\n5\n4.1](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/fa73816d08aaf4b9f8fcb478198fd56080ec8711cb9ae22e1fb8e349b1b2fc09.jpg)

8mm through-hole standoff (SMT type) P/N: 33-72000-0080
![Ø5,5\nØ2,6\n9,6\n8\n4,1](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/2282a8d661e7ce7370bf0c2b7cfad5b709426b125550d5cb716ffa4bce858cca.jpg)

8mm threaded standoff (DIP type) P/N: 33-72015-0050
![M2.5\nØ5.5\n10\n8\n5,7\n4.1](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/6d87503d4cefb63ee79426ce2c7472a4c825f1a51ba7840bd0896e4d9e12b34b.jpg)

# 10.8 Installation

Install a heatspreader or heatsink using the following instructions. The pictures below are for illustration purpose only.

Step 1: Remove the protective membranes from the thermal pads.

![Close-up of a microfluidic device with tweezers applying material to a green liquid crystal (no text or symbols visible)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/dda719b9014c02815e4c61b53d8a1bd49c29d14635c666ef1fac558b87370b15.jpg)

![The image shows a red icon of a document with a folded bottom-right corner. Inside the outline, there are two horizontal red lines centered within the shape.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/737dcc71e0f89359dcbb29af3f32164013f5a60ed3656a69170e0d67073559b7.jpg)

Note: All thermal pads have a protective membrane, depending on the module.

Step 2: Assemble the heatsink onto the COM Express module. Use the provided M2.5, L=6 mm screws to secure the heatsink to the module. The number of screw holes and screws depends on the module.

![DEV-0050958\n51-7221-0410\nC:\Program Files\NT 6.3.1.1\nSIN\n400mm x 100x 200mm\nDCT 2000\n1.8-3.4\n1.8-3.4](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/7bb0acdef1f1481b1df5184960c7e35cf00100aed03d621cfe08a80a883624ca.jpg)

![Two identical vertical objects, appearing to be stacks of metallic discs, stand side-by-side against a plain white background. Each object consists of a flat, silver-colored disc at the top with a central hole, followed by a series of stacked, darker metallic discs of varying sizes, and finished with a dark, cylindrical base at the bottom.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/1d639a34fdf16e61c90c433c5686dc15bde7b3f4cf375dc9625171734a8a4270.jpg)

Step 3: Place the COM Express module and heatsink assembly onto the connectors on the carrier board, as shown below. Then press down on the module until it is firmly seated on the carrier board.

![Close-up of hands holding a heatsink placed on a green printed circuit board (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/50b09c228d210da39b75f8ebe80d8745c8f9b114c4b4f722bbdb919e8222aca0.jpg)

Step 4: Use the M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.

The number of screw holes and screws are module and carrier board design dependent.

![Close-up of a green printed circuit board with soldering and mounting holes, no visible text or symbols](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/9376d21f18f1ebcde7b65c8cf0136a3a812f80781358f4f8d25450d5b25f8591.jpg)

![Five silver hex-head bolts are lined up diagonally from upper-left to lower-right on a white background.](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/a3edf284ba7ec4516260587975b42363b3c235679a6c3c381c370b45ff6bca7a.jpg)

Step 5: If you are installing a heatsink with a fan, plug the fan connector into the carrier board.

The location of the FAN connector for the COM Express module depends on carrier board design.

![Close-up of hands installing a circuit board with a fan component and a CPU fan blade (no visible text or symbols)](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/07971811d2f2ab8d3c59d412266d18b62ca9bd8d7b8195319f3ff928300e4c83.jpg)
[🔗 Link to the original document](.cexpress-asl-aln-user-manual-50m-72220-1010-11-1/cexpress-asl-aln-user-manual-50m-72220-1010-11-1.pdf)