# cExpress-MTL

User’s Guide

intel

![Close-up of a green printed circuit board with visible components and no readable text or symbols.](.cexpress-mtl-50m-72221-1010-11/c5e0c80fe37875e6690e1a5577165bb53d6df8676ffd3de885e5419837b1e196.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-03-11</td><td>AL</td></tr><tr><td>1.1</td><td>Pinout and signal descriptions updated</td><td>2025-05-29</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard safety warning symbol featuring a yellow triangle with a thick black border. Centered inside the triangle is a large black exclamation mark.](.cexpress-mtl-50m-72221-1010-11/7c4b12d469a3902df1325d69b7da9ac46aaeaa8ef620527ca779cad01e88ef55.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a crossed-out wheeled bin symbol, indicating that the item is electronic waste and should not be thrown in general trash. Below the symbol is a solid black rectangle.](.cexpress-mtl-50m-72221-1010-11/4670cf9fa847628e66c2245a19e2444ffecb8f2df3e1b782a9a6f626947a95f8.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a red icon on a white background. It depicts a square shape with a folded bottom-right corner, resembling a piece of paper or document. Inside the shape are two horizontal red lines: a longer one near the top and a shorter one centered below it, representing text.](.cexpress-mtl-50m-72221-1010-11/aa119493208b34235a04c67c852f79669119966d444a57ab6e2d041ac37c1426.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow, rounded-triangular warning sign containing a white exclamation mark in its center, set against a white background with faint diagonal lines.](.cexpress-mtl-50m-72221-1010-11/565aaff4914ddc3c5a42791bfe06ac5eeed6a6fe34fd914db691caae15e18035.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![A red triangle with rounded corners featuring a white exclamation point in the center.](.cexpress-mtl-50m-72221-1010-11/9ff32e544cfdc2c7dffc3eb64587d3e628edd43d00e8c30591672f3cc97e8b2d.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History .. 2

Preface ..

List of Figures ...

1. Introduction ... .12
2. Specifications.. .13

2.1. Core System... ... 13
2.2. Video... ... 14

2.2.1. Display interface Support . .15
2.3. Audio .. ... 15
2.4. Expansion Buses.. ... 15
2.5. GbE Ethernet... ... 16
2.6. Multi I/O and Storage.. .. 16
2.7. Trusted Platform Module (TPM).. .. 18
2.8. NVMe SSD.. ... 18
2.9. SEMA Board Controller .. .. 19
2.10. Debug... ... 19
2.11. Power.... ... 19
2.12. Mechanical and Environmental .. . 20

3. Block Diagram ... .2
4. Pinout and Signal Descriptions .... .22

4.1. Pin Summary .. . 22
4.2 Signal Terminology Descriptions.. . 27
4.3 AB Connector Signal Descriptions .. . 28

4.3.1 Audio... .28
4.3.2 Analog VGA.. .29
4.3.3 LVDS or eDP.... ... 30
4.3.4 Gigabit Ethernet.... .33
4.3.5 SATA .. ... 34
4.3.6 PCI Express... ... 35

4.3.7 LPC Bus.. .37

4.3.8 USB.. .... 38

4.3.9 SPI Bus (BIOS only).. .39

4.3.10 Miscellaneous.. .40

4.3.11 SMBus .. .41

4.3.12 I 2C Bus... .41

4.3.13 General Purpose I/O (GPIO) .. .42

4.3.14 Serial Interface Signals.. .. 42

4.3.15 Power and System Management . .... 43

4.3.16 Power and Ground .. ... 44

4.4 CD Connector Signal Descriptions .. .. 45

4.4.1 USB 3.0 Extensions . .45

4.4.2 PCI Express... ... 46

4.4.3 DDI1 Port... .47

4.4.4 DDI2 Port... ... 50

4.4.5 DDI3 Port... .53

4.4.6 PCIe Graphics Port (PEG).. ... 56

4.4.7 Module Type Definition .. .59

4.4.8 Power and Ground .. ... 60

5. Additional Features .. ...61

5.1 Module Feature Locations. . 61

5.2 Debug Connector... . 62

5.3 Status LEDs... . 63

5.4 Exception Codes.. . 64

5.5 Fan Connector... . 65

5.6 BIOS Default Reset Button... . 66

6. System Resources ........ ..67

6.1. System Memory Map... . 67

6.2. I/O Map ... . 69

6.3. Interrupt Request (IRQ) Lines ... . 70

6.4. PCI Configuration Space Map.. . 72

6.5. PCI Interrupt Routing Map ... . 74

6.6. SMBus Address Table .. . 75

7. BIOS Setup... ...76

7.1. Menu Structure... . 76

. 77

7.2.1. BIOS Information.. .77

7.2.2. System Information.. .77
7.2.3. Board Information . ... 78
7.2.4. System Date and Time.. .78

7.3. Advanced .. . 79

7.3.1. CPU Configuration.. .. 79
7.3.2. Power & Performance Configuration.. .. 80
7.3.3. Graphic Configuration . ... 90
7.3.4. Platform Settings... .... 92
7.3.5. Power Management .. ... 95
7.3.6. System Management... .... 96
7.3.7. Thermal Management... ... 98
7.3.8. Watchdog Timer.... ...100
7.3.9. USB Configuration ... ....101
7.3.10. AMI Graphics Output Protocol Policy .. ...102
7.3.11. Super IO Configuration. ...102
7.3.12. Serial Console Redirection.. ...106
7.3.13. Miscellaneous.... ...107
7.3.14. Network Stack Configuration . ...108
7.3.15. NVMe Configuration.. ...109
7.3.16. Trusted Computing.... ...109

7.4. Chipset .. ...110

7.4.1. Chipset > System Agent (SA) Configuration.. ...110
7.4.2. Chipset > PCH-IO Configuration... ...117

7.5. Security .... ..139

...139

7.6. Boot .... ....140

7.6.1. Boot Configuration.. ...140

7.7. Save & Exit.... ....141

7.7.1. Save Options... ...141
7.7.2. Default Options.... ...142

8. BIOS Checkpoints, Beep Codes .... . 143

8.1. Status Code Ranges . ..144
8.2. Standard Status Codes.. ....145

8.2.1. SEC Phase.. ...145
8.2.2. SEC Beep Codes... ...146
8.2.3. PEI Phase... ...146
8.2.4. PEI Beep Codes .. ...150
8.2.5. DXE Status Codes... ...150

8.2.6. DXE Beep Codes.... ...154
8.2.7. ACPI/ASL Checkpoint ... ...154

8.3. OEM-Reserved Checkpoint Ranges.. ..155

# 9. Software Support ... . 156

9.1. Windows... ..156
9.2. Ubuntu 24.04. LTS .. ..156
9.3. Yocto Linux 64-bit .. ..156
9.4. SEMA API .. ..156

# 10.Mechanical and Thermal... . 157

10.1. Module Dimensions ..... ..157
10.2. Height of Processor and Static Compressive Load .. ..158
10.3. Thermal Solutions .. ..159

10.3.1. Heatspreader: HTS... ...159
10.3.2. Heatsink: THS . ...160
10.3.3. Heatsink with Fan: THSF... ...161
10.3.4. Heatsink High Profile: THSH... ...162

10.4. Board to Board Connectors.. ...163

10.5. Mounting Method.. ..164
10.6. Standoff Types... ....165
10.7. Installation ... ....166

# List of Figures

Figure 1 – Module functional block diagram . .21

Figure 2 – Module rear side row and pin numbering....... ...22

Figure 3 – Module feature locations (top side) .. ...61

Figure 4 – cExpress-MTL and debug module... ...62

Figure 5 – Module mechanical dimensions ..... ... 157

Figure 6 – Heatspreader: HTS...... ..159

Figure 7 – Heatsink: THS.... ... 160

Figure 8 – Heatsink with fan: THSF.... .161

Figure 9 – Heatsink high profile: THSH.. .162

# 1. Introduction

The cExpress-MTL is a COM Express® COM.0 R3.1 Compact Size Type 6 module based on the intel® new generation edge/IoT platform on new Intel 4 process provides industry leading performance/watt. The new-generation CoreTM Ultra processors (formerly “Meter Lake H/U”) supporting up to 14 cores (Ultra 7) at maximum 28W TDP. Performance core and efficiency core improve multi-tasking ability include of two low power island E-core to reduce CPU power consumption. Up to 2x DDR5 SO-DIMMs supporting a maximum of 96GB memory capacity at up to 5600 MT/s. New integrated ARC graphics up to 128 EU that enhance close to two-time performance than previous generation platform. All CPU SKU build-in NPU to strengthen AI accelerator. Following PICMG R3.1 specifications all-around PCIe Gen4 support and integrated 2.5G Ethernet connectivity makes it suit for highperformance, low-power-consumption, powerful image processing capability and fast-response-required applications, including, but not limited to, video storage analytics, medical image presentation and analysis, intelligent surveillance, and industrial automation and control.

Meteor Lake has two kinds of cTDP CPU SKU (15W and 28W) can be choose. Low CPU power consumption means more suitable for use on handheld devices, such as handheld ultrasound devices. The module builds in PCIe gen 4 NVMe SSD in compact size dimension and new Integrated NPU for dedicated AI acceleration that reduces the system cost but improve the system AI processing ability. This design provides a better option for customer who have a strong need to reduce the size and cost of their product.

Input/output features include up to 24 PCIe Gen4 lanes, a single onboard 2.5-Gigabit Ethernet port, 4x USB 3.2/2.0 ports up to 10Gb/s, 2x SATA 6 Gb/s ports, independent four displays that resolution up to 8K. Additional General Purpose SPI (GP\_SPI), two MIPI-CSI connectors to support cameras and onboard storage up to 1T capacity etc. option function. Support for SMBus and I2C is also provided. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as a remote console, hardware monitor, and watchdog timer.

# 2. Specifications

# 2.1. Core System

# CPU

Intel® CoreTM Ultra Processors (formerly “Meteor Lake H/U”)

• Intel® CoreTM Ultra 7 155H 4.8/1.4GHz, 28W with 20-65W cTDP (16C/22T include 2 NPU)
• Intel® CoreTM Ultra 5 135H 4.6/1.7GHz, 28W with 20-65W cTDP (14C/18T include 2 NPU)
• Intel® CoreTM Ultra 5 125H 4.5/1.2GHz, 28W with 20-65W cTDP (14C/18T include 2 NPU)
• Intel® CoreTM Ultra 5 135U 4.4/1.6GHz, 15W with 12-28W cTDP (12C/14T include 2 NPU)
• Intel® CoreTM Ultra 5 125U 4.3/1.3GHz, 15W with 12-28W cTDP (12C/14T include 2 NPU)

# Memory

Up to 96GB DDR5, dual memory channel in 2x SODIMM sockets, maximum 48GB per socket, non-ECC

Up to 5600 MT/s memory speed

1x SODIMM sockets on top side and 1x SODIMM sockets on bottom side

# Cache (L3)

24MB: 155H

18MB: 135H, 125H

12MB: 135U, 125U

# Embedded BIOS

AMI Aptio V UEFI with CMOS backup in 32 MB SPI BIOS

# 2.2. Video

# GPU

Intel® Xe Graphics architecture with up to 128 execution units

# Feature Support

# Display Interface

4 independent and simultaneous combinations of DisplayPort/HDMI/LVDS/eDP/VGA and display alternative mode through USB4/Thunderbolt4 graphics outputs (4x 4K @60Hz, up to 8K@60Hz). (eDP optional in place of LVDS, VGA optional in place of DDI 3)

Playback of high-definition content including Blu-ray Disc and Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D)

# Graphics acceleration

DirectX 12 Video Acceleration (DXVA)/Open GL 4.6/Vulkan 1.2 and one VPL support for accelerated video processing

# Video Decode

8K60 12b 4:2:0 HEVC/VP9/SCC

8K30 10b 4:2:0 AV1

5K60 10b 4:4:4 HEVC/VP9/SCC

4K60 8b 4:2:0 AVC

# Video Encode

8K30 or 5K60 8b/10b 4:2:0 HEVC/VP9/SCC

4K60 10b 4:4:4 HEVC/VP9/SCC

4K60 8b 4:2:0 AVC

![The image displays a red icon resembling a document or memo pad. It features a red outline with rounded corners and a folded bottom-right corner. Inside the outline, two horizontal red lines are centered vertically, representing text.](.cexpress-mtl-50m-72221-1010-11/5c940b2a593ca4e61922466094d03d9a8b8b14262b663dbfbee47fca6bce9579.jpg)

Note: Availability of features is dependent on the operating system used (Windows 10 64-bit, Linux 64-bit).

# 2.2.1. Display interface Support

DDI x3: Digital Display Ports (DDI) support DisplayPort 1.4a (via TBT4 w/Hayden Bridge can upgrade to DP 2.1), HDMI 2.1 or DVI.

LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, supports DE mode and Hsync/Vsync mode.

Max. Resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported.

VGA: VGA BOM option support in place of DDI 3; max. resolution 1920x1200@60Hz

# 2.3. Audio

Intel® HD Audio integrated

Located on carrier Express-BASE6 or Express-BASE6 R3.1 (ALC886 standard support)

# 2.4. Expansion Buses

8 PEG Express Gen4: PEG Lane 0-7 (based on CPU SKU, 28W CPU SKU support)

PCIe reference clock uses PCIE\_CK\_REF6.

4 PEG Express Gen4: Two PEG Express Gen 4 at PEG Lane 8-11 and PEG Lane 12-15

4 PCI Express Gen4: Lanes 0-3 (configurable to 1 x4, 2 x2 and 4 x1)

2 PCI Express Gen4: Lane 4-5 (configurable to 1 x2 and 2 x1)

![The image displays a red icon resembling a document or file. It features a square outline with the bottom-right corner folded over. Inside the white interior, there are two horizontal red lines centered vertically, representing text.](.cexpress-mtl-50m-72221-1010-11/688cc73ad3a7dc98e19646cc17efa9db4f3adfbc34671853d1f585e50c539d55.jpg)

Note: 1. PCIe Gen4 support also depends on carrier board design.

2. PCIe lane 6-7 can be adjust at bios setup manual and combines PCIe Lane 4-5 can be configured 1 x4, 2 x2 and 4 x1 (sacrifice SATA 0-1)
3. PEG 0-7, 8-11, and 12-15 are recommended to be used for discrete graphics and storage purposes only.

Other: SMBus (system), I2 C (user), LPC bus (via eSPI to LPC bridge IC).

I 2 C from CPU is supported by BOM option and project basis

SMBus from EC (embedded controller) is supported by BOM option and project basis

Additional GP\_SPI (general purpose SPI by project basis)

# 2.5. GbE Ethernet

Intel® Ethernet Controller I226 Series (V, IT or LM version)

Up to 2.5GbE, 1000/100/10 Mbit/s connections

IT version supports TSN feature on Linux OS, GbE0\_SDP available if TSN support enabled (TBD)

# 2.6. Multi I/O and Storage

# USB

• USB4 x2: Build option (HW and BIOS) supported by project basis in place of DDI channels. Maximum 2x USB4 by using DDI 1 and DDI 2 channels. USB4 support also requires re-timer and PD on carrier.

![The image displays a red icon resembling a document or memo. It features a square shape with a folded bottom-right corner. Inside the red outline, there are two horizontal lines centered vertically, representing lines of text.](.cexpress-mtl-50m-72221-1010-11/86bf0cbd5cccddfe4c6a7a814d27421c4b84490eccced4c8e05815301158582a.jpg)

Note: Capable of TBT4. Please contact your local ADLINK representative for details.

• USB 3.2 Gen2 x4: USB port 0, 1, 2, 3 support
• USB 2.0 x4: USB port 4, 5, 6, 7 support
SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling
Up to 10Gb/s and also depends on carrier board design
USB\_OC pins share the same source, from SoC.

![The image displays a red icon of a document or page of paper. It features a thick red outline with the bottom-right corner folded upwards. Inside the red border, there are two horizontal red lines centered in the middle, resembling lines of text. The background is white.](.cexpress-mtl-50m-72221-1010-11/a6c1954d06ac327e37ffe6687082f94bbbfc9ece883709e31178886306fd609b.jpg)

Note: 1. Carrier board must be designed for Gen2 operation.

2. USB 0,1,2,3 are backward compatible with USB 2.0/1.1.

# SATA

SATA x2: Speed up to 6Gb/s (SATA 0,1)

![The image shows a red icon depicting a document or note. It has a square shape with rounded corners and a folded bottom-right corner (a dog-ear). Inside the white area, there are two horizontal red lines centered vertically, representing text.](.cexpress-mtl-50m-72221-1010-11/0fa129401eafa21c37cb92fce3cfb4de3c9a2ab7f4b649841081ebcf1553022d.jpg)

Note: 1. SATA [0:1] can be changed to PCIe[6:7] by bios setup menu.

# UART

2x UART interfaces SER0 and SER1 RX/TX on module

Console Redirection COM 1 or COM 2 selectable in BIOS

SER0, SER1 from CPU UART are supported by BOM option and project basis

Up to 4 serial ports supported by standard BIOS, including Super I/O on carrier board

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via embedded controller</td><td>4</td><td>0x3F8</td><td>Yes</td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via embedded controller</td><td>3</td><td>0x2F8</td><td>Yes</td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>5</td><td>0x240</td><td>Yes</td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>7</td><td>0x248</td><td>Yes</td></tr></table>

# GPIO or SD

4 GPO and 4 GPI (GPI with interrupt, TBC)

GPI and GPO from CPU GPIO are supported by BOM option and project basis

# MIPI-CSI

MIPI-CSI x1: 4 Lanes MIPI-CSI interface and supports camera video capture up to 750MP/s

# 2.7. Trusted Platform Module (TPM)

Chipset: Infineon solution

Type: TPM 2.0 (SPI bus-based)

# 2.8. NVMe SSD

NVMe SSD x1: Support PCIe Gen 4 x4 and the max capacity up to 1TB

# 2.9. SEMA Board Controller

Supports: Voltage/current monitoring, power sequence debug support, AT/ATX mode control, logistics and forensic information, flat panel control, general purpose I2C, failsafe BIOS (dual BIOS, opt. support), watchdog timer and fan control

# 2.10. Debug

30-pin flat cable connector for use with DB-30 x86 debug module

Supports embedded controller access, SPI BIOS flashing, internal power rail test points, debug LEDs

# 2.11. Power

Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)

Standard Voltage Input: AT: 12V±5% or ATX: 12V±5% / 5Vsb ±5%

Wide Voltage Input: AT: 8.5-20V or ATX: 8.5-20V / 5Vsb ±5% (only for standard operating temperature)

Power Management: ACPI 5.0 compliant

Power States: C0-C6, S0, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5). ECO Mode support for deep S5 for 5Vsb power saving

![The image displays a red icon on a white background, depicting a document or piece of paper with a folded top-right corner. Inside the red outline, there are two horizontal red lines centered, resembling text.](.cexpress-mtl-50m-72221-1010-11/5d122a6920826b86d92abfbcb5b4e86992505fc704b61f2671082c0892459eaf.jpg)

Note: 1. S3 support by AMI workaround. Intel will official release the S3 POR at 2025 Q1

# Power Consumption

Please contact our ADLINK representative for the document “COM Express Module Power Consumption.”

# 2.12. Mechanical and Environmental

# Form Factor and specification

PICMG COM Express Rev 3.1 (COM.0 R3.1), Type 6, Compact size 95 x 95 mm

# Operating Temperature

Standard 0°C to 60°C Storage: -20°C to 80°C

Extreme Rugged -40°C to 85°C Storage: -40°C to 85°C

# Humidity

5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27

MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D

# HALT tested

Thermal Stress, Vibration Stress, Thermal Shock and Combined Test

# 3. Block Diagram

![The diagram is a block diagram centered around the **Intel Core Ultra Processor (Meteor Lake-H/U)**.\n\n**Memory Connections (Top Left):**\n*   Two blocks labeled **DDR5 SODIMM Max. 5600 MT/s 8~48GB, non-ECC** connect to the processor via **DDR5 CHA** and **DDR5 CHB**.\n\n**Display and Video Connections (Top Left / Left / Right):**\n*   **eDP/LVDS** connects to **eDP to LVDS**, which connects to **DDI A**.\n*   **eDP x4** (dashed line) connects to **DDI A**.\n*   **VGA** connects to **DP to VGA** (Build option), which connects to **DDI B**.\n*   **DDI3** connects directly to **DDI3** on the far right.\n*   **TCP0** connects to **DDI/USB4/TBT4 Port 1**.\n*   **TCP1** connects to **DDI/USB4/TBT4 Port 2**.\n\n**USB, Network, and PCIe Connections (Left / Middle / Right):**\n*   **USB 2.0 Lane 0-7** connects to **USB2 0-7**.\n*   **Max 2.5 GbE** connects to **LAN i226**, which connects to **HSIO 10**.\n*   **HSIO 0** connects to **USB 3.2 Lane 0**.\n*   **HSIO 1** connects to **USB 3.2 Lane 1**.\n*   **TCP2** connects to **USB 3.2 Lane 2**.\n*   **TCP3** connects to **USB 3.2 Lane 3**.\n*   **PCIe Lane 4** (dashed) connects to **HSIO 5**.\n*   **HSIO 5** (dashed) connects to **PCIe Lane 7** and **PCIe Lane 6**.\n*   **GEN4 x8** connects to **PEG 0-7**.\n*   **PCIe Lane 0-3** (dashed) connects to **HSIO 6-9**.\n*   **HSIO 6-9** connects to **Gen4 x4**, which connects to **PEG 8-11**.\n*   **HSIO 6-9** connects to **Gen4 x4**, which connects to **PEG 12-15**.\n*   **SATA 0** connects to **MUX**, which connects to **HSIO 2**.\n*   **SATA 1** connects to **MUX**, which connects to **HSIO 3**.\n*   **PCIe Lane 5** connects to **HSIO 4**.\n*   **HSIO 4** connects to **MIPI CSI-E**, which connects to **MIPI Connector** (Build option).\n*   **HSIO 4** connects to **PCIe Gen4 NVMe SSD** (Build option).\n\n**GPIO, UART, SPI, and LPC Connections (Left / Bottom Center / Bottom Right):**\n*   **SMBUS** connects to **1X SMBUS**.\n*   **I2C** connects to **1X I2C**.\n*   **8 GPIO** connects to **GPIO 2X HSUART**.\n*   **GSP I** connects to **GSP I**.\n*   **SPI** connects to **SPI**.\n*   **2X UART** connects to **2X HSUART**.\n*   **LPC** connects to **Embedded Controller**.\n*   **eSPI** connects to **eSPI to LPC**, which connects to **Embedded Controller**.\n*   **1X SMBUS**, **1X I2C**, **GPIO 2X HSUART**, **GSP I**, and **SPI** (from the processor) connect to the **Embedded Controller**.\n*   **GSP I** (far left) connects to **Embedded Controller**.\n*   **SPI** (far left) connects to **Embedded Controller**.\n*   **2X UART** (far left) connects to **Embedded Controller**.\n\n**Peripherals and Storage (Bottom Right):**\n*   **SPI** (from processor) connects to **TPM 2.0** and **BIOS Flash**.\n*   **Embedded Controller** connects to **LM73**.\n*   **Embedded Controller** connects to **FAN connector** (Build option).](.cexpress-mtl-50m-72221-1010-11/b1f63d5312573bda88b88bf3394f54e386ef24d628c0c15c59704eff5e8b05ce.jpg)

Figure 1 – Module functional block diagram

# 4 Pinout and Signal Descriptions

# 4.1. Pin Summary

The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 6 in the PICMG COM.0 R3.1 specification. Signals described in the specification but not supported on the cExpress-MTL are marked with STRIKETHROUGH.

![D1\nCD\nC1\nB1\nAB\nA110\nA1](.cexpress-mtl-50m-72221-1010-11/f88afeab699596bbe05ec27846dbc2c4ca03f20df326c2655282b65733d000dd.jpg)

Figure 2 – Module rear side row and pin numbering

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>GND (FIXED)</td><td></td><td>B1</td><td>GND (FIXED)</td><td></td><td>C1</td><td>GND FIXED)</td><td></td><td>D1</td><td>GND FIXED)</td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td></td><td>B2</td><td>GBE0_ACT#</td><td></td><td>C2</td><td>GND</td><td></td><td>D2</td><td>GND</td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td></td><td>B3</td><td>LPC_FRAME#/ESPI_CS0# $^{1}$ </td><td></td><td>C3</td><td>USB_SSRX0-</td><td></td><td>D3</td><td>USB_SSTX0-</td></tr><tr><td>A4</td><td>GBE0_LINK_MID#</td><td></td><td>B4</td><td>LPC_AD0/ESPI_IO_0 $^{1}$ </td><td></td><td>C4</td><td>USB_SSRX0+</td><td></td><td>D4</td><td>USB_SSTX0+</td></tr><tr><td>A5</td><td>GBE0_LINK_MAX#</td><td></td><td>B5</td><td>LPC_AD1/ESPI_IO_1 $^{1}$ </td><td></td><td>C5</td><td>GND</td><td></td><td>D5</td><td>GND</td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td></td><td>B6</td><td>LPC_AD2/ESPI_IO_2 $^{1}$ </td><td></td><td>C6</td><td>USB_SSRX1-</td><td></td><td>D6</td><td>USB_SSTX1-</td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td></td><td>B7</td><td>LPC_AD3/ESPI_IO_3 $^{1}$ </td><td></td><td>C7</td><td>USB_SSRX1+</td><td></td><td>D7</td><td>USB_SSTX1+</td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td></td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td><td></td><td>C8</td><td>GND</td><td></td><td>D8</td><td>GND</td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td></td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td><td></td><td>C9</td><td>USB_SSRX2-</td><td></td><td>D9</td><td>USB_SSTX2-</td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td></td><td>B10</td><td>LPC_CLK/ESPI_CK $^{1}$ </td><td></td><td>C10</td><td>USB_SSRX2+</td><td></td><td>D10</td><td>USB_SSTX2+</td></tr><tr><td>A11</td><td>GND (FIXED)</td><td></td><td>B11</td><td>GND (FIXED)</td><td></td><td>C11</td><td>GND (FIXED)</td><td></td><td>D11</td><td>GND (FIXED)</td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td></td><td>B12</td><td>PWRBTN#</td><td></td><td>C12</td><td>USB_SSRX3-</td><td></td><td>D12</td><td>USB_SSTX3-</td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td></td><td>B13</td><td>SMB_CK</td><td></td><td>C13</td><td>USB_SSRX3+</td><td></td><td>D13</td><td>USB_SSTX3+</td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td></td><td>B14</td><td>SMB_DAT</td><td></td><td>C14</td><td>GND</td><td></td><td>D14</td><td>GND</td></tr><tr><td>A15</td><td>SUS_S3#</td><td></td><td>B15</td><td>SMB_ALERT#</td><td></td><td>C15</td><td>USB4_1_LSTX $^{1}$ </td><td></td><td>D15</td><td>DDI1_CTRLCLK_AUX+/USB4_1_AUX+ $^{1}$ </td></tr><tr><td>A16</td><td>SATA0_TX+</td><td></td><td>B16</td><td>SATA1_TX+</td><td></td><td>C16</td><td>USB4_1_LSRX $^{1}$ </td><td></td><td>D16</td><td>DDI1_CTRLDATA_AUX-/USB4_1_AUX- $^{1}$ </td></tr><tr><td>A17</td><td>SATA0_TX-</td><td></td><td>B17</td><td>SATA1_TX-</td><td></td><td>C17</td><td>USB4_RT_ENA $^{1}$ </td><td></td><td>D17</td><td>USB4_PD_I2C_ALERT# $^{1}$ </td></tr><tr><td>A18</td><td>SUS_S4#</td><td></td><td>B18</td><td>SUS_STAT#/ESPI_RESET# $^{1}$ </td><td></td><td>C18</td><td>GND</td><td></td><td>D18</td><td>PMCALERT# $^{1}$ </td></tr><tr><td>A19</td><td>SATA0_RX+</td><td></td><td>B19</td><td>SATA1_RX+</td><td></td><td>C19</td><td>PCIE_RX6+ $^{1}$ </td><td></td><td>D19</td><td>PCIE_TX6+</td></tr><tr><td>A20</td><td>SATA0_RX-</td><td></td><td>B20</td><td>SATA1_RX-</td><td></td><td>C20</td><td>PCIE_RX6- $^{1}$ </td><td></td><td>D20</td><td>PCIE_TX6-</td></tr><tr><td>A21</td><td>GND (FIXED)</td><td></td><td>B21</td><td>GND (FIXED)</td><td></td><td>C21</td><td>GND (FIXED)</td><td></td><td>D21</td><td>GND (FIXED)</td></tr><tr><td>A22</td><td>SATA2_TX+</td><td></td><td>B22</td><td>SATA3_TX+</td><td></td><td>C22</td><td>PCIE_RX7+ $^{1}$ </td><td></td><td>D22</td><td>PCIE_TX7+</td></tr><tr><td>A23</td><td>SATA2_TX-</td><td></td><td>B23</td><td>SATA3_TX-</td><td></td><td>C23</td><td>PCIE_RX7- $^{1}$ </td><td></td><td>D23</td><td>PCIE_TX7-</td></tr><tr><td>A24</td><td>SUS_S5#</td><td></td><td>B24</td><td>PWR_OK</td><td></td><td>C24</td><td>DDI1_HPD</td><td></td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>SATA2_RX+</td><td></td><td>B25</td><td>SATA3_RX+</td><td></td><td>C25</td><td>SML0_CLK $^{1}$ </td><td></td><td>D25</td><td>GND</td></tr><tr><td>A26</td><td>SATA2_RX-</td><td></td><td>B26</td><td>SATA3_RX-</td><td></td><td>C26</td><td>SML0_DAT $^{1}$ </td><td></td><td>D26</td><td>DDI1_PAIR0+/USB4_1_SSTX0+ $^{1}$ </td></tr><tr><td>A27</td><td>BATLOW#</td><td></td><td>B27</td><td>WDT</td><td></td><td>C27</td><td>SML1_CLK $^{1}$ </td><td></td><td>D27</td><td>DDI1_PAIR0-/USB4_1_SSTX0- $^{1}$ </td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td></td><td>B28</td><td>HDA_SDIN2/SNDW0_CLK $^{2}$ </td><td></td><td>C28</td><td>SML1_DAT $^{1}$ </td><td></td><td>D28</td><td>GND</td></tr><tr><td>A29</td><td>HDA_SYNC</td><td></td><td>B29</td><td>HDA_SDIN1/SNDW0_DAT $^{2}$ </td><td></td><td>C29</td><td>USB4_PD_I2C_CLK $^{1}$ </td><td></td><td>D29</td><td>DDI1_PAIR1+/USB4_1_SSRX0+ $^{1}$ </td></tr><tr><td>A30</td><td>HDA_RST#</td><td></td><td>B30</td><td>HDA_SDINO</td><td></td><td>C30</td><td>USB4_PD_I2C_DAT $^{1}$ </td><td></td><td>D30</td><td>DDI1_PAIR1-/USB4_1_SSRX0- $^{1}$ </td></tr><tr><td>A31</td><td>GND (FIXED)</td><td></td><td>B31</td><td>GND (FIXED)</td><td></td><td>C31</td><td>GND (FIXED)</td><td></td><td>D31</td><td>GND (FIXED)</td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td></td><td>B32</td><td>SPKR</td><td></td><td>C32</td><td>DDI2_CTRLCLK_AUX+/USB4_2_AUX+1</td><td></td><td>D32</td><td>DDI1_PAIR2+/USB4_1_SSTX1+1</td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td></td><td>B33</td><td>I2C_CK</td><td></td><td>C33</td><td>DDI2_CTRLDATA_AUX-/USB4_2_AUX-1</td><td></td><td>D33</td><td>DDI1_PAIR2-/USB4_1_SSTX1-1</td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS1</td><td></td><td>B34</td><td>I2C_DAT</td><td></td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td></td><td>D34</td><td>DDI1_DDC_AUX_SEL</td></tr><tr><td>A35</td><td>THRMTRIP#</td><td></td><td>B35</td><td>THRM#</td><td></td><td>C35</td><td>USB4_2_LSTX1</td><td></td><td>D35</td><td>USB4_2_LSRX1</td></tr><tr><td>A36</td><td>USB6-</td><td></td><td>B36</td><td>USB7-</td><td></td><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td></td><td>D36</td><td>DDI1_PAIR3+/USB4_1_SSRX1+1</td></tr><tr><td>A37</td><td>USB6+</td><td></td><td>B37</td><td>USB7+</td><td></td><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td></td><td>D37</td><td>DDI1_PAIR3-/USB4_1_SSRX1-1</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td></td><td>B38</td><td>USB_4_5_OC#</td><td></td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td></td><td>D38</td><td>GND</td></tr><tr><td>A39</td><td>USB4-</td><td></td><td>B39</td><td>USB5-</td><td></td><td>C39</td><td>DDI3_PAIR0+</td><td></td><td>D39</td><td>DDI2_PAIR0+/USB4_2_SSTX0+1</td></tr><tr><td>A40</td><td>USB4+</td><td></td><td>B40</td><td>USB5+</td><td></td><td>C40</td><td>DDI3_PAIR0-</td><td></td><td>D40</td><td>DDI2_PAIR0-/USB4_2_SSTX0-1</td></tr><tr><td>A41</td><td>GND (FIXED)</td><td></td><td>B41</td><td>GND (FIXED)</td><td></td><td>C41</td><td>GND (FIXED)</td><td></td><td>D41</td><td>GND (FIXED)</td></tr><tr><td>A42</td><td>USB2-</td><td></td><td>B42</td><td>USB3-</td><td></td><td>C42</td><td>DDI3_PAIR1+</td><td></td><td>D42</td><td>DDI2_PAIR1+/USB4_2_SSRX0+1</td></tr><tr><td>A43</td><td>USB2+</td><td></td><td>B43</td><td>USB3+</td><td></td><td>C43</td><td>DDI3_PAIR1-</td><td></td><td>D43</td><td>DDI2_PAIR1-/USB4_2_SSRX0-1</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td></td><td>B44</td><td>USB_0_1_OC#</td><td></td><td>C44</td><td>DDI3_HPD</td><td></td><td>D44</td><td>DDI2_HPD</td></tr><tr><td>A45</td><td>USB0-</td><td></td><td>B45</td><td>USB1-</td><td></td><td>C45</td><td>GP_SPI_CS#2</td><td></td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>USB0+</td><td></td><td>B46</td><td>USB1+</td><td></td><td>C46</td><td>DDI3_PAIR2+</td><td></td><td>D46</td><td>DDI2_PAIR2+/USB4_2_SSTX1+1</td></tr><tr><td>A47</td><td>VCC_RTC</td><td></td><td>B47</td><td>ESPI_EN#1</td><td></td><td>C47</td><td>DDI3_PAIR2-</td><td></td><td>D47</td><td>DDI2_PAIR2-/USB4_2_SSTX1-1</td></tr><tr><td>A48</td><td>PSMRST_OUT#</td><td></td><td>B48</td><td>USB0_HOST_PRSNT</td><td></td><td>C48</td><td>RSVD</td><td></td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GBE0_SDP1</td><td></td><td>B49</td><td>SYS_RESET#</td><td></td><td>C49</td><td>DDI3_PAIR3+</td><td></td><td>D49</td><td>DDI2_PAIR3+/USB4_2_SSRX1+1</td></tr><tr><td>A50</td><td>LPC_SERIRQ/ESPI_CS1#1</td><td></td><td>B50</td><td>CB_RESET#</td><td></td><td>C50</td><td>DDI3_PAIR3-</td><td></td><td>D50</td><td>DDI2_PAIR3-/USB4_2_SSRX1-1</td></tr><tr><td>A51</td><td>GND (FIXED)</td><td></td><td>B51</td><td>GND (FIXED)</td><td></td><td>C51</td><td>GND (FIXED)</td><td></td><td>D51</td><td>GND (FIXED)</td></tr><tr><td>A52</td><td>PCIE_TX5+1</td><td></td><td>B52</td><td>PCIE_RX5+1</td><td></td><td>C52</td><td>PEG_RX0+</td><td></td><td>D52</td><td>PEG_TX0+</td></tr><tr><td>A53</td><td>PCIE_TX5-1</td><td></td><td>B53</td><td>PCIE_RX5-1</td><td></td><td>C53</td><td>PEG_RX0-</td><td></td><td>D53</td><td>PEG_TX0-</td></tr><tr><td>A54</td><td>GPIO</td><td></td><td>B54</td><td>GPO1</td><td></td><td>C54</td><td>TYPE0#</td><td></td><td>D54</td><td>PEG_LANE_RV#</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td></td><td>B55</td><td>PCIE_RX4+</td><td></td><td>C55</td><td>PEG_RX1+</td><td></td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td></td><td>B56</td><td>PCIE_RX4-</td><td></td><td>C56</td><td>PEG_RX1-</td><td></td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td></td><td>B57</td><td>GPO2</td><td></td><td>C57</td><td>TYPE1#</td><td></td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td></td><td>B58</td><td>PCIE_RX3+</td><td></td><td>C58</td><td>PEG_RX2+</td><td></td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td></td><td>B59</td><td>PCIE_RX3-</td><td></td><td>C59</td><td>PEG_RX2-</td><td></td><td>D59</td><td>PEG_TX2-</td></tr><tr><td>A60</td><td>GND (FIXED)</td><td></td><td>B60</td><td>GND (FIXED)</td><td></td><td>C60</td><td>GND (FIXED)</td><td></td><td>D60</td><td>GND (FIXED)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td></td><td>B61</td><td>PCIE_RX2+</td><td></td><td>C61</td><td>PEG_RX3+</td><td></td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td></td><td>B62</td><td>PCIE_RX2-</td><td></td><td>C62</td><td>PEG_RX3-</td><td></td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1</td><td></td><td>B63</td><td>GPO3</td><td></td><td>C63</td><td>GND</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td></td><td>B64</td><td>PCIE_RX1+</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>GND</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td></td><td>B65</td><td>PCIE_RX1-</td><td></td><td>C65</td><td>PEG_RX4+</td><td></td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td></td><td>B66</td><td>WAKE0#</td><td></td><td>C66</td><td>PEG_RX4-</td><td></td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2</td><td></td><td>B67</td><td>WAKE1#</td><td></td><td>C67</td><td>RAPID_SHUTDOWN</td><td></td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td></td><td>B68</td><td>PCIE_RX0+</td><td></td><td>C68</td><td>PEG_RX5+</td><td></td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td></td><td>B69</td><td>PCIE_RX0-</td><td></td><td>C69</td><td>PEG_RX5-</td><td></td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND (FIXED)</td><td></td><td>B70</td><td>GND (FIXED)</td><td></td><td>C70</td><td>GND (FIXED)</td><td></td><td>D70</td><td>GND (FIXED)</td></tr><tr><td>A71</td><td>LVDS_A0+ / eDP_TX2+1</td><td></td><td>B71</td><td>LVDS_B0+</td><td></td><td>C71</td><td>PEG_RX6+</td><td></td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0- / eDP_TX2-1</td><td></td><td>B72</td><td>LVDS_B0-</td><td></td><td>C72</td><td>PEG_RX6-</td><td></td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+ / eDP_TX1+1</td><td></td><td>B73</td><td>LVDS_B1+</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>LVDS_A1- / eDP_TX1-1</td><td></td><td>B74</td><td>LVDS_B1-</td><td></td><td>C74</td><td>PEG_RX7+</td><td></td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+ / eDP_TX0+1</td><td></td><td>B75</td><td>LVDS_B2+</td><td></td><td>C75</td><td>PEG_RX7-</td><td></td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2- / eDP_TX0-1</td><td></td><td>B76</td><td>LVDS_B2-</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN / eDP_VDD_EN1</td><td></td><td>B77</td><td>LVDS_B3+</td><td></td><td>C77</td><td>GND</td><td></td><td>D77</td><td>GND</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td></td><td>B78</td><td>LVDS_B3-</td><td></td><td>C78</td><td>PEG_RX8+</td><td></td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td></td><td>B79</td><td>LVDS_BKLT_EN</td><td></td><td>C79</td><td>PEG_RX8-</td><td></td><td>D79</td><td>PEG_TX8-</td></tr><tr><td>A80</td><td>GND (FIXED)</td><td></td><td>B80</td><td>GND (FIXED)</td><td></td><td>C80</td><td>GND (FIXED)</td><td></td><td>D80</td><td>GND (FIXED)</td></tr><tr><td>A81</td><td>LVDS_A_CK+ / eDP_TX3+1</td><td></td><td>B81</td><td>LVDS_B_CK+</td><td></td><td>C81</td><td>PEG_RX9+</td><td></td><td>D81</td><td>PEG_TX9+</td></tr><tr><td>A82</td><td>LVDS_A_CK- / eDP_TX3-1</td><td></td><td>B82</td><td>LVDS_B_CK-</td><td></td><td>C82</td><td>PEG_RX9-</td><td></td><td>D82</td><td>PEG_TX9-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK / eDP_AUX+1</td><td></td><td>B83</td><td>LVDS_BKLT_CTRL / eDP_BKLT_CTRL1</td><td></td><td>C83</td><td>GND</td><td></td><td>D83</td><td>GND</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT / eDP_AUX-1</td><td></td><td>B84</td><td>VCC_5V_SBY</td><td></td><td>C84</td><td>GND</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3</td><td></td><td>B85</td><td>VCC_5V_SBY</td><td></td><td>C85</td><td>PEG_RX10+</td><td></td><td>D85</td><td>PEG_TX10+</td></tr><tr><td>A86</td><td>GP_SPI_MOSI2</td><td></td><td>B86</td><td>VCC_5V_SBY</td><td></td><td>C86</td><td>PEG_RX10-</td><td></td><td>D86</td><td>PEG_TX10-</td></tr><tr><td>A87</td><td>eDP_HPD</td><td></td><td>B87</td><td>VCC_5V_SBY</td><td></td><td>C87</td><td>GND</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE_CK_REF+</td><td></td><td>B88</td><td>BIOS_DIS1#</td><td></td><td>C88</td><td>PEG_RX11+</td><td></td><td>D88</td><td>PEG_TX11+</td></tr><tr><td>A89</td><td>PCIE_CK_REF-</td><td></td><td>B89</td><td>VGA_RED1</td><td></td><td>C89</td><td>PEG_RX11-</td><td></td><td>D89</td><td>PEG_TX11-</td></tr><tr><td>A90</td><td>GND (FIXED)</td><td></td><td>B90</td><td>GND (FIXED)</td><td></td><td>C90</td><td>GND (FIXED)</td><td></td><td>D90</td><td>GND (FIXED)</td></tr><tr><td>A91</td><td>SPI_POWER</td><td></td><td>B91</td><td>VGA_GRN1</td><td></td><td>C91</td><td>PEG_RX12+</td><td></td><td>D91</td><td>PEG_TX12+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td></td><td>B92</td><td>VGA_BLU1</td><td></td><td>C92</td><td>PEG_RX12-</td><td></td><td>D92</td><td>PEG_TX12-</td></tr><tr><td>A93</td><td>GPO0</td><td></td><td>B93</td><td>VGA_HSYNC $^1$ </td><td></td><td>C93</td><td>GND</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td></td><td>B94</td><td>VGA_VSYNC $^1$ </td><td></td><td>C94</td><td>PEG_RX13+</td><td></td><td>D94</td><td>PEG_TX13+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td></td><td>B95</td><td>VGA_I2C_CK $^1$ </td><td></td><td>C95</td><td>PEG_RX13-</td><td></td><td>D95</td><td>PEG_TX13-</td></tr><tr><td>A96</td><td>TPM_PP</td><td></td><td>B96</td><td>VGA_I2C_DAT $^1$ </td><td></td><td>C96</td><td>GND</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td></td><td>B97</td><td>SPI_CS#</td><td></td><td>C97</td><td>GND</td><td></td><td>D97</td><td>GND</td></tr><tr><td>A98</td><td>SER0_TX</td><td></td><td>B98</td><td>GP_SPI_MISO $^2$ </td><td></td><td>C98</td><td>PEG_RX14+</td><td></td><td>D98</td><td>PEG_TX14+</td></tr><tr><td>A99</td><td>SER0_RX</td><td></td><td>B99</td><td>GP_SPI_CK $^2$ </td><td></td><td>C99</td><td>PEG_RX14-</td><td></td><td>D99</td><td>PEG_TX14-</td></tr><tr><td>A100</td><td>GND (FIXED)</td><td></td><td>B100</td><td>GND (FIXED)</td><td></td><td>C100</td><td>GND (FIXED)</td><td></td><td>D100</td><td>GND (FIXED)</td></tr><tr><td>A101</td><td>SER1_TX/CAN_TX</td><td></td><td>B101</td><td>FAN_PWMOUT</td><td></td><td>C101</td><td>PEG_RX15+</td><td></td><td>D101</td><td>PEG_TX15+</td></tr><tr><td>A102</td><td>SER1_RX/CAN_RX</td><td></td><td>B102</td><td>FAN_TACHIN</td><td></td><td>C102</td><td>PEG_RX15-</td><td></td><td>D102</td><td>PEG_TX15-</td></tr><tr><td>A103</td><td>LID#</td><td></td><td>B103</td><td>SLEEP#</td><td></td><td>C103</td><td>GND</td><td></td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td></td><td>B104</td><td>VCC_12V</td><td></td><td>C104</td><td>VCC_12V</td><td></td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td></td><td>B105</td><td>VCC_12V</td><td></td><td>C105</td><td>VCC_12V</td><td></td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td></td><td>B106</td><td>VCC_12V</td><td></td><td>C106</td><td>VCC_12V</td><td></td><td>D106</td><td>VCC_12V $^1$ </td></tr><tr><td>A107</td><td>VCC_12V</td><td></td><td>B107</td><td>VCC_12V</td><td></td><td>C107</td><td>VCC_12V</td><td></td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td></td><td>B108</td><td>VCC_12V</td><td></td><td>C108</td><td>VCC_12V</td><td></td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td></td><td>B109</td><td>VCC_12V</td><td></td><td>C109</td><td>VCC_12V</td><td></td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND (FIXED)</td><td></td><td>B110</td><td>GND (FIXED)</td><td></td><td>C110</td><td>GND (FIXED)</td><td></td><td>D110</td><td>GND (FIXED)</td></tr></table>

![The image displays a red outline icon resembling a document or note with a folded bottom-right corner. Inside the outline, there are two horizontal lines centered within the shape.](.cexpress-mtl-50m-72221-1010-11/0c323326f010e905c1cda010813d8a53b3f5d1aa7cd93a2a952f583716cf24aa.jpg)

Note: Strike-through entries are not supported functions on this product.

PEG 0-7 are available only for 28W CPU SKUs.

1. eDP (in place of LVDS), VGA (in place of DDI 3), eSPI (in place of LPC), PCIe lane5-7 (via PCIe switch), USB4\_1/2 (in place of DDI 1/2), and GBE0\_SDP (for selected LAN controller versions) are BOM options supported on a project basis.
2. GP\_SPI and SNDW0 support TBC.

# 4.2 Signal Terminology Descriptions

Definitions of terms used in signal description tables

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>I/O</td><td>Bi-directional Input / Output</td></tr><tr><td>OD</td><td>Open drain output from the module</td></tr><tr><td></td><td></td></tr><tr><td>I 3.3V</td><td>Input 3.3V tolerant</td></tr><tr><td>I 5V</td><td>Input 5V tolerant</td></tr><tr><td>O 3.3V</td><td>Output 3.3V signal level</td></tr><tr><td>O 5V</td><td>Output 5V signal level</td></tr><tr><td>I/O 3.3V</td><td>Bi-directional signal 3.3V tolerant</td></tr><tr><td>I/O 5V</td><td>Bi-directional signal 5V tolerant</td></tr><tr><td>I/O  $3.3V_{SB}$ </td><td>Input or output 3.3V tolerant active in standby state</td></tr><tr><td></td><td></td></tr><tr><td>DDC</td><td>Display Data Channel</td></tr><tr><td>PCIE</td><td>PCI Express compatible differential signal</td></tr><tr><td>PEG</td><td>PCI Express Graphics</td></tr><tr><td>SATA</td><td>Serial ATA specification Revision 2.6 and 3</td></tr><tr><td>LVDS</td><td>Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal</td></tr><tr><td></td><td></td></tr><tr><td>P</td><td>Power Input / Output</td></tr><tr><td>REF</td><td>Reference voltage output. May be sourced from a Module power plane.</td></tr><tr><td>PDS</td><td>Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.</td></tr><tr><td></td><td></td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr></table>

# 4.3 AB Connector Signal Descriptions

4.3.1 Audio

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>AC_RST# / HDA_RST#</td><td>A30</td><td>Reset output to CODEC, active low.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>AC_SYNC / HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the CODEC(s).</td><td>O 3.3VSB</td><td></td><td>PCH internal PD 20Kohm</td></tr><tr><td>AC_BITCLK / HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external CODEC(s).</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>AC_SDOUT / HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the CODEC.</td><td>O 3.3VSB</td><td></td><td>PCH internal PD 20Kohm</td></tr><tr><td>AC_SDIN[2:0] / HDA_SDIN[2:0]</td><td>B28 B29 B30</td><td>Serial TDM data inputs from up to 3 CODECs.</td><td>I/O 3.3VSB</td><td></td><td>PCH internal PD 20Kohm AC_SDNI2/HDA_SDIN2 not supported</td></tr></table>

# 4.3.2 Analog VGA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>VGA_RED</td><td>B89</td><td>Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_GRN</td><td>B91</td><td>Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_BLU</td><td>B92</td><td>Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td></td></tr><tr><td>VGA_HSYNC</td><td>B93</td><td>Horizontal sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_VSYNC</td><td>B94</td><td>Vertical sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_I2C_CK</td><td>B95</td><td>DDC clock line (I2C port dedicated to identifying VGA monitor capabilities)</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>VGA_I2C_DAT</td><td>B96</td><td>DDC data line.</td><td>I/O OD 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

![The image displays a simple icon resembling a document or a note. It features a thick, red, rounded-square border with the bottom-right corner folded upwards (a 'dog-ear'). Inside the white area enclosed by the red border, there are two horizontal red lines centered horizontally, resembling simplified text or bullet points.](.cexpress-mtl-50m-72221-1010-11/11ae0a373704625c987965c10659578c2dc277aa5718e2e31e03348ed273352c.jpg)
Note: VGA is supported as a BOM option (in place of DDI 3) on a project basis.

# 4.3.3 LVDS or eDP

The module default supports a single or dual channel LVDS display panel with up to 24-bit colors. A BOM option is available that removes the eDP to LVDS bridge IC and outputs the eDP signals directly. eDP vs LVDS pin mapping is described below.

<table><tr><td>Pin #</td><td>LVDS mode</td><td>eDP mode</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td>eDP_TX2+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td>eDP_TX2-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td>eDP_TX1+</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td>eDP_TX1-</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td>eDP_TX0+</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td>eDP_TX0-</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>-</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>-</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td>eDP_TX3+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td>eDP_TX3-</td></tr><tr><td>B71</td><td>LVDS_B0+</td><td>-</td></tr><tr><td>B72</td><td>LVDS_B0-</td><td>-</td></tr><tr><td>B73</td><td>LVDS_B1+</td><td>-</td></tr><tr><td>B74</td><td>LVDS_B1-</td><td>-</td></tr><tr><td>B75</td><td>LVDS_B2+</td><td>-</td></tr><tr><td>B76</td><td>LVDS_B2-</td><td>-</td></tr><tr><td>B77</td><td>LVDS_B3+</td><td>-</td></tr><tr><td>B78</td><td>LVDS_B3-</td><td>-</td></tr><tr><td>B81</td><td>LVDS_B_CK+</td><td>-</td></tr><tr><td>B82</td><td>LVDS_B_CK-</td><td>-</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td>eDP_VDD_EN</td></tr><tr><td>B79</td><td>LVDS_BKLT_EN</td><td>eDP_BKLT_EN</td></tr><tr><td>B83</td><td>LVDS_BKLT_CTRL</td><td>eDP_BKLT_CTRL</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td>eDP_AUX+</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td>eDP_AUX-</td></tr><tr><td>A87</td><td>-</td><td>eDP_HPD</td></tr></table>

![The image displays a red icon representing a document or text file. It features a thick red outline of a square shape with the top-right corner folded downwards. Inside the outline, there are two horizontal red lines centered vertically, simulating lines of text.](.cexpress-mtl-50m-72221-1010-11/77ddeb143c4ed3a57ebcb537c6cad1b55407ac2ee647740068d2438f4c35a3b7.jpg)
Note: LVDS is the default mode and eDP is a BOM option.

4.3.3.1 Single/Dual Channel LVDS (default)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LVDS_A0+</td><td>A71</td><td>LVDS Channel A differential pairs</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A0-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A2-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3+</td><td>A78</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A3-</td><td>A79</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_A_CK+</td><td>A81</td><td>LVDS Channel A differential clock</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_A_CK-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B0+</td><td>B71</td><td>LVDS Channel B differential pairs</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_B0-</td><td>B72</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B1+</td><td>B73</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B1-</td><td>B74</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B2+</td><td>B75</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B2-</td><td>B76</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B3+</td><td>B77</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B3-</td><td>B78</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_B_CK+</td><td>B81</td><td>LVDS Channel B differential clock</td><td>O LVDS</td><td></td><td></td></tr><tr><td>LVDS_B_CK-</td><td>B82</td><td></td><td></td><td></td><td></td></tr><tr><td>LVDS_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_I2C_CK</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O 3.3V</td><td>PU 2k2 3.3V</td><td></td></tr></table>

4.3.3.2 4-lane eDP

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>eDP_TX3+</td><td>A81</td><td>eDP differential pairs</td><td>O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_TX3-</td><td>A82</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2+</td><td>A71</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX2-</td><td>A72</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1+</td><td>A73</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX1-</td><td>A74</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0+</td><td>A75</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_TX0-</td><td>A76</td><td></td><td></td><td></td><td></td></tr><tr><td>eDP_VDD_EN</td><td>A77</td><td>eDP power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_EN</td><td>B79</td><td>eDP backlight enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_CTRL</td><td>B83</td><td>eDP backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_AUX+</td><td>A83</td><td>eDP AUX+</td><td>I/O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_AUX-</td><td>A84</td><td>eDP AUX-</td><td>I/O PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_HPD</td><td>A87</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>PD 100K on this pin when eDP is supported</td></tr></table>

4.3.4 Gigabit Ethernet

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>GBE0_MDI0+</td><td>A13</td><td rowspan="3">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="8">I/O Analog</td><td rowspan="8"></td><td rowspan="8">Twisted pair signals for external transformer.</td></tr><tr><td>GBE0_MDI0-</td><td>A12</td></tr><tr><td>GBE0_MDI1+</td><td>A10</td></tr><tr><td>GBE0_MDI1-</td><td>A9</td><td>1000 100 10</td></tr><tr><td>GBE0_MDI2+</td><td>A7</td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td></tr><tr><td>GBE0_MDI2-</td><td>A6</td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td></tr><tr><td>GBE0_MDI3+</td><td>A3</td><td>MDI[2]+/- B1_DC+/-</td></tr><tr><td>GBE0_MDI3-</td><td>A2</td><td>MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td>Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td>Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK100# *</td><td>A4</td><td>Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK1000# *</td><td>A5</td><td>Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td>Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>REF GND min 3.3V max</td><td></td><td>Not supported</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td>Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.</td><td>IO 3.3VSB</td><td>GBE0_SDP</td><td>Depends on the selection of LAN controller. i225-IT support this pin</td></tr></table>

![The image displays a red icon representing a memo or document. Inside the red square frame, there is a white shape resembling a piece of paper with a folded bottom-right corner. Two horizontal red lines are centered within the white shape, symbolizing text.](.cexpress-mtl-50m-72221-1010-11/94bcf6551c5d17e3d840e1daa7aa40d254554abd5b85b66c9797e8201c71ca32.jpg)

Note: This product supports up to 2.5GbE. The LAN LED behavior is optimized for maximum 2.5GbE speed.

GBE0\_LINK1000# will be active for 2.5GbE speed indication.

GBE0\_LINK100# will be active for 1GbE speed indication or lower.

GBE0\_ACT# and GBE0\_LINK# share the same source from the LAN controller.

For 100Mbit/sec and 10Mbit/sec speed, the LAN LED will be OFF.

4.3.5 SATA

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_TX+SATA2_TX-</td><td>A22A23</td><td>Serial ATA channel 2, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA2_RX+SATA2_RX-</td><td>A25A26</td><td>Serial ATA channel 2, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA3_TX+SATA3_TX-</td><td>B22B23</td><td>Serial ATA channel 3, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA3_RX+SATA3_RX-</td><td>B25B26</td><td>Serial ATA channel 3, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Not supported</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10K3.3V</td><td>AC coupled on Module</td></tr></table>

4.3.5.1 PCH HSIO Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SOC</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>SATA0</td><td>HSIO 26</td><td></td></tr><tr><td>SATA1</td><td>HSIO 27</td><td></td></tr><tr><td>SATA2</td><td>HSIO 28</td><td>Not supported</td></tr><tr><td>SATA3</td><td>HSIO 29</td><td>Not supported</td></tr></table>

4.3.6 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX4+PCIE_TX4-</td><td>A55A56</td><td>PCI Express channel 4, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX4+PCIE_RX4-</td><td>B55B56</td><td>PCI Express channel 4, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX5+PCIE_TX5-</td><td>A52A53</td><td>PCI Express channel 5, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX5+PCIE_RX5-</td><td>B52B53</td><td>PCI Express channel 5, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>O PCIE</td><td></td><td></td></tr></table>

4.3.6.1 PCH HSIO Lane Assignments

<table><tr><td>Name</td><td>HSIO name on SOC / Switch IC</td><td>Comment</td></tr><tr><td colspan="3"></td></tr><tr><td>PCIE0</td><td>HSIO 22</td><td></td></tr><tr><td>PCIE1</td><td>HSIO 23</td><td></td></tr><tr><td>PCIE2</td><td>HSIO 24</td><td></td></tr><tr><td>PCIE3</td><td>HSIO 25</td><td></td></tr><tr><td>PCIE4</td><td>PCIe SW DPE_0</td><td></td></tr><tr><td>PCIE5</td><td>PCIe SW DPE_1</td><td></td></tr><tr><td>PCIE6</td><td>PCIe SW DPE_6</td><td></td></tr><tr><td>PCIE7</td><td>PCIe SW DPE_14</td><td></td></tr></table>

# 4.3.7 LPC Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>LPC_AD0</td><td>B4</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_AD1</td><td>B5</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD2</td><td>B6</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_AD3</td><td>B7</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>LPC_DRQ0#</td><td>B8</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>Not connected</td></tr><tr><td>LPC_DRQ1#</td><td>B9</td><td></td><td></td><td></td><td></td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O 3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3VSB</td><td></td><td>The LPC_CLK frequency is 24MHz on this platform</td></tr></table>

![The image displays a red icon resembling a document or file with a folded bottom-right corner. Inside the red border, there are two horizontal red lines centered horizontally.](.cexpress-mtl-50m-72221-1010-11/9062e386e324a78aec0f2fc8e5edd8b16ab155325079ecc2d8176a16a4e64c62.jpg)
Note: LPC Bus is supported by an eSPI to LPC bridge IC.

4.3.8 USB

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 1</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 2</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 3</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 4</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 5</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 6</td><td>I/O 3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7 (see *Note)</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>Not supported</td></tr></table>

![The image features a red icon of a document or page on a white background. The icon consists of a red outline of a rectangular shape with a folded bottom-right corner. Inside the outline, two horizontal red lines are centered vertically, representing text.](.cexpress-mtl-50m-72221-1010-11/4e7e5c9dac091d8014134ae634548de91a3e97be919b7cb688fa2c1e3e146658.jpg)
\*Note: A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.

4.3.9 SPI Bus (BIOS only)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for the carrier board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from the carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to the carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to the carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for the carrier board SPI – sourced from the module – nominally 3.3V. The module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>O P 3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not- connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not- connected</td></tr></table>

4.3.10 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the “speaker” in PC-AT systems</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>THRMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3VSB</td><td>PU 100K 3.3VSB</td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.</td><td>O OD 3.3V</td><td></td><td>There shall be PD on carrier board</td></tr><tr><td>FAN_TACHIN</td><td>B102</td><td>Fan tachometer input for a fan with a two-pulse output.</td><td>I OD 3.3V</td><td>PU 47K 3.3V</td><td></td></tr><tr><td>TPM_PP</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100K</td><td>PD only when TPM on module. Modules implementing a TPM shall pull down</td></tr></table>

4.3.11 SMBus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 2.2K3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 4.7K3.3VSB</td><td></td></tr></table>

4.3.12 I2 C Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source SEMA BMC as default (chipset by BOM option)</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source SEMA BMC as default (chipset by BOM option)</td></tr></table>

4.3.13 General Purpose I/O (GPIO)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins. Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

4.3.14 Serial Interface Signals

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>SER0_TX</td><td>A98</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER0_RX</td><td>A99</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr></table>

4.3.15 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for the module to reset and reboot. It may be falling edge sensitive. In situations where SYS_RESET# is unable to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from the module to the carrier board. Active low. Issued by the module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or it may be initiated by the module software.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from the main power supply. A high value indicates that the power is good. This signal can be used to hold off module startup, allowing carrier-based FPGAs or other configurable devices time to be programmed.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Should have weak pull up.</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates an imminent suspend operation; used to notify LPC devices.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates that the system is in the suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O 3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates that the system is in suspend to Disk state. Active low output.</td><td>O 3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates that the system is in Soft Off state.</td><td>O 3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake-up signal.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake-up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low or may be used to signal some other external power-management event.</td><td>I 3.3VSB</td><td>PU 10K 3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal used by the ACPI operating system for a LID switch.</td><td>I OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>I OD 3.3VSB</td><td>PU 47K 3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>RAPID_SHUTDOWN</td><td>C67</td><td>Trigger for Rapid Shutdown. Must be driven to 5V though a &lt;=50-ohm source impedance for ≥20 μs.</td><td>I CMOS 5VSB</td><td></td><td>Not supported</td></tr></table>

4.3.16 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104, A105, A106, A107, A108, A109, B104, B105, B106, B107, B109</td><td>Primary power input supports wide range of 5—20V input. All available VCC_12V pins on the connector(s) should be used.</td><td>P</td><td></td><td>8.5-20 V</td></tr><tr><td>VCC_5V_SBY</td><td>B84, B85, B86, B87</td><td>Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) should be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 4.4 CD Connector Signal Descriptions

4.4.1 USB 3.0 Extensions

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>C3C4</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>D3D4</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>C6C7</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>D6D7</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX2-USB_SSRX2+</td><td>C9C10</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX2-USB_SSTX2+</td><td>D9D10</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX3-USB_SSRX3+</td><td>C12C13</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX3-USB_SSTX3+</td><td>D12D13</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr></table>

# 4.4.1.1 USB Root Segmentation

All USB interfaces are derived from the xHCI controller.

4.4.2 PCI Express

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>PCIE_TX6+PCIE_TX6-</td><td>D19D20</td><td>PCI Express channel 6, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX6+PCIE_RX6-</td><td>C19C20</td><td>PCI Express channel 6, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX7+PCIE_TX7-</td><td>D22D23</td><td>PCI Express channel 7, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX7+PCIE_RX7-</td><td>C22C23</td><td>PCI Express channel 7, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr></table>

# 4.4.2.1 PCH HSIO Lane Assignments

Refer to Section 4.3.6.1 PCH HSIO Lane Assignments on page 36.

# 4.4.3 DDI1 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI1_PAIR0+</td><td>D26</td><td>DP1_LANE0+</td><td>TMDS1_DATA2+</td></tr><tr><td>DDI1_PAIR0-</td><td>D27</td><td>DP1_LANE0-</td><td>TMDS1_DATA2-</td></tr><tr><td>DDI1_PAIR1+</td><td>D29</td><td>DP1_LANE1+</td><td>TMDS1_DATA1+</td></tr><tr><td>DDI1_PAIR1-</td><td>D30</td><td>DP1_LANE1-</td><td>TMDS1_DATA1-</td></tr><tr><td>DDI1_PAIR2+</td><td>D32</td><td>DP1_LANE2+</td><td>TMDS1_DATA0+</td></tr><tr><td>DDI1_PAIR2-</td><td>D33</td><td>DP1_LANE2-</td><td>TMDS1_DATA0-</td></tr><tr><td>DDI1_PAIR3+</td><td>D36</td><td>DP1_LANE3+</td><td>TMDS1_CLK+</td></tr><tr><td>DDI1_PAIR3-</td><td>D37</td><td>DP1_LANE3-</td><td>TMDS1_CLK-</td></tr><tr><td>DDI1_PAIR4+</td><td>C25</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR4-</td><td>C26</td><td></td><td></td></tr><tr><td>DDI1_PAIR5+</td><td>C29</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR5-</td><td>C30</td><td></td><td></td></tr><tr><td>DDI1_PAIR6+</td><td>C15</td><td>-</td><td>-</td></tr><tr><td>DDI1_PAIR6-</td><td>C16</td><td></td><td></td></tr><tr><td>DDI1_HPD</td><td>C24</td><td>DP1_HPD</td><td>HDMI1_HPD</td></tr><tr><td>DDI1_CTRLCLK_AUX+</td><td>D15</td><td>DP1_AUX+</td><td>HMDI1_CTRLCLK</td></tr><tr><td>DDI1_CTRLCLK_AUX-</td><td>D16</td><td>DP1_AUX-</td><td>HMDI1_CTRLDATA</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td><td>DDI1_DDC_AUX_SEL</td></tr></table>

![The image displays a red icon of a document or piece of paper with a folded bottom-right corner. Inside the white interior, there are two horizontal red lines stacked vertically.](.cexpress-mtl-50m-72221-1010-11/7f09175b797bd90a90cec183610ed5317a1476a50970f16e48804e7137c7e9a1.jpg)

Note: Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DCcoupled, while the DP\_AUX+ /- pair must be AC-coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function.

4.4.3.1 DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>DP1_LANE0+</td><td>D26</td><td>DP Port 1, differential pair data lines</td><td>O PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP1_LANE0-</td><td>D27</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP1_LANE1+</td><td>D29</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE1-</td><td>D30</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE2+</td><td>D32</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE2-</td><td>D33</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE3+</td><td>D36</td><td></td><td></td><td></td></tr><tr><td>DP1_LANE3-</td><td>D37</td><td></td><td></td><td></td></tr><tr><td>DP1_HPD</td><td>C24</td><td>DP Port 1, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.</td></tr><tr><td>DP1_AUX+</td><td>D15</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PD 100K</td><td>AC coupled on Module</td></tr><tr><td>DP1_AUX-</td><td>D16</td><td>DP Port 1, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PU 100K</td><td>AC coupled on Module</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode.</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.4.3.2 HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TMDS1_DATA2+</td><td>D26</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIE</td><td rowspan="6"></td><td rowspan="6">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>TMDS1_DATA2-</td><td>D27</td></tr><tr><td>TMDS1_DATA1+</td><td>D29</td></tr><tr><td>TMDS1_DATA1-</td><td>D30</td></tr><tr><td>TMDS1_DATA0+</td><td>D32</td></tr><tr><td>TMDS1_DATA0-</td><td>D33</td></tr><tr><td>TMDS1_CLK+</td><td>D36</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS1_CLK-</td><td>D37</td></tr><tr><td>HDMI_HPD</td><td>C24</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>HDMI1_CTRLCLK</td><td>D15</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>HDMI1_CTRLDATA</td><td>D16</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

4.4.4 DDI2 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI2_PAIR0+</td><td>D39</td><td>DP2_LANE0+</td><td>TMDS2_DATA2+</td></tr><tr><td>DDI2_PAIR0-</td><td>D40</td><td>DP2_LANE0-</td><td>TMDS2_DATA2-</td></tr><tr><td>DDI2_PAIR1+</td><td>D42</td><td>DP2_LANE1+</td><td>TMDS2_DATA1+</td></tr><tr><td>DDI2_PAIR1-</td><td>D43</td><td>DP2_LANE1-</td><td>TMDS2_DATA1-</td></tr><tr><td>DDI2_PAIR2+</td><td>D46</td><td>DP2_LANE2+</td><td>TMDS2_DATA0+</td></tr><tr><td>DDI2_PAIR2-</td><td>D47</td><td>DP2_LANE2-</td><td>TMDS2_DATA0-</td></tr><tr><td>DDI2_PAIR3+</td><td>D49</td><td>DP2_LANE3+</td><td>TMDS2_CLK+</td></tr><tr><td>DDI2_PAIR3-</td><td>D50</td><td>DP2_LANE3-</td><td>TMDS2_CLK-</td></tr><tr><td>DDI2_HPD</td><td>D44</td><td>DP2_HPD</td><td>HDMI2_HPD</td></tr><tr><td>DDI2_CTRLCLK_AUX+</td><td>C32</td><td>DP2_AUX+</td><td>HMDI2_CTRLCLK</td></tr><tr><td>DDI2_CTRLCLK_AUX-</td><td>C33</td><td>DP2_AUX-</td><td>HMDI2_CTRLDATA</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>DDI2_DDC_AUX_SEL</td></tr></table>

![The image displays a red icon on a white background. It features a square shape with a folded bottom-right corner, resembling a piece of paper or a sticky note. Inside the red outline, there are two horizontal red lines near the top center.](.cexpress-mtl-50m-72221-1010-11/30a2371fbfc0b64ab47ab6981ca6c7cf3bf603734654c038439672fd8ed23a45.jpg)

# Note:

Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DCcoupled, while the DP\_AUX+ /- pair must be AC-coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function.

4.4.4.1 DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>DP2_LANE0+</td><td>D39</td><td>DP Port 2, differential pair data lines</td><td>O PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP2_LANE0-</td><td>D40</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP2_LANE1+</td><td>D42</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE1-</td><td>D43</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE2+</td><td>D46</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE2-</td><td>D47</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE3+</td><td>D49</td><td></td><td></td><td></td></tr><tr><td>DP2_LANE3-</td><td>D50</td><td></td><td></td><td></td></tr><tr><td>DP2_HPD</td><td>D44</td><td>DP Port 2, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.</td></tr><tr><td>DP2_AUX+</td><td>C32</td><td>DP Port 2, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PD 100K</td><td>AC coupled on Module</td></tr><tr><td>DP2_AUX-</td><td>C33</td><td>DP Port 2, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PU 100K</td><td>AC coupled on Module</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.4.4.2 HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TMDS2_DATA2+</td><td>D39</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIE</td><td rowspan="6"></td><td rowspan="6">AC coupled off Module100 nF DC blocking capacitors shall be placed on the carrier</td></tr><tr><td>TMDS2_DATA2-</td><td>D40</td></tr><tr><td>TMDS2_DATA1+</td><td>D42</td></tr><tr><td>TMDS2_DATA1-</td><td>D43</td></tr><tr><td>TMDS2_DATA0+</td><td>D46</td></tr><tr><td>TMDS2DATA0-</td><td>D47</td></tr><tr><td>TMDS2_CLK+</td><td>D49</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS2_CLK-</td><td>D50</td></tr><tr><td>HDM2_HPD</td><td>D44</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>HDMI2_CTRLCLK</td><td>C32</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC coupling on the module</td></tr><tr><td>HDMI2_CTRLDATA</td><td>C33</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC coupling on the module</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

4.4.5 DDI3 Port

<table><tr><td>Name</td><td>Pin #</td><td>DisplayPort (DP)</td><td>HDMI</td></tr><tr><td>DDI3_PAIR0+</td><td>C39</td><td>DP3_LANE0+</td><td>TMDS3_DATA2+</td></tr><tr><td>DDI3_PAIR0-</td><td>C40</td><td>DP3_LANE0-</td><td>TMDS3_DATA2-</td></tr><tr><td>DDI3_PAIR1+</td><td>C42</td><td>DP3_LANE1+</td><td>TMDS3_DATA1+</td></tr><tr><td>DDI3_PAIR1-</td><td>C43</td><td>DP3_LANE1-</td><td>TMDS3_DATA1-</td></tr><tr><td>DDI3_PAIR2+</td><td>C46</td><td>DP3_LANE2+</td><td>TMDS3_DATA0+</td></tr><tr><td>DDI3_PAIR2-</td><td>C47</td><td>DP3_LANE2-</td><td>TMDS3_DATA0-</td></tr><tr><td>DDI3_PAIR3+</td><td>C49</td><td>DP3_LANE3+</td><td>TMDS3_CLK+</td></tr><tr><td>DDI3_PAIR3-</td><td>C50</td><td>DP3_LANE3-</td><td>TMDS3_CLK-</td></tr><tr><td>DDI3_HPD</td><td>C44</td><td>DP3_HPD</td><td>HDMI3_HPD</td></tr><tr><td>DDI3_CTRLCLK_AUX+</td><td>C36</td><td>DP3_AUX+</td><td>HMDI3_CTRLCLK</td></tr><tr><td>DDI3_CTRLCLK_AUX-</td><td>C37</td><td>DP3_AUX-</td><td>HMDI3_CTRLDATA</td></tr><tr><td>DDI3_DDC_AUX_SEL</td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td>DDI3_DDC_AUX_SEL</td></tr></table>

![A red icon depicting a document with a folded bottom-right corner and two horizontal lines inside.](.cexpress-mtl-50m-72221-1010-11/a8efd683cd439297affcbf6a625d1b8736f745026569574ec622e6f401125464.jpg)

# Note:

Dual Mode (HDMI and DisplayPort on the same pins) implementations may be realized. This is desirable for SOCs that natively implement this capability. With such SOCs, the primary Dual Mode implementation challenge is that the HDMI\_CTRL\_DAT and HDMI\_CTRL\_CK lines are DCcoupled, while the DP\_AUX+ /- pair must be AC-coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX\_SEL pin function.

4.4.5.1 DisplayPort (DP) Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>DP3_LANE0+</td><td>C39</td><td>DP Port 3, differential pair data lines</td><td>O PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>DP3_LANE0-</td><td>C40</td><td></td><td></td><td></td><td rowspan="7">100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>DP3_LANE1+</td><td>C42</td><td></td><td></td><td></td></tr><tr><td>DP3_LANE1-</td><td>C43</td><td></td><td></td><td></td></tr><tr><td>DP3_LANE2+</td><td>C46</td><td></td><td></td><td></td></tr><tr><td>DP3_LANE2-</td><td>C47</td><td></td><td></td><td></td></tr><tr><td>DP3_LANE3+</td><td>C49</td><td></td><td></td><td></td></tr><tr><td>DP3_LANE3-</td><td>C50</td><td></td><td></td><td></td></tr><tr><td>DP3_HPD</td><td>C44</td><td>DP Port 3, detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>Module must tolerate high level in stand-by mode. The carrier board shall include a blocking FET on DP1_HPD to prevent back-drive current from damaging the Module.</td></tr><tr><td>DP3_AUX+</td><td>C36</td><td>DP Port 3, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PD 100K</td><td>AC coupled on Module</td></tr><tr><td>DP3_AUX-</td><td>C37</td><td>DP Port 3, Bidirectional Channel used for Link Management and Device Control</td><td>I/O PCIE</td><td>PU 100K</td><td>AC coupled on Module</td></tr><tr><td>DDI3_DDC_AUX_SEL</td><td>C38</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a floating pin on the carrier enable DisplayPort mode</td><td>I 3.3V</td><td>PD 1M</td><td>DP mode enabled</td></tr></table>

4.4.5.2 HDMI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TMDS3_DATA2+</td><td>C39</td><td rowspan="6">HDMI / DVI Port, Differential Pair Data Lines</td><td rowspan="6">O PCIE</td><td rowspan="6"></td><td rowspan="6">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier</td></tr><tr><td>TMDS3_DATA2-</td><td>C40</td></tr><tr><td>TMDS3_DATA1+</td><td>C42</td></tr><tr><td>TMDS3_DATA1-</td><td>C43</td></tr><tr><td>TMDS3_DATA0+</td><td>C46</td></tr><tr><td>TMDS3_DATA0-</td><td>C47</td></tr><tr><td>TMDS3_CLK+</td><td>C49</td><td rowspan="2">HDMI Port, Differential Pair Clock Lines</td><td rowspan="2"></td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>TMDS3_CLK-</td><td>C50</td></tr><tr><td>HDM3_HPD</td><td>C44</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>HDMI3_CTRLCLK</td><td>C36</td><td>I2C_CLK Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>HDMI3_CTRLDATA</td><td>C37</td><td>I2C_DAT Line for HDMI</td><td>I/O PCIE</td><td>PU 2.2K</td><td>AC couple on Module</td></tr><tr><td>DDI3_DDC_AUX_SEL</td><td>C38</td><td>Strapping Signal to select HDMI or DP output1M pull-down on the module and a pull high on the carrier enable HDMI mode</td><td>I 3.3V</td><td>PD 1M</td><td>HDMI mode enabled</td></tr></table>

4.4.6 PCIe Graphics Port (PEG)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td>PEG_TX0+PEG_TX0-</td><td>D52 D53</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX0+PEG_RX0-</td><td>C52C53</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX1+PEG_TX1-</td><td>D55 D56</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX1+PEG_RX1-</td><td>C55C56</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX2+PEG_TX2-</td><td>D58 D59</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX2+PEG_RX2-</td><td>C58C59</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX3+PEG_TX3-</td><td>D61 D62</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX3+PEG_RX3-</td><td>C61C62</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX4+PEG_TX4-</td><td>D65 D66</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX4+PEG_RX4-</td><td>C65C66</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX5+PEG_TX5-</td><td>D68 D69</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX5+PEG_RX5-</td><td>C68C69</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX6+PEG_TX6-</td><td>D71 D72</td><td>PCI Express Graphics transmit differential pairs.These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX6+PEG_RX6-</td><td>C71C72</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX7+PEG_TX7-</td><td>D74 D75</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX7+PEG_RX7-</td><td>C74C75</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX8+PEG_TX8-</td><td>D78 D79</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX8+PEG_RX8-</td><td>C78C79</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX9+PEG_TX9-</td><td>D81 D82</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX9+PEG_RX9-</td><td>C81C82</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX10+PEG_TX10-</td><td>D85 D86</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX10+PEG_RX10-</td><td>C85C86</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX11+PEG_TX11-</td><td>D88 D89</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX11+PEG_RX11-</td><td>C88C89</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX12+PEG_TX12-</td><td>D91 D92</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX12+PEG_RX12-</td><td>C91C92</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX13+PEG_TX13-</td><td>D94 D95</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX13+PEG_RX13-</td><td>C94C95</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX14+PEG_TX14-</td><td>D98 D99</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX14+PEG_RX14-</td><td>C98C99</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_TX15+PEG_TX15-</td><td>D101D102</td><td>PCI Express Graphics transmit differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>O PCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PEG_RX15+PEG_RX15-</td><td>C101C102</td><td>PCI Express Graphics receive differential pairs. These are the same lines as PCIE_TX[16:31]+ and – in Module pin-out Type 6</td><td>I PCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PEG_LANE_RV#</td><td>D54</td><td>PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order.</td><td>I 3.3V</td><td></td><td></td></tr></table>

4.4.7 Module Type Definition

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>TYPE0#</td><td>C54</td><td rowspan="3">The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC).</td><td rowspan="3"></td><td rowspan="3"></td><td rowspan="3">Type 6</td></tr><tr><td>TYPE1#</td><td>C57</td></tr><tr><td>TYPE2#</td><td>D57</td></tr><tr><td></td><td></td><td>For Pin-out Type 1 and Type 10 that lack a CD connector, these pins are not present (X)</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>TYPE2# TYPE1# TYPE0#</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>X X X Pinout Type 1</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>X X X Pinout Type 10</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC NC NC Pinout Type 2</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC NC GND Pinout Type 3</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC GND NC Pinout Type 4</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>NC GND GND Pinout Type 5</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>GND NC NC Pinout Type 6</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>GND NC GND Pinout Type 7</td><td></td><td></td><td></td></tr><tr><td></td><td></td><td>The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g. deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.</td><td></td><td></td><td></td></tr><tr><td>TYPE10#</td><td>A97</td><td>In case of a type 10 module this pin signal is tied to GND through a 47K resistor on the module.</td><td></td><td></td><td>No PD</td></tr></table>

4.4.8 Power and Ground

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU / PD</td><td>Comment</td></tr><tr><td colspan="6"></td></tr><tr><td>VCC_12V</td><td>C104, C105, C106, C107, C108, C109, D104, D105, D106, D107, D108, D109</td><td>Primary power input supports wide range 5 to 20V input. All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>8.5-20 V</td></tr><tr><td>GND</td><td>C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches, and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as follows:

# 5.1 Module Feature Locations

![Status LEDs\nBIOS Default\nReset Button\n30-pin Debug\nConnector\nADLINK\nCOM\nExpress\nFan](.cexpress-mtl-50m-72221-1010-11/7b05673b64223402056e681402ca45e414457adb557da762e30113e9b6a25992.jpg)

Figure 3 – Module feature locations (top side)

# 5.2 Debug Connector

This connector is particular useful during the carrier design and bring up phase. It offers access to the following critical parts of the module:

• Test points measurement for internal power rails
• SPI BIOS programming interface
Embedded Controller programming interface

![Two electronic circuit boards connected via a cable, one showing a green CPU interface and the other a green DB30 x86 microcontroller with gold contacts (no text or symbols on components)](.cexpress-mtl-50m-72221-1010-11/221081c342ef0da251745de691fe15fa8d25fe6460feadc6045af9b69a859fe5.jpg)

Figure 4 – cExpress-MTL and debug module

# 5.3 Status LEDs

Status LEDs are mounted on the module to facilitate easier maintenance.

![LED1 LED2 LED3\nIntel\nS2182L04](.cexpress-mtl-50m-72221-1010-11/3f142a7cc8589e1f7ab51ab72b00318cf769e289c17fcacc2a9985a7b67bd233.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td colspan="4"></td></tr><tr><td>LED1</td><td>Blue</td><td>EC output</td><td>Power Sequence Status Code (EC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>EC output and same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

# 5.4 Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td colspan="2"></td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>7</td><td>RESET_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr></table>

# 5.5 Fan Connector

Connector type: JVE 24W1125A-04M00

![Close-up of a green printed circuit board with electronic components and a circular component (no readable text or symbols)](.cexpress-mtl-50m-72221-1010-11/2448435e170eb59809105c01fd99866d66fd8ae7c684029d07310ba064f2cb2c.jpg)

<table><tr><td>Name</td><td>Description</td></tr><tr><td colspan="2"></td></tr><tr><td>1</td><td>FAN_PWMOUT</td></tr><tr><td>2</td><td>FAN_TACHIN</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>12V</td></tr></table>

# 5.6 BIOS Default Reset Button

![Close-up of a printed circuit board with integrated circuits and capacitors (no visible text or symbols)](.cexpress-mtl-50m-72221-1010-11/e6caa3fc7222993424e36f07688326fc45838a0e77f5e37d7fdf6b7d2f72e0d5.jpg)

To perform a hardware reset of BIOS default settings, perform the following steps:

1. Shut down the system.
2. Press and hold the BIOS Setup Defaults Reset button, then boot up the system. You can release the button when the BIOS prompt screen appears.
3. The BIOS prompt screen will display a confirmation that the BIOS defaults have been reset and will request that you reboot the system.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.cexpress-mtl-50m-72221-1010-11/3be3d8f2e02ddbca82bec4bc135b2ecdcbe90bbf9532b4184bf23d6c3295ba22.jpg)

# 6. System Resources

6.1. System Memory Map

<table><tr><td>Address Range (hex)</td><td>Description</td></tr><tr><td>00000000000A0000-000000008BFFFFFF</td><td>PCI Express Root Complex</td></tr><tr><td>000000008C00000 -000000008CFFFFFF</td><td>Intel RST VMD Controller 7D0B</td></tr><tr><td>000000008D000000-000000008D2FFFFF</td><td>PCI Express Root Port</td></tr><tr><td>000000008D300000-000000008D303FFF</td><td>Standard NVM Express Controller</td></tr><tr><td>000000008D400000-000000008D4030FF</td><td>Standard SATA AHCI Controller</td></tr><tr><td>00000000BFFFF000-00000000BFFFFFFF</td><td>Intel Active Management Technology-SOL</td></tr><tr><td>00000000C0000000-00000000CFFFFFFF</td><td>Motherboard resource</td></tr><tr><td>00000000E0D10000-00000000E0D5FFF</td><td>Intel Serial IO GPIO Host Controller-INTC1083</td></tr><tr><td>00000000FC800000-00000000FC81FFF</td><td>Motherboard resource</td></tr><tr><td>00000000FE010000-00000000FE010FFF</td><td>Intel SPI-7E23</td></tr><tr><td>00000000FED00000-00000000FED003FF</td><td>High precision event timer</td></tr><tr><td>00000000FED20000-00000000FED7FFF</td><td>Motherboard resource</td></tr><tr><td>00000000FED40000-00000000FED44FFF</td><td>Trusted Platform Module 2.0</td></tr><tr><td>00000000FED45000-00000000FEEFFFFF</td><td>Motherboard resource</td></tr><tr><td>0000004000000000-0000005010FFFFFF</td><td>Intel Graphics</td></tr><tr><td>0000005012000000-0000005014FFFFFF-</td><td>Intel RST VMD Controller 7D0B</td></tr><tr><td>0000005016200000-000000501623FFF</td><td>Thunderbolt Controller -7EC2</td></tr><tr><td>00000050162A0000-00000050162BFFF</td><td>Intel USB 3.20 eXtensible Host Controller -1.20</td></tr><tr><td>00000050162C8000-00000050162C80FF</td><td>Intel SMBus -7E22</td></tr><tr><td>00000050162CA000-00000050162CAFFF</td><td>Intel Serial IO Host Controller -7E51</td></tr><tr><td>00000050162CB000-00000050162CBFFF</td><td>Intel Serial IO Host Controller -7E50</td></tr><tr><td>00000050162CC000-00000050162CCFFF</td><td>Intel Management Engine Interface #1</td></tr><tr><td>00000050162CD000-00000050162CDFFF</td><td>Intel Serial IO Host Controller -7E7B</td></tr><tr><td>00000050162CE000-00000050162CEFFF</td><td>Intel Serial IO Host Controller -7E79</td></tr><tr><td>00000050162CF000-00000050162CFFFF</td><td>Intel Serial IO Host Controller -7E78</td></tr><tr><td>00000050162D1000-00000050162D1FFF</td><td>Thunderbolt Controller -7EC2</td></tr><tr><td>0000006010000000-0000006010FFFFFF</td><td>Intel Graphics</td></tr><tr><td>0000006016200000-0000006016312FFF</td><td>Thunderbolt Controller -7EC3</td></tr><tr><td>000003FFBEC00000-000003FFBEFFFFFF</td><td>Intel Imaging Signal Processor</td></tr><tr><td>000003FFBFC00000-000003FFBFDDFFFF</td><td>High-Definition Audio Controller</td></tr><tr><td>000003FFBFF80000-000003FFBFF9FFFF</td><td>Intel Innovation Platform Framework Processor Participant</td></tr><tr><td>000003FFBFFBA000-000003FFBFFBAFFF</td><td>Intel Serial IO UART Host Controller -7E25</td></tr><tr><td>000003FFBFFBB000-000003FFBFFBBFFF</td><td>Intel GNA Scoring Accelerator module</td></tr><tr><td>000003FFBFFBC000-000003FFBFFBFFFF</td><td>High-Definition Audio Controller</td></tr><tr><td>000003FFBFFFC000-000003FFBFFFFFFF</td><td>Intel Platform Monotoring (PMT) Driver</td></tr></table>

6.2. I/O Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>00h - 07h</td><td>Communications Port (COM1)</td></tr><tr><td>20h - 2Dh</td><td>Programmable Interrupt controller</td></tr><tr><td>2Eh - 2Fh</td><td rowspan="2">LPC SIO (W83627DHGSEC / NCT6126D) configuration index/data registers</td></tr><tr><td>4Eh - 4Fh</td></tr><tr><td>30h - 3Dh</td><td>Programmable Interrupt controller</td></tr><tr><td>40h - 43h</td><td>System Timer</td></tr><tr><td>60h &amp; 64h</td><td>PS2 Keyboard Mouse</td></tr><tr><td>61h</td><td>Motherboard resources</td></tr><tr><td>62h/66h, 68h/6Ch</td><td>IT5121E</td></tr><tr><td>67h - 92h</td><td>Real Time Clock Controller</td></tr><tr><td>A0h - B1h</td><td>Programmable Interrupt controller</td></tr><tr><td>B2h - B3h</td><td>Motherboard resources</td></tr><tr><td>B4h - BDh</td><td>Programmable Interrupt controller</td></tr><tr><td>200h - 201h</td><td>IT5121E</td></tr><tr><td>240h - 247h</td><td>Serial port 3 (COM3)</td></tr><tr><td>248h - 24Fh</td><td>Serial port 4 (COM4)</td></tr><tr><td>2F8h - 2FFh</td><td>Serial port 2 (COM2)</td></tr><tr><td>3F8h - 3FFh</td><td>Serial port 1 (COM1)</td></tr><tr><td>4D0h - 4D1h</td><td>Programmable Interrupt controller</td></tr><tr><td>680h - A6Fh</td><td>Motherboard resources</td></tr><tr><td>D00h - FFFFh</td><td>PCI Express Root Complex</td></tr><tr><td>164Eh – 20FEh</td><td>Motherboard resources</td></tr><tr><td>3020h – 3057h</td><td>Standard SATA AHCI Controller</td></tr><tr><td>EFA0h – EFBFh</td><td>Intel SMBus – 7E22</td></tr></table>

# 6.3. Interrupt Request (IRQ) Lines

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>System timer</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Standard PS/2 Keyboard</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>3</td><td>Serial Port 2</td><td>IRQ3 via SERIRQ</td><td>COM2</td></tr><tr><td>4</td><td>Serial Port 1</td><td>IRQ4 via SERIRQ</td><td>COM1</td></tr><tr><td>5</td><td>Serial Port 3</td><td>IRQ5 via SERIRQ</td><td>COM3</td></tr><tr><td>7</td><td>Serial Port 4</td><td>IRQ7 via SERIRQ</td><td>COM4</td></tr><tr><td>12</td><td>Standard PS/2 Mouse</td><td>IRQ12 via SERIRQ</td><td>No</td></tr><tr><td>14</td><td>Intel Serial IO Host GPIO Controller</td><td>N/A</td><td>No</td></tr><tr><td>16</td><td>High-Definition Audio Controller</td><td>N/A</td><td>No</td></tr><tr><td>16</td><td>Intel Serial IO UART Host Controller</td><td>N/A</td><td>No</td></tr><tr><td>19</td><td>Intel Active Management Technology</td><td>N/A</td><td>No</td></tr><tr><td>29</td><td>Intel Serial IO I2C Host Controller 7E50</td><td>N/A</td><td>No</td></tr><tr><td>30</td><td>Intel Serial IO I2C Host Controller 7E51</td><td>N/A</td><td>No</td></tr><tr><td>32</td><td>Intel Serial IO I2C Host Controller 7E78</td><td>N/A</td><td>No</td></tr><tr><td>33</td><td>Intel Serial IO I2C Host Controller 7E79</td><td>N/A</td><td>No</td></tr><tr><td>35</td><td>Intel Serial IO I2C Host Controller 7E7B</td><td>N/A</td><td>No</td></tr><tr><td>55 to 511</td><td>Microsoft ACPI Compliant System</td><td>N/A</td><td>No</td></tr><tr><td>-76</td><td>Intel GNA Scoring Accelerator module</td><td>N/A</td><td>No</td></tr><tr><td>-75 to -63</td><td>Intel Ethernet Controller I226-IT</td><td>N/A</td><td>No</td></tr><tr><td>-62</td><td>Intel Management Engine Interface</td><td>N/A</td><td>No</td></tr><tr><td>-61</td><td>Intel USB 3.20 eXtensible Host Controller -1.20</td><td>N/A</td><td>No</td></tr><tr><td>-60 to -45</td><td>Thunderbolt Controller -7EC2</td><td>N/A</td><td>No</td></tr><tr><td>-44</td><td>Intel USB 3.20 eXtensible Host Controller -1.20</td><td>N/A</td><td>No</td></tr><tr><td>-43</td><td>Intel Graphics</td><td>N/A</td><td>No</td></tr><tr><td>-42 to -24</td><td>Intel RST VMD Controller 7D0B</td><td>N/A</td><td>No</td></tr><tr><td>-23 to -7</td><td>Standard NVM Express Controller</td><td>N/A</td><td>No</td></tr><tr><td>-6</td><td>Standard SATA AHCI Controller</td><td>N/A</td><td>No</td></tr><tr><td>-5 to -2</td><td>PCI Express Root Port</td><td>N/A</td><td>No</td></tr></table>

![The image displays a red icon resembling a document or text file. It features a white square with a thick red outline, where the bottom-right corner is folded upwards. Inside the white space, two horizontal red lines are centered vertically, resembling text.](.cexpress-mtl-50m-72221-1010-11/d3b4a5ceb0bffa5290cd483cfe76c31e033efa80a77908f451cc6e5f5a17afe5.jpg)
Note: These IRQs can be used for PCI devices when the onboard device is disabled.

6.4. PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Corporation Host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel Corporation VGA Controller</td></tr><tr><td>00h</td><td>04h</td><td>00h</td><td>Internal</td><td>Intel Corporation Data Acquisition</td></tr><tr><td>00h</td><td>05h</td><td>00h</td><td>Internal</td><td>Intel Corporation Multimedia Device</td></tr><tr><td>00h</td><td>06h</td><td>00h</td><td>Internal</td><td>Intel Corporation PCI To PCI Bridge</td></tr><tr><td>00h</td><td>06h</td><td>02h</td><td>Internal</td><td>Intel Corporation PCI To PCI Bridge</td></tr><tr><td>00h</td><td>07h</td><td>00h</td><td>Internal</td><td>Intel Corporation PCI To PCI Bridge</td></tr><tr><td>00h</td><td>07h</td><td>01h</td><td>Internal</td><td>Intel Corporation PCI To PCI Bridge</td></tr><tr><td>00h</td><td>08h</td><td>00h</td><td>Internal</td><td>Intel Corporation System Device</td></tr><tr><td>00h</td><td>0Ah</td><td>00h</td><td>Internal</td><td>Intel Corporation Data Acquisition</td></tr><tr><td>00h</td><td>0Dh</td><td>00h</td><td>Internal</td><td>Intel Corporation XHCI USB Controller</td></tr><tr><td>00h</td><td>0Dh</td><td>02h</td><td>Internal</td><td>Intel Corporation USB Controller</td></tr><tr><td>00h</td><td>0Eh</td><td>00h</td><td>Internal</td><td>Intel Corporation RAID Controller</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>Intel Corporation XHCI USB Controller</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>Intel Corporation RAM Controller</td></tr><tr><td>00h</td><td>15h</td><td>00h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>15h</td><td>01h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>15h</td><td>03h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel Corporation Communication Device</td></tr><tr><td>00h</td><td>16h</td><td>03h</td><td>Internal</td><td>Intel Corporation Serial Device</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Internal</td><td>Intel Corporation AHCI Controller</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>19h</td><td>01h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>1Eh</td><td>00h</td><td>Internal</td><td>Intel Corporation Communication Device</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel Corporation ISA Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>Intel Corporation HD Audio Device</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>Intel Corporation SMBus Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>01h</td><td>00h</td><td>00h</td><td>Internal</td><td>Intel Corporation Elthernet Controller</td></tr><tr><td>02h</td><td>00h</td><td>00h</td><td>Internal</td><td>Mass Storage Controller</td></tr></table>

6.5. PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>IOE PCIE Port 1</td><td>IOE PCIE Port 2</td><td>Lpc Bridge</td><td>HD Audio Controller</td><td>SMBus</td><td>SATA Controller</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTC:34</td><td>none</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTB:17</td><td>INTB:17</td><td>INTD:35</td><td>none</td><td>none</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTC:18</td><td>INTC:18</td><td>INTA:32</td><td>INTC:18</td><td>none</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTD:19</td><td>INTD:19</td><td>INTB:33</td><td>none</td><td>none</td></tr></table>

<table><tr><td>INT Line</td><td>XHCI Controller</td><td>TypeC Subsystem XHCI</td><td>ITBT PCIE Port 0</td><td>ITBT PCIE Port 1</td><td>ITBT PCIE Port 2</td><td>ITBT PCIE Port 3</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTA:17</td><td>INTB:17</td><td>INTB:17</td><td>INTB:17</td><td>INTB:17</td></tr><tr><td>Int2</td><td>none</td><td>none</td><td>INTC:18</td><td>INTC:18</td><td>INTC:18</td><td>INTC:18</td></tr><tr><td>Int3</td><td>none</td><td>none</td><td>INTD:19</td><td>INTD:19</td><td>INTD:19</td><td>INTD:19</td></tr></table>

<table><tr><td>INT Line</td><td>PCIE Port1</td><td>PCIE Port 2</td><td>PCIE Port 3</td><td>PCIE Port 4</td><td>PCIE Port 5</td><td>PCIE Port 6</td><td>PCIE Port 7</td><td>PCIE Port 8</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB 17</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td></tr></table>

# 6.6. SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DDR5 Channel A(SO-DIMM1)</td><td>A0h</td></tr><tr><td>DDR5 Channel B(SO-DIMM2)</td><td>A2h</td></tr></table>

# 7. BIOS Setup

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS InformationSystem InformationSystem DateSystem Time</td><td>CPU Configuration▶Power &amp; Performance ▶Graphics Configuration ▶Platform Settings ▶Power Management ▶System Management ▶Thermal Management ▶Watchdog Timer ▶USB Configuration ▶AMI Graphic Output Protocol Policy ▶Super IO Configuration ▶Serial Port Console Redirection ▶Miscellaneous ▶Network Stack Configuration ▶NVME Configuration ▶Trusted Computing ▶Intel Ethernet Controller ▶</td><td>System Agent (SA)Configuration ▶PCH-IO Configuration ▶</td><td>PasswordDescriptionSecure BootMenu ▶</td><td>BootConfiguration</td><td>Save OptionsDefault OptionsBoot Override</td></tr></table>

![The image displays a simple red icon featuring a square shape with a folded bottom-right corner, containing two horizontal red lines in the center to represent a document or text.](.cexpress-mtl-50m-72221-1010-11/9493fa80c76203a4b43cc120d12b81d069f98d2dd84a5ec975a670db6d93f267.jpg)
Note: ► indicates a submenu
Gray text indicates info only

# 7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the system date and time. Refer to the tables below the screenshot of this menu for details on the submenus and settings.

7.2.1. BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vender</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Displays Core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays compliancy information</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Displays compliancy information</td></tr><tr><td>GOP Driver Version</td><td>Info only</td><td>Displays Intel Graphic Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Displays Intel CSME Version</td></tr></table>

7.2.2. System Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Displays Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Displays CPU Signature</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Displays CPU Brand Name</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays CPU Stepping</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Displays CPU Frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Displays installed memory size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays memory frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Displays PCH Information.</td></tr><tr><td>Board Information</td><td>Submenu</td><td></td></tr></table>

7.2.3. Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Displays SMC serial Number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Displays SMC manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Displays SMC last repair date.</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Displays SMC MAC ID.</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down.</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.2.4. System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1. CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Brand String</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel Virtualization Technology support or not.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled,Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Performance-cores</td><td>All, 5, 4, 3, 2, 1</td><td>Number of P-cores to enable in each processor package. Note: Number of Cores and E-cores are looked at together. When both are {0,0}, Pcode will enable all cores.</td></tr><tr><td>Active Efficient-cores</td><td>All,7,6,5,4,3,2,1,0</td><td>Number of E-cores to enable in each processor package. Note: Number of Cores and E-cores are looked at together. When both are {0,0}, Pcode will enable all cores.</td></tr><tr><td>Hyper-Threading</td><td>Disabled,Enabled</td><td>Enable or Disable Hyper-Threading Technology.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>Disabled,Enabled</td><td>Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect.</td></tr><tr><td>Total Memory Encryption</td><td>DisabledEnabled</td><td>Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.</td></tr></table>

# 7.3.2. Power & Performance Configuration

7.3.2.1. CPU - Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Performance Mode</td><td>Max Battery, Max Non-Turbo Performance, Turbo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled, Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Race To Halt (RTH)</td><td>Disabled, Enabled</td><td>Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled, Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware-controlled P-states.</td></tr><tr><td>Per Core P State OS control P State</td><td>Disabled, Enabled</td><td>Enable/Disable Per Core P state OS control mode. Disabling will set Bit 31 = 1 command 0x06. When set, the highest core request is used for all other core requests.</td></tr><tr><td>HwP Autonomous Per Core P State</td><td>Disabled, Enabled</td><td>Disable Autonomous PCPS (Bit 30 = 1, command 0x11) Autonomous will request the same value for all cores all the time. Enable PCPS (default Bit 30 = 0, command 0x11)</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>Disabled, Enabled</td><td>Enable EPP grouping (default Bit 29 =0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (Bit 29 =1 , command 0x11) autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>Disabled, Enabled</td><td>Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b , subcommand 0x3 to 1. This will allow OOB EPB PECI override control</td></tr><tr><td>HwP Lock</td><td>Disabled, Enabled</td><td>Enable/Disable HWP Lock support in Misc Power Management MSR.</td></tr><tr><td>HDC Control</td><td>Disabled, Enabled</td><td>This option allows HDC configuration.</td></tr><tr><td>Turbo Mode</td><td>Disabled, Enabled</td><td>Enable/Disable processor Turbo Mode (requires EMTTM enabled too). AUTO means enabled.</td></tr><tr><td>View/Configure Turbo Options</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Current Turbo Settings</td></tr><tr><td>Max Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Min Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Power Limit 1</td><td>Info only</td><td></td></tr><tr><td>Power Limit 2</td><td>Info only</td><td></td></tr><tr><td>Energy Efficient P-state</td><td>Disabled, Enabled</td><td>Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR 1B0h and CPUID Fun</td></tr><tr><td>Package Power Limit MSR Lock</td><td>Disabled, Enabled</td><td>Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.</td></tr><tr><td>Energy Efficient Turbo</td><td>Disabled, Enabled</td><td>Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.</td></tr><tr><td>Config TDP Configurations</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Config TDP Configurations</td></tr><tr><td>Enable Configurable TDP</td><td>Applies to non-cTDP, Applies to cTDP</td><td>Applies TDP initialization settings based on non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and BIOS will bypass cTDP initialization flow</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal, Down2, Down1, Deactivate</td><td>Configurable TDP Mode as Nominal/Up/Down/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>Configurable TDP Lock</td><td>Enabled, Disabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0.</td></tr><tr><td>ConfigTDP Levels</td><td>3</td><td></td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>24 (Unlocked)</td><td></td></tr><tr><td>Power Limit 1</td><td>45.0W (MSR:45.0)</td><td></td></tr><tr><td>Power Limit 2</td><td>115.0W (MSR:115.0)</td><td></td></tr><tr><td colspan="3">Custom Settings Nominal</td></tr><tr><td>ConfigTDP Nominal</td><td>Ratio:25 TAR:24 PL1:13.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0xFF, 0x00, 0x01]</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td colspan="3">Custom Settings Level1</td></tr><tr><td>ConfigTDP Level1</td><td>Ratio:18 TAR:17 PL1:3.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit andTDP</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does notexceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 112, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>0</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value.</td></tr><tr><td colspan="3">Custom Settings Level2</td></tr><tr><td>ConfigTDP Level2</td><td>Ratio:28 TAR:27 PL1:1.0W</td><td></td></tr><tr><td>Power Limit 1</td><td>0</td><td>Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Overclocking SKU: Value must be between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). Other SKUs: This value must be between Min Power Limit and TDP</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. 0 = no custom override. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td>Power Limit 1 Time Window*</td><td>0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 14, 16, 20, 24, 28, 32, 40, 48, 56, 64, 80, 96, 111, 128</td><td>Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which TDP value should be maintained.</td></tr><tr><td>ConfigTDP Turbo Activation Ratio</td><td>0</td><td>Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value</td></tr><tr><td>CPU VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">CPU VR Settings</td></tr><tr><td>Current VccIn Aux Icc Max</td><td>136</td><td></td></tr><tr><td>PSYS Slope</td><td>0</td><td>PSYS Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x9."</td></tr><tr><td>PSYS Offset</td><td>0</td><td>PSYS Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. PSYS Uses BIOSVR mailbox command 0x4.</td></tr><tr><td>PSYS Prefix</td><td>+, -</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>PSYS PMax Power</td><td>0</td><td>PSYS PMax power, defined in 1/8 Watt increments. Range 0-8192. For a PMax of 125W, enter 1000. 0 = AUTO. Uses BIOS VR mailbox command 0xB.</td></tr><tr><td>Min Voltage Override</td><td>Disabled, Enabled</td><td>Min Voltage Override. Enable to override minimum voltage for runtime and for C8.</td></tr><tr><td>VccIn Aux Icc Max</td><td>0</td><td>Sets the Max Icc VccIn Aux value defined in 1/4A increments. Range is 0-512. For an IccMax 32A, enter 128(32*4).</td></tr><tr><td>VccIn Aux IMON Slope</td><td>100</td><td>VccIN Aux IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Offset</td><td>0</td><td>VccIN Aux IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x18.</td></tr><tr><td>VccIn Aux IMON Prefix</td><td>+.-</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>Vsys/Psys Critical</td><td>Disabled,Psys Critical,Vsys Critical</td><td>Vsys/Psys Critical Enable or disable</td></tr><tr><td>Assertion Deglitch Mantissa</td><td>1</td><td>Assertion Deglitch Mantissa 0x4F[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>Assertion Deglitch Exponent</td><td>0</td><td>Assertion Deglitch Exponent 0x4F[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Mantissa</td><td>13</td><td>De Assertion Deglitch Mantissa 0x49[7-3]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>De assertion Deglitch Exponent</td><td>2</td><td>De Assertion Deglitch Exponent 0x49[3-0]. Assertion Deglitch = 2μs * Mantissa * 2^(Exponent)</td></tr><tr><td>VR Power Delivery Design</td><td>Auto</td><td>Specifies the ADL Desktop board design used for the VR settings override values. By default, BIOS will override the default Desktop VR settings based on the board design. A value of AUTO(0) will use the board ID to determine the board design. Any other value will override the board id logic to provide a custom VR Power Delivery Design value. This is intended primarily for validation.</td></tr><tr><td>Acoustic Noise Settings</td><td>Submenu</td><td></td></tr><tr><td>Acoustic Noise Mitigation</td><td>Disabled, Enabled</td><td>Enabling this option will help mitigate acoustic noise on certain SKUs when the CPU is in deeper C state</td></tr><tr><td>Pre Wake Time</td><td>0</td><td>Set the maximum Pre Wake randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Up Time</td><td>0</td><td>Set the maximum Ramp Up randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td>Ramp Down Time</td><td>0</td><td>Set the maximum Ramp Down randomization time in micro ticks. Range is 0-255. This is for acoustic noise mitigation Dynamic Periodicity Alteration (DPA) tuning.</td></tr><tr><td colspan="3">IA VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for IA Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state.</td></tr><tr><td>Slow Slew Rate for IA Domain</td><td>Fast/2, Fast/4, Fast/8, Fast/16</td><td>Set VR IA Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8, 16 to slow down the slew rate to help minimize acoustic noise</td></tr><tr><td colspan="3">GT VR Domain</td></tr><tr><td>Disable Fast PKG C State Ramp for GT Domain</td><td>FALSE, TRUE</td><td>This option needs to be configured to reduce acoustic noise during deeper C states. False: Don't disable Fast ramp during deeper C states; True: Disable Fast ramp during deeper C state</td></tr><tr><td>Slow Slew Rate for GT Domain</td><td>Fast/2, Fast/4, Fast/8</td><td>Set VR GT Slow Slew Rate for Deep Package C State ramp time; Slow slew rate equals to Fast divided by number, the number is 2, 4, 8 to slow down the slew rate to help minimize acoustic noise; divide by 16 is disabled</td></tr><tr><td>Core/IA VR Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Core/IA VR Domain</td></tr><tr><td>VR Config Enable</td><td>Disabled, Enabled</td><td>VR Config Enable</td></tr><tr><td>Current AC Loadline</td><td>230</td><td></td></tr><tr><td>Current DC Loadline</td><td>230</td><td></td></tr><tr><td>Current Psi1 Threshold</td><td>80</td><td></td></tr><tr><td>Current Psi2 Threshold</td><td>20</td><td></td></tr><tr><td>Current Psi3 Threshold</td><td>4</td><td></td></tr><tr><td>Current Imon Slope</td><td>0</td><td></td></tr><tr><td>Current Imon Offset</td><td>1</td><td></td></tr><tr><td>Current VR Current Limit</td><td>640</td><td></td></tr><tr><td>Current Tdc Current Limit</td><td>640</td><td></td></tr><tr><td>Current Voltage Limit</td><td>1600</td><td></td></tr><tr><td>AC Loadline</td><td>0</td><td>AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>DC Loadline</td><td>0</td><td>DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. Uses BIOS mailbox command 0x2.</td></tr><tr><td>PS Current Threshold1</td><td>80</td><td>PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold2</td><td>20</td><td>PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS Current Threshold3</td><td>4</td><td>PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, which translates to 0-128A. 0 = AUTO. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS3 Enable</td><td>Disabled, Enabled</td><td>PS3 Enable/Disable. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>PS4 Enable</td><td>Disabled, Enabled</td><td>PS4 Enable/Disable. 0 - Disabled, 1 - Enabled. Uses BIOS VR mailbox command 0x3.</td></tr><tr><td>IMON Slope</td><td>0</td><td>IMON Slope defined in 1/100 increments. Range is 0-200. For a 1.25 slope, enter 125. 0 = AUTO. Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Offset</td><td>0</td><td>IMON Offset defined in 1/1000 increments. Range is 0-63999. For an offset of 25.348, enter 25348. IMON Uses BIOS VR mailbox command 0x4.</td></tr><tr><td>IMON Prefix</td><td>+,-</td><td>Sets the offset value as positive or negative.</td></tr><tr><td>VR Current Limit</td><td>0</td><td>Voltage Regulator Current Limit (IccMax). This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 0 means AUTO. Uses BIOS VR mailbox command 0x6.</td></tr><tr><td>Core VR Fast Vmode</td><td>Disabled, Enabled</td><td>Core VR Fast Vmode. Use to control Core Fast Vmode Enable/Disable. The value will only be effective by enabling the corresponding CEP.</td></tr><tr><td>Fast Vmode Itrip ICC Limit</td><td>548</td><td>Voltage Regulator Fast Vmode Itrip ICC Limit. A value of 400 = 100A. A value of 0 corresponds to feature disabled (no reactive protection). This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. The value is represented in 1/4 A increments. Uses BIOS VR mailbox command 0x25.</td></tr><tr><td>VR Voltage Limit</td><td>0</td><td>Voltage Limit (VMAX). This value represents the Maximum instantaneous voltage allowed at any given time. Range is 0 - 7999mV. Uses BIOS VR mailbox command 0x8.</td></tr><tr><td>TDC Enable</td><td>Disabled, Enabled</td><td>TDC Enable. 0- Disable, 1 - Enable</td></tr><tr><td>TDC Current Limit</td><td>0</td><td>TDC Current Limit, defined in 1/8A increments. Range 0-32767. For a TDC Current Limit of 125A, enter 1000. 0 = 0 Amps. Uses BIOS VR mailbox command 0x1A.</td></tr><tr><td>TDC Time Window</td><td>1 sec</td><td>VR TDC Time Window, value in seconds. 1s is default. Range from 1s to 448s.</td></tr><tr><td>TDC Lock</td><td>Disabled, Enabled</td><td>TDC Lock</td></tr><tr><td>IRMS</td><td>Disabled, Enabled</td><td>Enable/Disable IRMS – Current root mean square</td></tr><tr><td>GT VR Settings</td><td>Submenu</td><td></td></tr><tr><td>RFI Settings</td><td>Submenu</td><td></td></tr><tr><td colspan="3">RFI Domain</td></tr><tr><td>RFI Current Frequency</td><td>139.200MHz</td><td></td></tr><tr><td>RFI Frequency</td><td>0</td><td>Set desired RFI frequency, in increments of 100KHz. (For a frequency of 100.6MHz, enter 1006.)</td></tr><tr><td>FIVR Spread Spectrum</td><td>Disabled, Enabled</td><td>Enable or Disable the Spread Spectrum</td></tr><tr><td>RFI Spread Spectrum</td><td>0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%</td><td>Set the Spread Spectrum</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled, Enabled</td><td>Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>Disabled, Enabled</td><td>Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2.</td></tr><tr><td>ATX Telemetry Unit</td><td>Watts, Percentage</td><td>ATX Telemetry Unit in Watts or Percentage.</td></tr><tr><td>Power Limit 4 Override</td><td>Disabled, Enabled</td><td>Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>Disabled, Enabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Thermal Monitor</td><td>Disabled, Enabled</td><td>Enable/Disable Thermal Monitor</td></tr><tr><td>Interrupt Redirection Mode Selection</td><td>Fixed Priority, Round robin, Hash Vector, No Change</td><td>Interrupt Redirection Mode Select for Logical Interrupts</td></tr><tr><td>Timed MWAIT</td><td>Disabled, Enabled</td><td>Enable/Disable Timed MWAIT Support</td></tr><tr><td>Custom P-state Table</td><td>Submenu</td><td></td></tr><tr><td colspan="3">Custom P-state Table</td></tr><tr><td>Number of P states</td><td>0</td><td>Sets the number of custom P-states. At least 2 states must be present.</td></tr><tr><td>EC Turbo Control Mode</td><td>Disabled, Enabled</td><td>Enable/Disable EC Turbo Control mode</td></tr><tr><td>Energy Performance Gain</td><td>Disabled, Enabled</td><td>Enable/Disable Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>26</td><td></td></tr><tr><td>EPG DIMM ldd3P</td><td>11</td><td></td></tr><tr><td>Power Limit 3 Settings</td><td>Submenu</td><td></td></tr><tr><td>Power Limit 3 Override</td><td>Disabled, Enabled</td><td>Enable/Disable Power Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CPU Lock Configuration</td><td>Submenu</td><td>Enable/Disable Power Limit 3 override. If this option is disabled, BIOS will leave the hardware default values for Power Limit 3 and Power Limit 3 Time Window.</td></tr><tr><td>CFG Lock</td><td>Disabled, Enabled</td><td>Configure MSR 0Xe2[15], CFG Lock bit</td></tr><tr><td>Overclocking Lock</td><td>Disabled, Enabled</td><td>Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO (194) MSR</td></tr></table>

# 7.3.2.2. GT Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RC6(Render Standby)*</td><td>Disabled, Enabled</td><td>Check to enable render standby support.</td></tr><tr><td>Maximum GT frequency</td><td>Default Max Frequency,100Mhz, 150Mhz,200Mhz, 250Mhz,300Mhz, 350Mhz,400Mhz, 450Mhz,500Mhz, 550Mhz,600Mhz, 650Mhz,700Mhz, 750Mhz,800Mhz, 850Mhz,900Mhz, 950Mhz,1000Mhz, 1050Mhz,1100Mhz, 1150Mhz,1200Mhz</td><td>Maximum GT frequency limited by the user. Choose between 100MHz (RPN) and 1350MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU</td></tr><tr><td>Disable Turbo GT frequency</td><td>Enabled, Disabled</td><td>Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited</td></tr></table>

7.3.3. Graphic Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>LVDS Backlight Mode</td><td>EC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight</td><td>Submenu</td><td></td></tr><tr><td>LVDS Backlight Brightness</td><td>Value Range (0-255)</td><td>A change takes effect immediately. The value range starts by 0 and ends of 255.</td></tr><tr><td>DDI port 3</td><td>No DeviceDisplay PortHDMIDisplayPort withHDMI/DVI Compatibility</td><td>DDI port 3 function choose to DisplayPort or HDMI</td></tr></table>

# 7.3.4. Platform Settings

7.3.4.1. TSCC Platform Setting

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Disable TBT PCIE Tree BME</td><td>Disabled, Enabled</td><td>Recommend enabling &#x27;VT-d&#x27;, &#x27;DMA Control Guarantee&#x27; and &#x27;Control Iommu Pre-boot Behavior&#x27; options along with this.</td></tr><tr><td>USBC connector manager selection</td><td>DisableEnable UCSI 1.2Enable UCSI 2.0</td><td>Select UCSI or UCMC device in ACPI support based on configuration</td></tr><tr><td>Type C retimer TX Compliance Mode</td><td>DisableEnable</td><td>Default is disable Compliance Mode. Change to enabled for Type C retimer Tx Compliance Mode testing.</td></tr><tr><td>BIOS-TCSS handshake</td><td>DisabledEnable</td><td>Enable/Disable BIOS TCSS handshake messages.\nDisabled: TCSS handshake disabled \nEnabled: TCSS handshake with either EC or PMC is enabled based on the board ID</td></tr><tr><td>Timeout for EC USB enumeration message</td><td>Range 50 to 1000Default 500</td><td>BIOS-EC handshake message USBC_GetUSBConnStatus timeout value in milli seconds</td></tr><tr><td>USBC and USBA Wake Capability</td><td>S3S4</td><td>USBC and USBA Wake Capability</td></tr><tr><td>PD PS_ON mode selection</td><td>DisableEnable PD/PD-lessPS_ON</td><td>Select TCSS PD Policy on Low Power Entry</td></tr><tr><td>Type C Port 1Conv to Type</td><td>DisableEnable</td><td>Enable / Disable Type C Port 1 Convert to TypeA</td></tr><tr><td>Type C Port 2Conv to Type</td><td>DisableEnable</td><td>Enable / Disable Type C Port 2 Convert to TypeA</td></tr><tr><td>Type C Port 3Conv to Type</td><td>DisableEnable</td><td>Enable / Disable Type C Port 3 Convert to TypeA</td></tr><tr><td>Type C Port 4Conv to Type</td><td>DisableEnable</td><td>Enable / Disable Type C Port 4 Convert to TypeA</td></tr><tr><td>Thunder (TM) Configuration</td><td></td><td></td></tr><tr><td>USBC DataRole Swap Platform Disable Option</td><td>TRUEFALSE</td><td>Enable/Disable setting USBC DataRole Swap Platform Disable Option</td></tr></table>

7.3.4.1.1 Thunder (TM) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIE Tunneling over USB4</td><td>Disabled, Enabled</td><td>Enable or disable PCIE Tunneling over USB4</td></tr><tr><td>USB4 CM Mode</td><td>Firmware CMSoftware CMOS DependentCM Debug</td><td>FW CM - The system boots with FW CM in both BIOS and OS phase.\nSW CM - The system boots with SW CM in BIOS phase all the time, then boot to OS based on OS preference for backward and forward compatible.\nOS dependent - The system will boot with SW CM in BIOS phase after saving this setting, then boot to OS based on OS preference the reflect to CM setting to next BIOS boot.\nCM debug - The system with boot without any CM in BIOS phase, then boot to OS with the CM based on OS&#x27; preference by every boot.</td></tr><tr><td>Integrated Thunderbolt (TM) Enable</td><td>Disable Enable</td><td>Enable or Disable Integrated Thunderbolt (TM).</td></tr><tr><td>OS Native Resource Balance</td><td>Disabled Enable</td><td>OS Native Resource Balance</td></tr><tr><td>Connect Topology Timeout value for ITBT</td><td>Range 1 to 65535Default 5000</td><td>Connect Topology Timeout value for Integrated Thunderbolt (TM) Controller</td></tr><tr><td>Force Power on Timeout value for ITBT</td><td>Range 1 to 65535Default 500</td><td>Force Power On Timeout value for Integrated Thunderbolt (TM)</td></tr><tr><td>ITBT RTD3</td><td>Disable Enable</td><td>ITBT RTD3 Enable/Disable. Note: ITBT RTD3 Disabled is not supported when SW CM is applied for OS</td></tr><tr><td>ITBT RTD3 EXIT DELAY</td><td>Range 0 to 20000Default 0</td><td>ITBT RTD3 EXIT DELAY</td></tr><tr><td>PCIE RTD3 POLLING LINK ACTIVE TIMEOUT</td><td>Range 0 to 20000Default 0</td><td>ADJUST LINK ACTIVE POLLING TIME DURING D3C EXIT AND DELAY IN PS0 BEFORE RETURN TO OS (milli seconds)</td></tr></table>

7.3.4.2. ACPI D3Cold settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ACPI D3Cold Support</td><td>Disabled,Enabled</td><td>Enable/Disable ACPI D3Cold support to be executed on D3 entry and exit\n\nNote: Disable it would affect the Storage D3 setting</td></tr><tr><td>VR Ramp up delay</td><td>Range 0 to 100Default 16</td><td>Delay between subsequent VR ramp ups if they are all Turn ON at the same time</td></tr><tr><td>PCIE Slot 5 Device Power-on delay in ms</td><td>Range 0 to 200Default 100</td><td>Delay between applying core power and Deasserting PERST#</td></tr><tr><td>Audio Delay</td><td>Range 0 to 1000Default 200</td><td>Delay after applying power to HD Audio (Realtek) codec device.</td></tr><tr><td>SensorHub</td><td>Range 0 to 1000Default 68</td><td>Delay after applying power to SensorHub device.</td></tr><tr><td>TouchPad</td><td>Range 0 to 1000Default 68</td><td>Delay after applying power to TouchPad device.</td></tr><tr><td>TouchPanel</td><td>Range 0 to 1000Default 68</td><td>Delay in PR_ON after applying power to TouchPanel device.</td></tr><tr><td>P-state Capping</td><td>DisableENABLE</td><td>Set_PPC and send ACPI notification</td></tr><tr><td>USB Port 1</td><td>High SpeedSuper SpeedDisable</td><td>USB RTD3 support. Super Speed: USB3.0 devices will be exposed as RTD3 capable. High Speed: USB2.0 devices will be exposed as RTD3 capable. Disabled: USB RTD3 support disabled.\n\n For SawtoothPeak USB Port1(Below) is Superspeed and Port2(Top) is HighSpeed. Check respective board configuration to know about USB port position.</td></tr><tr><td>USB Port 2</td><td>High SpeedSuper SpeedSuper Speed WWANDisable</td><td>USB RTD3 support. Super Speed: USB3.0 devices will be exposed as RTD3 capable. High Speed: USB2.0 devices will be exposed as RTD3 capable. Disabled: USB RTD3 support disabled.\n\n For SawtoothPeak USB Port1(Below) is Superspeed and Port2(Top) is HighSpeed. Check respective board configuration to know about USB port position.</td></tr><tr><td>ZPODD</td><td>DisableEnable</td><td>Zero Power ODD option is applicable only for the board with ZPODD support.</td></tr><tr><td>Sata Port 0</td><td>DisableEnable</td><td>Setup option to control the SATA port RTD3 functionality</td></tr><tr><td>Sata Port 1</td><td>DisableEnable</td><td>Setup option to control the SATA port RTD3 functionality</td></tr><tr><td>PCIe Remapped CR1</td><td>DisableEnable</td><td>PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.</td></tr><tr><td>PCIe Remapped CR2</td><td>DisableEnable</td><td>PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.</td></tr><tr><td>PCIe Remapped CR3</td><td>DisableEnable</td><td>PCIe RTD3 setup conflicts with SATA RTD3. Platform specific.</td></tr><tr><td>RTD3 Support for PCIE Rootports</td><td>DisableEnable</td><td>DisableEnable</td></tr></table>

7.3.5. Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Disabled, Enabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Disabled, Enabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State*</td><td>Suspend Disabled, S3(Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>LID Function</td><td>Disabled, Enabled</td><td>Enable/Disable LID Function</td></tr><tr><td>Sleep Function</td><td>Disabled, Enabled</td><td>Enable/Disable Sleep Button Function</td></tr><tr><td>ECO Mode*</td><td>Disabled, Enabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power-Up Mode*</td><td>Turn On, Remain Off, Last State</td><td>Turn On:</td></tr><tr><td colspan="3">ATTENTION: The Power-Up Mode only has effect when the module is in ATX-Mode.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td></td></tr></table>

7.3.5.1. Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info only</td><td></td></tr><tr><td>Main Current</td><td>Read only</td><td>Displays input current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Displays input power.</td></tr><tr><td>RTC</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>5VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design.</td></tr><tr><td>VIN</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3V</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VMEM</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr><tr><td>VCORE</td><td>Read only</td><td>Displays the sensed voltage based on hardware design</td></tr></table>

7.3.6. System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info only</td><td></td></tr><tr><td>SEMA Firmware Version</td><td>Info only</td><td></td></tr><tr><td>SEMA Flags</td><td>Submenu</td><td></td></tr><tr><td>SEMA Features</td><td>Info only</td><td></td></tr><tr><td>Uptime &amp; Power Cycles Counter</td><td>Read only</td><td></td></tr><tr><td>System Restart Event</td><td>Read only</td><td></td></tr><tr><td>4096 Bytes User-Flash</td><td>Read only</td><td></td></tr><tr><td>Runtime Watchdog</td><td>Read only</td><td></td></tr><tr><td>Temperatures</td><td>Read only</td><td></td></tr><tr><td>Voltage Monitor</td><td>Read only</td><td></td></tr><tr><td>Display Backlight Control</td><td>Read only</td><td></td></tr><tr><td>Power-up Watchdog</td><td>Read only</td><td></td></tr><tr><td>Power Monitor (Current Sense)</td><td>Read only</td><td></td></tr><tr><td>Boot Counter</td><td>Read only</td><td></td></tr><tr><td>Dual-BIOS</td><td>Read only</td><td></td></tr><tr><td>I2C Bus 1</td><td>Read only</td><td></td></tr><tr><td>I2C Bus 2</td><td>Read only</td><td></td></tr><tr><td>CPU Fan</td><td>Read only</td><td></td></tr><tr><td>System Fan 1</td><td>Read only</td><td></td></tr><tr><td>AT/ATX Mode</td><td>Read only</td><td></td></tr><tr><td>ACPI Thermal Trigger</td><td>Read only</td><td></td></tr><tr><td>Power-up to Last State</td><td>Read only</td><td></td></tr><tr><td>Backlight Restore</td><td>Read only</td><td></td></tr><tr><td>Ext - GPIO</td><td>Read only</td><td></td></tr><tr><td>I2C Bus 3</td><td>Read only</td><td></td></tr><tr><td>Other BMC</td><td>Read only</td><td></td></tr><tr><td>Error Log</td><td>Read only</td><td></td></tr><tr><td>Wake-by-BMC</td><td>Read only</td><td></td></tr><tr><td>Soft Fan</td><td>Read only</td><td></td></tr><tr><td>Parameter Memory</td><td>Read only</td><td></td></tr><tr><td>Ext-GPIO Input Interrupt Support</td><td>Read only</td><td></td></tr></table>

# 7.3.6.1. System Management > SEMA Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Flags</td><td>Info only</td><td></td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td></td></tr></table>

# 7.3.7. Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info Only</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled95 C98 C100 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled100C105C110C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Active Cooling Trip Point</td><td>40 C50 C60 C70 CRefer to BMC</td><td>This value is the temperature threshold of the active cooling trip point.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled</td></tr><tr><td>Temperature and Fan Speed</td><td>Submenu</td><td></td></tr></table>

7.3.7.1. Thermal Management-> Temperature and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current CPU Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Display Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Display Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Display Max Board Temperature</td></tr><tr><td>CPU Fan Speed</td><td>Info Only</td><td>Display CPU Fan Speed</td></tr><tr><td>Smart Fan</td><td>Submenu</td><td></td></tr></table>

7.3.7.2. Submenu: Thermal Management > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td>Info Only</td><td></td></tr><tr><td>CPU Smart FanTemperature Source</td><td>CPU SensorBoard Sensor</td><td>CPU Smart FanTemperature Source</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan)Fan OffFan On</td><td>Select CPU Fan control mode.</td></tr><tr><td>Trigger Point 1</td><td>Info-only</td><td></td></tr><tr><td>Trigger Temperature</td><td>40</td><td>Set the temperature value for trigger point 1 to control CPU fan.</td></tr><tr><td>PWM Level</td><td>30</td><td>When configured sensor reaches the trigger temperature value, set PWM level for this condition.</td></tr><tr><td>Trigger Point 2</td><td>Info-only</td><td></td></tr><tr><td>Trigger Temperature</td><td>50</td><td>Set the temperature value for trigger point 2 to control CPU fan.</td></tr><tr><td>PWM Level</td><td>40</td><td>When configured sensor reaches the trigger temperature value, set PWM level for this condition.</td></tr><tr><td>Trigger Point 3</td><td>Info-only</td><td></td></tr><tr><td>Trigger Temperature</td><td>60</td><td>Set the temperature value for trigger point 3 to control CPU fan.</td></tr><tr><td>PWM Level</td><td>63</td><td>When configured sensor reaches the trigger temperature value, set PWM level for this condition.</td></tr><tr><td>Trigger Point 4</td><td>Info-only</td><td></td></tr><tr><td>Trigger Temperature</td><td>70</td><td>Set the temperature value for trigger point 4 to control CPU fan.</td></tr><tr><td>PWM Level</td><td>100</td><td>When configured sensor reaches the trigger temperature value, set PWM level for this condition.</td></tr></table>

# 7.3.8. Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up watchdog</td><td>Disabled Enabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up. Press F12 during start up to disable the Power Up Watchdog.</td></tr><tr><td>ATTENTION: Pressing F12 during startup disables the Power Up Watchdog.</td><td>Info only</td><td></td></tr><tr><td>RunTime Watchdog</td><td>DisabledEnabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr></table>

7.3.9. USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attachment USB devices.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable / Disable USB Mass Storge Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.&#x27;Auto&#x27; uses default value: for a Root po\rt it is 100ms, for a Hub port the delay is taken form Hub descriptor.</td></tr></table>

7.3.10. AMI Graphics Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Intel(R) Graphics Controller</td></tr><tr><td colspan="3">Intel(R) GOP Driver [17.0.10xx]</td></tr><tr><td>Output Select</td><td>HDMI</td><td>Auto detect Output Interface</td></tr><tr><td>Output Select*</td><td>HDMI/DP/eDP</td><td>Manual select Output Interface</td></tr><tr><td>Brightness Setting</td><td>[ Max-Value, Min-Value, Step-Value, Step-Value] = [ 0xFFFFFFF, 0x00000000, 0x00000001, Brightness Setting]</td><td>Item shown when eDP detectedSet Gop Brightness value</td></tr><tr><td>BIST Enable</td><td>Disabled, Enabled</td><td>Item shown when eDP detectedStarts or stops the BIST on the integrated display panel.</td></tr></table>

7.3.11. Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>ITE5121 Super IO Configuration</td><td>submenu</td><td></td></tr><tr><td>Nct6126dSec Super IO Configuration</td><td>submenu</td><td></td></tr></table>

7.3.11.1. Super IO Configuration> ITE5121 Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IT5121E Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

7.3.11.2. Super IO Configuration> Nct6126dSec Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nct6126dSec Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

7.3.11.3. Super IO Configuration >ITE5121 Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=3F8h; IRQ=4</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr><tr><td>Change Settings</td><td>NormalHigh Speed</td><td>Select an optimal setting for Super IO Device.</td></tr></table>

7.3.11.4. Super IO Configuration >ITE5121 Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=2F8h; IRQ=3</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=2F8h; IRQ=3IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr></table>

7.3.11.5. Super IO Configuration > Nct6126dSec Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td rowspan="2">Serial Port</td><td>Disabled</td><td rowspan="2">Enable or Disable Serial Port (COM).</td></tr><tr><td>Enabled</td></tr><tr><td>Device Settings</td><td>IO=240h; IRQ=5</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>Auto</td><td>Select an optimal setting for Super IO device.</td></tr><tr><td></td><td>IO=240h; IRQ=10IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12IO=260h;IRQ=3,4,5,6,7,10,11,12IO=268h;IRQ=3,4,5,6,7,10,11,12</td><td></td></tr><tr><td>UART Mode</td><td>RS232RS485RS422</td><td>Change UART mode.</td></tr></table>

7.3.11.6. Super IO Configuration > Nct6126dSec Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=248h; IRQ=7</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=248h; IRQ=10IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12IO=260h;IRQ=3,4,5,6,7,10,11,12IO=268h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr><tr><td>UART Mode</td><td>RS232RS485RS422</td><td>Change UART mode.</td></tr></table>

# 7.3.12. Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>Disabled, Enabled</td><td>To enable or disable console redirection of COMx.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

# 7.3.12.1. Serial Port Console > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection..</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr></table>

# 7.3.13. Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info only</td><td></td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions (S3 &amp; S4 &amp; S5) to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. ATX: OS will turn off system power when shutdown.</td></tr><tr><td>I2C Speed Control</td><td>100 Kbps400 Kbps</td><td>I2C Speed Control</td></tr><tr><td>SMBUS Select Configuration</td><td>From ECFROM PCH</td><td>SMBUS select configuration from PCH or EC.</td></tr><tr><td>WOL From S5</td><td>OFFON</td><td>This Config to control power on/off LAN in S5 State by SEMA(EC)</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr><tr><td>EC SATA PCIE Select Configuration</td><td>SATAPCIE</td><td>EC SATA PCIE Select Configuration. 0: SATA / 1: PCIE.</td></tr></table>

7.3.14. Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>Ipv4 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv4 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>Ipv6 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>IPv6 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>0</td><td>Wait time in seconds to press ESC key to abort the PXE boot.Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>1</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

7.3.15. NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Seg:Bus:Dev:Func</td><td colspan="2">Info only</td></tr><tr><td>Model Number</td><td colspan="2">Info only</td></tr><tr><td>Total Size</td><td colspan="2">Info only</td></tr><tr><td>Vendor ID</td><td colspan="2">Info only</td></tr><tr><td>Device ID</td><td colspan="2">Info only</td></tr><tr><td>Namespace</td><td colspan="2">Info only</td></tr><tr><td>Self Test Option</td><td>Short Extended</td><td>Select either Short or Extended Self Test. Short option will take couple of minutes and extended option will take several minutes to complete.</td></tr><tr><td>Self Test Action</td><td>Controller Only Test Controller and NameSpace Test</td><td>Select either to test Controller alone or Controller and NameSpace. Selecting Controller and Namespace option will take lot longer to complete the test.</td></tr><tr><td>Run Device Self Test</td><td></td><td>Perform device self test for the corresponding Option and Action selected by user. Pressing the &#x27;Esc&#x27; key will abort the test. Result shown below is the recent result logged in the device.</td></tr></table>

7.3.16. Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable, Enable</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td colspan="3">NO Security Device Found</td></tr></table>

# 7.4. Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>submenu</td><td></td></tr></table>

7.4.1. Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>submenu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration</td><td>submenu</td><td>Graphics Configuration</td></tr><tr><td>TCSS setup menu</td><td>submenu</td><td>TCSS Configuration settings</td></tr><tr><td>VMD setup menu</td><td>submenu</td><td>VMD Configuration settings</td></tr><tr><td>VT-d setup menu</td><td>submenu</td><td>VT-d Configuration settings</td></tr><tr><td>Intel TXT Information</td><td>Info-only</td><td>Display Intel TXT information</td></tr><tr><td>GNA Device (B0:D8:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable SA GNA Device.</td></tr><tr><td>CRID Support</td><td>Enabled, Disabled</td><td>Enable/Disable SA CRID and TCSS CRID control for Intel SIPP</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enabled, Disabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB.</td></tr><tr><td>IPU Device (B0:D5:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU Device \nThis option will be grayed out when IPU is fused off from silicon.</td></tr><tr><td>NPU Device (B0:D11:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable NPU (Neural Processing Unit) Device.</td></tr><tr><td>MIPI Camera Enable</td><td>Enabled, Disabled</td><td>MIPI Camera Configuration</td></tr></table>

7.4.1.1. Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info-only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info-only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info-only</td><td></td></tr><tr><td>Controller x Channel x Slot x</td><td>Info-only</td><td></td></tr><tr><td>Size</td><td>Info-only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info-only</td><td></td></tr><tr><td>Manufacturer</td><td>Info-only</td><td></td></tr><tr><td>Memory Test on Warm Boot</td><td>Enabled, Disabled</td><td>Enable Or Disable Base Memory Test Run on Warm Boot</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067133314001600180018672000213322002400260026672800293330003200</td><td>Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller</td></tr><tr><td>Controller 0, Channel 0 DIMM Control</td><td>Enabled, Disabled</td><td>Controller 0, Channel 0 DIMM Control Support - Enable or Disable Dimms on Controller 0, Channel 0.</td></tr><tr><td>Controller 1, Channel 0 DIMM Control</td><td>Enabled, Disabled</td><td>Controller 1, Channel 0 DIMM Control Support - Enable or Disable Dimms on Controller 1, Channel 0.</td></tr><tr><td>In-Band ECC Support (Industrial SKU only)</td><td>Enabled, Disabled</td><td>Enable/Disable In-Band ECC. Either the IBECC or the TME can be enabled.</td></tr><tr><td>In-Band ECC Error Injection</td><td>Disabled, Enabled</td><td>By enabling this Error Injection feature, the user acknowledges the security risks</td></tr><tr><td>In-Band ECC Operation Mode</td><td>0, 1, 2</td><td>0: Functional Mode protects requests based on the address range, 1: Makes all requests non protected and ignore range checks, 2:Makes all requests protected and ignore range checks</td></tr></table>

7.4.1.2. Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>Disabled, Enabled</td><td>If Enabled, it will not scan for External Gfx Card on PEG and PCH PCIE Ports</td></tr><tr><td>Primary Display</td><td>Auto, IGFX, PEG Slot, PCH PCI, HG</td><td>Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select HG for Hybrid Gfx.</td></tr><tr><td>Select PCIE Card</td><td>Auto, Elk Creek 4, PEG Eval</td><td>Select the card used on the platform</td></tr><tr><td>Internal Graphics</td><td>Auto, Disabled, Enabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB, 4MB, 8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB, 256MB, 512MB, 1024MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M, 32M, 64M, 96M, 128M, 160M, 4M, 8M, 12M, 16M,20M, 24M, 28M, 32M/F7, 36M, 40M, 44M, 48M, 52M, 56M, 60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M, 256M, MAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>Intel Graphics Pei Display Peim</td><td>Enabled, Disabled</td><td>Enable/Disable Pei (Early) Display</td></tr></table>

7.4.1.3. Chipset > System Agent (SA) Configuration > TCSS setup menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IOM FW version</td><td>Info-only</td><td></td></tr><tr><td>PHY FW version</td><td>Info-only</td><td></td></tr><tr><td>TBT FW IMR Status</td><td>Info-only</td><td></td></tr><tr><td>TBT FW version</td><td>Info-only</td><td></td></tr><tr><td>Deepest TC state</td><td>Info-only</td><td></td></tr><tr><td>TCSS xHCI Support</td><td>Enabled, Disabled</td><td>Enable/Disable TCSS xHCI</td></tr><tr><td>TSCC USB Configuration</td><td>submenu</td><td>SA TCSS USB Configuration settings</td></tr><tr><td>ITBT PCIE0 Root Port</td><td>Enabled, Disabled</td><td>Enable/Disable ITBT PCIE ROOT</td></tr><tr><td>ITBT PCIE1 Root Port</td><td>Enabled, Disabled</td><td>Enable/Disable ITBT PCIE ROOT</td></tr><tr><td>ITBT PCIE2 Root Port</td><td>Enabled, Disabled</td><td>Enable/Disable ITBT PCIE ROOT</td></tr><tr><td>ITBT PCIE3 Root Port</td><td>Enabled, Disabled</td><td>Enable/Disable ITBT PCIE ROOT</td></tr><tr><td>ITBT DMA0</td><td>Disabled, Enabled</td><td>Enable/Disable ITBT DMA0</td></tr><tr><td>ITBT DMA1</td><td>Disabled, Enabled</td><td>Enable/Disable ITBT DMA1</td></tr><tr><td>VCCST status of IOM</td><td>Disabled, Enabled</td><td>Enables/Disables VCCST. \nEnable: Sends VCCST ON message to EC or PMC \nDisable: Sends VCCST OFF message to EC or PMC</td></tr><tr><td>D3 Cold Enable/Disable</td><td>Disabled, Enabled</td><td>Enables/Disables D3 Cold. \nEnable: D3 cold support for IOM is enabled \nDisable: D3 cold support for IOM is Disabled</td></tr><tr><td>D3 Hot</td><td>Disabled, Enabled</td><td>Enables/Disables D3 Hot. \nEnable: D3 Hot support for IOM is enabled \nDisable: D3 Hot support for IOM is Disabled</td></tr><tr><td>Tc C-State Limit</td><td>Disabled, 1,2,4,5,6,7,10,</td><td>BIOS mailbox to limit deepest TCx state</td></tr><tr><td>PCI Express Root Port 0</td><td>submenu</td><td></td></tr><tr><td>PCI Express Root Port 1</td><td>submenu</td><td>PCI Express Root Port Settings.</td></tr></table>

7.4.1.3.1 Chipset > System Agent (SA) Configuration > TCSS setup menu >TCSS USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB CONNECT OVERRIDE</td><td>DisabledEnabled</td><td>Option will allow VCCSTTPC to turn off even when there is a connection for a USB3 port.</td></tr><tr><td>TCSS xDCI Support</td><td>DisabledEnabled</td><td>Enable/Disable TCSS xDCI</td></tr><tr><td>TCSS CPU USB PDO Programming</td><td>Disabled, Enabled</td><td>Select &#x27;Enabled&#x27; if Port Disable Override functionality is used.</td></tr><tr><td>TCSS CPU USB Port Disable Override</td><td>DisabledEnabled</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr></table>

7.4.1.3.2 Chipset > System Agent (SA) Configuration > TCSS setup menu > PCI Express Root Port 0

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PTM</td><td>DisabledEnabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>LTR</td><td>DisabledEnabled</td><td>PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Enabled</td><td>Snoop Latency Override for SA PCIE.\nDisabled: Disable override.\nManual: Manually enter override values.\nAuto (default): Maintain default BIOS flow.</td></tr><tr><td>Snoop Latency Valu</td><td>0 to 1023200</td><td>LTR Snoop Latency value of SA PCIE</td></tr><tr><td>Snoop Latency Multiplier</td><td>1 ns32 ns1024 ns32678 ns1048576 ns33554432 ns</td><td>LTR Non Snoop Latency Multiplier of SA PCIE</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Enabled</td><td>Non Snoop Latency Override for SA PCIE.\nDisabled: Disable override.\nManual: Manually enter override values.\nAuto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Value</td><td>0 to 1023200</td><td>LTR Non Snoop Latency value of PCH PCIE</td></tr><tr><td>Non Snoop Latency Multiplier</td><td>1 ns32 ns1024 ns32678 ns1048576 ns33554432 ns</td><td>LTR Non Snoop Latency Multiplier of SA PCIE</td></tr><tr><td>Force LTR Override</td><td>Disabled, Enabled</td><td>Force LTR Override for ITBT PCIE.\nDisabled: LTR override values will not be forced.\nEnable: LTR override values will be forced and LTR messages from the device will be ignored.</td></tr><tr><td>LTR Lock</td><td>Disabled, Enabled</td><td>PCIE LTR Configuration Lock</td></tr></table>

7.4.1.3.3 Chipset > System Agent (SA) Configuration > TCSS setup menu > PCI Express Root Port 1

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PTM</td><td>DisabledEnabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>LTR</td><td>DisabledEnabled</td><td>PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Enabled</td><td>Snoop Latency Override for SA PCIE.\nDisabled: Disable override.\nManual: Manually enter override values.\nAuto (default): Maintain default BIOS flow.</td></tr><tr><td>Snoop Latency Valu</td><td>0 to 1023200</td><td>LTR Snoop Latency value of SA PCIE</td></tr><tr><td>Snoop Latency Multiplier</td><td>1 ns32 ns1024 ns32678 ns1048576 ns33554432 ns</td><td>LTR Non Snoop Latency Multiplier of SA PCIE</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Enabled</td><td>Non Snoop Latency Override for SA PCIE.\nDisabled: Disable override.\nManual: Manually enter override values.\nAuto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Value</td><td>0 to 1023200</td><td>LTR Non Snoop Latency value of PCH PCIE</td></tr><tr><td>Non Snoop Latency Multiplier</td><td>1 ns32 ns1024 ns32678 ns1048576 ns33554432 ns</td><td>LTR Non Snoop Latency Multiplier of SA PCIE</td></tr><tr><td>Force LTR Override</td><td>Disabled, Enabled</td><td>Force LTR Override for ITBT PCIE.\nDisabled: LTR override values will not be forced.\nEnable: LTR override values will be forced and LTR messages from the device will be ignored.</td></tr><tr><td>LTR Lock</td><td>Disabled, Enabled</td><td>PCIE LTR Configuration Lock</td></tr></table>

7.4.1.4. Chipset > System Agent (SA) Configuration > VMD Setup Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable VMD controller</td><td>Disabled, Enabled</td><td>Enable/Disable to VMD controller</td></tr></table>

7.4.1.5. Chipset > System Agent (SA) Configuration > VT-d setup menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Pre-boot DMA Protection</td><td>Disabled, Enabled</td><td>Enable DMA Protection in Pre-boot environment (If DMAR table is installed in DXE and If VTD_INFO_PPI is installed in PEI.)</td></tr><tr><td>DMA Control Guarantee</td><td>Disabled, Enabled</td><td>Enable/Disable DMA_CONTROL_GUARANTEE bit</td></tr></table>

7.4.2. Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>Security Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial I/O Configuration</td><td>Submenu</td><td></td></tr><tr><td>Thermal Throttling Control</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN Controller</td><td>Info-Only</td><td>No GbE Region</td></tr><tr><td>State After G3</td><td>S0 State S5 State</td><td>Specify what state to go to when power is re-applied after a power failure (G3 state)</td></tr><tr><td>Port 80h Redirection</td><td>LPC Bus PCIE Bus</td><td>Control where the Port 80h cycles are sent.</td></tr><tr><td>Enhance Port 80h LPC Decoding</td><td>Disabled, Enabled</td><td>Support the word/dword decoding of port 80h behind LPC</td></tr><tr><td>IOAPIC 24-119 Entries</td><td>Disabled, Enabled</td><td>Enables/Disables IOAPIC 24-119 Entries. IRQ24-119 may be used by PCH devices. Disabling those interrupts may cause certain devices failure.</td></tr><tr><td>Enable 8254 Clock Gate</td><td>Disabled, Enabled</td><td>Enables/Disables 8254 clock gate in early phase. Set 8254CGE is necessary for SLP_S0 support. Platform is albe to disable this policy and set 8254CGE in late phase.</td></tr><tr><td>Lock PCH Sideband Access</td><td>Disabled, Enabled</td><td>Lock PCH Sideband access, include SideBand interface lock and SideBand PortID mask for certain end point (e.g. PSFx). The option is invalid if POSTBOOT SAI is set.</td></tr><tr><td>Flash Protection Range Registers (FPRR)</td><td>Disabled, Enabled</td><td>Enable Flash Protection Range Registers</td></tr><tr><td>SPD Write Disable</td><td>TRUE,FALSE</td><td>Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr><tr><td>LGMR</td><td>Disabled,Enabled</td><td>64KB memory block for LGMR (LPC Memory Range Decode)</td></tr><tr><td>HOST_C10 reporting to Target</td><td>Disabled,Enabled</td><td>This option enables HOST_C10 reporting to Target via eSPI Virtual Wire</td></tr><tr><td>OS IDLE Mode</td><td>Disabled,Enabled</td><td>Enable/Disable OS Idle Mode Feature</td></tr><tr><td>S0ix Auto Demotion</td><td>Disabled,Enabled</td><td>Enable/Disable Host Low Power Mode S0ix Auto-Demotion</td></tr></table>

7.4.2.1. Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Port8xh Decode</td><td>Disabled, Enabled</td><td>PCI Express Port8xh Decode Enable/Disable.</td></tr><tr><td>Compliance Test Mode</td><td>Disabled, Enabled</td><td>Enable when using Compliance Load Board</td></tr><tr><td>PCIE clocks</td><td>All port aet to Platform-POR</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>PCIE Ports 1-4 Configuration</td><td>4x1 Port, 1x2 2x1 Port, 1x2 2x1 Port Reversed, 2x2 Port, 2x2 Port Reversed, 1x4 Port, 1x4 Port Reversed</td><td>Please make sure the system boots completed after changing the configuration. Do not attempt to Shut Down Your Computer, doing that may lead to system malfunction.</td></tr><tr><td>PCIE Ports 5-8 Configuration</td><td>4x1 Port, 1x2 2x1 Port, 1x2 2x1 Port Reversed, 2x2 Port, 2x2 Port Reversed, 1x4 Port, 1x4 Port Reversed</td><td>Please make sure the system boots completed after changing the configuration. Do Not Attempt to Shut Down Your Computer, doing that may lead to system malfunction.</td></tr><tr><td>PCI Express Root Port PXPA3</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPA4</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPB1</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPC</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPD</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPE</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPF</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr></table>

7.4.2.1.1 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPA3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled,Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual,Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.2 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPA4

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA4</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.3 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPB1

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPB1</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled,Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.4 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPC

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPC</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled,Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.5 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPD

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPD</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled,Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.6 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPE

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA4</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled,Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.7 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port PXPF

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPF</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1, L0sL1, Auto</td><td>Set the ASPM Level: Force L0s - Force all links to L0s state. AUTO - BIOS auto configure. DISABLE - Disables ASPM.</td></tr><tr><td>L1 Substates</td><td>Disabled, L1.1, L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>Disabled, Enabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>Disabled, Enabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>FOM Scoreboard Control Policy</td><td>Auto, Gen3, Gen4, Gen3/Gen4, Gen5</td><td>Select the FOM Scoreboard Control Policy, when set to Auto, speed is based on TLS</td></tr><tr><td>URR</td><td>Disabled, Enabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled, Enabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled, Enabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled, Enabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled,Enabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled, Enabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled, Enabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Timeout</td><td>0 to 655350</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>Disabled, Enabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>LTR</td><td>Disabled, Enabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled, Manual, Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>P2P Support</td><td>Disabled, Enabled</td><td>Program P2P Support Registers according to setup option</td></tr><tr><td>PCIe EQ override</td><td>Disabled, Enabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.2. Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Disabled,Enabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Controller Speed</td><td>Default,Gen1,Gen2,Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Test Mode</td><td>Disabled,Enabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Aggressive LPM Support</td><td>Disabled,Enabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>Port 0</td><td>Disabled,Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>External</td><td>Disabled,Enabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>Disabled,Enabled</td><td>If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive,Solid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>Unknown,ISATA,Direct Connect,Flex,M2</td><td>Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2</td></tr><tr><td>SATA Port 0 DevSlp</td><td>Disabled,Enabled</td><td>Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>DITO Configuration</td><td>Disabled,Enabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>Port 1</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>External</td><td>Disabled, Enabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>Disabled, Enabled</td><td>If enabled for any of ports Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise, all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive, Solid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>Unknown, ISATA, Direct Connect, Flex, M2</td><td>Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2</td></tr><tr><td>SATA Port 0 DevSlp</td><td>Disabled, Enabled</td><td>Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>DITO Configuration</td><td>Disabled, Enabled</td><td>Enable/Disable DITO Configuration</td></tr></table>

7.4.2.3. Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xDCI Support</td><td>Disabled, Enabled</td><td>Enable/Disable xDCI (USB OTG Device)</td></tr><tr><td>USB PDO Programming</td><td>Disabled, Enabled</td><td>Select 'Enabled' if Port Disable Override functionality is used.</td></tr><tr><td>USB Overcurrent</td><td>Disabled, Enabled</td><td>Select 'Disabled' for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>Disabled, Enabled</td><td>Select 'Enabled' if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Audio Offload</td><td>Disabled,Enabled</td><td>Enable/Disable USB Audio Offload functionality</td></tr><tr><td>Enable HSII on xHCI</td><td>Disabled, Enabled</td><td>Enable/Disable HSII feature. It may lead to increased power consumption.</td></tr><tr><td>USB3.1 Port 0 Speed Selection</td><td>Gen2, Gen1</td><td>USB3.1 Speed selection; Gen1 or Gen2</td></tr><tr><td>USB3.1 Port 1 Speed Selection</td><td>Gen2, Gen1</td><td>USB3.1 Speed selection; Gen1 or Gen2</td></tr><tr><td>USB Port Disable Override</td><td>Disabled, Enabled</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB SW Device Mode Port #0</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #1</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #2</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #3</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #4</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #5</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #6</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #7</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #8</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #9</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr></table>

7.4.2.4. Chipset > PCH-IO Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Memory Lock</td><td>Disabled, Enabled</td><td>Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>Disabled, Enabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr><tr><td>Force unlock on all GPIO pads</td><td>Disabled, Enabled</td><td>If Enabled BIOS will force all GPIO pads to be in unlocked state</td></tr></table>

7.4.2.5. Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>Disabled,Enabled</td><td>Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled.</td></tr></table>

7.4.2.6. Chipset > PCH-IO Configuration > Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other:I2C0 and I2C1,2,3UART0 and UART1,SPI0,1UART2 and I2C4,5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>I2C1 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other:I2C0 and I2C1,2,3UART0 and UART1,SPI0,1UART2 and I2C4,4 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>I2C3 Controller</td><td>Disabled,Enabled</td><td>I3C cannot be enabled if I2C#3 is enabled due to an ITSS requirement that there are at most 4 unique IRQs per Device, whereas D21 has 5 functions</td></tr><tr><td>I2C4 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller For I2C5 and UART2 to work this device has to be enabled</td></tr><tr><td>I2C5 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller For this device to work I2C4 has to be enabled</td></tr><tr><td>SPI0 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other: I2C0 and I2C1,2,3UART0 and UART1, SPI0,1UART2 and I2C4,5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>SPI1 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other: I2C0 and I2C1,2,3UART0 and UART1, SPI0,1UART2 and I2C4.5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>SPI2 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other: I2C0 and I2C1,2,3UART0 and UART1, SPI0,1UART2 and I2C4;5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>UART0 Controller</td><td>Disabled,Enabled</td><td>Set UART0 mode - DBG used for BIOS log print and/or Kernel OS Debug - COM - 16550 compatible serial port with Power Gating support</td></tr><tr><td>UART1 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other: I2C0 and I2C1,2,3UART0 and UART1, SPI0,1UART2 and I2C1,5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>UART2 Controller</td><td>Disabled,Enabled</td><td>Enables/Disables Serial I/O Controller If given device is Function 0 PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible. This is needed to allow PCI enumerator access functions above 0 in a multifunction device. The following devices depend on each other: I2C0 and I2C1,2,3UART0 and UART1, SPI0,1UART2 and I2C1;5 UART 0 (00:30:00) cannot be disabled when:1. Child device is enabled like CNVi Bluetooth (\_SB.PC00.UA00.BTH0) UART 0 (00:30:00) cannot be enabled when:1. I2S Audio codec is enabled (\_SB.PC00.I2C0.HDAC)</td></tr><tr><td>GPIO IRQ Route</td><td>IRQ 14IRQ 15</td><td>Route all GPIOs to one of the IRQ.</td></tr><tr><td>WITT/MITT I2C Test Device</td><td>Disabled, Enabled</td><td>Enable/Disable I2C WITT Test Device</td></tr><tr><td>WITT/MITT I3C Test Device</td><td>Disabled, Enabled</td><td>Enable/Disable I3C WITT Test Device</td></tr><tr><td>WITT/MITT SPI Test Device</td><td>Disabled, Enabled</td><td>Enable/Disable SPI WITT Test Device</td></tr><tr><td>UART Test Device</td><td>Disabled, Enabled</td><td>Choose if UART Test Device is used and with which controller</td></tr><tr><td>Additional Serial IO devices</td><td>Disabled, Enabled</td><td>When enabled, ACPI will report additional devices connected to Serial IO.</td></tr><tr><td>SerialIO timing parameters</td><td>Disabled, Enabled</td><td>Enables additional timing parameters for all Serial IO controllers. Defaults can be changed in each controller setting. Platform restart required to apply changes</td></tr></table>

7.4.2.7. Chipset > PCH-IO Configuration > Thermal Throttling Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SOC Thermal Throttling Level</td><td>Suggested Setting, Manual</td><td>Determine if use Intel suggested setting</td></tr><tr><td>IOE Thermal Throttling Level</td><td>Suggested Setting, Manual</td><td>Determine if use Intel suggested setting</td></tr><tr><td>SATA Thermal Setting</td><td>Suggested Setting, Manual</td><td>Determine if use Intel suggested setting</td></tr></table>

# 7.5. Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Set Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Set User Password</td></tr><tr><td>HDD Security Configuration</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>submenu</td><td></td></tr></table>

# 7.5.1. Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Disabled Enabled</td><td>The Secure Boot feature is Active if Secure Boot is Enabled, the Platform Key(PK) is enrolled, and the system is in User mode. The mode change requires platform reset</td></tr><tr><td>Secure Boot Mode</td><td>Standard Custom</td><td>The Secure Boot mode options: Standard or Custom. In Custom mode, the Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr><tr><td>Restore Factory Keys</td><td>Info only</td><td>Force System to User Mode. Install factory default Secure Boot key databases</td></tr><tr><td>Reset To Setup Mode</td><td>Info only</td><td></td></tr><tr><td>Key Management</td><td></td><td>Enables expert users to modify Secure Boot Policy variables without full authentication</td></tr></table>

# 7.6. Boot

7.6.1. Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot option.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll Sata Devices</td><td>If Last Boot SATA Devices Only, Only last boot SATA device will be available in Post. If All SATA Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>NVME Support</td><td>DisabledEnabled</td><td>If disabled, NVMe device will be skipped.</td></tr><tr><td>VGA Support</td><td>AutoEFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. EFI driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>DisabledFull InitialPartial Initial</td><td>If disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>DisabledEnabled</td><td>If disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>DisabledEnabled</td><td>If Disabled, NetWork Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>DisabledEnabled</td><td>If disable, Redirection function will be disabled.</td></tr></table>

# 7.7. Save & Exit

# 7.7.1. Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Option</td><td>Info only</td><td></td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Changes</td><td></td><td>Save changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr></table>

7.7.2. Default Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Default Options</td><td>Info only</td><td></td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

# 8. BIOS Checkpoints, Beep Codes

This section of the document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core and do not include any chipset or board specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the tasks the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized and are generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

Security (SEC) – initial low-level initialization
Pre-EFI Initialization (PEI)– memory initialization1
• Driver Execution Environment (DXE) – main hardware initialization2
• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, …)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a POST Card or POST Diagnostic Card. These are PCI addin cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

1 Analogous to “bootblock” functionality of legacy BIOS
2 Analogous to “POST” functionality in legacy BIOS

# 8.1. Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0F</td><td>SEC execution</td></tr><tr><td>0x10 – 0x2F</td><td>PEI CAR execution</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0xCF</td><td>DXE execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2. Standard Status Codes

# 8.2.1. SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr></table>

<table><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2. SEC Beep Codes

None

8.2.3. PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12 – 0x14</td><td>Reserved for CPU</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16 – 0x18</td><td>Reserved for North Bridge</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A – 0x1C</td><td>Reserved for South Bridge</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38 – 0x3A</td><td>Reserved for North Bridge initialization</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C -0x3E</td><td>Reserved for South Bridge</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB - 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4. PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5. DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64 – 0x67</td><td>Reserved for CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B – 0x6F</td><td>Reserved for North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73 – 0x77</td><td>Reserved for South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

8.2.6. DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met (out of resource)</td></tr></table>

8.2.7. ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

8.3. OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

# 9. Software Support

# 9.1. Windows

Windows 10 IoT Enterprise 2021 LTSC Windows 11 IoT Enterprise 2024 LTSC (2H’ 24)

# 9.2. Ubuntu 24.04. LTS

Kernel version

# 9.3. Yocto Linux 64-bit

https://github.com/ADLINK/meta-adlink-x86-64bit (TBC)

# 9.4. SEMA API

# 10. Mechanical and Thermal

All dimensions are shown in millimeters with a tolerance of ± 0.25mm unless otherwise noted. The tolerances on the module connector locating peg holes (dimesions [16.50, 6.00]&[16.50,18.00])should be ± 0.10mm.

# 10.1. Module Dimensions

![95 80 74.2 16.5 4\n4\nconnector on bottom side\n37.7\n51.7\nTop View\nTop\n91 91 95\n91 77.49 16.5 4\nSide View\n5.2\n4\n2](.cexpress-mtl-50m-72221-1010-11/5440b5d30972284c24a8e26e1599fe65ecd70256d137f1d72d7c205e7d984a6b.jpg)

Figure 5 – Module mechanical dimensions

# 10.2. Height of Processor and Static Compressive Load

# Processor Height Tolerance

The tolerance of the processor height is one of the key factors to consider when designing your thermal solution, as illustrated below. Please contact our ADLINK representative for further details.

![Die\nDie\nSubstrate\nModule PCB\nh](.cexpress-mtl-50m-72221-1010-11/88c5f8ffe422f1eebfcc6692088d251dc07b34c24d51c66947bb673cd5ddacdc.jpg)

<table><tr><td></td><td>Typical</td><td>Tolerance</td></tr><tr><td>h</td><td>1.25 mm</td><td>+/- 0.1mm</td></tr></table>

# Static Compressive Load

Another key factor to consider is the static compressive load. The cExpress-MTL module exhibits a processor maximum pressure die of 40 lbf.

# 10.3. Thermal Solutions

# 10.3.1. Heatspreader: HTS

Dimensions: mm

![The image displays a technical schematic of a mechanical assembly presented in six distinct views.\n\n*   **Top Left:** A side profile view showing a base plate with components mounted on top, labeled with vertical dimensions '11' and '5'.\n*   **Top Center:** An isometric view of the assembled unit featuring a central yellow module with a dark screen, surrounded by cylindrical standoffs. Text reads 'M2.5*6pcs'.\n*   **Top Right:** An isometric view of a separate square base plate with mounting holes.\n*   **Bottom Left:** A top-down view of a square plate with a dimension of '95' on both the vertical and horizontal axes.\n*   **Bottom Center:** A side profile view showing the thin edge of the assembly.\n*   **Bottom Right:** A front view showing the yellow module and a black rectangular component. Dimensions are labeled: '76' (top horizontal), '87' (left vertical), and '87' (bottom horizontal).](.cexpress-mtl-50m-72221-1010-11/4c2f2262903ec8d5ececb37c66f8163c7f762fd6bd99b3086f610512dbf46f28.jpg)
Figure 6 – Heatspreader: HTS

# 10.3.2. Heatsink: THS

Dimensions: mm

![This image is a technical drawing of a square heat sink assembly, presented in six distinct views arranged in two rows.\n\n**Top Row:**\n*   **Left:** A side profile view showing the assembly's thickness. Vertical dimension is labeled **17**, and the width of the top component is labeled **5**.\n*   **Center:** An isometric view showing the base plate, side fins, and a central yellow module with a dark grey inset. Four mounting posts are visible. A label points to the screws reading **M2.5*6pcs**.\n*   **Right:** A top-down isometric view highlighting the dense array of vertical cooling fins.\n\n**Bottom Row:**\n*   **Left:** A front view of the fin array. The view is square with mounting holes in the corners. Vertical dimension is **95** and horizontal width is **95**.\n*   **Center:** A thin side profile view.\n*   **Right:** A rear view showing the back of the plate. It features a central yellow module with a dark grey rectangle and a black rectangular component to the left. Vertical height is **87**, bottom width is **87**, and an upper horizontal width is **76**.](.cexpress-mtl-50m-72221-1010-11/b0b7bed8d9fe93b54b04689ce54d0c7d79a12da9e4fa809b304880886a87d47e.jpg)
Figure 7 – Heatsink: THS

Dimensions: mm

# 10.3.3. Heatsink with Fan: THSF

![The image displays technical drawings and specifications for a computer cooling assembly, presented in six views:\n\n**Top Row:**\n*   **Left:** A side profile of the heatsink and fan. Dimensions indicate a total height of **36** and a fan thickness of **5**.\n*   **Center:** An isometric view of the top mounting plate. A label reads '**M2.5*6pcs**' pointing to the mounting posts.\n*   **Right:** An isometric view showing the black fan mounted on the heatsink fins.\n\n**Bottom Row:**\n*   **Left:** A front view of the cooler with the fan attached. It is square-shaped with dimensions of **95** in height and **95** in width. A dimension line indicates a cable length of **300**.\n*   **Center:** A thin side profile view showing the cable exit point.\n*   **Right:** A rear view of the heatsink showing the mounting plate structure. Dimensions marked are **76** (top width between holes), **87** (total height), and **87** (bottom width).](.cexpress-mtl-50m-72221-1010-11/78364982f373fa0dde5c3e4bf4df62c3459236b092f2dbd322fb116eb7435918.jpg)
Figure 8 – Heatsink with fan: THSF

# 10.3.4. Heatsink High Profile: THSH

Dimensions: mm

![Cross-sectional diagram of a microchip or integrated circuit with pin array and labeled dimensions (36 and 5 units)](.cexpress-mtl-50m-72221-1010-11/abe8975f39e6e8e5bc51906395d5480eb6f57a788b48354f0cc1b68bc32bcf52.jpg)

![3D technical diagram of a heat sink with a yellow component and labeled M2.5*6pcs (no readable text or symbols beyond label)](.cexpress-mtl-50m-72221-1010-11/f08232d046312494551ecdc2237956af4e7dd17506c058ee09c0aab4c4dc8c62.jpg)

![3D rendering of a heat sink with parallel ribbed heat exchangers (no text or symbols)](.cexpress-mtl-50m-72221-1010-11/53c97e1b78fdf3ef11021d3d889cbf83bac7e0b10abe67a8b8572ed486023370.jpg)

![Pure geometric pattern with vertical stripes and dimension labels (95), no text or symbols present](.cexpress-mtl-50m-72221-1010-11/a3fd11d560c495dd7fbdd0917bbf256020a99482d3b02db99ed20dfe8663316c.jpg)

![Pure diagram of a vertical panel or enclosure with no text, numbers, or symbols visible](.cexpress-mtl-50m-72221-1010-11/9bd27148b0e936a93b2bb07ce54278db57ed7dee537a5a9450e99ae4a74da45a.jpg)

![76\n87\n87](.cexpress-mtl-50m-72221-1010-11/217f0dbf7b4031d1b4bf7c2dfc7901d8fff72138da06185abee6416636aea995.jpg)

Figure 9 – Heatsink high profile: THSH

# 10.4. Board to Board Connectors

To accommodate different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When using 5-mm receptacles, the carrier board should be free of components.

Tyco 3-1827253-6, Tyco 2357787-1

ept 401-51101-51, ept 401-51103-51

Foxconn QT002206-2141-3H, Foxconn QT5GB26-44703-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
• This connector can be used with 5-mm through-hole standoffs (SMT type).

Tyco 3-6318491-6, Tyco 2357798-1

ept 401-55101-51, ept 401-55103-51

Foxconn QT002206-4141-3H, Foxconn QT5GB26-74703-3H

• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
• This connector can be used with 8-mm through-hole standoffs (SMT type).

Common Specifications

<table><tr><td>Current capacity: 0.5A per pin</td><td>UL certification (ECBT2.E28476)</td></tr><tr><td>Rated voltage: 50V AC</td><td>Copper alloy (contacts)</td></tr><tr><td>Insulation resistance: 100M or greater @ 500 VDC</td><td>Housing: thermo-plastic molded compound (L.C.P.)</td></tr><tr><td>Temperature rating: -40°C to 85°C</td><td></td></tr></table>

# 10.5. Mounting Method

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the 5-mm or 8-mm board-to-board connectors, there are also top and bottom mounting. In top mounting, the threaded standoffs are on the carrier board, and the thermal solution is attached with through-hole standoffs. In bottom mounting, the threaded standoffs are on the thermal solution, and the carrier board has through-hole standoffs.

<table><tr><td>Top Mounting with 5 mm connectors
M2.5: 18 mm with spring / washer
2 mm heatsprader with 9 mm through-hole standoffs
COM Express Module ~ 2 mm
5 mm threaded standoff (DIP)
Carrier Board ~ 2 mm</td><td>Bottom Mounting with 5 mm connectors
2 mm heatsprader with 9 mm threaded standoffs
COM Express Module ~ 2 mm
5 mm through hole standoff (SMT)
Carrier Board ~ 2 mm
M2.5: 14 mm with spring / washer</td></tr><tr><td>Top Mounting with 8 mm connectors
M2.5: 18 mm with spring / washer
2 mm heatsprader with 9 mm through-hole standoffs
COM Express Module ~ 2 mm
8 mm threaded standoff (DIP)
Carrier Board ~ 2 mm</td><td>Bottom Mounting with 8 mm connectors
2 mm heatsprader with 9 mm threaded standoffs
COM Express Module ~ 2 mm
8 mm through hole standoff (SMT)
Carrier Board ~ 2 mm
M2.5: 16 mm with spring / washer</td></tr></table>

# 10.6. Standoff Types

The standoffs available for top and bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

5mm through-hole standoff (SMT type) P/N: 33-72000-0050
![Ø5.5\nØ2,8\n7\n5\n4.1](.cexpress-mtl-50m-72221-1010-11/19923274df97042636f8a8e6c96f78196be9fada9b4f2d44ee0f721aeb6578dd.jpg)

5mm threaded standoff (DIP type) P/N: 33-72016-0050
![M2.5\nØ5.5\n7\n5\n4.1](.cexpress-mtl-50m-72221-1010-11/d51c0b76d856143601ec769321d7376e56e1518f8d1f19c9011269f30bc272e6.jpg)

8mm through-hole standoff (SMT type) P/N: 33-72000-0080
![φ5.5\nφ2,6\n9.6\n8\n4.1](.cexpress-mtl-50m-72221-1010-11/6432615b3f72cf601f61c67810affae48d15b934e2a137638450e7bb66dbb2b5.jpg)

8mm threaded standoff (DIP type) P/N: 33-72015-0050
![M2.5\nØ5.5\n10\n8\n5,7\n4.1](.cexpress-mtl-50m-72221-1010-11/38a27e8095a9f092b9cf7f43c7e32dc7a135378bc988fb75d28d3bc937737379.jpg)

# 10.7. Installation

Install a heatspreader or heatsink using the following instructions. The images below are for illustration purposes only.

Step 1: Remove the protective membranes from the thermal pads.

![Close-up of a microfluidic chip with green liquid and translucent film, being handled by tweezers (no text or symbols visible)](.cexpress-mtl-50m-72221-1010-11/913001e0132020ee76831f5717208e5a8bb360fc8421293f9f37d74ba206f8d2.jpg)

![This is a red line-art icon depicting a piece of paper or a document. The shape features a folded corner (dog-ear) on the top right side. Inside the document outline, there are two horizontal lines centered vertically, representing text.](.cexpress-mtl-50m-72221-1010-11/29e7256a60f0ce209fa4aa88c0fe9e38b5b039a006e90d9e2af9c13edb05e3b3.jpg)

Note: All thermal pads have a protective membrane, depending on the module.

Step 2: Assemble the heatsink onto the COM Express module. Use the 3x M2.5, L=6mm screws provided to fasten the heatsink to the module. The number of screw holes and screws may vary by module.

![DEV-005098\nS/N\n2451 100W/100W\nE2P86M,16A/16A/16B\n51-12221-0410\nC E84671 NIS K\nNAM-4-3 13.3%\nD01\nARM-4H50\nDT-2-2000\nTZ 17\n13.3.9](.cexpress-mtl-50m-72221-1010-11/8b7c5ebb01c3902df4d9d273836204018d58393cfc42488d78cb428734553c8f.jpg)

![Two identical metal carriage bolts stand vertically side-by-side against a plain white background. Each bolt features a flat, slotted head at the top, followed by a stack of four square sections, and terminates in a threaded rod at the bottom. There is no text present in the image.](.cexpress-mtl-50m-72221-1010-11/472857dc445db94815df2423036648dc484e565ccf3ff263a27dd6acb1077aab.jpg)

Step 3: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown below. Press down on the module until the module is securely seated on the carrier board.

![Close-up of hands holding a cooling fan on a green printed circuit board (no visible text or symbols)](.cexpress-mtl-50m-72221-1010-11/423d86d87c99006adadaa535c6973a2e72d239e05c79e520f3744af3b5347d69.jpg)

Step 4: Use the 5x M2.5 (L=16mm) screws provided to secure the COM Express module to the carrier board from the solder side.

The number of screw holes and screws are module and carrier board design dependent.

![Close-up of a green printed circuit board with soldering tool, showing solder points and traces (no readable text or symbols)](.cexpress-mtl-50m-72221-1010-11/be42a2f076619e31db9e9ed1092d6a1645bf6617243e6f8c525fe0e0cd819442.jpg)

![The image features six silver hexagonal bolts arranged in a diagonal row, slanting upwards from left to right against a plain white background.](.cexpress-mtl-50m-72221-1010-11/29def7c71613a5e1d79044fedbcdc2e9663e66695c25e972089caf75da073bef.jpg)

Step 5: If you are installing a heatsink with a fan, plug the fan connector into the carrier board.

The location of the FAN connector for the COM Express module depends on carrier board design.

![Close-up of hands installing a circuit board with a fan component and a CPU fan blade (no visible text or symbols)](.cexpress-mtl-50m-72221-1010-11/f3fab12753f3cd49e56418031022d0805e49ec7af6121605ea4368c699ef72dc.jpg)
[🔗 Link to the original document](.cexpress-mtl-50m-72221-1010-11/cexpress-mtl-50m-72221-1010-11.pdf)