# cExpress-WL User's Manual

COM Express Compact Size Type 6 Module with Quad-Core Mobile 8th Gen Intel® Core™ and Celeron® Processors

![Close-up of a green printed circuit board with visible components and gold contacts (no readable text or symbols)](.cexpress-wl-50m-00029-1020-12/75f8779ffb1f91a763a0136f4f33f7b8a7608c859e68f30107566fb97e8817a4.jpg)

![COM\nExpress®](.cexpress-wl-50m-00029-1020-12/d2b0e1723b71ebe2365ee74c94529b48a6675829b11f2c0c8d02154afb17430f.jpg)

Manual Rev.: 1.2

Revision Date: June 24, 2021

Part Number: 50M-00029-1020

# Preface

# Copyright

Copyright © 2019, 2020, 2021 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.cexpress-wl-50m-00029-1020-12/2ade5a70f5b23828b03dc0abd3b1eb00a2e81869de2fcd31559041420e15b33d.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin with crossed lines indicating no waste or prohibition (no text or symbols)](.cexpress-wl-50m-00029-1020-12/fb1845b7eb408e5e7a192a22b33dd8dae39b9633cf1e94fed6fdbafc4bfa653d.jpg)

![Li-ion](.cexpress-wl-50m-00029-1020-12/a7a4d10c7209bb4c83461d103fb3e8625d4b878cb9b3777ca947c7426e189c29.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cexpress-wl-50m-00029-1020-12/b72f22c19cfd0b3a26011cf1c9f182e1ebd335553fa2308ed7331da9691d1cc3.jpg)

![廢電池請回收](.cexpress-wl-50m-00029-1020-12/b95403eba75bec0552d5ea8fc6f911dcc6b84c90c51dd3b61f974c2bca7e61b0.jpg)

# California Proposition 65 Warning

![The image displays a standard triangular warning sign. It features a yellow background enclosed by a thick black border. In the center is a large, black exclamation mark. There is no text present.](.cexpress-wl-50m-00029-1020-12/3b279bea9ce3dfb6f0463d0564d871a8f7591f452b805dad97e06855f38aeb6f.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2019-07-30</td><td>JC</td></tr><tr><td>1.1</td><td>Update specifications, mechanical info</td><td>2020-10-06</td><td>JC</td></tr><tr><td>1.2</td><td>Add comments for GBE0 ACT/LINK pins (A8/B2)</td><td>2021-06-24</td><td>JC</td></tr></table>

# Table of Contents

# Preface....ii

# List of Figures ......v

# List of Tables......vi

# 1. Introduction......1

# 2. Specifications ....3

2.1. Core System 3

2.2. Expansion Busses....3

2.3. Video....4

2.4. Audio....4

2.5. LAN 4

2.6. Multi I/O and Storage 5

2.7. Serial I/O on Module 5

2.8. Trusted Platform Module (TPM)....5

2.9. SEMA Board Controller....5

2.10. Debug 6

2.11. Power Specifications....6

2.12. Power Consumption....6

2.13. Operating Temperatures....6

2.14.Environmental....6

2.15. Specification Compliance....7

2.16. Operating Systems....7

2.17. Functional Diagram....8

2.18. Mechanical Drawing....9

# 3. Pinouts and Signal Descriptions....11

3.1. AB/CD Pin Definitions 11

3.2. Signal Description Terminology .... 14

3.3. AB Signal Descriptions....15

3.4. CD Signal Descriptions 27

# 4. Connector Pinouts on Module....35

4.1. Connector, Switch and LED Locations....35

4.2. 40-pin Debug Connector....37

4.3. Status LEDs 38

4.4. Fan Connector 39

4.5. BIOS Setup Defaults Reset Button 40

4.6. Switch Settings 41

# 5. Smart Embedded Management Agent (SEMA) 43

5.1. Board Specific SEMA Functions 44

# 6. System Resources ....47

6.1. System Memory Map 47

6.2. I/O Map 47
6.3. Interrupt Request (IRQ) Lines 49
6.4. PCI Configuration Space Map....50
6.5. PCI Interrupt Routing Map .... 51
6.6. SMBus Address Table 51

# 7. BIOS Setup....53

7.1. Menu Structure....53
7.2. Main 54
7.3. Advanced 56
7.4. Chipset....68
7.5. Security 75
7.6. Boot....76
7.7. Save & Exit 77

# 8. BIOS Checkpoints, Beep Codes....79

8.1. Status Code Ranges....80
8.2. Standard Status Codes....80
8.3. OEM-Reserved Checkpoint Ranges 87

# 9. Mechanical Information......89

9.1. Board-to-Board Connectors 89
9.2. Thermal Solution....90
9.3. Mounting Methods....93
9.4. Standoff Types....94

# Safety Instructions....95

# Getting Service....96

# List of Figures

Figure 1: cExpress-WL Functional Block Diagram....8
Figure 2: cExpress-WL Mechanical Drawing ....9
Figure 3: cExpress-WL Connector, Switch and LED Locations.... 36
Figure 4: Compact Size COM Express Module and DB40 Debug Module.... 36
Figure 5: cExpress-WL Switch Locations....41
Figure 6: COM Express Mounting Methods....93
Figure 7: COM Express Standoff Types....94

# List of Tables

Table 1: cExpress-WL AB/CD Pin Definitions.... 11

Table 2: 40-pin Debug Connector Pin Definition.... 37

Table 3: cExpress-WL LED Descriptions ...... 38

Table 4: Fan Connector Pin Definition ...... 39

Table 6: BIOS Select and Mode Configuration Switch Settings.... 42

Table 7: SEMA Onboard Voltage Monitor 44

Table 8: SEMA BMC Status 45

Table 9: SEMA Exception Codes....46

Table 10: SEMA BMC Flags....46

# 1. Introduction

The cExpress-WL is the first COM Express® COM.0 R3.0 Compact Size Type 6 module supporting the ultra-low-power quad-core 64-bit $8^{\text{th}}$ Generation Intel® Core™ i7/i5 processors and dual-core Intel® Core™ i3, Celeron® processors (formerly "Whiskey Lake U"). The quad-core processors support up to 8 threads (Intel® Hyper-Threading Technology) as well as an impressive turbo boost of up to 4.4GHz. These combined features make the cExpress-WL well suited to customers who need uncompromising system performance and responsiveness in a long product life solution. The cExpress-WL is equipped with up to two SODIMM sockets with a maximum 64GB DDR4 2400MHz non-ECC memory capacity to match the processors performance boost.

Integrated Intel Gen 9 LP Graphics includes features such as OpenGL 4.5, DirectX 12/11, OpenCL 2.1/2.0/1.2, Intel® Clear Video HD Technology, and DirectX Video Acceleration (DXVA) support for full H.265/HEVC 10-bit, MPEG2, VP9 hardware codecs. In addition, High Dynamic Range is supported for enhanced picture color and quality and digital content protection has been upgraded to HDCP 2.2. Graphics outputs include LVDS and three DDI ports supporting HDMI/DVI/DisplayPort and eDP/VGA as a build option. Maximum supported display resolutions are two 4K and one 1080p displays.

Input/output features include eight PCIe Gen3 lanes that can be used for NVMe SSD, allowing applications access to the highest speed storage solutions, as well as a single onboard Gigabit Ethernet port, four USB 3.1 Gen2 ports, four USB 2.0 ports, and up to three SATA 6 Gb/s ports. Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer.

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# 2. Specifications

# 2.1. Core System

<table><tr><td>CPU</td><td>8th Gen Intel® CoreTM and and Intel®Celeron® Processor (formerly “Whiskey Lake U”)Intel® CoreTM i7-8665UE, 1.7(4.4)GHz, 8MB, 15W (25W-12.5W cTDP), 4C/GT2Intel® CoreTM i5-8365UE, 1.6(4.1)GHz, 6MB, 15W (25W-12.5W cTDP), 4C/GT2Intel® CoreTM i3-8145UE, 2.2(3.9)GHz, 4MB, 15W (25W-12.5W cTDP), 2C/GT2Intel® Celeron® 4305UE, 2.0GHz, 2MB, 15W, 2C/GT1Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.0, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure Key, Intel® TSXNI (availability of features may vary between processor SKUs)</td></tr><tr><td>Cache</td><td>8MB for CoreTM i7, 6MB for CoreTM i5, 4MB for CoreTM i3, 2MB for Celeron®</td></tr><tr><td>Memory</td><td>Up to 64GB 2133/2400 MHz DDR4 in two SODIMM socketsMaximum 32GB per socket</td></tr><tr><td>Embedded BIOS</td><td>AMI Aptio V UEFI with CMOS backup in 32 (or 16) MB SPI BIOS with Intel® AMT 11.0 support</td></tr></table>

# 2.2. Expansion Busses

<table><tr><td>PCI Express</td><td>6 PCI Express x1 Gen3 (AB): Lanes 0/1/2/3/4/52 PCI Express x1 Gen3 (CD): Lane 6/71 PCI Express x1 Gen3 (CD): Lane 16 (muxed with SATA port 3, build option)Notes: PCIe lanes 0/1/2/3 can also be configured to x2, x4. PCIe lanes 4/5 can also be configured to x2. Maximum 5 PCIe devices for Lane 0-7 and 16.</td></tr><tr><td>Other</td><td>LPC busSMBus (system) $I^{2}C$  (user)</td></tr></table>

# 2.3. Video

<table><tr><td>Integrated on Processor</td><td>Intel® Gen 9 LP Graphics core architecture</td></tr><tr><td>GPU Feature Support</td><td>3 independent and simultaneous combinations of DisplayPort/HDMI/LVDS graphics outputs (eDP optional in place of LVDS, VGA optional in place of DDI 2)Encode/transcode HD contentPlayback of high definition content including Blu-ray DiscPlayback of Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D) DirectX Video Acceleration (DXVA) support for accelerated video processingHEVC/H.265 10-bit/8-bit, H.264, M/JPEG, MPEG2, VC1, WMV9, VP9 HW decodeHEVC/H.265, H.264, M/JPEG, MPEG2, VP9 HW encodeAdvanced Scheduler 2.0, 1.0, XPDM support DirectX up to 12OpenGL up to 4.5, OpenCL up to 2.1 supportNote: Availability of features dependent on operating system (Windows 10 64-bit, Linux 64-bit)</td></tr><tr><td>Display Interface Support</td><td>LVDS: Single/dual channel 18/24-bit LVDS through eDP to LVDS, supports DE mode and Hsync/Vsync mode. Max. resolution is 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported.eDP: eDP 1.4 up to 4 lane support, in place of LVDS (BOM option), max. resolution is 4096x2304@60Hz, 24bppDigital Display Ports x3: DDI1/2 support DisplayPort 1.2/HDMI 1.4/DVI VGA: VGA support, in place of DDI 2. Max. resolution is 1920x1200@60Hz</td></tr></table>

# 2.4. Audio

<table><tr><td>Integrated</td><td>Intel® HD Audio integrated</td></tr><tr><td>Codec</td><td>Located on carrier Express-BASE6 (ALC886 standard support)</td></tr></table>

# 2.5. LAN

<table><tr><td>Integrated</td><td>MAC integrated</td></tr><tr><td>Intel PHY</td><td>Intel® Ethernet Controller I219-LM or I219-V (only LM version supports iAMT)</td></tr><tr><td>Interface</td><td>10/100/1000 Mbit/s connection</td></tr></table>

# 2.6. Multi I/O and Storage

<table><tr><td>Integrated</td><td>Integrated in SoC</td></tr><tr><td> $USB^{(1)}$ </td><td>4x USB 3.1 Gen2 (USB 0,1,2,3), 4x USB 2.0 (USB 4,5,6,7)All USB supported by xHCI controllers</td></tr><tr><td> $SATA^{(2)}$ </td><td>3x SATA 6Gb/s (SATA 0,1,2)SATA port 2 muxed with PCIe Lane 16 (SATA is default)</td></tr><tr><td>GPIO/SD</td><td>4 GPO and 4 GPI (GPI with interrupt)SD/GPIO muxed design, switched by BIOS settingSD functions as storage device only</td></tr></table>

Notes: (1)USB 3.1 Gen2 support is dependent on carrier board design.
(2)For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board.

# 2.7. Serial I/O on Module

- Chipset: Nuvoton NCT5104D
- Ports: 2x UARTs Rx/Tx only
- Console Redirection: COM 1 or COM 2 selectable in BIOS

<table><tr><td>COM Port</td><td>Description</td><td>IRQ</td><td>Address</td><td>Console Redirection Support</td></tr><tr><td>COM 1</td><td>Supported by module (SER0, A98/A99), via SOC</td><td>4</td><td>0x3F8</td><td>Yes</td></tr><tr><td>COM 2</td><td>Supported by module (SER1, A101/A102), via SOC</td><td>3</td><td>0x2F8</td><td>Yes</td></tr><tr><td>COM 3</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>5</td><td>0x240</td><td>Yes</td></tr><tr><td>COM 4</td><td>Supported by Super I/O (W83627DHG) on carrier board</td><td>7</td><td>0x248</td><td>Yes</td></tr></table>

Note: NCT5104D is 16550-compatible and supports up to 1.5Mb/s (baud rate at 24MHz)

# 2.8. Trusted Platform Module (TPM)

- Chipset: Infineon solution
- Type: TPM 2.0

# 2.9. SEMA Board Controller

● Type: ADLINK Smart Embedded Management Agent (SEMA)
- Functions:

• Voltage/Current monitoring
• Power sequence debug support
- AT/ATX mode control
• Logistics and forensic information

- Flat panel control
- General purpose I2C
- Failsafe BIOS (dual BIOS) (build option feature)
• Watchdog timer and fan control

# 2.10. Debug

\- 40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs

# 2.11. Power Specifications

<table><tr><td>Power Modes</td><td>AT and ATX mode (AT mode startup controlled by SEMA Board Controller)</td></tr><tr><td>Standard Voltage Input</td><td>ATX: 12V±5% / 5Vsb ±5% or AT = 12V±5%</td></tr><tr><td>Wide Voltage Input</td><td>ATX: 5-20V, 5Vsb ±5% or AT @ 5-20V</td></tr><tr><td>Power Management</td><td>ACPI 5.0 compliant, Smart Battery support</td></tr><tr><td>Power States</td><td>Supports C1-C6, S0, S1, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5)</td></tr><tr><td>ECO Mode</td><td>Supports deep S5 for 5Vsb power saving</td></tr></table>

# 2.12. Power Consumption

Please contact your ADLINK representative for the document "COM Express Module Power Consumption".

# 2.13. Operating Temperatures

<table><tr><td>Standard Operating Temperature</td><td>0°C to +60°C (Wide Voltage Input)Storage: -20°C to +80°C</td></tr><tr><td>Extreme Rugged Operating Temperature</td><td>-40°C to +85°C (Standard Voltage Input)Storage: -40°C to +85°CSelected SoC SKUs by project basis</td></tr></table>

# 2.14. Environmental

<table><tr><td>Humidity</td><td>Operating: 5-90% RH, non-condensingStorage: 5-95% RH (and operating with conformal coating)</td></tr><tr><td>Shock and Vibration</td><td>IEC 60068-2-64 and IEC-60068-2-27MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,Condition D</td></tr><tr><td>HALT</td><td>Thermal Stress, Vibration Stress, Thermal Shock and Combined Test</td></tr></table>

# 2.15. Specification Compliance

● PICMG COM.0: Rev 3.0 Type 6, Compact size 95 x 95 mm

# 2.16. Operating Systems

<table><tr><td>Standard Support</td><td>Windows 10 (64-bit)Windows 10 IOT Enterprise (64-bit)Yocto project based Linux (64-bit)Ubuntu LTS (64-bit, under planning)VxWorks 7.0</td></tr><tr><td>Extended Support (BSP)</td><td>Yocto project based Linux (64-bit)</td></tr></table>

2.17. Functional Diagram
![The diagram illustrates the connectivity of a central System on Chip (SoC) to various interface columns (AB and CD) and peripheral components.\n\n**Central Block**\n*   **8th Gen Intel® Core™ Intel® Celeron® SoC** (formerly “Whiskey Lake-U”)\n\n**Left Column (AB)**\n*   **LVDS:** Connected via 'eDP' to a block labeled 'LVDS eDP to LVDS', situated under text reading 'Single/dual channel 18/24-bit LVDS'. A dashed arrow labeled 'eDP 4 lanes (build option)' points from the LVDS block back toward the eDP connection.\n*   **VGA:** A dashed line connects to a dashed box labeled 'VGA DP to VGA' with text '(build option)'.\n*   **USB:** '8x USB 2.0/1.0 (ports 0-7)'\n*   **PCIe:** '6x PCIe x1 Gen3 (port 0-5, supports x2, x4)'\n*   **SATA:** '2x SATA 6Gb/s (port 0-1)'\n*   **SATA/PCIe Mux:** '1x SATA 6Gb/s (port 2) Muxed with PCIe port 16'\n*   **GbE:** A block labeled 'GbE'\n*   **Audio:** 'HD Audio'\n*   **LPC:** 'LPC bus (eSPI as build option)' connects to blocks labeled 'LPC to UART' and 'TPM 2.0'. The 'LPC to UART' block connects to 'UART0 UART1'.\n*   **GPIO/SD:** A line labeled 'SD' connects to a 'GPIO' block, which connects to a 'Switch' block, leading to 'GPIO SD'.\n*   **SMBus:** 'SMBus'\n*   **Bottom Signals:** Arrows point from 'GP I²C', 'DDC I²C', 'SPI CS#', and 'SPI'.\n\n**Right Column (CD)**\n*   **Memory:** 'SODIMM 4-32 GB DDR4 non-ECC (top side)' and 'SODIMM 4-32 GB DDR4 non-ECC (bottom side)'\n*   **Display:** 'DDI1 (4 lanes) DP/HDMI' and 'DDI2 (4 lanes) DP/HDMI'\n*   **PCIe:** '2x PCIe x1 Gen3 (port 6-7, x1 only)'\n*   **PCIe Mux:** '1x PCIe x1 Gen3 (port 16) (build option, in place of SATA2)' (dashed line)\n*   **USB:** '4x USB 3.1 Gen2 upgrade (port 0-3)'\n*   **eMMC:** 'eMMC 8-64GB' (dashed box)\n\n**Bottom Section**\n*   **HSUART:** Label near the bottom of the SoC.\n*   **i²C:** Connects the SoC to the bottom block.\n*   **New SEMA BMC:** Connected via 'SMBus' and 'i²C'.\n*   **BIOS:** 'SPI 0 BIOS' and 'SPI 1 BIOS' (dashed box).\n*   **Thermal Sensor:** Connected to the BMC.](.cexpress-wl-50m-00029-1020-12/c52d056a7d11cd365be428390be1e15b1d01f082a1f97fcadd45527cb2014a0f.jpg)

Figure 1: cExpress-WL Functional Block Diagram

# 2.18. Mechanical Drawing

![95\n80\n74.2\n16.5\n4\n0\n4\n6\n18\nconnector on bottom side\n35\nTop View\n91\n91\n19\n4\n91\n95\nSide View\n5.2\n4\n2](.cexpress-wl-50m-00029-1020-12/1bf8311d7724e0f1af6fe90ceadcf55a81b72d647b5f496e9a6a125e863a02e0.jpg)

All are dimensions shown in millimeters.

Tolerances should be $\pm0.25mm\ (\pm0.010"$ ), unless otherwise noted. The tolerances of the module connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00]) should be $\pm0.10mm\ (\pm0.004"$ ).

Figure 2: cExpress-WL Mechanical Drawing

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# 3. Pinouts and Signal Descriptions

# 3.1. AB/CD Pin Definitions

The cExpress-WL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector. All pins in the COM Express specification are described, including those not supported on the cExpress-WL. Those not supported on the cExpress-WL module are crossed out.

Table 1: cExpress-WL AB/CD Pin Definitions

<table><tr><td colspan="3">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td colspan="2">Row D</td></tr><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td></td></tr><tr><td>A1</td><td>GND (fixed)</td><td>B1</td><td>GND (fixed)</td><td>C1</td><td>GND (fixed)</td><td>D1</td><td>GND (fixed)</td><td></td></tr><tr><td>A2</td><td>GBE0_MDI3-</td><td>B2</td><td>GBE0_ACT#</td><td>C2</td><td>GND</td><td>D2</td><td>GND</td><td></td></tr><tr><td>A3</td><td>GBE0_MDI3+</td><td>B3</td><td>LPC_FRAME#/ESPI_CS0#</td><td>C3</td><td>USB_SSRX0-</td><td>D3</td><td>USB_SSTX0-</td><td></td></tr><tr><td>A4</td><td>GBE0_LINK100#</td><td>B4</td><td>LPC_AD0/ESPI_IO_0</td><td>C4</td><td>USB_SSRX0+</td><td>D4</td><td>USB_SSTX0+</td><td></td></tr><tr><td>A5</td><td>GBE0_LINK1000#</td><td>B5</td><td>LPC_AD1/ESPI_IO_1</td><td>C5</td><td>GND</td><td>D5</td><td>GND</td><td></td></tr><tr><td>A6</td><td>GBE0_MDI2-</td><td>B6</td><td>LPC_AD2/ESPI_IO_2</td><td>C6</td><td>USB_SSRX1-</td><td>D6</td><td>USB_SSTX1-</td><td></td></tr><tr><td>A7</td><td>GBE0_MDI2+</td><td>B7</td><td>LPC_AD3/ESPI_IO_3</td><td>C7</td><td>USB_SSRX1+</td><td>D7</td><td>USB_SSTX1+</td><td></td></tr><tr><td>A8</td><td>GBE0_LINK#</td><td>B8</td><td>LPC_DRQ0#/ESPI_ALERT0#</td><td>C8</td><td>GND</td><td>D8</td><td>GND</td><td></td></tr><tr><td>A9</td><td>GBE0_MDI1-</td><td>B9</td><td>LPC_DRQ1#/ESPI_ALERT1#</td><td>C9</td><td>USB_SSRX2-</td><td>D9</td><td>USB_SSTX2-</td><td></td></tr><tr><td>A10</td><td>GBE0_MDI1+</td><td>B10</td><td>LPC_CLK/ESPI_CK</td><td>C10</td><td>USB_SSRX2+</td><td>D10</td><td>USB_SSTX2+</td><td></td></tr><tr><td>A11</td><td>GND (fixed)</td><td>B11</td><td>GND (fixed)</td><td>C11</td><td>GND (fixed)</td><td>D11</td><td>GND (fixed)</td><td></td></tr><tr><td>A12</td><td>GBE0_MDI0-</td><td>B12</td><td>PWRBTN#</td><td>C12</td><td>USB_SSRX3-</td><td>D12</td><td>USB_SSTX3-</td><td></td></tr><tr><td>A13</td><td>GBE0_MDI0+</td><td>B13</td><td>SMB_CK</td><td>C13</td><td>USB_SSRX3+</td><td>D13</td><td>USB_SSTX3+</td><td></td></tr><tr><td>A14</td><td>GBE0_CTREF</td><td>B14</td><td>SMB_DAT</td><td>C14</td><td>GND</td><td>D14</td><td>GND</td><td></td></tr><tr><td>A15</td><td>SUS_S3#</td><td>B15</td><td>SMB_ALERT#</td><td>C15</td><td>DDI1_PAIR6+</td><td>D15</td><td>DDI1_CTRLCLK_AUX+</td><td></td></tr><tr><td>A16</td><td>SATA0_TX+</td><td>B16</td><td>SATA1_TX+</td><td>C16</td><td>DDI1_PAIR6-</td><td>D16</td><td>DDI1_CTRLDATA_AUX</td><td></td></tr><tr><td>A17</td><td>SATA0_TX-</td><td>B17</td><td>SATA1_TX-</td><td>C17</td><td>RSVD</td><td>D17</td><td>RSVD</td><td></td></tr><tr><td>A18</td><td>SUS_S4#</td><td>B18</td><td>SUS_STAT#/ESPI_RESET#</td><td>C18</td><td>RSVD</td><td>D18</td><td>RSVD</td><td></td></tr><tr><td>A19</td><td>SATA0_RX+</td><td>B19</td><td>SATA1_RX+</td><td>C19</td><td>PCIE_RX6+</td><td>D19</td><td>PCIE_TX6+</td><td></td></tr><tr><td>A20</td><td>SATA0_RX-</td><td>B20</td><td>SATA1_RX-</td><td>C20</td><td>PCIE_RX6-</td><td>D20</td><td>PCIE_TX6-</td><td></td></tr><tr><td>A21</td><td>GND (fixed)</td><td>B21</td><td>GND (fixed)</td><td>C21</td><td>GND (fixed)</td><td>D21</td><td>GND (fixed)</td><td></td></tr><tr><td>A22</td><td>SATA2_TX+</td><td>B22</td><td>SATA3_TX+</td><td>C22</td><td>PCIE_RX7+</td><td>D22</td><td>PCIE_TX7+</td><td></td></tr><tr><td>A23</td><td>SATA2_TX-</td><td>B23</td><td>SATA3_TX-</td><td>C23</td><td>PCIE_RX7-</td><td>D23</td><td>PCIE_TX7-</td><td></td></tr><tr><td>A24</td><td>SUS_S5#</td><td>B24</td><td>PWR_OK</td><td>C24</td><td>DDI1_HPD</td><td>D24</td><td>RSVD</td><td></td></tr><tr><td>A25</td><td>SATA2_RX+</td><td>B25</td><td>SATA3_RX+</td><td>C25</td><td>DDI1_PAIR4+</td><td>D25</td><td>RSVD</td><td></td></tr><tr><td>A26</td><td>SATA2_RX-</td><td>B26</td><td>SATA3_RX-</td><td>C26</td><td>DDI1_PAIR4-</td><td>D26</td><td>DDI1_PAIR0+</td><td></td></tr><tr><td>A27</td><td>BATLOW#</td><td>B27</td><td>WDT</td><td>C27</td><td>RSVD</td><td>D27</td><td>DDI1_PAIR0-</td><td></td></tr><tr><td>A28</td><td>(S)ATA_ACT#</td><td>B28</td><td>HDA_SDIN2</td><td>C28</td><td>RSVD</td><td>D28</td><td>RSVD</td><td></td></tr><tr><td>A29</td><td>HDA_SYNC</td><td>B29</td><td>HDA_SDIN1</td><td>C29</td><td>DDI1_PAIR5+</td><td>D29</td><td>DDI1_PAIR1+</td><td></td></tr><tr><td>A30</td><td>HDA_RST#</td><td>B30</td><td>HDA_SDIN0</td><td>C30</td><td>DDI1_PAIR5-</td><td>D30</td><td>DDI1_PAIR1-</td><td></td></tr><tr><td>A31</td><td>GND (fixed)</td><td>B31</td><td>GND (fixed)</td><td>C31</td><td>GND (fixed)</td><td>D31</td><td>GND (fixed)</td><td></td></tr><tr><td>A32</td><td>HDA_BITCLK</td><td>B32</td><td>SPKR</td><td>C32</td><td>DDI2_CTRLCLK_AUX+</td><td>D32</td><td>DDI1_PAIR2+</td><td></td></tr><tr><td>A33</td><td>HDA_SDOUT</td><td>B33</td><td>I2C_CK</td><td>C33</td><td>DDI2_CTRLDATA_AUX-</td><td>D33</td><td>DDI1_PAIR2-</td><td></td></tr><tr><td>A34</td><td>BIOS_DIS0#/ESPI_SAFS</td><td>B34</td><td>I2C_DAT</td><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td>D34</td><td>DDI1_DDC_AUX_SEL</td><td></td></tr><tr><td>A35</td><td>THRMTRIP#</td><td>B35</td><td>THRM#</td><td>C35</td><td>RSVD</td><td>D35</td><td>RSVD</td><td></td></tr></table>

Row A
Notes: 4-lane eDP is available as BOM option in place of LVDS.
Row B
VGA is available as BOM option in place of DDI 2.
Row C
I2C bus from SOC is available as BOM option.
Row D
SER 0/1 from a on-board LPC-to-UART IC (NCT5104D) is available as BOM option.

<table><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td></tr><tr><td>A36</td><td>USB6-</td><td>B36</td><td>USB7-</td><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td>D36</td><td>DDI1_PAIR3+</td></tr><tr><td>A37</td><td>USB6+</td><td>B37</td><td>USB7+</td><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td>D37</td><td>DDI1_PAIR3-</td></tr><tr><td>A38</td><td>USB_6_7_OC#</td><td>B38</td><td>USB_4_5_OC#</td><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td>D38</td><td>RSVD</td></tr><tr><td>A39</td><td>USB4-</td><td>B39</td><td>USB5-</td><td>C39</td><td>DDI3_PAIR0+</td><td>D39</td><td>DDI2_PAIR0+</td></tr><tr><td>A40</td><td>USB4+</td><td>B40</td><td>USB5+</td><td>C40</td><td>DDI3_PAIR0-</td><td>D40</td><td>DDI2_PAIR0-</td></tr><tr><td>A41</td><td>GND (fixed)</td><td>B41</td><td>GND (fixed)</td><td>C41</td><td>GND (fixed)</td><td>D41</td><td>GND (fixed)</td></tr><tr><td>A42</td><td>USB2-</td><td>B42</td><td>USB3-</td><td>C42</td><td>DDI3_PAIR1+</td><td>D42</td><td>DDI2_PAIR1+</td></tr><tr><td>A43</td><td>USB2+</td><td>B43</td><td>USB3+</td><td>C43</td><td>DDI3_PAIR1-</td><td>D43</td><td>DDI2_PAIR1-</td></tr><tr><td>A44</td><td>USB_2_3_OC#</td><td>B44</td><td>USB_0_1_OC#</td><td>C44</td><td>DDI3_HPD</td><td>D44</td><td>DDI2_HPD</td></tr><tr><td>A45</td><td>USB0-</td><td>B45</td><td>USB1-</td><td>C45</td><td>RSVD</td><td>D45</td><td>RSVD</td></tr><tr><td>A46</td><td>USB0+</td><td>B46</td><td>USB1+</td><td>C46</td><td>DDI3_PAIR2+</td><td>D46</td><td>DDI2_PAIR2+</td></tr><tr><td>A47</td><td>VCC_RTC</td><td>B47</td><td>ESPI_EN#</td><td>C47</td><td>DDI3_PAIR2-</td><td>D47</td><td>DDI2_PAIR2-</td></tr><tr><td>A48</td><td>RSVD</td><td>B48</td><td>USB0_HOST_PRSNT</td><td>C48</td><td>RSVD</td><td>D48</td><td>RSVD</td></tr><tr><td>A49</td><td>GBE0_SDP</td><td>B49</td><td>SYS_RESET#</td><td>C49</td><td>DDI3_PAIR3+</td><td>D49</td><td>DDI2_PAIR3+</td></tr><tr><td>A50</td><td>LPC_SERIRQ</td><td>B50</td><td>CB_RESET#</td><td>C50</td><td>DDI3_PAIR3-</td><td>D50</td><td>DDI2_PAIR3-</td></tr><tr><td>A51</td><td>GND (fixed)</td><td>B51</td><td>GND (fixed)</td><td>C51</td><td>GND (fixed)</td><td>D51</td><td>GND (fixed)</td></tr><tr><td>A52</td><td>PCIE_TX5+</td><td>B52</td><td>PCIE_RX5+</td><td>C52</td><td>PEG_RX0+* (Lane 16)</td><td>D52</td><td>PEG_TX0+* (Lane 16)</td></tr><tr><td>A53</td><td>PCIE_TX5-</td><td>B53</td><td>PCIE_RX5-</td><td>C53</td><td>PEG_RX0-* (Lane 16)</td><td>D53</td><td>PEG_TX0-* (Lane 16)</td></tr><tr><td>A54</td><td>GPIO/SD_DATA0</td><td>B54</td><td>GPO1/SD_CMD</td><td>C54</td><td>TYPE0#</td><td>D54</td><td>PEG_LANE_RV#</td></tr><tr><td>A55</td><td>PCIE_TX4+</td><td>B55</td><td>PCIE_RX4+</td><td>C55</td><td>PEG_RX1+</td><td>D55</td><td>PEG_TX1+</td></tr><tr><td>A56</td><td>PCIE_TX4-</td><td>B56</td><td>PCIE_RX4-</td><td>C56</td><td>PEG_RX1-</td><td>D56</td><td>PEG_TX1-</td></tr><tr><td>A57</td><td>GND</td><td>B57</td><td>GPO2/SD_WP</td><td>C57</td><td>TYPE1#</td><td>D57</td><td>TYPE2#</td></tr><tr><td>A58</td><td>PCIE_TX3+</td><td>B58</td><td>PCIE_RX3+</td><td>C58</td><td>PEG_RX2+</td><td>D58</td><td>PEG_TX2+</td></tr><tr><td>A59</td><td>PCIE_TX3-</td><td>B59</td><td>PCIE_RX3-</td><td>C59</td><td>PEG_RX2-</td><td>D59</td><td>PEG_TX2-</td></tr><tr><td>A60</td><td>GND (fixed)</td><td>B60</td><td>GND (fixed)</td><td>C60</td><td>GND (fixed)</td><td>D60</td><td>GND (fixed)</td></tr><tr><td>A61</td><td>PCIE_TX2+</td><td>B61</td><td>PCIE_RX2+</td><td>C61</td><td>PEG_RX3+</td><td>D61</td><td>PEG_TX3+</td></tr><tr><td>A62</td><td>PCIE_TX2-</td><td>B62</td><td>PCIE_RX2-</td><td>C62</td><td>PEG_RX3-</td><td>D62</td><td>PEG_TX3-</td></tr><tr><td>A63</td><td>GPI1/SD_DATA1</td><td>B63</td><td>GPO3/SD_CD#</td><td>C63</td><td>RSVD</td><td>D63</td><td>RSVD</td></tr><tr><td>A64</td><td>PCIE_TX1+</td><td>B64</td><td>PCIE_RX1+</td><td>C64</td><td>RSVD</td><td>D64</td><td>RSVD</td></tr><tr><td>A65</td><td>PCIE_TX1-</td><td>B65</td><td>PCIE_RX1-</td><td>C65</td><td>PEG_RX4+</td><td>D65</td><td>PEG_TX4+</td></tr><tr><td>A66</td><td>GND</td><td>B66</td><td>WAKE0#</td><td>C66</td><td>PEG_RX4-</td><td>D66</td><td>PEG_TX4-</td></tr><tr><td>A67</td><td>GPI2/SD_DATA2</td><td>B67</td><td>WAKE1#</td><td>C67</td><td>RAPID_SHUTDOWN</td><td>D67</td><td>GND</td></tr><tr><td>A68</td><td>PCIE_TX0+</td><td>B68</td><td>PCIE_RX0+</td><td>C68</td><td>PEG_RX5+</td><td>D68</td><td>PEG_TX5+</td></tr><tr><td>A69</td><td>PCIE_TX0-</td><td>B69</td><td>PCIE_RX0-</td><td>C69</td><td>PEG_RX5-</td><td>D69</td><td>PEG_TX5-</td></tr><tr><td>A70</td><td>GND (fixed)</td><td>B70</td><td>GND (fixed)</td><td>C70</td><td>GND (fixed)</td><td>D70</td><td>GND (fixed)</td></tr><tr><td>A71</td><td>LVDS_A0+</td><td>B71</td><td>LVDS_B0+</td><td>C71</td><td>PEG_RX6+</td><td>D71</td><td>PEG_TX6+</td></tr><tr><td>A72</td><td>LVDS_A0-</td><td>B72</td><td>LVDS_B0-</td><td>C72</td><td>PEG_RX6-</td><td>D72</td><td>PEG_TX6-</td></tr><tr><td>A73</td><td>LVDS_A1+</td><td>B73</td><td>LVDS_B1+</td><td>C73</td><td>GND</td><td>D73</td><td>GND</td></tr><tr><td>A74</td><td>LVDS_A1-</td><td>B74</td><td>LVDS_B1-</td><td>C74</td><td>PEG_RX7+</td><td>D74</td><td>PEG_TX7+</td></tr><tr><td>A75</td><td>LVDS_A2+</td><td>B75</td><td>LVDS_B2+</td><td>C75</td><td>PEG_RX7-</td><td>D75</td><td>PEG_TX7-</td></tr><tr><td>A76</td><td>LVDS_A2-</td><td>B76</td><td>LVDS_B2-</td><td>C76</td><td>GND</td><td>D76</td><td>GND</td></tr><tr><td>A77</td><td>LVDS_VDD_EN</td><td>B77</td><td>LVDS_B3+</td><td>C77</td><td>RSVD</td><td>D77</td><td>RSVD</td></tr><tr><td>A78</td><td>LVDS_A3+</td><td>B78</td><td>LVDS_B3-</td><td>C78</td><td>PEG_RX8+</td><td>D78</td><td>PEG_TX8+</td></tr><tr><td>A79</td><td>LVDS_A3-</td><td>B79</td><td>LVDS_BKLT_EN</td><td>C79</td><td>PEG_RX8-</td><td>D79</td><td>PEG_TX8-</td></tr><tr><td colspan="3">Row A</td><td colspan="2">Row B</td><td colspan="2">Row C</td><td>Row D</td></tr><tr><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td><td>Pin</td><td>Name</td></tr><tr><td>A80</td><td>GND (FIXED)</td><td>B80</td><td>GND (FIXED)</td><td>C80</td><td>GND (FIXED)</td><td>D80</td><td>GND (FIXED)</td></tr><tr><td>A81</td><td>LVDS_A_CK+</td><td>B81</td><td>LVDS_B_CK+</td><td>C81</td><td>PEG_RX9+</td><td>D81</td><td>PEG_TX9+</td></tr><tr><td>A82</td><td>LVDS_A_CK-</td><td>B82</td><td>LVDS_B_CK-</td><td>C82</td><td>PEG_RX9-</td><td>D82</td><td>PEG_TX9-</td></tr><tr><td>A83</td><td>LVDS_I2C_CK</td><td>B83</td><td>LVDS_BKLT_CTRL</td><td>C83</td><td>RSVD</td><td>D83</td><td>RSVD</td></tr><tr><td>A84</td><td>LVDS_I2C_DAT</td><td>B84</td><td>VCC_5V_SBY</td><td>C84</td><td>GND</td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GPI3/SD_DATA3</td><td>B85</td><td>VCC_5V_SBY</td><td>C85</td><td>PEG_RX10+</td><td>D85</td><td>PEG_TX10+</td></tr><tr><td>A86</td><td>RSVD</td><td>B86</td><td>VCC_5V_SBY</td><td>C86</td><td>PEG_RX10-</td><td>D86</td><td>PEG_TX10-</td></tr><tr><td>A87</td><td>eDP_HPD</td><td>B87</td><td>VCC_5V_SBY</td><td>C87</td><td>GND</td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>PCIE0_CK_REF+</td><td>B88</td><td>BIOS_DIS1#</td><td>C88</td><td>PEG_RX11+</td><td>D88</td><td>PEG_TX11+</td></tr><tr><td>A89</td><td>PCIE0_CK_REF-</td><td>B89</td><td>VGA_RED*</td><td>C89</td><td>PEG_RX11-</td><td>D89</td><td>PEG_TX11-</td></tr><tr><td>A90</td><td>GND (fixed)</td><td>B90</td><td>GND (fixed)</td><td>C90</td><td>GND (fixed)</td><td>D90</td><td>GND (fixed)</td></tr><tr><td>A91</td><td>SPI_POWER</td><td>B91</td><td>VGA_GRN*</td><td>C91</td><td>PEG_RX12+</td><td>D91</td><td>PEG_TX12+</td></tr><tr><td>A92</td><td>SPI_MISO</td><td>B92</td><td>VGA_BLU*</td><td>C92</td><td>PEG_RX12-</td><td>D92</td><td>PEG_TX12-</td></tr><tr><td>A93</td><td>GPO0/SD_CLK</td><td>B93</td><td>VGA_HSYNC*</td><td>C93</td><td>GND</td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>SPI_CLK</td><td>B94</td><td>VGA_VSYNC*</td><td>C94</td><td>PEG_RX13+</td><td>D94</td><td>PEG_TX13+</td></tr><tr><td>A95</td><td>SPI_MOSI</td><td>B95</td><td>VGA_I2C_CK*</td><td>C95</td><td>PEG_RX13-</td><td>D95</td><td>PEG_TX13-</td></tr><tr><td>A96</td><td>TPM_PP</td><td>B96</td><td>VGA_I2C_DAT*</td><td>C96</td><td>GND</td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>TYPE10#</td><td>B97</td><td>SPI_CS#</td><td>C97</td><td>RSVD</td><td>D97</td><td>RSVD</td></tr><tr><td>A98</td><td>SER0_TX</td><td>B98</td><td>RSVD</td><td>C98</td><td>PEG_RX14+</td><td>D98</td><td>PEG_TX14+</td></tr><tr><td>A99</td><td>SER0_RX</td><td>B99</td><td>RSVD</td><td>C99</td><td>PEG_RX14-</td><td>D99</td><td>PEG_TX14-</td></tr><tr><td>A100</td><td>GND (fixed)</td><td>B100</td><td>GND (fixed)</td><td>C100</td><td>GND (fixed)</td><td>D100</td><td>GND (fixed)</td></tr><tr><td>A101</td><td>SER1_TX</td><td>B101</td><td>FAN_PWMOUT</td><td>C101</td><td>PEG_RX15+</td><td>D101</td><td>PEG_TX15+</td></tr><tr><td>A102</td><td>SER1_RX</td><td>B102</td><td>FAN_TACHIN</td><td>C102</td><td>PEG_RX15-</td><td>D102</td><td>PEG_TX15-</td></tr><tr><td>A103</td><td>LID# **</td><td></td><td>SLEEP# **</td><td>C103</td><td>GND</td><td>D103</td><td>GND</td></tr><tr><td>A104</td><td>VCC_12V</td><td>B104</td><td>VCC_12V</td><td>C104</td><td>VCC_12V</td><td>D104</td><td>VCC_12V</td></tr><tr><td>A105</td><td>VCC_12V</td><td>B105</td><td>VCC_12V</td><td>C105</td><td>VCC_12V</td><td>D105</td><td>VCC_12V</td></tr><tr><td>A106</td><td>VCC_12V</td><td>B106</td><td>VCC_12V</td><td>C106</td><td>VCC_12V</td><td>D106</td><td>VCC_12V</td></tr><tr><td>A107</td><td>VCC_12V</td><td>B107</td><td>VCC_12V</td><td>C107</td><td>VCC_12V</td><td>D107</td><td>VCC_12V</td></tr><tr><td>A108</td><td>VCC_12V</td><td>B108</td><td>VCC_12V</td><td>C108</td><td>VCC_12V</td><td>D108</td><td>VCC_12V</td></tr><tr><td>A109</td><td>VCC_12V</td><td>B109</td><td>VCC_12V</td><td>C109</td><td>VCC_12V</td><td>D109</td><td>VCC_12V</td></tr><tr><td>A110</td><td>GND (fixed)</td><td>B110</td><td>GND (fixed)</td><td>C110</td><td>GND (fixed)</td><td>D110</td><td>GND (fixed)</td></tr></table>

ESPI is available as BOM option (TBD)
PEG 0 (Lane 16) is available as BOM option in place of SATA port 2

# 3.2. Signal Description Terminology

The following terms are used in the COM Express AB/CD Signal Descriptions below.

I Input to the Module

O Output from the Module

I/O Bi-directional input/output signal

OD Open drain output

I 3.3V Input 3.3V tolerant

I 5V Input 5V tolerant

I 3.3Vsb Input 3.3V tolerant active in standby state

O 3.3V Output 3.3V signal level

O 5V Output 5V signal level

I/O 3.3V Bi-directional signal 3.3V tolerant

I/O 5V Bi-directional signal 5V tolerant

I/O 3.3Vsb Bi-directional 3.3V tolerant active in standby state

P Power Input/Output

REF Reference voltage output that may be sourced from a module power plane.

PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected. The signal is used to indicate the PICMG module type to the Carrier Board.

PU ADLINK implemented pull-up resistor on module

PD ADLINK implemented pull-down resistor on module

# 3.3. AB Signal Descriptions

# 3.3.1. Audio Signals

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>HDA_RST#</td><td>A30</td><td>Reset output to CODEC, active low.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>HDA_SYNC</td><td>A29</td><td>Sample-synchronization signal to the CODEC(s).</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>HDA_BITCLK</td><td>A32</td><td>Serial data clock generated by the external CODEC(s).</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>HDA_SDOUT</td><td>A33</td><td>Serial TDM data output to the CODEC.</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>HDA_SDIN[2:0]</td><td>B28B29B30</td><td>Serial TDM data inputs from up to 3 CODECs.</td><td>I 3.3VSB</td><td>ChipsetInternalPD14K-26K</td><td>HDA_SDIN0: supportedHDA_SDIN1: supportedHDA_SDIN2: not supported</td></tr></table>

# 3.3.2. Analog VGA

Note: VGA is supported by build option, in place of DDI 2.

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VGA_RED</td><td>B89</td><td>Red for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td>shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_GRN</td><td>B91</td><td>Green for monitorAnalog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td>shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_BLU</td><td>B92</td><td>Blue for monitor.Analog DAC output, designed to drive a 37.5-Ohm equivalent load.</td><td>O Analog</td><td>PD 150R</td><td>shall also be terminated on the carrier with 150Ω resistor to ground close to VGA connector</td></tr><tr><td>VGA_HSYNC</td><td>B93</td><td>Horizontal sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_VSYNC</td><td>B94</td><td>Vertical sync output to VGA monitor</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>VGA_I2C_CK</td><td>B95</td><td>DDC clock line (I2C port dedicated to identify VGA monitor capabilities)</td><td>I/O OD 3.3V</td><td>PU 2.2K 3.3V</td><td></td></tr><tr><td>VGA_I2C_DAT</td><td>B96</td><td>DDC data line.</td><td>I/O OD 3.3V</td><td>PU 2.2K 3.3V</td><td></td></tr></table>

3.3.3. LVDS

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LVDS_A0+</td><td>A71</td><td rowspan="8">LVDS Channel A differential pairs</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="20">LVDS is default support</td></tr><tr><td>LVDS_A0-</td><td>A72</td></tr><tr><td>LVDS_A1+</td><td>A73</td></tr><tr><td>LVDS_A1-</td><td>A74</td></tr><tr><td>LVDS_A2+</td><td>A75</td></tr><tr><td>LVDS_A2-</td><td>A76</td></tr><tr><td>LVDS_A3+</td><td>A78</td></tr><tr><td>LVDS_A3-</td><td>A79</td></tr><tr><td>LVDS_A_CK+</td><td>A81</td><td rowspan="2">LVDS Channel A differential clock</td><td rowspan="2">O LVDS</td><td rowspan="2"></td></tr><tr><td>LVDS_A_CK-</td><td>A82</td></tr><tr><td>LVDS_B0+</td><td>B71</td><td rowspan="8">LVDS Channel B differential pairs</td><td rowspan="8">O LVDS</td><td rowspan="8"></td></tr><tr><td>LVDS_B0-</td><td>B72</td></tr><tr><td>LVDS_B1+</td><td>B73</td></tr><tr><td>LVDS_B1-</td><td>B74</td></tr><tr><td>LVDS_B2+</td><td>B75</td></tr><tr><td>LVDS_B2-</td><td>B76</td></tr><tr><td>LVDS_B3+</td><td>B77</td></tr><tr><td>LVDS_B3-</td><td>B78</td></tr><tr><td>LVDS_B_CK+</td><td>B81</td><td rowspan="2">LVDS Channel B differential clock</td><td rowspan="2">O LVDS</td><td rowspan="2"></td></tr><tr><td>LVDS_B_CK-</td><td>B82</td></tr><tr><td>LVDS_VDD_EN</td><td>A77</td><td>LVDS panel power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_EN</td><td>B79</td><td>LVDS panel backlight enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_BKLT_CTRL</td><td>B83</td><td>LVDS panel backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>LVDS_I2C_CK</td><td>A83</td><td>DDC lines used for flat panel detection and control.</td><td>I/O OD 3.3V</td><td>PU 2.2K 3.3V</td><td></td></tr><tr><td>LVDS_I2C_DAT</td><td>A84</td><td>DDC lines used for flat panel detection and control.</td><td>I/O OD 3.3V</td><td>PU 2.2K 3.3V</td><td></td></tr></table>

# 3.3.4. eDP

Note: eDP is supported by build option, in place of LVDS.

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>eDP_TX3+</td><td>A81</td><td rowspan="8">eDP differential pairs</td><td rowspan="8">O PCIE</td><td rowspan="8"></td><td rowspan="8">AC coupled off module</td></tr><tr><td>eDP_TX3-</td><td>A82</td></tr><tr><td>eDP_TX2+</td><td>A71</td></tr><tr><td>eDP_TX2-</td><td>A72</td></tr><tr><td>eDP_TX1+</td><td>A73</td></tr><tr><td>eDP_TX1-</td><td>A74</td></tr><tr><td>eDP_TX0+</td><td>A75</td></tr><tr><td>eDP_TX0-</td><td>A76</td></tr><tr><td>eDP_VDD_EN</td><td>A77</td><td>eDP power enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_EN</td><td>B79</td><td>eDP backlight enable</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_BKLT_CTRL</td><td>B83</td><td>eDP backlight brightness control</td><td>O 3.3V</td><td>PD 100K</td><td></td></tr><tr><td>eDP_AUX+</td><td>A83</td><td>eDP AUX+</td><td>I/OPCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_AUX-</td><td>A84</td><td>eDP AUX-</td><td>I/OPCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>eDP_HPD</td><td>A87</td><td>Detection of Hot Plug / Unplug and notification of the link layer</td><td>I 3.3V</td><td>PD 100K</td><td>PD 100K on this pin when eDP is supported</td></tr></table>

# 3.3.5. Gigabit Ethernet

<table><tr><td>Gigabit Ethernet</td><td>Pin #</td><td colspan="4">Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td rowspan="6">GBE0_MDI0+GBE0_MDI0-GBE0_MDI1+GBE0_MDI1-GBE0_MDI2+GBE0_MDI2-GBE0_MDI3+GBE0_MDI3-</td><td rowspan="6">A13A12A10A9A7A6A3A2</td><td colspan="4">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td><td rowspan="6">I/O Analog</td><td rowspan="6"></td><td rowspan="6">Twisted pair signals for external transformer.</td></tr><tr><td colspan="2">1000</td><td>100</td><td>10</td></tr><tr><td>MDI[0]+/-</td><td>B1_DA+/-</td><td>TX+/-</td><td>TX+/-</td></tr><tr><td>MDI[1]+/-</td><td>B1_DB+/-</td><td>RX+/-</td><td>RX+/-</td></tr><tr><td>MDI[2]+/-</td><td>B1_DC+/-</td><td></td><td></td></tr><tr><td>MDI[3]+/-</td><td>B1_DD+/-</td><td></td><td></td></tr><tr><td>GBE0_ACT#</td><td>B2</td><td colspan="4">Gigabit Ethernet Controller 0 activity indicator, active low.</td><td>OD 3.3VSB</td><td></td><td rowspan="2">These 2 pins (A8, B2) share the same source</td></tr><tr><td>GBE0_LINK#</td><td>A8</td><td colspan="4">Gigabit Ethernet Controller 0 link indicator, active low.</td><td>OD 3.3VSB</td><td></td></tr><tr><td>GBE0_LINK100#</td><td>A4</td><td colspan="4">Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_LINK1000#</td><td>A5</td><td colspan="4">Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.</td><td>OD 3.3VSB</td><td></td><td></td></tr><tr><td>GBE0_CTREF</td><td>A14</td><td colspan="4">Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.</td><td>REF GND min 3.3V max</td><td></td><td>NC pin</td></tr><tr><td>GBE0_SDP</td><td>A49</td><td colspan="4">Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as 1pps signal.</td><td>IO 3.3VSB</td><td></td><td>Not supported NC pin</td></tr></table>

3.3.6. SATA

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SATA0_TX+SATA0_TX-</td><td>A16A17</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA0_RX+SATA0_RX-</td><td>A19A20</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_TX+SATA1_TX-</td><td>B16B17</td><td>Serial ATA channel 1, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA1_RX+SATA1_RX-</td><td>B19B20</td><td>Serial ATA channel 1, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_TX+SATA2_TX-</td><td>A22A23</td><td>Serial ATA channel 2, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA2_RX+SATA2_RX-</td><td>A25A26</td><td>Serial ATA channel 2, Receive Input differential pair.</td><td>I SATA</td><td></td><td>AC coupled on Module</td></tr><tr><td>SATA3_TX+SATA3_TX-</td><td>B22B23</td><td>Serial ATA channel 3, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Not supported</td></tr><tr><td>SATA3_RX+SATA3_RX-</td><td>B25B26</td><td>Serial ATA channel 3, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Not supported</td></tr><tr><td>(S)ATA_ACT#</td><td>A28</td><td>ATA (parallel and serial) or SAS activity indicator, active low.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

SATA port 2 is muxed with PCIe Lane 16. SATA port 2 is default support.

PCH HSIO Lane Assignments

<table><tr><td>SATA on COMe Module</td><td>HSIO Function on PCH</td><td>Comment</td></tr><tr><td>SATA 0</td><td>SATA #0</td><td></td></tr><tr><td>SATA 1</td><td>SATA #1a</td><td></td></tr><tr><td>SATA 2</td><td>SATA #2</td><td></td></tr><tr><td>SATA 3</td><td>N/A</td><td>Not supported</td></tr></table>

3.3.7. PCI Express

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PCIE_TX0+PCIE_TX0-</td><td>A68A69</td><td>PCI Express channel 0, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX0+PCIE_RX0-</td><td>B68B69</td><td>PCI Express channel 0, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX1+PCIE_TX1-</td><td>A64A65</td><td>PCI Express channel 1, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX1+PCIE_RX1-</td><td>B64B65</td><td>PCI Express channel 1, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX2+PCIE_TX2-</td><td>A61A62</td><td>PCI Express channel 2, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX2+PCIE_RX2-</td><td>B61B62</td><td>PCI Express channel 2, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX3+PCIE_TX3-</td><td>A58A59</td><td>PCI Express channel 3, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX3+PCIE_RX3-</td><td>B58B59</td><td>PCI Express channel 3, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX4+PCIE_TX4-</td><td>A55A56</td><td>PCI Express channel 4, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX4+PCIE_RX4-</td><td>B55B56</td><td>PCI Express channel 4, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_TX5+PCIE_TX5-</td><td>A52A53</td><td>PCI Express channel 5, Transmit Output differential pair.</td><td>OPCIE</td><td></td><td>AC coupled on Module</td></tr><tr><td>PCIE_RX5+PCIE_RX5-</td><td>B52B53</td><td>PCI Express channel 5, Receive Input differential pair.</td><td>IPCIE</td><td></td><td>AC coupled off Module</td></tr><tr><td>PCIE_CLK_REF+PCIE_CLK_REF-</td><td>A88A89</td><td>PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes.</td><td>OPCIE</td><td></td><td></td></tr></table>

Note: Maximum 5 PCIe devices for PCIe 0-7 and PCIe 16.

PCH HSIO Lane Assignments

<table><tr><td>PCIe on COMe Module</td><td>HSIO Function on PCH</td><td>Comment</td></tr><tr><td>PCIE 0</td><td>PCIe #5</td><td rowspan="4"></td></tr><tr><td>PCIE 1</td><td>PCIe #6</td></tr><tr><td>PCIE 2</td><td>PCIe #7</td></tr><tr><td>PCIE 3</td><td>PCIe #8</td></tr><tr><td>PCIE 4</td><td>PCIe #13</td><td rowspan="4"></td></tr><tr><td>PCIE 5</td><td>PCIe #14</td></tr><tr><td>PCIE 6</td><td>PCIe #10</td></tr><tr><td>PCIE 7</td><td>PCIe #15</td></tr></table>

3.3.8. LPC Bus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>LPC_AD[0:3]</td><td>B4-B7</td><td>LPC multiplexed address, command and data bus</td><td>I/O 3.3V</td><td>Chipset Internal PU 15~40K</td><td></td></tr><tr><td>LPC_FRAME#</td><td>B3</td><td>LPC frame indicates the start of an LPC cycle</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>LPC_DRQ0#LPC_DRQ1#</td><td>B8B9</td><td>LPC serial DMA request</td><td>I 3.3V</td><td></td><td>NC pins</td></tr><tr><td>LPC_SERIRQ</td><td>A50</td><td>LPC serial interrupt</td><td>I/O 3.3V</td><td>PU 8.2K 3.3V</td><td></td></tr><tr><td>LPC_CLK</td><td>B10</td><td>LPC clock output -33MHz nominal</td><td>O 3.3V</td><td></td><td>The LPC_CLK frequency is 24MHz on this platform</td></tr></table>

ESPI is BOM option feature (TBD)

3.3.9. USB

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>USB0+USB0-</td><td>A46A45</td><td>USB differential data pairs for Port 0</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB1+USB1-</td><td>B46B45</td><td>USB differential data pairs for Port 1</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB2+USB2-</td><td>A43A42</td><td>USB differential data pairs for Port 2</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB3+USB3-</td><td>B43B42</td><td>USB differential data pairs for Port 3</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB4+USB4-</td><td>A40A39</td><td>USB differential data pairs for Port 4</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB5+USB5-</td><td>B40B39</td><td>USB differential data pairs for Port 5</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB6+USB6-</td><td>A37A36</td><td>USB differential data pairs for Port 6</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB7+USB7-</td><td>B37B37</td><td>USB differential data pairs for Port 7</td><td>I/O3.3VSB</td><td></td><td>USB 1.1/ 2.0 compliant</td></tr><tr><td>USB_0_1_OC#</td><td>B44</td><td>USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_2_3_OC#</td><td>A44</td><td>USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_4_5_OC#</td><td>B38</td><td>USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB_6_7_OC#</td><td>A38</td><td>USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td>Do not pull high on carrier</td></tr><tr><td>USB0_HOST_PRSNT</td><td>B48</td><td>Module USB client may detect the presence of a USB host on USB0. A high value indicates that a host is present.</td><td>I 3.3VSB</td><td></td><td>The detection pin of the chipset is connected to B48 on the module (USB0_HOST_PRSNT), but the function is not on the platform vendor&#x27;s support list.Not supported</td></tr></table>

3.3.10. USB Root Segmentation

<table><tr><td>USB on COMe Module</td><td>HSIO Function on PCH</td><td>Comment</td></tr><tr><td>USB 0</td><td>USB 3.1 #1</td><td rowspan="4">All USB are from XHCI controllers.</td></tr><tr><td>USB 1</td><td>USB 3.1 #2</td></tr><tr><td>USB 2</td><td>USB 3.1 #3</td></tr><tr><td>USB 3</td><td>USB 3.1 #4</td></tr></table>

3.3.11. SPI (BIOS only)

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPI_CS#</td><td>B97</td><td>Chip select for Carrier Board SPI BIOS Flash.</td><td>O 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SPI_MISO</td><td>A92</td><td>Data in to module from carrier board SPI BIOS flash.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_MOSI</td><td>A95</td><td>Data out from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_CLK</td><td>A94</td><td>Clock from module to carrier board SPI BIOS flash.</td><td>O 3.3VSB</td><td></td><td></td></tr><tr><td>SPI_POWER</td><td>A91</td><td>Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V.The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER.SPI_POWER shall only be used to power SPI devices on the Carrier</td><td>OP3.3VSB</td><td></td><td></td></tr><tr><td>BIOS_DIS0#</td><td>A34</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not-connected.</td></tr><tr><td>BIOS_DIS1#</td><td>B88</td><td>Selection strap to determine the BIOS boot device.</td><td>I</td><td>PU 10K3.3VSB</td><td>Carrier shall pull to GND or leave not-connected</td></tr></table>

# 3.3.12. Miscellaneous

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SPKR</td><td>B32</td><td>Output for audio enunciator, the “speaker” in PC-AT systems</td><td>O 3.3V</td><td></td><td></td></tr><tr><td>WDT</td><td>B27</td><td>Output indicating that a watchdog time-out event has occurred.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>THRM#</td><td>B35</td><td>Input from off-module temp sensor indicating an over-temp situation.</td><td>I 3.3VSB</td><td></td><td></td></tr><tr><td>THRMTRIP#</td><td>A35</td><td>Active low output indicating that the CPU has entered thermal shutdown.</td><td>O 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>FAN_PWMOUT</td><td>B101</td><td>Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.</td><td>O OD 3.3V</td><td></td><td>There shall be PD on carrier board</td></tr><tr><td>FAN_TACHIN</td><td>B102</td><td>Fan tachometer input for a fan with a two pulse output.</td><td>I OD 3.3V</td><td>PU 47K 3.3V</td><td></td></tr><tr><td>TPM_PP</td><td>A96</td><td>Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.</td><td>I 3.3V</td><td>PD 100K</td><td>PD only when TPM on module. Modules implementing a TPM shall pull down</td></tr></table>

# 3.3.13. SMBus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SMB_CK</td><td>B13</td><td>System Management Bus bidirectional clock line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>SMB_DAT#</td><td>B14</td><td>System Management Bus bidirectional data line. Power sourced through 3.3V standby rail and main power rails.</td><td>I/O OD3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>SMB_ALERT#</td><td>B15</td><td>System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 3.3V standby rail and main power rails.</td><td>I 3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr></table>

# 3.3.14. I2C Bus

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>I2C_CK</td><td>B33</td><td>General purpose I2C port clock output/input</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source SEMA BMC as default (chipset by build option)</td></tr><tr><td>I2C_DAT</td><td>B34</td><td>General purpose I2C port data I/O line</td><td>I/O OD 3.3VSB</td><td>PU 2.2K 3.3VSB</td><td>Source SEMA BMC as default (chipset by build option)</td></tr></table>

3.3.15. General Purpose I/O (GPIO)

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>GPO[0]</td><td>A93</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[1]</td><td>B54</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[2]</td><td>B57</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPO[3]</td><td>B63</td><td>General purpose output pins.</td><td>O 3.3V</td><td>PD 10K 3.3V</td><td>After hardware RESET output low</td></tr><tr><td>GPI[0]</td><td>A54</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[1]</td><td>A63</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[2]</td><td>A67</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr><tr><td>GPI[3]</td><td>A85</td><td>General purpose input pins.Pulled high internally on the module.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td></td></tr></table>

3.3.16. Serial Interface Signals

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>SER0_TX</td><td>A98</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER0_RX</td><td>A99</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr><tr><td>SER1_TX</td><td>A101</td><td>General purpose serial port transmitter</td><td>O CMOS 3.3V</td><td></td><td>Power rail tolerance 5V, 12VThere shall be PD on carrier board</td></tr><tr><td>SER1_RX</td><td>A102</td><td>General purpose serial port receiver</td><td>I CMOS 3.3V</td><td>PU 10K 3.3V</td><td>Power rail tolerance 5V, 12V</td></tr></table>

Note: UART (SER) default support from SOC. A on-board LPC-to-UART IC is supported by BOM option.

3.3.17. Power and System Management

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PWRBTN#</td><td>B12</td><td>Power button to bring system out of S5 (soft off), active on falling edge.</td><td>I3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>SYS_RESET#</td><td>B49</td><td>Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.</td><td>I3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>CB_RESET#</td><td>B50</td><td>Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.</td><td>O3.3V</td><td></td><td></td></tr><tr><td>PWR_OK</td><td>B24</td><td>Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.</td><td>I3.3VSB</td><td>PU 10K3.3VSB</td><td>Should have weak pull up.</td></tr><tr><td>SUS_STAT#</td><td>B18</td><td>Indicates imminent suspend operation; used to notify LPC devices.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>SUS_S3#</td><td>A15</td><td>Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.</td><td>O3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>SUS_S4#</td><td>A18</td><td>Indicates system is in Suspend to Disk state. Active low output.</td><td>O3.3VSB</td><td>PD 100K</td><td></td></tr><tr><td>SUS_S5#</td><td>A24</td><td>Indicates system is in Soft Off state.</td><td>O3.3VSB</td><td></td><td></td></tr><tr><td>WAKE0#</td><td>B66</td><td>PCI Express wake up signal.</td><td>I3.3VSB</td><td>PU 8.2K3.3VSB</td><td></td></tr><tr><td>WAKE1#</td><td>B67</td><td>General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity.</td><td>I3.3VSB</td><td>PU 8.2K3.3VSB</td><td>Connect to WAKE 0#</td></tr><tr><td>BATLOW#</td><td>A27</td><td>Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.</td><td>I3.3VSB</td><td>PU 10K3.3VSB</td><td></td></tr><tr><td>LID#</td><td>A103</td><td>LID button. Low active signal used by the ACPI operating system for a LID switch.</td><td>I OD3.3VSB</td><td>PU 47K3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>SLEEP#</td><td>B103</td><td>Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.</td><td>I OD3.3VSB</td><td>PU 47K3.3VSB</td><td>Emulated on GPIO (BIOS)</td></tr><tr><td>RAPID_SHUTDOWN</td><td>C67</td><td>Trigger for Rapid Shutdown. Must be driven to 5V though a &lt;=50 ohm source impedance for ≥ 20 μs.</td><td>I CMOS5VSB</td><td>PD 100K</td><td>Not supported</td></tr></table>

# 3.3.18. Power and Ground

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>A104-A109B104-B109</td><td>Primary power input: +12V nominal (wide range 8.5 ~ 20V).All available VCC_12V pins on the connector(s) shall be used.</td><td>P</td><td></td><td>5-20 V</td></tr><tr><td>VCC_5V_S BY</td><td>B84-B87</td><td>Standby power input: +5.0V nominal. See section 7 “Electrical Specifications” for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.</td><td>P</td><td></td><td>5Vsb ±5%</td></tr><tr><td>VCC_RTC</td><td>A47</td><td>Real-time clock circuit-power input. Nominally +3.0V.</td><td>P</td><td></td><td></td></tr><tr><td>GND</td><td>A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21,B31, B41, B51, B60, B70, B80, B90, B100, B110</td><td>Ground - DC power and signal and AC signal return path.</td><td>P</td><td></td><td></td></tr></table>

# 3.4. CD Signal Descriptions

# 3.4.1. USB 3.0 Extension

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>USB_SSRX0-USB_SSRX0+</td><td>C3C4</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB0</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX0-USB_SSTX0+</td><td>D3D4</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB0</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX1-USB_SSRX1+</td><td>C6C7</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB1</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX1-USB_SSTX1+</td><td>D6D7</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX2-USB_SSRX2+</td><td>C9C10</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX2-USB_SSTX2+</td><td>D9D10</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>USB_SSRX3-USB_SSRX3+</td><td>C12C13</td><td>Additional Receive signal differential pairs for the SuperSpeed USB data path on USB3</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>USB_SSTX3-USB_SSTX3+</td><td>D12D13</td><td>Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB3</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr></table>

# 3.4.2. PCI Express x1

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PCIE_TX6+PCIE_TX6-</td><td>D19D20</td><td>PCI Express channel 6, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX6+PCIE_RX6-</td><td>C19C20</td><td>PCI Express channel 6, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr><tr><td>PCIE_TX7+PCIE_TX7-</td><td>D22D23</td><td>PCI Express channel 7, Transmit Output differential pair.</td><td>O PCIE</td><td></td><td>AC coupled on module</td></tr><tr><td>PCIE_RX7+PCIE_RX7-</td><td>C22C23</td><td>PCI Express channel 7, Receive Input differential pair.</td><td>I PCIE</td><td></td><td>AC coupled off module</td></tr></table>

Maximum 5 PCIe devices for PCIe 0-7 and PCIe 16

# 3.4.3. DDI Channels

DDI 1

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>DDI1_PAIR0+</td><td>D26</td><td rowspan="14">Digital Display Interface1 differential pairs</td><td rowspan="14">O PCIE</td><td rowspan="14"></td><td rowspan="14">AC coupled off Module Pair 4 to Pair 6 Not supported</td></tr><tr><td>DDI1_PAIR0-</td><td>D27</td></tr><tr><td>DDI1_PAIR1+</td><td>D29</td></tr><tr><td>DDI1_PAIR1-</td><td>D30</td></tr><tr><td>DDI1_PAIR2+</td><td>D32</td></tr><tr><td>DDI1_PAIR2-</td><td>D33</td></tr><tr><td>DDI1_PAIR3+</td><td>D36</td></tr><tr><td>DDI1_PAIR3-</td><td>D37</td></tr><tr><td>DDI1_PAIR4+</td><td>C25</td></tr><tr><td>DDI1_PAIR4-</td><td>C26</td></tr><tr><td>DDI1_PAIR5+</td><td>C29</td></tr><tr><td>DDI1_PAIR5-</td><td>C30</td></tr><tr><td>DDI1_PAIR6+</td><td>C15</td></tr><tr><td>DDI1_PAIR6-</td><td>C16</td></tr><tr><td>DDI1_HPD</td><td>C24</td><td>Digital Display Interface Hot-Plug Detect</td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td rowspan="2">DDI1_CTRLCLK_AUX+</td><td rowspan="2">D15</td><td>If DDI1_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PD 100K</td><td>AC couple on Module DP1_AUX+</td></tr><tr><td>If DDI1_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI1_CTRLCLK PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td rowspan="2">DDI1_CTRLDATA_AUX-</td><td rowspan="2">D16</td><td>If DDI1_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PU 100K 3.3V</td><td>AC couple on Module DP1_AUX-</td></tr><tr><td>If DDI1_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI1_CTRLDATA PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td>DDI1_DDC_AUX_SEL</td><td>D34</td><td>Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module.If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.</td><td>I 3.3V</td><td>PD 1M</td><td></td></tr></table>

DDI 2

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>DDI2_PAIR0+</td><td>D39</td><td rowspan="8">Digital Display Interface2 differential pairs</td><td rowspan="8">O PCIE</td><td rowspan="8"></td><td rowspan="8">AC coupled off Module</td></tr><tr><td>DDI2_PAIR0-</td><td>D40</td></tr><tr><td>DDI2_PAIR1+</td><td>D42</td></tr><tr><td>DDI2_PAIR1-</td><td>D43</td></tr><tr><td>DDI2_PAIR2+</td><td>D46</td></tr><tr><td>DDI2_PAIR2-</td><td>D47</td></tr><tr><td>DDI2_PAIR3+</td><td>D49</td></tr><tr><td>DDI2_PAIR3-</td><td>D50</td></tr><tr><td>DDI2_HPD</td><td>D44</td><td></td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td rowspan="2">DDI2_CTRLCLK_AUX+</td><td rowspan="2">C32</td><td>If DDI2_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PD 100K</td><td>AC couple on Module DP2_AUX+</td></tr><tr><td>If DDI2_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI2_CTRLCLK PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td rowspan="2">DDI2_CTRLDATA_AUX-</td><td rowspan="2">C33</td><td>If DDI2_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PU 100K 3.3V</td><td>AC couple on Module DP2_AUX-</td></tr><tr><td>If DDI2_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI2_CTRLDATA PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td>DDI2_DDC_AUX_SEL</td><td>C34</td><td>Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.</td><td>I 3.3V</td><td>PD 1M</td><td></td></tr></table>

DDI 3 (Not supported on this product)

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>DDI3_PAIR0+</td><td>C39</td><td rowspan="8">Digital Display Interface3 differential pairs</td><td rowspan="8">O PCIE</td><td rowspan="8"></td><td rowspan="8">AC coupled off Module</td></tr><tr><td>DDI3_PAIR0-</td><td>C40</td></tr><tr><td>DDI3_PAIR1+</td><td>C42</td></tr><tr><td>DDI3_PAIR1-</td><td>C43</td></tr><tr><td>DDI3_PAIR2+</td><td>C46</td></tr><tr><td>DDI3_PAIR2-</td><td>C47</td></tr><tr><td>DDI3_PAIR3+</td><td>C49</td></tr><tr><td>DDI3_PAIR3-</td><td>C50</td></tr><tr><td>DDI3_HPD</td><td>C44</td><td></td><td>I 3.3V</td><td>PD 100K</td><td></td></tr><tr><td rowspan="2">DDI3_CTRLCLK_AUX+</td><td rowspan="2">C36</td><td>If DDI3_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PD 100K</td><td>AC couple on Module DP3_AUX+</td></tr><tr><td>If DDI3_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI3_CTRLCLK PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td rowspan="2">DDI3_CTRLDATA_AUX-</td><td rowspan="2">C37</td><td>If DDI3_DDC_AUX_SEL is floating</td><td>I/O PCIE</td><td>PU 100K 3.3V</td><td>AC couple on Module DP3_AUX-</td></tr><tr><td>If DDI3_DDC_AUX_SEL pulled high</td><td>I/O OD 3.3V</td><td></td><td>HDMI3_CTRLDATA PU 2.2K 3.3V when DDC_AUX_SEL is high</td></tr><tr><td>DDI3_DDC_AUX_SEL</td><td>C38</td><td>Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.</td><td>I 3.3V</td><td>PD 1M</td><td></td></tr></table>

3.4.4. DDI to DP/HDMI Mapping

<table><tr><td>Pin</td><td>Pin Name</td><td>DP</td><td>HDMI / DVI</td></tr><tr><td>D26</td><td>DDI1_PAIR0+</td><td>DP1_LANE0+</td><td>TMDS1_DATA2+</td></tr><tr><td>D27</td><td>DDI1_PAIR0-</td><td>DP1_LANE0-</td><td>TMDS1_DATA2-</td></tr><tr><td>D29</td><td>DDI1_PAIR1+</td><td>DP1_LANE1+</td><td>TMDS1_DATA1+</td></tr><tr><td>D30</td><td>DDI1_PAIR1-</td><td>DP1_LANE1-</td><td>TMDS1_DATA1-</td></tr><tr><td>D32</td><td>DDI1_PAIR2+</td><td>DP1_LANE2+</td><td>TMDS1_DATA0+</td></tr><tr><td>D33</td><td>DDI1_PAIR2-</td><td>DP1_LANE2-</td><td>TMDS1_DATA0-</td></tr><tr><td>D36</td><td>DDI1_PAIR3+</td><td>DP1_LANE3+</td><td>TMDS1_CLK+</td></tr><tr><td>D37</td><td>DDI1_PAIR3-</td><td>DP1_LANE3-</td><td>TMDS1_CLK-</td></tr><tr><td>C25</td><td>DDI1_PAIR4+</td><td></td><td></td></tr><tr><td>C26</td><td>DDI1_PAIR4-</td><td></td><td></td></tr><tr><td>C29</td><td>DDI1_PAIR5+</td><td></td><td></td></tr><tr><td>C30</td><td>DDI1_PAIR5-</td><td></td><td></td></tr><tr><td>C15</td><td>DDI1_PAIR6+</td><td></td><td></td></tr><tr><td>C16</td><td>DDI1_PAIR6-</td><td></td><td></td></tr><tr><td>C24</td><td>DDI1_HPD</td><td>DP1_HPD</td><td>HDMI1_HPD</td></tr><tr><td>D15</td><td>DDI1_CTRLCLK_AUX+</td><td>DP1_AUX+</td><td>HMDI1_CTRLCLK</td></tr><tr><td>D16</td><td>DDI1_CTRLDATA_AUX-</td><td>DP1_AUX-</td><td>HMDI1_CTRLDATA</td></tr><tr><td>D34</td><td>DDI1_DDC_AUX_SEL</td><td></td><td></td></tr><tr><td>D39</td><td>DDI2_PAIR0+</td><td>DP2_LANE0+</td><td>TMDS2_DATA2+</td></tr><tr><td>D40</td><td>DDI2_PAIR0-</td><td>DP2_LANE0-</td><td>TMDS2_DATA2-</td></tr><tr><td>D42</td><td>DDI2_PAIR1+</td><td>DP2_LANE1+</td><td>TMDS2_DATA1+</td></tr><tr><td>D43</td><td>DDI2_PAIR1-</td><td>DP2_LANE1-</td><td>TMDS2_DATA1-</td></tr><tr><td>D46</td><td>DDI2_PAIR2+</td><td>DP2_LANE2+</td><td>TMDS2_DATA0+</td></tr><tr><td>D47</td><td>DDI2_PAIR2-</td><td>DP2_LANE2-</td><td>TMDS2_DATA0-</td></tr><tr><td>D49</td><td>DDI2_PAIR3+</td><td>DP2_LANE3+</td><td>TMDS2_CLK+</td></tr><tr><td>D50</td><td>DDI2_PAIR3-</td><td>DP2_LANE3-</td><td>TMDS2_CLK-</td></tr><tr><td>D44</td><td>DDI2_HPD</td><td>DP2_HPD</td><td>HDMI2_HPD</td></tr><tr><td>C32</td><td>DDI2_CTRLCLK_AUX+</td><td>DP2_AUX+</td><td>HDMI2_CTRLCLK</td></tr><tr><td>C33</td><td>DDI2_CTRLDATA_AUX-</td><td>DP2_AUX-</td><td>HDMI2_CTRLDATA</td></tr><tr><td>C34</td><td>DDI2_DDC_AUX_SEL</td><td></td><td></td></tr><tr><td>C39</td><td>DDI3_PAIR0+</td><td>DP3_LANE0+</td><td>TMDS3_DATA2+</td></tr><tr><td>C40</td><td>DDI3_PAIR0-</td><td>DP3_LANE0-</td><td>TMDS3_DATA2-</td></tr><tr><td>C42</td><td>DDI3_PAIR1+</td><td>DP3_LANE1+</td><td>TMDS3_DATA1+</td></tr><tr><td>C43</td><td>DDI3_PAIR1-</td><td>DP3_LANE1-</td><td>TMDS3_DATA1-</td></tr><tr><td>C46</td><td>DDI3_PAIR2+</td><td>DP3_LANE2+</td><td>TMDS3_DATA0+</td></tr><tr><td>C47</td><td>DDI3_PAIR2-</td><td>DP3_LANE2-</td><td>TMDS3_DATA0-</td></tr><tr><td>C49</td><td>DDI3_PAIR3+</td><td>DP3_LANE3+</td><td>TMDS3_CLK+</td></tr><tr><td>C50</td><td>DDI3_PAIR3-</td><td>DP3_LANE3-</td><td>TMDS3_CLK-</td></tr><tr><td>C44</td><td>DDI3_HPD</td><td>DP3_HPD</td><td>HDMI3_HPD</td></tr><tr><td>C36</td><td>DDI3_CTRLCLK_AUX+</td><td>DP3_AUX+</td><td>HDMI3_CTRLCLK</td></tr><tr><td>C37</td><td>DDI3_CTRLDATA_AUX-</td><td>DP3_AUX-</td><td>HDMI3_CTRLDATA</td></tr><tr><td>C38</td><td>DDI3_DDC_AUX_SEL</td><td></td><td></td></tr></table>

3.4.5. PCI Express Graphics (PEG)

<table><tr><td>Signal</td><td>Pin</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>PEG_RX0+</td><td>C52</td><td rowspan="32">PCI Express Graphics transmit differential pairs.</td><td rowspan="32">I PCIE</td><td rowspan="32"></td><td rowspan="32">Only support PEG 0 (PCIe lane 16) by BOM option, replace of SATA port 2Rest of lanes are Not supportedAC couple off module</td></tr><tr><td>PEG_RX0-</td><td>C53</td></tr><tr><td>PEG_RX1+</td><td>C55</td></tr><tr><td>PEG_RX1-</td><td>C56</td></tr><tr><td>PEG_RX2+</td><td>C58</td></tr><tr><td>PEG_RX2-</td><td>C59</td></tr><tr><td>PEG_RX3+</td><td>C61</td></tr><tr><td>PEG_RX3-</td><td>C62</td></tr><tr><td>PEG_RX4+</td><td>C65</td></tr><tr><td>PEG_RX4-</td><td>C66</td></tr><tr><td>PEG_RX5+</td><td>C68</td></tr><tr><td>PEG_RX5-</td><td>C69</td></tr><tr><td>PEG_RX6+</td><td>C71</td></tr><tr><td>PEG_RX6-</td><td>C72</td></tr><tr><td>PEG_RX7+</td><td>C74</td></tr><tr><td>PEG_RX7-</td><td>C75</td></tr><tr><td>PEG_RX8+</td><td>C78</td></tr><tr><td>PEG_RX8-</td><td>C79</td></tr><tr><td>PEG_RX9+</td><td>C81</td></tr><tr><td>PEG_RX9-</td><td>C82</td></tr><tr><td>PEG_RX10+</td><td>C85</td></tr><tr><td>PEG_RX10-</td><td>C86</td></tr><tr><td>PEG_RX11+</td><td>C88</td></tr><tr><td>PEG_RX11-</td><td>C89</td></tr><tr><td>PEG_RX12+</td><td>C91</td></tr><tr><td>PEG_RX12-</td><td>C92</td></tr><tr><td>PEG_RX13+</td><td>C94</td></tr><tr><td>PEG_RX13-</td><td>C95</td></tr><tr><td>PEG_RX14+</td><td>C98</td></tr><tr><td>PEG_RX14-</td><td>C99</td></tr><tr><td>PEG_RX15+</td><td>C101</td></tr><tr><td>PEG_RX15</td><td>C102</td></tr><tr><td>PEG_TX0+</td><td>D52</td><td rowspan="31">PCI Express Graphics receive differential pairs.</td><td rowspan="31">O PCIE</td><td rowspan="31"></td><td rowspan="31">Only support PEG 0 (PCIe lane 16) by BOM option, replace of SATA port 2Rest of lanes are Not supportedAC couple on module</td></tr><tr><td>PEG_TX0-</td><td>D53</td></tr><tr><td>PEG_TX1+</td><td>D55</td></tr><tr><td>PEG_TX1-</td><td>D56</td></tr><tr><td>PEG_TX2+</td><td>D58</td></tr><tr><td>PEG_TX2-</td><td>D59</td></tr><tr><td>PEG_TX3+</td><td>D61</td></tr><tr><td>PEG_TX3-</td><td>D62</td></tr><tr><td>PEG_TX4+</td><td>D65</td></tr><tr><td>PEG_TX4-</td><td>D66</td></tr><tr><td>PEG_TX5+</td><td>D68</td></tr><tr><td>PEG_TX5-</td><td>D69</td></tr><tr><td>PEG_TX6+</td><td>D71</td></tr><tr><td>PEG_TX6-</td><td>D72</td></tr><tr><td>PEG_TX7+</td><td>D74</td></tr><tr><td>PEG_TX7-</td><td>D75</td></tr><tr><td>PEG_TX8+</td><td>D78</td></tr><tr><td>PEG_TX8-</td><td>D79</td></tr><tr><td>PEG_TX9+</td><td>D81</td></tr><tr><td>PEG_TX9-</td><td>D82</td></tr><tr><td>PEG_TX10+</td><td>D85</td></tr><tr><td>PEG_TX10-</td><td>D86</td></tr><tr><td>PEG_TX11+</td><td>D88</td></tr><tr><td>PEG_TX11-</td><td>D89</td></tr><tr><td>PEG_TX12+</td><td>D91</td></tr><tr><td>PEG_TX12-</td><td>D92</td></tr><tr><td>PEG_TX13+</td><td>D94</td></tr><tr><td>PEG_TX13-</td><td>D95</td></tr><tr><td>PEG_TX14+</td><td>D98</td></tr><tr><td>PEG_TX14-</td><td>D99</td></tr><tr><td>PEG_TX15+</td><td>D101</td></tr><tr><td>PEG_TX15-</td><td>D102</td><td></td><td></td><td></td><td></td></tr><tr><td>PEG_LANE_RV#</td><td>D54</td><td>PCI Express Graphics lane reversal input strap.Pull low on the Carrier board to reverse lane order.</td><td>I 3.3V</td><td>PU 10K 3.3V</td><td>Not supported</td></tr></table>

# 3.4.6. Module Type Definition

<table><tr><td>Signal</td><td>Pin #</td><td colspan="4">Description</td><td>I/O</td><td>Comment</td></tr><tr><td>TYPE0#</td><td>C54</td><td rowspan="2" colspan="4">The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don&#x27;t care (X).</td><td rowspan="3"></td><td rowspan="3">Type 6</td></tr><tr><td>TYPE1#</td><td>C57</td></tr><tr><td>TYPE2#</td><td>D57</td><td>TYPE2#</td><td>TYPE1#</td><td>TYPE0#</td><td></td></tr><tr><td></td><td></td><td>X</td><td>X</td><td>X</td><td>Pinout Type 1</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>NC</td><td>Pinout Type 2</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>NC</td><td>GND</td><td>Pinout Type 3 (no IDE)</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>NC</td><td>Pinout Type 4 (no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td>NC</td><td>GND</td><td>GND</td><td>Pinout Type 5 (no IDE, no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td>GND</td><td>NC</td><td>NC</td><td>Pinout Type 6 (no IDE, no PCI)</td><td></td><td></td></tr><tr><td></td><td></td><td>GND</td><td>NC</td><td>GND</td><td>Pinout Type 7</td><td></td><td></td></tr><tr><td></td><td></td><td colspan="4">The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.</td><td></td><td></td></tr></table>

# 3.4.7. Power and Ground

<table><tr><td>Signal</td><td>Pin #</td><td>Description</td><td>I/O</td><td>PU/PD</td><td>Comment</td></tr><tr><td>VCC_12V</td><td>C104-C109D104-D109</td><td>Primary power input: +12V nominal (wide range 5 - 20V).All available VCC_12V pins on the connector(s) shall be used</td><td>P</td><td></td><td>5-20V</td></tr><tr><td>GND</td><td>C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70, C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110</td><td>Ground - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to carrier board GND plane.</td><td>P</td><td></td><td></td></tr></table>

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# 4. Connector Pinouts on Module

This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification

# 4.1. Connector, Switch and LED Locations

![BIOS Defaults\nReset Switch\n4-pin Fan\nAB\nGD\nLED1\nLED2\nLED3\nSoC\nKeep out\n40-pin Debug\nConnector](.cexpress-wl-50m-00029-1020-12/dddfa63b564fbe3c864922aa979f06545bf09fd3dfda9e46d937b8eb8d60ac86.jpg)

![Keep out](.cexpress-wl-50m-00029-1020-12/6085509fdca99fa68623d23e71f3f51a4dc42b1e438a23a0022e84996cd24dae.jpg)

Figure 3: cExpress-WL Connector, Switch and LED Locations

# cExpress-WL and the DB40 Debug Module

For illustration purposes only

![Two electronic circuit boards with visible components and connectors, one showing a flexible ribbon cable (no text or symbols)](.cexpress-wl-50m-00029-1020-12/9574523e56d846da680c42d63c68032ccbc5dc07e5b1b6c6d4d15fc290c9933a.jpg)

Figure 4: Compact Size COM Express Module and DB40 Debug Module

# 4.2. 40-pin Debug Connector

FPC Connector Type: FCI 59GF Flex 10042867

Pin Orientation
![Close-up of a green printed circuit board with a black connector and gold contacts, labeled with numbers 1 and 40 (no readable text beyond labels)](.cexpress-wl-50m-00029-1020-12/baea05de8fc4e612850c6189ebe1bef2050bf7359abbce44a89383c24082788a.jpg)

40-pin Debug Connector Pin Definition on the COM Express Module

<table><tr><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td></tr><tr><td>40</td><td rowspan="7">SPI Program interface</td><td>VCC_SPI_IN</td><td>SPI Power Input from flash tool to module. HW need add MOS FET to switch SPI power for SPI ROM</td></tr><tr><td>39</td><td>GND</td><td></td></tr><tr><td>38</td><td>SPI_BIOS_CS 0#</td><td></td></tr><tr><td>37</td><td>SPI_BIOS_CS 1#</td><td></td></tr><tr><td>36</td><td>SPI_BIOS_MI SO</td><td></td></tr><tr><td>35</td><td>SPI_BIOS_M OSI</td><td></td></tr><tr><td>34</td><td>SPI_BIOS_CLK</td><td></td></tr><tr><td>33</td><td rowspan="10">LPC Bus</td><td>3V3_LPC</td><td>System power 3.3V provide from COM module</td></tr><tr><td>32</td><td>GND</td><td></td></tr><tr><td>31</td><td>BIOS_DIS0</td><td></td></tr><tr><td>30</td><td>RST#</td><td></td></tr><tr><td>29</td><td>CLK33_LPC</td><td></td></tr><tr><td>28</td><td>LPC_FRAME #</td><td></td></tr><tr><td>27</td><td>LPC_AD3</td><td></td></tr><tr><td>26</td><td>LPC_AD2</td><td></td></tr><tr><td>25</td><td>LPC_AD1</td><td>always power 3.3V provide from COM module</td></tr><tr><td>24</td><td>LPC_AD0</td><td></td></tr><tr><td>23</td><td rowspan="3">BMC Program interface</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td></tr><tr><td>22</td><td>3.3V_BMC</td><td>always power 3.3V provide from COM module</td></tr><tr><td>21</td><td>GND</td><td></td></tr></table>

<table><tr><td>Pin</td><td>Interface</td><td>Signal</td><td>Remark</td></tr><tr><td>20</td><td rowspan="8">BMC Program interface (cont&#x27;d)</td><td>TXD6</td><td></td></tr><tr><td>19</td><td>RXD6</td><td></td></tr><tr><td>18</td><td>FUMD0</td><td></td></tr><tr><td>17</td><td>RESET_IN#</td><td></td></tr><tr><td>16</td><td>DATA</td><td></td></tr><tr><td>15</td><td>CLK</td><td></td></tr><tr><td>14</td><td>OCD0A</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>13</td><td>OCD0B</td><td>Include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_BMC</td></tr><tr><td>12</td><td rowspan="7">Test points</td><td>PWRBTN#</td><td></td></tr><tr><td>11</td><td>SYS_RESET#</td><td></td></tr><tr><td>10</td><td>CB_RESET#</td><td></td></tr><tr><td>9</td><td>CB_PWROK</td><td></td></tr><tr><td>8</td><td>SUS_S3#</td><td></td></tr><tr><td>7</td><td>SUS_S4#</td><td></td></tr><tr><td>6</td><td>SUS_S5#</td><td></td></tr><tr><td>5</td><td rowspan="4">BMC Debug signals</td><td>POSTWDT_DIS #</td><td>Connect to Jumper for Debug</td></tr><tr><td>4</td><td>SEL_BIOS</td><td>Connect to Jumper for Debug</td></tr><tr><td>3</td><td>BIOS_MODE</td><td>Connect to Jumper for Debug</td></tr><tr><td>2</td><td>BMC_STATUS</td><td></td></tr><tr><td>1</td><td>Reserved</td><td></td><td></td></tr></table>

Table 2: 40-pin Debug Connector Pin Definition
Note: The pin definition on the debug module is the inverse of that on the COM Express module.

# 4.3. Status LEDs

To facilitate easier maintenance, status LED's are mounted on the board.

![Close-up of a green printed circuit board with various electronic components and traces (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/36cc86c08b12ab557a900f0066812bcb8b6c987dd1dbea27337d5d5112d323cf.jpg)

LED1 LED2 LED3

LED Descriptions

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC output</td><td>Power Sequence Status Code (BMC)Power Changes, RESET(see 5.1.4 Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source 3Vcc</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>BMC outputand same signal as WDT (B27) on BtB connector</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

Table 3: cExpress-WL LED Descriptions

# 4.4. Fan Connector

Connector Type: JVE 24W1125A-04M00

Pin Orientation
![Close-up of a green printed circuit board with various electronic components and connectors (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/ff91c3122c14df98903666efb30427b4b4664020837ff213d6919b4225d7fa09.jpg)

1 2 3 4
Pin Assignment

<table><tr><td>Name</td><td>Description</td></tr><tr><td>1</td><td>FAN_PWMOUT</td></tr><tr><td>2</td><td>FAN_TACHIN</td></tr><tr><td>3</td><td>Ground</td></tr><tr><td>4</td><td>5V</td></tr></table>

Table 4: Fan Connector Pin Definition

# 4.5. BIOS Setup Defaults Reset Button

![Close-up of a green printed circuit board with electronic components and a circular component (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/45ba797efb799cb894683d5ce0d48f26b29dc879ff282385786dd9f8661682ae.jpg)

To perform a hardware reset of BIOS default settings, perform the following steps:

1. Shut down the system.
2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears
3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.cexpress-wl-50m-00029-1020-12/167826c4ce0f85652f97715b4221f65b01ba29ec62b5a253e271c1c56fb1fbaa.jpg)

# 4.6. Switch Settings

Switch Locations

![Close-up of a green printed circuit board with multiple chips and electronic components (no readable text or symbols)](.cexpress-wl-50m-00029-1020-12/94953d7c72a831d365546796d153ba7fbd541ce9840611e00aa4323059981979.jpg)

BIOS Select and Mode Configuration Switch
Figure 5: cExpress-WL Switch Locations

# 4.6.1. BIOS Select and Mode Configuration Switch

The module has two BIOS chips and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using BIOS Select and Mode Configuration Switch, Pin 2.

Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier.

In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated.

In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1.

<table><tr><td>Mode</td><td>Pin 1</td><td>Pin 2</td></tr><tr><td>Boot from SPI0 (default)</td><td>On</td><td>—</td></tr><tr><td>Boot from SPI1</td><td>Off</td><td>—</td></tr><tr><td>Set BIOS to PICMG mode</td><td>—</td><td>On</td></tr><tr><td>Set BIOS to Failsafe BIOS mode (default)</td><td>—</td><td>Off</td></tr></table>

Table 5: BIOS Select and Mode Configuration Switch Settings

# 5. Smart Embedded Management Agent (SEMA)

The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented:

• Total operating hours counter. Counts the number of hours the module has been run in minutes.
- On-time minutes counter. Counts the seconds since last system start.
- Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash.
• Power cycles counter
- Boot counter. Counts the number of boot attempts.
- Watchdog Timer. Set/Reset/Disable Watchdog Timer. Features auto-reload at power-up.
• System Restart Cause. Power loss/BIOS Fail/Watchdog/Internal Reset/External Reset
- Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS. (this feature is suppôt by BOM option, project basis)
• Flash area. 1kB Flash area for customer data
• 2K Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
• Board Identify. Vendor/Board/Serial number/Production Date
• Main-current & voltage. Monitors drawn current and main voltages

For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual, downloadable at: http://www.adlinktech.com/sema/.

# 5.1. Board Specific SEMA Functions

# 5.1.1. Voltages

The BMC of the cExpress-WL implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).

<table><tr><td>ADC Channel</td><td>Voltage Name</td><td>Voltage Formula [V]</td></tr><tr><td>0</td><td>VCORE</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>1</td><td>VCC_GT</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>2</td><td>1V05_A</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>3</td><td>VDDQ</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>4</td><td>VRTC</td><td>(MSB&lt;&lt;8 + LSB) x 1.01 x 3.3 / 1024</td></tr><tr><td>5</td><td>V3P3S</td><td>(MSB&lt;&lt;8 + LSB) x 1.1 x 3.3 / 1024</td></tr><tr><td>6</td><td>V3P3A</td><td>(MSB&lt;&lt;8 + LSB) x 1.100 x 3.3 / 1024</td></tr><tr><td>7</td><td>V5S</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>8</td><td>VCCST</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>9</td><td>VCCIO</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>10</td><td>VCCSTG</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>11</td><td>VCCSA</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>12</td><td>1V8_A</td><td>(MSB&lt;&lt;8 + LSB) x 1 x 3.3 / 1024</td></tr><tr><td>13</td><td>V5SBY</td><td>(MSB&lt;&lt;8 + LSB) x 1.826 x 3.3 / 1024</td></tr><tr><td>14</td><td>V12</td><td>(MSB&lt;&lt;8 + LSB) x 6 x 3.3 / 1024</td></tr><tr><td>15</td><td>(MAIN CURRENT)</td><td>Use Main Current Function</td></tr></table>

Table 6: SEMA Onboard Voltage Monitor

# 5.1.2. Main Current

The BMC of the cExpress-WL implements a current monitor. The current can be read by calling the SEMA function "Get Main Current". The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.

$$
\text { Main   Current } = (\text { MSB\_n } &lt;   &lt;   8 + \text { LSB\_n }) \times 8. 0 6 \mathrm{mA}
$$

# 5.1.3. BMC Status

This register shows the status of BMC controlled signals on the cExpress-WL.

&lt;table&gt;<tr><td>Status Bit</td><td>Signal</td></tr><tr><td>0</td><td>WDT_OUT</td></tr><tr><td>1</td><td>LVDS_VDDEN</td></tr><tr><td>2</td><td>LVDS_BKLTEN</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>POSTWDT_DISn</td></tr><tr><td>5</td><td>SEL_BIOS</td></tr><tr><td>6</td><td>BIOS_DIS0n</td></tr><tr><td>7</td><td>BIOS_DIS1n</td></tr></table>

Table 7: SEMA BMC Status

# 5.1.4. Exception Codes

In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception Code” command is not needed or supported.

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_SUSCLK</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>7</td><td>RESET_FAIL</td></tr><tr><td>8</td><td>RESETIN_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RFID_MEMFAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>15</td><td>NO_V1P05S_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>18</td><td>NO_V5SBY</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr></table>

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>20</td><td>NO_V5_DUAL</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr><tr><td>22</td><td>NO_P_5V_3V3_S0_PG</td></tr></table>

Table 8: SEMA Exception Codes

# 5.1.5. BMC Flags

The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.

<table><tr><td>Bit</td><td>Description</td></tr><tr><td>[0 ~ 4]</td><td>Exception Code</td></tr><tr><td>[6]</td><td>0 = AT mode1 = ATX mode</td></tr><tr><td>[7]</td><td>0 = Standard BIOS1 = Fail-safe BIOS.</td></tr></table>

Table 9: SEMA BMC Flags

# 6. System Resources

# 6.1. System Memory Map

<table><tr><td>Address Range (hex)</td><td>Description</td></tr><tr><td>FF000000-FFFFFFFF</td><td>Motherboard resources</td></tr><tr><td>FEE00000-FEEFFFFF</td><td>Motherboard resources</td></tr><tr><td>FED90000-FED93FFF</td><td>Motherboard resources</td></tr><tr><td>FED45000-FED8FFFF</td><td>Motherboard resources</td></tr><tr><td>FED20000-FED3FFFF</td><td>Motherboard resources</td></tr><tr><td>FED19000-FED19FFF</td><td>Motherboard resources</td></tr><tr><td>FED10000-FED17FFF</td><td>Motherboard resources</td></tr><tr><td>FED00000-FED003FF</td><td>High precision event timer</td></tr><tr><td>FC800000-FE7FFFF</td><td>PCI Express Root Complex</td></tr><tr><td>E0000000-EFFFFFFFF</td><td>Motherboard resources</td></tr><tr><td>90000000-DFFFFFFFF</td><td>PCI Express Root Complex</td></tr><tr><td>8BE11000-8BE11FFF</td><td>UCSI USB Connector manager</td></tr><tr><td>40000000-403FFFFFF</td><td>Motherboard resources</td></tr><tr><td>000A0000-000FFFFFF</td><td>PCI Express Root Complex</td></tr><tr><td>00000 – 9CFFF</td><td>System Board</td></tr></table>

# 6.2. I/O Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>20h – 21h</td><td>Interrupt Controller</td></tr><tr><td>24h – 25h</td><td>Interrupt Controller</td></tr><tr><td>28h – 29h</td><td>Interrupt Controller</td></tr><tr><td>2Ch – 2Dh</td><td>Interrupt Controller</td></tr><tr><td>2E-02F</td><td>Super I/O</td></tr><tr><td>30h – 31h</td><td>Interrupt Controller</td></tr><tr><td>34h – 35h</td><td>Interrupt Controller</td></tr><tr><td>38h – 39h</td><td>Interrupt Controller</td></tr><tr><td>3Ch – 3Dh</td><td>Interrupt Controller</td></tr><tr><td>40h – 43h</td><td>System timer</td></tr><tr><td>4Eh – 4Fh</td><td>Microcontroller</td></tr><tr><td>50h – 53h</td><td>System timer</td></tr><tr><td>60h</td><td>Standard PS/2 Keyboard</td></tr><tr><td>61h</td><td>NMI Controller</td></tr><tr><td>62h</td><td>Microcontroller</td></tr><tr><td>63h</td><td>NMI Controller</td></tr><tr><td>64h</td><td>Standard PS/2 Keyboard</td></tr><tr><td>65h</td><td>NMI Controller</td></tr><tr><td>66h</td><td>NMI Controller</td></tr><tr><td>67h</td><td>NMI Controller</td></tr><tr><td>70h</td><td>RTC Controller</td></tr><tr><td>71h</td><td>RTC Controller</td></tr><tr><td>72h</td><td>RTC Controller</td></tr><tr><td>73h</td><td>RTC Controller</td></tr><tr><td>74h</td><td>RTC Controller</td></tr><tr><td>75h</td><td>RTC Controller</td></tr><tr><td>76h – 77h</td><td>RTC Controller</td></tr><tr><td>80h</td><td>LPC/eSPI or PCIe</td></tr><tr><td>84h-86h</td><td>LPC/eSPI or PCIe</td></tr><tr><td>88h</td><td>LPC/eSPI or PCIe</td></tr><tr><td>8Ch-8Eh</td><td>LPC/eSPI or PCIe</td></tr><tr><td>90h</td><td>LPC/eSPI</td></tr><tr><td>92h</td><td>Reset Generator</td></tr><tr><td>94h-96h</td><td>LPC/eSPI</td></tr><tr><td>98h</td><td>LPC/eSPI</td></tr><tr><td>9Ch-9Eh</td><td>LPC/eSPI</td></tr><tr><td>A0h – A1h</td><td>Interrupt Controller</td></tr><tr><td>A4h – A5h</td><td>Interrupt Controller</td></tr><tr><td>A8h – A9h</td><td>Interrupt Controller</td></tr><tr><td>ACh - ADh</td><td>Interrupt Controller</td></tr><tr><td>B0h – B1h</td><td>Interrupt Controller</td></tr><tr><td>B2h – B3h</td><td>Power Management</td></tr><tr><td>B4h – B5h</td><td>Interrupt Controller</td></tr><tr><td>B8h – B9h</td><td>Interrupt Controller</td></tr><tr><td>BCh – BDh</td><td>Interrupt Controller</td></tr><tr><td>200h -207h</td><td>Gameport Low</td></tr><tr><td>208h -20Fh</td><td>Gameport High</td></tr><tr><td>240h – 247h</td><td>Communications Port (COM3)</td></tr><tr><td>248h – 24Fh</td><td>Communications Port (COM4)</td></tr><tr><td>2F8h – 2FFh</td><td>Communications Port (COM2)</td></tr><tr><td>3F8h – 3FFh</td><td>Communications Port (COM1)</td></tr><tr><td>4D0h – 4D1h</td><td>Interrupt Controller</td></tr><tr><td>680h – 69Fh</td><td>Motherboard resources</td></tr><tr><td>6A0h</td><td>Motherboard resources</td></tr><tr><td>CF9h</td><td>Reset Generator</td></tr></table>

# 6.3. Interrupt Request (IRQ) Lines

PIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 4 (COM2)</td><td>IRQ3 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 3 (COM1)</td><td>IRQ4 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port 1 (COM3)</td><td>IRQ5 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>Generic</td><td>IRQ6 via SERIRQ / PIRQ</td><td>No</td></tr><tr><td>7</td><td>Serial Port 2 (COM4)</td><td>IRQ7 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>Real-time clock</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>Generic</td><td>N/A</td><td>Note (1)</td></tr><tr><td>10</td><td>Generic</td><td>IRQ10 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>11</td><td>Generic</td><td>IRQ11 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ / PIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>GSPI, UART, I2C, SDIO</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Gpio</td><td>PIRQ</td><td>Note (1)</td></tr><tr><td>15</td><td>Gpio</td><td>PIRQ</td><td>Note (1)</td></tr></table>

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

APIC Mode

<table><tr><td>IRQ#</td><td>Typical Interrupt Resource</td><td>Connected to Pin</td><td>Available</td></tr><tr><td>0</td><td>Counter 0</td><td>N/A</td><td>No</td></tr><tr><td>1</td><td>Keyboard controller</td><td>IRQ1 via SERIRQ</td><td>No</td></tr><tr><td>2</td><td>Cascade interrupt from slave PIC</td><td>N/A</td><td>No</td></tr><tr><td>3</td><td>Serial Port 4 (COM2)</td><td>IRQ3 via SERIRQ</td><td>Note (1)</td></tr><tr><td>4</td><td>Serial Port 3 (COM1)</td><td>IRQ4 via SERIRQ</td><td>Note (1)</td></tr><tr><td>5</td><td>Serial Port 1 (COM3)</td><td>IRQ5 via SERIRQ</td><td>Note (1)</td></tr><tr><td>6</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>7</td><td>Serial Port 2 (COM4)</td><td>IRQ7 via SERIRQ</td><td>Note (1)</td></tr><tr><td>8</td><td>N/A</td><td>N/A</td><td>No</td></tr><tr><td>9</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>10</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>11</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr><tr><td>12</td><td>PS/2 Mouse</td><td>IRQ12 via SERIRQ</td><td>Note (1)</td></tr><tr><td>13</td><td>Math Processor</td><td>N/A</td><td>Note (1)</td></tr><tr><td>14</td><td>Intel Serial IO GPIO Host Controller</td><td>IRQ14 via SERIRQ</td><td>Note (1)</td></tr><tr><td>15</td><td>N/A</td><td>N/A</td><td>Note (1)</td></tr></table>

Note (1): These IRQs can be used for PCI devices when onboard device is disabled.

6.4. PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Routing</td><td>Description</td></tr><tr><td>00h</td><td>00h</td><td>00h</td><td>N/A</td><td>Intel host Bridge</td></tr><tr><td>00h</td><td>02h</td><td>00h</td><td>Internal</td><td>Intel I.G.D.</td></tr><tr><td>00h</td><td>08h</td><td>00h</td><td>Internal</td><td>Gaussian Mixture Model</td></tr><tr><td>00h</td><td>12h</td><td>00h</td><td>Internal</td><td>Thermal Subsystem</td></tr><tr><td>00h</td><td>14h</td><td>00h</td><td>Internal</td><td>xHCI Controller</td></tr><tr><td>00h</td><td>14h</td><td>02h</td><td>Internal</td><td>Intel RAM</td></tr><tr><td>00h</td><td>14h</td><td>05h</td><td>Internal</td><td>Intel Corporation System Device</td></tr><tr><td>00h</td><td>15h</td><td>00h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>15h</td><td>01</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Internal</td><td>Intel Management Engine Interface</td></tr><tr><td>00h</td><td>16h</td><td>03h</td><td>Internal</td><td>Keyboard and Text (KT) Redirection</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Internal</td><td>Intel AHCI controller</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Internal</td><td>Intel Corporation Controller</td></tr><tr><td>00h</td><td>1Ah</td><td>00h</td><td>Internal</td><td>Intel Corporation System Device</td></tr><tr><td>00h</td><td>1Ch</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Ch</td><td>05h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Ch</td><td>06h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Ch</td><td>07h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Dh</td><td>00h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Dh</td><td>04h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Dh</td><td>05h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Dh</td><td>06h</td><td>Internal</td><td>Intel PCI Express Root port</td></tr><tr><td>00h</td><td>1Fh</td><td>00h</td><td>Internal</td><td>Intel LPC Interface Bridge</td></tr><tr><td>00h</td><td>1Fh</td><td>03h</td><td>Internal</td><td>HDA Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>04h</td><td>Internal</td><td>SMBus Controller</td></tr><tr><td>00h</td><td>1Fh</td><td>05h</td><td>Internal</td><td>SPI</td></tr><tr><td>00h</td><td>1Fh</td><td>06h</td><td>Internal</td><td>GbE Controller</td></tr></table>

# 6.5. PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>IGFX</td><td>LPC Bridge</td><td>HD Audio Controller</td><td>SMBus</td><td>GbE Controller</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td></td><td>INTD:17</td><td></td><td></td><td></td></tr><tr><td>Int2</td><td></td><td>INTC:18</td><td></td><td></td><td></td></tr><tr><td>Int3</td><td></td><td>INTB:19</td><td></td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>SATA Controller</td><td>ME Controller</td><td>XHCI Controller</td><td>Thermal Subsystem</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td></td><td>INTB:17</td><td>INTB:17</td><td>INTB:17</td></tr><tr><td>Int2</td><td></td><td>INTC:18</td><td>INTC:18</td><td>INTC:18</td></tr><tr><td>Int3</td><td></td><td>INTD:19</td><td>INTD:19</td><td>INTD:19</td></tr></table>

<table><tr><td>INT Line</td><td>PCIE Port1</td><td>PCIE Port 2</td><td>PCIE Port 3</td><td>PCIE Port 4</td><td>PCIE Port 5</td><td>PCIE Port 6</td><td>PCIE Port 7</td><td>PCIE Port 8</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:18</td><td>INTB:16</td><td>INTC:17</td><td>INTD:18</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:19</td><td>INTC:17</td><td>INTD:18</td><td>INTA:19</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:16</td><td>INTD:18</td><td>INTA:19</td><td>INTB:16</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:17</td><td>INTA:19</td><td>INTB:16</td><td>INTC:17</td></tr></table>

# 6.6. SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>DDR4 Channel A(SO-DIMM1)</td><td>A0h</td></tr><tr><td>DDR4 Channel B(SO-DIMM2)</td><td>A4h</td></tr><tr><td>Thermal Sensor</td><td>92h</td></tr><tr><td>BMC</td><td>50h</td></tr><tr><td>Extend GPIO (PCA9535)</td><td>40h</td></tr><tr><td>NXP (eDP to LVDS transmitter)</td><td>C0h</td></tr></table>

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# 7. BIOS Setup

# 7.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the Submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS InformationSystem InformationBoard Information ▶System DateSystem Time</td><td>CPU Configuration ▶Graphics Configuration ▶Power Management ▶USB Configuration ▶Network Stack Configuration ▶AMT Configuration ▶System Management ▶Thermal Management ▶Watchdog Timer ▶Super IO Configuration ▶Serial Console Redirection ▶TPM 2.0 Configuration ▶Miscellaneous ▶Network Stack Configuration ▶</td><td>System Agent (SA)Configuration ▶PCH-IOConfiguration ▶</td><td>Password DescriptionSecure Boot Menu ▶</td><td>Boot Configuration</td><td>Save OptionsBoot Override</td></tr></table>

# Notes:

▶ indicates a Submenu
Gray text indicates info only

# 7.2. Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the Submenus and settings.

# 7.2.1. BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vender</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display Core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Display Build Date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display MRC information</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Display GOP version.</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display ME FW version.</td></tr></table>

# 7.2.2. System Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU signature.</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display CPU brand name.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU stepping.</td></tr><tr><td>GT Info</td><td>Info only</td><td>Display GT info of Intel Graphics.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH information.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display PCH stepping.</td></tr><tr><td>Board Information</td><td>Submenu</td><td></td></tr></table>

# 7.2.3. Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC serial number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC last repair date.</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display SMC MAC ID.</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down.</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

# 7.2.4. System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# 7.3. Advanced

This menu contains the settings for most of the user interfaces in the system

7.3.1. CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Package</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU information.</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display CPU Microcode Revision.</td></tr><tr><td>Speed</td><td>Info only</td><td>Display CPU frequency.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel Virtualization Technology support or not.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>Boot performance mode</td><td>Max Battery Max Non-Turbo Performance Turbo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology).</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled Enabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable/Disable processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available and enabled).</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.</td></tr><tr><td>Platform PL1 Power</td><td>0</td><td>Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). For 12.50W, enter12500. This setting will act as the new PL1 value for the Package RAPL algorithm.</td></tr><tr><td>Platform PL1 Time Window</td><td>0</td><td>Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Package C State Limit</td><td>C0/C1C2C3C6C7C7SC8C9C10CPU DefaultAuto</td><td>Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit.</td></tr><tr><td>Active Processor Cores</td><td>All123</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>VT-d capability.</td></tr><tr><td>DTS SMM</td><td>DisabledEnabledCritical Temp Reporting (Out of spec)</td><td>Disabled: ACPI thermal management uses EC reported temperature values.</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>DisabledEnabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology.</td></tr></table>

7.3.2. Graphic Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS</td><td colspan="2">Info only</td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/VESA 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select.</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select.</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select.</td></tr><tr><td>LVDS Backlight Mode</td><td>BMC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight Brightness</td><td>255</td><td>A change takes effect immediately.</td></tr><tr><td>Brightnesst Setting</td><td>255</td><td>Set GOP Brightness value</td></tr><tr><td>Integrated Display Configuration</td><td colspan="2">Info only</td></tr><tr><td>eDP/LVDS</td><td>DisableEnable</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>Set DDI port 1 function to DisplayPort or HDMI..</td></tr><tr><td>DDI port 2</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>Set DDI port 2 to DisplayPort or HDMI</td></tr><tr><td>DDI port 3</td><td>No DeviceDisplay PortHDMIDisplayPort with HDMI/DVI Compatible</td><td>Set DDI port 3 function to DisplayPort or HDMI.No DDI3 support on this platform</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.This platform supports GOP driver</td></tr></table>

# 7.3.3. Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Management</td><td colspan="2">Info only</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>Lock Legacy Resources</td><td>DisabledEnabled</td><td>Enables or Disbles Lock Legacy Resources</td></tr><tr><td>LID Function</td><td>DisabledEnabled</td><td>Enable/Disable LID Function</td></tr><tr><td>ECO Mode</td><td>DisabledEnabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds before you can restart the system.</td></tr><tr><td>Power-Up Mode</td><td>Turn OnRemain OffLast State</td><td>Turn On:The machine starts automatically when the power supply is turned on.Remain off:To start the machine the power button has to pressed.Last State:The machine will power up to last power state</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td></td></tr></table>

# 7.3.3.1. Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power.</td></tr><tr><td>VCORE</td><td>Read only</td><td>Display actual voltage of the VCC_CORE.</td></tr><tr><td>VGFX</td><td>Read only</td><td>Display actual voltage of the VGFX</td></tr><tr><td>1.05VSB</td><td>Read only</td><td>Display actual voltage of the 1.05VSB.</td></tr><tr><td>VEME</td><td>Read only</td><td>Display actual voltage of the VEME</td></tr><tr><td>RTC</td><td>Read only</td><td>Display actual voltage of the RTC.</td></tr><tr><td>3.3V</td><td>Read only</td><td>Display actual voltage of the 3.3V</td></tr><tr><td>3.3VSB</td><td>Read only</td><td>Display actual voltage of the 3.3VSB</td></tr><tr><td>5V</td><td>Read only</td><td>Display actual voltage of the 5V</td></tr><tr><td>VCCST</td><td>Read only</td><td>Display actual voltage of the VCCST.</td></tr><tr><td>VCCIO</td><td>Read only</td><td>Display actual voltage of the VCCIO.</td></tr><tr><td>VCCSTG</td><td>Read only</td><td>Display actual voltage of the VCCSTG.</td></tr><tr><td>VCCSA</td><td>Read only</td><td>Display actual voltage of the VCCSA.</td></tr><tr><td>1.8VSB</td><td>Read only</td><td>Display actual voltage of the 1.8VSB</td></tr><tr><td>5VSB</td><td>Read only</td><td>Display actual voltage of the 5VSB</td></tr><tr><td>VIN</td><td>Read only</td><td>Display actual voltage of the VIN</td></tr></table>

7.3.4. USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td colspan="2">Info only</td></tr><tr><td>USB Module Version</td><td>Info only</td><td></td></tr><tr><td>USB Controllers:</td><td>Info only</td><td></td></tr><tr><td>USB Devices:</td><td>Info only</td><td></td></tr><tr><td>XHCI Compliance Mode</td><td>DisabledEnabled</td><td>Option to enable Compliance Mode. Default is to disable Compliance Mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>xDCI Support</td><td>DisabledEnabled</td><td>Enable/Disable xDCI (USB OTG Device).</td></tr><tr><td>USB Port Disable Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr></table>

7.3.5. AMT Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>AMT Configuration</td><td>Info only</td><td></td></tr><tr><td>AMT BIOS Features</td><td>DisabledEnabled</td><td>When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup.</td></tr><tr><td>MEBx hotkey Pressed</td><td>DisabledEnabled</td><td>OEMFLag Bit 1: Enable automatic MEBx hotkey press.</td></tr></table>

Note: Intel® Core™ i3 and Celeron® do not support AMT.

7.3.6. System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td colspan="2">Info only</td></tr><tr><td>Version:</td><td>Read only</td><td></td></tr><tr><td>SEMA Firmware</td><td>Read only</td><td></td></tr><tr><td>Build Date</td><td>Read only</td><td></td></tr><tr><td>SEMA Bootloader</td><td>Read only</td><td></td></tr><tr><td>Build Date</td><td>Read only</td><td></td></tr><tr><td>SEMA Features</td><td>Submenu</td><td></td></tr><tr><td>Flags</td><td>Submenu</td><td></td></tr></table>

7.3.6.1. System Management > SEMA Features

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Features:</td><td>Info only</td><td>Displays the SEMA features.</td></tr></table>

7.3.6.2. System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td></td></tr><tr><td>Exception Code</td><td>Read only</td><td></td></tr></table>

7.3.7. Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan Speed</td><td colspan="2">Info only</td></tr><tr><td>CPU Temperature</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td></td></tr><tr><td>Startup</td><td>Read only</td><td></td></tr><tr><td>Min</td><td>Read only</td><td></td></tr><tr><td>Max</td><td>Read only</td><td></td></tr><tr><td>Board Temperatures</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td></td></tr><tr><td>Startup</td><td>Read only</td><td></td></tr><tr><td>Min</td><td>Read only</td><td></td></tr><tr><td>Max</td><td>Read only</td><td></td></tr><tr><td>CPU Fan Speed</td><td colspan="2">Read only</td></tr><tr><td>Smart Fan</td><td colspan="2">Submenu</td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>This value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C</td><td>This value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Active Cooling Trip Point</td><td>Disabled40 C50 C60 C70 CRefer to BMC</td><td>This value is the temperature threshold of the Active Cooling Trip Point.Refer to BMC: Use the BMC FW settings.</td></tr></table>

7.3.7.1. Temperatures and Fan Speed > Smart Fan

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Smart Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Smart FanTemperature Source</td><td>CPU Sensor Board Sensor</td><td>CPU Smart FanTemperature Source.</td></tr><tr><td>CPU Fan Mode</td><td>AUTO (Smart Fan) Fan Off Fan On</td><td>CPU Fan Mode</td></tr><tr><td>Trigger Point 1</td><td colspan="2">Info only</td></tr><tr><td>Trigger Temperature</td><td>49</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>40</td><td>PWM Level</td></tr><tr><td>Trigger Point 2</td><td colspan="2">Info only</td></tr><tr><td>Trigger Temperature</td><td>59</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>60</td><td>PWM Level</td></tr><tr><td>Trigger Point 3</td><td colspan="2">Info only</td></tr><tr><td>Trigger Temperature</td><td>69</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>80</td><td>PWM Level</td></tr><tr><td>Trigger Point 4</td><td colspan="2">Info only</td></tr><tr><td>Trigger Temperature</td><td>79</td><td>Trigger Temperature</td></tr><tr><td>PWM Level</td><td>100</td><td>PWM Level</td></tr></table>

7.3.8. Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td colspan="2">Info only</td></tr><tr><td>Power-Up watchdog</td><td>DisabledEnabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up.Press F12 during start uo disable the Power Up Watchdog.</td></tr><tr><td>ATTENTION: Pressing F12 during start up disables the Power Up Watchdog.</td><td>Info only</td><td></td></tr><tr><td>RunTime Watchdog</td><td>DisabledEnabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled.</td></tr></table>

7.3.9. Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>W83627DHGSEC Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr><tr><td>NCT5104D Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr><tr><td>NCT5104DSEC Super IO Configuration</td><td>Info only</td><td></td></tr></table>

7.3.9.1. W83627DHGSEC Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port</td><td>EnabledDisabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=240h; IRQ=5</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=240h; IRQ=10IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12IO=260h;IRQ=3,4,5,6,7,10,11,12IO=268h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr></table>

7.3.9.2. W83627DHGSEC Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port</td><td>EnabledDisabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=248h; IRQ=7</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=248h; IRQ=10IO=240h;IRQ=3,4,5,6,7,10,11,12IO=248h;IRQ=3,4,5,6,7,10,11,12IO=250h;IRQ=3,4,5,6,7,10,11,12IO=258h;IRQ=3,4,5,6,7,10,11,12IO=260h;IRQ=3,4,5,6,7,10,11,12IO=268h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr></table>

7.3.9.3. NCT5104D Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port</td><td>EnabledDisabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=3f8h; IRQ=4</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr></table>

7.3.9.4. NCT5104D Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td colspan="2">Info only</td></tr><tr><td>Serial Port</td><td>EnabledDisabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=2F8h; IRQ=3</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=2F8h; IRQ=3IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Select an optimal setting for Super IO device.</td></tr></table>

7.3.10. Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port Console</td><td colspan="2">Info only</td></tr><tr><td>COM1</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM2</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM3</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM4</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

7.3.10.1. Serial Port Console > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100:ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection..</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffersare full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>Disabled Enable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>Disabled Enable</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>Disabled Enable</td><td>Enables or disables extended terminal resolution</td></tr></table>

<table><tr><td rowspan="6">Putty KeyPad</td><td>VT100</td><td rowspan="6">Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>LINUX</td></tr><tr><td>XTERMR6</td></tr><tr><td>SCO</td></tr><tr><td>ESCN</td></tr><tr><td>VT400</td></tr></table>

# 7.3.10.2. Serial Port Console > Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Redirection COM Port</td><td>COM1COM2COM3COM4</td><td>Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages.</td></tr><tr><td>Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection.</td></tr><tr><td>Redirect After POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

# 7.3.11. Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>DisabledEnabled</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr></table>

# 7.3.12. Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td colspan="2">Info only</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr><tr><td>SD Card/GPIO Mode</td><td>GPIOSD Card</td><td>Select SD Card or GPIO function.</td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>ATX: OS will turn off system power when shutdown.Note: AT mode will not support S3 &amp; S4 &amp; S5, so it will change Power Loss State to Power On.</td></tr><tr><td>BMC I2C Mode</td><td>100Kbps400Kbps</td><td>BMC I2C Mode</td></tr></table>

# 7.3.13. Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td colspan="2">Info only</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI Network Stack</td></tr><tr><td>Ipv4 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be availabe</td></tr><tr><td>Ipv4 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be availabe</td></tr><tr><td>Ipv6 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be availabe</td></tr><tr><td>Ipv6 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be availabe</td></tr></table>

# 7.4. Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>Submenu</td><td></td></tr></table>

# 7.4.1. Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td colspan="2">Info only</td></tr><tr><td>SA PCIe Code Version</td><td>Read only</td><td></td></tr><tr><td>VT-d</td><td>Read only</td><td></td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td></td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td></td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>EnabledDisabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment</td></tr></table>

# 7.4.1.1. Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td colspan="2">Info only</td></tr><tr><td>Memody RC Version</td><td>Read only</td><td></td></tr><tr><td>Memory Frequency</td><td>Read only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Read only</td><td></td></tr><tr><td>Channel 0 Slot 0</td><td>Read only</td><td></td></tr><tr><td>Channel 1 Slot 1</td><td>Read only</td><td></td></tr><tr><td>Memory ratio/reference clock options moved to overclock-&gt;Memory-&gt;Custom profile menu</td><td>Info only</td><td></td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067133314001600180018672000213322002400260026672800293330003200</td><td>Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largestMMIO length of installed graphic controller</td></tr></table>

7.4.1.2. Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td colspan="2">Info only</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>DisabledEnabled</td><td>If Enable, it will not scan for External Gfx Card on PEG and PCH PCIE Ports</td></tr><tr><td>Primary Display</td><td>AutoIGFXPCIe</td><td>Select which IGFX / PCIe Graphics device should be Primary Display or select SG for Switchable Gfx.</td></tr><tr><td>Select PCIE Card</td><td>AutoElk Creek 4PEG Eval</td><td>Select the card used on the platform</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M64M4M8M12M16M20M24M28M32M/F736M40M44M48M52M56M60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr></table>

7.4.2. Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA And RST Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr><tr><td>SCS Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN Controller</td><td>EnabledDisabled</td><td>Enable/Disable onboard NIC.</td></tr><tr><td>Wake on LAN For S5 Enable</td><td>EnabledDisabled</td><td>Enable/Disable integrated LAN to wake the system.</td></tr><tr><td>Serial IRQ Mode</td><td>QuietContinuous</td><td>Configure Serial IRQ Mode.</td></tr><tr><td>High Precision Timer</td><td>DisabledEnabled</td><td>Enable or Disable the High Precision Event Timer.</td></tr><tr><td>Pcie PII SSC</td><td>Auto0.0%0.1%0.2%0.3%0.4%0.5%0.6%0.7%0.8%0.9%1.0%1.1%1.2%1.3%1.4%1.5%1.6%1.7%1.8%1.9%2.0%</td><td>Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.This is only for testing phase</td></tr><tr><td>SPD Write Disable</td><td>TRUEFALSE</td><td>Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr></table>

7.4.2.1. Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td colspan="2">Info only</td></tr><tr><td>PCI Express Clock Gating</td><td>DisabledEnabled</td><td>PCI Express Clock Gating Enable/Disable for each root port.</td></tr><tr><td>DMI Link ASPM Control</td><td>DisabledL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>PCIE Port assigned to LAN</td><td>Read only</td><td></td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td>Enable when using Compliance Load Board.</td></tr><tr><td>PCIe-USB Glitch W/A</td><td>DisabledEnabled</td><td>PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.</td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td>When Disabled, prevents PCIE rootport function swap. If any function other than 0th is enabled, 0th will become visible.</td></tr><tr><td>PCIE Ports 0-3 Configuration</td><td>4x1 Port1x2 2x1 Port2x2 Port1x4 Port</td><td>To configure PCI-E Port 0-3 of PCH.[4X1]: Port 0-3 (x1)[1x2 2x1]: Port 0 (x2), Port 1 (disabled), Ports 2 and Port 3 (x1)[2x2]: Port 0-1 (x2) and Port 2-3 (x2)[1x4]: Port 0 (x4), Ports 1-3 (disabled)</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr></table>

7.4.2.2. Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port</td><td>DisabledEnable</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-inSlot</td><td>Built-In: a built-in device is connected to this rootport.SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level.Force L0s - Force all links to L0s StateAuto - BIOS auto configure;Disabled - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Gen3 Eq Phase3 Method</td><td>HardwareStatic Coeff.</td><td>PCIe Gen3 Equalization Phase 3 Method</td></tr><tr><td>UPTP</td><td>5</td><td>Upstream Port Transmitter Preset</td></tr><tr><td>DPTP</td><td>7</td><td>Downstream Port Transmitter Preset</td></tr><tr><td>ACS</td><td>Disabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td></td><td>Enable</td><td></td></tr><tr><td>PTM</td><td>Disabled Enable</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>Disabled Enable</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>Disabled Enable</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>Disabled Enable</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>Disabled Enable</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>Disabled Enable</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>Disabled Enable</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>CTO</td><td>Disabled Enable</td><td>PCI Express Completion Timer TO Enable/Disable</td></tr><tr><td>SEFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>Disabled Enable</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>Disabled Enable</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>Disabled Enable</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>Disabled Enable</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Configure PCIe Speed.</td></tr><tr><td>Transmitter Half Swing</td><td>Disabled Enabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Non-Compliance</td><td>Disabled Enable</td><td>Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reseved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB.</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info only</td><td></td></tr><tr><td>LTR</td><td>Disabled Enable</td><td>PCH PCIE Latency Reporting Enable/Disable.</td></tr><tr><td>Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow."</td></tr><tr><td>Non Snoop Latency Override</td><td>Disabled Manual Auto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Force LTR Override</td><td>Disabled Enable</td><td>Force LTR Override for PCH PCIE.</td></tr><tr><td>LTR Lock</td><td>Disabled Enable</td><td>PCIE LTR Configuration Lock</td></tr></table>

7.4.2.3. Chipset > PCH-IO Configuration > SATA and RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA And RST Configuration</td><td colspan="2">Info only</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST Premium With Intel Optane SystemAcceleration</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td></td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>Serial ATA Port X</td><td colspan="2">Info only</td></tr><tr><td>Software Preserve</td><td colspan="2">Info only</td></tr><tr><td>Port X</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td colspan="2">Info only</td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>SATA Port X DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr></table>

7.4.2.4. Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio SubsystemConfiguration Settings</td><td colspan="2">Info only</td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device.</td></tr></table>

7.4.2.5. Chipset > PCH-IO Configuration > SCS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>eMMC 5.0 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.0 Controller</td></tr><tr><td>eMMC 5.0 HS400</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.0 HS400 Mode</td></tr><tr><td>SDCard 3.0 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS SDHC 3.0 Controller.</td></tr></table>

Note: This feature is only supported for HW BOMs equipped with eMMC.

# 7.5. Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td colspan="2">Info only</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td></td></tr><tr><td>User Password</td><td>Enter password</td><td></td></tr><tr><td>Secure Boot menu</td><td>Submenu</td><td></td></tr></table>

# 7.5.1. Secure Boot menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Boot</td><td colspan="2">Info only</td></tr><tr><td>Secure Boot Control</td><td>DisabledEnabled</td><td>Secure Boot feature is Active if Secure Boot is Enabled, platform Key(PK) is enrolled and the System is in User mode,The mode change requires platform reset</td></tr></table>

# 7.6. Boot

7.6.1. Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>SATA Support</td><td>Last Boot HDD Only All Sata Devices</td><td>If Last Boot HDD Only, Only last boot HDD device will be available in Post. If All Sata Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>VGA Support</td><td>Auto EFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. Efi driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>Disabled Full Initial Partial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>Disabled Enabled</td><td>If Disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>Disabled Enabled</td><td>If Disabled, NetWork Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>Disabled Enabled</td><td>If disable, Redirection function will be disabled.</td></tr><tr><td>Boot mode select</td><td>UEFI</td><td>Select boot mode UEFI</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Boot Option Priorities</td><td>Info only</td><td></td></tr></table>

# 7.7. Save & Exit

# 7.7.1. Reset Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Save Changes and Reset</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr></table>

# 7.7.2. Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

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# 8. BIOS Checkpoints, Beep Codes

This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

# Checkpoints and Beep Codes Definition

A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.

Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.

# Aptio Boot Flow

While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:

• Security (SEC) – initial low-level initialization
- Pre-EFI Initialization (PEI) – memory initialization $^{1}$
- Driver Execution Environment (DXE) – main hardware initialization $^{2}$
- Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, ...)

# Viewing BIOS Checkpoints

Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.

Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.

Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints.

$^{1}$ Analogous to “bootblock” functionality of legacy BIOS

$^{2}$ Analogous to “POST” functionality in legacy BIOS

# 8.1. Status Code Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xCF</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 8.2. Standard Status Codes

# 8.2.1. SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2. SEC Beep Codes

None

# 8.2.3. PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4. PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5. DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

# 8.2.6. DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

# 8.2.7. ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

# 8.3. OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xFC</td><td>OEM BDS initialization codes</td></tr></table>

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# 9. Mechanical Information

# 9.1. Board-to-Board Connectors

To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

# Tyco 3-6318491-6

# Foxconn QT002206-4141-3H

# ePT 401-55103-51

- 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
- This connector can be used with 8 mm through-hole standoffs (SMT type).

![Exterior view of a multi-pin electronic component with no visible text or symbols](.cexpress-wl-50m-00029-1020-12/cf8e6909aad1ce719dd4a270a5ce345c6faeb9f8286f30e1299f381e46817b38.jpg)

# Common Specifications

• Current capacity: 0.5A per pin
• Rated voltage: 50 VAC
• Insulation resistance: 100M or greater @ 500 VDC
• Temperature rating: -40°C \~ 85°C
• UL certification (ECBT2.E28476)
• Copper alloy (contacts)
• Housing: thermo-plastic molded compound (L.C.P.)

# 9.2. Thermal Solution

This section presents general thermal solution information for COM Express modules for your reference. Photos and details may vary depending on the specific module.

# 9.2.1. Heat Spreaders

The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.

# 9.2.2. Heat Sinks

A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.

# 9.2.3. Installation

Install a heat spreader or heat sink using the following instructions.

Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.

![Hand in white glove holding a green printed circuit board with electronic components (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/ecf80155e782455d3a2fbe9f29b8124241bd7f14c19cf7385c9961a4dacf2406.jpg)

Step 2: Remove the protective membranes from the thermal pads.

![Close-up of a small green textured object being processed with tweezers using a tool, placed on a white surface (no text or symbols visible)](.cexpress-wl-50m-00029-1020-12/32d703657784c9475fab7dafc5918c5ca8f459725ef59728bb69102c0731877f.jpg)

Note: Not all thermal pads have a protective membrane (module dependent).

Step 3: Assemble the heatsink onto the COM Express module. Use the three M2.5, L=8mm screws provided to fasten the heatsink to the module.

![Close-up of a green printed circuit board with multiple electronic components and a metal tool inserted (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/32c212589ec32eac8f9d93010b224a301e4fd11c584f3a41c282fb80570fda66.jpg)

![Three identical silver metal screws are arranged in a horizontal row against a plain white background.](.cexpress-wl-50m-00029-1020-12/b5c73cb0315363c8be94145ba7fe5f4cc6069ba45afff2a4be2bb2aebd942e92.jpg)

Note: The CExpress-WL uses three screws to attach the heatsink to the COM Express module.

Step 4: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.

![Close-up of a green printed circuit board with electronic components and a gloved hand adjusting it (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/e118aca29274e445228dbc2e823420425783d8291e349d20712156ff82a0a290.jpg)

Then press down on the module until it is firmly seated on the carrier board.

Step 5: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.

![Close-up of a green printed circuit board with multiple electronic components and red circular annotations highlighting specific areas (no readable text or symbols)](.cexpress-wl-50m-00029-1020-12/6cd7750116874a3983b2c8c729c89c618437ad6125e5e7e3126d5e7f6d1f330b.jpg)

![Five metallic screwdrivers arranged horizontally on a plain background (no text or symbols visible)](.cexpress-wl-50m-00029-1020-12/19646cc335abd39cee5530a18de0c7467bbee6c7e1a6744a1f69659d61299916.jpg)

Step 6: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.

![Close-up of a green computer motherboard with a hand holding a cooling fan and power supply (no visible text or symbols)](.cexpress-wl-50m-00029-1020-12/4c1e2b47324d9203fa555311a222050d17dbed682c166388eedb1dfa7a74178d.jpg)

# 9.3. Mounting Methods

There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.

![The image displays two technical diagrams side-by-side illustrating mounting configurations.\n\n**Left Side: Top Mounting**\nThe header reads 'Top Mounting with 8 mm connectors'. The diagram shows a vertical stack of components labeled as follows from top to bottom:\n*   A screw labeled 'M2.5 : 18 mm with spring / washer'\n*   A grey component labeled '2 mm heatspreader with 9 mm through-hole standoffs'\n*   A green strip labeled 'COM Express Module ~2 mm'\n*   A grey component labeled '8 mm threaded standoff (DIP)'\n*   A green strip labeled 'Carrier Board ~2 mm'\n\n**Right Side: Bottom Mounting**\nThe header reads 'Bottom Mounting with 8 mm connectors'. The diagram shows a vertical stack of components labeled as follows from top to bottom:\n*   A grey component labeled '2 mm heatspreader with 9 mm threaded standoffs'\n*   A green strip labeled 'COM Express Module ~2 mm'\n*   A grey component labeled '8 mm through hole standoff (SMT)'\n*   A green strip labeled 'Carrier Board ~2 mm'\n*   A screw labeled 'M2.5 : 16 mm with spring/washer'](.cexpress-wl-50m-00029-1020-12/d565f7f4dfdadc749758e9384e9ac812ab2ded1a4677d7a725ea5ddcc70c6db4.jpg)
Figure 6: COM Express Mounting Methods

# 9.4. Standoff Types

The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request.

![8mm through-hole standoff (SMT type)\nP/N: 33-72000-0080\n8mm threaded standoff (DIP type)\nP/N: 33-72015-0050](.cexpress-wl-50m-00029-1020-12/7266d5078f5def9cc83c6c14f418263b2845bfbfb8bf89db4a96b10cd942eb37.jpg)

Figure 7: COM Express Standoff Types

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

- Please read these safety instructions carefully.
- Please keep this User's Manual for later reference.
- Read the specifications section of this manual for detailed information on the operating environment of this equipment.
- When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

- Keep equipment away from water or liquid sources.
- Keep equipment away from high heat or high humidity.
- Keep equipment properly ventilated (do not block or cover ventilation openings).
■ Make sure to use recommended voltage and power source settings.
■ Always install and operate equipment near an easily accessible electrical socket-outlet.
- Secure the power cord (do not place any object on/over the power cord).
- Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
- If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

\- Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

<table><tr><td>Address:</td><td>9F, No.166 Jian Yi Road, Zhonghe District New Taipei City 235, Taiwan</td></tr><tr><td>Tel:</td><td>+886-2-8226-5877</td></tr><tr><td>Fax:</td><td>+886-2-8226-5717</td></tr><tr><td>Email:</td><td>service@adlinktech.com</td></tr></table>

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

<table><tr><td>Address:</td><td>300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China</td></tr><tr><td>Tel:</td><td>+86-21-5132-8988</td></tr><tr><td>Fax:</td><td>+86-21-5132-3588</td></tr><tr><td>Email:</td><td>market@adlinktech.com</td></tr></table>

# ADLINK Technology GmbH

<table><tr><td>Address:</td><td>Hans-Thoma-Straße 11, D-68163, Mannheim, Germany</td></tr><tr><td>Tel:</td><td>+49-621-43214-0</td></tr><tr><td>Fax:</td><td>+49-621 43214-30</td></tr><tr><td>Email:</td><td>emea@adlinktech.com</td></tr></table>

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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