![Close-up of a COMHPC A321 microprocessor board with visible circuitry and gold contacts (no text or symbols)](.com-hpc-alt-50m-00115-1010-11/e489a9b9044f148d644e2632f8f3544624e82d4372d0d787b6184c72b27099e0.jpg) Revision History
RevisionDescriptionDateAuthor
1.0Initial release2023-01-10CC
1.1Pinout and signal descriptions and BIOS checkpoints, beep codes updated2025-07-30AL
# Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. 区 ![The image displays a standard warning symbol featuring a yellow triangle with a thick black border. Centered inside the triangle is a large black exclamation point. The sign is set against a white background, with a horizontal black line visible just above the top edge of the triangle.](.com-hpc-alt-50m-00115-1010-11/a046ef507c51a68ffe0ef6dc9d263309515f7f36970fc2a6fce2d4eac1ba624a.jpg) California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. # Copyright © 2025 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: • Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image displays a red icon on a white background representing a document or text file. It consists of a thick red outline of a vertical rectangular page with a folded bottom-right corner. Inside the outline, two horizontal red bars are centered vertically, resembling lines of text.](.com-hpc-alt-50m-00115-1010-11/dbd1f8e235987951f1a2fa0e58ff3a27566a2ed09aa553a0401c997d5d587a54.jpg) Note: This information adds clarity or specifics to text and illustrations. ![A yellow triangular warning sign containing a central exclamation point, set against a background of faint diagonal stripes.](.com-hpc-alt-50m-00115-1010-11/235ad9f8f58b7776665a599b80a282f4177486012c43075dfe52f8419acb736d.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image displays a red triangular warning sign with rounded corners. Centered within the red triangle is a white exclamation point.](.com-hpc-alt-50m-00115-1010-11/1ab571585d479ce940060125ec0edabf0258c05963a3cf32519b9c345bd30d7f.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Getting Service Ask an Expert: https://www.adlinktech.com/en/askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5706 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. # Table of Contents Revision History .. Preface .. 1. Introduction ... 2. Specifications... 2.1 Core System... ..4 2.2 Expansion Busses... ..5 2.3 Ethernet .. ...8 2.4 Multi I/O and Storage... ..9 2.5 Others... ... 10 2.6 Security .... . 11 2.7 Module Management Controller (MMC)... . 11 2.8 Debug... . 17 2.9 Power... ... 17 2.10 Mechanical and Environmental . .. 18 3. Block Diagram .............. ...20 4. Pinout and Signal Descriptions ....... ...21 4.1 Pin Summary .. .. 21 4.2 Signal Terminology Descriptions... ..6 4.3 Signal Descriptions on J1/J2 Connectors ... 4.3.1 Ethernet KR/KX.. 4.3.2 NBASE-T Ethernet.. ..9 4.3.3 PCI Express... . 11 4.3.4 USB.. . 19 4.3.5 Asynchronous Serial Port.. . 21 4.3.6 I2C ... . 22 4.3.7 Port 80 Support on USB\_PD I2C Bus.. . 23 4.3.8 IPMB .. . 23 4.3.9 General Purpose SPI .. . 24 4.3.10 Power & System Management .. . 24 4.3.11 Thermal Protection... ... 26 4.3.12 SMBus .. ... 26 4.3.13 General Purpose Input Outputs... . 26 4.3.14 Module Type Definition .. . 27 4.3.15 Miscellaneous Signals .. ... 28 4.3.16 Power and Ground .. ... 30 5. Additional Features .. ..31 5.1 Debug Connector (40-pin connector) .. . 32 5.2 Status LEDs... . 33 5.3 Fan Connector... . 34 5.4 BIOS Default Reset (update later).. . 35 5.5 BIOS Boot Select (update later).. . 36 6. BIOS Checkpoints, Beep Codes .. .37 6.1 Status Code Ranges . . 38 7. Mechanical and Thermal.. .39 7.1 Module Dimensions . . 39 .. 40 7.2.1 Heatsink : THS-ALT-BL .. .... 40 7.2.2 Low Profile Active Cooler: THSF-ALT-BL-S.. . 41 7.2.3 High Profile Passive Heatsink: THSH-ALT-VC . ... 42 7.2.4 Active Cooling: THSF-ALT-BL.. .... 43 # List of Figures Figure 1 – Functional block diagram .. ...20 Figure 2 – Rear side row ......... ...21 Figure 4 – Heatsink THS-ALT-BL. ...40 Figure 5 – THSF-ALT-BL-S... ..41 Figure 6 – High profile passive heatsink THSH-ALT-VC..... ...42 Figure 7 – Cooler THSF-ALT-BL... ...43 # 1. Introduction ![The image displays a yellow triangular warning icon featuring a white exclamation mark centered inside, set against a light grey background.](.com-hpc-alt-50m-00115-1010-11/b3324696e803b424eec1e5ba9da95834bcf5d05432807fa0578824567a75fc26.jpg) Caution: This is an EA (early available) engineering manual. The contents may not accurately reflect the actual or final version of this product. ADLINK COM-HPC-ALT is a COM-HPC® Server Type Size E compliance module featuring Ampere® Altra® Series SoC. It supports up to 128 cores and boosts up to 2.6GHz based on 190W TDP while providing up to 384GB of RDIMM, UDIMM, LRDIMM DDR4 six-channel memory at up to 3200 MT/s in 6 DIMM sockets. These combined features make the COM-HPC-ALT well suited to customers who need uncompromising system performance and responsiveness embedded solutions with extended product life. The COM-HPC-ALT features 4x 110G SFP+ interfaces by Broadcom BCM57502 (PCIex8 input, 4x 10G-KR output) and a single on-board Gigabit Ethernet port by Intel i210/i211 series. It features 64x PCIe Gen4 physical lanes, 4x USB 3.x upgrade signals, and 4x USB 2.0 ports The COM-HPC-ALT features 1x GPP\_SPI and 1x Boot\_SPI, 1x SMBus, 2x I2C, 2x UART and 12x GPIO. No eSPI offered The COM-HPC-ALT based discrete circuit and MMC (ATMEGA128), instead of CLPD, are supported by the module for power sequence control The COM-HPC-ALT supports IPMB, which supports an MMC (module management controller, ATMEGA) and its firmware on the module. Combined with a dedicate 1x PCIe lane (it is called PCIe\_BMC), IPMB can enable Carrier BMC (for example, AST2500 or equivalent) and access necessary message (for example, voltage information and CPU temperature on module) between MMC and Carrier BMC. In addition, an EEPROM is located on I2C\_0 bus as a traditional COMe EEPROM usage and also as a FRU for Carrier BMC One security chip is supported on the module. The traditional TPM 2.0, SPI based (same as Ampere Altra reference design) (it is on GP\_SPI bus) The module is equipped with EDK2 (bootloader, open source) BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer. No EC on this product. # 2. Specifications # 2.1 Core System # SoC Ampere Computing, Ampere® Altra® Series Processors • M128-26 128 cores, 2.6GHz, 190W TDP • Q80-26 80 cores, 2.6GHz, 150W TDP • Q64-22 64 cores, 2.2GHz, 95W TDP • Q32-17 32 cores, 1,7GHz, 65W TDP # Memory Up to 384GB 3200 MT/s DDR4 in 6 DIMM sockets, Maximum 64GB per socket Supports RDIMM, UDIMM and LRDIMM and 3DS 3 DIMM on the right side, the other 3 DIMMs on the left side # Cache 1 MB L2 cache per core 32 MB system level cache # Embedded BIOS EDK2 UEFI with CMOS backup in 32 (or 16, TBC) MB SPI BIOS # 2.2 Expansion Busses # PCI Express # 64x PCIe lanes with 5x PCIe\_REFCLK / 5x PCIe\_CLKREQ Up to Gen4 speed \- PCIe 0-7 1 x4 or 2 x2 config at 0-3, 1 x4 or 2 x2 config at 4-7, 1 x8 config at 0-7 \- PCIe 8-15 1 x4 or 2 x2 config at 8-11, 1 x4 or 2 x2 config at 12-15, 1 x8 config at 8-15 \- PCIe 16-31 1 x16 or 2 x8 or 4 x4 config at 16-31, \- PCIe 32-47 1 x16 or 2 x8 or 4 x4 config at 32-47, PCIe 48-63 1 x16 or 2 x8 or 4 x4 config at 48-63, Lane polarity inversion (from Root Complex B) (from Root Complex B) (from Root Complex A) (from Root Complex A) (from Root Complex A) 5x PCIe\_REFCLK/PCIe\_CLKREQ ```txt PCIe_REFCLK0_LO & PCIe_CLKREQ0_LO# : for PCIe lanes [0:7] and PCIe_BMC PCIe_REFCLK0_HI & PCIe_CLKREQ0_HI# : for PCIe lanes [8:15] PCIe_REFCLK1 & PCIe_CLKREQ1# : for PCIe lanes [16:31] PCIe_REFCLK2 & PCIe_CLKREQ2# : for PCIe lanes [32:47] PCIe_REFCLK3 & PCIe_CLKREQ3# : for PCIe lanes [48:63] ``` ![A red icon resembling a square document with a folded bottom-right corner, featuring two horizontal white lines in the center resembling an equals sign.](.com-hpc-alt-50m-00115-1010-11/c608e80329809963505e48835f9bcb1e0a8a014bd1070d05936e615c41ef6cfd.jpg) Note: Due to SoC orientation, the trace of PCIe 48-63 lanes over the PICMG specification marginally and may require re-driver on carrier. # PCI Express Dedicated for Carrier BMC 1x PCIe lane (called PCIe\_BMC) They can be used to connect the Carrier BMC (located on carrier) and combined with MMC (Module Management Controller, build option feature), such as voltage monitoring, power on/off, in the server applications. # Boot SPI 1x Boot\_SPI, 2x Boot\_SPI\_CS dedicated for boot BIOS flash usage SPI clock is either 20 MHz, 25 MHz, 33 MHz (Ampere Altra SOC only support up to 30MHz) Support 3.3V of VCC\_BOOT\_SPI pin, if SPI flash on carrier is implemented, it shall be powered by VCC\_BOOT\_SPI pin # BIOS Boot Selection BIOS flash can be boot up at SPI bus, can be located at module or carrier or combined # I2C 2x I2C, I2C 0 and I2C 1 I2C 0 additional offer ALERT# input and 3.3V power rail (source from Ampere Altra SoC) I2C 1 is 1.8V power rail (source from Ampere Altra SoC) Supports software programmable clock of 100 KHz (standard mode) and 400 KHz operation (fast mode) Supports multi-master, allowing carrier to read the module’s EEPROM before powering up the module Support 7-bit and 10-bit address mode An EEPROM is located on I2C 0, which can be used as Module EEPROM and IPMI FRU, combined together # USB\_PD\_I2C COM-HPC Module should support exporting Port 80 information over the USB\_PD I2C bus (signals USB\_OD\_I2C\_DAT and USB\_PD\_I2C\_CLK) to Carrier hardware that implements a pair of 7-segment displays to show the codes The USB\_PD\_I2C comes from MMC ATMEGA128 and USB\_PD\_I2C, MMC and SOC connect to the same bus # IPMB 1x IPMB comes from MMC. Please refer to section 2.9 Module Management Controller for further details IPMB is used with a Carrier BMC. MMC is ATMEGA solution that communicate with Ampere Altra SOC through UART Several monitored voltage (for example, memory voltage, CPU voltage) and temperature (for example, CPU temperature) can be communicated between MMC and Carrier BMC through IPMB. A dedicated PCIe x1 lane is also available on the Carrier BMC, allowing the Carrier BMC to generate a VGA or other format video output, for management functions. # General Purpose SPI 1x GP\_SPI, 2x GP\_SPI\_CS A TPM is located on GP\_SPI bus # SM Bus 1x SMBus comes from SoC I2C\_9 bus # 2.3 Ethernet # NBASE-T Ethernet Intel® Ethernet Controller i210/i211, connected to the SoC through PCIe lane Supports 10/100/1000 Mbps data transfer rates, both full-duplex and half-duplex Supports NBASET\_SDP, Software-Defined Pin. Can also be used for IEEE 1588 support such as 1pps signal Supports Wake on LAN at S3/S4/S5 Supports PXE boot # Ethernet KR/KX Interfaces Broadcom® Ethernet Controller BCM57502, connected to the SoC through PCIex8 lane 4x 10GBASE-KR and its sideband signals Supports both full-duplex and half-duplex # 2.4 Multi I/O and Storage # USB Up to 4x USB 3.2 Gen1/2.0 (USB 0,1,2,3; via PCIe to USB IC) (the IC is Renesas uPD720201) SuperSpeedPlus, SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signalling # Asynchronous Serial Port Two UART interfaces UART0 and UART1. UART0 supports TX RX RTS CTS. UART1 supports TX/RX Console Redirection UART0 or UART1 selectable in BIOS Up to 2 serial ports are supported in standard BIOS including Super I/O on the carrier
COM PortDescriptionIRQAddressConsole Redirection Support
COM 1Supported by module (SER0, A98/A99), via SOC40x3F8Yes
COM 2Supported by module (SER1, A101/A102), via SOC30x2F8Yes
![The image shows a red icon of a document or memo. It is a red outline of a piece of paper with a folded bottom-right corner. Inside the outline are two horizontal red lines.](.com-hpc-alt-50m-00115-1010-11/7376cb6494be5376f9f2d3a309fb85c160a174ad6e0e35b829da9368647cf7fd.jpg) Note: UART0, 1 both source from SOC. UART0 offers TX, RX, RTS#, CTS#. UART1 only offers TX and RX; its RTS#, CTS# are simulated by 2 GPIO from SOC. # GPIO 12x GPIO Supports GPI with interrupt # 2.5 Others # FAN Control Control source is from MMC FAN control is offered # Health Monitoring CPU temperature (through I2C3 of SOC) and board temperature are monitored by MMC. 8-10 voltage are monitored by EC, customer can get voltage information on BIOS menu and also shown in SEMA GUI and access it through SEMA API 1. CPU core 2. GFX core 3. Memory power 4. 5VSB (ROW AB/CD) 5. Main power (ROW AB/CD, 8.5V\~20V or 5V\~xxV) 6. 5VDUAL (CPU board) 7. 3.3VS (CPU board) 8. 3.3VSTBY (CPU board) 9. RTC battery (ROW AB/CD) 10. MAINPWRSENSE(For BMC calculate power consumption of the main power) # 2.6 Security This module offers one security-related chip on the module. # Trusted Platform Module (TPM) Chipset: Infineon solution Type: TPM 2.0 (SPI bus based) (located on GP\_SPI) # 2.7 Module Management Controller (MMC) A Module Management Controller (MMC) is supported by default, which offers power sequence management and IPMB that can be connected to Carrier BMC for voltage, current, temperature, and other system information through IPMI protocol The selected MMC is ATMEGA128A-MU (Microchip) (-40 to 85°C) solution. MMC connects to SOC through UART interface MMC connects to a HW monitor through I2C bus to monitor module’s voltage, current and temperature MMC only offers two I2C, one is used for USB\_PD\_I2C, the other used for IPMB. # Overview COM-HPC Module and Carrier boards may support out-of-band (OOB) management features. These features may be implemented on COM-HPC Server or Client systems. Traditionally OOB management is more of a server class feature, but the option is there for both COM-HPC Clients and Servers. There is a separate PICMG document that describes COM-HPC OOB management features in details — PICMG COM-HPC Platform Management Interface Specification. The management architecture is divided into BMC (Board Management Controller) and MMC (Module Management Controller), which are explained in the following sections. BMC (Board Management Controller) (Located on Carrier board if deployed) This is a microcontroller subsystem, usually based on the Carrier, that performs system out-of-band management functions such as firmware updates, power and reset control, performance monitoring and more. For COM-HPC module, which are hosted on the carrier, it may be a full subsystem with CPU / SOC, DRAM memory, an internal display controller and more. It may be ARM based. It may run a Linux or other OS. A popular vendor for this sort of BMC part is Aspeed, and in particular the Aspeed AST2510 and successor parts. Many other vendors and parts are possible. It is anticipated that in most situations the BMC, if deployed, will be on the Carrier. Implementation of OOB management and a BMC on the Carrier is entirely optional. A Carrier based BMC is intended to work in conjunction with a Module based microcontroller referred to as the MMC (described below). A Carrier BMC, if deployed, shall implement an IPMB interface to the COM-HPC Module. This is the channel for IPMI support. The Carrier BMC may also make use of the COM-HPC I2C0, USB, eSPI, NBASET0, UARTx and / or the PCIe\_BMC interfaces, as well as controlling the module power signals like PWRBTN, ...). Any COM-HPC USB host port may be used to interface to a Carrier BMC USB client port. The Module USB port is usually a Module chipset or SOC host port, and not a MMC USB port. Designers should avoid using COM-HPC USB0, as it has special privileges allowing it to be used as a host or client. Designers may want to avoid using COM-HPC USB0, 1, 2, 3 as they are defined to allow USB SuperSpeed capability and BMC devices to not typically have USB SuperSpeed capability. USB4, 5, 6 or 7 should be used for the BMC interface if available. Of the two COM-HPC UART interfaces that may be used to interface to a Carrier BMC, UART1 should be selected as UART0 is often used for functions such as Console Redirect. # MMC (Module Management Controller) (Located on COM-HPC Module, optional) The MMC is a Module based microcontroller that may work in conjunction with a Carrier based BMC. If there is no Carrier BMC, then the MMC shall fall back to a mode that does not depend on the Carrier BMC, allowing the Module to function without external OOB management. The MMC shall powered by the VCC\_5V\_SBY supply to allow for OOB functionality even when the main supply is not available, however, it should also use the main VCC rail, if available. In most implementations, the MMC will be a relatively small low cost and low power device, in order to keep Module costs down for customers that do not require OOB management features. It may serve as a sensor aggregator. It may serve as host for nonvolatile Module parameter storage. The MMC, if implemented, shall include an IPMB slave interface. It may additionally interface to the Carrier BMC over any of several other COM-HPC interfaces, including the I2C0 and or UART0 ports. # Carrier and Module BMC and MMC Combinations The PICMG COM-HPC Platform Management Interface Specification defines a number of different carrier and module options, which differ based on their management capabilities. Table 45 below lays out the options and defines a shorthand notation for the options. Full details are in the PICMG COM-HPC Platform Management Interface Specification. Table 45: Carrier and Module BMC and MMC Combinations and Shorthand Notation
Shorthand NotationDescription
CarrierC.UUnmanagedThe carrier has no BMC. Power and chassis management is typically done via a small microcontrollerManagement depends on the Module's capabilities
C.MManaged via Carrier based BMCAn IPMB communication channel to the MMCShallbe implementedThe BMcamayalso make use of the NBASET0, eSPI, USB, I2C0, UART0, PCIe_BMC, and / or the GPIO interfacesProvides Redfish to the outside (or IPMI for legacy)iKVM for the module via PCIe_BMC/USB
ModuleM.UUnmanaged (No MMC)Shouldimplement a dedicated EEPROM (EeeP) for module identificationCPU management possible via I2C0, NBASET0, eSPI, USB, UART0, GPIO, PCIe_BMC (all except IPMB), depending on the Carrier capabilities
M.BBasic Management capabilities via low cost MMCAn IPMB interface to Carrier BMCShallbe implementedManagement via external interfaces (IPMB, I2C0, NBASET0, eSPI, USB, UART0, GPIO, PCIe_BMC)
M.FFull Management capabilities (typically via ARM-based OS)NBASET0 is shared by MMC and CPU (switched on Module), providing a high-speed OOB communication channelAn IPMB interface to Carrier BMCShallbe implementedAdditional interfacesmaybe used (I2C0, NBASET0, eSPI, USB, UART0, GPIO, PCIe_BMC)
Assuming that the Types of the Carrier and Module match up (Server with Server, Client with Client) and the board sizes / connector positions match up (size A, B, C or size D,E) then a C.U or C.M Carrier shall be basically operable with a M.U or M.B or M.F Module. The OOB management features may be missing, depending on what is matched with what. Additionally, there will likely be some vendor specific aspects to OOB management options. M.B Module and C.M Carrier will be implemented at ADLINK COM-HPC Server Module and COM-HPC Server Carrier as first wave. ![**Labeled Blocks:**\n\n* **COM-HPC Carrier (C.M)**\n * Managed (via BMC)\n* **BMC**\n* **PWRBTN#, RSTBTN#**\n* **Management network**\n* **Compute network**\n* **COM-HPC Module (M.B)**\n * Basic management capabilities (low-cost MMC)\n* **Power & Chassis Mgmt**\n * (PWRBTN#, RSTBTN#, VIN_PWR_OK, SUS_S3, ...)\n* **Module Power Management**\n* **IPMB**\n* **I2C0**\n* **MMC**\n * emulated EEPROM\n* **NBASET0**\n* **GPIO UART**\n* **CPU/ FPGA/ GPU**\n* **ESPI**\n* **PCIE**\n* **USB**\n\n**Connections:**\n\n* A line connects the text 'PWRBTN#, RSTBTN#' to the 'BMC' block.\n* Lines connect 'Management network' and 'Compute network' to a bidirectional switch symbol.\n* A line connects the right output of the switch symbol to the 'BMC' block.\n* A line connects the bottom output of the switch symbol to the line labeled 'NBASET0'.\n* A line labeled 'Power & Chassis Mgmt (PWRBTN#, RSTBTN#, VIN_PWR_OK, SUS_S3, ...)' connects the 'BMC' block to the 'Module Power Management' block.\n* A line labeled 'IPMB' connects the 'BMC' block to the 'MMC' block.\n* A line labeled 'I2C0' connects the 'BMC' block to the 'emulated EEPROM' block inside the 'MMC' block. There is a junction dot on this line.\n* A dotted line connects the junction dot on the 'I2C0' line to the 'CPU/ FPGA/ GPU' block.\n* A line labeled 'NBASET0' connects the 'BMC' block to the 'CPU/ FPGA/ GPU' block.\n* A line labeled 'GPIO UART' connects the 'BMC' block to the 'CPU/ FPGA/ GPU' block.\n* Lines labeled 'ESPI', 'PCIE', and 'USB' connect the 'BMC' block to the 'CPU/ FPGA/ GPU' block.](.com-hpc-alt-50m-00115-1010-11/94d606e40e161cbf51d953342d6a87565c69c5e1a84281df6b38c2114e9bd4fc.jpg) # IPMI on COM-HPC The COM-HPC management platform shall use an IPMI (Intelligent Platform Management Interface) for communication between the Carrier BMC and MMC, over the COM-HPC IPMB port. The interface from the BMC to the user is independent from this, and may be realized using Redfish, it may support IPMI for legacy support. The interface used for IPMI between BMC and MMC shall be IPMB (an I2C bus specifically for IPMI use. As set of IPMI commands for communication between MMC and BMC have been defined in the PICMG COM-HPC Platform Management Interface Specification. Most of those commands are not specific to COM-HPC, but defined in the IPMI specification and related specifications. However, also some COM-HPC specific commands have been developed. Specifically, the following command sets are covered: - IPM Device Global Commands: Initialization and module discovery - BMC Watchdog and Device and Messaging Commands: System interface and BMC interaction. - Chassis Device Commands: Power control and boot options - Event Commands: IPMI event handling - PEF and Alerting Commands: Alerting and trigger support - Sensor Device Commands: Sensor monitoring and housekeeping - FRU Device Commands: Inventory data - SDR Device Commands: Sensor information - SEL Device Commands: System event logging - LAN Device Commands and HPM.2: Support for Ethernet - Serial/Modem Device Commands: For UART and SOL support - AdvancedTCA subset: For Fan Management - HPM.1: For Firmware update - HPM.2: For managing BMC-MMC Ethernet communication - COM-HPC specific Commands: For fast sensors and JTAG support The inventory data available via IPMI FRU also includes information present in the COM-HPC EEPROM (see Section Error! Bookmark not defined.). The COM-HPC EEPROM content is defined in the PICMG Embedded EEPROM for COM-HPC document, a companion document to the PICMG COM-HPC Platform Management Interface Specification. The information available in the COM-HPC EEPROM area will be converted from EeeP format into IPMI FRU data structures by the MMC. In order to accomplish this, the MMC reads the data from the EEPROM during start of the system, and buffers the data internally to service incoming IPMI FRU accesses. The EEPROM area for storing EeeP data may be implemented as a physical EEPROM on the board, on the I2C0 bus. Alternatively, it may be realized within the MMC. This is illustrated in Figure 10 above. In that figure, it is labeled as an “emulated EEPROM”. An I2C slave interface on the MMC is connected to the I2C0 bus of the COM-HPC module. This easesimplementation, as the MMC does not need to fetch information from the physical COM-HPC EEPROM, and also prevents potential access conflicts between the MMC and other I2C agents on the Baseboard or Carrier. The MMC implemented this way does not need I2C Master or Multi-Master capability. # COM-HPC EEPROM Modules and Carriers for COM-HPC should implement an EEPROM which allows the identification of Module or Carrier features via I2C. This feature is similar to the COM Express EEPROM defined in the PICMG COM Express specification. Some Module vendors will find a benefit in software reuse with test scripts and software infrastructure developed for COM Express use. The COM-HPC EEPROM content is defined in the EeeP for COM-HPC (Embedded EEPROM for COM-HPC) document, a companion document to the PICMG COM-HPC Platform Management Interface Specification. The EeeP for COM-HPC specification is derived from the Eeep for COM-Express document and introduces new data structures specific to COM-HPC modules and carriers, while the data structures for COM Express modules and carriers remain untouched. A new revision has been assigned to distinguish between COM Express and COM-HPC EEPROMs. # EEPROM Device Information If the COM Express Module and / or Carrier EEPROMs are implemented on COM-HPC, then the COM-HPC I2C0 port shall be used to interface to the EEPROMs. The EEPROM devices shall have a capacity of at least 32 Kbits, and shall have three address inputs. Suitable devices include the Atmel AT24C32C, the ST M24C32 and other compatible devices. Larger capacity devices may be used if they are compatible with the base 32 Kbit part referenced above. # COM-HPC Module EEPROM The Module should implement a serial EEPROM that identifies the Module using the EeeP defined Unique Device ID. In addition this EEPROM should describe the available module interfaces and capabilities as described in the EeeP for COM-HPC specification. The EEPROM may be implemented as a physical EEPROM on the board, or may be realized within the MMC (see Section Error! Bookmark not defined.). The Module EEPROM allows the Carrier Board to set up any software configurable Carrier Board features in a way that is appropriate for the Module board. The Module EEPROM I2C device address lines, A2, A1 and A0 shall be pulled to a logic low, placing the device at address 0x50 (7 bit I2C addressing) and address 0xA0(8 bit I2C addressing). Note: I2C address A6-A3 are fixed at 1010b for I2C EEPROM devices per the I2C specification. # COM-HPC Carrier Board EEPROM The Carrier Board should implement a serial EEPROM that identifies the Carrier using the Unique Device Id and describes the expected PCI Express link configuration. In addition this EEPROM may describe the expected link presence for SATA, USB, DDI, VGA, LAN, audio, and the expected presence of miscellaneous I/O signals. The EEPROM may be implemented as a physical EEPROM on the board, or may be realized within the BMC (see Section Error! Bookmark not defined.). The Carrier EEPROM allows the Module firmware to set up any software configurable Module features in a way that is appropriate for the Carrier Board. If there is an incompatibility between the expected Carrier Board configuration and the Module capabilities, an error message may be generated. The error messaging is Module vendor specific and is not defined by this standard. The Carrier EEPROM device address lines, A2, A1 and A0 shall be pulled to a logic high, placing the device at address 0x57 (7 bit addressing) and 0xAE(8 bit addressing). I2C addresses A6-A3 are fixed at 1010b for I2C EEPROM devices. # 2.8 Debug 40 pin flat cable connector to be used with DB40 HPC debug module Supports BIOS POST code LED, BMC access, SPI BIOS flashing, internal power rail test points, debug LEDs # 2.9 Power Power Modes: AT and ATX mode Standard Voltage Input: ATX 12V±5% / 5Vsb ±5% or AT 12V±5% Power Management: ACPI 5.0 compliant, Smart Battery support Power States: C1-C6, S0, S1, S5, S5 ECO mode (Wake-on-USB, WoL S5) ECO Mode support for deep S5 for 5Vsb power saving # 2.10 Mechanical and Environmental # Form Factor and Specification PICMG COM-HPC Rev 1.0, Server Type, Size D 200 x 160 mm Operating Temperature
Standard0°C to 60°C at 12VStorage: -20°C to 80°C
Industrial-20°C to 70°C at 12VStorage: -20°C to 80°C
Operate at -40°C to 85°C at 12V is by project basis discussion # Humidity 5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # HALT tested Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # EMI EN55032 Class B inside an enclosure Ultrasound equipment will typically be sensitive to noise in the 1MHz to 20MHz band, we shall handle it well during these bands # De-rating De-rating file is provided by RD (delta temperature of some of components is based on the experience of previous products) and reviewed/approved by RRC team before each Gerber Out Once we have real sample on-hand, the temperature of critical components shall be measured and feedback to the De-rating file to see if it still in specification. # MTBF 200,000 hrs commercial 40℃ ambient (according MIL calculation) based on actual calculated de-rating 120,000 hrs ETT -20℃\~70℃ ambient (according MIL calculation) based on actual calculated de-rating (excludes the BCM57504 LAN controller) # 3. Block Diagram ![**Left Column (J1)**\n* **Header:** J1\n* **Group Labels:** 'GROUP 0 Low', 'GROUP 0 High'\n* **Labeled Blocks/Items:**\n * 'PCIe Lane 0-3', 'PCIe Lane 4-7', 'PCIe Lane 8-11', 'PCIe Lane 12-15'\n * 'PCIe_BMC x1'\n * 'ETH_KR 0-3', 'ETH_KR 4-7'\n * '4x USB 3.x/2.0 0-3', '4x USB 2.0 4-7'\n * 'SATA Port 0-1'\n * 'NBASE-T 0'\n * 'BOOT_SPI', 'GPP_SPI'\n * 'SMBus'\n * 'I2C 0 (w/ ALERT#)', 'I2C 1'\n * 'UART 0', 'UART 1', 'GPIO x12'\n * 'USB_PD_IPMB', 'eSPI'\n\n**Central Block**\n* **Main Labels:** 'Ampere Computing', 'Altra'\n* **Top Labels:** '(Root Complex B)', 'can be x8', '(Root Complex B)', 'can be x8', '(Root Complex A)', '(Root Complex A)'\n* **Side Labels:** 'PCIe x8', 'PCIe x1', 'I2C_9', 'HSUART', 'HSUART', 'HSUART'\n\n**Right Column (J2)**\n* **Header:** J2\n* **Group Labels:** 'GROUP 1', 'GROUP 2', 'GROUP 3'\n* **Labeled Blocks/Items:**\n * 'PCIe Lane 16-31', 'PCIe Lane 32-47', 'PCIe Lane 48-63'\n * 'ETH_Sidebands', 'Rapid_Shutdown'\n\n**Intermediary and Peripheral Blocks**\n* **Small Blue Boxes:** 'BCM57502', 'µPD720201', 'LAN Intel i210', 'BIOS', 'TPM', 'EEPROM', 'MMC ATMEGA'\n* **Bottom Blocks:** 'Discrete (power sequence)', Six blocks labeled 'DIMM 3200 MT/s'\n* **Other Text:** 'Sensor for monitoring voltage/current/temp', 'UART_1 RTS#, CTS# simulated by GPIO'\n\n**Connections and Line Labels**\n* **Top Left:** Lines labeled '1 x4, 2 x2' connect 'PCIe Lane 0-3' and 'PCIe Lane 4-7' to the center block. Lines labeled '2 x2, 1 x4' connect 'PCIe Lane 8-11' and 'PCIe Lane 12-15' to the center block.\n* **Right Side:** Lines labeled '1 x16, 2 x8, 4 x4' connect 'PCIe Lane 16-31', 'PCIe Lane 32-47', and 'PCIe Lane 48-63' to the center block.\n* **Specific Connections:**\n * 'ETH_KR 0-3' connects to 'BCM57502', which connects to 'PCIe x8' on the center block.\n * '4x USB 3.x/2.0 0-3' connects to 'µPD720201', which connects to 'PCIe x1' on the center block.\n * 'NBASE-T 0' connects to 'LAN Intel i210', which connects to the center block.\n * 'BOOT_SPI' connects to 'BIOS', which connects to the center block.\n * 'GPP_SPI' connects to 'TPM', which connects to the center block.\n * 'SMBus' connects to 'EEPROM', which connects to 'I2C_9' on the center block.\n * 'USB_PD_IPMB', 'eSPI', and 'Sensor for monitoring voltage/current/temp' all connect to 'MMC ATMEGA'.](.com-hpc-alt-50m-00115-1010-11/3bae57313298a6c9a4ee2afb4befc2cdaaf9a07dbd0b4c1698d46cf0f045f455.jpg) Note: -All the PCIe are Gen4 -I2C\_9 from Altra SOC supports CCIX mode code (ready now) or general purpose SMBUS mode code (TBC), either one -UART\_1: TX, RX come from SOC, RTS#, CTS# are simulated by SOC GPIO -USB\_PD\_I2C, MMC, SOC: connect together -need work with AST2500 Remote BMC on carrier Figure 1 – Functional block diagram # 4. Pinout and Signal Descriptions # 4.1 Pin Summary The below table is a comprehensive list of all signal pins supported on the dual 400-pin COM-HPC connectors (J1 and J2) as defined for Server Type in the PICMG COM-HPC Rev 1.0 specification. Signals described in the specification but not supported on the COM-HPC-ALT are marked by strikethrough ROW A/B/C/D on J1 connector, ROW E/F/G/H on J2 connector ![J2\nPIN H100\nPIN E01\nSize E\n(200 x 160mm)\nJ1\nPIN A01\nPIN D100](.com-hpc-alt-50m-00115-1010-11/bd86c64fcadeafb0dd5822edcd6f40c08fd28f2e564aadc161a6bb7c3cce74c1.jpg) Figure 2 – Rear side row
Row ARow BRow CRow D
A1VCCB1VCCC1VCCD1VCC
A2VCCB2PWRBTN#C2RSTBTN#D2VCC
A3VCCB3VCCC3VCCD3VCC
A4VCCB4THERMTRIP#C4CARRIER_HOT#D4VCC
A5VCCB5VCCC5VCCD5VCC
A6VCCB6TAMPER#C6VIN_PWR_OKD6VCC
A7VCCB7VCCC7VCCD7VCC
A8VCCB8SUS_S3#C8SUS_S4_S5#D8VCC
A9VCCB9VCCC9VCCD9VCC
A10GNDB10WD_STROBE#C10GNDD10WAKE0#
A11BATLOW#B11WD_OUTC11FAN_PWMOUTD11WAKE1#
A12PLTRST#B12GNDC12FAN_TACHIND12GND
A13GNDB13USB5-C13GNDD13USB1-
A14USB7-B14USB5+C14USB3-D14USB1+
A15USB7+B15GNDC15USB3+D15GND
A16GNDB16USB4-C16GNDD16USB0-
A17USB6-B17USB4+C17USB2-D17USB0+
A18USB6+B18GNDC18USB2+D18GND
A19GNDB19RSVDC19GNDD19ETH0_RX-
A20ETH4_RX-B20RSVDC20ETH0_TX-D20ETH0_RX+
A21ETH4_RX+B21RSVDC21ETH0_TX+D21GND
A22GNDB22RSVDC22GNDD22ETH1_RX-
A23ETH5_RX-B23RSVDC23ETH1_TX-D23ETH1_RX+
A24ETH5_RX+B24VCC_5V_SBYC24ETH1_TX+D24GND
A25GNDB25USB67_OC#C25GNDD25ETH2_RX-
A26ETH6_RX-B26USB45_OC#C26ETH2_TX-D26ETH2_RX+
A27ETH6_RX+B27USB23_OC#C27ETH2_TX+D27GND
A28GNDB28USB01_OC#C28GNDD28ETH3_RX-
A29ETH7_RX-B29SML1_CLKC29ETH3_TX-D29ETH3_RX+
A30ETH7_RX+B30SML1_DATC30ETH3_TX+D30GND
A31GNDB31PMCALERT#C31GNDD31USB3_SSTX-
A32RSVDB32SML0_CLKC32USB3_SSRX-D32USB3_SSTX+
A33RSVDB33SML0_DATC33USB3_SSRX+D33GND
A34GNDB34USB_PD_ALERT#C34GNDD34USB2_SSTX-
A35ETH4_TX-B35USB_PD_I2C_CLKC35USB2_SSRX-D35USB2_SSTX+
A36ETH4_TX+B36USB_PD_I2C_DATC36USB2_SSRX+D36GND
A37GNDB37USB_RT_ENAC37GNDD37USB1_SSTX0-
A38ETH5_TX-B38USB1_LSRXC38USB1_SSRX0-D38USB1_SSTX0+
A39ETH5_TX+B39USB1_LSTXC39USB1_SSRX0+D39GND
A40GNDB40USB0_LSRXC40GNDD40USB1_SSTX1-
A41ETH6_TX-B41USB0_LSTXC41USB1_SSRX1-D41USB1_SSTX1+
A42ETH6_TX+B42GNDC42USB1_SSRX1+D42GND
A43GNDB43USB0_AUX-C43GNDD43USB0_SSTX0-
A44ETH7_TX-B44USB0_AUX+C44USB0_SSRX0-D44USB0_SSTX0+
A45ETH7_TX+B45RSVDC45USB0_SSRX0+D45GND
A46GNDB46RSVDC46GNDD46USB0_SSTX1-
A47USB1_AUX-B47VCC_BOOT_SPIC47USB0_SSRX1-D47USB0_SSTX1+
A48USB1_AUX+B48BOOT_SPI_CS#C48USB0_SSRX1+D48GND
A49GNDB49BSEL0C49GNDD49SATA0_RX-
A50eSPI_IO0B50BSEL1C50BOOT_SPI_IO0D50SATA0_RX+
A51eSPI_IO1B51BSEL2C51BOOT_SPI_IO1D51GND
A52eSPI_IO2B52eSPI_ALERT0#C52BOOT_SPI_IO2D52SATA0_TX-
A53eSPI_IO3B53eSPI_ALERT1#C53BOOT_SPI_IO3D53SATA0_TX+
A54eSPI_CLKB54eSPI_CS0#C54BOOT_SPI_CLKD54GND
A55GNDB55eSPI_CS1#C55GNDD55SATA1_RX-
A56PCIe_CLKREQ0_LO#B56eSPI_RST#C56PCIe_REFCLK0_HI-D56SATA1_RX+
A57PCIe_CLKREQ0_HI#B57GNDC57PCIe_REFCLK0_HI+D57GND
A58GNDB58PCIe_BMC_RX-C58GNDD58SATA1_TX-
A59PCIe_BMC_TX-B59PCIe_BMC_RX+C59PCIe_REFCLK0_LO-D59SATA1_TX+
A60PCIe_BMC_TX+B60GNDC60PCIe_REFCLK0_LO+D60GND
A61GNDB61PCIe08_RX-C61GNDD61PCIe00_TX-
A62PCIe08_TX-B62PCIe08_RX+C62PCIe00_RX-D62PCIe00_TX+
A63PCIe08_TX+B63GNDC63PCIe00_RX+D63GND
A64GNDB64PCIe09_RX-C64GNDD64PCIe01_TX-
A65PCIe09_TX-B65PCIe09_RX+C65PCIe01_RX-D65PCIe01_TX+
A66PCIe09_TX+B66GNDC66PCIe01_RX+D66GND
A67GNDB67PCIe10_RX-C67GNDD67PCIe02_TX-
A68PCIe10_TX-B68PCIe10_RX+C68PCIe02_RX-D68PCIe02_TX+
A69PCIe10_TX+B69GNDC69PCIe02_RX+D69GND
A70GNDB70PCIe11_RX-C70GNDD70PCIe03_TX-
A71PCIe11_TX-B71PCIe11_RX+C71PCIe03_RX-D71PCIe03_TX+
A72PCIe11_TX+B72GNDC72PCIe03_RX+D72GND
A73GNDB73PCIe12_RX-C73GNDD73PCIe04_TX-
A74PCIe12_TX-B74PCIe12_RX+C74PCIe04_RX-D74PCIe04_TX+
A75PCIe12_TX+B75GNDC75PCIe04_RX+D75GND
A76GNDB76PCIe13_RX-C76GNDD76PCIe05_TX-
A77PCIe13_TX-B77PCIe13_RX+C77PCIe05_RX-D77PCIe05_TX+
A78PCIe13_TX+B78GNDC78PCIe05_RX+D78GND
A79GNDB79PCIe14_RX-C79GNDD79PCIe06_TX-
A80PCIe14_TX-B80PCIe14_RX+C80PCIe06_RX-D80PCIe06_TX+
A81PCIe14_TX+B81GNDC81PCIe06_RX+D81GND
A82GNDB82PCIe15_RX-C82GNDD82PCIe07_TX-
A83PCIe15_TX-B83PCIe15_RX+C83PCIe07_RX-D83PCIe07_TX+
A84PCIe15_TX+B84GNDC84PCIe07_RX+D84GND
A85GNDB85RSVDC85GNDD85NBASET0_MDIO-
A86VCC_RTCB86RSMRST_OUT#C86SMB_CLKD86NBASET0_MDIO+
A87SUS_CLKB87UART1_TXC87SMB_DATD87GND
A88GPIO_00B88UART1_RXC88SMB_ALERT#D88NBASET0_MDI1-
A89GPIO_01B89UART1_RTS#C89UART0_TXD89NBASET0_MDI1+
A90GPIO_02B90UART1_CTS#C90UART0_RXD90GND
A91GPIO_03B91IPMB_CLKC91UART0_RTS#D91NBASET0_MDI2-
A92GPIO_04B92IPMB_DATC92UART0_CTS#D92NBASET0_MDI2+
A93GPIO_05B93GPSPI_MOSIC93I2C0_CLKD93GND
A94GPIO_06B94GPSPI_MISOC94I2C0_DATD94NBASET0_MDI3-
A95GPIO_07B95GPSPI_CS0#C95I2C0_ALERT#D95NBASET0_MDI3+
A96GPIO_08B96GPSPI_CS1#C96I2C1_CLKD96GND
A97GPIO_09B97GPSPI_CS2#C97I2C1_DATD97NBASET0_LINK_MAX#
A98GPIO_10B98GPSPI_CS3#C98NBASET0_SDPD98NBASET0_LINK_MID#
A99GPIO_11B99GPSPI_CLKC99NBASET0_CTREFD99NBASET0_LINK_ACT#
A100TYPE0B100GPSPI_ALERT#C100TYPE1D100TYPE2
Row ERow FRow GRow H
E1RAPID_SHUTDOWNF1ETH2_SDPG1RSVDH1RSVD
E2GNDF2ETH3_SDPG2RSVDH2RSVD
E3RSVDF3ETH4_SDPG3RSVDH3RSVD
E4RSVDF4ETH5_SDPG4RSVDH4RSVD
E5GNDF5ETH6_SDPG5RSVDH5RSVD
E6RSVDF6ETH7_SDPG6RSVDH6RSVD
E7RSVDF7ETH4-7_I2C_CLKG7RSVDH7RSVD
E8GNDF8ETH4-7_I2C_DATG8RSVDH8RSVD
E9RSVDF9ETH4-7_INT#G9RSVDH9RSVD
E10RSVDF10ETH4-7_MDIO_CLKG10RSVDH10RSVD
E11GNDF11ETH4-7_MDIO_DATG11RSVDH11RSVD
E12RSVDF12ETH4-7_PHY_INT#G12RSVDH12RSVD
E13RSVDF13ETH4-7_PHY_RST#G13RSVDH13RSVD
E14GNDF14ETH4-7_PRSNT#G14GNDH14RSVD
E15RSVDF15RSVDG15RSVDH15RSVD
E16RSVDF16RSVDG16RSVDH16RSVD
E17GNDF17RSVDG17RSVDH17RSVD
E18RSVDF18RSVDG18RSVDH18RSVD
E19RSVDF19GNDG19RSVDH19GND
E20GNDF20PCIe32_RX-G20GNDH20PCIe40_TX-
E21PCIe32_TX-F21PCIe32_RX+G21PCIe40_RX-H21PCIe40_TX+
E22PCIe32_TX+F22GNDG22PCIe40_RX+H22GND
E23GNDF23PCIe33_RX-G23GNDH23PCIe41_TX-
E24PCIe33_TX-F24PCIe33_RX+G24PCIe41_RX-H24PCIe41_TX+
E25PCIe33_TX+F25GNDG25PCIe41_RX+H25GND
E26GNDF26PCIe34_RX-G26GNDH26PCIe42_TX-
E27PCIe34_TX-F27PCIe34_RX+G27PCIe42_RX-H27PCIe42_TX+
E28PCIe34_TX+F28GNDG28PCIe42_RX+H28GND
E29GNDF29PCIe35_RX-G29GNDH29PCIe43_TX-
E30PCIe35_TX-F30PCIe35_RX+G30PCIe43_RX-H30PCIe43_TX+
E31PCIe35_TX+F31GNDG31PCIe43_RX+H31GND
E32GNDF32PCIe36_RX-G32GNDH32PCIe44_TX-
E33PCIe36_TX-F33PCIe36_RX+G33PCIe44_RX-H33PCIe44_TX+
E34PCIe36_TX+F34GNDG34PCIe44_RX+H34GND
E35GNDF35PCIe37_RX-G35GNDH35PCIe45_TX-
E36PCIe37_TX-F36PCIe37_RX+G36PCIe45_RX-H36PCIe45_TX+
E37PCIe37_TX+F37GNDG37PCIe45_RX+H37GND
E38GNDF38PCIe38_RX-G38GNDH38PCIe46_TX-
E39PCIe38_TX-F39PCIe38_RX+G39PCIe46_RX-H39PCIe46_TX+
E40PCIe38_TX+F40GNDG40PCIe46_RX+H40GND
E41GNDF41PCIe39_RX-G41GNDH41PCIe47_TX-
E42PCIe39_TX-F42PCIe39_RX+G42PCIe47_RX-H42PCIe47_TX+
E43PCIe39_TX+F43GNDG43PCIe47_RX+H43GND
E44GNDF44PCIe16_RX-G44GNDH44PCIe24_TX-
E45PCIe16_TX-F45PCIe16_RX+G45PCIe24_RX-H45PCIe24_TX+
E46PCIe16_TX+F46GNDG46PCIe24_RX+H46GND
E47GNDF47PCIe17_RX-G47GNDH47PCIe25_TX-
E48PCIe17_TX-F48PCIe17_RX+G48PCIe25_RX-H48PCIe25_TX+
E49PCIe17_TX+F49GNDG49PCIe25_RX+H49GND
E50GNDF50PCIe18_RX-G50GNDH50PCIe26_TX-
E51PCIe18_TX-F51PCIe18_RX+G51PCIe26_RX-H51PCIe26_TX+
E52PCIe18_TX+F52GNDG52PCIe26_RX+H52GND
E53GNDF53PCIe19_RX-G53GNDH53PCIe27_TX-
E54PCIe19_TX-F54PCIe19_RX+G54PCIe27_RX-H54PCIe27_TX+
E55PCIe19_TX+F55GNDG55PCIe27_RX+H55GND
E56GNDF56PCIe20_RX-G56GNDH56PCIe28_TX-
E57PCIe20_TX-F57PCIe20_RX+G57PCIe28_RX-H57PCIe28_TX+
E58PCIe20_TX+F58GNDG58PCIe28_RX+H58GND
E59GNDF59PCIe21_RX-G59GNDH59PCIe29_TX-
E60PCIe21_TX-F60PCIe21_RX+G60PCIe29_RX-H60PCIe29_TX+
E61PCIe21_TX+F61GNDG61PCIe29_RX+H61GND
E62GNDF62PCIe22_RX-G62GNDH62PCIe30_TX-
E63PCIe22_TX-F63PCIe22_RX+G63PCIe30_RX-H63PCIe30_TX+
E64PCIe22_TX+F64GNDG64PCIe30_RX+H64GND
E65GNDF65PCIe23_RX-G65GNDH65PCIe31_TX-
E66PCIe23_TX-F66PCIe23_RX+G66PCIe31_RX-H66PCIe31_TX+
E67PCIe23_TX+F67GNDG67PCIe31_RX+H67GND
E68GNDF68PCIe48_RX-G68GNDH68PCIe56_TX-
E69PCIe48_TX-F69PCIe48_RX+G69PCIe56_RX-H69PCIe56_TX+
E70PCIe48_TX+F70GNDG70PCIe56_RX+H70GND
E71GNDF71PCIe49_RX-G71GNDH71PCIe57_TX-
E72PCIe49_TX-F72PCIe49_RX+G72PCIe57_RX-H72PCIe57_TX+
E73PCIe49_TX+F73GNDG73PCIe57_RX+H73GND
E74GNDF74PCIe50_RX-G74GNDH74PCIe58_TX-
E75PCIe50_TX-F75PCIe50_RX+G75PCIe58_RX-H75PCIe58_TX+
E76PCIe50_TX+F76GNDG76PCIe58_RX+H76GND
E77GNDF77PCIe51_RX-G77GNDH77PCIe59_TX-
E78PCIe51_TX-F78PCIe51_RX+G78PCIe59_RX-H78PCIe59_TX+
E79PCIe51_TX+F79GNDG79PCIe59_RX+H79GND
E80GNDF80PCIe52_RX-G80GNDH80PCIe60_TX-
E81PCIe52_TX-F81PCIe52_RX+G81PCIe60_RX-H81PCIe60_TX+
E82PCIe52_TX+F82GNDG82PCIe60_RX+H82GND
E83GNDF83PCIe53_RX-G83GNDH83PCIe61_TX-
E84PCIe53_TX-F84PCIe53_RX+G84PCIe61_RX-H84PCIe61_TX+
E85PCIe53_TX+F85GNDG85PCIe61_RX+H85GND
E86GNDF86PCIe54_RX-G86GNDH86PCIe62_TX-
E87PCIe54_TX-F87PCIe54_RX+G87PCIe62_RX-H87PCIe62_TX+
E88PCIe54_TX+F88GNDG88PCIe62_RX+H88GND
E89GNDF89PCIe55_RX-G89GNDH89PCIe63_TX-
E90PCIe55_TX-F90PCIe55_RX+G90PCIe63_RX-H90PCIe63_TX+
E91PCIe55_TX+F91GNDG91PCIe63_RX+H91GND
E92GNDF92PCIe_REFCLK2-G92GNDH92PCIe_REFCLKIN0-
E93PCIe_REFCLK1-F93PCIe_REFCLK2+G93PCIe_REFCLK3-H93PCIe_REFCLKIN0+
E94PCIe_REFCLK1+F94GNDG94PCIe_REFCLK3+H94GND
E95GNDF95PCIe_CLKREQ3#G95GNDH95PCIe_REFCLKIN1-
E96PCIe_CLKREQ1#F96ETH0-3_PRSNT#G96ETH0-3_I2C_CLKH96PCIe_REFCLKIN1+
E97PCIe_CLKREQ2#F97ETH0-3_PHY_RST#G97ETH0-3_I2C_DATH97GND
E98PCIe_CLKREQ_OUT0#F98ETH0_SDPG98ETH0-3_PHY_INT#H98ETH0-3_MDIO_CLK
E99PCIe_CLKREQ_OUT1#F99ETH1_SDPG99ETH0-3_INT#H99ETH0-3_MDIO_DAT
E100PCIe_PERST_IN0#F100PCIe_PERST_IN1#G100PCIe_WAKE_OUT0#H100PCIe_WAKE_OUT1#
![The image features a red icon on a white background. It depicts a document or memo shape with the top-right corner folded down. Inside the red outline, there are two horizontal lines centered horizontally, representing text.](.com-hpc-alt-50m-00115-1010-11/8c0e34f5c540f9b04600b27c90e90a2a2e8d6d26fc13adf4a56671f6bfae0219.jpg) Note: Strikethrough entries are functions not supported by this product. IPMB is supported if there’s MMC on module. No eSPI support on this platform # 4.2 Signal Terminology Descriptions Definitions of the terms used for signal description tables
TermDescription
IInput to the module
OOutput from the module
I/OBi-directional Input / Output
ODOpen drain output from the module
I 3.3VInput 3.3V tolerant
I 5VInput 5V tolerant
O 3.3VOutput 3.3V signal level
O 5VOutput 5V signal level
I/O 3.3VBi-directional signal 3.3V tolerant
I/O 5VBi-directional signal 5V tolerant
I/O $3.3V_{SB}$ Input or output 3.3V tolerant active in standby state
DDCDisplay Data Channel
PCIEPCI Express compatible differential signal
PEGPCI Express Graphics
SATASerial ATA specification Revision 2.6 and 3
LVDSLow Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal
PPower Input / Output
REFReference voltage output. May be sourced from a Module power plane.
PDSPull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.
PUPU (pull-up) resistor on module
PDPD (pull-down) resistor on module
# 4.3 Signal Descriptions on J1/J2 Connectors # 4.3.1 Ethernet KR/KX Ethernet KR interface are defined for COM-HPC. For these ports, the Ethernet MACs are located on COM-HPC module. PHYs (if used) are on the Carrier. In some cases, no PHY is required, for short cable (“Direct Attach” cables) or Carrier runs. COM-HPC support both of MDIO and I2C control interfaces for the PHYs. The MDIO and I2C control interfaces are grouped into quads, for KR ports 0:3 and ports 4:7
NamePin #DescriptionI/OPU / PDComment
ETH0_TX-C20Ethernet KR ports, transmit output differential pairs.OAC coupled Off Module
ETH0_TX+C21KR
ETH1_TX-C23
ETH1_TX+C24
ETH2_TX-C26
ETH2_TX+C27
ETH3_TX-C29
ETH3_TX+C30
ETH0_RX-D19Ethernet KR ports, receive input differential pairs.IAC coupled Off Module
ETH0_RX+D20KR
ETH1_RX-D22
ETH1_RX+D23
ETH2_RX-D25
ETH2_RX+D26
ETH3_RX-D28
ETH3_RX+D29
ETH0-3_MDIO_DATH99Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 0 to 3I/O3.3VSBPU 2K2Not Supported
ETH0-3_MDIO_CLKH98Clock signal for Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 0 to 3O3.3VSBNot Supported
ETH0-3_INT#G99Active low interrupt signal from IO Port expanders for ETH ports 0 to 3I3.3VSBPU 4K7
ETH0-3_PHY_INT#G98Active low PHY interrupt signal from ETH ports 0 to 3I3.3VSBPU 4K7
ETH0-3_PHY_RST#F97Active low output PHY reset signal for ETH ports 0 to 3.O3.3VSB
ETH0-3_I2C_DATG97I2C data signal of the 2-wire management interface used by the Ethernet KR controller to access the management registers of an external SFP Module or to configure the Carrier PHY for ETHx ports 0 to 3 and for serialized status information (e.g. LED states)..I/O OD3.3VSBPU 1K
ETH0-3_I2C_CLKG96The I2C clock signals associated with ETH0-3 I2C data lines in the row above.I/O OD3.3VSBPU 1K
ETH0_SDPF98Software-Definable Pins. Can also be used for IEEE1588 support such as a PPS signal.I/O3.3VSBNot Supported
ETH1_SDPF99
ETH2_SDPF1
ETH3_SDPF2
ETH0-3_PRSNT#F96Carrier pulls this line to GND if there is Carrier hardware present to support Ethernet KR signalling on ETH0 through ETH3. If the entire KR quad is not supported it should fill from ETH0 on up.I3.3VSBPU 4K7
![The image shows a reddish-pink outline icon representing a document or page. It is roughly square-shaped with a folded bottom-right corner (a 'dog-ear'). Inside the outline, there are two horizontal lines centered vertically, resembling text or a list.](.com-hpc-alt-50m-00115-1010-11/ec3539a5ea159321f99d9498c6b4bd1e6ff8c2009e10fac3333f25608c912128.jpg) Note: The Ethernet KR support is 10GBASE-KR # 4.3.2 NBASE-T Ethernet The port may operate in 10Gbps, 5Gbps, 2.5Gbps, 1Gbps, 100Mbps, or 10Mbps modes. Magnetics are to be on the Carrier board. The COM-HPC module shall be capable of 1000BASE-T mode.
NamePin #DescriptionI/OPU / PDComment
NBASET0_MD10-NBASET0_MD10+NBASET0_MD11-NBASET0_MD11+NBASET0_MD12-NBASET0_MD12+NBASET0_MD13-NBASET0_MD13+D85D86D88D89D91D92D93D94Ethernet Controller 1: Media Dependent Interface Differential Pairs0,1,2,3. The MDI can operate in 10Gbps, 1Gbps, 100Mbps and 10Mbps modes. Some pairs are unused in some modes, per the following:I/O AnalogTwisted pair signals for external transformer.
$\phi$ 10000BASE-T $\phi$ 1000BASE-T $\phi$ 100BASE-TX $\phi$ 10BASE-T $\phi$
MDI[0]+/~ $\phi$ B1_DA+/- $\phi$ TX+/- $\phi$ TX+/- $\phi$
MDI[1]+/~ $\phi$ B1_DB+/- $\phi$ RX+/- $\phi$ RX+/- $\phi$
MDI[2]+/~ $\phi$ B1_DC+/- $\phi$ $\phi$ $\phi$
MDI[3]+/~ $\phi$ B1_DD+/- $\phi$ $\phi$ $\phi$
NBASET0_LINK_ACT#D99NBASE-T Ethernet Controller activity indicator, active low.20 mA or more current sink capability at VOL of 0.4V max.20 mA or more current source capability at VOH of 2.4V min.O 3.3VSBNeed add pull-high on carrier board
NBASET0_LINK_MAX#D97NBASE-T Ethernet Controller MAX Speed Link indicator, active low. If active, the link is established at the maximum speed that the Ethernet controller is capable of (which may be 10G, 5G, 2.5G etc).20 mA or more current sink capability at VOL of 0.4V max.20 mA or more current source capability at VOH of 2.4V min.O 3.3VSB
NBASET0_LINK_MID#D98NBASE-T Ethernet Controller MID Speed Link indicator, active low. If active, the link is established but at a speed lower than what the maximum speed that the Ethernet controller is capable of.20 mA or more current sink capability at VOL of 0.4V max.20 mA or more current source capability at VOH of 2.4V min.O 3.3VSB
NBASET0_CTREFC99Reference voltage for Carrier Board NBASET Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. If not needed, these pins may be left open on the Carrier. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be limited to 250 mA or less.REFGND min3.3V maxNot Supported
NBASET0_SDPC98NBASE-T Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as a 1pps signal.IO 3.3VSB
4.3.3 PCI Express
NamePin #DescriptionI/OPU / PDComment
PCIe00_TX+D62PCI Express Differential Transmit Pairs 0-7O PCIeAC coupled on Module
PCIe00_TX-D61PCIe Group 0 Low
PCIe01_TX+D65
PCIe01_TX-D64
PCIe02_TX+D68
PCIe03_TX-D67
PCIe03_TX+D71
PCIe03_TX-D70
PCIe04_TX+D74
PCIe04_TX-D73
PCIe05_TX+D77
PCIe05_TX-D76
PCIe06_TX+D80
PCIe06_TX-D79
PCIe07_TX+D83
PCIe07_TX-D82
PCIe00_RX+C63PCI Express Differential Receive Pairs 0-7I PCIeAC coupled off Module
PCIe00_RX-C62PCIe Group 0 Low
PCIe01_RX+C66
PCIe01_RX-C65
PCIe02_RX+C69
PCIe02_RX-C68
PCIe03_RX+C72
PCIe03_RX-C71
PCIe04_RX+C75
PCIe04_RX-C74
PCIe05_RX+C78
PCIe05_RX-C77
PCIe06_RX+C81
PCIe06_RX-C80
PCIe07_RX+C84
PCIe07_RX-C83
PCIe08_TX+A63PCI Express Differential Transmit Pairs 8-15O PCIeAC coupled on Module
PCIe08_TX-PCIe09_TX+A62A66PCIe Group 0 HighA Server Module may map up to 8 higher bandwidth PCIe lanes to Group 0 High
PCIe09_TX-A65
PCIe10_TX+A69
PCIe10_TX-A68
PCIe11_TX+A72
PCIe11_TX-A71
PCIe12_TX+A75
PCIe12_TX-A74
PCIe13_TX+A78
PCIe13_TX-A77
PCIe14_TX+A81
PCIe14_TX-A80
PCIe15_TX+A84
PCIe15_TX-A83
PCIe08_RX+B62PCI Express Differential Receive Pairs 8-15I PCIeAC coupled off Module
PCIe08_RX-B61PCIe Group 0 High
PCIe09_RX+B65A Server Module may map up to 8 higher bandwidth
PCIe09_RX-B64PCIe lanes to Group 0 High
PCIe10_RX+B68
PCIe10_RX-B67
PCIe11_RX+B71
PCIe11_RX-B70
PCIe12_RX+B74
PCIe12_RX-B73
PCIe13_RX+B77
PCIe13_RX-B76
PCIe14_RX+B80
PCIe14_RX-B79
PCIe15_RX+B83
PCIe15_RX-B82
PCIe16_TX+E46PCI Express Differential Transmit Pairs 16-31O PCIeAC coupled on Module
PCIe16_TX-E46PCIe Group 1
PCIe17_TX+E49
PCIe17_TX-E48
PCIe18_TX+E52
PCIe18_TX-E51
PCIe19_TX+E55
PCIe19_TX-E54
PCIe20_TX+E58
PCIe20_TX-E57
PCIe21_TX+E61
PCIe21_TX-E60
PCIe22_TX+E64
PCIe22_TX-E63
PCIe23_TX+E67
PCIe23_TX-E66
PCIe24_TX+H45
PCIe24_TX-H44
PCIe25_TX+H48
PCIe25_TX-H47
PCIe26_TX+H51
PCIe26_TX-H50
PCIe27_TX+H54
PCIe27_TX-H53
PCIe28_TX+H57
PCIe28_TX-H56
PCIe29_TX+H60
PCIe29_TX-H59
PCIe30_TX+H63
PCIe30_TX-H62
PCIe31_TX+H66
PCIe31_TX-H65
PCIe16_RX+F45PCI Express Differential Receive Pairs 16-31PCIe Group 1I PCIeAC coupled off Module
PCIe16_RX-F44
PCIe17_RX+F48
PCIe17_RX-F47
PCIe18_RX+F51
PCIe18_RX-F50
PCIe19_RX+F54
PCIe19_RX-F53
PCIe20_RX+F57
PCIe20_RX-F56
PCIe21_RX+F60
PCIe21_RX-F59
PCIe22_RX+F63
PCIe22_RX-F62
PCIe23_RX+F66
PCIe23_RX-PCIe24_RX+PCIe24_RX-PCIe25_RX+PCIe25_RX-PCIe26_RX+PCIe26_RX-PCIe27_RX+PCIe27_RX-PCIe28_RX+PCIe28_RX-PCIe29_RX+PCIe29_RX-PCIe30_RX+PCIe30_RX-PCIe31_RX+PCIe31_RX-F65G46G45G49G48G52G51G55G54G58G57G61G60G64G63G67G66
PCIe32_TX+PCIe32_TX-PCIe33_TX+PCIe33_TX-PCIe34_TX+PCIe34_TX-PCIe35_TX+PCIe35_TX-PCIe36_TX+PCIe36_TX-PCIe37_TX+PCIe37_TX-PCIe38_TX+PCIe38_TX-PCIe39_TX+PCIe39_TX-PCIe40_TX+PCIe40_TX-PCIe41_TX+PCIe41_TX-PCIe42_TX+PCIe42_TX-PCIe43_TX+E22E21E25E24E28E27E31E30E34E33E37E36E40E39E43E42H22H21H24H23H27H26H30PCI Express Differential Transmit Pairs 32-47PCIe Group 2O PCIeAC coupled on Module
PCIe43_TX-H29
PCIe44_TX+H33
PCIe44_TX-H32
PCIe45_TX+H36
PCIe45_TX-H35
PCIe46_TX+H39
PCIe46_TX-H38
PCIe47_TX+H42
PCIe47_TX-H41
PCIe32_RX+F21PCI Express Differential Receive Pairs 32-47PCIe Group 2I PCIeAC coupled off Module
PCIe32_RX-F20
PCIe33_RX+F24
PCIe33_RX-F23
PCIe34_RX+F27
PCIe34_RX-F26
PCIe35_RX+F30
PCIe35_RX-F29
PCIe36_RX+F33
PCIe36_RX-F32
PCIe37_RX+F36
PCIe37_RX-F35
PCIe38_RX+F39
PCIe38_RX-F38
PCIe39_RX+F42
PCIe39_RX-F41
PCIe40_RX+G22
PCIe40_RX-G21
PCIe41_RX+G25
PCIe41_RX-G24
PCIe42_RX+G28
PCIe42_RX-G27
PCIe43_RX+G31
PCIe43_RX-G30
PCIe44_RX+G34
PCIe44_RX-G33
PCIe45_RX+G37
PCIe45_RX-G36
PCIe46_RX+G40
PCIe46_RX-G39
PCIe47_RX+PCIe47_RX-G43G42
PCIe48_TX+PCIe48_TX-PCIe49_TX+PCIe49_TX-PCIe50_TX+PCIe50_TX-PCIe51_TX+PCIe51_TX-PCIe52_TX+PCIe52_TX-PCIe53_TX+PCIe53_TX-PCIe54_TX+PCIe54_TX-PCIe55_TX+PCIe55_TX-PCIe56_TX+PCIe56_TX-PCIe57_TX+PCIe57_TX-PCIe58_TX+PCIe58_TX-PCIe59_TX+PCIe59_TX-PCIe60_TX+PCIe60_TX-PCIe61_TX+PCIe61_TX-PCIe62_TX+PCIe62_TX-PCIe63_TX+PCIe63_TX-E70E69E73E72E76E75E79E78E82E81E85E84E88E87E91E90H69H68H72H71H75H74H78H77H81H80H84H83H87H86H91H90PCI Express Differential Transmit Pairs 48-63PCIe Group 3O PCIeAC coupled on Module
PCIe48_RX+PCIe48_RX-PCIe49_RX+PCIe49_RX-PCIe50_RX+PCIe50_RX-PCIe51_RX+PCIe51_RX-PCIe52_RX+PCIe52_RX-PCIe53_RX+PCIe53_RX-PCIe54_RX+PCIe54_RX-PCIe55_RX+PCIe55_RX-PCIe56_RX+PCIe56_RX-PCIe57_RX+PCIe57_RX-PCIe58_RX+PCIe58_RX-PCIe59_RX+PCIe59_RX-PCIe60_RX+PCIe60_RX-PCIe61_RX+PCIe61_RX-PCIe62_RX+PCIe62_RX-PCIe63_RX+PCIe63_RX-F69F68F72F71F75F74F78F77F81F80F84F83F87F86F90F89G70G69G73G72G76G75G79G78G82G81G85G84G84G88G87G91G90PCI Express Differential Receive Pairs 48-63PCIe Group 3I PCIeAC coupled off Module
PCIe_BMC_TX-PCIe_BMC_TX+A59A60PCI Express Differential Transmit Pair for Carrier BMC(Board Management Controller)O PCIeAC coupled on Module
PCIe_BMC_RX-PCIe_BMC_RX+B58B59PCI Express Differential Transmit Pair for Carrier BMC(Board Management Controller)I PCIeAC coupled off Module
PCIe_REFCLK0_LO-PCIe_REFCLK0_LO+C59C60Reference clock pair for PCIe lanes [0:7], also referred to PCIe Group 0 Low and for the PCIe_BMC linkO PCIe
PCIe_REFCLK0_HI-PCIe_REFCLK0_HI+C57C56Reference clock pair for PCIe lanes [8:15], also referred to PCIe Group 0 HighO PCIe
PCIe_REFCLK1-PCIe_REFCLK1+E93E94Reference clock pair for PCIe lanes [16:31], also referred to PCIe Group 1O PCIe
PCIe_REFCLK2-PCIe_REFCLK2+F92F93Reference clock pair for PCIe lanes [32:47], also referred to PCIe Group 2O PCIe
PCIe_REFCLK3-PCIe_REFCLK3+G93G94Reference clock pair for PCIe lanes [48:63], also referred to PCIe Group 2O PCIe
PCIe_CLKREQ0_LO#A56PCIe reference clock request signals from Carrier devices for PCIe_REFCLK0_LO clock pairI/O OD3.3VPU 10K
PCIe_CLKREQ0_HI#A57PCIe reference clock request signals from Carrier devices for PCIe_REFCLK0_HI clock pairI/O OD3.3VPU 10K
PCIe_CLKREQ0_1#E96PCIe reference clock request signals from Carrier devices for PCIe_REFCLK1 clock pairI/O OD3.3VPU 10K
PCIe_CLKREQ0_2#E97PCIe reference clock request signals from Carrier devices for PCIe_REFCLK2 clock pairI/O OD3.3VPU 10K
PCIe_CLKREQ0_3#F95PCIe reference clock request signals from Carrier devices for PCIe_REFCLK3 clock pairI/O OD3.3VPU 10K
# 4.3.4 USB The COM-HPC Server Module supports up to eight USB 2.0 ports, up to two USB 3.2 Gen1 or Gen2 ports and up to two USB 3.2 Gen2x2 ports or USB4 ports. A USB 3.2 Gen2x2 may be used as USB 3.2 Gen1 or Gen2 port as well. To realize a COM-HPC USB 3.2 Gen1, Gen2, Gen2x2 or USB4 port, one of the four available USB 2.0 ports from the USB[0:3] pool must be used along with the SuperSpeed pins. The specific pairings noted in table below need to be made.
NamePin #DescriptionI/OPU / PDComment
USB0+D17USB 2.0 differential pairs, channels 0 through 7.I/OUSB 1.1/2.0 compliant
USB0-D163.3VSBThis product only support USB0-3 through a PCIe to USB IC
USB1+D14USB0 may be configured as a USB client or as a host,or both at the Module designer's discretion. All other
USB1-D13
USB2+C18USB ports, if implemented, shall be host ports.
USB2-C17
USB3+C15If any SuperSpeed ports are implemented, then theymust be supported by a USB 2.0 port, using one ofthe USB[0:3] ports from this pool.
USB3-C14
USB0_SSTX0+D44Four sets of SuperSpeed transmit pairs, used torealize the transmit side of two USB 3.2 Gen 2x2ports.O PCIeAC coupled on Module
USB0_SSTX0-D43This product only support USB0-3 (up to USB 3.2 Gen1)through a PCIe to USB IC
USB1_SSTX0+D38Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TXpair, single RX pair per port) may be implementedusing a portion of this interface.
USB1_SSTX0-D37These ports shall be used in conjunction with thecorresponding USB 2.0 port pair (e.g. USB0_SSxxx+/- shall be used with the USB0 USB 2.0 pair and so on,USB1_SSxxx+/- with the USB1 USB 2.0 pair).
USB0_SSRX0+C45Four sets of SuperSpeed receive pairs, used to realizethe transmit side of two USB 3.2 Gen 2x2 ports.I PCIeAC coupled off Module
USB0_SSRX0-C44This product only support USB0-3 (up to USB 3.2 Gen1)through a PCIe to USB IC
USB1_SSRX0+C39Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TXpair, single RX pair per port) may be implementedusing a portion of this interface.
USB1_SSRX0-C38These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/- shall be used with the USB0 USB 2.0 pair and so on, USB1_SSxxx+/- with the USB1 USB 2.0 pair).
USB2_SSTX+USB2_SSTX-USB3_SSTX+USB3_SSTX-D35D34D32D31Two sets of high speed transmit pairs, to realize two USB 3.2 Gen 1 or Gen 2 implementations.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/- shall be used with the USB2 USB 2.0 pair and USB3_SSxxx+/- with the USB3 USB 2.0 pair).O PCIeAC coupled on ModuleThis product only support USB0-3 (up to USB 3.2 Gen1) through a PCIe to USB IC
USB2_SSRX+USB2_SSRX-USB3_SSRX+USB3_SSRX-C36C35C33C32Two sets of high speed receive pairs, to realize two USB 3.2 Gen 1 or Gen 2 implementations.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/- shall be used with the USB2 USB 2.0 pair and USB3_SSxxx+/- with the USB3 USB 2.0 pair).I PCIeAC coupled off ModuleThis product only support USB0-3 (up to USB 3.2 Gen1) through a PCIe to USB IC
USB01_OC#USB23_OC#USB45_OC#USB67_OC#B28B27B26B25USB over-current sense, USB channels 0,1; channels 2,3; channels 4,5 and channels 6,7 respectively.A pull-up for each of these lines to the 3.3V Suspend rail shall be present on the Module.The pull-up should be 10K. An open drain driver from USB current monitors on the Carrier Board may drive this line low. The Carrier Board shall not pull these lines up.Note that the over-current limits for USB 2.0 and USB 3.0 are different; this is a Carrier board implementation item.I 3.3VSBPU 10K3.3VSBDo not pull high on carrier
RSMRST_OUT#B86USB devices that are to be powered in the S5 / S4 / S3 Suspend states should not have their 5V VBUS power enabled before RSMRST_OUT# transitions to the hi state.RSMRST_OUT# is also described in Power and System Management sectionO3.3VSB
This platform doesn’t support USB4, thus additional signals required by USB4 are not shown here. # 4.3.5 Asynchronous Serial Port Two logic level Module “5 wire” (TX, RX, RTS#, CTS#, GND) asynchronous serial ports are provided for general purpose use and for use with debugging software that make use of the “console redirect” features available in many BIOS and operating systems. The Module BIOS should support “console redirect” to the UART0 port. It is preferred that if the Module is based on an Intel x86 architecture, the Module serial ports be I/O mapped and be register compatible with the National Semiconductor 16550 UARTs that were used in the PC AT architecture. The Module asynchronous serial ports should not be implemented as USB peripherals, as such implementations are generally not useful for low level debug purposes. The COM-HPC UART signals are “logic level” signals and are the logic inverse of what is on an RS-232 line. The “Mark” (logic 1) voltage level is nominally 3.3V on the COM-HPC line and the “Space” (logic 0) is nominally 0V. RS-232 transceivers (on the Carrier) invert the signals and change the levels – so that a “Mark” is between -3V and -25V, and a “Space” is between +3V and +25V In some situations, the UARTx\_RTS# line can be used alternatively as an RS485 transmit enable line.
NamePin #DescriptionI/OPU / PDComment
UART0_TXC89Logic level asynchronous serial port transmit signalO 3.3V
UART1_TXB87
UART0_RXC90Logic level asynchronous serial port receive signalI 3.3VPU 10K
UART1_RXB88
UART0_RTS#C91Logic level asynchronous serial port Request to Send signal, active lowO 3.3V
UART1_RTS#B89
UART0_CTS#C92Logic level asynchronous serial port Clear to Send input, active lowI 3.3V
UART1_CTS#B90
# 4.3.6 I2C Two general purpose I2C ports are defined for COM-HPC. The first of the two supports an ALERT# input. The ports shall support 100KHz operation and should 400KHz operation. The ports should be multi-master capable. I2C0 is defined to operate from a 3.3V rail and I2C1 from a 1.8V rail. The I2C1 port may be I3C capable. I2C source from Ampere Altra SOC supports multi-master
NamePin #DescriptionI/OPU / PDComment
I2C0_CLKC93Clock I/O line for the general purpose I2C0 portI/O OD 3.3VSBPU 2K2 3.3VSB
I2C0_DATC94Data I/O line for the general purpose I2C0 portI/O OD 3.3VSBPU 2K2 3.3VSB
I2C0_ALERT#C95Alert input / interrupt for I2C0I 3.3VPU 2K2 3.3VSB
I2C1_CLKC96Clock I/O line for the general purpose I2C1 portI/O OD 1.8VSBPU 4K7 1.8VSBI3C Not supported
I2C1_DATC97Data I/O line for the general purpose I2C1 portI/O OD 1.8VSBPU 4K7 1.8VSBI3C Not supported
![The image displays a red outline icon of a document or piece of paper. The top right corner is folded down. Inside the outline, there are two horizontal red lines, resembling text or a list.](.com-hpc-alt-50m-00115-1010-11/f2910e2bede20780e4f053034369e0a1169ae4d91df0e3f188477221c47aa606.jpg) Note: multi-master support is I2C0 and I2C1 Supports 100KHz, 400KHz, and 1MHz # 4.3.7 Port 80 Support on USB\_PD I2C Bus COM-HPC Module should support exporting Port 80 information over the USB\_PD I2C bus (signals USB\_PD\_I2C\_DAT and USB\_PD\_I2C\_CLK) (pin B36 and B35) to Carrier hardware that implements a pair of 7-segment displays to show the codes. # 4.3.8 IPMB An IPMB (Intelligent Platform Management Bus) port is defined for both the Client and Server pinout types for platform management functions. The IPMB is used (optionally) with a Carrier based BMC (Board Management Controller) Master. On the Module, the IPMB should be routed to and used with a MMC (Module Management Controller). The Module IPMB is a slave port. See Section Error! Bookmark not defined. below for more details on platform management topics.
NamePin #DescriptionI/OPU / PDComment
IPMB_CLKB91Clock I/O line for the multi-master IPMB portI/O OD3.3VSBPU 2K23.3VSB
IPMB_DATB92Data I/O line for the multi-master IPMB portI/O OD3.3VSBPU 2K23.3VSB
![The image shows a simple icon of a document or page. It features a thick red outline of a piece of paper with the bottom-right corner folded over. Inside the white interior of the page, there are two horizontal red bars positioned near the center, resembling lines of text.](.com-hpc-alt-50m-00115-1010-11/08dc53967431f9fa7c3d4e5aef8ff2cf18c3193b30359a736fb736ceed2ceb72.jpg) Note: Weak pull-up values are shown for the IPMB CLK and DAT lines in Table above. These are merely to prevent the lines from floating if no Carrier BMC is present. Stiffer pull-ups should be implemented on the Carrier with values appropriate to the situation at hand if the Carrier implements a BMC and an IPMB master. # 4.3.9 General Purpose SPI
NamePin #DescriptionI/OPU / PDComment
GP_SPI_MISOB94Serial data into the COM-HPC Module from the Carrier GP_SPI device ("Master In Slave Out")I 3.3V
GP_SPI_MOSIB93Serial data from the COM-HPC Module to the Carrier GP_SPI device ("Master Out Slave In")O 3.3V
GP_SPI_CLKB99Clock from the Module to Carrier GP_SPI deviceO 3.3V
GP_SPI_CS0#B95GP_SPI chip selects, active lowO 3.3VGP_SPI CS2 and CS3 are not supported.
GP_SPI_CS1#B96
GP_SPI_CS2#B97
GP_SPI_CS3#B98
GP_SPI_ALERT#B100Alert (interrupt) from a Carrier GP_SPI device to the ModuleI 3.3VPU 10K
# 4.3.10 Power & System Management VIN\_PWR\_OK indicates that all the power to the Module is stable within the specified range and can be used to enable Module internal power supplies.
NamePin #DescriptionI/OPU / PDComment
PWRBTN#B02A falling edge creates a power button event. Power button events can be used to bring a system out of S5 soft off and other suspend states, as well as powering the system down.I 3.3VSBPU 10K
RSTBTN#C02Reset button input. Active low request for Module to reset and reboot. May be falling edge sensitive. For situations when RSTBTN# is not able to reestablish control of the system, VIN_PWR_OK or a power cycle may be used.I 3.3VSBPU 90K
PLTRST#A12Platform Reset: output from Module to Carrier Board. Active low. Issued by Module chipset and may result from a low RSTBTN# input, a low VIN_PWR_OK input, a VCC power input that falls below theminimum specification, a watchdog timeout, ormaybe initiated by the Module software..O 3.3VSB
VIN_PWR_OKC06Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow Carrier based FPGAs or other configurable devices time to be programmed.I 3.3VPU 10K
SUS_S3#B08Indicates system is in Suspend to RAM state. Active low output. An inverted copy of SUS_S3# on the Carrier Boardshouldbe used to enable the non-standby power on a typical ATX supply.Even in single input supply system implementations (AT mode, no standby input), the SUS_S3# Module output should be used disable any Carrier voltage regulators when SUS_S3# is low, to prevent bleed leakage from Carrier circuits into the Module.O 3.3VSBNot Supported
SUS_S4_S5#C08Indicates system is in Suspend to Disk (S4) or Soft Off (S5) state. Active low output.O 3.3VSB
SUS_CLKA8732.768 kHz +/- 100 ppm clock used by Carrier peripherals such as M.2 cards in their low power modes.O 3.3VSB
WAKE0#D10PCI Express wake up signal.I/O 3.3VSBPU 10K
WAKE1#D11General purpose wake up signal. May be used to implement wake-up on PS2 keyboard or mouse activity.I 3.3VSBPU 10K
BATLOW#A11Indicates that external battery is low.This port provides a battery-low signal to the Module for orderly transitioning to power saving or power cut-off ACPI modes.I 3.3VSBPU 10K
TAMPER#B06Tamper or Intrusion detection line on VCC_RTC power well. Carrier hardware pulls this low on a Tamper event.Not Supported
RSMRST_OUT#B86This is a buffered copy of the internal Module RSMRST# (Resume Reset, active low) signal. The internal Module RSMRST# signal is an input to the chipset or SOC and when it transitions from low to high it indicates that the suspend well power rails are stable.USB devices on the Carrier that are to be active in S5 / S3 / S0 should not have their 5V supply applied before RSMRST_OUT# goes high.RSMRST_OUT# shall be a 3.3V CMOS Module output, active in all power states.O 3.3VSB
# 4.3.11 Thermal Protection
NamePin #DescriptionI/OPU / PDComment
CARRIER_HOT#C04Input from off-Module temp sensor indicating an over-temp situation.I 3.3VPU 4.7K
THERMTRIP#B04Active low output indicating that the CPU has entered thermal shutdown.O 3.3V
# 4.3.12 SMBus
NamePin #DescriptionI/OPU / PDComment
SMB_CLKC86System Management Bus bidirectional clock line.I/O OD 3.3VSBPU 2.2KThe maximum capacitance on the Carrier Board shall not exceed 100pF
SMB_DATC87System Management Bus bidirectional data line.I/O OD 3.3VSBPU 2.2KThe maximum capacitance on the Carrier Board shall not exceed 100Pf
SMB_ALERT#C88System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system.I 3.3VSBPU 10KThe maximum capacitance on the Carrier Board shall not exceed 100pF
# 4.3.13 General Purpose Input Outputs
NamePin #DescriptionI/OPU / PDComment
GPIO_00A88General purpose input / output pins. Upon a hardware reset, these pins should be configured as inputs.I/O3.3VSBPU 100K3.3VSB
GPIO_01A89
GPIO_02A90
GPIO_03A91
GPIO_04A92As inputs, these pins should be able to generate an interrupt to the Module host.
GPIO_05A93
GPIO_06A94
GPIO_07A95
GPIO_08A96
GPIO_09A97
GPIO_10A98
GPIO_11A99
4.3.14 Module Type Definition
NamePin #DescriptionI/OComment
TYPE0A100The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC). These pins shall be pulled up on the Carrier, to Carrier standby voltage rail of 5V or less. Carrier hardware reads the level on these straps.Server Module – Fixed 12V input
TYPE1C100
TYPE2D100
Module ConnectionsMeaning
RefTYPE2TYPE1TYPE0
7NCNCNCReserved
6NCNCGNDReserved
5NCGNDNCReserved
4NCGNDGNDServer Module – Fixed 12V input
3GNDNCNCReserved
2GNDNCGNDReserved
1GNDGNDNCClient Module - Wide Range 8V to 20V input
0GNDGNDGNDClient Module – Fixed 12V input
The Module shall implement all three TYPE[x] pins per the table above.
The Carrier Board should implement combinatorial logic that monitors the Module TYPE pins and keeps power off (e.g deactivates the ATX PS_ON# signal to an ATX power supply or otherwise deactivates VCC to the COM-HPC Module) if an incompatible Module pin-out type is detected. All three TYPE[x] pins should be monitored by the Carrier. The Carrier Board logic may also implement a fault indicator such as an LED.
4.3.15 Miscellaneous Signals
NamePin #DescriptionI/OPU / PDComment
WD_OUTB11Output indicating that a watchdog time-out event has occurred. Refer to Section 5.3 for details.O 3.3V
WD_STROBE#B10Strobe input to watchdog timer. Periodic strobing prevents the watchdog, if enabled, from timing out.I 3.3V
FAN_PWMOUTC11Fan speed control for a secondary system fan. The primary fan control signals for CPU thermal management are on the Module, along with a vendor specific connector.Fan controls use the Pulse Width Modulation (PWM) technique to control the fan's RPM. CMOS output; Carrier designers should buffer this signal with an open drain FET and pullup or other robust Carrier device(s).O 3.3V
FAN_TACHINC12Fan tachometer input for a fan with a two pulse output for the secondary fan.I OD 3.3VPU 10K
RSVDReserved pins. These may be assigned functions in future versions of this specification. Reserved pins shall not be connected to anything, and shall not be connected to each other.
WD\_OUT If a Module supports a watchdog timer it shall minimally support output mode 1 and may also support output modes 2 or 3 as defined in the table below. The selection of the output modes may be realized by software configurable hardware or by Module build options.
WD ModeDescriptionComment
1The Module generates an internal reset. Module output pin PLTRST# is driven low. The WD_OUT pin is driven high until the unit resets.
2The Module only drives WD_OUT pin high until cleared by Module software.
3The Module generates an NMI. The WD_OUT pin is driven high until cleared by Module software.
The watchdog output shall come up as a logic low and shall be disabled upon power-on-reset (VCC power cycle) or external system reset (when RSTBTN# pin is toggled low by external hardware). The watchdog may be enabled by BIOS or system software. # WD\_STROBE# Typically, the watchdog parameters (output options, enabling, enable delay, timeout delay) are managed by the Module BIOS, often via a BIOS setup screen. The regular watchdog software strobes to prevent a watchdog timeout are typically handled by the Module’s application software. There may be API abstractions to isolate the application software from the watchdog hardware. In COM-HPC (unlike COM-Express), there is a hardware strobe option. Carrier board hardware may periodically drive (“strobe”) the Module WD\_STROBE# input pin low to keep the watchdog from timing out. The software and hardware strobes should be implemented as a logical OR by the Module design, so that either method may be used, or both, to keep the watchdog from timing out. The software programmable Watchdog Enable Delay is the time between when the watchdog is enabled by firmware and when the first watchdog strobe is needed to prevent a watchdog time out. The enable delay allows time for the operating system to boot and the application to load and initialize. This feature is sometimes referred to as a “two stage” watchdog. After the initial Enable Delay, the enabled watchdog must be periodically strobed by software to prevent a watchdog timeout. The Strobe Interval shall be software programmable. Recommended ranges in enable delay and max strobe periods are given in the following table.
Min ValueMax Value
Enable Delay1 second10 minutes
Strobe Interval0.1 second10 minutes
4.3.16 Power and Ground
NamePin #DescriptionI/OPU / PDComment
VCCA01-A09B01B03B05B07B09C01C03C05C07C09D01-D09Primary power input:fixed +12V on the Client Type 0; wide range +8V to +20V on the Client Type 1; fixed +12V on the Server.All available VCC pins on the connector shall be used.P12V +/- 5%
VCC_5V_SBYB24Standby power input: +5.0V nominal.Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.P5VSB +/- 5%
VCC_RTCA86Real-time clock circuit-power input. Nominally +3.0V.P
GNDGround - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to Carrier Board GND plane(s).P
# 5. Additional Features This chapter describes the connectors, LEDs, and switches, located on the module and are not necessarily included in the PICMG standard specification. The locations of these parts are as shown below: ![BIOS\nDefault\nReset\nFan Connector\nADLINK COM-HPCS](.com-hpc-alt-50m-00115-1010-11/efddd2fa6c2baf73e64044c8eca91ef22b534c48439855288b5c6cfeba6161ed.jpg) ![40-Pin\nDebug\nConnect\nLOTES SKT 4926 BP DIC:11720A](.com-hpc-alt-50m-00115-1010-11/ea383dba69445bcb85bf1bdced11b01e8ca595afe16ebe4039e89ffacdc34258.jpg) # 5.1 Debug Connector (40-pin connector) This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: • SPI BIOS programming interface I2C bus for BIOS POST code readout • BMC programming interface Test points for measurement of internal power rails ![Scanned technical diagram of a computer motherboard layout with labeled components and connectors](.com-hpc-alt-50m-00115-1010-11/b5e8d8ba8d8c7dafcf5b66f0b48796aa01e08a3b7b74d137d1c3b5f5f41cf07e.jpg) ![Illustration of a mechanical device with a lever and shaft, no visible text or symbols](.com-hpc-alt-50m-00115-1010-11/5d98878edccda209f56623ebae613ae21e7ef811842bfb022d48916faa39af45.jpg) # 5.2 Status LEDs Status LEDs are mounted on the module as below LED1 LED2 LED3 ![Close-up of a green printed circuit board with various electronic components and connectors (no visible text or symbols)](.com-hpc-alt-50m-00115-1010-11/1d3ae00a79c3702627761655915d0fbd7a3326e3c44e2805dc94e4ee1c31c25f.jpg)
NameColorConnectionFunction
LED1BlueBMC outputPower Sequence Status Code (BMC) Power Changes, Reset (see Exception Codes Table below)
LED2GreenPower Source 3VccS0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3RedBMC output and same signal as WDT (B27) on BtB connectorModule power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a Reset not initiated by the BMC can clear the WD LED (user action)
# 5.3 Fan Connector Connector Type: JVE 24W1125A-04M00 ![Close-up of a green printed circuit board with various electronic components and connectors (no readable text or symbols)](.com-hpc-alt-50m-00115-1010-11/b6da02e2bb1c33d46e3198e5fcd1344e3cbafcf379c256d78477eb9795b6e9af.jpg)
NameDescription
1FAN_PWMOUT
2FAN_TACHIN
3GND
412V*
The supply voltage and maximum current of the fan connector is dependent on the module’s input voltage (VCC\_12V pins) • If the module’s input voltage is 12V or lower, the supply voltage will be equal to the module’s input voltage and the maximum supply current of the fan connector will be TBC mA. • If the module’s input voltage is from 12V to 20V, the supply voltage will be 12V (± 5%) and the maximum supply current of the fan connector will be TBC mA.. # 5.4 BIOS Default Reset (update later) ![The image shows a close-up of a green circuit board with a red arrow pointing horizontally from the left towards a small, white, rectangular socket connector. Below this connector is another similar white socket. To the right, there are small black surface-mounted components and a larger black rectangular chip. At the bottom, a large, circular gold-colored pad with a central hole is visible.](.com-hpc-alt-50m-00115-1010-11/66bf6bf55ab66a6db02af39d304444c3a23c2a7f206d9a47ee76a06723f64e78.jpg) To perform a hardware reset of the default BIOS settings, follow the steps below: 1. Shut down the system. 2. Hold down the BIOS Setup Defaults Reset Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears. 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.com-hpc-alt-50m-00115-1010-11/35d4a0a6a52dbc41126ad986db11821d99084286867aaccea5a6b31ea95c3943.jpg) # 5.5 BIOS Boot Select (update later) The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using the BIOS Select and Mode Configuration Switch, Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, BIOS Select and Mode Configuration Switch, Pin 1 is used to select whether to boot from SPI0 or SPI1.
ModePin 1Pin 2
Boot from SPI0 (default)On-
Boot from SPI1Off-
Set BIOS to PICMG mode (default, TBC)-On
Set BIOS to Failsafe BIOS mode-Off
# 6. BIOS Checkpoints, Beep Codes This document section lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board-specific checkpoint definitions. # Checkpoints and Beep Codes Definition A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout the boot block and Power-On Self-Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process. Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker. # Aptio Boot Flow While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions: Security (SEC) – initial low-level initialization Pre-EFI Initialization (PEI) – memory initialization1 Driver Execution Environment (DXE) – main hardware initialization2 Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, …) # Viewing BIOS Checkpoints Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a POST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display. Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated. Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing AMI Aptio BIOS checkpoints. 1 Analogous to “boot block” functionality of legacy BIOS 2 Analogous to “POST” functionality in legacy BIOS # Aptio V Checkpoint and Beep Codes Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com # Viewing Checkpoints Checkpoints generated by Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-in cards show the value of I/O port 80h on a LED display. Checkpoint cards are available through a variety of computer mail-order outlets. Newer systems feature support for AMI Debug Rx, a USB connected alternative to the PCI POST Card. AMI Debug Rx is a low-cost debug tool built around the debug port feature common to today’s USB 2.0 EHCI controllers. AMI Debug Rx is designed as replacement for the PCI POST Checkpoint Card as newer systems omit PCI expansion slots. Along with checkpoints, AMI Debug Rx has several features specifically designed for BIOS developers. # 6.1 Status Code Ranges
Code RangeDescription
0x01 – 0x0BSEC execution
0x0C – 0x0FSEC errors
0x10 – 0x2FPEI execution up to and including memory detection
0x30 – 0x4FPEI execution after memory detection
0x50 – 0x5FPEI errors
0x60 – 0x8FDXE execution up to BDS
0x90 – 0xFCBDS execution
0xD0 – 0xDFDXE errors
0xE0 – 0xE8S3 Resume (PEI)
0xE9 – 0xEFS3 Resume errors (PEI)
0xF0 – 0xF8Recovery (PEI)
0xF9 – 0xFFRecovery errors (PEI)
Note: Table above is subject to future updates. # 7. Mechanical and Thermal # 7.1 Module Dimensions ![200\nJ2\nCLOSE LOPE\nDTCUXXW\nOPEN K201\n160\nJ1](.com-hpc-alt-50m-00115-1010-11/4bcba235d6df6cbd7c7ed490ab5174adfc455bf74dae67a5cd5966e706d56a44.jpg) Figure 3 – Module dimensions (mm) # 7.2 Thermal Solutions # 7.2.1 Heatsink : THS-ALT-BL ![3D rendering of a heat sink component with ribbed heat fins and mounting feet (no text or symbols)](.com-hpc-alt-50m-00115-1010-11/806b01087489b652ad1cff7a6d5ca97a3600df17cb766a875b75d9f39fb3d3ef.jpg) Figure 4 – Heatsink THS-ALT-BL # 7.2.2 Low Profile Active Cooler: THSF-ALT-BL-S ![3D rendering of a COM-HPC® heat sink with cooling fins and fan (no text or symbols on the diagram itself)](.com-hpc-alt-50m-00115-1010-11/f043dbf59adada3431124007932fba1184c78c0a60747bb6b4878373603ccbd0.jpg) Figure 5 – THSF-ALT-BL-S # 7.2.3 High Profile Passive Heatsink: THSH-ALT-VC ![3D technical illustration of a heat exchanger or cooling unit with multiple heat sinks and cooling elements (no text or symbols visible)](.com-hpc-alt-50m-00115-1010-11/8d990a6cde3c2adbdca726d51357ff2365fcf0899736b2f46e5edfe1762a04a4.jpg) Figure 6 – High profile passive heatsink THSH-ALT-VC # 7.2.4 Active Cooling: THSF-ALT-BL ![3D rendering of a computer cooling unit with two blue fans and a red heat sink (no text or symbols visible)](.com-hpc-alt-50m-00115-1010-11/29f34072e753a625d9a7dad2a8b16d3e60c995f50523aaf7b8ecd1330edc5624.jpg) Figure 7 – Cooler THSF-ALT-BL [🔗 Link to the original document](.com-hpc-alt-50m-00115-1010-11/com-hpc-alt-50m-00115-1010-11.pdf)