# COM-HPC Client Base

User’s Guide

![Close-up of a dark printed circuit board with visible components like J1, J2, and COM-HPC, no readable text or symbols beyond labels.](.com-hpc-client-base-manual-50m-77108-1000-01/2e78279643f45600e1af2638299258c116abacd7f28911004fdb9ec9774e1427.jpg)

Revision: 0.1 Preliminary

Date: 2024-06-16

Part Number: 50M-77108-1000

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2024-06-16</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

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California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

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# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2024 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a red icon on a white background. It features a stylized outline of a document or piece of paper with a folded bottom-right corner. Inside the red border, there are three horizontal red lines centered vertically, resembling text lines.](.com-hpc-client-base-manual-50m-77108-1000-01/874ef9254edaaa9891efd0c02438d59adaa7d2dfd17cf96e11961d138d2bc435.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a standard warning icon featuring a yellow triangle with rounded corners. Inside the triangle is a white exclamation mark centered vertically.](.com-hpc-client-base-manual-50m-77108-1000-01/dd94d9faf3ec154be14994c93bf6f64ff8b9c16de683ef3c6a1755eaf45648bc.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![A red triangular warning sign featuring a white exclamation point in its center.](.com-hpc-client-base-manual-50m-77108-1000-01/d6f5aa66827d785e48912c79f912eae6f753df915415d15a0e7822508fee4816.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

1. Introduction ... .10
2. Special Features.. .1

2.1. PCI Express x16 Gen5... . 11
2.2. Two Ethernet RJ45.. . 11
2.3. Two USB4 Type-C.. 11
2.4. Two M.2 Connector ... . 11

3. Component Location....... ..12
4. Functional Diagram... .13
5. Connectors and Pinouts ...... ..14

5.1. Carrier Board Signals — Client Type .. .. 14
5.2. Connector Location and Pinout Compatibility... .. 15
5.3. Carrier Board Design... ... 16
5.4. COM-HPC Board-to-board Connectors.. .. 16
5.5. PCIe x16 Slot.. . 22
5.6. PCIe x4 Slot ... .. 23
5.7. PCIe x1 Slot ... .. 24
5.8. M.2 M-KEY... .. 25
5.9. M.2 E-KEY... .. 26
5.10. DisplayPort / HDMI... . 27
5.11. eDP / DSI.. .. 27
5.12. Audio HDA .. .. 29
5.13. Audio SNDW .. . 29
5.14. Ethernet NBASE-T... . 30
5.15. CSI Camera Serial Interface .. . 30
5.16. USB .. . 31
5.17. GPIO ... .. 33
5.18. I2C .. ... 33
5.19. UART / COM... . 34
5.20. eSPI Debug Connector.. . 35

5.21. SMB ... . 35
5.22. FAN Connector.. . 36
5.23. Carrier BIOS... . 37
5.24. GP\_SPI... . 37
5.25. Front Panel Control.. . 38
5.26. Other Jumpers .. . 38
5.27. Power Connectors.. . 39

6. Carrier BIOS (need update) .... ...41

7. Switches, POST and LEDs.. ...42

7.1. Switches.. . 42

7.2. POST and inductors LEDs.. ... 42

7.3. ATX Power Connectors .. .. 43

7.4. AT Power Mode... .. 43

# List of Figures

Figure 1 – Component location.. ..12
Figure 2 – Functional diagram.............. ...13
Figure 3 – Carrier board signals, Server type pinout......... ...14
Figure 4 – Connector location and pinout compatibility (Size C as example) ... .15

# 1. Introduction

![The image displays a red warning sign shaped like a triangle with rounded corners. Centered inside the red triangle is a white exclamation mark. The background surrounding the sign is white.](.com-hpc-client-base-manual-50m-77108-1000-01/19b6d9b6424446e73c1578dcb7edde36db20cb5da0e8c2125e7d3afcab1b7b64.jpg)

Warning: This is an EA (early available) engineering manual. The contents may not accurately reflect the actual or final version of this product.

The COM-HPC modular approach of custom carrier combined with off-the-shelf system cores relives developers and manufacturers the need to design their own system core, thereby not only accelerating their proof of concept significantly but also empowers them to upgrade to later generation processors without redesign. The COM-HPC concept reduces engineering complexity, lowers the threshold for total project quantity, and last but not least brings your product to the market in no time. The average time to design a carrier board is less than half the time of a full custom board.

The COM-HPC Client Base, based on PICMG COM-HPC R1.0, is an ATX size carrier board, supplied by ATX and AT power source through 24+4 power connector. Together with the COM-HPC Client Type module of your choice and off-the-shelf add-on cards, you can quickly emulate the functionality of your desired end product for software development and hardware verification.

To build a functional prototype of your target system you will need:

COM-HPC Client Type module
COM-HPC Client Base carrier
PCI Express-based storage or SATA storage (SATA storage solutions are dependent on module specifications)

The COM-HPC Client Base is compatible with Size A, Size B and Size C COM-HPC Client Type modules and may accommodate:

1x PCI Express x16 slot, up to Gen5
2x PCI Express x4 slots, 3x PCI Express x1 slots and 1x M.2 M-key connector, 1x M.2 E-key connector
2x DP ports, 1x HDMI port, 1x eDP connector and 3-in-1 Audio port
2x USB4 Type-C, 2x USB3 Type-A, 2x USB2 Type-A and multiple USB headers for front panel usage
2x Ethernet RJ45 connector, up to 10GBASE-T
2x MIPI-CSI connectors

# 2. Special Features

# 2.1. PCI Express x16 Gen5

FHFL PCI Express cards in the PCIE16-31 slot can support up to 2-slot-width PCI Express cards. of the capability of PCI Express Gen5 depends on the module specifications.

# 2.2. Two Ethernet RJ45

2x RJ45 connectors are capable of 10GbE speed, depending on the module specifications.

# 2.3. Two USB4 Type-C

2x USB4 Type-C connectors support up to USB 40Gbit/s and DisplayPort, depending on the module specifications.

# 2.4. Two M.2 Connector

1x M.2 M-key (PCIe x4, up to 22110) for NVMe storage usage.

1x M.2 E-key (PCIex1 and USB, up to 2230) for wireless module usage.

# 3. Component Location

![J1\nJ2\nJ3\nJ4\nJ5\nJ6\nJ7\nJ8\nJ9\nJ10\nJ11\nJ12\nJ13\nJ14\nJ15\nJ16\nJ17\nJ18\nJ19\nJ20\nJ21\nJ22\nJ23\nJ24\nJ25\nJ26\nJ27\nJ28\nJ29\nJ30\nJ31\nJ32\nJ33\nJ34\nJ35\nJ36\nJ37\nJ38\nJ39\nJ40\nJ41\nJ42\nJ43\nJ44\nJ45\nJ46\nJ47\nJ48\nJ49\nJ50\nJ51\nJ52\nJ53\nJ54\nJ55\nJ56\nJ57\nJ58\nJ59\nJ60\nJ61\nJ62\nJ63\nJ64\nJ65\nJ66\nJ67\nJ68\nJ69\nJ70\nJ71\nJ72\nJ73\nJ74\nJ75\nJ76\nJ77\nJ78\nJ79\nJ80\nJ81\nJ82\nJ83\nJ84\nJ85\nJ86\nJ87\nJ88\nJ89\nJ90\nJ91\nJ92\nJ93\nJ94\nJ95\nJ96\nJ97\nJ98\nJ99\nJ100](.com-hpc-client-base-manual-50m-77108-1000-01/368c51a3c18a080654695c2553c2ca34d58529532da75b7283922f85cfd53b32.jpg)

Figure 1 – Component location

# 4. Functional Diagram

![This block diagram, titled **COM-HPC Client Base**, illustrates the connectivity of a high-performance client motherboard. It centers around two main processing blocks, **NBASET_0** and **NBASET_1**, and details their connections to various external ports, expansion slots, and peripheral controllers.\n\n**Main Processing Blocks:**\n*   **NBASET_0**: A large grey block containing labels for various interfaces including **DDI_0**, **DDI_1**, **EDP**, **PCIe 5**, **PCIe 6**, **PCIe 7**, **PCIe 0-3**, **PCIe 12-15**, **PCIe 8-11**, **PCIe 4 / USB2_6**, **GPIO_0-11**, **UART_0-1**, **I2C_0**, **I2C_1**, **Boot_SPI**, **GP_SPI**, **SMB**, **ESPI**, **Thermal**, **HDA**, **SNDW_0-1**, **USB2_4-5**, **USB2_0-1**, **USB4/3.x_0-1**, **USB2_3**, **USB2_7**, and **USB2_2**.\n*   **NBASET_1**: A large grey block containing labels for **PCIe 16-31**, **DDI_2**, **CSI_0**, **CSI_1**, **USB4/3.x_3**, and **USB4/3.X_2**.\n\n**External Connectors and Peripherals:**\n*   **Top Left:** Two **RJ45** connectors, a **DP** connector, an **HDMI** connector, and another **DP** connector.\n*   **Left Side (IO Panel):** Audio jacks (Blue, Green, Pink), and two sets of **USB Type A** and **USB Type C** ports.\n*   **Expansion Slots:** Two **PCIe x1** slots, two **PCIe x4** slots, an **M.2 M Key** slot, an **M.2 E Key** slot, and a **PCIe x16** slot (far right).\n*   **Camera:** Two camera connectors connected to **CSI_0** and **CSI_1**.\n*   **Front Panel:** **2xUSB (front panel)** (two instances), and **USB TypeE (front panel)**.\n*   **Other:** **2x COM** ports, **2x FAN connector**.\n\n**Intermediary Blocks and Connections:**\n*   **Audio:** The audio jacks connect to the **Audio Codec TBC** block, which links to **HDA** and **SNDW_0-1** in **NBASET_0**.\n*   **Thunderbolt/USB-C:** The **USB Type C** and **Type A** ports connect to a dashed box containing **TBT4 Intel JHL8540** and **USB PD TI TPS65994AE**. This block connects to **NBASET_0** via lines labeled **2xUSB**, **2xUSB (for Type C)**, and **2xUSB (for Type A)**.\n*   **USB Hubs:** Two **USB Hub** blocks connect the internal **USB2_7** / **USB2_2** and **USB2_3** lines to the **2xUSB (front panel)** headers.\n*   **Super I/O:** A **Super I/O NCT6126D** block connects to **2x COM** and **2x FAN connector**. It is linked to **NBASET_0** via headers labeled **GPIO_0-11**, **UART_0-1**, **I2C_0**, **I2C_1**, **Boot_SPI**, **GP_SPI**, **SMB**, **ESPI**, and **Thermal**. It also connects to an **EEPROM** block.\n*   **PCIe Routing:**\n    *   **NBASET_0** connects to **PCIe x1**, **PCIe x4**, **M.2 M Key**, and **M.2 E Key** slots.\n    *   **NBASET_1** connects to the **PCIe x16** slot.\n    *   **DDI_2** in **NBASET_1** connects to the lower **DP** port.\n    *   **DDI_0** / **DDI_1** in **NBASET_0** connect to the **HDMI** port.\n    *   **EDP** in **NBASET_0** connects to the upper **DP** port.\n    *   The top two **RJ45** connectors connect to **NBASET_0**.\n    *   **USB4/3.x_3** / **USB4/3.X_2** in **NBASET_1** connect to **USB TypeE (front panel)**.](.com-hpc-client-base-manual-50m-77108-1000-01/22265d32fd08b9b41c92b2ad6fd9a53f48a68f7f252384260e17fc8645269d8f.jpg)

Figure 2 – Functional diagram

# 5. Connectors and Pinouts

# 5.1. Carrier Board Signals — Client Type

![| Category | Component | Value |\n| -------- | --------- | ----- |\n| J2 (E/F/G/H) | DDI 3 | 32x |\n| J2 (E/F/G/H) | USB 4/3.x upgrade | 2x |\n| J2 (E/F/G/H) | PCIe | 32x |\n| J2 (E/F/G/H) | NBASE-T (max. 10G) | 1 |\n| J2 (E/F/G/H) | MIPI CSI | 2x |\n| J2 (E/F/G/H) | ETH_KR (max. 25G) | 2x |\n| J2 (E/F/G/H) | PCIe Target | - |\n| J2 (E/F/G/H) | RSVD | - |\n| J1 (A/B/C/D) | 12V (8-20V opt.) | 5Vsb |\n| J1 (A/B/C/D) | USB 2.0 | 8x |\n| J1 (A/B/C/D) | USB 4/3.x upgrade | 2x |\n| J1 (A/B/C/D) | Audio I2S / Soundwire | - |\n| J1 (A/B/C/D) | DDI 1 | - |\n| J1 (A/B/C/D) | DDI 2 | - |\n| J1 (A/B/C/D) | eDP /DSI | - |\n| J1 (A/B/C/D) | IPMB & PCIe | - |\n| J1 (A/B/C/D) | eSPI | - |\n| J1 (A/B/C/D) | SATA | 2x |\n| J1 (A/B/C/D) | PCIe | 16x |\n| J1 (A/B/C/D) | NBASE-T (max. 10G) | 0 |\nBoot SPI, GP_SPI, 2x UART, SMB, 2x I2C, 12x GPIO, Fusa are defined on the specification but not shown above](.com-hpc-client-base-manual-50m-77108-1000-01/9e2e9ffedae35f276776b019fb944e436b9fae5f3749a6d453d8315c518011f4.jpg)

Figure 3 – Carrier board signals, Server type pinout

# 5.2. Connector Location and Pinout Compatibility

Connector positions and pinouts comply with the pinout and signal descriptions within the PICMG COM-HPC Carrier Design Guide R2. This document includes: descriptions of pinouts, signals, and mechanical characteristics of the COM-HPC specification. The COM-HPC Client Base carrier is compatible with COM-HPC modules in Size A, Size B and Size C form factor, Client Type pinout, and COM-HPC Module Base Specification R1.x.

![pin H100\nJ2 upper side\npin E01\npin D100\nJ1 lower side\npin A01](.com-hpc-client-base-manual-50m-77108-1000-01/b0de90a4ad2e08440ffb2dc4e75d22830f74a454e9bbae837a985f61db4b95ea.jpg)

Figure 4 – Connector location and pinout compatibility (Size C as example)

# 5.3. Carrier Board Design

COM-HPC Client Base follows the PICMG COM-HPC Carrier Design Guide where possible, and its design and schematic have been fully verified. It is recommended to utilize them as references for your carrier board design. COM-HPC Client Base schematics and mechanical files, as well as the CDG, can be downloaded from ADLINK COM’s webpage.

# 5.4. COM-HPC Board-to-board Connectors

Signals and Pinouts for COM-HPC Client Type (Size A, B & C)

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>VCC</td><td></td><td>B1</td><td>VCC</td><td></td><td>C1</td><td>VCC</td><td></td><td>D1</td><td>VCC</td></tr><tr><td>A2</td><td>VCC</td><td></td><td>B2</td><td>PWRBTN#</td><td></td><td>C2</td><td>RSTBTN#</td><td></td><td>D2</td><td>VCC</td></tr><tr><td>A3</td><td>VCC</td><td></td><td>B3</td><td>VCC</td><td></td><td>C3</td><td>VCC</td><td></td><td>D3</td><td>VCC</td></tr><tr><td>A4</td><td>VCC</td><td></td><td>B4</td><td>THERMTRIP#</td><td></td><td>C4</td><td>CARRIER_HOT#</td><td></td><td>D4</td><td>VCC</td></tr><tr><td>A5</td><td>VCC</td><td></td><td>B5</td><td>VCC</td><td></td><td>C5</td><td>VCC</td><td></td><td>D5</td><td>VCC</td></tr><tr><td>A6</td><td>VCC</td><td></td><td>B6</td><td>TAMPER#</td><td></td><td>C6</td><td>VIN_PWR_OK</td><td></td><td>D6</td><td>VCC</td></tr><tr><td>A7</td><td>VCC</td><td></td><td>B7</td><td>VCC</td><td></td><td>C7</td><td>VCC</td><td></td><td>D7</td><td>VCC</td></tr><tr><td>A8</td><td>VCC</td><td></td><td>B8</td><td>SUS_S3#</td><td></td><td>C8</td><td>SUS_S4_S5#</td><td></td><td>D8</td><td>VCC</td></tr><tr><td>A9</td><td>VCC</td><td></td><td>B9</td><td>VCC</td><td></td><td>C9</td><td>VCC</td><td></td><td>D9</td><td>VCC</td></tr><tr><td>A10</td><td>GND</td><td></td><td>B10</td><td>WD_STROBE#</td><td></td><td>C10</td><td>GND</td><td></td><td>D10</td><td>WAKE0#</td></tr><tr><td>A11</td><td>BATLOW#</td><td></td><td>B11</td><td>WD_OUT</td><td></td><td>C11</td><td>FAN_PWMOUT</td><td></td><td>D11</td><td>WAKE1#</td></tr><tr><td>A12</td><td>PLTRST#</td><td></td><td>B12</td><td>GND</td><td></td><td>C12</td><td>FAN_TACHIN</td><td></td><td>D12</td><td>GND</td></tr><tr><td>A13</td><td>GND</td><td></td><td>B13</td><td>USB5-</td><td></td><td>C13</td><td>GND</td><td></td><td>D13</td><td>USB1-</td></tr><tr><td>A14</td><td>USB7-</td><td></td><td>B14</td><td>USB5+</td><td></td><td>C14</td><td>USB3-</td><td></td><td>D14</td><td>USB1+</td></tr><tr><td>A15</td><td>USB7+</td><td></td><td>B15</td><td>GND</td><td></td><td>C15</td><td>USB3+</td><td></td><td>D15</td><td>GND</td></tr><tr><td>A16</td><td>GND</td><td></td><td>B16</td><td>USB4-</td><td></td><td>C16</td><td>GND</td><td></td><td>D16</td><td>USB0-</td></tr><tr><td>A17</td><td>USB6-</td><td></td><td>B17</td><td>USB4+</td><td></td><td>C17</td><td>USB2-</td><td></td><td>D17</td><td>USB0+</td></tr><tr><td>A18</td><td>USB6+</td><td></td><td>B18</td><td>GND</td><td></td><td>C18</td><td>USB2+</td><td></td><td>D18</td><td>GND</td></tr><tr><td>A19</td><td>GND</td><td></td><td>B19</td><td>I2S_LRCLK/SNDW_CLK3/HDA_SYNC</td><td></td><td>C19</td><td>GND</td><td></td><td>D19</td><td>DDIO_SDA_AUX-</td></tr><tr><td>A20</td><td>DDI1_SDA_AUX-</td><td></td><td>B20</td><td>I2S_DOUT/SNDW_DAT3/HDA_SDO</td><td></td><td>C20</td><td>SNDW_DMIC_CLK1</td><td></td><td>D20</td><td>DDIO_SCL_AUX+</td></tr><tr><td>A21</td><td>DDI1_SCL_AUX+</td><td></td><td>B21</td><td>I2S_MCLK/HDA_RST#</td><td></td><td>C21</td><td>SNDW_DMIC_DAT1</td><td></td><td>D21</td><td>GND</td></tr><tr><td>A22</td><td>GND</td><td></td><td>B22</td><td>I2S_DIN/SNDW_DAT2/HDA_SDI</td><td></td><td>C22</td><td>GND</td><td></td><td>D22</td><td>DDIO_PAIR0-</td></tr><tr><td>A23</td><td>DDI1_PAIR0-</td><td></td><td>B23</td><td>I2S_CLK/SNDW_CLK2/HDA_BCLK</td><td></td><td>C23</td><td>SNDW_DMIC_CLK0</td><td></td><td>D23</td><td>DDI0_PAIR0+</td></tr><tr><td>A24</td><td>DDI1_PAIR0+</td><td></td><td>B24</td><td>VCC_5V_SBY</td><td></td><td>C24</td><td>SNDW_DMIC_DAT0</td><td></td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>GND</td><td></td><td>B25</td><td>USB67_OC#</td><td></td><td>C25</td><td>GND</td><td></td><td>D25</td><td>DDI0_PAIR1-</td></tr><tr><td>A26</td><td>DDI1_PAIR1-</td><td></td><td>B26</td><td>USB45_OC#</td><td></td><td>C26</td><td>DDI0_DDC_AUX_SEL</td><td></td><td>D26</td><td>DDI0_PAIR1+</td></tr><tr><td>A27</td><td>DDI1_PAIR1+</td><td></td><td>B27</td><td>USB23_OC#</td><td></td><td>C27</td><td>DDI1_DDC_AUX_SEL</td><td></td><td>D27</td><td>GND</td></tr><tr><td>A28</td><td>GND</td><td></td><td>B28</td><td>USB01_OC#</td><td></td><td>C28</td><td>DDI0_HPD</td><td></td><td>D28</td><td>DDI0_PAIR2-</td></tr><tr><td>A29</td><td>DDI1_PAIR2-</td><td></td><td>B29</td><td>SML1_CLK</td><td></td><td>C29</td><td>DDI1_HPD</td><td></td><td>D29</td><td>DDI0_PAIR2+</td></tr><tr><td>A30</td><td>DDI1_PAIR2+</td><td></td><td>B30</td><td>SML1_DAT</td><td></td><td>C30</td><td>eDP_HPD</td><td></td><td>D30</td><td>GND</td></tr><tr><td>A31</td><td>GND</td><td></td><td>B31</td><td>PMCALERT#</td><td></td><td>C31</td><td>eDP_VDD_EN</td><td></td><td>D31</td><td>DDI0_PAIR3-</td></tr><tr><td>A32</td><td>DDI1_PAIR3-</td><td></td><td>B32</td><td>SML0_CLK</td><td></td><td>C32</td><td>eDP_BKLT_EN</td><td></td><td>D32</td><td>DDI0_PAIR3+</td></tr><tr><td>A33</td><td>DDI1_PAIR3+</td><td></td><td>B33</td><td>SML0_DAT</td><td></td><td>C33</td><td>eDP_BKLTCTL</td><td></td><td>D33</td><td>GND</td></tr><tr><td>A34</td><td>GND</td><td></td><td>B34</td><td>USB_PD_ALERT#</td><td></td><td>C34</td><td>GND</td><td></td><td>D34</td><td>AC_PRESENT</td></tr><tr><td>A35</td><td>eDP_AUX-</td><td></td><td>B35</td><td>USB_PD_I2C_CLK</td><td></td><td>C35</td><td>USB1_AUX-</td><td></td><td>D35</td><td>RSVD</td></tr><tr><td>A36</td><td>eDP_AUX+</td><td></td><td>B36</td><td>USB_PD_I2C_DAT</td><td></td><td>C36</td><td>USB1_AUX+</td><td></td><td>D36</td><td>GND</td></tr><tr><td>A37</td><td>GND</td><td></td><td>B37</td><td>USB_RT_ENA</td><td></td><td>C37</td><td>GND</td><td></td><td>D37</td><td>USB1_SSTX0-</td></tr><tr><td>A38</td><td>eDP_TX0-</td><td></td><td>B38</td><td>USB1_LSRX</td><td></td><td>C38</td><td>USB1_SSRX0-</td><td></td><td>D38</td><td>USB1_SSTX0+</td></tr><tr><td>A39</td><td>eDP_TX0+</td><td></td><td>B39</td><td>USB1_LSTX</td><td></td><td>C39</td><td>USB1_SSRX0+</td><td></td><td>D39</td><td>GND</td></tr><tr><td>A40</td><td>GND</td><td></td><td>B40</td><td>USB0_LSRX</td><td></td><td>C40</td><td>GND</td><td></td><td>D40</td><td>USB1_SSTX1-</td></tr><tr><td>A41</td><td>eDP_TX1-</td><td></td><td>B41</td><td>USB0_LSTX</td><td></td><td>C41</td><td>USB1_SSRX1-</td><td></td><td>D41</td><td>USB1_SSTX1+</td></tr><tr><td>A42</td><td>eDP_TX1+</td><td></td><td>B42</td><td>GND</td><td></td><td>C42</td><td>USB1_SSRX1+</td><td></td><td>D42</td><td>GND</td></tr><tr><td>A43</td><td>GND</td><td></td><td>B43</td><td>USB0_AUX-</td><td></td><td>C43</td><td>GND</td><td></td><td>D43</td><td>USB0_SSTX0-</td></tr><tr><td>A44</td><td>eDP_TX2-</td><td></td><td>B44</td><td>USB0_AUX+</td><td></td><td>C44</td><td>USB0_SSRX0-</td><td></td><td>D44</td><td>USB0_SSTX0+</td></tr><tr><td>A45</td><td>eDP_TX2+</td><td></td><td>B45</td><td>LID#</td><td></td><td>C45</td><td>USB0_SSRX0+</td><td></td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>GND</td><td></td><td>B46</td><td>SLEEP#</td><td></td><td>C46</td><td>GND</td><td></td><td>D46</td><td>USB0_SSTX1-</td></tr><tr><td>A47</td><td>eDP_TX3-</td><td></td><td>B47</td><td>VCC_BOOT_SPI</td><td></td><td>C47</td><td>USB0_SSRX1-</td><td></td><td>D47</td><td>USB0_SSTX1+</td></tr><tr><td>A48</td><td>eDP_TX3+</td><td></td><td>B48</td><td>BOOT_SPI_CS#</td><td></td><td>C48</td><td>USB0_SSRX1+</td><td></td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GND</td><td></td><td>B49</td><td>BSEL0</td><td></td><td>C49</td><td>GND</td><td></td><td>D49</td><td>SATA0_RX-</td></tr><tr><td>A50</td><td>eSPI_IO0</td><td></td><td>B50</td><td>BSEL1</td><td></td><td>C50</td><td>BOOT_SPI_IO0</td><td></td><td>D50</td><td>SATA0_RX+</td></tr><tr><td>A51</td><td>eSPI_IO1</td><td></td><td>B51</td><td>BSEL2</td><td></td><td>C51</td><td>BOOT_SPI_IO1</td><td></td><td>D51</td><td>GND</td></tr><tr><td>A52</td><td>eSPI_IO2</td><td></td><td>B52</td><td>eSPI_ALERT0#</td><td></td><td>C52</td><td>BOOT_SPI_IO2</td><td></td><td>D52</td><td>SATA0_TX-</td></tr><tr><td>A53</td><td>eSPI_IO3</td><td></td><td>B53</td><td>eSPI_ALERT1#</td><td></td><td>C53</td><td>BOOT_SPI_IO3</td><td></td><td>D53</td><td>SATA0_TX+</td></tr><tr><td>A54</td><td>eSPI_CLK</td><td></td><td>B54</td><td>eSPI_CS0#</td><td></td><td>C54</td><td>BOOT_SPI_CLK</td><td></td><td>D54</td><td>GND</td></tr><tr><td>A55</td><td>GND</td><td></td><td>B55</td><td>eSPI_CS1#</td><td></td><td>C55</td><td>GND</td><td></td><td>D55</td><td>SATA1_RX-</td></tr><tr><td>A56</td><td>PCIe_CLKREQ0_LO#</td><td></td><td>B56</td><td>eSPI_RST#</td><td></td><td>C56</td><td>PCIe_REFCLK0_HI-</td><td></td><td>D56</td><td>SATA1_RX+</td></tr><tr><td>A57</td><td>PCIe_CLKREQ0_HI#</td><td></td><td>B57</td><td>GND</td><td></td><td>C57</td><td>PCIe_REFCLK0_HI+</td><td></td><td>D57</td><td>GND</td></tr><tr><td>A58</td><td>GND</td><td></td><td>B58</td><td>PCIe_BMC_RX-</td><td></td><td>C58</td><td>GND</td><td></td><td>D58</td><td>SATA1_TX-</td></tr><tr><td>A59</td><td>PCIe_BMC_TX-</td><td></td><td>B59</td><td>PCIe_BMC_RX+</td><td></td><td>C59</td><td>PCIe_REFCLK0_LO-</td><td></td><td>D59</td><td>SATA1_TX+</td></tr><tr><td>A60</td><td>PCIe_BMC_TX+</td><td></td><td>B60</td><td>GND</td><td></td><td>C60</td><td>PCIe_REFCLK0_LO+</td><td></td><td>D60</td><td>GND</td></tr><tr><td>A61</td><td>GND</td><td></td><td>B61</td><td>PCIe08_RX-</td><td></td><td>C61</td><td>GND</td><td></td><td>D61</td><td>PCIe00_TX-</td></tr><tr><td>A62</td><td>PCIe08_TX-</td><td></td><td>B62</td><td>PCIe08_RX+</td><td></td><td>C62</td><td>PCIe00_RX-</td><td></td><td>D62</td><td>PCIe00_TX+</td></tr><tr><td>A63</td><td>PCIe08_TX+</td><td></td><td>B63</td><td>GND</td><td></td><td>C63</td><td>PCIe00_RX+</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>GND</td><td></td><td>B64</td><td>PCIe09_RX-</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>PCIe01_TX-</td></tr><tr><td>A65</td><td>PCIe09_TX-</td><td></td><td>B65</td><td>PCIe09_RX+</td><td></td><td>C65</td><td>PCIe01_RX-</td><td></td><td>D65</td><td>PCIe01_TX+</td></tr><tr><td>A66</td><td>PCIe09_TX+</td><td></td><td>B66</td><td>GND</td><td></td><td>C66</td><td>PCIe01_RX+</td><td></td><td>D66</td><td>GND</td></tr><tr><td>A67</td><td>GND</td><td></td><td>B67</td><td>PCIe10_RX-</td><td></td><td>C67</td><td>GND</td><td></td><td>D67</td><td>PCIe02_TX-</td></tr><tr><td>A68</td><td>PCIe10_TX-</td><td></td><td>B68</td><td>PCIe10_RX+</td><td></td><td>C68</td><td>PCIe02_RX-</td><td></td><td>D68</td><td>PCIe02_TX+</td></tr><tr><td>A69</td><td>PCIe10_TX+</td><td></td><td>B69</td><td>GND</td><td></td><td>C69</td><td>PCIe02_RX+</td><td></td><td>D69</td><td>GND</td></tr><tr><td>A70</td><td>GND</td><td></td><td>B70</td><td>PCIe11_RX-</td><td></td><td>C70</td><td>GND</td><td></td><td>D70</td><td>PCIe03_TX-</td></tr><tr><td>A71</td><td>PCIe11_TX-</td><td></td><td>B71</td><td>PCIe11_RX+</td><td></td><td>C71</td><td>PCIe03_RX-</td><td></td><td>D71</td><td>PCIe03_TX+</td></tr><tr><td>A72</td><td>PCIe11_TX+</td><td></td><td>B72</td><td>GND</td><td></td><td>C72</td><td>PCIe03_RX+</td><td></td><td>D72</td><td>GND</td></tr><tr><td>A73</td><td>GND</td><td></td><td>B73</td><td>PCIe12_RX-</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>PCIe04_TX-</td></tr><tr><td>A74</td><td>PCIe12_TX-</td><td></td><td>B74</td><td>PCIe12_RX+</td><td></td><td>C74</td><td>PCIe04_RX-</td><td></td><td>D74</td><td>PCIe04_TX+</td></tr><tr><td>A75</td><td>PCIe12_TX+</td><td></td><td>B75</td><td>GND</td><td></td><td>C75</td><td>PCIe04_RX+</td><td></td><td>D75</td><td>GND</td></tr><tr><td>A76</td><td>GND</td><td></td><td>B76</td><td>PCIe13_RX-</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>PCIe05_TX-</td></tr><tr><td>A77</td><td>PCIe13_TX-</td><td></td><td>B77</td><td>PCIe13_RX+</td><td></td><td>C77</td><td>PCIe05_RX-</td><td></td><td>D77</td><td>PCIe05_TX+</td></tr><tr><td>A78</td><td>PCIe13_TX+</td><td></td><td>B78</td><td>GND</td><td></td><td>C78</td><td>PCIe05_RX+</td><td></td><td>D78</td><td>GND</td></tr><tr><td>A79</td><td>GND</td><td></td><td>B79</td><td>PCIe14_RX-</td><td></td><td>C79</td><td>GND</td><td></td><td>D79</td><td>PCIe06_TX-</td></tr><tr><td>A80</td><td>PCIe14_TX-</td><td></td><td>B80</td><td>PCIe14_RX+</td><td></td><td>C80</td><td>PCIe06_RX-</td><td></td><td>D80</td><td>PCIe06_TX+</td></tr><tr><td>A81</td><td>PCIe14_TX+</td><td></td><td>B81</td><td>GND</td><td></td><td>C81</td><td>PCIe06_RX+</td><td></td><td>D81</td><td>GND</td></tr><tr><td>A82</td><td>GND</td><td></td><td>B82</td><td>PCIe15_RX-</td><td></td><td>C82</td><td>GND</td><td></td><td>D82</td><td>PCIe07_TX-</td></tr><tr><td>A83</td><td>PCIe15_TX-</td><td></td><td>B83</td><td>PCIe15_RX+</td><td></td><td>C83</td><td>PCIe07_RX-</td><td></td><td>D83</td><td>PCIe07_TX+</td></tr><tr><td>A84</td><td>PCIe15_TX+</td><td></td><td>B84</td><td>GND</td><td></td><td>C84</td><td>PCIe07_RX+</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GND</td><td></td><td>B85</td><td>TEST#</td><td></td><td>C85</td><td>GND</td><td></td><td>D85</td><td>NBASET0_MDIO-</td></tr><tr><td>A86</td><td>VCC_RTC</td><td></td><td>B86</td><td>RSMRST_OUT#</td><td></td><td>C86</td><td>SMB_CLK</td><td></td><td>D86</td><td>NBASET0_MDIO+</td></tr><tr><td>A87</td><td>SUS_CLK</td><td></td><td>B87</td><td>UART1_TX</td><td></td><td>C87</td><td>SMB_DAT</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>GPIO_00</td><td></td><td>B88</td><td>UART1_RX</td><td></td><td>C88</td><td>SMB_ALERT#</td><td></td><td>D88</td><td>NBASET0_MDI1-</td></tr><tr><td>A89</td><td>GPIO_01</td><td></td><td>B89</td><td>UART1_RTS#</td><td></td><td>C89</td><td>UART0_TX</td><td></td><td>D89</td><td>NBASET0_MDI1+</td></tr><tr><td>A90</td><td>GPIO_02</td><td></td><td>B90</td><td>UART1_CTS#</td><td></td><td>C90</td><td>UART0_RX</td><td></td><td>D90</td><td>GND</td></tr><tr><td>A91</td><td>GPIO_03</td><td></td><td>B91</td><td>IPMB_CLK</td><td></td><td>C91</td><td>UART0_RTS#</td><td></td><td>D91</td><td>NBASET0_MDI2-</td></tr><tr><td>A92</td><td>GPIO_04</td><td></td><td>B92</td><td>IPMB_DAT</td><td></td><td>C92</td><td>UART0_CTS#</td><td></td><td>D92</td><td>NBASET0_MDI2+</td></tr><tr><td>A93</td><td>GPIO_05</td><td></td><td>B93</td><td>GPSPI_MOSI</td><td></td><td>C93</td><td>I2C0_CLK</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>GPIO_06</td><td></td><td>B94</td><td>GPSPI_MISO</td><td></td><td>C94</td><td>I2C0_DAT</td><td></td><td>D94</td><td>NBASET0_MDI3-</td></tr><tr><td>A95</td><td>GPIO_07</td><td></td><td>B95</td><td>GPSPI_CS0#</td><td></td><td>C95</td><td>I2C0_ALERT#</td><td></td><td>D95</td><td>NBASET0_MDI3+</td></tr><tr><td>A96</td><td>GPIO_08</td><td></td><td>B96</td><td>GPSPI_CS1#</td><td></td><td>C96</td><td>I2C1_CLK</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>GPIO_09</td><td></td><td>B97</td><td>GPSPI_CS2#</td><td></td><td>C97</td><td>I2C1_DAT</td><td></td><td>D97</td><td>NBASET0_LINK_MAX#</td></tr><tr><td>A98</td><td>GPIO_10</td><td></td><td>B98</td><td>GPSPI_CS3#</td><td></td><td>C98</td><td>NBASET0_SDP</td><td></td><td>D98</td><td>NBASET0_LINK_MID#</td></tr><tr><td>A99</td><td>GPIO_11</td><td></td><td>B99</td><td>GPSPI_CLK</td><td></td><td>C99</td><td>NBASET0_CTREF</td><td></td><td>D99</td><td>NBASET0_LINK_ACT#</td></tr><tr><td>A100</td><td>TYPE0</td><td></td><td>B100</td><td>GPSPI_ALERT#</td><td></td><td>C100</td><td>TYPE1</td><td></td><td>D100</td><td>TYPE2</td></tr></table>

<table><tr><td colspan="2">Row E</td><td></td><td colspan="2">Row F</td><td></td><td colspan="2">Row G</td><td></td><td colspan="2">Row H</td></tr><tr><td>E1</td><td>RAPID_SHUTDOWN</td><td></td><td>F1</td><td>FUSA_STATUS0</td><td></td><td>G1</td><td>VCC_5V_SBY</td><td></td><td>H1</td><td>GND</td></tr><tr><td>E2</td><td>GND</td><td></td><td>F2</td><td>FUSA_STATUS1</td><td></td><td>G2</td><td>GND</td><td></td><td>H2</td><td>USB2_SSTX0-</td></tr><tr><td>E3</td><td>DDI2_SDA_AUX-</td><td></td><td>F3</td><td>FUSA_ALERT#</td><td></td><td>G3</td><td>USB2_SSRX0-</td><td></td><td>H3</td><td>USB2_SSTX0+</td></tr><tr><td>E4</td><td>DDI2_SDA_AUX+</td><td></td><td>F4</td><td>FUSA_SPI_CS#</td><td></td><td>G4</td><td>USB2_SSRX0+</td><td></td><td>H4</td><td>GND</td></tr><tr><td>E5</td><td>GND</td><td></td><td>F5</td><td>FUSA_SPI_CLK</td><td></td><td>G5</td><td>GND</td><td></td><td>H5</td><td>USB2-SSTX1-</td></tr><tr><td>E6</td><td>DDI2_PAIR0-</td><td></td><td>F6</td><td>FUSA_SPI_MISO</td><td></td><td>G6</td><td>USB2_SSRX1-</td><td></td><td>H6</td><td>USB2-SSTX1+</td></tr><tr><td>E7</td><td>DDI2_PAIR0+</td><td></td><td>F7</td><td>FUSA_SPI_MOSI</td><td></td><td>G7</td><td>USB2_SSRX1+</td><td></td><td>H7</td><td>GND</td></tr><tr><td>E8</td><td>GND</td><td></td><td>F8</td><td>FUSA_SPI_ALERT</td><td></td><td>G8</td><td>GND</td><td></td><td>H8</td><td>USB3_SSTX0-</td></tr><tr><td>E9</td><td>DDI2_PAIR1-</td><td></td><td>F9</td><td>FUSA_VOLTAGE_ERR#</td><td></td><td>G9</td><td>USB3_SSRX0-</td><td></td><td>H9</td><td>USB3_SSTX0+</td></tr><tr><td>E10</td><td>DDI2_PAIR1+</td><td></td><td>F10</td><td>PROCHOT#</td><td></td><td>G10</td><td>USB3_SSRX0+</td><td></td><td>H10</td><td>GND</td></tr><tr><td>E11</td><td>GND</td><td></td><td>F11</td><td>CATERR#</td><td></td><td>G11</td><td>GND</td><td></td><td>H11</td><td>USB3-SSTX1-</td></tr><tr><td>E12</td><td>DDI2_PAIR2-</td><td></td><td>F12</td><td>RSVD</td><td></td><td>G12</td><td>USB3_SSRX1-</td><td></td><td>H12</td><td>USB3-SSTX1+</td></tr><tr><td>E13</td><td>DDI2_PAIR2+</td><td></td><td>F13</td><td>RSVD</td><td></td><td>G13</td><td>USB3_SSRX1+</td><td></td><td>H13</td><td>GND</td></tr><tr><td>E14</td><td>GND</td><td></td><td>F14</td><td>RSVD</td><td></td><td>G14</td><td>GND</td><td></td><td>H14</td><td>USB2_AUX-</td></tr><tr><td>E15</td><td>DDI2_PAIR3-</td><td></td><td>F15</td><td>RSVD</td><td></td><td>G15</td><td>USB3_LSRX</td><td></td><td>H15</td><td>USB2_AUX+</td></tr><tr><td>E16</td><td>DDI2_PAIR3+</td><td></td><td>F16</td><td>RSVD</td><td></td><td>G16</td><td>USB3_LSTX</td><td></td><td>H16</td><td>GND</td></tr><tr><td>E17</td><td>GND</td><td></td><td>F17</td><td>RSVD</td><td></td><td>G17</td><td>USB3_LSRX</td><td></td><td>H17</td><td>USB3_AUX-</td></tr><tr><td>E18</td><td>DDI2_DDC_AUX_SEL</td><td></td><td>F18</td><td>RSVD</td><td></td><td>G18</td><td>USB3_LSTX</td><td></td><td>H18</td><td>USB3_AUX+</td></tr><tr><td>E19</td><td>DDI2_HPD</td><td></td><td>F19</td><td>GND</td><td></td><td>G19</td><td>PEG_LANE_REV#</td><td></td><td>H19</td><td>GND</td></tr><tr><td>E20</td><td>GND</td><td></td><td>F20</td><td>PCIe32_RX-</td><td></td><td>G20</td><td>GND</td><td></td><td>H20</td><td>PCIe40_TX-</td></tr><tr><td>E21</td><td>PCIe32_TX-</td><td></td><td>F21</td><td>PCIe32_RX+</td><td></td><td>G21</td><td>PCIe40_RX-</td><td></td><td>H21</td><td>PCIe40_TX+</td></tr><tr><td>E22</td><td>PCIe32_TX+</td><td></td><td>F22</td><td>GND</td><td></td><td>G22</td><td>PCIe40_RX+</td><td></td><td>H22</td><td>GND</td></tr><tr><td>E23</td><td>GND</td><td></td><td>F23</td><td>PCIe33_RX-</td><td></td><td>G23</td><td>GND</td><td></td><td>H23</td><td>PCIe41_TX-</td></tr><tr><td>E24</td><td>PCIe33_TX-</td><td></td><td>F24</td><td>PCIe33_RX+</td><td></td><td>G24</td><td>PCIe41_RX-</td><td></td><td>H24</td><td>PCIe41_TX+</td></tr><tr><td>E25</td><td>PCIe33_TX+</td><td></td><td>F25</td><td>GND</td><td></td><td>G25</td><td>PCIe41_RX+</td><td></td><td>H25</td><td>GND</td></tr><tr><td>E26</td><td>GND</td><td></td><td>F26</td><td>PCIe34_RX-</td><td></td><td>G26</td><td>GND</td><td></td><td>H26</td><td>PCIe42_TX-</td></tr><tr><td>E27</td><td>PCIe34_TX-</td><td></td><td>F27</td><td>PCIe34_RX+</td><td></td><td>G27</td><td>PCIe42_RX-</td><td></td><td>H27</td><td>PCIe42_TX+</td></tr><tr><td>E28</td><td>PCIe34_TX+</td><td></td><td>F28</td><td>GND</td><td></td><td>G28</td><td>PCIe42_RX+</td><td></td><td>H28</td><td>GND</td></tr><tr><td>E29</td><td>GND</td><td></td><td>F29</td><td>PCIe35_RX-</td><td></td><td>G29</td><td>GND</td><td></td><td>H29</td><td>PCIe43_TX-</td></tr><tr><td>E30</td><td>PCIe35_TX-</td><td></td><td>F30</td><td>PCIe35_RX+</td><td></td><td>G30</td><td>PCIe43_RX-</td><td></td><td>H30</td><td>PCIe43_TX+</td></tr><tr><td>E31</td><td>PCIe35_TX+</td><td></td><td>F31</td><td>GND</td><td></td><td>G31</td><td>PCIe43_RX+</td><td></td><td>H31</td><td>GND</td></tr><tr><td>E32</td><td>GND</td><td></td><td>F32</td><td>PCIe36_RX-</td><td></td><td>G32</td><td>GND</td><td></td><td>H32</td><td>PCIe44_TX-</td></tr><tr><td>E33</td><td>PCIe36_TX-</td><td></td><td>F33</td><td>PCIe36_RX+</td><td></td><td>G33</td><td>PCIe44_RX-</td><td></td><td>H33</td><td>PCIe44_TX+</td></tr><tr><td>E34</td><td>PCIe36_TX+</td><td></td><td>F34</td><td>GND</td><td></td><td>G34</td><td>PCIe44_RX+</td><td></td><td>H34</td><td>GND</td></tr><tr><td>E35</td><td>GND</td><td></td><td>F35</td><td>PCIe37_RX-</td><td></td><td>G35</td><td>GND</td><td></td><td>H35</td><td>PCIe45_TX-</td></tr><tr><td>E36</td><td>PCIe37_TX-</td><td></td><td>F36</td><td>PCIe37_RX+</td><td></td><td>G36</td><td>PCIe45_RX-</td><td></td><td>H36</td><td>PCIe45_TX+</td></tr><tr><td>E37</td><td>PCIe37_TX+</td><td></td><td>F37</td><td>GND</td><td></td><td>G37</td><td>PCIe45_RX+</td><td></td><td>H37</td><td>GND</td></tr><tr><td>E38</td><td>GND</td><td></td><td>F38</td><td>PCIe38_RX-</td><td></td><td>G38</td><td>GND</td><td></td><td>H38</td><td>PCIe46_TX-</td></tr><tr><td>E39</td><td>PCIe38_TX-</td><td></td><td>F39</td><td>PCIe38_RX+</td><td></td><td>G39</td><td>PCIe46_RX-</td><td></td><td>H39</td><td>PCIe46_TX+</td></tr><tr><td>E40</td><td>PCIe38_TX+</td><td></td><td>F40</td><td>GND</td><td></td><td>G40</td><td>PCIe46_RX+</td><td></td><td>H40</td><td>GND</td></tr><tr><td>E41</td><td>GND</td><td></td><td>F41</td><td>PCIe39_RX-</td><td></td><td>G41</td><td>GND</td><td></td><td>H41</td><td>PCIe47_TX-</td></tr><tr><td>E42</td><td>PCIe39_TX-</td><td></td><td>F42</td><td>PCIe39_RX+</td><td></td><td>G42</td><td>PCIe47_RX-</td><td></td><td>H42</td><td>PCIe47_TX+</td></tr><tr><td>E43</td><td>PCIe39_TX+</td><td></td><td>F43</td><td>GND</td><td></td><td>G43</td><td>PCIe47_RX+</td><td></td><td>H43</td><td>GND</td></tr><tr><td>E44</td><td>GND</td><td></td><td>F44</td><td>PCIe16_RX-</td><td></td><td>G44</td><td>GND</td><td></td><td>H44</td><td>PCIe24_TX-</td></tr><tr><td>E45</td><td>PCIe16_TX-</td><td></td><td>F45</td><td>PCIe16_RX+</td><td></td><td>G45</td><td>PCIe24_RX-</td><td></td><td>H45</td><td>PCIe24_TX+</td></tr><tr><td>E46</td><td>PCIe16_TX+</td><td></td><td>F46</td><td>GND</td><td></td><td>G46</td><td>PCIe24_RX+</td><td></td><td>H46</td><td>GND</td></tr><tr><td>E47</td><td>GND</td><td></td><td>F47</td><td>PCIe17_RX-</td><td></td><td>G47</td><td>GND</td><td></td><td>H47</td><td>PCIe25_TX-</td></tr><tr><td>E48</td><td>PCIe17_TX-</td><td></td><td>F48</td><td>PCIe17_RX+</td><td></td><td>G48</td><td>PCIe25_RX-</td><td></td><td>H48</td><td>PCIe25_TX+</td></tr><tr><td>E49</td><td>PCIe17_TX+</td><td></td><td>F49</td><td>GND</td><td></td><td>G49</td><td>PCIe25_RX+</td><td></td><td>H49</td><td>GND</td></tr><tr><td>E50</td><td>GND</td><td></td><td>F50</td><td>PCIe18_RX-</td><td></td><td>G50</td><td>GND</td><td></td><td>H50</td><td>PCIe26_TX-</td></tr><tr><td>E51</td><td>PCIe18_TX-</td><td></td><td>F51</td><td>PCIe18_RX+</td><td></td><td>G51</td><td>PCIe26_RX-</td><td></td><td>H51</td><td>PCIe26_TX+</td></tr><tr><td>E52</td><td>PCIe18_TX+</td><td></td><td>F52</td><td>GND</td><td></td><td>G52</td><td>PCIe26_RX+</td><td></td><td>H52</td><td>GND</td></tr><tr><td>E53</td><td>GND</td><td></td><td>F53</td><td>PCIe19_RX-</td><td></td><td>G53</td><td>GND</td><td></td><td>H53</td><td>PCIe27_TX-</td></tr><tr><td>E54</td><td>PCIe19_TX-</td><td></td><td>F54</td><td>PCIe19_RX+</td><td></td><td>G54</td><td>PCIe27_RX-</td><td></td><td>H54</td><td>PCIe27_TX+</td></tr><tr><td>E55</td><td>PCIe19_TX+</td><td></td><td>F55</td><td>GND</td><td></td><td>G55</td><td>PCIe27_RX+</td><td></td><td>H55</td><td>GND</td></tr><tr><td>E56</td><td>GND</td><td></td><td>F56</td><td>PCIe20_RX-</td><td></td><td>G56</td><td>GND</td><td></td><td>H56</td><td>PCIe28_TX-</td></tr><tr><td>E57</td><td>PCIe20_TX-</td><td></td><td>F57</td><td>PCIe20_RX+</td><td></td><td>G57</td><td>PCIe28_RX-</td><td></td><td>H57</td><td>PCIe28_TX+</td></tr><tr><td>E58</td><td>PCIe20_TX+</td><td></td><td>F58</td><td>GND</td><td></td><td>G58</td><td>PCIe28_RX+</td><td></td><td>H58</td><td>GND</td></tr><tr><td>E59</td><td>GND</td><td></td><td>F59</td><td>PCIe21_RX-</td><td></td><td>G59</td><td>GND</td><td></td><td>H59</td><td>PCIe29_TX-</td></tr><tr><td>E60</td><td>PCIe21_TX-</td><td></td><td>F60</td><td>PCIe21_RX+</td><td></td><td>G60</td><td>PCIe29_RX-</td><td></td><td>H60</td><td>PCIe29_TX+</td></tr><tr><td>E61</td><td>PCIe21_TX+</td><td></td><td>F61</td><td>GND</td><td></td><td>G61</td><td>PCIe29_RX+</td><td></td><td>H61</td><td>GND</td></tr><tr><td>E62</td><td>GND</td><td></td><td>F62</td><td>PCIe22_RX-</td><td></td><td>G62</td><td>GND</td><td></td><td>H62</td><td>PCIe30_TX-</td></tr><tr><td>E63</td><td>PCIe22_TX-</td><td></td><td>F63</td><td>PCIe22_RX+</td><td></td><td>G63</td><td>PCIe30_RX-</td><td></td><td>H63</td><td>PCIe30_TX+</td></tr><tr><td>E64</td><td>PCIe22_TX+</td><td></td><td>F64</td><td>GND</td><td></td><td>G64</td><td>PCIe30_RX+</td><td></td><td>H64</td><td>GND</td></tr><tr><td>E65</td><td>GND</td><td></td><td>F65</td><td>PCIe23_RX-</td><td></td><td>G65</td><td>GND</td><td></td><td>H65</td><td>PCIe31_TX-</td></tr><tr><td>E66</td><td>PCIe23_TX-</td><td></td><td>F66</td><td>PCIe23_RX+</td><td></td><td>G66</td><td>PCIe31_RX-</td><td></td><td>H66</td><td>PCIe31_TX+</td></tr><tr><td>E67</td><td>PCIe23_TX+</td><td></td><td>F67</td><td>GND</td><td></td><td>G67</td><td>PCIe31_RX+</td><td></td><td>H67</td><td>GND</td></tr><tr><td>E68</td><td>GND</td><td></td><td>F68</td><td>RSVD</td><td></td><td>G68</td><td>GND</td><td></td><td>H68</td><td>RSVD</td></tr><tr><td>E69</td><td>RSVD</td><td></td><td>F69</td><td>RSVD</td><td></td><td>G69</td><td>RSVD</td><td></td><td>H69</td><td>RSVD</td></tr><tr><td>E70</td><td>RSVD</td><td></td><td>F70</td><td>GND</td><td></td><td>G70</td><td>RSVD</td><td></td><td>H70</td><td>GND</td></tr><tr><td>E71</td><td>RSVD</td><td></td><td>F71</td><td>NBASET1_MDI0-</td><td></td><td>G71</td><td>GND</td><td></td><td>H71</td><td>CSI1_RX0-</td></tr><tr><td>E72</td><td>RSVD</td><td></td><td>F72</td><td>NBASET1_MDI0+</td><td></td><td>G72</td><td>CSI0_RX0-</td><td></td><td>H72</td><td>CSI1_RX0+</td></tr><tr><td>E73</td><td>RSVD</td><td></td><td>F73</td><td>GND</td><td></td><td>G73</td><td>CSI0_RX0+</td><td></td><td>H73</td><td>GND</td></tr><tr><td>E74</td><td>RSVD</td><td></td><td>F74</td><td>NBASET1_MDI1-</td><td></td><td>G74</td><td>GND</td><td></td><td>H74</td><td>CSI1_RX1-</td></tr><tr><td>E75</td><td>RSVD</td><td></td><td>F75</td><td>NBASET1_MDI1+</td><td></td><td>G75</td><td>CSI0_RX1-</td><td></td><td>H75</td><td>CSI1_RX1+</td></tr><tr><td>E76</td><td>RSVD</td><td></td><td>F76</td><td>GND</td><td></td><td>G76</td><td>CSI0_RX1+</td><td></td><td>H76</td><td>GND</td></tr><tr><td>E77</td><td>RSVD</td><td></td><td>F77</td><td>NBASET1_MDI2-</td><td></td><td>G77</td><td>GND</td><td></td><td>H77</td><td>CSI1_RX2-</td></tr><tr><td>E78</td><td>NBASET1_CTREF</td><td></td><td>F78</td><td>NBASET1_MDI2+</td><td></td><td>G78</td><td>CSI0_RX2-</td><td></td><td>H78</td><td>CSI1_RX2+</td></tr><tr><td>E79</td><td>NBASET1_SDP</td><td></td><td>F79</td><td>GND</td><td></td><td>G79</td><td>CSI0_RX2+</td><td></td><td>H79</td><td>GND</td></tr><tr><td>E80</td><td>NBASET1_LINK_MID#</td><td></td><td>F80</td><td>NBASET1_MDI3-</td><td></td><td>G80</td><td>GND</td><td></td><td>H80</td><td>CSI1_RX3-</td></tr><tr><td>E81</td><td>NBASET1_LINK_ACT#</td><td></td><td>F81</td><td>NBASET1_MDI3+</td><td></td><td>G81</td><td>CSI0_RX3-</td><td></td><td>H81</td><td>CSI1_RX3+</td></tr><tr><td>E82</td><td>NBASET1_LINK_MAX#</td><td></td><td>F82</td><td>GND</td><td></td><td>G82</td><td>CSI0_RX3+</td><td></td><td>H82</td><td>GND</td></tr><tr><td>E83</td><td>GND</td><td></td><td>F83</td><td>RSVD</td><td></td><td>G83</td><td>GND</td><td></td><td>H83</td><td>CSI1_CLK-</td></tr><tr><td>E84</td><td>RSVD</td><td></td><td>F84</td><td>RSVD</td><td></td><td>G84</td><td>CSI0_CLK-</td><td></td><td>H84</td><td>CSI1_CLK+</td></tr><tr><td>E85</td><td>RSVD</td><td></td><td>F85</td><td>GND</td><td></td><td>G85</td><td>CSI0_CLK+</td><td></td><td>H85</td><td>GND</td></tr><tr><td>E86</td><td>GND</td><td></td><td>F86</td><td>ETH0_TX-</td><td></td><td>G86</td><td>GND</td><td></td><td>H86</td><td>CSI1_I2C_CLK</td></tr><tr><td>E87</td><td>ETH0_RX-</td><td></td><td>F87</td><td>ETH0_TX+</td><td></td><td>G87</td><td>CSI0_I2C_CLK</td><td></td><td>H87</td><td>CSI1_I2C_DAT</td></tr><tr><td>E88</td><td>ETH0_RX+</td><td></td><td>F88</td><td>GND</td><td></td><td>G88</td><td>CSI0_I2C_DAT</td><td></td><td>H88</td><td>CSI1_MCLK</td></tr><tr><td>E89</td><td>GND</td><td></td><td>F89</td><td>ETH1_TX-</td><td></td><td>G89</td><td>CSI0_MCLK</td><td></td><td>H89</td><td>CSI1_RST#</td></tr><tr><td>E90</td><td>ETH1_RX-</td><td></td><td>F90</td><td>ETH1_TX+</td><td></td><td>G90</td><td>CSI0_RST#</td><td></td><td>H90</td><td>CSI1_ENA</td></tr><tr><td>E91</td><td>ETH1_RX+</td><td></td><td>F91</td><td>GND</td><td></td><td>G91</td><td>CSI0_ENA</td><td></td><td>H91</td><td>GND</td></tr><tr><td>E92</td><td>GND</td><td></td><td>F92</td><td>PCIe_REFCLK2-</td><td></td><td>G92</td><td>GND</td><td></td><td>H92</td><td>PCIe_REFCLKIN0-</td></tr><tr><td>E93</td><td>PCIe_REFCLK1-</td><td></td><td>F93</td><td>PCIe_REFCLK2+</td><td></td><td>G93</td><td>RSVD</td><td></td><td>H93</td><td>PCIe_REFCLKIN0+</td></tr><tr><td>E94</td><td>PCIe_REFCLK1+</td><td></td><td>F94</td><td>GND</td><td></td><td>G94</td><td>RSVD</td><td></td><td>H94</td><td>GND</td></tr><tr><td>E95</td><td>GND</td><td></td><td>F95</td><td>RSVD</td><td></td><td>G95</td><td>GND</td><td></td><td>H95</td><td>PCIe_REFCLKIN1-</td></tr><tr><td>E96</td><td>PCIe_CLKREQ1#</td><td></td><td>F96</td><td>ETH0_1_PRSNT#</td><td></td><td>G96</td><td>ETH0_1_I2C_CLK</td><td></td><td>H96</td><td>PCIe_REFCLKIN1+</td></tr><tr><td>E97</td><td>PCIe_CLKREQ2#</td><td></td><td>F97</td><td>ETH0_1_PHY_RST#</td><td></td><td>G97</td><td>ETH0_1_I2C_DAT</td><td></td><td>H97</td><td>GND</td></tr><tr><td>E98</td><td>PCIe_CLKREQ_OUT0#</td><td></td><td>F98</td><td>ETH0_SDP</td><td></td><td>G98</td><td>ETH0_1_PHY_INT#</td><td></td><td>H98</td><td>ETH0_1_MDIO_CLK</td></tr><tr><td>E99</td><td>PCIe_CLKREQ_OUT1#</td><td></td><td>F99</td><td>ETH1_SDP</td><td></td><td>G99</td><td>ETH0_1_INT#</td><td></td><td>H99</td><td>ETH0_1_MDIO_DAT</td></tr><tr><td>E100</td><td>PCIe_PERST_IN0#</td><td></td><td>F100</td><td>PCIe_PERST_IN1#</td><td></td><td>G100</td><td>PCIe_WAKE_OUT0#</td><td></td><td>H100</td><td>PCIe_WAKE_OUT1#</td></tr></table>

# 5.5. PCIe x16 Slot

The example below illustrates the interface or usage of each connectors/jumper.

# PCle 16-31: Group 1 Lanes 16:31 assigned PClex16 Slot

slikscreen

interface from module or IC on carrier

more information

PCIe 16-31: Group 1 Lanes 16:31 assigned PCIex16 slot, supporting up to Gen5 speeds, depending on the module specifications.

![Front view of a computer RAM module with memory slots and indicator lights (no text or symbols visible)](.com-hpc-client-base-manual-50m-77108-1000-01/34ad25a31e79eed86fcb59f4ab6b754a675db652c802f304f129d3696bde80f8.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+ 12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+ 12V</td><td>A2</td><td>+ 12V</td></tr><tr><td>B3</td><td>+ 12V</td><td>A3</td><td>+ 12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+ 3.3V</td></tr><tr><td>B10</td><td>+ 3.3VAUX</td><td>A10</td><td>+ 3.3V</td></tr><tr><td>B11</td><td>WAKE#</td><td>A11</td><td>PERST#</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td>B33</td><td>PETp4</td><td>A33</td><td>RSVD</td></tr><tr><td>B34</td><td>PETn4</td><td>A34</td><td>GND</td></tr><tr><td>B35</td><td>GND</td><td>A35</td><td>PERp4</td></tr><tr><td>B36</td><td>GND</td><td>A36</td><td>PERn4</td></tr><tr><td>B37</td><td>PETp5</td><td>A37</td><td>GND</td></tr><tr><td>B38</td><td>PETn5</td><td>A38</td><td>GND</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B43</td><td>GND</td><td>A43</td><td>PERp6</td></tr><tr><td>B44</td><td>GND</td><td>A44</td><td>PERn6</td></tr><tr><td>B45</td><td>PETp7</td><td>A45</td><td>GND</td></tr><tr><td>B46</td><td>PETn7</td><td>A46</td><td>GND</td></tr><tr><td>B47</td><td>GND</td><td>A47</td><td>PERp7</td></tr><tr><td>B48</td><td>PRSNT</td><td>A48</td><td>PERn7</td></tr><tr><td>B49</td><td>GND</td><td>A49</td><td>GND</td></tr><tr><td>B50</td><td>PETp8</td><td>A50</td><td>RSVD</td></tr><tr><td>B51</td><td>PETn8</td><td>A51</td><td>GND</td></tr><tr><td>B52</td><td>GND</td><td>A52</td><td>PERp8</td></tr><tr><td>B53</td><td>GND</td><td>A53</td><td>PERn8</td></tr><tr><td>B54</td><td>PETp9</td><td>A54</td><td>GND</td></tr><tr><td>B55</td><td>PETn9</td><td>A55</td><td>GND</td></tr><tr><td>B56</td><td>GND</td><td>A56</td><td>PERp9</td></tr><tr><td>B57</td><td>GND</td><td>A57</td><td>PERn9</td></tr><tr><td>B58</td><td>PETp10</td><td>A58</td><td>GND</td></tr><tr><td>B59</td><td>PETn10</td><td>A59</td><td>GND</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B64</td><td>GND</td><td>A64</td><td>PERp11</td></tr><tr><td>B65</td><td>GND</td><td>A65</td><td>PERn11</td></tr><tr><td>B66</td><td>PETp12</td><td>A66</td><td>GND</td></tr><tr><td>B67</td><td>PETn12</td><td>A67</td><td>GND</td></tr><tr><td>B68</td><td>GND</td><td>A68</td><td>PERp12</td></tr><tr><td>B69</td><td>GND</td><td>A69</td><td>PERn12</td></tr><tr><td>B70</td><td>PETp13</td><td>A70</td><td>GND</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B39</td><td>GND</td><td>A39</td><td>PERp5</td></tr><tr><td>B40</td><td>GND</td><td>A40</td><td>PERn5</td></tr><tr><td>B41</td><td>PETp6</td><td>A41</td><td>GND</td></tr><tr><td>B42</td><td>PETn6</td><td>A42</td><td>GND</td></tr><tr><td>B71</td><td>PETn13</td><td>A71</td><td>GND</td></tr><tr><td>B72</td><td>GND</td><td>A72</td><td>PERp13</td></tr><tr><td>B73</td><td>GND</td><td>A73</td><td>PERn13</td></tr><tr><td>B74</td><td>PETp14</td><td>A74</td><td>GND</td></tr><tr><td>B75</td><td>PETn14</td><td>A75</td><td>GND</td></tr><tr><td>B76</td><td>GND</td><td>A76</td><td>PERp14</td></tr><tr><td>B77</td><td>GND</td><td>A77</td><td>PERn14</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B60</td><td>GND</td><td>A60</td><td>PERp10</td></tr><tr><td>B61</td><td>GND</td><td>A61</td><td>PERn10</td></tr><tr><td>B62</td><td>PETp11</td><td>A62</td><td>GND</td></tr><tr><td>B63</td><td>PETn11</td><td>A63</td><td>GND</td></tr><tr><td>B78</td><td>PETp15</td><td>A78</td><td>GND</td></tr><tr><td>B79</td><td>PETn15</td><td>A79</td><td>GND</td></tr><tr><td>B80</td><td>GND</td><td>A80</td><td>PERp15</td></tr><tr><td>B81</td><td>PRSNT</td><td>A81</td><td>PERn15</td></tr><tr><td>B82</td><td>RSVD</td><td>A82</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.6. PCIe x4 Slot

PCIE0-3: Group 0 Low Lanes 0:3 assigned PCIex4 slot

PCIE12-15: Group 0 High Lanes 12:15 assigned PCIex4 slot

Open-ended slot

![This is a top-down illustration of a split keyboard featuring a grey chassis and black keycaps. The keys are arranged in two distinct rectangular clusters separated by a vertical gap in the center. Each cluster contains five rows of keys. Small circular details are visible along the bottom edge of the frame, with the second-to-last circle on the right appearing greenish. There is a small rectangular protrusion on the far left edge. No text is visible on the keyboard.](.com-hpc-client-base-manual-50m-77108-1000-01/8812f0dea2b71b7dddf6d5c568970620bf0ba8b3c0f7379c17e9d147a0d05585.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.7. PCIe x1 Slot

PCIE5: Group 0 Low Lanes 5 assigned PCIex1 slot

PCIE6: Group 0 Low Lanes 6 assigned PCIex1 slot

PCIE7: Group 0 Low Lanes 7 assigned PCIex1 slot

Open-ended slot (to be phased in later)

![The image displays a black-and-white schematic line drawing of a rectangular electronic device, resembling a server rack or network appliance. It features rows of vertical slats running along the top and bottom edges. In the center, there are two horizontal rectangular panels; the left panel is significantly wider than the right panel. On the far left edge, a small vertical rectangle suggests a handle or latch, while the far right edge features a cluster of small circles, likely representing indicator lights. There is no text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/57285230bb571202ac370d4021af82ab8115f0b4a2c7b586791fb5986b9d67e4.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.8. M.2 M-KEY

M2\_M: Group 0 High Lanes 8-11 assigned M.2 slot Up to 22110 M.2 dimension

![The image displays a vertical label with two distinct sections. On the left is a black vertical bar featuring the white text 'M.2' oriented vertically, reading from bottom to top. To its right is a white vertical bar containing a black vertical barcode pattern.](.com-hpc-client-base-manual-50m-77108-1000-01/91815e501552b87bf7c6917183e9538c5f86a4d3405559623a9a8908bbd2e929.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CONFIG</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>+3.3V</td></tr><tr><td>5</td><td>PERn3</td><td>6</td><td>N.C</td></tr><tr><td>7</td><td>PERp3</td><td>8</td><td>N.C</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>DAS/DSS#</td></tr><tr><td>11</td><td>PETn3</td><td>12</td><td>+3.3V</td></tr><tr><td>13</td><td>PETp3</td><td>14</td><td>+3.3V</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>+3.3V</td></tr><tr><td>17</td><td>PERn2</td><td>18</td><td>+3.3V</td></tr><tr><td>19</td><td>PERp2</td><td>20</td><td>N.C</td></tr><tr><td>21</td><td>CONFIG</td><td>22</td><td>N.C</td></tr><tr><td>23</td><td>PETn2</td><td>24</td><td>N.C</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>25</td><td>PETp2</td><td>26</td><td>N.C</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>N.C</td></tr><tr><td>29</td><td>PERn1</td><td>30</td><td>N.C</td></tr><tr><td>31</td><td>PERp1</td><td>32</td><td>N.C</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>N.C</td></tr><tr><td>35</td><td>PETn1</td><td>36</td><td>N.C</td></tr><tr><td>37</td><td>PETp1</td><td>38</td><td>DEVSLP</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>N.C</td></tr><tr><td>41</td><td>PERn0</td><td>42</td><td>N.C</td></tr><tr><td>43</td><td>PERp0</td><td>44</td><td>N.C</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>N.C</td></tr><tr><td>47</td><td>PETn0</td><td>48</td><td>N.C</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>49</td><td>PETp0</td><td>50</td><td>PETST#</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>CLKREQ#</td></tr><tr><td>53</td><td>REFCLKN</td><td>54</td><td>PEWAKE#</td></tr><tr><td>55</td><td>REFCLKP</td><td>56</td><td>N.C</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>N.C</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td>67</td><td>N.C</td><td>68</td><td>SUSCLK</td></tr><tr><td>69</td><td>CONFIG</td><td>70</td><td>+3.3V</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>+3.3V</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>+3.3V</td></tr><tr><td>75</td><td>CONFIG</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.9. M.2 E-KEY

M2\_E: PCIe Group 0, Low Lane 4, and USB2 port 6 assigned Up to 2230 M.2 dimension

![The image displays a vertical graphic resembling a stylized QR code. On the left side, a solid black vertical bar runs the length of the image. Centered within this bar is the white text 'M.2', oriented vertically with the 'M' at the top, a dot in the middle, and the '2' at the bottom. To the right of the black bar is a grid of black and white squares representing the QR code data, with two visible square-in-square finder patterns on the far right side.](.com-hpc-client-base-manual-50m-77108-1000-01/b4d59d75a02eb3c0e8739e2a5628145d3461127c3b21a74e1217e81e279f45a8.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>USB_D+</td><td>4</td><td>+3.3V</td></tr><tr><td>5</td><td>USB_D-</td><td>6</td><td>LED_1#</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>N.C</td></tr><tr><td>9</td><td>N.C</td><td>10</td><td>N.C</td></tr><tr><td>11</td><td>N.C</td><td>12</td><td>N.C</td></tr><tr><td>13</td><td>N.C</td><td>14</td><td>N.C</td></tr><tr><td>15</td><td>N.C</td><td>16</td><td>N.C</td></tr><tr><td>17</td><td>N.C</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>N.C</td><td>20</td><td>N.C</td></tr><tr><td>21</td><td>N.C</td><td>22</td><td>N.C</td></tr><tr><td>23</td><td>N.C</td><td></td><td></td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>32</td><td>N.C</td><td>33</td><td>GND</td></tr><tr><td>34</td><td>N.C</td><td>35</td><td>PETp0</td></tr><tr><td>36</td><td>N.C</td><td>37</td><td>PETn0</td></tr><tr><td>38</td><td>N.C</td><td>39</td><td>GND</td></tr><tr><td>40</td><td>N.C</td><td>41</td><td>PERp0</td></tr><tr><td>42</td><td>N.C</td><td>43</td><td>PERn0</td></tr><tr><td>44</td><td>N.C</td><td>45</td><td>GND</td></tr><tr><td>46</td><td>N.C</td><td>47</td><td>REFCLKp0</td></tr><tr><td>48</td><td>N.C</td><td>49</td><td>REFCLKn0</td></tr><tr><td>50</td><td>SUSCLK</td><td>51</td><td>GND</td></tr><tr><td>52</td><td>PERST0#</td><td>53</td><td>CLKREQ0#</td></tr><tr><td>54</td><td>W_DISABLE2#</td><td>55</td><td>PWAKE0#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>56</td><td>W_DISABLE1#</td><td>57</td><td>GND</td></tr><tr><td>58</td><td>I2C_DATA</td><td>59</td><td>N.C</td></tr><tr><td>60</td><td>I2C_CLK</td><td>61</td><td>N.C</td></tr><tr><td>62</td><td>ALERT#</td><td>63</td><td>GND</td></tr><tr><td>64</td><td>N.C</td><td>65</td><td>N.C</td></tr><tr><td>66</td><td>N.C</td><td>67</td><td>N.C</td></tr><tr><td>68</td><td>N.C</td><td>69</td><td>GND</td></tr><tr><td>70</td><td>N.C</td><td>71</td><td>N.C</td></tr><tr><td>72</td><td>+3.3V</td><td>73</td><td>N.C</td></tr><tr><td>74</td><td>+3.3V</td><td>75</td><td>GND</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.10. DisplayPort / HDMI

HDMI/DP Combo connector at Rear I/O

• HDMI\_DDI0: DDI0 channel assigned
• DP\_DDI1: DDI1 channel assigned (DP++ feature depends on the module specifications)

Vertical DP connector at Rear I/O

• DP\_DDI2: DDI2 channel assigned

# 5.11. eDP / DSI

eDP/DSI: 4 lanes eDP/DSI signal assigned

40-pin connectors

![This image displays a simple, cartoon-style illustration of a wooden fence section. It features three horizontal yellow rails stacked vertically. These rails are supported by vertical posts positioned at the far left, center, and far right. The entire structure is outlined in black, with the horizontal rails and vertical posts colored yellow and shaded with orange on their ends. There is no text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/966607370bcde0d1f728468febb7b043f16f84554701c74de681535a318b0412.jpg)

eDP or DSI depends on the module specifications

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>N.C</td><td>2</td><td>+12V</td></tr><tr><td>3</td><td>+12V</td><td>4</td><td>+12V</td></tr><tr><td>5</td><td>+12V</td><td>6</td><td>N.C</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>BKL_CTRL</td></tr><tr><td>9</td><td>BKL_ENABLE</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>HPD</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>N.C</td><td>20</td><td>+3.3V</td></tr><tr><td>21</td><td>+3.3V</td><td>22</td><td>+3.3V</td></tr><tr><td>23</td><td>+3.3V</td><td>24</td><td>GND</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>25</td><td>AUX_N</td><td>26</td><td>AUX_P</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>eDP_LANE0_P</td></tr><tr><td>29</td><td>eDP_LANE0_N</td><td>30</td><td>GND</td></tr><tr><td>31</td><td>eDP_LANE1_P</td><td>32</td><td>eDP_LANE1_N</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>eDP_LANE2_P</td></tr><tr><td>35</td><td>eDP_LANE2_N</td><td>36</td><td>GND</td></tr><tr><td>37</td><td>eDP_LANE3_P</td><td>38</td><td>eDP_LANE3_N</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>N.C</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

![The image displays a simple icon resembling a document or file. It features a thick red outline of a rectangular piece of paper with the top-right corner folded down (a 'dog-ear'). Inside the white interior, there are two horizontal red lines centered vertically, resembling text lines.](.com-hpc-client-base-manual-50m-77108-1000-01/864cfd8a9d5f68bde431747cf96f2ee41aaebceaac92796c4f694a04bdbd8708.jpg)

Note: Pins 2, 3, 4, and 5 supply 12V for backlight power.

# PANEL\_PWR: power for eDP/DSI panel

6-pin headers

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>+3.3V</td><td>4</td><td>+3.3V</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr></table>

![The image displays a vertical column of four horizontal ovals stacked on top of each other. Inside each oval are two small squares positioned side-by-side. In the top three ovals, both squares are white with black outlines. In the bottom oval, the left square is white with a black outline, while the right square is solid black.](.com-hpc-client-base-manual-50m-77108-1000-01/3b34365c218e1223a3ca087e017a576781cdd79c6bd2fe5107e4765882cfb3d7.jpg)

JP28: panel power setting

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>3.3V (default)</td></tr><tr><td>2-3</td><td>5V</td></tr></table>

JP29: backlight power setting

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>12V (default)</td></tr><tr><td>2-3</td><td>5V</td></tr></table>

# 5.12. Audio HDA

Audio: HDA/I2S assigned at Rear I/O

3-in-1 audio jack

HDA/I2S depends on the audio codec and module specifications

Audio function is not enabled in this version

<table><tr><td>Color</td><td>Signal</td></tr><tr><td>BLUE</td><td>LINE-IN</td></tr><tr><td>GREEN</td><td>LINE-OUT</td></tr><tr><td>PINK</td><td>MIC-IN</td></tr></table>

![A vertical grey rectangular panel features three circular lights stacked vertically. The top light is blue, the middle light is green, and the bottom light is pink, each containing a black circle in its center.](.com-hpc-client-base-manual-50m-77108-1000-01/337d2a3262877887ff048ab58d8ee43d038976aacfad1bd0ea125e3ac70f86e5.jpg)

# 5.13. Audio SNDW

SNDW0: SNDW0 signal assigned

SNDW1: SNDW1 signal assigned

Audio function is not enabled in this version

![The image is a black-and-white line drawing featuring a horizontal rectangular box. Inside the box, there are five geometric shapes arranged in a row. On the far left is a small square, followed by four circles of uniform size spaced evenly to its right.](.com-hpc-client-base-manual-50m-77108-1000-01/6dbeafc61fdcaf1aebcdd9edb6c5a312f9a3bd1c36457d998ff3ee411a224e79.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>+1.8V</td><td>4</td><td>SNDW_CLK</td></tr><tr><td>5</td><td>SNDW_DATA</td><td>6</td><td>GND</td></tr></table>

# 5.14. Ethernet NBASE-T

2-in-1 Ethernet Connector at Rear I/O

ETH\_0: NBASET\_0 assigned (lower one)

ETH\_1: NBASET\_1 assigned (upper one)

Up to 10GbE, depending on the module specifications

![The image displays a schematic diagram of a dual-port faceplate or wall plate. It features two large black connector cutouts arranged vertically, separated by a thin horizontal grey line. In the upper section, a lime green square is positioned at the top left and a light blue square is at the top right. In the lower section, the layout is mirrored, with a light blue square at the bottom left and a lime green square at the bottom right.](.com-hpc-client-base-manual-50m-77108-1000-01/bd1b958c8a15557d22b9ea6299295de7ee4697207ea9e72e689973f31f462dc4.jpg)

<table><tr><td>LED Function</td><td>LED Color</td><td>LED State</td><td>Description</td></tr><tr><td rowspan="2">Speed</td><td rowspan="2">Green/Yellow</td><td>Green</td><td>A speed lower than what the maximum speed that the Ethernet controller of module is capable of.</td></tr><tr><td>Yellow</td><td>The maximum speed that the Ethernet controller of Module is capable of</td></tr><tr><td rowspan="3">Status &amp; Activity</td><td rowspan="3">Yellow</td><td>Off</td><td>No link</td></tr><tr><td>Steady On</td><td>Link established, no activity detected</td></tr><tr><td>Blinking</td><td>Link established, activity detected</td></tr></table>

# 5.15. CSI Camera Serial Interface

CSI0: TBD-pin connector: CSI\_0 assigned

CSI1: TBD-pin connector: CSI\_1 assigned

CSI function is not enabled in this version

![The image displays a simple, schematic line drawing of a bowl or dish. It features a long, horizontal grey rectangle at the top, which sits above a white, trapezoidal shape outlined in black that tapers downward. A thin black horizontal line runs along the very bottom edge of the drawing.](.com-hpc-client-base-manual-50m-77108-1000-01/4bfea6e38fa739cfd21c9f636843ac8f9df90e92a70efc2551e2da4bc719fb0c.jpg)

# 5.16. USB

USB Type-A / Type-C Combo connector at Rear I/O

• USBA\_HUB: 1x USB3.x/2.0 from USB Hub assigned, Type-A connector, up to 10Gbit/s
• USBC\_USB0: USB\_0 assigned, Type-C connector, USB4 capable

USB\_0 consists of USB4/3.x SSTX/RX pairs from port 0, USB2.0 D+/D- from port 0 and sidebands

USB4 at Type-C depends on module specification. It is implemented by USB\_0 from module and PD/Re-timer on carrier board

![This image displays a flat, digital icon of a piece of office equipment, likely a printer or fax machine. It features two main sections: a top panel with a dark grey border containing a bright blue horizontal bar and three small white buttons below it, and a lower panel with rounded corners containing five white, pill-shaped slots arranged horizontally.](.com-hpc-client-base-manual-50m-77108-1000-01/c68daab28ab48be5a4a29c2f4bf0d235e7591cfaa81e96bb6e1ace8d4709b16a.jpg)

USB Type-A / Type-C Combo connector at Rear I/O

• USBA\_HUB: 1x USB3.x/2.0 from USB Hub assigned, Type-A connector, up to 10Gbit/s
• USBC\_USB1: USB\_1 assigned, Type-C connector, USB4 capable

USB\_1 consists of USB4/3.x SSTX/RX pairs from port 1, USB2.0 D+/D- from port 1 and sidebands

USB4 at Type-C depends on module specification. It is implemented by USB\_1 from module and PD/Re-timer on carrier board

![A low-resolution pixelated icon depicting a grey office machine, likely a fax machine. The top section features a light grey screen with a bright blue horizontal bar in the center and three small, dark grey buttons below it. The bottom section shows a paper tray or output slot with a dark grey border containing three light blue, pill-shaped rectangles.](.com-hpc-client-base-manual-50m-77108-1000-01/049eb129c039526c0437fad3736d534ed8c9210617b16354ee148f6991d82422.jpg)

USB Type-A 2-in-1 connector at Rear I/O

• USB\_4: USB\_4 assigned, Type-A connector, up to USB2.0 speed
• USB\_5: USB\_5 assigned, Type-A connector, up to USB2.0 speed

![The image is a vertical graphic resembling a filing cabinet or server rack. It features a light grey rectangular frame set against a dark grey background. Inside the frame are two identical horizontal sections stacked vertically. Each section contains a black horizontal bar with a white top edge and three small, light blue rectangles positioned below it. There is no text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/883527bb7982d3855041c5c5181ceb641bb7ad19059520f5213d4401f44fc8de.jpg)

F\_2XUSB\_3.2: 2x USB3.x/2.0 from USB Hub assigned, up to 10Gbit/s

Front panel usage, 19-pin, 2.54mm pitch

This function is not enabled in this version

![The image displays a vertical black bar on the far left. To the right of the bar are two columns of white dots arranged vertically. Above the left column is the text 'L.' and above the right column is the text 'R.'. Each column contains twelve white dots.](.com-hpc-client-base-manual-50m-77108-1000-01/f68bff04d40c23b936226eafb7075f7e3460fce72b33b5c6bd08227d1b4265d0.jpg)

F\_2XUSB\_2.0: 2x USB2.0 from USB Hub assigned

Front panel usage, 9-pin, 2.54 mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+5V</td></tr><tr><td>3</td><td>HUB_USB2_N</td><td>4</td><td>HUB_USB1_N</td></tr><tr><td>5</td><td>HUB_USB2_P</td><td>6</td><td>HUB_USB1_P</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

![The image displays five black digits arranged horizontally in a row against a white background. The digits are stylized, resembling the number 8.\n\nThe text is: **88888**](.com-hpc-client-base-manual-50m-77108-1000-01/b7e66ee6ff3b83b802e52028b29156e61d22dd8169d5d24e090d51acd9d16d71.jpg)

F\_USBE\_USB2: USB\_2 assigned, Type-E connector, up to 10Gbit/s

Front panel usage

![The image displays a schematic diagram of an electronic component, resembling an integrated circuit or microcontroller. It features a large, dark grey central rectangle. Above and below this central block are two rows of eight small, white rectangular pins or contacts each. Flanking the central block on the far left and right are black, connector-like structures. The entire component is enclosed within a thin black rectangular border against a white background.](.com-hpc-client-base-manual-50m-77108-1000-01/99c45d2cddc6ffe3fddb77b6b56fbb9a7525b3655a4a54dd6d51a6553586beb4.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>VBUS</td><td>2</td><td>USB2_TX0_P</td></tr><tr><td>3</td><td>USB2_TX0_N</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB2_RX0_P</td><td>6</td><td>USB2_RX0_N</td></tr><tr><td>7</td><td>VBUS</td><td>8</td><td>PD_CC1</td></tr><tr><td>9</td><td>N.C</td><td>10</td><td>N.C</td></tr><tr><td>11</td><td>VBUS</td><td>12</td><td>USB2_TX1_P</td></tr><tr><td>13</td><td>USB2_TX1_N</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>USB2_RX1_P</td><td>16</td><td>USB2_RX1_N</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>USB2_USB2.0_N</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>19</td><td>USB2_USB2.0_P</td><td>20</td><td>PD_CC2</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.17. GPIO

GPIO: GPIO 0-11 signal assigned

14-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>3.3V</td><td>2</td><td>GPIO_06</td></tr><tr><td>3</td><td>GPIO_00</td><td>2</td><td>GPIO_07</td></tr><tr><td>5</td><td>GPIO_01</td><td>4</td><td>GPIO_08</td></tr><tr><td>7</td><td>GPIO_02</td><td>6</td><td>GPIO_09</td></tr><tr><td>9</td><td>GPIO_03</td><td>8</td><td>GPIO_10</td></tr><tr><td>11</td><td>GPIO_04</td><td>10</td><td>GPIO_11</td></tr><tr><td>13</td><td>GPIO_05</td><td>12</td><td>GND</td></tr></table>

![The image displays a horizontal row of eight black, rounded rectangular shapes against a white background, with a black bar running along the very top edge. Inside each black shape are white elements arranged in a vertical column. The first five shapes from the left and the last two shapes each contain three small white dots stacked vertically. The sixth shape from the left contains a top white dot, a middle white square, and a bottom white dot.](.com-hpc-client-base-manual-50m-77108-1000-01/efe7b83b6f35c4102531ae0de7922ea98056807ea72901ceea48fdb756ece8d6.jpg)

# 5.18. I2C

I2C0: I2C0 bus assigned, 3.3V, 4-pin, 2.54mm pitch

I2C1: I2C1 bus assigned, 1.8V, 4-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V (for I2C0) +1.8B (for I2C1)</td><td>2</td><td>I2C_DATA</td></tr><tr><td>3</td><td>I2C_CLK</td><td>4</td><td>GND</td></tr></table>

![The image shows a black horizontal rectangle with rounded corners (a pill shape) containing four small white dots arranged in a straight, evenly spaced horizontal line.](.com-hpc-client-base-manual-50m-77108-1000-01/44ed0744f512ca8af3f2cb74846e13213ef1fe5fe94b3ce83aacde17dcffc35a.jpg)

# 5.19. UART / COM

COM1\_SER0: UART0 signal assigned, 2.0mm pitch

COM2\_SER1: UART1 signal assigned, 2.0mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>N.C</td><td>2</td><td>N.C</td></tr><tr><td>3</td><td>UART_RX</td><td>4</td><td>UART_RTS</td></tr><tr><td>5</td><td>UART_TX</td><td>6</td><td>UART_CTS</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>N.C</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>N.C</td></tr></table>

![The image displays a black rectangle containing six white dots arranged in two rows of three. The rectangle is framed by a thin white border against a white background. A small white horizontal line is visible at the top center, and a faint vertical white line runs along the left side of the black rectangle.](.com-hpc-client-base-manual-50m-77108-1000-01/667f8ddaa29488127789285fb28da4a1bdfa712357fa6b6823b6cc13e6c32dab.jpg)

COM3: UART from Super I/O signal assigned, 2.0mm pitch

COM4: UART from Super I/O signal assigned, 2.0mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DCD</td><td>2</td><td>DSR</td></tr><tr><td>3</td><td>RX</td><td>4</td><td>RTS</td></tr><tr><td>5</td><td>TX</td><td>6</td><td>CTS</td></tr><tr><td>7</td><td>DTR</td><td>8</td><td>RI</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>N.C</td></tr></table>

![The image displays a black rectangular box with a thin white border. Inside the black area, there are twelve white dots arranged in three horizontal rows of four dots each. Above the top row of dots, centered horizontally, is a small, solid white horizontal rectangle.](.com-hpc-client-base-manual-50m-77108-1000-01/1ce0ff5efd3b79cf1e9dacffa5f0c51514a156a67ebf349205a5630dabf0874d.jpg)

JP42/JP41: selection of RS232/RS485/RS422 mode for COM3

<table><tr><td>Mode</td><td>JP42</td><td>JP41</td></tr><tr><td>RS232 (default)</td><td>2-3</td><td>1-2</td></tr><tr><td>RS485</td><td>1-2</td><td>2-3</td></tr><tr><td>RS422</td><td>1-2</td><td>1-2</td></tr></table>

![The image features a small, horizontal rectangular object with a rounded left edge, enclosed within a black square border. The object is divided vertically into two sections. The left section is light gray and contains a single small black square in its center. The right section is black and features two small white dots arranged horizontally. A thin vertical black line separates the two sections.](.com-hpc-client-base-manual-50m-77108-1000-01/f5193b4493b612ea77cd8c5fc767b237425a34694fc6239d09312b0f05996bc0.jpg)

# 5.20. eSPI Debug Connector

ESPI: for eSPI debugging connection purpose

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>eSPI_CLK</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>eSPI_CS0</td><td>4</td><td>N.C</td></tr><tr><td>5</td><td>CB_RST</td><td>6</td><td>+5V</td></tr><tr><td>7</td><td>eSPI_IO_3</td><td>8</td><td>eSPI_IO_2</td></tr><tr><td>9</td><td>+ 3.3VSB</td><td>10</td><td>eSPI_IO_1</td></tr><tr><td>11</td><td>eSPI_IO_0</td><td>12</td><td>eSPI_ALERT0#</td></tr><tr><td>13</td><td>SMB_CK</td><td>14</td><td>SMB_DAT</td></tr><tr><td>15</td><td>+1.8VSB</td><td>16</td><td>eSPI_CS1</td></tr><tr><td>17</td><td>eSPI_RST#</td><td>18</td><td>N.C</td></tr><tr><td>19</td><td>+5V</td><td>20</td><td>eSPI_ALEART1#</td></tr></table>

![The image displays a vertical column of ten light gray, rounded rectangular shapes resembling checkboxes or buttons. Each shape contains two small squares side-by-side. The top nine shapes feature two empty squares with black outlines, while the bottommost shape features a solid black square on the left and an empty square on the right.](.com-hpc-client-base-manual-50m-77108-1000-01/81252e6c930215e7a7066e90c959e683a0c4e019036d52d2591af64b1e5587cf.jpg)

# 5.21. SMB

SMBUS: SMBus assigned, 4-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>SMB_DATA</td></tr><tr><td>3</td><td>SMB_CLK</td><td>4</td><td>GND</td></tr></table>

![The image displays a black, horizontal pill-shaped rectangle with rounded ends. Inside this black shape, four small white dots are arranged in a single horizontal row. The background surrounding the shape is white.](.com-hpc-client-base-manual-50m-77108-1000-01/74ae53378b37dec5f2f77540a34bca980764ff38a72e7bf66eb46eac5d9a24e3.jpg)

# 5.22. FAN Connector

MODULE\_FAN: FAN control signals from module assigned, 4-pin

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![The image displays a simple black-and-white line drawing of a vertical rectangular object, resembling a drawer front or cabinet panel. On the left side, there is a narrow vertical strip. To the right of this strip is a larger rectangular section containing a vertical column of four small squares.](.com-hpc-client-base-manual-50m-77108-1000-01/3c007acd5b62e29ad0d333ed01ff405f83492fdca0e4dd8b3aede74faa06ac39.jpg)

SYS\_FAN1: FAN control signals from Super I/O assigned, 4-pin

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN0</td></tr><tr><td>3</td><td>SENSE_FAN0</td></tr><tr><td>4</td><td>PWMOUT_FAN0</td></tr></table>

![The image displays a simple black-and-white line drawing. On the left side, there is a vertical rectangle resembling a door, which contains a smaller horizontal rectangle near the top, suggesting a handle. To the right of this door-like shape is a larger vertical rectangle representing a panel or wall. Inside the right portion of this larger rectangle, aligned vertically near the right edge, is a column of four small squares. The topmost square is filled in with solid black, while the three squares beneath it are empty white outlines.](.com-hpc-client-base-manual-50m-77108-1000-01/5f7214897c6d7afdcfe940305077e65aa8cd9900ad0d302ddd3dad14ef825a86.jpg)

SYS\_FAN2: FAN control signals from Super I/O assigned, 4-pin

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN1</td></tr><tr><td>3</td><td>SENSE_FAN1</td></tr><tr><td>4</td><td>PWMOUT_FAN1</td></tr></table>

![The image is a black-and-white line drawing of a vertical rectangular structure. On the left side, there is a narrow vertical column adjacent to a wider column containing a single horizontal rectangle. To the right of these sections is a larger area containing four small squares arranged in a vertical column. There is no text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/5a7320f5770b06cfeedd35ad1b7e4902eac1163f0e323bffa715f82e01e17f1d.jpg)

# 5.23. Carrier BIOS

A SPI BIOS Socket on carrier board

• Allow boot-up from the carrier with proper jumper settings.

BSEL1/BSEL2/BSEL3: jumpers for module boot-up selection

<table><tr><td>BESL2</td><td>BSEL1</td><td>BSEL0</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>1-2</td><td>1-2</td><td>Module SPI0/SPI1 (default)</td></tr><tr><td>1-2</td><td>1-2</td><td>2-3</td><td>Carrier SPI0/Module SPI1</td></tr><tr><td>1-2</td><td>2-3</td><td>1-2</td><td>Module SPI0/Carrier SPI1</td></tr></table>

![The image displays a black-and-white graphic of a stylized electronic component, resembling a microchip or processor. The central element is a large, black, vertically oriented shape with rounded corners and vertical indentations. Two thin white lines run vertically through the center of this black shape, branching slightly near the bottom. Flanking the central shape on both the left and right sides are rectangular columns filled with a grid of small, white square-like shapes against a black background, representing pins or contact points. There is no text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/657d08b41ce1e915e82f45a2367afa2adcb76f7e27483f48c55335fe2f902be4.jpg)

![The image displays a vertical battery icon with a rounded bottom. The top two-thirds of the icon is black and contains two small white squares arranged vertically. The bottom third is light grey and contains a single square symbol, which appears to be a white square with a black square inside it.](.com-hpc-client-base-manual-50m-77108-1000-01/34c583c3a50f45a14f9a93800d28bd1f8d74591441a7856e492315d18ab2d592.jpg)

# 5.24. GP\_SPI

GP\_SPI: GP\_SPI assigned, 12-pin, 2.54mm pitch

GP\_SPI depends on the module specifications

![The image displays a horizontal row of five identical, vertically oriented, rounded rectangular shapes in grey. Inside each shape, near the top short edge, are two small black dots side-by-side. Near the bottom short edge, centered horizontally, is a small square with a black outline.](.com-hpc-client-base-manual-50m-77108-1000-01/4a131084ed07dfb8d8f996dae2fbe0286f8934d27147747c3bfec27cd7d5cb0e.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>N.C</td></tr><tr><td>3</td><td>GP_SPI_CLK</td><td>4</td><td>GP_SPI_MOSI</td></tr><tr><td>5</td><td>GP_SPI_CS2#</td><td>6</td><td>GP_SPI_MISO</td></tr><tr><td>7</td><td>GP_SPI_CS3#</td><td>8</td><td>GP_SPI_CS0#</td></tr><tr><td>9</td><td>GP_SPI_ALERT#</td><td>10</td><td>GP_SPI_CS1#</td></tr><tr><td>11</td><td>N.C</td><td>12</td><td>GNG</td></tr></table>

# 5.25. Front Panel Control

Power Button, Reset Button, HDD LED, Power LED for front panel header

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>19</td><td>N.C</td><td>20</td><td>N.C</td></tr><tr><td>17</td><td>N.C</td><td>18</td><td>BUZZER</td></tr><tr><td>15</td><td>N.C</td><td>16</td><td>N.C</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>N.C</td></tr><tr><td>11</td><td>+5VSB</td><td>12</td><td>+5V</td></tr><tr><td>9</td><td>N.C</td><td>10</td><td>N.C</td></tr><tr><td>7</td><td>SYS_RESET#</td><td>8</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>PWR_BTN#</td></tr><tr><td>3</td><td>HDD_LED_N</td><td>4</td><td>GND</td></tr><tr><td>1</td><td>HDD_LED_P</td><td>2</td><td>+5V</td></tr></table>

![The image displays a vertical column of calculator buttons arranged in a grid of three columns. The buttons are grey with rounded corners and feature two small circular indentations. The text on the buttons, read from top to bottom and left to right, is:\n\n-, =, (\n7, 8, 9\n4, 5, 6\n1, 2, 3\n(), 0](.com-hpc-client-base-manual-50m-77108-1000-01/9b361d03cd07b31643613dc90bb5118224c8cd319f161b9c14be7239d71104f4.jpg)

# 5.26. Other Jumpers

JP5: clear CMOS.

To clear CMOS, shut down the power and short pin 2 and pin 3 (short VBAT to ground)

<table><tr><td>Jumper</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>Normal (default)</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr></table>

![The image displays a vertical graphic with a rounded bottom edge. The upper section is black and contains two small white squares arranged vertically. The lower section is grey and contains a single white square centered horizontally.](.com-hpc-client-base-manual-50m-77108-1000-01/61a1144937f26f49b8202d62035ea6578ae3250d5332d6c08d67b1880d826b72.jpg)

JP43: Enable or Disable Super I/O on carrier board

This function is not enabled yet at this version. The Super I/O at this version is always enabled

<table><tr><td>Jumper</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>TBC</td></tr><tr><td>2-3</td><td>TBC</td></tr></table>

![The image features a vertical rectangle with rounded corners, resembling a simplified remote or device. It is divided horizontally into a black upper section and a light grey lower section. Three small white squares are aligned vertically down the center: two are positioned within the black section, and one is positioned within the grey section.](.com-hpc-client-base-manual-50m-77108-1000-01/088f6156ab7c473da4ea5f4f7b1c6db901ceae54fbf28b64ff8a6a66e4b310ae.jpg)

JP3: Selection of Super I/O address

<table><tr><td>Jumper</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>4Eh</td></tr><tr><td>2-3</td><td>2Eh (default)</td></tr></table>

![The image displays a simple, vertical illustration of a remote control. The device is divided into two sections: the upper portion is black and features two small, white square buttons stacked vertically. The lower portion is grey and contains a single, larger white square button centered near the bottom. The entire object has a rounded rectangular shape with a curved bottom edge.](.com-hpc-client-base-manual-50m-77108-1000-01/546357c79f19801f081e45dcbae77fb386e4a026869adfcf858ce531e21fcf39.jpg)

# 5.27. Power Connectors

ATX\_24: ATX 24-pin Power Connector

Connect the ATX 24-pin (or 20-pin) connector to supply power to COM-HPC Client Base carrier.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>13</td><td>+3.3V</td></tr><tr><td>2</td><td>+3.3V</td><td>14</td><td>-12V</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>COM</td></tr><tr><td>4</td><td>+5V</td><td>16</td><td>PWR_ON</td></tr><tr><td>5</td><td>GND</td><td>17</td><td>COM</td></tr><tr><td>6</td><td>+5V</td><td>18</td><td>COM</td></tr><tr><td>7</td><td>GND</td><td>19</td><td>COM</td></tr><tr><td>8</td><td>PWR_GOOD</td><td>20</td><td>-5V</td></tr><tr><td>9</td><td>+5VSB</td><td>21</td><td>+5V</td></tr><tr><td>10</td><td>+12V</td><td>22</td><td>+5V</td></tr><tr><td>11</td><td>+12V</td><td>23</td><td>+5V</td></tr><tr><td>12</td><td>+3.3V</td><td>24</td><td>COM</td></tr></table>

![Simple diagram of a door with multiple compartments and a door handle (no text or symbols)](.com-hpc-client-base-manual-50m-77108-1000-01/621407d25420488f9b830e32f0c682778055d3c5214be79f1181b664e63c7cfc.jpg)

# ATX\_4: ATX 12V 4-pin Connector.

Connect the ATX 12V 4-pin connector to supply power to the COM-HPC Client module.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>+12V</td></tr><tr><td>4</td><td>+12V</td></tr></table>

![The image displays a section of a digital interface, likely from 3D modeling software, featuring a 2x2 grid of light grey geometric shapes on a white background.\n\n*   **Left Column:** Two identical squares are stacked vertically.\n*   **Right Column:** Two identical shapes are stacked vertically. Each shape consists of a square section on the left and a semi-circle section attached to its right side.\n*   **Lines:** Thin black lines separate the quadrants of the grid. A thick black vertical line runs down the far right edge of the image.\n\nThere is no visible text in the image.](.com-hpc-client-base-manual-50m-77108-1000-01/02b20fc304c456348988f108648b530eadf6c224986666407631eb6745dcbad3.jpg)

# JP46: selection of 5VSB source for module

<table><tr><td>Jumper</td><td>Module 5VSBY SOURCE</td></tr><tr><td>2-3</td><td>ATX Power Supply source (default)</td></tr><tr><td>3-4</td><td>DC to DC Power source</td></tr><tr><td>1-2</td><td>None</td></tr></table>

![The image features a horizontal rectangular graphic resembling a button or toggle switch. The left portion is black and contains two small white dots arranged vertically. The right portion is light gray and features a single small white square centered within it. The rightmost edge of the rectangle is rounded.](.com-hpc-client-base-manual-50m-77108-1000-01/629e9317c4ad836a21d50caa2b34cd7372a032fae78a3f1b8a791221f0da44cf.jpg)

# JP45, JP31: selection of power mode

AT mode means short PS\_ON# to ground directly to force power on

<table><tr><td>JP45</td><td>JP31</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>1-2</td><td>ATX Mode (default)</td></tr><tr><td>2-3</td><td>2-3</td><td>AT Mode</td></tr></table>

![A horizontal, rectangular object with a rounded left end. The left section is light gray and contains a small, dark square with a lighter center. The right section is black and features two small white dots.](.com-hpc-client-base-manual-50m-77108-1000-01/f0a78c9c4a4d7d67e95a77d197c75857d88ae55dbe216175e869842f2c797fe6.jpg)

# JP44: selection of PS\_ON source, from S3 or from S5

<table><tr><td>Jumper</td><td>ATX Power PS_ON Selection</td></tr><tr><td>2-3</td><td>Source from S5</td></tr><tr><td>1-2</td><td>Source from S3 (default)</td></tr></table>

![The image displays a close-up of the upper portion of an electronic device. On the left, a light gray section with a rounded edge features a black power symbol, depicted as a square with a white dot inside. To the right, on a black background, three small white dots are arranged in a horizontal row. A thin vertical line is visible on the far right edge.](.com-hpc-client-base-manual-50m-77108-1000-01/201e9be26913d88d07aeb1ad9beca85ab2d27731d55db7bb5a247eadbd985b54.jpg)

# 6. Carrier BIOS (need update)

The COM-HPC Client Base supports Carrier BIOS, using Boot Serial Peripheral Interface (SPI) for COM-HPC modules.

Secondary BIOS solutions can be used as an alternative to the on-module BIOS and provide support for the following:

• Testing new BIOS versions
• Development of firmware modifications
• Recovery if soldered BIOS on module is corrupted

To use the BIOS on the module:

short pins 1-2 on BESL2, BESL1, BESL0; reference section 5.23

To use the BIOS on the carrier board:

short pins 2-3 on BESL0, and keep pin 1-2 on BESL2, BESL1; reference section 5.23

Make sure that the secondary BIOS flash chip has been properly installed into the Carrier BIOS socket before BOOT BIOS adjusting.

![BSEL2\nBSEL1\nSYS_FAN1\nBSEL0\nSATAO\nBSEL1 BSEL0 BIOS Boot Select\n1- 1-2 1-2 Module SPIO/SPI1\n1-2 1-2 2-3 Carrier SPIO/Module SPI1\n1-2 2-3 1-2 Module SPIO/Carrier SPI1](.com-hpc-client-base-manual-50m-77108-1000-01/ba652e888c3473f95aaa72a7c04e04dfed05335387e4d26948ec59b1c553c98c.jpg)

# 7. Switches, POST and LEDs

# 7.1. Switches

There are four switches

PWR\_BTN: ATX Power Button

PWR\_BTN: Reset Button

SLP\_BTN: Sleep Button

LID\_BTN: Lid Button

Both SLP and LID buttons support COM Express Type 6 modules for ACPI power management behavior setting in an OS environment.

# 7.2. POST and inductors LEDs

An eSPI-based POST display is added for debugging.

The two 7-SEG LEDs shows the actual POST data.

A row of mini-LEDs nearby the POST display

indicates the following:

5VSB: ATX power attached on standby or active

S3: Indicates S3 status

PWR\_ON: Indicates power on

WDT: Indicates WDT (watchdog timer) activity

HDD: Indicates hard drive activity (at M.2 M-key)

WIFI: Indicates wireless device activity (at M.2 E-key)

# 7.3. ATX Power Connectors

The COM-HPC Client Base has one ATX 24-pin connector to supply power to the carrier board and one ATX 12V 4-pin connector to supply power to the COM-HPC module.

The system will not power on unless an ATX 12V 4-pin connector is connected. (JP45, JP31 at default setting)

![JP45\n0.22\n180\n25\n0.22\n180\n25\n0.22\n180\n25\nATX_24\nJP46\nJP33\nJP44\nJP46\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP33\nJP44\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP32\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP31\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP30\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP29\nJP28](.com-hpc-client-base-manual-50m-77108-1000-01/8f20da4c36d30972e6e993beef866b75b66bf19a1621e024c10e7ea44e938123.jpg)

# 7.4. AT Power Mode

To operate the system in AT Mode with an ATX power supply, Refer to section 5.27 jumper settings of JP45, JP31 for details
[🔗 Link to the original document](.com-hpc-client-base-manual-50m-77108-1000-01/com-hpc-client-base-manual-50m-77108-1000-01.pdf)
