# COM-HPC Mini Base-ATX

User’s Guide

![Close-up of a black printed circuit board with various electronic components and connectors (no visible text or labels)](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/45f0040287109fcf0e72007b47261c9a5c0c55f61f121166c176949c63a30b47.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>0.1</td><td>Preliminary release</td><td>2025-06-17</td><td>AL</td></tr><tr><td>0.2</td><td>Connectors and pinouts and power input connection updated</td><td>2025-06-23</td><td>AL</td></tr><tr><td>0.3</td><td>Power input connection updated</td><td>2025-06-25</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

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California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

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# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image displays a simple icon of a document or memo pad. It features a thick, reddish-orange outline of a white shape with the bottom-right corner folded over. Centered within the white area are two horizontal reddish-orange lines, resembling text.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/c5dc632b2c03142dd08d62ac1d2c402a1c74c66f106094f66e7b09f13bb3bbab.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow triangular warning sign with a black outline. In the center of the triangle is a white exclamation point.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/24da99b315e00c777b003704f4269583568ce83a0d78566eced2b60259da6e1f.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image shows a red, triangular warning sign with rounded corners. Inside the red triangle is a white exclamation mark centered vertically and horizontally. This is a standard symbol indicating caution or danger.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/b97a7c4959d0b2a50494236d980396004e2304294930dcb9dfd5c8a489e16b04.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

1. Introduction ... .10
2. Special Features.. .1

2.1. PCI Express x8 Gen5 ... . 11
2.2. Two Ethernet RJ45.. . 11
2.3. Two USB4 Type-C.. 11

3. Component Location Layout... ..12
4. Functional Diagram... .13
5. Connectors and Pinouts ...... ..14

5.1. Carrier Board Signals — Mini Type.. .. 14
5.2. Connector Location and Pinout Compatibility.... .. 15
5.3. Carrier Board Design... .. 16
5.4. COM-HPC Board-to-board Connectors.. .. 16
5.5. PCIe x8 Slot .. .. 20
5.6. PCIe x4 Slot .. .. 21
5.7. M.2 M-KEY... . 22
5.8. DisplayPort ... .. 22
5.9. eDP ..... .. 23
5.10. Audio HDA .. .. 25
5.11. Audio SNDW .. .. 25
5.12. Ethernet NBASE-T.. .. 26
5.13. USB .. .. 26
5.14. GPIO.. .. 28
5.15. I2C ... ... 28
5.16. UART / COM.. . 29
5.17. eSPI Debug Connector.. . 30
5.18. SMB ... .. 30
5.19. FAN Connector.. . 31
5.20. Carrier BIOS... .. 32
5.21. Front Panel Control.. .. 33

5.22. Other Jumpers ... ... 33
5.23. Power Connectors.. ... 34

6. Carrier BIOS ... ...36

7. Switches, POST, and LEDs.. .37

7.1. Control Switches .. ... 37
7.2. Post Display and LEDs ... .. 37

8. Power Input Connection ...... ...38

8.1. 12V Power Input at 24+4 Pin Power Connectors .. . 38
8.2. 8-20V Power Input at 4-Pin Power Connectors.. ... 39

# List of Figures

Figure 1 – Component location.. ..12
Figure 2 – Functional diagram.............. ...13
Figure 3 – Carrier board signals, server type pinout ......... ...14
Figure 4 – COM-HPC mini connector location and pinout compatibility... .15

# 1. Introduction

The COM-HPC modular approach, which combines a custom carrier with off-the-shelf system cores, relieves developers and manufacturers from the need to design their own system cores. This not only significantly accelerates their proof of concept but also empowers them to upgrade to latergeneration processors without a complete redesign. The COM-HPC concept reduces engineering complexity, lowers the minimum project quantity threshold, and—most importantly—gets your product to market in no time. On average, designing a carrier board takes less than half the time of creating a full custom board.

The COM-HPC Mini Base-ATX, based on PICMG COM-HPC R1.2, is an ATX-sized carrier board intended for validation purposes. With power input via a 24+4 pin power connector (or a 4-pin connector, TBC), and support for a COM-HPC Mini Type module of your choice along with off-the-shelf add-on cards, you can quickly emulate the functionality of your target end product for software development and hardware verification.

To build a functional prototype of your target system, you will need:

COM-HPC Mini Type module
COM-HPC Mini Base-ATX carrier
PCI Express-based storage or SATA storage (SATA storage solutions are dependent on module specifications)

The COM-HPC Mini Base-ATX is compatible with COM-HPC Mini Type modules and may accommodate:

1x PCI Express x8 slot, up to Gen5 (x4 or x8 configuration depends on module specifications)
1x PCI Express x4 slots and 1x M.2 M-key connector (supports up to 22110 M.2 M-key device)
1x DP ports, 1x eDP connector, and a 3-in-1 Audio port
2x USB4 Type-C, 2x USB3.x Type-A, 2x USB2.0 Type-A, and multiple USB headers for front panel use
2x Ethernet RJ45 connectors, up to 10GBASE-T (speed depends on module specifications)
Headers for I2C, SMBus, GPIO, COM ports, and more

# 2. Special Features

# 2.1. PCI Express x8 Gen5

FHFL PCI Express cards in the PCIE8-15 slot can support up to 2-slot-width PCI Express cards. The capability of PCI Express Gen5 and link configuration depend on the module specifications.

# 2.2. Two Ethernet RJ45

2x RJ45 connectors are capable of 10GbE speed, depending on the module specifications.

# 2.3. Two USB4 Type-C

2x USB4 Type-C connectors support up to USB3.x and DP alternative mode, depending on the module specifications.

# 3. Component Location Layout

![ATX_24\nATX_4\nSM_BATT\nEDP_DSI\nJP45\nJP1\nJP29\nRST_BTN\nSLP_BTN\nLID_BTN\nGP_SPI (opt.)\nF_2XUSB2.0\nSYS_FAN0\nF_MISC\nPVRR_BTN\n8 8\nM.2 Key-M\nPCIE4-7\nM.2\nSATA1 (opt.)\nOnly for SATA USAGE\nSuper I/O\nJP3\nGPIO\nI2CO_SMBUS\n8 8\nRTC (Battery)\nJP5\nCarrier_BIOS\nSystem PD FW\nStore Re-timer FW\nBSEL2\nBSEL1\nBSEL0\nDP_DDI0\nUSB_2 (top)\nUSB_4\nUSBA_SS6\nUSBC_SS2&3\nUSBA_SS7\nUSBC_SS4&5\nETH_0 (top)\nETH_1\nAudio\nAudio Sub\nPCIE8-15\nPCIE0-3\nAudio codec\nCOM1_SER0 COM2_SER1\nCOM1_SER0 COM2_SER1\nSNDW3 (opt.)\nSNDW2 (opt.)\nSNDW1 (opt.)\nSNDW0 (opt.)\nAudio\nRe-timer\nRe-timer\nAudio Sub](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/48728310394753a5703728e271e4dd2574d754ecf101b58b76d5f861d291b551.jpg)

Figure 1 – Component location

# 4. Functional Diagram

![The diagram is titled **COM-HPC mini Base**. It illustrates the connectivity of a central processor/base block (the large grey vertical rectangle) to various external interfaces and components.\n\n**Central Block Labels:**\nThe central block contains the following interface labels:\n*   NBSET 0\n*   NBSET 1\n*   SS 0-1 (DDI_0)\n*   EDP / DSI\n*   PCIe 4-5\n*   PCIe 6 / SATA_1\n*   PCIe 7 / SATA_0\n*   PCIe 0-3\n*   PCIe 8-11, 12-15\n*   GPIO_0-11\n*   UART_0-1\n*   I2C_0\n*   I2C_1\n*   Boot_SPI\n*   GP_SPI (opt.)\n*   SMB\n*   ESPI\n*   Thermal\n*   HDA /S2S/SNDW\n*   SNDW(0-1)\n*   USB3\n*   SS 6 (USB3_1)\n*   SS 2-3 (USB4_0)\n*   USB0\n*   USB5\n*   SS 7 (USB3_0)\n*   SS 4-5 (USB4_1)\n*   USB1\n*   USB2\n*   USB4\n*   USB(6.7)\n*   VCC_RTC\n*   Miscs.\n\n**Left Side Connections:**\n*   **DP:** Connects to SS 0-1 (DDI_0) and EDP / DSI.\n*   **Audio Jacks:** Connect to **Audio Codec Realtek ALC888**, which connects to HDA /S2S/SNDW.\n*   **USB Headers (Top Pair):** Connect to **TBT4 Intel JHL9040RIT** and **USB PD TI TPS65994BH**, and connect to lines USB3, SS 6 (USB3_1), SS 2-3 (USB4_0), and USB0.\n*   **USB Headers (Middle Pair):** Connect to **TBT4 Intel JHL9040RIT** and **USB PD TI TPS65994BH**, and connect to lines USB5, SS 7 (USB3_0), SS 4-5 (USB4_1), and USB1.\n*   **USB Headers (Bottom Pair):** Connect directly to USB2 and USB4.\n*   **SNDW:** **2xSNDW Headers (SNDW_2 & 3) (opt.)** connects to SNDW(0-1).\n\n**Right Side Connections:**\n*   **M.2/SATA:** **M.2 M Key (up to 22110)** and **SATA (optional)** connect via **MUX** blocks to PCIe 6 / SATA_1 and PCIe 7 / SATA_0.\n*   **PCIe Slots:** **PCIe x4** connects to PCIe 0-3. **PCIe x8** connects to PCIe 8-11, 12-15.\n*   **GPIO/Fan:** **2nd FAN connector** connects to GPIO_0-11, UART_0-1, I2C_0, and I2C_1.\n*   **EEPROM:** Connects to Boot_SPI.\n*   **Super I/O:** **Super I/O NCT6126D** connects to ESPI (via **ESPI Header**), SMB, Thermal, **COM Header**, **COM Header (COM3)** (via **SP339**), and **2x System FAN connector**. A note states 'eSPI_CS1 enabled required'.\n*   **SNDW:** **2xSNDW Headers (opt.)** connects via a dashed line to SNDW(0-1).\n\n**Bottom Connections:**\n*   **RTC:** **RTC BAT Clear CMOS** connects to VCC_RTC.\n*   **Front Panel:** **2xUSB (front panel)** connects to USB(6.7). **LEDs** and **BTN (PWR, RST, LID, SLP)** connect to Miscs.\n\n**Note:**\n*   'Note: SS means Super Speed Lanes. One SS consists of TX+/-, RX+/-'\n*   'USB0 means USB2.0 D+/D- port 0'](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/907d799a472f8c8456a9322b78ed67543407f09382e07f87018b92ad07313599.jpg)

Figure 2 – Functional diagram

# 5. Connectors and Pinouts

# 5.1. Carrier Board Signals — Mini Type

J1

![| Category | Value |\n|---|---|\n| 12V 5VSB (8-20V opt.) | - |\n| Audio HDA / I2S / Soundwire | - |\n| eDP | - |\n| USB2.0 8x | - |\n| 2x USB3 or USB4_1 | - |\n| 2x USB3 or USB4_3 | - |\n| DDI_0 or USB4_2 | - |\n| DDI_1 or USB4_0 | - |\n| 8x PCIe SATA, SGMII muxed | - |\n| 8x PCIe NVMe, GPU | - |\n| PCIe Target | - |\n| NBASE-T (max. 10G) 2x | - |\n| CAN 1x | - |\n| eSPI | - |](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/8191b5b77ea1c47b98ac4befd4a065d01b947aaf5f04b3ea28b0f365ebeb6212.jpg)

Figure 3 – Carrier board signals – mini-type Pinout

# 5.2. Connector Location and Pinout Compatibility

Connector positions and pinouts comply with the pinout and signal descriptions defined in the PICMG COM-HPC Carrier Design Guide R2. This document includes descriptions of pinouts, signals, and mechanical characteristics specified by the COM-HPC specification. The COM-HPC Mini Base-ATX carrier is compatible with COM-HPC Mini modules and the COM-HPC Module Base Specification R1.2.

![COM+HPC™\nMini\n(95 x 70mm)\nJ1](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/d7c9898dfc5e654362ae2658b46a5fe8a7664e30c71ba5e4f06cc59f3bd0a7b9.jpg)

Figure 4 – COM-HPC mini connector location and pinout compatibility

# 5.3. Carrier Board Design

COM-HPC Mini Base-ATX follows the PICMG COM-HPC Carrier Design Guide where applicable, and its design and schematics have been fully verified. It is recommended to utilize them as references for your carrier board design. COM-HPC Mini Base-ATX schematics and mechanical files, as well as the CDG, can be downloaded from ADLINK COM’s webpage or contact your local ADLINK representative.

# 5.4. COM-HPC Board-to-board Connectors

Signals and Pinouts for COM-HPC Mini Type

Signals described in the specification but not supported on the COM-HPC-mini carrier are marked by STRIKETHROUGH.

In addition, the overall feature set also depends on the module specifications.

<table><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A1</td><td>VCC</td><td></td><td>B1</td><td>VCC</td><td></td><td>C1</td><td>VCC</td><td></td><td>D1</td><td>VCC</td></tr><tr><td>A2</td><td>VCC</td><td></td><td>B2</td><td>PWRBTN#</td><td></td><td>C2</td><td>RSTBTN#</td><td></td><td>D2</td><td>VCC</td></tr><tr><td>A3</td><td>VCC</td><td></td><td>B3</td><td>VCC</td><td></td><td>C3</td><td>VCC</td><td></td><td>D3</td><td>VCC</td></tr><tr><td>A4</td><td>VCC</td><td></td><td>B4</td><td>THERMTRIP#</td><td></td><td>C4</td><td>CARRIER_HOT#</td><td></td><td>D4</td><td>VCC</td></tr><tr><td>A5</td><td>RAPID_SHUTDOWN</td><td></td><td>B5</td><td>CAN_TX</td><td></td><td>C5</td><td>CAN_RX</td><td></td><td>D5</td><td>PLTRST#</td></tr><tr><td>A6</td><td>FUSA_SPI_ALERT</td><td></td><td>B6</td><td>TAMPER#</td><td></td><td>C6</td><td>VIN_PWR_OK</td><td></td><td>D6</td><td>FUSA_SPI_CS#</td></tr><tr><td>A7</td><td>FUSA_STATUS0</td><td></td><td>B7</td><td>PROCHOT#</td><td></td><td>C7</td><td>CATERR#</td><td></td><td>D7</td><td>FUSA_SPI_CLK</td></tr><tr><td>A8</td><td>FUSA_STATUS1</td><td></td><td>B8</td><td>SUS_S3#</td><td></td><td>C8</td><td>SUS_S4_S5#</td><td></td><td>D8</td><td>FUSA_SPI_MISO</td></tr><tr><td>A9</td><td>PCIe_PERST_IN0#</td><td></td><td>B9</td><td>FUSA_VOLTAGE_ERR#</td><td></td><td>C9</td><td>FUSA_ALERT#</td><td></td><td>D9</td><td>FUSA_SPI_MOSI</td></tr><tr><td>A10</td><td>GND</td><td></td><td>B10</td><td>WD_STROBE#</td><td></td><td>C10</td><td>BATLOW#</td><td></td><td>D10</td><td>WAKE0#</td></tr><tr><td>A11</td><td>PCIe_REFCLKIN0-</td><td></td><td>B11</td><td>WD_OUT</td><td></td><td>C11</td><td>FAN_PWMOUT</td><td></td><td>D11</td><td>WAKE1#</td></tr><tr><td>A12</td><td>PCIe_REFCLKIN0+</td><td></td><td>B12</td><td>GND</td><td></td><td>C12</td><td>FAN_TACHIN</td><td></td><td>D12</td><td>GND</td></tr><tr><td>A13</td><td>GND</td><td></td><td>B13</td><td>USB5-</td><td></td><td>C13</td><td>GND</td><td></td><td>D13</td><td>USB1-</td></tr><tr><td>A14</td><td>USB7-</td><td></td><td>B14</td><td>USB5+</td><td></td><td>C14</td><td>USB3-</td><td></td><td>D14</td><td>USB1+</td></tr><tr><td>A15</td><td>USB7+</td><td></td><td>B15</td><td>GND</td><td></td><td>C15</td><td>USB3+</td><td></td><td>D15</td><td>GND</td></tr><tr><td>A16</td><td>GND</td><td></td><td>B16</td><td>USB4-</td><td></td><td>C16</td><td>GND</td><td></td><td>D16</td><td>USB0-</td></tr><tr><td>A17</td><td>USB6-</td><td></td><td>B17</td><td>USB4+</td><td></td><td>C17</td><td>USB2-</td><td></td><td>D17</td><td>USB0+</td></tr><tr><td>A18</td><td>USB6+</td><td></td><td>B18</td><td>GND</td><td></td><td>C18</td><td>USB2+</td><td></td><td>D18</td><td>GND</td></tr><tr><td>A19</td><td>GND</td><td></td><td>B19</td><td>I2S_LRCLK/SNDW_CLK3/HDA_SYNC</td><td></td><td>C19</td><td>GND</td><td></td><td>D19</td><td>SS01_SDA_AUX-</td></tr><tr><td>A20</td><td>SS23_SDA_AUX-</td><td></td><td>B20</td><td>I2S_DOUT/SNDW_DAT3/HDA_SDO</td><td></td><td>C20</td><td>SNDW_DMIC_CLK1</td><td></td><td>D20</td><td>SS01_SCL_AUX+</td></tr><tr><td>A21</td><td>SS23_SCL_AUX+</td><td></td><td>B21</td><td>I2S_MCLK/HDA_RST#</td><td></td><td>C21</td><td>SNDW_DMIC_DAT1</td><td></td><td>D21</td><td>GND</td></tr><tr><td>A22</td><td>GND</td><td></td><td>B22</td><td>I2S_DIN/SNDW_DAT2/HDA_SDI</td><td></td><td>C22</td><td>GND</td><td></td><td>D22</td><td>SS0_TX-</td></tr><tr><td>A23</td><td>SS2_TX-</td><td></td><td>B23</td><td>I2S_CLK/SNDW_CLK2/HDA_BCLK</td><td></td><td>C23</td><td>SNDW_DMIC_CLK0</td><td></td><td>D23</td><td>SS0_TX+</td></tr><tr><td>A24</td><td>SS2_TX+</td><td></td><td>B24</td><td>RSVD</td><td></td><td>C24</td><td>SNDW_DMIC_DAT0</td><td></td><td>D24</td><td>GND</td></tr><tr><td>A25</td><td>GND</td><td></td><td>B25</td><td>USB67_OC#</td><td></td><td>C25</td><td>GND</td><td></td><td>D25</td><td>SS0_RX-</td></tr><tr><td>A26</td><td>SS2_RX-</td><td></td><td>B26</td><td>USB45_OC#</td><td></td><td>C26</td><td>USB0_LSRX/DDI1_DDC_AUX_SEL</td><td></td><td>D26</td><td>SS0_RX+</td></tr><tr><td>A27</td><td>SS2_RX+</td><td></td><td>B27</td><td>USB23_OC#</td><td></td><td>C27</td><td>USB1_LSRX</td><td></td><td>D27</td><td>GND</td></tr><tr><td>A28</td><td>GND</td><td></td><td>B28</td><td>USB01_OC#</td><td></td><td>C28</td><td>USB0_LSTX/DDI1_HPD</td><td></td><td>D28</td><td>SS1_TX-</td></tr><tr><td>A29</td><td>SS3_TX-</td><td></td><td>B29</td><td>SML1_CLK</td><td></td><td>C29</td><td>USB1_LSTX</td><td></td><td>D29</td><td>SS1_TX+</td></tr><tr><td>A30</td><td>SS3_TX+</td><td></td><td>B30</td><td>SML1_DAT</td><td></td><td>C30</td><td>eDP_HPD</td><td></td><td>D30</td><td>GND</td></tr><tr><td>A31</td><td>GND</td><td></td><td>B31</td><td>PMCALERT#</td><td></td><td>C31</td><td>eDP_VDD_EN</td><td></td><td>D31</td><td>SS1_RX1</td></tr><tr><td>A32</td><td>SS3_RX-</td><td></td><td>B32</td><td>SML0_CLK</td><td></td><td>C32</td><td>eDP_BKLT_EN</td><td></td><td>D32</td><td>SS1_RX+</td></tr><tr><td>A33</td><td>SS3_RX+</td><td></td><td>B33</td><td>SML0_DAT</td><td></td><td>C33</td><td>eDP_BKLTCTL</td><td></td><td>D33</td><td>GND</td></tr><tr><td>A34</td><td>GND</td><td></td><td>B34</td><td>USB_PD_ALERT#</td><td></td><td>C34</td><td>GND</td><td></td><td>D34</td><td>ACPRESENT</td></tr><tr><td>A35</td><td>eDP_AUX-</td><td></td><td>B35</td><td>USB_PD_I2C_CLK</td><td></td><td>C35</td><td>USB3_AUX-</td><td></td><td>D35</td><td>NBASET1_SDP</td></tr><tr><td>A36</td><td>eDP_AUX+</td><td></td><td>B36</td><td>USB_PD_I2C_DAT</td><td></td><td>C36</td><td>USB3_AUX+</td><td></td><td>D36</td><td>GND</td></tr><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A37</td><td>GND</td><td></td><td>B37</td><td>USB_RT_ENA</td><td></td><td>C37</td><td>GND</td><td></td><td>D37</td><td>SS6_TX-</td></tr><tr><td>A38</td><td>eDP_TX0-</td><td></td><td>B38</td><td>USB3_LSRX</td><td></td><td>C38</td><td>SS6_RX-</td><td></td><td>D38</td><td>SS6_TX+</td></tr><tr><td>A39</td><td>eDP_TX0+</td><td></td><td>B39</td><td>USB3_LSTX</td><td></td><td>C39</td><td>SS6_RX+</td><td></td><td>D39</td><td>GND</td></tr><tr><td>A40</td><td>GND</td><td></td><td>B40</td><td>USB2_LSRX/DDI0_DDC_AUX_SEL</td><td></td><td>C40</td><td>GND</td><td></td><td>D40</td><td>SS7_TX-</td></tr><tr><td>A41</td><td>eDP_TX1-</td><td></td><td>B41</td><td>USB2_LSTX/DDI0_HPD</td><td></td><td>C41</td><td>SS7_RX-</td><td></td><td>D41</td><td>SS7_TX+</td></tr><tr><td>A42</td><td>eDP_TX1+</td><td></td><td>B42</td><td>GND</td><td></td><td>C42</td><td>SS7_RX+</td><td></td><td>D42</td><td>GND</td></tr><tr><td>A43</td><td>GND</td><td></td><td>B43</td><td>USB1_AUX-</td><td></td><td>C43</td><td>GND</td><td></td><td>D43</td><td>SS4_TX-</td></tr><tr><td>A44</td><td>eDP_TX2-</td><td></td><td>B44</td><td>USB1_AUX+</td><td></td><td>C44</td><td>SS4_RX-</td><td></td><td>D44</td><td>SS4_TX+</td></tr><tr><td>A45</td><td>eDP_TX2+</td><td></td><td>B45</td><td>LID#</td><td></td><td>C45</td><td>SS4_RX+</td><td></td><td>D45</td><td>GND</td></tr><tr><td>A46</td><td>GND</td><td></td><td>B46</td><td>SLEEP#</td><td></td><td>C46</td><td>GND</td><td></td><td>D46</td><td>SS5_TX-</td></tr><tr><td>A47</td><td>eDP_TX3-</td><td></td><td>B47</td><td>VCC_BOOT_SPI</td><td></td><td>C47</td><td>SS5_RX-</td><td></td><td>D47</td><td>SS5_TX+</td></tr><tr><td>A48</td><td>eDP_TX3+</td><td></td><td>B48</td><td>BOOT_SPI_CS#</td><td></td><td>C48</td><td>SS5_RX+</td><td></td><td>D48</td><td>GND</td></tr><tr><td>A49</td><td>GND</td><td></td><td>B49</td><td>BSEL0</td><td></td><td>C49</td><td>GND</td><td></td><td>D49</td><td>NBASET1_MDIO-</td></tr><tr><td>A50</td><td>eSPI_IO0</td><td></td><td>B50</td><td>BSEL1</td><td></td><td>C50</td><td>BOOT_SPI_IO0</td><td></td><td>D50</td><td>NBASET1_MDIO+</td></tr><tr><td>A51</td><td>eSPI_IO1</td><td></td><td>B51</td><td>BSEL2</td><td></td><td>C51</td><td>BOOT_SPI_IO1</td><td></td><td>D51</td><td>GND</td></tr><tr><td>A52</td><td>eSPI_IO2</td><td></td><td>B52</td><td>eSPI_ALERT0#</td><td></td><td>C52</td><td>BOOT_SPI_IO2</td><td></td><td>D52</td><td>NBASET1_MDII-</td></tr><tr><td>A53</td><td>eSPI_IO3</td><td></td><td>B53</td><td>eSPI_ALERT1#</td><td></td><td>C53</td><td>BOOT_SPI_IO3</td><td></td><td>D53</td><td>NBASET1_MDII+</td></tr><tr><td>A54</td><td>eSPI_CLK</td><td></td><td>B54</td><td>eSPI_CS0#</td><td></td><td>C54</td><td>BOOT_SPI_CLK</td><td></td><td>D54</td><td>GND</td></tr><tr><td>A55</td><td>GND</td><td></td><td>B55</td><td>eSPI_CS1#</td><td></td><td>C55</td><td>GND</td><td></td><td>D55</td><td>NBASET1_MDII2-</td></tr><tr><td>A56</td><td>PCIe_CLKREQ0_LO#</td><td></td><td>B56</td><td>eSPI_RST#</td><td></td><td>C56</td><td>PCIe_REFCLK0_HI-</td><td></td><td>D56</td><td>NBASET1_MDI2+</td></tr><tr><td>A57</td><td>PCIe_CLKREQ0_HI#</td><td></td><td>B57</td><td>PCIe_WAKE_OUT0#</td><td></td><td>C57</td><td>PCIe_REFCLK0_HI+</td><td></td><td>D57</td><td>GND</td></tr><tr><td>A58</td><td>PCIe_CLKREQ_OUT0#</td><td></td><td>B58</td><td>NBASET1_LINK_MID#</td><td></td><td>C58</td><td>GND</td><td></td><td>D58</td><td>NBASET1_MDI3-</td></tr><tr><td>A59</td><td>NBASET1_LINK_MAX#</td><td></td><td>B59</td><td>NBASET1LINK_ACT#</td><td></td><td>C59</td><td>PCIe_REFCLK0_LO-</td><td></td><td>D59</td><td>NBASET1_MDI3+</td></tr><tr><td>A60</td><td>NBASET1_CTREF</td><td></td><td>B60</td><td>GND</td><td></td><td>C60</td><td>PCIe_REFCLK0_LO+</td><td></td><td>D60</td><td>GND</td></tr><tr><td>A61</td><td>GND</td><td></td><td>B61</td><td>PCIe08_RX-</td><td></td><td>C61</td><td>GND</td><td></td><td>D61</td><td>PCIe00_TX-</td></tr><tr><td>A62</td><td>PCIe08_TX-</td><td></td><td>B62</td><td>PCIe08_RX+</td><td></td><td>C62</td><td>PCIe00_RX-</td><td></td><td>D62</td><td>PCIe00_TX+</td></tr><tr><td>A63</td><td>PCIe08_TX+</td><td></td><td>B63</td><td>GND</td><td></td><td>C63</td><td>PCIe00_RX+</td><td></td><td>D63</td><td>GND</td></tr><tr><td>A64</td><td>GND</td><td></td><td>B64</td><td>PCIe09_RX-</td><td></td><td>C64</td><td>GND</td><td></td><td>D64</td><td>PCIe01_TX-</td></tr><tr><td>A65</td><td>PCIe09_TX-</td><td></td><td>B65</td><td>PCIe09_RX+</td><td></td><td>C65</td><td>PCIe01_RX-</td><td></td><td>D65</td><td>PCIe01_TX+</td></tr><tr><td>A66</td><td>PCIe09_TX+</td><td></td><td>B66</td><td>GND</td><td></td><td>C66</td><td>PCIe01_RX+</td><td></td><td>D66</td><td>GND</td></tr><tr><td>A67</td><td>GND</td><td></td><td>B67</td><td>PCIe10_RX-</td><td></td><td>C67</td><td>GND</td><td></td><td>D67</td><td>PCIe02_TX-/SGMII1_TX-</td></tr><tr><td>A68</td><td>PCIe10_TX-</td><td></td><td>B68</td><td>PCIe10_RX+</td><td></td><td>C68</td><td>PCIe02_RX-/SGMII1_RX-</td><td></td><td>D68</td><td>PCIe02_TX+/SGMII1_TX+</td></tr><tr><td>A69</td><td>PCIe10_TX+</td><td></td><td>B69</td><td>GND</td><td></td><td>C69</td><td>PCIe02_RX+/SGMII1_RX+</td><td></td><td>D69</td><td>GND</td></tr><tr><td>A70</td><td>GND</td><td></td><td>B70</td><td>PCIe11_RX-</td><td></td><td>C70</td><td>GND</td><td></td><td>D70</td><td>PCIe03_TX-/SGMII0_TX-</td></tr><tr><td>A71</td><td>PCIe11_TX-</td><td></td><td>B71</td><td>PCIe11_RX+</td><td></td><td>C71</td><td>PCIe03_RX-/SGMII0_RX-</td><td></td><td>D71</td><td>PCIe03_TX+/SGMII0_TX+</td></tr><tr><td>A72</td><td>PCIe11_TX+</td><td></td><td>B72</td><td>GND</td><td></td><td>C72</td><td>PCIe03_RX+/SGMII0_RX+</td><td></td><td>D72</td><td>GND</td></tr><tr><td colspan="2">Row A</td><td></td><td colspan="2">Row B</td><td></td><td colspan="2">Row C</td><td></td><td colspan="2">Row D</td></tr><tr><td>A73</td><td>GND</td><td></td><td>B73</td><td>PCIe12_RX-</td><td></td><td>C73</td><td>GND</td><td></td><td>D73</td><td>PCIe04_TX-</td></tr><tr><td>A74</td><td>PCIe12_TX-</td><td></td><td>B74</td><td>PCIe12_RX+</td><td></td><td>C74</td><td>PCIe04_RX-</td><td></td><td>D74</td><td>PCIe04_TX+</td></tr><tr><td>A75</td><td>PCIe12_TX+</td><td></td><td>B75</td><td>GND</td><td></td><td>C75</td><td>PCIe04_RX+</td><td></td><td>D75</td><td>GND</td></tr><tr><td>A76</td><td>GND</td><td></td><td>B76</td><td>PCIe13_RX-</td><td></td><td>C76</td><td>GND</td><td></td><td>D76</td><td>PCIe05_TX-</td></tr><tr><td>A77</td><td>PCIe13_TX-</td><td></td><td>B77</td><td>PCIe13_RX+</td><td></td><td>C77</td><td>PCIe05_RX-</td><td></td><td>D77</td><td>PCIe05_TX+</td></tr><tr><td>A78</td><td>PCIe13_TX+</td><td></td><td>B78</td><td>GND</td><td></td><td>C78</td><td>PCIe05_RX+</td><td></td><td>D78</td><td>GND</td></tr><tr><td>A79</td><td>GND</td><td></td><td>B79</td><td>PCIe14_RX-</td><td></td><td>C79</td><td>GND</td><td></td><td>D79</td><td>PCIe06_TX-/SATA1_TX-</td></tr><tr><td>A80</td><td>PCIe14_TX-</td><td></td><td>B80</td><td>PCIe14_RX+</td><td></td><td>C80</td><td>PCIe06_RX-/SATA1_RX-</td><td></td><td>D80</td><td>PCIe06_TX+/SATA1_TX+</td></tr><tr><td>A81</td><td>PCIe14_TX+</td><td></td><td>B81</td><td>GND</td><td></td><td>C81</td><td>PCIe06_RX+/SATA1_RX+</td><td></td><td>D81</td><td>GND</td></tr><tr><td>A82</td><td>GND</td><td></td><td>B82</td><td>PCIe15_RX-</td><td></td><td>C82</td><td>GND</td><td></td><td>D82</td><td>PCIe07_TX-/SATA0_TX-</td></tr><tr><td>A83</td><td>PCIe15_TX-</td><td></td><td>B83</td><td>PCIe15_RX+</td><td></td><td>C83</td><td>PCIe07_RX-/SATA0_RX-</td><td></td><td>D83</td><td>PCIe07_TX+/SATA0_TX+</td></tr><tr><td>A84</td><td>PCIe15_TX+</td><td></td><td>B84</td><td>GND</td><td></td><td>C84</td><td>PCIe07_RX+/SATA0_RX+</td><td></td><td>D84</td><td>GND</td></tr><tr><td>A85</td><td>GND</td><td></td><td>B85</td><td>TEST#</td><td></td><td>C85</td><td>GND</td><td></td><td>D85</td><td>NBASET0_MDIO-</td></tr><tr><td>A86</td><td>VCC_RTC</td><td></td><td>B86</td><td>RSMRST_OUT#</td><td></td><td>C86</td><td>SMB_CLK</td><td></td><td>D86</td><td>NBASET0_MDIO+</td></tr><tr><td>A87</td><td>SUS_CLK</td><td></td><td>B87</td><td>UART1_TX</td><td></td><td>C87</td><td>SMB_DAT</td><td></td><td>D87</td><td>GND</td></tr><tr><td>A88</td><td>GPIO_00</td><td></td><td>B88</td><td>UART1_RX</td><td></td><td>C88</td><td>SMB_ALERT#</td><td></td><td>D88</td><td>NBASET0_MDI1-</td></tr><tr><td>A89</td><td>GPIO_01</td><td></td><td>B89</td><td>UART1_RTS#</td><td></td><td>C89</td><td>UART0_TX</td><td></td><td>D89</td><td>NBASET0_MDI1+</td></tr><tr><td>A90</td><td>GPIO_02</td><td></td><td>B90</td><td>UART1_CTS#</td><td></td><td>C90</td><td>UART0_RX</td><td></td><td>D90</td><td>GND</td></tr><tr><td>A91</td><td>GPIO_03</td><td></td><td>B91</td><td>I2C2_CLK/ETH_MDIO_CLK</td><td></td><td>C91</td><td>UART0_RTS#</td><td></td><td>D91</td><td>NBASET0_MDI2-</td></tr><tr><td>A92</td><td>GPIO_04</td><td></td><td>B92</td><td>I2C2_DAT/ETH_MDIO_DAT</td><td></td><td>C92</td><td>UART0_CTS#</td><td></td><td>D92</td><td>NBASET0_MDI2+</td></tr><tr><td>A93</td><td>GPIO_05</td><td></td><td>B93</td><td>GP_SPI_MOSI</td><td></td><td>C93</td><td>I2C0_CLK</td><td></td><td>D93</td><td>GND</td></tr><tr><td>A94</td><td>GPIO_06</td><td></td><td>B94</td><td>GP_SPI_MISO</td><td></td><td>C94</td><td>I2C0_DAT</td><td></td><td>D94</td><td>NBASET0_MDI3-</td></tr><tr><td>A95</td><td>GPIO_07</td><td></td><td>B95</td><td>GP_SPI_CS0#</td><td></td><td>C95</td><td>I2C0_ALERT#</td><td></td><td>D95</td><td>NBASET0_MDI3+</td></tr><tr><td>A96</td><td>GPIO_08</td><td></td><td>B96</td><td>GP_SPI_CS1#</td><td></td><td>C96</td><td>I2C1_CLK</td><td></td><td>D96</td><td>GND</td></tr><tr><td>A97</td><td>GPIO_09</td><td></td><td>B97</td><td>GP_SPI_CS2#</td><td></td><td>C97</td><td>I2C1_DAT</td><td></td><td>D97</td><td>NBASET0_LINK_MAX#</td></tr><tr><td>A98</td><td>GPIO_10</td><td></td><td>B98</td><td>GP_SPI_CS3#</td><td></td><td>C98</td><td>NBASET0_SDP</td><td></td><td>D98</td><td>NBASET0_LINK_MID#</td></tr><tr><td>A99</td><td>GPIO_11</td><td></td><td>B99</td><td>GP_SPI_CLK</td><td></td><td>C99</td><td>NBASET0_CTREF</td><td></td><td>D99</td><td>NBASET0_LINK_ACT#</td></tr><tr><td>A100</td><td>PINOUT_TYPE0</td><td></td><td>B100</td><td>GP_SPI_ALERT#</td><td></td><td>C100</td><td>PINOUT_TYPE1</td><td></td><td>D100</td><td>PINOUT_TYPE2</td></tr></table>

![The image shows a square icon with a thick red border. Inside, there is a white shape resembling a document with a folded top-right corner. Two horizontal red lines are centered within the shape. There is no text in the image.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/a2104f034b41bcb6a3059fa8d28562312de1e20e0f3674957dcb604c93948747.jpg)
Note: SATA, SNDW, GP\_SPI are optional feature and also depends on module’s specifications

![The image shows a graphic icon of a document or file. It features a thick red outline forming a rectangular shape with a folded bottom-right corner. Inside the outline, two horizontal red lines are centered vertically, representing text lines. The background within the red border is white.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/4bb5a75ee89058ef8b803d5cf27377781e7446fe856adafc2c51ec7861527a74.jpg)
Note: ESPI\_CS1 pin need be enabled at module’s BIOS setting. Super I/O works if the ESPI\_CS1 enabled

The example below illustrates the interface or usage of each connectors/jumper.

# PCle 16-31: Group 1 Lanes 16:31 assigned PClex16 Slot

slikscreen

interface from module or IC on carrier

more information

# 5.5. PCIe x8 Slot

PCIE8-15: Lanes 8-15 assigned to the PCIex8 slot, supporting speeds up to Gen5. The slot is open-ended and supports

x8 or x4 configuration, for example one x8 or two x4, depending on the PCIe root port configuration.

The speed and configuration are dependent on the module specifications.

An additional PCIe lane-splitting add-on is required to validate two x4 signal configurations.

![Pure electrical circuit lines without any symbols](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/4ad4f4ec996fd7ba904970045b02aa18c903ae2bfadb7cc31b81bb0b4e8cecd1.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+ 12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+ 12V</td><td>A2</td><td>+ 12V</td></tr><tr><td>B3</td><td>+ 12V</td><td>A3</td><td>+ 12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+ 3.3V</td></tr><tr><td>B10</td><td>+ 3.3VAUX</td><td>A10</td><td>+ 3.3V</td></tr><tr><td>B11</td><td>WAKE#</td><td>A11</td><td>PERST#</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td>B33</td><td>PETp4</td><td>A33</td><td>RSVD</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B43</td><td>GND</td><td>A43</td><td>PERp6</td></tr><tr><td>B44</td><td>GND</td><td>A44</td><td>PERn6</td></tr><tr><td>B45</td><td>PETp7</td><td>A45</td><td>GND</td></tr><tr><td>B46</td><td>PETn7</td><td>A46</td><td>GND</td></tr><tr><td>B47</td><td>GND</td><td>A47</td><td>PERp7</td></tr><tr><td>B48</td><td>PRSNT</td><td>A48</td><td>PERn7</td></tr><tr><td>B49</td><td>GND</td><td>A49</td><td>GND</td></tr><tr><td>B50</td><td>PETp8</td><td>A50</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr></table>

<table><tr><td>B34</td><td>PETn4</td><td>A34</td><td>GND</td></tr><tr><td>B35</td><td>GND</td><td>A35</td><td>PERp4</td></tr><tr><td>B36</td><td>GND</td><td>A36</td><td>PERn4</td></tr><tr><td>B37</td><td>PETp5</td><td>A37</td><td>GND</td></tr><tr><td>B38</td><td>PETn5</td><td>A38</td><td>GND</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B39</td><td>GND</td><td>A39</td><td>PERp5</td></tr><tr><td>B40</td><td>GND</td><td>A40</td><td>PERn5</td></tr><tr><td>B41</td><td>PETp6</td><td>A41</td><td>GND</td></tr><tr><td>B42</td><td>PETn6</td><td>A42</td><td>GND</td></tr></table>

<table><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.6. PCIe x4 Slot

PCIE0-3: Lanes 0:3 assigned PCIex4 slot

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B1</td><td>+12V</td><td>A1</td><td>PRSNT</td></tr><tr><td>B2</td><td>+12V</td><td>A2</td><td>+12V</td></tr><tr><td>B3</td><td>+12V</td><td>A3</td><td>+12V</td></tr><tr><td>B4</td><td>GND</td><td>A4</td><td>GND</td></tr><tr><td>B5</td><td>SMB_CLK</td><td>A5</td><td>JTAG</td></tr><tr><td>B6</td><td>SMB_DAT</td><td>A6</td><td>JTAG</td></tr><tr><td>B7</td><td>GND</td><td>A7</td><td>JTAG</td></tr><tr><td>B8</td><td>+3.3V</td><td>A8</td><td>JTAG</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B9</td><td>JTAG</td><td>A9</td><td>+3.3V</td></tr><tr><td>B10</td><td>+3.3VAUX</td><td>A10</td><td>+3.3V</td></tr><tr><td>B11</td><td>WAKE</td><td>A11</td><td>PERST#</td></tr></table>

![The image shows a horizontal, rectangular grey hardware component, resembling a server chassis panel or backplane. It features two long, black horizontal strips running across the center, each containing a repeating pattern of vertical slats or vents. On the far left edge, a small grey latch protrudes, while on the far right edge, there is a small circular indentation. Along the bottom edge, several small, faint circular markings or screws are visible.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/4c457ada51dbec9ecf3aa2d0393f24fcdbff64dc0168aa9f3ea03f91baa3b19a.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B12</td><td>RSVD</td><td>A12</td><td>GND</td></tr><tr><td>B13</td><td>GND</td><td>A13</td><td>REFCLK+</td></tr><tr><td>B14</td><td>PETp0</td><td>A14</td><td>REFCLK-</td></tr><tr><td>B15</td><td>PETn0</td><td>A15</td><td>GND</td></tr><tr><td>B16</td><td>GND</td><td>A16</td><td>PERp0</td></tr><tr><td>B17</td><td>PRSNT</td><td>A17</td><td>PERn0</td></tr><tr><td>B18</td><td>GND</td><td>A18</td><td>GND</td></tr><tr><td>B19</td><td>PETp1</td><td>A19</td><td>RSVD</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B20</td><td>PETn1</td><td>A20</td><td>GND</td></tr><tr><td>B21</td><td>GND</td><td>A21</td><td>PERp1</td></tr><tr><td>B22</td><td>GND</td><td>A22</td><td>PERn1</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B23</td><td>PETp2</td><td>A23</td><td>GND</td></tr><tr><td>B24</td><td>PETn2</td><td>A24</td><td>GND</td></tr><tr><td>B25</td><td>GND</td><td>A25</td><td>PERp2</td></tr><tr><td>B26</td><td>GND</td><td>A26</td><td>PERn2</td></tr><tr><td>B27</td><td>PETp3</td><td>A27</td><td>GND</td></tr><tr><td>B28</td><td>PETn3</td><td>A28</td><td>GND</td></tr><tr><td>B29</td><td>GND</td><td>A29</td><td>PERp3</td></tr><tr><td>B30</td><td>RSVD</td><td>A30</td><td>PERn3</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>B31</td><td>PRSNT</td><td>A31</td><td>GND</td></tr><tr><td>B32</td><td>GND</td><td>A32</td><td>RSVD</td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.7. M.2 M-KEY

M.2 Key-M: Lanes 4-7 assigned M.2 slot Up to 22110 M.2 dimension

![This image displays a vertical rectangular graphic, resembling a label. On the left, a dark grey background features the text 'M.2' in large, white, italicized sans-serif font. To the right, a narrower vertical strip has a white background with a repeating pattern of small, vertical black dashes.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/503579bfe2c3560bc14f9f86d52412474b175b469e178290fde919d8b63634d5.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CONFIG</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>+3.3V</td></tr><tr><td>5</td><td>PERn3</td><td>6</td><td>N.C</td></tr><tr><td>7</td><td>PERp3</td><td>8</td><td>N.C</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>DAS/DSS#</td></tr><tr><td>11</td><td>PETn3</td><td>12</td><td>+3.3V</td></tr><tr><td>13</td><td>PETp3</td><td>14</td><td>+3.3V</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>+3.3V</td></tr><tr><td>17</td><td>PERn2</td><td>18</td><td>+3.3V</td></tr><tr><td>19</td><td>PERp2</td><td>20</td><td>N.C</td></tr><tr><td>21</td><td>CONFIG</td><td>22</td><td>N.C</td></tr><tr><td>23</td><td>PETn2</td><td>24</td><td>N.C</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>25</td><td>PETp2</td><td>26</td><td>N.C</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>N.C</td></tr><tr><td>29</td><td>PERn1</td><td>30</td><td>N.C</td></tr><tr><td>31</td><td>PERp1</td><td>32</td><td>N.C</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>N.C</td></tr><tr><td>35</td><td>PETn1</td><td>36</td><td>N.C</td></tr><tr><td>37</td><td>PETp1</td><td>38</td><td>DEVSLP</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>N.C</td></tr><tr><td>41</td><td>PERn0</td><td>42</td><td>N.C</td></tr><tr><td>43</td><td>PERp0</td><td>44</td><td>N.C</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>N.C</td></tr><tr><td>47</td><td>PETn0</td><td>48</td><td>N.C</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>49</td><td>PETp0</td><td>50</td><td>PETST#</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>CLKREQ#</td></tr><tr><td>53</td><td>REFCLKN</td><td>54</td><td>PEWAKE#</td></tr><tr><td>55</td><td>REFCLKP</td><td>56</td><td>N.C</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>N.C</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td>67</td><td>N.C</td><td>68</td><td>SUSCLK</td></tr><tr><td>69</td><td>CONFIG</td><td>70</td><td>+3.3V</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>+3.3V</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>+3.3V</td></tr><tr><td>75</td><td>CONFIG</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

# 5.8. DisplayPort

DP connector at Rear I/O

• DP\_DDI0: DDI0 channel assigned. DDI0 consist of SS 0-1 high speed signals and its relative sideband signals DP++ function depends on the module specifications

# 5.9. eDP

EDP\_DSI: 4 lanes eDP signal assigned

40-pin connectors

DSI not supported

![The image displays a horizontal, cylindrical object colored primarily yellow with darker orange caps at the left and right ends. It is outlined with black lines. Inside the yellow section, there are horizontal black lines running near the top and bottom edges, and vertical black lines separating the yellow section from the end caps. The entire object is framed by thin black horizontal lines at the very top and bottom.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/dd88e31f66c1b1fadb496f31db5dc3207b3f1d8cbe06ed356ea0b9919d556941.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>N.C</td><td>2</td><td>BKL_PWR</td></tr><tr><td>3</td><td>BKL_PWR</td><td>4</td><td>BKL_PWR</td></tr><tr><td>5</td><td>BKL_PWR</td><td>6</td><td>N.C</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>BKL_CTRL</td></tr><tr><td>9</td><td>BKL_ENABLE</td><td>10</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>HPD</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>N.C</td><td>20</td><td>Panel_PWR</td></tr><tr><td>21</td><td>Panel_PWR</td><td>22</td><td>Panel_PWR</td></tr><tr><td>23</td><td>Panel_PWR</td><td>24</td><td>GND</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>25</td><td>AUX_N</td><td>26</td><td>AUX_P</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>eDP_LANE0_P</td></tr><tr><td>29</td><td>eDP_LANE0_N</td><td>30</td><td>GND</td></tr><tr><td>31</td><td>eDP_LANE1_P</td><td>32</td><td>eDP_LANE1_N</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>eDP_LANE2_P</td></tr><tr><td>35</td><td>eDP_LANE2_N</td><td>36</td><td>GND</td></tr><tr><td>37</td><td>eDP_LANE3_P</td><td>38</td><td>eDP_LANE3_N</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>N.C</td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td></tr></table>

![The image displays a red icon resembling a document or a note. It is a square shape with a white interior and a red outline. The bottom-right corner is folded inward (a page curl effect) and is colored red. Inside the white space, there are two horizontal red lines centered horizontally.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/61b0ab469d0e707812cff2c51236bc645b3d4a1c03c81245d5a90b095639e90f.jpg)

Note: BKL\_PWR (backlight power) defaults to 5V, and Panel\_PWR defaults to 3.3V. Both can be adjusted using JP28, JP29, as shown in the table below.

# PANEL\_PWR: power for eDP panel

6-pin head

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>+3.3V</td><td>4</td><td>+3.3V</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr></table>

![The image displays a vertical stack of three rounded rectangular shapes resembling buttons on a remote control. The top two shapes each contain two small, empty square outlines side-by-side. The bottom shape contains a small, empty square outline on the left and a larger, solid black square on the right.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/24cc836850de21780630ff5f22f7525afe756720f48fb9a2b206952910f50218.jpg)

# JP28: panel power setting

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>3.3V (default)</td></tr><tr><td>2-3</td><td>5V</td></tr></table>

# JP29: backlight power setting

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>12V</td></tr><tr><td>2-3</td><td>5V (default)</td></tr></table>

# 5.10. Audio HDA

Audio\_HDA: HDA assigned at Rear I/O

3-in-1 audio jack

<table><tr><td>Color</td><td>Signal</td></tr><tr><td>BLUE</td><td>LINE-IN</td></tr><tr><td>GREEN</td><td>LINE-OUT</td></tr><tr><td>PINK</td><td>MIC-IN</td></tr></table>

![The image displays a vertical grey rectangular panel containing three circular lights arranged in a column. The top light is a light blue ring with a black center. The middle light is a light green ring with a black center. The bottom light is a light pink ring with a black center. There is no text visible in the image.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/ea3542d1b70cb4974283bc86f2a7ef8fe3aaee1023cc650da29e0e73fe8c9b3d.jpg)

# 5.11. Audio SNDW

SNDW0: SNDW0 signal assigned

SNDW1: SNDW1 signal assigned

SNDW2: SNDW2 signal assigned

SNDW3: SNDW3 signal assigned

![The image displays a simple line drawing of a rectangular input field. Inside the rectangle, there is a small square symbol on the left, followed by five hollow circles spaced out horizontally to the right.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/6ebfa8789fd8e7287088c0effe11fbde475b2590db156f85832ac6aca0937338.jpg)

SNDW function is not enabled. The readiness of SNDW devices and drivers are low.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+3.3V</td></tr><tr><td>3</td><td>+1.8V</td><td>4</td><td>SNDW_CLK</td></tr><tr><td>5</td><td>SNDW_DATA</td><td>6</td><td>GND</td></tr></table>

# 5.12. Ethernet NBASE-T

2-in-1 Ethernet Connector at Rear I/O

ETH\_0: NBASET\_0 assigned (upper one)

ETH\_1: NBASET\_1 assigned (lower one)

Up to 10GbE, depending on the module specifications

![The diagram features a central vertical rectangular device, resembling a network switch, containing two black RJ45 ports stacked vertically.\n\n**Labeled Blocks:**\n*   **Left:** Text reading 'Link Speed'.\n*   **Center:** A grey device with two black ports. Above the top port and below the bottom port are indicator lights: a green triangle on the left and an orange rectangle on the right for each section.\n*   **Right:** Text reading 'Link Status & Activity'.\n\n**Connections:**\n*   **Green Lines:** Two green lines connect the 'Link Speed' text to the green indicator lights on the left side of the central device.\n*   **Yellow Lines:** Two yellow lines connect the 'Link Status & Activity' text to the orange indicator lights on the right side of the central device.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/bd7619cbf39200d60a776b455b75267b2d76450349385807acf1867179ff5b07.jpg)

<table><tr><td>LED Function</td><td>LED Color</td><td>LED State</td><td>Description</td></tr><tr><td rowspan="3">Status &amp; Activity</td><td rowspan="3">Orange</td><td>Off</td><td>No Link</td></tr><tr><td>Steady On</td><td>Link established, no activity detected</td></tr><tr><td>Blinking</td><td>Link established, activity detected</td></tr><tr><td rowspan="3">Speed</td><td rowspan="3">Green/Orange</td><td>Off</td><td>10M</td></tr><tr><td>Green</td><td>100M/1G link speed</td></tr><tr><td>Orange</td><td>Max. link speed(2.5GbE based on current existing module specification)</td></tr></table>

# 5.13. USB

USB Type-A / Type-C Combo connector at Rear I/O

• USBA\_SS6: 1x USB3.x/2.0 assigned, Type-A connector, up to 10Gbit/s
• USBC\_SS2&3: USB4\_0 (USB4 port 0) assigned, Type-C connector, USB4 capable

![The image displays a vertical illustration of a piece of electronic equipment, resembling a reel-to-reel tape recorder. The top section features a dark grey panel with a bright blue horizontal bar, likely representing a VU meter or tape counter, situated above two thin horizontal lines. The main body is light grey. The bottom section contains a window revealing a tape mechanism, depicted as a black shape with a white strip of tape wrapped around it, marked by small blue rectangles. The entire object is outlined in black with a flat, digital art style.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/d6e5363ef0fcd229d2eca5f2c4ecf19efae9537be4d70d676f2572d047d5723d.jpg)

USBA\_SS6 consists of SS lane 6 (USB3.x SSTX/RX pairs, sometimes called as USB3.x port 1), USB3 (USB2.0 D+/D- from port 3)

USBC\_SS2&3 consists of SS lane 2-3 (SSTX/RX pairs, sometimes called as USB4 port 0), USB0 (USB2.0 D+/D- from port 0) and sidebands

USB4 at Type-C depends on module specification (HW/BIOS configuration)

USB Type-A / Type-C Combo connector at Rear I/O

• USBA\_SS7: 1x USB3.x/2.0 assigned, Type-A connector, up to 10Gbit/s
• USBC\_SS4&5: USB4\_1 (USB4 port 1) assigned, Type-C connector, USB4 capable

![This image displays a vertical, rectangular icon resembling a computer tower or hardware device. The top section features a dark grey border enclosing a light grey interior. Inside this upper area, a bright blue horizontal bar is positioned near the top edge, with three small, light blue horizontal dashes situated below it. The bottom section consists of a separate rectangular area with a thick dark grey border, containing a horizontal row of dashes or a segmented bar in light grey, resembling a floppy disk drive slot.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/ce44bd9bd46d9763be041fafc827a133c50b7ebf4886e07158db458c545e4ad6.jpg)

USBA\_SS7 consists of SS lane 7 (USB3.x SSTX/RX pairs, sometimes called as USB3.x port 0), USB5 (USB2.0 D+/D- from port 5)

USBC\_SS4&5 consists of SS lane 4-5 (SSTX/RX pairs, sometimes called as USB4 port 1), USB1 (USB2.0 D+/D- from port 1) and sidebands

USB4 at Type-C depends on module specification (HW/BIOS configuration)

USB Type-A 2-in-1 connector at Rear I/O

• USB\_2: USB2 (USB2.0 port 2) assigned, Type-A connector, up to USB2.0 speed
• USB\_4: USB4 (USB2.0 port 4) assigned, Type-A connector, up to USB2.0 speed

![The image displays a vertical stack of two identical horizontal rectangular shapes against a grey background. Each shape is outlined in black and contains a dark horizontal band near the top. Below this band, three small, light blue rectangular shapes are arranged in a row. There is no text in the image.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/45bcd74acdbac9189b381c8c70a2b871a885e77fa8a3a6649e2e8983ae8d6561.jpg)

F\_2XUSB\_2.0: 2x USB2.0 from USB6 and USB7 (USB2.0 port 6 and port 7)

Front panel usage, 9-pin, 2.54 mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+5V</td><td>2</td><td>+5V</td></tr><tr><td>3</td><td>USB7_N</td><td>4</td><td>USB6_N</td></tr><tr><td>5</td><td>USB7_P</td><td>6</td><td>USB6_P</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td></td><td></td></tr></table>

![The image displays a horizontal row of black capital letter 'B' characters against a white background. There are four complete 'B's visible, followed by a fifth 'B' that is partially cut off on the right edge.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/e53748a76561c8cd769cb5015ab435ce1cdaf17730ca8fe13f127e474875a32e.jpg)

# 5.14. GPIO

GPIO: GPIO 0-11 signal assigned

14-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>1.8V</td><td>2</td><td>GPIO_06</td></tr><tr><td>3</td><td>GPIO_00</td><td>4</td><td>GPIO_07</td></tr><tr><td>5</td><td>GPIO_01</td><td>6</td><td>GPIO_08</td></tr><tr><td>7</td><td>GPIO_02</td><td>8</td><td>GPIO_09</td></tr><tr><td>9</td><td>GPIO_03</td><td>10</td><td>GPIO_10</td></tr><tr><td>11</td><td>GPIO_04</td><td>12</td><td>GPIO_11</td></tr><tr><td>13</td><td>GPIO_05</td><td>14</td><td>GND</td></tr></table>

![The image shows a horizontal row of eight identical black shapes against a white background. Each shape is a vertically oriented rounded rectangle (or capsule). Inside each black shape are three small white dots arranged in a vertical column. The shapes are separated by thin white gaps. A thick black horizontal bar runs across the very top edge of the image.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/c9b68a71fb219d8bf19cbc91d7964d1d8241a079d8966ed320609b631f209f5f.jpg)

# 5.15. I2C

I2C0: I2C0 bus assigned, 4-pin, 2.54mm pitch

I2C1: I2C1 bus assigned, 4-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+1.8V</td><td>2</td><td>I2C_DATA</td></tr><tr><td>3</td><td>I2C_CLK</td><td>4</td><td>GND</td></tr></table>

![The image displays a black, horizontal, pill-shaped object (a rectangle with fully rounded ends) centered on a white background. Inside the black shape, there are four small white dots arranged in a horizontal row.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/7930d011db4a68d70296ec598d64c5069c7b0e00d52299d0f327bd6a378d9a5f.jpg)

# 5.16. UART / COM

COM1\_SER0: UART0 signal assigned, 2.0mm pitch

COM2\_SER1: UART1 signal assigned, 2.0mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>N.C</td><td>2</td><td>N.C</td></tr><tr><td>3</td><td>UART_RX</td><td>4</td><td>UART_RTS</td></tr><tr><td>5</td><td>UART_TX</td><td>6</td><td>UART_CTS</td></tr><tr><td>7</td><td>N.C</td><td>8</td><td>N.C</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>N.C</td></tr></table>

![The image displays a black rectangle with a thin white border. Inside the black area, there are twelve white dots arranged in three rows and four columns. A small sliver of white is visible along the very top edge.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/75f7d8bc0cfb42c948e45a7504ff878b09db9dc75ea2f1b49b174bc139d23eed.jpg)

COM3: UART from Super I/O signal assigned, 2.0mm pitch

COM4: UART from Super I/O signal assigned, 2.0mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DCD</td><td>2</td><td>DSR</td></tr><tr><td>3</td><td>RX</td><td>4</td><td>RTS</td></tr><tr><td>5</td><td>TX</td><td>6</td><td>CTS</td></tr><tr><td>7</td><td>DTR</td><td>8</td><td>RI</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>N.C</td></tr></table>

![The image displays a black rectangular area surrounded by a white border. Inside the black area, near the top, is a thin white horizontal rectangle. Below this rectangle, there are two rows of six white circular dots each, arranged in a grid pattern.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/68f67373a044145919bbe4d6d300f396748b8320b561b29c9ef436fcf4965b16.jpg)

MODE0/MODE1: selection of RS232/RS485/RS422 mode for COM3

<table><tr><td>Mode</td><td>MODE1</td><td>MODE0</td></tr><tr><td>RS232 (default)</td><td>2-3</td><td>1-2</td></tr><tr><td>RS485</td><td>1-2</td><td>2-3</td></tr><tr><td>RS422</td><td>1-2</td><td>1-2</td></tr></table>

![The image displays a close-up of a remote control interface. On the left, there is a light gray section with rounded corners containing a white square icon (a square outline with a smaller square inside). To the right, a black section contains three white icons arranged horizontally: a double left-pointing arrow (rewind), a single right-pointing triangle (play), and a double right-pointing arrow (fast forward).](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/dd070a1a2dd0aaf144ec48ce09bcd2ba97290d3097c96eaa223631bf818a195c.jpg)

# 5.17. eSPI Debug Connector

ESPI: for eSPI debugging connection purpose

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>eSPI_CLK</td><td>2</td><td>GND</td></tr><tr><td>3</td><td>eSPI_CS0</td><td>4</td><td>N.C</td></tr><tr><td>5</td><td>CB_RST</td><td>6</td><td>+5V</td></tr><tr><td>7</td><td>eSPI_IO_3</td><td>8</td><td>eSPI_IO_2</td></tr><tr><td>9</td><td>+ 3.3VSB</td><td>10</td><td>eSPI_IO_1</td></tr><tr><td>11</td><td>eSPI_IO_0</td><td>12</td><td>eSPI_ALERT0#</td></tr><tr><td>13</td><td>SMB_CK</td><td>14</td><td>SMB_DAT</td></tr><tr><td>15</td><td>+1.8VSB</td><td>16</td><td>eSPI_CS1</td></tr><tr><td>17</td><td>eSPI_RST#</td><td>18</td><td>N.C</td></tr><tr><td>19</td><td>+5V</td><td>20</td><td>eSPI_ALEART1#</td></tr></table>

![The image displays a vertical column of ten identical, light-grey rounded rectangles stacked one above the other. Each rectangle contains two smaller, vertically aligned squares inside it. In the first nine rectangles from the top, both squares are empty (white). In the bottommost rectangle, the top square is empty, while the bottom square is filled with solid black.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/dc0b329a344f5624280c3a58c6f371ef785370e2104b2181d4905089ee33b41f.jpg)

# 5.18. SMB

SMBUS: SMBus assigned, 4-pin, 2.54mm pitch

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+1.8V</td><td>2</td><td>SMB_DATA</td></tr><tr><td>3</td><td>SMB_CLK</td><td>4</td><td>GND</td></tr></table>

![The image displays a black, horizontally oriented pill-shaped rectangle with rounded corners set against a white background. Inside the black shape, there are four small white dots arranged in an evenly spaced horizontal row.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/7966570c3482f0fa4dc11c1a36cad7633a5cbad57b6bb62b1aa114fc397ed051.jpg)

# 5.19. FAN Connector

2nd\_FAN (or named as MODULE\_FAN): Secondary FAN control signals from module assigned, 4-pin

It can be used for module FAN control or can be used for system Fan control. The FAN table is stored in the module’s EC controller, and the default FAN table is configured for module FAN usage. Refer to the module’s user manual for detail.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN</td></tr><tr><td>3</td><td>SENSE_FAN</td></tr><tr><td>4</td><td>PWMOUT_FAN</td></tr></table>

![This is a black and white line drawing of a vertical rectangle. Inside the rectangle, a vertical line divides the space into a left and right section. The left section contains a tall rectangular shape with a smaller rectangular shape inside it near the top. The right section contains a column of four small squares stacked vertically.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/6466d177218dc7e634f7cbe22318eae4f49679bceb61c28ce1d1014f1f971b66.jpg)

SYS\_FAN0: FAN control signals from Super I/O assigned, 4-pin

ESPI\_CS1 need be enabled at module’s BIOS setting to make Super I/O works

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN0</td></tr><tr><td>3</td><td>SENSE_FAN0</td></tr><tr><td>4</td><td>PWMOUT_FAN0</td></tr></table>

![The image is a black-and-white line drawing of a rectangular object, likely a schematic or diagram. It is divided vertically into sections. On the far left, there is a narrow vertical strip. Next to it, a section contains a horizontal rectangle near the top. To the right, a larger vertical section contains a column of four squares: a square at the very top, followed by three smaller squares stacked vertically below it.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/ddadcdb466fb1d9efea4a0f8b55e5793e11c3d232f442f23159f1f2371e832d2.jpg)

SYS\_FAN1: FAN control signals from Super I/O assigned, 4-pin

ESPI\_CS1 need be enabled at module’s BIOS setting to make Super I/O works

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>+12V_5V_FAN1</td></tr><tr><td>3</td><td>SENSE_FAN1</td></tr><tr><td>4</td><td>PWMOUT_FAN1</td></tr></table>

![The image is a simple black-and-white line drawing containing no text. It depicts a vertical rectangular structure divided into sections. On the left, there is a vertical strip next to a rectangular area containing a horizontal rectangle. To the right, a tall column features four small squares stacked vertically; the top square is filled with solid black, while the three squares beneath it are empty white squares with black outlines.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/03d35b66108d6aef8fe409358f43ef9f072c24382757559ba409eea7dc154483.jpg)

# 5.20. Carrier BIOS

A SPI BIOS Socket on carrier board

• Allow boot-up from the carrier with proper jumper settings.

![A black and white line drawing of a mechanical retaining ring, commonly known as a snap ring. The ring is oriented horizontally with a central, solid black curved body connecting two outer ends. The left and right ends are depicted as rectangular sections filled with vertical parallel lines, resembling serrated teeth. A vertical line runs down the center of the black body.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/7b4209713a1d2f4ff1c82a2aa36843f8e99918f3e546bd6df357244d2812cd15.jpg)

BSEL0/BSEL1/BSEL2: Jumpers for module boot-up selection

<table><tr><td>BESL2</td><td>BSEL1</td><td>BSEL0</td><td>BIOS Boot Select</td></tr><tr><td>1-2</td><td>1-2</td><td>1-2</td><td>Module SPI0/SPI1 (default)</td></tr><tr><td>1-2</td><td>1-2</td><td>2-3</td><td>Carrier SPI0/Module SPI1</td></tr><tr><td>1-2</td><td>2-3</td><td>1-2</td><td>Module SPI0/Carrier SPI1</td></tr></table>

![The image displays a vertical, rectangular graphic with a rounded bottom. The upper two-thirds of the shape are black and contain two small white dots arranged vertically. The bottom third is light gray and features a small black square with a white dot in the center. The overall design resembles a minimalist face or a battery icon.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/bf80b62b60af80e9d31bf0a97eb28874ac3cb63801e360631a70e5f2ed203568.jpg)

Note: Boot from Carrier SPI BIOS ROM will require specific BIOS firmware. The SPI ROM inside the socket is without any firmware

# 5.21. Front Panel Control

F\_MISC: Power Button, Reset Button, HDD LED, Power LED for front panel header

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>19</td><td>N.C</td><td>20</td><td>N.C</td></tr><tr><td>17</td><td>N.C</td><td>18</td><td>BUZZER</td></tr><tr><td>15</td><td>N.C</td><td>16</td><td>N.C</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>N.C</td></tr><tr><td>11</td><td>+5VSB</td><td>12</td><td>+5V</td></tr><tr><td>9</td><td>N.C</td><td>10</td><td>N.C</td></tr><tr><td>7</td><td>SYS_RESET#</td><td>8</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>PWR_BTN#</td></tr><tr><td>3</td><td>HDD_LED_N</td><td>4</td><td>GND</td></tr><tr><td>1</td><td>HDD_LED_P</td><td>2</td><td>+5V</td></tr></table>

![The image shows a grid of twelve checkboxes arranged in two columns and six rows. The bottom checkbox in the left column is checked, indicated by a small black square inside it. All other eleven checkboxes are empty.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/20dee7f8201e024f1c17e821af136b6c52a3a67f23208c9231164d942af6305d.jpg)

# 5.22. Other Jumpers

JP5: clear CMOS.

To clear CMOS, shut down the power and short pin 2 and pin 3 (short VBAT to ground)

<table><tr><td>Jumper</td><td>Clear CMOS</td></tr><tr><td>1-2</td><td>Normal (default)</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr></table>

![The image displays a stylized, vertical graphic resembling a simplified face or battery icon. It is a rounded rectangle divided horizontally into two sections. The upper section is black and contains two small white squares arranged vertically. The lower section is light grey and contains a single white square centered within it.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/66fb7d52a8a4f476d3cf245f44f931e3bcbaa65a97e3c5462f30f085564bcc7f.jpg)

JP3: Selection of Super I/O address

<table><tr><td>Jumper</td><td>Selection of Super I/O address</td></tr><tr><td>1-2</td><td>4Eh</td></tr><tr><td>2-3</td><td>2Eh (default)</td></tr></table>

![The image displays a vertical rectangular graphic divided into two distinct sections. The upper section is black and features three small white squares arranged vertically in a column. The lower section is a light gray or off-white rounded rectangle containing a single small black square centered at the bottom.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/d2ee71d9c7c215141f3c35cc8d11a375e593606f2169f8890d839094c3787a41.jpg)

JP45: Module Type detection

<table><tr><td>Jumper</td><td>Status</td></tr><tr><td>1-2</td><td>Detect (default)</td></tr><tr><td>2-3</td><td>Undetect</td></tr></table>

![The image displays a vertical, capsule-shaped object. The upper section is black and contains two small white squares stacked vertically. The lower section is light grey and contains a single white square centered horizontally.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/dac32a793b8c790239494cf2c0b5ea77214b95e04f45dabf6bc4f1c18a16c931.jpg)

The functionality of Module Type detection requires the carrier board to implement combinatorial logic that monitors the module TYPE pins and keeps the power off if an incompatible module pinout type is detected.

# 5.23. Power Connectors

The COM-HPC Mini module requires only a single power rail input and does not need a standby power rail, as defined by the PICMG specification.

To make power sourcing more convenient and straightforward, the power connectors are designed based on the ATX power style and require only the main power rail.

# ATX\_24: 24-Pin Power Connector

Connect the ATX 24-pin (or 20-pin) connector to supply power to the COM-HPC Mini Base-ATX carrier and the COM-HPC Mini module.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>+3.3V (not used)</td><td>13</td><td>+3.3V (not used)</td></tr><tr><td>2</td><td>+3.3V (not used)</td><td>14</td><td>-12V (not used)</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>GND</td></tr><tr><td>4</td><td>+5V (not used)</td><td>16</td><td>PWR_ON</td></tr><tr><td>5</td><td>GND</td><td>17</td><td>GND</td></tr><tr><td>6</td><td>+5V (not used)</td><td>18</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>19</td><td>GND</td></tr><tr><td>8</td><td>PWR_GOOD</td><td>20</td><td>-5V (not used)</td></tr><tr><td>9</td><td>+5VSB (not used)</td><td>21</td><td>+5V (not used)</td></tr><tr><td>10</td><td>+12V</td><td>22</td><td>+5V (not used)</td></tr><tr><td>11</td><td>+12V</td><td>23</td><td>+5V (not used)</td></tr></table>

![Simple line drawing of a door with multiple compartments and a door handle (no text or symbols)](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/d088f05a3f3bc63e82b7349753d6d06e409d2e2dbb2f78703a3993fefb0882e4.jpg)

<table><tr><td>12</td><td>+3.3V (not used)</td><td>24</td><td>GND</td></tr></table>

3.3V, 5V, 5VSB are not used even although it is connected

In addition, specific logic design on the carrier board will always ensure that PWR\_ON and PWR\_GOOD are enabled.

# ATX\_4: 4-Pin Power Connector

Connect the ATX 12V 4-pin connector to supply power to the COM-HPC Mini Base-ATX carrier and the COM-HPC Mini module

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>+12V</td></tr><tr><td>4</td><td>+12V</td></tr></table>

![The image displays a black-and-white line drawing of a rectangular layout, likely a floor plan. It is divided into four quadrants by a central vertical line and a central horizontal line.\n\n*   **Left Side:** The left column consists of two identical squares stacked vertically.\n*   **Right Side:** The right column consists of two squares stacked vertically. Each square contains a quarter-circle arc in the corner adjacent to the central dividing line (the top square has the arc in the bottom-left corner, and the bottom square has it in the top-left corner).\n*   **Right Edge:** There is a small rectangular protrusion or tab extending from the right edge, positioned between the upper and lower right squares.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/ca29ff0edca550621ff5c2170adf36faec2c0aba90720f0e19bf88563411c9f8.jpg)

JP1: selection of AT source

<table><tr><td>Jumper</td><td>Module 5VSBY SOURCE</td></tr><tr><td>3-4</td><td>AT mode from PSU (default)</td></tr><tr><td>1-2</td><td>AT mode from Smart Battery (default)</td></tr></table>

![The image displays a horizontal rectangular graphic divided into two sections. The left section is black and contains two small white squares arranged side-by-side. The right section is light grey, has a rounded right edge, and contains two small white squares arranged side-by-side. There is no text visible in the image.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/6f9a80c57d5f928513db1641f60374c19a958e1567bdefb27f5944680b9abce9.jpg)

![A red outline icon depicting a document or page with a curled top-right corner. Inside the document shape, there are two horizontal red lines representing text.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/7dccef72aef626ded878171970befe3a5255047773e993afdf3adc6c8e771b58.jpg)

Note: JP1 is for the ATX power source. JP1 sets PS\_ON enabled at all times. It is recommended to keep the default jumper setting unchanged.

# 6. Carrier BIOS

The COM-HPC Mini Base-ATX supports a Carrier BIOS, using the Boot Serial Peripheral Interface (SPI) for COM-HPC modules.

Secondary BIOS solutions can be used as an alternative to the on-module BIOS and provide support for the following:

• Testing new BIOS versions
• Development of firmware modifications
Recovery, in case the soldered BIOS on the module is corrupted (optional)

To use the BIOS on the module:

short pins 1-2 on BESL2, BESL1, BESL0; reference section 5.20

To use the BIOS on the carrier board:

short pins 2-3 on BESL0, and keep pin 1-2 on BESL2, BESL1; reference section 5.20

Make sure that the secondary BIOS flash chip is properly installed into the Carrier BIOS socket before adjusting the BOOT BIOS selection.

![BSEL0\nBSEL2\nSYS_FAN1 MODULE_FAN\nBattery\nJP5\nJP48\nJP47\nI/O status indicators\n-2 Enable\n-2-3 Disable\nJP48 RTC discharge\n-2 Short\n-2-3 Open\nCarrier_BIOS](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/b47363bad9a7c45a451f2c6d93811e6d093c366c5fc3962bb4671087bf184e09.jpg)

![The image displays a red icon resembling a document or note with a folded bottom-right corner. Inside the white interior, there are two horizontal red lines stacked vertically.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/81cd550147f76da6c3a50b2d7e7838b3fdc3cba0555644d440b58bc92b816989.jpg)

Note: Booting from the Carrier SPI BIOS ROM requires specific BIOS firmware. The SPI ROM inside the socket does not contain any firmware by default.

# 7. Switches, POST, and LEDs

# 7.1. Control Switches

<table><tr><td>Button</td><td>Description</td></tr><tr><td>PWR_BTN</td><td>Power Button</td></tr><tr><td>RST_BTN</td><td>Reset Button</td></tr><tr><td>SLP_BTN</td><td>Sleep Button</td></tr><tr><td>LID_BTN</td><td>Lid Button</td></tr></table>

Both the SLP and LID buttons support COM-HPC modules for ACPI power management behavior setting in an OS environment. (functionality also depends on the module specifications, especially the module’s BIOS configuration).

# 7.2. Post Display and LEDs

An I2C-based POST display is added for debugging. The two 7-SEG LEDs show the actual POST data.

A row of mini-LEDs near the POST display indicates the following:

<table><tr><td>LED</td><td>Description</td></tr><tr><td>5VSB</td><td>24+4-pin power attached on standby or active (no function)</td></tr><tr><td>S3</td><td>Indicates S3 status</td></tr><tr><td>PWR_ON</td><td>Indicates power on</td></tr><tr><td>HDD</td><td>Indicates hard drive activity (at M.2 M-key)</td></tr><tr><td>WDT</td><td>Indicates WDT (watchdog timer) activity</td></tr></table>

![SYSB\nS3\nPWR_ON\nHDD\nWDT\nF_MISC\nPWR_BTN\n10\n8.0\n8.0](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/b5df4f69e90803eb1ab33ecb861d33152908b25170d108e23e42340b015e0112.jpg)

# 8. Power Input Connection

COM-HPC mini module only requires single power rail input, check section 5.23 as reference

# 8.1. 12V Power Input at 24+4 Pin Power Connectors

For the standard 12V power input usage: This is used to connect an ATX power supply that provides only the 12V power rail.

It supplies 12V to the COM-HPC Mini module. The system will not power on unless the 4-pin connector is connected.
Power components on the carrier board convert the 12V input to other required power rails for carrier board operation (the carrier uses both 12V and other generated power rails).

![Feed 12V\nATX_24\nATX_4\nJP41\nJP31\nMODULE_FAN](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/67d7cffbf7c3f512ce6930bf5e76609b0187a40f7f59e019ac4cd77268ba24c2.jpg)

![The image displays a red icon on a white background. The icon resembles a square piece of paper or a document with a folded top-right corner. Inside the shape, there are two horizontal red lines centered vertically, resembling a block of text.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/9a896bdafefe735514eaed20b63d2e22e0bc898da1d818213d960ab0ff2ad891.jpg)

Note: Always powers on by default. It means the system will automatically power on once the mechanical switch of the power supply is switchedon.

# 8.2. 8-20V Power Input at 4-Pin Power Connectors

Connecting a single rail (8–20V) power source to the 4-pin connector is required.

It will supply 8-20V to the COM-HPC Mini module.

Power components located on the carrier board convert this voltage to other power rails needed for carrier board operation.

The carrier board supports single-rail wide-range DC power input (8–20V) through a standard 4-pin ATX-style power connector.

![Wide Range Power Input\nno connection\nATX_24\nATX_4\nJ346\nJ346\nJ346\nMODULE_FAN](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/400a01797f4d93bb720a2eead53e01f296d033d403b745ecd68cf0cdbcf524fc.jpg)

![The image displays a red icon resembling a document or file. It features a square outline with a folded bottom-right corner. Inside the shape, there are three horizontal red lines stacked vertically, representing text or a list.](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/8e767e6cf81df66513ea13dad7bf44648aa42b1874e75db0fa9ce3fe51fc95f2.jpg)

Note: Only the +12V and GND pins are used — the +5V, +3.3V, and other ATX rails are not connected internally. This connector is repurposed to accept a wide-range DC input.
[🔗 Link to the original document](.com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626/com-hpc-mini-base-atx-manual-50m-77110-1000-03-20250626.pdf)
