# COM-HPC-sIDH/R User’s Guide intel ![Close-up of a COM-HPC processor on a circuit board with visible components and gold contacts (no readable text or symbols)](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/0d826e1d79a3c448adb3021333ed47ba8f5b9ed57e5e0d362333ea1dce61d721.jpg) COM+HPC Revision: Rev. 0.2 Preliminary Date: 2024-08-26 Part Number: 50M-73103-1000 Revision History

Revision	Description	Date	Author
0.1	Preliminary release	2023-05-05	CC
0.2	SKUs added	2024-08-26	AL

# Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![The image displays a standard warning sign: a yellow equilateral triangle with a thick black border. Centered inside the triangle is a black exclamation point.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/db05578b99a30253dc61d3c5980236e649a73e5b3d7094c8c38e53a1f0971b55.jpg) California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. ![A black line drawing of a pedal bin is crossed out with a large 'X'. A solid black rectangle obscures the area below the bin.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/49e77afb3e65d9b91d4b1af757f830a7c40ecc99a110431186fd631c33b81a3c.jpg) # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. # Copyright © 2024 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image displays a red icon resembling a document or memo pad with a folded top-right corner. Inside the shape are two horizontal red lines, suggesting text or a list.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/7211dd19002ade1cb1aefaab6e26819b85c00b6be3abb358cfd218b4bb0bd0c8.jpg) Note: This information adds clarity or specifics to text and illustrations. ![The image displays a low-resolution, pixelated graphic of a yellow triangular warning sign. The triangle has a thick black outline and points upward. Centered inside the yellow shape is a black exclamation point. The background is white.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/c198b4bf2da549314c5d175ae4df0b0965793526cc93fd4a0390f16b65733048.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image displays a red triangular warning sign with a white exclamation mark in the center.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/6a8699ea66388cdccdf0b48525ee3d6554f18b658de564e506fbb8a4f60d7ba2.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Getting Service Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5706 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. # Table of Contents Revision History .. Preface . List of Figures ... .10 1. Introduction .. .11 2. Specifications.. .12 2.1. Core System... .12 2.2. Expansion Busses . ... 13 2.3. Ethernet KR... ... 14 2.4. Ethernet NBASE-T.. ... 15 2.5. Multi I/O and Storage .. ..15 2.6. Trusted Platform Module (TPM)... ..17 2.7. SEMA Board controller... ... 17 2.8. Remote Management & Module Management Controller (MMC).. ..17 ... 18 2.10. Power.... ... 18 2.11. Mechanical and Environmental... ... 18 3. Block Diagram... ..20 4. Pinout and Signal Descriptions .... ...21 4.1. Pin Summary... ..21 4.2. Signal Terminology Descriptions ... ... 28 4.3. Signal Descriptions on J1/J2 Connectors .. ..29 4.3.1 Ethernet KR . ..29 4.3.2 NBASE-T Ethernet... ..31 4.3.3 PCI Express .. ..33 4.3.4 USB.... .... 40 4.3.5 SATA .. .... 42 4.3.6 Asynchronous Serial Port.. ..43 4.3.7 I2C .. .... 43 4.3.8 eSPI .. .... 44 4.3.9 Boot SPI (BIOS ONLY) and Boot Select.. ..44 4.3.10 Port 80 Support on USB\_PD I2C Bus .. ... 45 4.3.11 IPMB .. .... 46 4.3.12 General Purpose SPI .. .... 46 4.3.13 Power & System Management..... ..47 4.3.14 Rapid Shutdown... .... 48 4.3.15 Thermal Protection... .... 48 4.3.16 SMBus .. .... 49 4.3.17 General Purpose Input Outputs.. ..49 4.3.18 Module Type Definition... ..50 4.3.19 Miscellaneous Signals ... ..51 4.3.20 Power and Ground . ..52 5. Additional Features ...... ...53 5.1 Debug Connector (40-pin connector)... ..55 5.2 Status LEDs... ..56 5.3 Exception Codes.. ..57 5.4 Fan Connector... ..58 5.5 BIOS Default Reset . ..59 5.6 BIOS Boot Select . ..60 5.7 MIPI 60 Debug Header .. ..61 6. System Resources ... ..63 6.1 System Memory Map ... ..63 6.2 I/O Map ... ..64 6.3 Interrupt Request (IRQ) Lines .. ..65 6.4 PCI Configuration Space Map ... ..66 6.5 PCI Interrupt Routing Map ... ..70 6.6 SMBus Address Table.. ..71 7. BIOS Setup... ..72 7.1 Menu Structure... ..72 8. BIOS Checkpoints, Beep Codes .... ...74 9. Software Support .... ...76 9.1. Windows Server 2019 64-bit .. ..76 9.2. Windows 10 IoT Enterprise 64-bit ... ..76 9.3. Yocto Linux 64-bit (TBC)... ..76 10. Mechanical... ..77 11.Thermal.. ..78 11.1. Thermal Solutions.. ..78 11.1.1 Heatspreader: HTS... ..78 11.1.2 Heatsink: THS-BL.. ..79 11.1.3 Heatsink with Fan: THSF... .... 80 11.1.4 Heatsink with Fan: THSF-BL-S ... ..81 # List of Figures Figure 1 – Module function diagram... ...20 Figure 2 - Module rear side row and pin numbering ....... ...21 Figure 3 – Module feature locations (front).... ..53 Figure 4 – Module feature locations (bottom) .... ...54 Figure 5 – Module mechanical dimensions ..... .77 Figure 6 – Heatspreader: HTS....... ...78 Figure 7 – Heatsink: THS-BL.. ..79 Figure 8 – Heatsink with Fan: THSF..... ..80 Figure 9 – Heatsink with Fan: THSF-BL-S... ..81 # 1. Introduction The COM-HPC-sIDH is a Server Type COM-HPC Size D module based on Intel® Xeon® D-2700 processors (formerly “Ice Lake-D HCC”). The processor puts an emphasis on longevity and industrial-class reliability, offers up to 20 cores at 3.1GHz boost frequency, and features AVX512-VNNI (Vector Neural Network Instructions) that deliver accelerated AI inferencing performance. Typical industries in need of such high performance, low power characteristics include industrial automation and control, medical ultra sound, image processing and analysis, high-speed video encoding and streaming, predictive traffic analysis, and multi-camera-based AI. The COM-HPC-sIDH has up to four DIMM sockets supporting up to 256GB (4x 64GB) of DDR4 RDIMM memory, or even higher with LRDIMM. It provides a memory frequency of up to 3200 MT/s, dependent on system configuration. Selected SKUs features industrial class reliability with extended temperature range operability. Combined with ultra-low latency-focused Intel® Time Coordinated Computing (Intel® TCC) technology, COM-HPC-sIDH is well suited for mission critical, hard real-time, and rugged solutions. The integrated high speed Ethernet controller inside Intel® Xeon® D-2700 processors provides up to 8x 10G networking with selected PHY on carrier for SFP+ or 10GBASE-T feature, or 4x 25G based on selected PHY on carrier for SFP+, or 10G/25G in KR backplane usage and even up to 40G/50G/100G (TBC) in KR backplane usage. It also includes an onboard 2.5Gigabit Ethernet port with optional Time Sensitive Network (TSN) support. An optional IPMB via MMC (module management controller, located on module) and a dedicated PCIe lane (PCIe\_BMC) are also offered. By connecting these IPMB, dedicated PCIe lane and other management buses, such as eSPI, UART, to the carrier board BMC (for example, AST2500), it allows for outof-band management. Inputs/outputs provided include up to two PCIe Gen4 x16 and another two PCIe Gen3 x8 lanes that can be used for AI accelerator and NVMe SSD, four USB 3.0/2.0 ports, two SATA 6Gb/s ports, and 12x GPIO pins. TPM chip is equipped for security-related usage. Optional onboard eMMC is offered by project basis. Support for SMBus, two I 2 C. is also available The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor, and watchdog timer. # 2. Specifications # 2.1. Core System # CPU Intel® Xeon® D-2700 Processor (formerly “Ice Lake-D HCC”) • Xeon(R) D-2896TER 2.0/3.2GHz 30MB 110W (100G Ethernet bandwidth (eTEMP) • Xeon(R) D-2899NT, 2.2/3.1GHz, 30MB, 22C/44T, 135W (50G Ethernet bandwidth) (Intel QAT) • Intel® Xeon® D-2796TE, 2.0/3.1GHz, 30MB, 20C/40T, 118W (100G Ethernet bandwidth) (eTemp) • Intel® Xeon® D-2775TE, 2.0/3.1GHz, 25MB, 16C/32T, 100W (100G Ethernet bandwidth) (eTemp) • Intel® Xeon® D-2752TER, 1.8/2.8GHz, 20MB, 12C/24T, 77W (50G Ethernet bandwidth) (eTemp) • Intel® Xeon® D-2733NT, 2.1/3.2GHz, 15MB, 8C/16T, 80W (50G Ethernet bandwidth) (Intel QAT) • Intel® Xeon® D-2712T, 1.9/3.0GHz, 15MB, 4C/8T, 65W (50G Ethernet bandwidth) ![The image displays a document icon featuring a white background with a thick red outline. The bottom-right corner of the document is folded inward (a 'dog-ear'). Inside the document area, there are two horizontal red lines centered vertically.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/57143d3b781ac4347f1ee432bdefd27149af11eaefe3314780b2b9ba9c68dbba.jpg) Note: Other non-IOTG SKU not listed may be supported by project basis. Please contact our ADLINK local representative. # Memory Up to 256GB (4x 64GB) DDR4 RDIMM in four DIMM sockets (up to 512 GB by 4x 128GB configuration at LRDIMM, TBC) Up to 3200 MT/s for D-2899NT Up to 2933 MT/s for D-2896TER/D-2796TE/D-2775TE, 2667 MT/s for D-2752TER/D-2733NT/D-2712T1 DIMM per channel architecture for maximum performance # Embedded BIOS AMI Aptio V UEFI with CMOS backup in 64 (or 32, TBC) MB SPI BIOS, dual BIOS by build option # 2.2. Expansion Busses 1 PCI Express x16 Gen4: Lane 16-31 (configurable to 1 x16, 2 x8 or 4 x4) 1 PCI Express x16 Gen4: Lane 32-47 (configurable to 1 x16, 2 x8 or 4 x4) 1 PCI Express x8 Gen3: Lane 0-7 (configurable to 1 x8, 2 x4, 4 x2 or 4 x1. x1 usage at Lane 0, 2, 4, 6) 1 PCI Express x8 Gen3: Lane 8-15 (configurable to 1 x8, 2 x4, 4 x2 or 4 x1. x1 usage at Lane 8, 10, 12, 14) Additional 1 PCI Express x1 Gen3 (PCIe\_BMC) is used for connecting to carrier board BMC ![The image shows a red icon representing a document or file. It is a rounded rectangular outline with the bottom-right corner folded upwards. Inside the outline, there are two horizontal red lines centered near the top.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/074e3278ed2535e7a245bca220440a0f2e122177996e9f76c710329d44283857.jpg) Note: Gen4 support dependent on carrier design. # 4 PCI Express Reference Clock: PCIe\_REFCLK0\_LO: used for PCIe Lane 0-7 and PCIe\_BMC recommended PCIe\_REFCLK0\_HI: used for PCIe Lane 8-15 recommended PCIe\_REFCLK1: used for PCIe Lane 16-31 recommended PCIe\_REFCLK2: used for PCIe Lane 32-47 recommended ![A red icon on a white background depicting a stylized document or page with a folded top-right corner. Inside the page shape are two horizontal red lines, resembling text or a list.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/6b099553e5c4d114aad257087370b6fde299c4f61d6cb3cae890063630e0e498.jpg) Note: PCIe 8-11 should be used for the first NVMe instance and PCIe 12-15 should be used for the second NMVe instance. These are recommended by COM-HPC specifications. Other: SMBus (system), 2x I2C (user, I2C\_0, I2C\_1, I2C\_0 offers ALERT#), eSPI bus # 2.3. Ethernet KR # Ethernet Controller Integrated on SoC Up to 8x Ethernet KR interfaces with sideband signals ![The image displays a red icon representing a document or memo. It features a red outline of a rectangular piece of paper with the top-right corner folded over (a 'dog-ear'). Inside the outline, centered horizontally, are two horizontal red bars stacked vertically, resembling lines of text.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/c4c9d276f43147dc1bc76e3d3f68a48348d51929c4384a41973b50d7c783f3c3.jpg) Note: PHY on carrier is required for Optical Fiber / Copper. Ethernet MAC configuration

		KR_0	KR_1	KR_2	KR_3	KR_4	KR_5	KR_6	KR_7	Note for possible usage
For 100G Ethernet Bandwidth SKU D-2896TER D-2796TE D-2775TE	2x 100G	100G				100G (failover)				Backplane usage
	2x 50G	50G				50G				Backplane usage
	2x 40G	40G				40G				Backplane usage
	4x 25G	25G	25G	25G	25G					Backplane usageSFP+ (1pc, C827 on carrier)
	8x 10G	10G	10G	10G	10G	10G	10G	10G	10G	Backplane usageSFP+ (2pcs, C827 on carrier)10G BASE-T (2pcs, X557-AT4 on carrier)
For 50G Ethernet Bandwidth SKU D-2899NT D-2752TER D-2733NT D-2712T	1x 50G	50G								Backplane usage
	1x 40G	40G								Backplane usage
	4x 10G	10G	10G	10G	10G					Backplane usageSFP+ (1pc, C827 on carrier)10G BASE-T (1pc, X557-AT4 on carrier)

![The image displays a white icon shaped like a piece of paper with a folded bottom-right corner. It is outlined in red and features two horizontal red lines centered within the shape.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/efccefc55a6eec39ad568f1ba8c133ff8bf68e00188e9e4f47a4a38ea4bff8e1.jpg) # Note: 1. Firmware for each configuration may differ and is dependent on silicon vendor. 2. Table above shows highest speed supported per lane and can be configured to lower speeds. 3.10G and 40G support require the use of 4 lanes, while 50G support require 2 lanes. 4.For detailed circuit information between Ethernet Controller, PHY, and firmware, please contact your local ADLINK representative. # 2.4. Ethernet NBASE-T 1x NBASE-T port Onboard Intel® i225 series (IT version) Ethernet Controller 2.5Gbps, 1Gbps and 100/10Mbps connections, 1000BASE-T mode support IT version supports TSN on Linux OS, with NBASET0\_SDP available when TSN support is enabled (TBC) # 2.5. Multi I/O and Storage # USB 4x USB3.0/2.0/1.1 (USB 0, 1, 2, 3) SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling # SATA (TBC) 2x SATA 6Gb/s (SATA 0, 1) ![The image displays a red icon resembling a document or sheet of paper. It features a rounded rectangular outline with a folded bottom-right corner. Inside the outline are two horizontal red lines, resembling text or a list, with the top line being longer than the bottom one.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/449c189feb918fbcb0bb527a840fec89c3d6f2ca3f8ab5e207b5a6300b7eb0ff.jpg) Note: HSIO combined bandwidth support can be up to the equivalence of 16 PCIe Gen3 lanes. PCIe lane 0-15, SATA, USB High-speed SSTX/RX pair, NBASE-T, and PCIe\_BMC are sourced from HSIO. # On-board Storage eMMC 5.1, ranges from 32GB/64GB. Build option support by project basis eMMC as boot-up device for Windows Server 2019 (Yocto support TBC) # GPIO 12x GPIO GPI with interrupt # UART 2x UART interfaces on module Console Redirection COM 1 or COM 2 selectable in BIOS

COM Port	Description	IRQ	Address	Console Redirection Support
COM 0	Supported by module (UART 0), via embedded controller	4	0x3F8	Yes
COM 1	Supported by module (UART 1), via embedded controller	5	0x2F8	Yes

![A red icon depicting a document or page with a folded bottom-right corner. Inside the outline are two horizontal lines stacked vertically in the center.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/95f08ced4e34c558c8fcf44b8e6dc276dba00771e843d3625caf83565388c2d7.jpg) # Note: 1.The Carrier BMC of ADLINK’s reference COM-HPC Server Base offers 2x UART ports and share the physical connector/header with module’s UART ports, which can be switched using jumper settings. 2.Carrier BMC\_UART\_0 and Module\_UART\_0 connect to a DB9 connector of COM-HPC Server Base. It can be used as BMC Serial over LAN if sourced from Carrier BMC\_UART\_0. The Carrier BMC\_UART\_0 IRQ is 9, Address is 0x220. 3.Carrier BMC\_UART\_1 and Module\_UART\_1 connect to a pin header of COM-HPC Server Base. It can be used as console module. The Carrier BMC\_UART\_1 IRQ is 10, Address is 0x228. # 2.6. Trusted Platform Module (TPM) Chipset: Infineon solution Type: TPM 2.0 (SPI bus based) # 2.7. SEMA Board controller Supports: Voltage/current monitoring, power sequence debug support, logistics and forensic information, general purpose I2C, failsafe BIOS (dual BIOS, build opt. support), watchdog timer and fan control # 2.8. Remote Management & Module Management Controller (MMC) An IPMB (Intelligent Platform Management Bus) port and PCIe\_BMC lane can work in conjunction with Carrier BMC for remote management applications, build option, supported by project basis # IPMB It is offered by MMC (Module Management Controller) and is used for the connection between Carrier BMC and module MMC, build option # PCIe\_BMC It is a dedicated PCIe x1 lane for Carrier BMC, lets Carrier BMC emulate graphics card features and is mainly used for KVM # MMC, Module Management Controller It works in conjunction with Carrier BMC through IPMB and/or UART, I2C Reacts with Carrier BMC, e.g. forwarding COM-HPC module’s temperature, voltage, FAN speed, board information to Carrier BMC. Information is either obtained by MMC itself through GPIO/I2C or by communication with SEMA Board Controller. Remotely power on/off COM-HPC module through Carrier BMC/MMC is also supported # 2.9. Debug 40-pin flat cable connector for use with DB40-HPC debug module Supports BIOS POST code LED, SEMA Board Controller access, Module Management Controller access, SPI BIOS flashing, internal power rail test points, debug LEDs # 2.10. Power Power Modes: AT mode Standard Voltage Input: AT: 12V±5%Power Management: ACPI 5.0 compliant Power States: S0, S5 (WoL S5) # 2.11. Mechanical and Environmental # Form Factor and Specification PICMG COM-HPC Rev 1.1, Server Type, Size D 160 x 160 mm # Operating Temperature Standard 0°C to 60°C (Standard Voltage Input) Storage: -20°C to 80°C Extreme Rugged -40°C to 85°C (Standard Voltage Input) Storage: -40°C to 85°C (Selected SoC SKUs) # Humidity 5-90% RH operating, non-condensing, 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # HALT tested Thermal Stress, Vibration Stress, Thermal Shock and Combined Test # 3. Block Diagram ![The diagram illustrates the connectivity of an **Intel® Xeon® D** processor.\n\n**Left Side (J1) Connections:**\n* **PCIe Lane 0-3**, **PCIe Lane 4-7**, **PCIe Lane 8-11**, **PCIe Lane 12-15**: Connect to the Intel chip via lines labeled **1 x4, 2 x2**.\n* **PCIe_BMC x1**, **ETH_KR 0-3**, **ETH_KR 4-7**, **USB 2.0 Lane 0-3**, **USB 2.0 Lane 4-7**, **USB 3.x Lane 0-3**, **USB_PD_I2C/ALERT#**: Connect directly to the Intel chip.\n * **USB 3.x Lane 0-3** has the label **1x SSTX/SSRX pair per port**.\n* **NBASE-T 0**: Connects to a block labeled **LAN I225** (with label **Max. 2.5G**), which then connects to the Intel chip.\n* **SATA Port 1**: Connects to a block labeled **BIOS**, which connects to the Intel chip.\n* **SATA Port 0**, **BOOT_SPI**, **GPP_SPI**: Connect to a block labeled **TPM**, which connects to the Intel chip.\n* **SMBus**: Connects to a block labeled **EEPROM (FRU)**, which connects to the Intel chip (labeled **SMB**).\n* **I2C 0 (w/ ALERT#)**, **I2C 1**, **UART 0-1**, **12x GPIO**: Connect to a block labeled **SEMA Board Controller**.\n* **IPMB**: Connects to the **SEMA Board Controller** and a dashed block labeled **MMC**.\n* **eSPI**: Connects to the **SEMA Board Controller**.\n* The **SEMA Board Controller** connects back to the Intel chip via lines labeled **HSUART** and **eSPI**.\n\n**Right Side (J2) Connections:**\n* **PCIe Lane 16-31**, **PCIe Lane 32-47**, **PCIe Lane 48-63**: Connect to the Intel chip.\n * **PCIe Lane 16-31** and **PCIe Lane 32-47** are labeled **1 x16, 2 x8, 4 x4** and **Gen4**.\n* **ETH_Sidebands**: Connects to the Intel chip.\n* Dashed blocks **eMMC 5.1 32/64GB** and **XDP debug connector** connect to the Intel chip.\n\n**Memory Connections:**\n* **iMC 0** connects to **Ch0** and **Ch1**, each leading to a **DIMM** block.\n* **iMC 1** connects to **Ch3** and **Ch4**, each leading to a **DIMM** block.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/af325ee9430687a111901acbeb3fe235de97e830bdcc7b4a6a1f1a82aba4135e.jpg) Figure 1 – Module function diagram # 4 Pinout and Signal Descriptions # 4.1. Pin Summary The table below is a comprehensive list of all signal pins supported on the dual 400-pin COM-HPC connectors as defined for Server Type in the PICMG COM-HPC R1.1 specification. Signals described in the specification but not supported on the COM-HPC-sIDH are marked by STRIKETHROUGH. ![PIN H100\nPIN E01\n12\nSize D\n(160 x 160mm)\nPIN D100\n11\nPIN A01](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/21ff9e83c1367d62d4d31b8a095e1d1aa33c22a780b637633b4608fd87aac469.jpg) Figure 2 - Module rear side row and pin numbering

Row A		Row B		Row C		Row D
A1	VCC	B1	VCC	C1	VCC	D1	VCC
A2	VCC	B2	PWRBTN#	C2	RSTBTN#	D2	VCC
A3	VCC	B3	VCC	C3	VCC	D3	VCC
A4	VCC	B4	THERMTRIP#	C4	CARRIER_HOT#	D4	VCC
A5	VCC	B5	VCC	C5	VCC	D5	VCC
A6	VCC	B6	TAMPER#	C6	VIN_PWR_OK	D6	VCC
A7	VCC	B7	VCC	C7	VCC	D7	VCC
A8	VCC	B8	SUS_S3#	C8	SUS_S4_S5#	D8	VCC
A9	VCC	B9	VCC	C9	VCC	D9	VCC
A10	GND	B10	WD_STROBE#	C10	GND	D10	WAKE0#
A11	BATLOW#	B11	WD_OUT	C11	FAN_PWMOUT	D11	WAKE1#
A12	PLTRST#	B12	GND	C12	FAN_TACHIN	D12	GND
A13	GND	B13	USB5-	C13	GND	D13	USB1-
A14	USB7-	B14	USB5+	C14	USB3-	D14	USB1+
A15	USB7+	B15	GND	C15	USB3+	D15	GND
A16	GND	B16	USB4-	C16	GND	D16	USB0-
A17	USB6-	B17	USB4+	C17	USB2-	D17	USB0+
A18	USB6+	B18	GND	C18	USB2+	D18	GND
A19	GND	B19	RSVD	C19	GND	D19	ETH0_RX-
A20	ETH4_RX-	B20	RSVD	C20	ETH0_TX-	D20	ETH0_RX+
A21	ETH4_RX+	B21	RSVD	C21	ETH0_TX+	D21	GND
A22	GND	B22	RSVD	C22	GND	D22	ETH1_RX-
A23	ETH5_RX-	B23	RSVD	C23	ETH1_TX-	D23	ETH1_RX+
A24	ETH5_RX+	B24	VCC_5V_SBY	C24	ETH1_TX+	D24	GND
A25	GND	B25	USB67_OC#	C25	GND	D25	ETH2_RX-
A26	ETH6_RX-	B26	USB45_OC#	C26	ETH2_TX-	D26	ETH2_RX+
A27	ETH6_RX+	B27	USB23_OC#	C27	ETH2_TX+	D27	GND
A28	GND	B28	USB01_OC#	C28	GND	D28	ETH3_RX-
A29	ETH7_RX-	B29	SML1_CLK	C29	ETH3_TX-	D29	ETH3_RX+
A30	ETH7_RX+	B30	SML1_DAT	C30	ETH3_TX+	D30	GND
A31	GND	B31	PMCALERT#	C31	GND	D31	USB3_SSTX-
A32	RSVD	B32	SML0_CLK	C32	USB3_SSRX-	D32	USB3_SSTX+
A33	RSVD	B33	SML0_DAT	C33	USB3_SSRX+	D33	GND
A34	GND	B34	USB_PD_ALERT#	C34	GND	D34	USB2_SSTX-
A35	ETH4_TX-	B35	USB_PD_I2C_CLK	C35	USB2_SSRX-	D35	USB2_SSTX+
A36	ETH4_TX+	B36	USB_PD_I2C_DAT	C36	USB2_SSRX+	D36	GND
A37	GND	B37	USB_RT_ENA	C37	GND	D37	USB1_SSTX0-
A38	ETH5_TX-	B38	USB1_LSRX	C38	USB1_SSRX0-	D38	USB1_SSTX0+
A39	ETH5_TX+	B39	USB1_LSTX	C39	USB1_SSRX0+	D39	GND
A40	GND	B40	USB0_LSRX	C40	GND	D40	USB1_SSTX1-
A41	ETH6_TX-	B41	USB0_LSTX	C41	USB1_SSRX1-	D41	USB1_SSTX1+
A42	ETH6_TX+	B42	GND	C42	USB1_SSRX1+	D42	GND
A43	GND	B43	USB0_AUX-	C43	GND	D43	USB0_SSTX0-
A44	ETH7_TX-	B44	USB0_AUX+	C44	USB0_SSRX0-	D44	USB0_SSTX0+
A45	ETH7_TX+	B45	RSVD	C45	USB0_SSRX0+	D45	GND
A46	GND	B46	RSVD	C46	GND	D46	USB0_SSTX1-
A47	USB1_AUX-	B47	VCC_BOOT_SPI	C47	USB0_SSRX1-	D47	USB0_SSTX1+
A48	USB1_AUX+	B48	BOOT_SPI_CS#	C48	USB0_SSRX1+	D48	GND
A49	GND	B49	BSEL0	C49	GND	D49	SATA0_RX-*
A50	eSPI_IO0	B50	BSEL1	C50	BOOT_SPI_IO0	D50	SATA0_RX+ *
A51	eSPI_IO1	B51	BSEL2	C51	BOOT_SPI_IO1	D51	GND
A52	eSPI_IO2	B52	eSPI_ALERT0#	C52	BOOT_SPI_IO2	D52	SATA0_TX-*
A53	eSPI_IO3	B53	eSPI_ALERT1#	C53	BOOT_SPI_IO3	D53	SATA0_TX+ *
A54	eSPI_CLK	B54	eSPI_CS0#	C54	BOOT_SPI_CLK	D54	GND
A55	GND	B55	eSPI_CS1#	C55	GND	D55	SATA1_RX-*
A56	PCIe_CLKREQ0_LO#	B56	eSPI_RST#	C56	PCIe_REFCLK0_HI-	D56	SATA1_RX+*
A57	PCIe_CLKREQ0_HI#	B57	GND	C57	PCIe_REFCLK0_HI+	D57	GND
A58	GND	B58	PCIe_BMC_RX-	C58	GND	D58	SATA1_TX-*
A59	PCIe_BMC_TX-	B59	PCIe_BMC_RX+	C59	PCIe_REFCLK0_LO-	D59	SATA1_TX+*
A60	PCIe_BMC_TX+	B60	GND	C60	PCIe_REFCLK0_LO+	D60	GND
A61	GND	B61	PCIe08_RX-	C61	GND	D61	PCIe00_TX-
A62	PCIe08_TX-	B62	PCIe08_RX+	C62	PCIe00_RX-	D62	PCIe00_TX+
A63	PCIe08_TX+	B63	GND	C63	PCIe00_RX+	D63	GND
A64	GND	B64	PCIe09_RX-	C64	GND	D64	PCIe01_TX-
A65	PCIe09_TX-	B65	PCIe09_RX+	C65	PCIe01_RX-	D65	PCIe01_TX+
A66	PCIe09_TX+	B66	GND	C66	PCIe01_RX+	D66	GND
A67	GND	B67	PCIe10_RX-	C67	GND	D67	PCIe02_TX-
A68	PCIe10_TX-	B68	PCIe10_RX+	C68	PCIe02_RX-	D68	PCIe02_TX+
A69	PCIe10_TX+	B69	GND	C69	PCIe02_RX+	D69	GND
A70	GND	B70	PCIe11_RX-	C70	GND	D70	PCIe03_TX-
A71	PCIe11_TX-	B71	PCIe11_RX+	C71	PCIe03_RX-	D71	PCIe03_TX+
A72	PCIe11_TX+	B72	GND	C72	PCIe03_RX+	D72	GND
A73	GND	B73	PCIe12_RX-	C73	GND	D73	PCIe04_TX-
A74	PCIe12_TX-	B74	PCIe12_RX+	C74	PCIe04_RX-	D74	PCIe04_TX+
A75	PCIe12_TX+	B75	GND	C75	PCIe04_RX+	D75	GND
A76	GND	B76	PCIe13_RX-	C76	GND	D76	PCIe05_TX-
A77	PCIe13_TX-	B77	PCIe13_RX+	C77	PCIe05_RX-	D77	PCIe05_TX+
A78	PCIe13_TX+	B78	GND	C78	PCIe05_RX+	D78	GND
A79	GND	B79	PCIe14_RX-	C79	GND	D79	PCIe06_TX-
A80	PCIe14_TX-	B80	PCIe14_RX+	C80	PCIe06_RX-	D80	PCIe06_TX+
A81	PCIe14_TX+	B81	GND	C81	PCIe06_RX+	D81	GND
A82	GND	B82	PCIe15_RX-	C82	GND	D82	PCIe07_TX-
A83	PCIe15_TX-	B83	PCIe15_RX+	C83	PCIe07_RX-	D83	PCIe07_TX+
A84	PCIe15_TX+	B84	GND	C84	PCIe07_RX+	D84	GND
A85	GND	B85	TEST#	C85	GND	D85	NBASET0_MDIO-
A86	VCC_RTC	B86	RSMRST_OUT#	C86	SMB_CLK	D86	NBASET0_MDIO+
A87	SUS_CLK	B87	UART1_TX	C87	SMB_DAT	D87	GND
A88	GPIO_00	B88	UART1_RX	C88	SMB_ALERT#	D88	NBASET0_MDI1-
A89	GPIO_01	B89	UART1_RTS#	C89	UART0_TX	D89	NBASET0_MDI1+
A90	GPIO_02	B90	UART1_CTS#	C90	UART0_RX	D90	GND
A91	GPIO_03	B91	IPMB_CLK	C91	UART0_RTS#	D91	NBASET0_MDI2-
A92	GPIO_04	B92	IPMB_DAT	C92	UART0_CTS#	D92	NBASET0_MDI2+
A93	GPIO_05	B93	GPSPI_MOSI	C93	I2C0_CLK	D93	GND
A94	GPIO_06	B94	GPSPI_MISO	C94	I2C0_DAT	D94	NBASET0_MDI3-
A95	GPIO_07	B95	GPSPI_CS0#	C95	I2C0_ALERT#	D95	NBASET0_MDI3+
A96	GPIO_08	B96	GPSPI_CS1#	C96	I2C1_CLK	D96	GND
A97	GPIO_09	B97	GPSPI_CS2#	C97	I2C1_DAT	D97	NBASET0_LINK_MAX#
A98	GPIO_10	B98	GPSPI_CS3#	C98	NBASET0_SDP *	D98	NBASET0_LINK_MID#
A99	GPIO_11	B99	GPSPI_CLK	C99	NBASET0_CTREF	D99	NBASET0_LINK_ACT#
A100	TYPE0	B100	GPSPI_ALERT#	C100	TYPE1	D100	TYPE2
Row E		Row F		Row G		Row H
E1	RAPID_SHUTDOWN	F1	ETH2_SDP	G1	VCC_5V_SBY	H1	RSVD
E2	GND	F2	ETH3_SDP	G2	FUSA_STATUS0	H2	RSVD
E3	RSVD	F3	ETH4_SDP	G3	FUSA_STATUS1	H3	RSVD
E4	RSVD	F4	ETH5_SDP	G4	FUSA_ALERT#	H4	RSVD
E5	GND	F5	ETH6_SDP	G5	FUSA_SPI_CS#	H5	RSVD
E6	RSVD	F6	ETH7_SDP	G6	FUSA_SPI_CLK	H6	RSVD
E7	RSVD	F7	ETH4-7_I2C_CLK	G7	FUSA_SPI_MISO	H7	RSVD
E8	GND	F8	ETH4-7_I2C_DAT	G8	FUSA_SPI_MOSI	H8	RSVD
E9	RSVD	F9	ETH4-7_INT#	G9	FUSA_SPI_ALERT	H9	RSVD
E10	RSVD	F10	ETH4-7_MDIO_CLK	G10	FUSA_VOLTAGE_ERR#	H10	RSVD
E11	GND	F11	ETH4-7_MDIO_DAT	G11	PROCHOT#	H11	RSVD
E12	RSVD	F12	ETH4-7_PHY_INT#	G12	CATERR#	H12	RSVD
E13	RSVD	F13	ETH4-7_PHY_RST#	G13	RSVD	H13	RSVD
E14	GND	F14	ETH4-7_PRSNT#	G14	GND	H14	RSVD
E15	RSVD	F15	RSVD	G15	RSVD	H15	RSVD
E16	RSVD	F16	RSVD	G16	RSVD	H16	RSVD
E17	GND	F17	RSVD	G17	RSVD	H17	RSVD
E18	RSVD	F18	RSVD	G18	RSVD	H18	RSVD
E19	RSVD	F19	GND	G19	RSVD	H19	GND
E20	GND	F20	PCIe32_RX-	G20	GND	H20	PCIe40_TX-
E21	PCIe32_TX-	F21	PCIe32_RX+	G21	PCIe40_RX-	H21	PCIe40_TX+
E22	PCIe32_TX+	F22	GND	G22	PCIe40_RX+	H22	GND
E23	GND	F23	PCIe33_RX-	G23	GND	H23	PCIe41_TX-
E24	PCIe33_TX-	F24	PCIe33_RX+	G24	PCIe41_RX-	H24	PCIe41_TX+
E25	PCIe33_TX+	F25	GND	G25	PCIe41_RX+	H25	GND
E26	GND	F26	PCIe34_RX-	G26	GND	H26	PCIe42_TX-
E27	PCIe34_TX-	F27	PCIe34_RX+	G27	PCIe42_RX-	H27	PCIe42_TX+
E28	PCIe34_TX+	F28	GND	G28	PCIe42_RX+	H28	GND
E29	GND	F29	PCIe35_RX-	G29	GND	H29	PCIe43_TX-
E30	PCIe35_TX-	F30	PCIe35_RX+	G30	PCIe43_RX-	H30	PCIe43_TX+
E31	PCIe35_TX+	F31	GND	G31	PCIe43_RX+	H31	GND
E32	GND	F32	PCIe36_RX-	G32	GND	H32	PCIe44_TX-
E33	PCIe36_TX-	F33	PCIe36_RX+	G33	PCIe44_RX-	H33	PCIe44_TX+
E34	PCIe36_TX+	F34	GND	G34	PCIe44_RX+	H34	GND
E35	GND	F35	PCIe37_RX-	G35	GND	H35	PCIe45_TX-
E36	PCIe37_TX-	F36	PCIe37_RX+	G36	PCIe45_RX-	H36	PCIe45_TX+
E37	PCIe37_TX+	F37	GND	G37	PCIe45_RX+	H37	GND
E38	GND	F38	PCIe38_RX-	G38	GND	H38	PCIe46_TX-
E39	PCIe38_TX-	F39	PCIe38_RX+	G39	PCIe46_RX-	H39	PCIe46_TX+
E40	PCIe38_TX+	F40	GND	G40	PCIe46_RX+	H40	GND
E41	GND	F41	PCIe39_RX-	G41	GND	H41	PCIe47_TX-
E42	PCIe39_TX-	F42	PCIe39_RX+	G42	PCIe47_RX-	H42	PCIe47_TX+
E43	PCIe39_TX+	F43	GND	G43	PCIe47_RX+	H43	GND
E44	GND	F44	PCIe16_RX-	G44	GND	H44	PCIe24_TX-
E45	PCIe16_TX-	F45	PCIe16_RX+	G45	PCIe24_RX-	H45	PCIe24_TX+
E46	PCIe16_TX+	F46	GND	G46	PCIe24_RX+	H46	GND
E47	GND	F47	PCIe17_RX-	G47	GND	H47	PCIe25_TX-
E48	PCIe17_TX-	F48	PCIe17_RX+	G48	PCIe25_RX-	H48	PCIe25_TX+
E49	PCIe17_TX+	F49	GND	G49	PCIe25_RX+	H49	GND
E50	GND	F50	PCIe18_RX-	G50	GND	H50	PCIe26_TX-
E51	PCIe18_TX-	F51	PCIe18_RX+	G51	PCIe26_RX-	H51	PCIe26_TX+
E52	PCIe18_TX+	F52	GND	G52	PCIe26_RX+	H52	GND
E53	GND	F53	PCIe19_RX-	G53	GND	H53	PCIe27_TX-
E54	PCIe19_TX-	F54	PCIe19_RX+	G54	PCIe27_RX-	H54	PCIe27_TX+
E55	PCIe19_TX+	F55	GND	G55	PCIe27_RX+	H55	GND
E56	GND	F56	PCIe20_RX-	G56	GND	H56	PCIe28_TX-
E57	PCIe20_TX-	F57	PCIe20_RX+	G57	PCIe28_RX-	H57	PCIe28_TX+
E58	PCIe20_TX+	F58	GND	G58	PCIe28_RX+	H58	GND
E59	GND	F59	PCIe21_RX-	G59	GND	H59	PCIe29_TX-
E60	PCIe21_TX-	F60	PCIe21_RX+	G60	PCIe29_RX-	H60	PCIe29_TX+
E61	PCIe21_TX+	F61	GND	G61	PCIe29_RX+	H61	GND
E62	GND	F62	PCIe22_RX-	G62	GND	H62	PCIe30_TX-
E63	PCIe22_TX-	F63	PCIe22_RX+	G63	PCIe30_RX-	H63	PCIe30_TX+
E64	PCIe22_TX+	F64	GND	G64	PCIe30_RX+	H64	GND
E65	GND	F65	PCIe23_RX-	G65	GND	H65	PCIe31_TX-
E66	PCIe23_TX-	F66	PCIe23_RX+	G66	PCIe31_RX-	H66	PCIe31_TX+
E67	PCIe23_TX+	F67	GND	G67	PCIe31_RX+	H67	GND
E68	GND	F68	PCIe48_RX-	G68	GND	H68	PCIe56_TX-
E69	PCIe48_TX-	F69	PCIe48_RX+	G69	PCIe56_RX-	H69	PCIe56_TX+
E70	PCIe48_TX+	F70	GND	G70	PCIe56_RX+	H70	GND
E71	GND	F71	PCIe49_RX-	G71	GND	H71	PCIe57_TX-
E72	PCIe49_TX-	F72	PCIe49_RX+	G72	PCIe57_RX-	H72	PCIe57_TX+
E73	PCIe49_TX+	F73	GND	G73	PCIe57_RX+	H73	GND
E74	GND	F74	PCIe50_RX-	G74	GND	H74	PCIe58_TX-
E75	PCIe50_TX-	F75	PCIe50_RX+	G75	PCIe58_RX-	H75	PCIe58_TX+
E76	PCIe50_TX+	F76	GND	G76	PCIe58_RX+	H76	GND
E77	GND	F77	PCIe51_RX-	G77	GND	H77	PCIe59_TX-
E78	PCIe51_TX-	F78	PCIe51_RX+	G78	PCIe59_RX-	H78	PCIe59_TX+
E79	PCIe51_TX+	F79	GND	G79	PCIe59_RX+	H79	GND
E80	GND	F80	PCIe52_RX-	G80	GND	H80	PCIe60_TX-
E81	PCIe52_TX-	F81	PCIe52_RX+	G81	PCIe60_RX-	H81	PCIe60_TX+
E82	PCIe52_TX+	F82	GND	G82	PCIe60_RX+	H82	GND
E83	GND	F83	PCIe53_RX-	G83	GND	H83	PCIe61_TX-
E84	PCIe53_TX-	F84	PCIe53_RX+	G84	PCIe61_RX-	H84	PCIe61_TX+
E85	PCIe53_TX+	F85	GND	G85	PCIe61_RX+	H85	GND
E86	GND	F86	PCIe54_RX-	G86	GND	H86	PCIe62_TX-
E87	PCIe54_TX-	F87	PCIe54_RX+	G87	PCIe62_RX-	H87	PCIe62_TX+
E88	PCIe54_TX+	F88	GND	G88	PCIe62_RX+	H88	GND
E89	GND	F89	PCIe55_RX-	G89	GND	H89	PCIe63_TX-
E90	PCIe55_TX-	F90	PCIe55_RX+	G90	PCIe63_RX-	H90	PCIe63_TX+
E91	PCIe55_TX+	F91	GND	G91	PCIe63_RX+	H91	GND
E92	GND	F92	PCIe_REFCLK2-	G92	GND	H92	PCIe_REFCLKIN0-
E93	PCIe_REFCLK1-	F93	PCIe_REFCLK2+	G93	PCIe_REFCLK3-	H93	PCIe_REFCLKIN0+
E94	PCIe_REFCLK1+	F94	GND	G94	PCIe_REFCLK3+	H94	GND
E95	GND	F95	PCIe_CLKREQ3#	G95	GND	H95	PCIe_REFCLKIN1-
E96	PCIe_CLKREQ1#	F96	ETH0-3_PRSNT#	G96	ETH0-3_I2C_CLK	H96	PCIe_REFCLKIN1+
E97	PCIe_CLKREQ2#	F97	ETH0-3_PHY_RST#	G97	ETH0-3_I2C_DAT	H97	GND
E98	PCIe_CLKREQ_OUT0#	F98	ETH0_SDP	G98	ETH0-3_PHY_INT#	H98	ETH0-3_MDIO_CLK
E99	PCIe_CLKREQ_OUT1#	F99	ETH1_SDP	G99	ETH0-3_INT#	H99	ETH0-3_MDIO_DAT
E100	PCIe_PERST_IN0#	F100	PCIe_PERST_IN1#	G100	PCIe_WAKE_OUT0#	H100	PCIe_WAKE_OUT1#

![This image displays a red icon of a document page with a folded bottom-right corner. Inside the page outline, there are two horizontal lines representing text.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/0ead72054be03219d3b5292642caadf36cbad63603e94c1f0a39900ae4073464.jpg) Note: NBASET0\_SDP depends on LAN controller SK. # 4.2. Signal Terminology Descriptions Meaning of the terms used in signal description tables

Term	Description
I	Input to the module
O	Output from the module
I/O	Bi-directional Input / Output
OD	Open drain output from the module

I 3.3V	Input 3.3V tolerant
I 5V	Input 5V tolerant
O 3.3V	Output 3.3V signal level
O 5V	Output 5V signal level
I/O 3.3V	Bi-directional signal 3.3V tolerant
I/O 5V	Bi-directional signal 5V tolerant
I/O $3.3V_{SB}$	Input or output 3.3V tolerant active in standby state

DDC	Display Data Channel
PCIE	PCI Express compatible differential signal
PEG	PCI Express Graphics
SATA	Serial ATA specification Revision 2.6 and 3
LVDS	Low Voltage Differential Signal - 330 mV nominal; 450 mV maximum differential signal

P	Power Input / Output
REF	Reference voltage output. May be sourced from a Module power plane.
PDS	Pull-down strap. A Module output pin that is either tied to GND or is not connected.Used to signal Module capabilities to the Carrier Board.

PU	PU (pull-up) resistor on module
PD	PD (pull-down) resistor on module

# 4.3. Signal Descriptions on J1/J2 Connectors # 4.3.1 Ethernet KR KR interface are defined for COM-HPC. For these ports, the Ethernet MACs are located on COM-HPC module. PHYs (if used) are on the Carrier. COM-HPC support both of MDIO and I2C control interfaces for the PHYs. The MDIO and I2C control interfaces are grouped into quads, for KR ports 0:3 and ports 4:7

Name	Pin #	Description	I/O	PU / PD	Comment
ETH0_TX-	C20	Ethernet KR ports, transmit output differential pairs.	O		AC coupled off Module
ETH0_TX+	C21		KR
ETH1_TX-	C23
ETH1_TX+	C24
ETH2_TX-	C26
ETH2_TX+	C27
ETH3_TX-	C29
ETH3_TX+	C30
ETH0_RX-	D19	Ethernet KR ports, receive input differential pairs.	I		AC coupled off Module
ETH0_RX+	D20		KR
ETH1_RX-	D22
ETH1_RX+	D23
ETH2_RX-	D25
ETH2_RX+	D26
ETH3_RX-	D28
ETH3_RX+	D29
ETH0-3_MDIO_DAT	H99	Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 0 to 3	I/O	PU 1K
ETH0-3_MDIO_DAT	H99		3.3VSB	3.3VSB
ETH0-3_MDIO_CLK	H98	Clock signal for Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 0 to 3	O	PU 1K
ETH0-3_MDIO_CLK	H98		3.3VSB	3.3VSB
ETH0-3_INT#	G99	Active low interrupt signal from IO Port expanders for ETH ports 0 to 3	I	PU 10K
ETH0-3_INT#	G99		3.3VSB	3.3VSB
ETH0-3_PHY_INT#	G98	Active low PHY interrupt signal from ETH ports 0 to 3	$\ddagger$	PU 1K	Not supported
ETH0-3_PHY_INT#	G98	Active low PHY interrupt signal from ETH ports 0 to 3	3.3VSB	3.3VSB
ETH0-3_PHY_RST#	F97	Active low output PHY reset signal for ETH ports 0 to 3.	O3.3VSB	PU 4.7K3.3VSB
ETH0-3_I2C_DAT	G97	I2C data signal of the 2-wire management interface used by the Ethernet KR controller to access the management registers of an external SFP Module or to configure the Carrier PHY for ETHx ports 0 to 3 and for serialized status information (e.g. LED states)..	I/O OD3.3VSB	PU 10K3.3VSB
ETH0-3_I2C_CLK	G96	The I2C clock signals associated with ETH0-3 I2C data lines in the row above.	I/O OD3.3VSB	PU 10K3.3VSB
ETH0_SDP	F98	Software-Definable Pins. Can also be used for IEEE1588 support such as a PPS signal.	I/O3.3VSB
ETH1_SDP	F99
ETH2_SDP	F1
ETH3_SDP	F2
ETH0-3_PRSNT#	H96	Carrier pulls this line to GND if there is Carrier hardware present to support Ethernet KR signaling on ETH0 through ETH3. If the entire KR quad is not supported it should fill from ETH0 on up.	I3.3VSB	PU 10K3.3VSB

Name	Pin #	Description	I/O	PU / PD	Comment
ETH4_TX-	A35	Ethernet KR ports, transmit output differential pairs.	O		AC coupled off Module
ETH4_TX+	A36		KR
ETH5_TX-	A38
ETH5_TX+	A39
ETH6_TX-	A41
ETH6_TX+	A42
ETH7_TX-	A44
ETH7_TX+	A45
ETH4_RX-	A20	Ethernet KR ports, receive input differential pairs.	I		AC coupled off Module
ETH4_RX+	A21		KR
ETH5_RX-	A23
ETH5_RX+	A24
ETH6_RX-	A26
ETH6_RX+	A27
ETH7_RX-	A29
ETH7_RX+	A30
ETH4-7_MDIO_DAT	F11	Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 4 to 7	I/O	PU 1K
ETH4-7_MDIO_DAT	F11		3.3VSB	3.3VSB
ETH4-7_MDIO_CLK	F10	Clock signal for Management Data I/O interface mode data signal for serial data transfers between the MAC and an external PHY for ETHx ports 4 to 7	O3.3VSB	PU 1K3.3VSB
ETH4-7_INT#	F9	Active low interrupt signal from IO Port expanders for ETH ports 4 to 7	I3.3VSB	PU 4.7K3.3VSB
ETH4-7_PHY_INT#	F12	Active low PHY interrupt signal from ETH ports 4 to 7	↓3.3VSB		Not supported
ETH4-7_PHY_RST#	F13	Active low output PHY reset signal for ETH ports 4 to 7.	O3.3VSB	PU 4.7K3.3VSB
ETH4-7_I2C_DAT	F8	I2C data signal of the 2-wire management interface used by the Ethernet KR controller to access the management registers of an external SFP Module or to configure the Carrier PHY for ETHx ports 4 to 7 and for serialized status information (e.g. LED states)..	I/O OD3.3VSB	PU 10K3.3VSB
ETH4-7_I2C_CLK	F7	The I2C clock signals associated with ETH4-7 I2C data lines in the row above.	I/O OD3.3VSB	PU 10K3.3VSB
ETH4_SDP	F3	Software-Definable Pins. Can also be used for IEEE1588 support such as a PPS signal.	I/O3.3VSB
ETH5_SDP	F4
ETH6_SDP	F5
ETH7_SDP	F6
ETH4-7_PRSNT#	F14	Carrier pulls this line to GND if there is Carrier hardware present to support Ethernet KR signaling on ETH4 through ETH7. If the entire KR quad is not supported it should fill from ETH4 on up.	I3.3VSB	PU 10K3.3VSB

# 4.3.2 NBASE-T Ethernet Magnetics are on the Carrier board. The COM-HPC module shall be capable of 1000BASE-T mode.

Name	Pin #	Description	I/O	PU / PD	Comment
NBASET0_MDI0-	D85	Ethernet Controller 1: Media Dependent Interface Differential Pairs	I/O Analog		Twisted pair signals for external transformer.
NBASET0_MDI0+	D86	0,1,2,3. The MDI can operate in 10Gbps, 1Gbps, 100Mbps and 10 Mbps modes. Some pairs are unused in some modes, per the following:
NBASET0_MDI1-	D88
NBASET0_MDI1+	D89
NBASET0_MDI2-	D91
NBASET0_MDI2+	D92

NBASET0_MDI3-NBASET0_MDI3+	D93D94		10000BASE-T1000BASE-T	100BASE-TX	10BASE-T
		MDI[0]+/-	B1_DA+/-	TX+/-	TX+/-
		MDI[1]+/-	B1_DB+/-	RX+/-	RX+/-
		MDI[2]+/-	B1_DC+/-
		MDI[3]+/-	B1_DD+/-
NBASET0_LINK_ACT#	D99	NBASE-T Ethernet Controller activity indicator, active low. 20 mA or more current sink capability at VOL of 0.4V max. 20 mA or more current source capability at VOH of 2.4V min.				O 3.3VSB
NBASET0_LINK_MAX#	D97	NBASE-T Ethernet Controller MAX Speed Link indicator, active low. If active, the link is established at the maximum speed that the Ethernet controller is capable of (which may be 10G, 5G, 2.5G etc). 20 mA or more current sink capability at VOL of 0.4V max. 20 mA or more current source capability at VOH of 2.4V min.				O 3.3VSB
NBASET0_LINK_MID#	D98	NBASE-T Ethernet Controller MID Speed Link indicator, active low. If active, the link is established but at a speed lower than what the maximum speed that the Ethernet controller is capable of. 20 mA or more current sink capability at VOL of 0.4V max. 20 mA or more current source capability at VOH of 2.4V min.				O 3.3VSB
NBASET0_CTREF	C99	Reference voltage for Carrier Board NBASET Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the Module PHY and may be as low as 0V and as high as 3.3V. If not needed, these pins may be left open on the Carrier. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be limited to 250 mA or less.				REF GND min 3.3V max	Not supported
NBASET0_SDP	C98	NBASE-T Ethernet Controller 0 Software-Definable Pin. Can also be used for IEEE1588 support such as a 1pps signal.				IO 3.3VSB	Depends on LAN controller SKU

4.3.3 PCI Express

Name	Pin #	Description	I/O	PU / PD	Comment
PCIe00_TX+	D62	PCI Express Differential Transmit Pairs 0-7PCIe Group 0 Low	O PCIe		AC coupled on Module
PCIe00_TX-	D61
PCIe01_TX+	D65
PCIe01_TX-	D64
PCIe02_TX+	D68
PCIe03_TX-	D67
PCIe03_TX+	D71
PCIe03_TX-	D70
PCIe04_TX+	D74
PCIe04_TX-	D73
PCIe05_TX+	D77
PCIe05_TX-	D76
PCIe06_TX+	D80
PCIe06_TX-	D79
PCIe07_TX+	D83
PCIe07_TX-	D82
PCIe00_RX+	C63	PCI Express Differential Receive Pairs 0-7PCIe Group 0 Low	I PCIe		AC coupled off Module
PCIe00_RX-	C62
PCIe01_RX+	C66
PCIe01_RX-	C65
PCIe02_RX+	C69
PCIe02_RX-	C68
PCIe03_RX+	C72
PCIe03_RX-	C71
PCIe04_RX+	C75
PCIe04_RX-	C74
PCIe05_RX+	C78
PCIe05_RX-	C77
PCIe06_RX+	C81
PCIe06_RX-	C80
PCIe07_RX+	C84
PCIe07_RX-	C83
PCIe08_TX+	A63	PCI Express Differential Transmit Pairs 8-15PCIe Group 0 HighA Server Module may map up to 8 higher bandwidthPCIe lanes to Group 0 High	O PCIe		AC coupled on Module
PCIe08_TX-	A62
PCIe09_TX+	A66
PCIe09_TX-PCIe10_TX+	A65A69
PCIe10_TX-	A68
PCIe11_TX+	A72
PCIe11_TX-	A71
PCIe12_TX+	A75
PCIe12_TX-	A74
PCIe13_TX+	A78
PCIe13_TX-	A77
PCIe14_TX+	A81
PCIe14_TX-	A80
PCIe15_TX+	A84
PCIe15_TX-	A83
PCIe08_RX+	B62	PCI Express Differential Receive Pairs 8-15	I PCIe		AC coupled off Module
PCIe08_RX-	B61	PCIe Group 0 High
PCIe09_RX+	B65	A Server Module may map up to 8 higher bandwidth
PCIe09_RX-	B64	PCIe lanes to Group 0 High
PCIe10_RX+	B68
PCIe10_RX-	B67
PCIe11_RX+	B71
PCIe11_RX-	B70
PCIe12_RX+	B74
PCIe12_RX-	B73
PCIe13_RX+	B77
PCIe13_RX-	B76
PCIe14_RX+	B80
PCIe14_RX-	B79
PCIe15_RX+	B83
PCIe15_RX-	B82
PCIe16_TX+	E46	PCI Express Differential Transmit Pairs 16-31	O PCIe		AC coupled on Module
PCIe16_TX-	E46	PCIe Group 1
PCIe17_TX+	E49
PCIe17_TX-	E48
PCIe18_TX+	E52
PCIe18_TX-	E51
PCIe19_TX+	E55
PCIe19_TX-	E54
PCIe20_TX+	E58
PCIe20_TX-	E57
PCIe21_TX+	E61
PCIe21_TX-	E60
PCIe22_TX+	E64
PCIe22_TX-	E63
PCIe23_TX+	E67
PCIe23_TX-	E66
PCIe24_TX+	H45
PCIe24_TX-	H44
PCIe25_TX+	H48
PCIe25_TX-	H47
PCIe26_TX+	H51
PCIe26_TX-	H50
PCIe27_TX+	H54
PCIe27_TX-	H53
PCIe28_TX+	H57
PCIe28_TX-	H56
PCIe29_TX+	H60
PCIe29_TX-	H59
PCIe30_TX+	H63
PCIe30_TX-	H62
PCIe31_TX+	H66
PCIe31_TX-	H65
PCIe16_RX+	F45	PCI Express Differential Receive Pairs 16-31PCIe Group 1	I PCIe		AC coupled off Module
PCIe16_RX-	F44
PCIe17_RX+	F48
PCIe17_RX-	F47
PCIe18_RX+	F51
PCIe18_RX-	F50
PCIe19_RX+	F54
PCIe19_RX-	F53
PCIe20_RX+	F57
PCIe20_RX-	F56
PCIe21_RX+	F60
PCIe21_RX-	F59
PCIe22_RX+	F63
PCIe22_RX-	F62
PCIe23_RX+	F66
PCIe23_RX-	F65
PCIe24_RX+	G46
PCIe24_RX-PCIe25_RX+PCIe25_RX-PCIe26_RX+PCIe26_RX-PCIe27_RX+PCIe27_RX-PCIe28_RX+PCIe28_RX-PCIe29_RX+PCIe29_RX-PCIe30_RX+PCIe30_RX-PCIe31_RX+PCIe31_RX-	G45G49G48G52G51G55G54G58G57G61G60G64G63G67G66
PCIe32_TX+PCIe32_TX-PCIe33_TX+PCIe33_TX-PCIe34_TX+PCIe34_TX-PCIe35_TX+PCIe35_TX-PCIe36_TX+PCIe36_TX-PCIe37_TX+PCIe37_TX-PCIe38_TX+PCIe38_TX-PCIe39_TX+PCIe39_TX-PCIe40_TX+PCIe40_TX-PCIe41_TX+PCIe41_TX-PCIe42_TX+PCIe42_TX-PCIe43_TX+PCIe43_TX-PCIe44_TX+PCIe44_TX-	E22E21E25E24E28E27E31E30E34E33E37E36E40E39E43E42H22H21H24H23H27H26H30H29H33H32	PCI Express Differential Transmit Pairs 32-47PCIe Group 2	O PCIe		AC coupled on Module
PCIe45_TX+	H36
PCIe45_TX-	H35
PCIe46_TX+	H39
PCIe46_TX-	H38
PCIe47_TX+	H42
PCIe47_TX-	H41
PCIe32_RX+	F21	PCI Express Differential Receive Pairs 32-47PCIe Group 2	I PCIe		AC coupled off Module
PCIe32_RX-	F20
PCIe33_RX+	F24
PCIe33_RX-	F23
PCIe34_RX+	F27
PCIe34_RX-	F26
PCIe35_RX+	F30
PCIe35_RX-	F29
PCIe36_RX+	F33
PCIe36_RX-	F32
PCIe37_RX+	F36
PCIe37_RX-	F35
PCIe38_RX+	F39
PCIe38_RX-	F38
PCIe39_RX+	F42
PCIe39_RX-	F41
PCIe40_RX+	G22
PCIe40_RX-	G21
PCIe41_RX+	G25
PCIe41_RX-	G24
PCIe42_RX+	G28
PCIe42_RX-	G27
PCIe43_RX+	G31
PCIe43_RX-	G30
PCIe44_RX+	G34
PCIe44_RX-	G33
PCIe45_RX+	G37
PCIe45_RX-	G36
PCIe46_RX+	G40
PCIe46_RX-	G39
PCIe47_RX+	G43
PCIe47_RX-	G42
PCIe48_TX+PCIe48_TX-PCIe49_TX+PCIe49_TX-PCIe50_TX+PCIe50_TX-PCIe51_TX+PCIe51_TX-PCIe52_TX+PCIe52_TX-PCIe53_TX+PCIe53_TX-PCIe54_TX+PCIe54_TX-PCIe55_TX+PCIe55_TX-PCIe56_TX+PCIe56_TX-PCIe57_TX+PCIe57_TX-PCIe58_TX+PCIe58_TX-PCIe59_TX+PCIe59_TX-PCIe60_TX+PCIe60_TX-PCIe61_TX+PCIe61_TX-PCIe62_TX+PCIe62_TX-PCIe63_TX+PCIe63_TX-	E70E69E73E72E76E75E79E78E82E81E85E84E88E87E91E90H69H68H72H71H75H74H78H77H81H80H84H83H87H86H91H90	PCI Express Differential Transmit Pairs 48-63PCIe Group 3	O PCIe		Not supported
PCIe48_RX+PCIe48_RX-PCIe49_RX+PCIe49_RX-PCIe50_RX+PCIe50_RX-PCIe51_RX+	F69F68F72F71F75F74F78	PCI Express Differential Receive Pairs 48-63PCIe Group 3	I PCIe		Not supported
PCIe51_RX-PCIe52_RX+PCIe52_RX-PCIe53_RX+PCIe53_RX-PCIe54_RX+PCIe54_RX-PCIe55_RX+PCIe55_RX-PCIe56_RX+PCIe56_RX-PCIe57_RX+PCIe57_RX-PCIe58_RX+PCIe58_RX-PCIe59_RX+PCIe59_RX-PCIe60_RX+PCIe60_RX-PCIe61_RX+PCIe61_RX-PCIe62_RX+PCIe62_RX-PCIe63_RX+PCIe63_RX-	F77F81F80F84F83F87F86F90F89G70G69G73G72G76G75G79G78G82G81G85G84G88G87G91G90
PCIe_BMC_TX-PCIe_BMC_TX+	A59A60	PCI Express Differential Transmit Pair for Carrier BMC(Board Management Controller)	O PCIe		AC coupled on Module
PCIe_BMC_RX-PCIe_BMC_RX+	B58B59	PCI Express Differential Transmit Pair for Carrier BMC(Board Management Controller)	I PCIe		AC coupled off Module
PCIe_REFCLK0_LO-PCIe_REFCLK0_LO+	C59C60	Reference clock pair for PCIe lanes [0:7], also referred to PCIe Group 0 Low and for the PCIe_BMC link	O PCIe
PCIe_REFCLK0_HI-PCIe_REFCLK0_HI+	C57C56	Reference clock pair for PCIe lanes [8:15], also referred to PCIe Group 0 High	O PCIe
PCIe_REFCLK1-PCIe_REFCLK1+	E93E94	Reference clock pair for PCIe lanes [16:31], also referred to PCIe Group 1	O PCIe
PCIe_REFCLK2-PCIe_REFCLK2+	F92F93	Reference clock pair for PCIe lanes [32:47], also referred to PCIe Group 2	O PCIe
PCIe_REFCLK3-PCIe_REFCLK3+	G93G94	Reference clock pair for PCIe lanes [48:63], also referred to PCIe Group 2	O PCIe		Not Supported
PCIe_CLKREQ0_LO#	A56	PCIe reference clock request signals from Carrier devices for PCIe_REFCLK0_LO clock pair	I/O OD3.3V	PU 10K3.3V
PCIe_CLKREQ0_HI#	A57	PCIe reference clock request signals from Carrier devices for PCIe_REFCLK0_HI clock pair	I/O OD3.3V	PU 10K3.3V
PCIe_CLKREQ0_1#	E96	PCIe reference clock request signals from Carrier devices for PCIe_REFCLK1 clock pair	I/O OD3.3V	PU 10K3.3V
PCIe_CLKREQ0_2#	E97	PCIe reference clock request signals from Carrier devices for PCIe_REFCLK2 clock pair	I/O OD3.3V	PU 10K3.3
PCIe_CLKREQ0_3#	F95	PCIe reference clock request signals from Carrier devices for PCIe_REFCLK3 clock pair	I/O OD3.3V	PU 10K3.3V	Not supported

# 4.3.4 USB To realize a COM-HPC USB 3.2 Gen1, Gen2, Gen2x2 or USB4 port, one of the four available USB 2.0 ports from the USB[0:3] pool must be used along with the SuperSpeed pins. Specific pairings are described in table below.

Name	Pin #	Description	I/O	PU / PD	Comment
USB0+	D17	USB 2.0 differential pairs, channels 0 through 7.	I/O		USB 1.1/2.0 compliant
USB0-	D16		3.3VSB
USB1+	D14	USB0 may be configured as a USB client or as a host, or both at the Module designer's discretion. All other USB ports, if implemented, shall be host ports.			USB Client mode – Not supported
USB1-	D13
USB2+	C18
USB2-	C17
USB3+	C15	If any SuperSpeed ports are implemented, then they must be supported by a USB 2.0 port, using one of the USB[0:3] ports from this pool.
USB3-	C14
USB4+	B17	USB 2.0 differential pairs, channels 0 through 7.	I/O		Not supported
USB4-	B16		3.3VSB
USB5+	B14	USB0 may be configured as a USB client or as a host, or both at the Module designer's discretion. All other USB ports, if implemented, shall be host ports.
USB5-	B13
USB6+	A18
USB6-USB7+USB7-	A17A15A14
		If any SuperSpeed ports are implemented, then they must be supported by a USB 2.0 port, using one of the USB[0:3] ports from this pool.
USB0_SSTX0+USB0_SSTX0-USB1_SSTX0+USB1_SSTX0-USB0_SSTX1+USB0_SSTX1-USB1_SSTX1+USB1_SSTX1-	D44D43D38D37D47D46D41D40	Four sets of SuperSpeed transmit pairs, used to realize the transmit side of two USB 3.2 Gen 2x2 ports.Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TX pair, single RX pair per port) may be implemented using a portion of this interface.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/- shall be used with the USB0 USB 2.0 pair and so on, USB1_SSxxx+/- with the USB1 USB 2.0 pair).	O PCIe		AC coupled on Module
USB0_SSRX0+USB0_SSRX0-USB1_SSRX0+USB1_SSRX0-USB0_SSRX1+USB0_SSRX1-USB1_SSRX1+USB1_SSRX1-	C45C44C39C38C48C47C42C41	Four sets of SuperSpeed receive pairs, used to realize the transmit side of two USB 3.2 Gen 2x2 ports.Alternatively, USB 3.2 Gen 1 or Gen 2 ports (single TX pair, single RX pair per port) may be implemented using a portion of this interface.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB0_SSxxx+/- shall be used with the USB0 USB 2.0 pair, USB1_SSxxx+/- with the USB1 USB 2.0 pair).	I PCIe		AC coupled off Module
USB2_SSTX+USB2_SSTX-USB3_SSTX+USB3_SSTX-	D35D34D32D31	Two sets of high speed transmit pairs, to realize two USB 3.2 Gen 1 or Gen 2 implementations.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/- shall be used with the USB2 USB 2.0 pair and USB3_SSxxx+/- with the USB3 USB 2.0 pair).	O PCIe		AC coupled on Module
USB2_SSRX+USB2_SSRX-USB3_SSRX+USB3_SSRX-	C36C35C33C32	Two sets of high speed receive pairs, to realize two USB 3.2 Gen 1 or Gen 2 implementations.These ports shall be used in conjunction with the corresponding USB 2.0 port pair (e.g. USB2_SSxxx+/-shall be used with the USB2 USB 2.0 pair and USB3_SSxxx+/- with the USB3 USB 2.0 pair).	I PCIe		AC coupled off Module
USB01_OC#	B28	USB over-current sense, USB channels 0,1; channels 2,3; channels 4,5 and channels 6,7 respectively.	I 3.3VSB	PU 10K	Do not pull high on carrier
USB23_OC#	B27			3.3VSB
USB45_OC#	B26	A pull-up for each of these lines to the 3.3V Suspend rail shall be present on the Module.
USB67_OC#	B25	The pull-up should be 10K. An open drain driver from USB current monitors on the Carrier Board may drive this line low. The Carrier Board shall not pull these lines up. Note that the over-current limits for USB 2.0 and USB 3.0 are different; this is a Carrier board implementation item.
RSMRST_OUT#		USB devices that are to be powered in the S5 / S4 / S3 Suspend states should not have their 5V VBUS power enabled before RSMRST_OUT# transitions to the hi state. RSMRST_OUT# is also described in Power and System Management section	O 3.3VSB	PD 1K

This platform doesn’t support USB4, thus additional signals required by USB4 are not shown here. 4.3.5 SATA

Name	Pin #	Description	I/O	PU / PD	Comment
SATA0_TX+	D53	Serial ATA Channel 0 transmit differential pair.	O SATA		AC coupled on Module
SATA0_TX-	D52
SATA0_RX+	D50	Serial ATA Channel 0 receive differential pair.	I SATA		AC coupled on Module
SATA0_RX-	D49
SATA1_TX+	D59	Serial ATA Channel 1 transmit differential pair.	O SATA		AC coupled on Module
SATA1_TX-	D58
SATA1_RX+	D56	Serial ATA Channel 1 receive differential pair.	I SATA		AC coupled on Module
SATA1_RX-	D55

4.3.6 Asynchronous Serial Port

Name	Pin #	Description	I/O	PU / PD	Comment
UART0_TX	C89	Logic level asynchronous serial port transmit signal	O 3.3V
UART1_TX	B87
UART0_RX	C90	Logic level asynchronous serial port receive signal	I 3.3V	PU 10K
UART1_RX	B88			3.3V
UART0_RTS#	C91	Logic level asynchronous serial port Request to Send signal, active low	O 3.3V		UART1_RTS# Not supported
UART1_RTS#	B89
UART0_CTS#	C92	Logic level asynchronous serial port Clear to Send input, active low	I 3.3V		UART1_CTS# Not supported
UART1_CTS#	B90

# 4.3.7 I2C Two general purpose I2C ports are defined for COM-HPC. The first of the two supports an ALERT# input. I2C0 is defined to operate from a 3.3V rail and I2C1 from a 1.8V rail.

Name	Pin #	Description	I/O	PU / PD	Comment
I2C0_CLK	C93	Clock I/O line for the general purpose I2C0 port	I/O OD 3.3VSB	PU 4.7K 3.3VSB
I2C0_DAT	C94	Data I/O line for the general purpose I2C0 port	I/O OD 3.3VSB	PU 4.7K 3.3VSB
I2C0_ALERT#	C95	Alert input / interrupt for I2C0	I 3.3V	PU 10K 3.3VSB
I2C1_CLK	C96	Clock I/O line for the general purpose I2C1 port	I/O OD 1.8VSB	PU 4.7K 1.8VSB
I2C1_DAT	C97	Data I/O line for the general purpose I2C1 port	I/O OD 1.8VSB	PU 4.7K 1.8VSB

4.3.8 eSPI

Name	Pin #	Description	I/O	PU / PD	Comment
eSPI_IO0	A50	eSPI Master Data Input / Outputs. These are bi directional input/output pins used to transfer data between master and slaves.	I/O	PU 10K
eSPI_IO1	A51		CMOS	1.8VSB
eSPI_IO2	A52		1.8VSB
eSPI_IO3	A53
eSPI_CS0#	B54	eSPI Master Chip Select Outputs. A low selects a particular eSPI slave for the transaction. Each of the eSPI slaves is connected to a dedicated Chip Select pin. If an eSPI_CSx# pins is not in use, it shall be either pulled high or actively driven high.	O	PU 10K
eSPI_CS1#	B55		COMS	1.8VSB
			1.8VSB
eSPI_CLK	A54	eSPI Master Clock Output. This pin provides the reference timing for all the serial input and output operations.	O	PU 10K
			CMOS	1.8VSB
eSPI_ALERT0#	B52	eSPI pins used by eSPI slave to request service from the eSPI master.	I	PU 10K
eSPI_ALERT1#	B53		COMS	1.8VSB
			1.8VSB
ESPI_RST#	B56	eSPI Reset - resets the eSPI interface for both master and slaves. eSPI_RST# is typically driven from the eSPI master to eSPI slaves.	O	PU 10K
			CMOS	1.8VSB

4.3.9 Boot SPI (BIOS ONLY) and Boot Select

Name	Pin #	Description	I/O	PU / PD	Comment
BOOT_SPI_CS#	B48	Chip select for Carrier Board SPI. See Table 20 "BIOS Select Options: Module eSPI and SPI Chip Select Routing" for implementation details. If the BOOT_SPI_CS# pin is not in use, it shall be either pulled high or actively driven high.	O VCC_BOOT_SPI	PU 10K
BOOT_SPI_IO0	C50	Bidirectional 4 bit data path out of and into a Carrier SPI flash operating in Serial Quad Interface (SQI) mode. If the flash memory device is operating in traditional Serial Peripheral Interface (SPI) mode, then signal BOOT_SPI_IO0 is used for getting serial data into the flash device (referred to as SI or MOSI	I/O CMOS VCC_BOOT_SPI		BOOT_SPI_IO2 and BOOT_SPI_IO3: Not Supported
BOOT_SPI_IO1	C51
BOOT_SPI_IO2	C52
BOOT_SPI_IO3	C53
		in SPI Flash data sheets) and signal BOOT_SPI_IO1 is used to get serial data from the flash device (referred to as SO or MISO in flash data sheets)
BOOT_SPI_CLK	C54	Clock from Module chipset to Carrier SPI	O VCC_BOOT_SPI		Clock support is 48MHz, can be adjusted by project basis
VCC_BOOT_SPI	B47	Power supply for Carrier Board SPI – sourced from Module – nominally either 1.8V or 3.3V. The Module shall provide a minimum of 100mA on VCC_BOOT_SPI. Carriers shall use less than 100mA from this power source.VCC_BOOT_SPI shall only be used to power SPI devices on the Carrier Board.The Module vendor may choose what power domains the BOOT_SPI is active in.	O 3.3VSB
BSEL2	B51	Boot Select pins. These pins distinguish between a	I	PU 10K
BSEL1	B50	SPI or eSPI BIOS boot and between an on—Module or off-Module BIOS. Details are in Table 20: BIOS Select Options: Module eSPI and SPI Chip Select Routing.
BSEL0	B49	Pulled up on Module to vendor specific power rail

# 4.3.10 Port 80 Support on USB\_PD I2C Bus COM-HPC Module should support exporting Port 80 information over the USB\_PD I2C bus (signals USB\_PD\_I2C\_DAT and USB\_PD\_I2C\_CLK) (pin B36 and B35) to Carrier hardware that implements a pair of 7-segment displays to show the codes.

Name	Pin #	Description	I/O	PU / PD	Comment
USB_PD_I2C_DAT	B36	I2C data line between Module based Embedded Controller master and Carrier based USB Power Delivery Controller slave.	OD3.3VB	PU 4K73.3VSB
USB_PD_I2C_CLK	B35	I2C clock line between Module based Embedded Controller master and Carrier based USB Power Delivery Controller slave.	OD3.3VSB	PU 4K73.3VSB
USB_PD_ALERT#	B34	I2C clock line between Module based Embedded Controller master and Carrier based USB Power Delivery Controller slave.	$\frac{1}{3.3VSB}$		Not Supported

# 4.3.11 IPMB The IPMB (Intelligent Platform Management Bus) is used (optionally) with a Carrier based BMC (Board Management Controller) Master. On the module, the IPMB should be routed to and used with an MMC (Module Management Controller). The Module IPMB is a slave port.

Name	Pin #	Description	I/O	PU / PD	Comment
IPMB_CLK	B91	Clock I/O line for the multi-master IPMB port	I/O ODCMOS3.3VB	PU 47K3.3VSB
IPMB_DAT	B92	Data I/O line for the multi-master IPMB port	I/O ODCMOS3.3VSB	PU 47K3.3VSB

4.3.12 General Purpose SPI

Name	Pin #	Description	I/O	PU / PD	Comment
GP_SPI_MISO	B94	Serial data into the COM-HPC Module from the Carrier GP_SPI device ("Master In Slave Out")	13.3V	PU 10K	Not supported
GP_SPI_MOSI	B93	Serial data from the COM-HPC Module to the Carrier GP_SPI device ("Master Out Slave In")	03.3V		Not supported
GP_SPI_CLK	B99	Clock from the Module to Carrier GP_SPI device	03.3V		Not supported
GP_SPI_CS0#	B95	GP_SPI chip selects, active low	03.3V		Not supported
GP_SPI_CS1#	B96
GP_SPI_CS2#	B97
GP_SPI_CS3#	B98
GP_SPI_ALERT#	B100	Alert (interrupt) from a Carrier GP_SPI device to the Module	13.3V	PU 10K	Not supported

4.3.13 Power & System Management

Name	Pin #	Description	I/O	PU / PD	Comment
PWRBTN#	B02	A falling edge creates a power button event. Power button events can be used to bring a system out of S5 soft off and other suspend states, as well as powering the system down.	I 3.3VSB	PU 4K73.3VSB
RSTBTN#	C02	Reset button input. Active low request for Module to reset and reboot. May be falling edge sensitive. For situations when RSTBTN# is not able to reestablish control of the system, VIN_PWR_OK or a power cycle may be used.	I 3.3VSB	PU 10K3.3VSB
PLTRST#	A12	Platform Reset: output from Module to Carrier Board. Active low. Issued by Module chipset and may result from a low RSTBTN# input, a low VIN_PWR_OK input, a VCC power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the Module software..	O 3.3VSB
VIN_PWR_OK	C06	Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow Carrier based FPGAs or other configurable devices time to be programmed.	I 3.3V	PU 10K3.3VSB
SUS_S3#	B08	Indicates system is in Suspend to RAM state. Active low output. An inverted copy of SUS_S3# on the Carrier Board should be used to enable the non-standby power on a typical ATX supply.Even in single input supply system implementations (AT mode, no standby input), the SUS_S3# Module output should be used disable any Carrier voltage regulators when SUS_S3# is low, to prevent bleed leakage from Carrier circuits into the Module.	O 3.3VSB
SUS_S4_S5#	C08	Indicates system is in Suspend to Disk (S4) or Soft Off (S5) state. Active low output.	O 3.3VSB
SUS_CLK	A87	32.768 kHz +/- 100 ppm clock used by Carrier peripherals such as M.2 cards in their low power modes.	O 3.3VSB
WAKE0#	D10	PCI Express wake up signal.	I/O 3.3VSB	PU 10K3.3VSB
WAKE1#	D11	General purpose wake up signal. May be used to implement wake-up on PS2 keyboard or mouse activity.	I 3.3VSB	PU 10K3.3VSB
BATLOW#	A11	Indicates that external battery is low.This port provides a battery-low signal to the Module for orderlytransitioning to power saving or power cut-off ACPI modes.	I 3.3VSB	PU 10K3.3VSB
TAMPER#	B06	Tamper or Intrusion detection line on VCC_RTC power well. Carrier hardware pulls this low on a Tamper event.			Not Supported
RSMRST_OUT#	B86	This is a buffered copy of the internal Module RSMRST# (Resume Reset, active low) signal. The internal Module RSMRST# signal is an input to the chipset or SOC and when it transitions from low to high it indicates that the suspend well power rails are stable.USB devices on the Carrier that are to be active in S5 / S3 / S0 should not have their 5V supply applied before RSMRST_OUT# goes high.RSMRST_OUT# shall be a 3.3V CMOS Module output, active in all power states.	O 3.3VSB

# 4.3.14 Rapid Shutdown

Name	Pin #	Description	I/O	PU / PD	Comment
RAPID_SHUTDOWN	E1	Trigger for Rapid Shutdown. Must be driven to 5V though a <=50 ohm source impedance for ≥20 μs. Pull-down / disable on Module if RAPID_SHUTDOWN pin is not asserted.	I-5VSB		Not supported

# 4.3.15 Thermal Protection

Name	Pin #	Description	I/O	PU / PD	Comment
CARRIER_HOT#	C04	Input from off-Module temp sensor indicating an over-temp situation.	I 3.3V	PU 100K3.3V
THERMTRIP#	B04	Active low output indicating that the CPU has entered thermal shutdown.	O 3.3V	PU4.99K3.3V

4.3.16 SMBus

Name	Pin #	Description	I/O	PU / PD	Comment
SMB_CLK	C86	System Management Bus bidirectional clock line.	I/O OD 3.3VSB	PU 4.7K 3.3VSB	The maximum capacitance on the Carrier Board shall not exceed 100pF
SMB_DAT	C87	System Management Bus bidirectional data line.	I/O OD 3.3VSB	PU 4.7K 3.3VSB	The maximum capacitance on the Carrier Board shall not exceed 100Pf
SMB_ALERT#	C88	System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system.	I 3.3VSB	PU 4.7K 3.3VSB	The maximum capacitance on the Carrier Board shall not exceed 100pF

4.3.17 General Purpose Input Outputs

Name	Pin #	Description	I/O	PU / PD	Comment
GPIO_00	A88	General purpose input / output pins. Upon a hardware reset, these pins should be configured as inputs.	I/O 3.3V	PU 100K3.3V
GPIO_01	A89
GPIO_02	A90
GPIO_03	A91
GPIO_04	A92	As inputs, these pins should be able to generate an interrupt to the Module host.
GPIO_05	A93
GPIO_06	A94
GPIO_07	A95
GPIO_08	A96
GPIO_09	A97
GPIO_10	A98
GPIO_11	A99

4.3.18 Module Type Definition

Name	Pin #	Description					I/O	Comment
TYPE0	A100	The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the Module. The pins are tied on the Module to either ground (GND) or are no-connects (NC). These pins shall be pulled up on the Carrier, to Carrier standby voltage rail of 5V or less. Carrier hardware reads the level on these straps.						Server Module – Fixed 12V input
TYPE1	C100
TYPE2	D100
		Module Connections				Meaning
		Ref	TYPE2	TYPE1	TYPE0
		7	NC	NC	NC	Reserved
		6	NC	NC	GND	Reserved
		5	NC	GND	NC	Reserved
		4	NC	GND	GND	Server Module – Fixed 12V input
		3	GND	NC	NC	Reserved
		2	GND	NC	GND	Reserved
		1	GND	GND	NC	Client Module - Wide Range 8V to 20V input
		0	GND	GND	GND	Client Module – Fixed 12V input
		The Module shall implement all three TYPE[x] pins per the table above.
		The Carrier Board should implement combinatorial logic that monitors the Module TYPE pins and keeps power off (e.g deactivates the ATX PS_ON# signal to an ATX power supply or otherwise deactivates VCC to the COM-HPC Module) if an incompatible Module pin-out type is detected. All three TYPE[x] pins should be monitored by the Carrier. The Carrier Board logic may also implement a fault indicator such as an LED.

4.3.19 Miscellaneous Signals

Name	Pin #	Description	I/O	PU / PD	Comment
WD_OUT	B11	Output indicating that a watchdog time-out event has occurred. Refer to Section 5.3 for details.	O 3.3V
WD_STROBE#	B10	Strobe input to watchdog timer. Periodic strobing prevents the watchdog, if enabled, from timing out.	I 3.3V	PU 100K 3.3V
FAN_PWMOUT	C11	Fan speed control for a secondary system fan. The primary fan control signals for CPU thermal management are on the Module, along with a vendor specific connector.Fan controls use the Pulse Width Modulation (PWM) technique to control the fan's RPM. CMOS output; Carrier designers should buffer this signal with an open drain FET and pullup or other robust Carrier device(s).	O 3.3V
FAN_TACHIN	C12	Fan tachometer input for a fan with a two pulse output for the secondary fan.	I OD 3.3V	PU 10K 3.3V
RSVD		Reserved pins. These may be assigned functions in future versions of this specification. Reserved pins shall not be connected to anything, and shall not be connected to each other.

4.3.20 Power and Ground

Name	Pin #	Description	I/O	PU / PD	Comment
VCC	A01-A09B01B03B05B07B09C01C03C05C07C09D01-D09	Primary power input:fixed +12V on the Client Type 0; wide range +8V to +20V on the Client Type 1; fixed +12V on the Server.All available VCC pins on the connector shall be used.	P		12V +/- 5%
VCC_5V_SBY	B24	Standby power input: +5.0V nominal.Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.	P		Not Supported
VCC_RTC	A86	Real-time clock circuit-power input. Nominally +3.0V.	P
GND		Ground - DC power and signal and AC signal return path.All available GND connector pins shall be used and tied to Carrier Board GND plane(s).	P

# 5. Additional Features This chapter describes the connectors, LEDs, and switches, located on the module and are not necessarily included in the PICMG standard specification. The locations of these parts are as shown below: XDP debug header (Chris) ![40-pin\nDebug\nConnect\nFan Connector\nCOM·HPC® ADLINK\nBIOS\nDefault\nReset](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/d0b717ddc9cd94f2d38513210a6b6ce2fdde4eb631e9ba39291942fd7c4a267b.jpg) Figure 3 – Module feature locations (front) ![BIOS setting switch\nMMC switch\n(for debug only)](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/8577c7883fffe4a77adfa36a565c91297d728af51e9e29d8784b71016b9bdc34.jpg) Figure 4 – Module feature locations (bottom) # 5.1 Debug Connector (40-pin connector) This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: Test points for measurement of internal power rails SPI BIOS programming interface I2C bus for BIOS POST code readout Module EC and MMC programming interface # 5.2 Status LEDs Status LEDs are mounted on the module as below ![Close-up of a black electronic circuit board with integrated circuits and connectors (no visible text or symbols)](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/65f37bf98299c0e200c0a8339c828f00a212813dc9a2621a7487c98d91aa6f82.jpg)

Name	Color	Connection	Function
LED1	Blue	BMC output	Power Sequence Status Code (BMC) Power Changes, Reset (see Exception Codes Table below)
LED2	Green	Power Source 3Vcc	S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF
LED3	Red	BMC output and same signal as WDT (B27) on BtB connector	Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a Reset not initiated by the BMC can clear the WD LED (user action)

5.3 Exception Codes

Exception Code	Error Message
0	NOERROR
3	NO_SLP_S5
4	NO_SLP_S4
5	NO_SLP_S3
6	BIOS_FAIL
7	RESET_FAIL
9	NO_CB_PWROK
10	CRITICAL_TEMP
11	POWER_FAIL
12	VOLTAGE_FAIL
13	RSMRST_FAIL
14	NO_VDDQ_PG
16	NO_VCORE_PG
17	NO_SYS_GD
19	NO_V3P3A
21	NO_PWRSRC_GD
24	NO_PCH_PG

# 5.4 Fan Connector Connector Type: JVE 24W1125A-04M00 ![Close-up of a printed circuit board with integrated circuits and components (no visible text or symbols)](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/009c955f1bc8b121df8576674cc8c0c56adb85c71f2a8b23d0b521c4ce1edb4b.jpg)

Name	Description
1	FAN_PWMOUT
2	FAN_TACHIN
3	GND
4	12V*

The supply voltage and maximum current of the fan connector is dependent on the module’s input voltage (VCC\_12V pins) # 5.5 BIOS Default Reset ![The image displays a vertical black printed circuit board featuring a red arrow pointing rightward towards a central silver rectangular connector. White text labels 'U1' and 'U2' are printed on the board near small surface-mount components and silver solder points.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/7be43bf9a760215ec2a1bc98f07425e3b11add4b2fdd0b9cc082f48163cd5cfb.jpg) To perform a hardware reset of the default BIOS settings, follow the steps below: 1. Shut down the system. 2. Hold down the BIOS Setup Defaults Reset Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears. 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. ![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\nExpress-HL REV:1.04\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.\nDefault settings had been loaded due to BIOS_DEFAULT jumper is set!\nPlease turn off system power and remove BIOS_DEFAULT jumper!](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/cc1f5ce712ec6f246107cf0877075cf0ca2b3719f644af98cb0ba29f6233d3e4.jpg) # 5.6 BIOS Boot Select The module has two BIOS chips (BOM option) and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe" modes using the BIOS Select and Mode Configuration Switch, Pin 2. Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip cannot be placed in the SPI0 slot on the carrier. In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module. In Failsafe mode, the SPI0 BIOS socket on the carrier can be populated. In either mode, BIOS Select and Mode Configuration Switch, Pin 1 is used to select whether to boot from SPI0 or SPI1.

Mode	Pin 1	Pin 2
Boot from SPI0 (default)	On	-
Boot from SPI1	Off	-
Set BIOS to PICMG mode (default, TBC)	-	On
Set BIOS to Failsafe BIOS mode	-	Off

# 5.7 MIPI 60 Debug Header The MIPI60 debug header is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources.

Pin	MIPI60 Signal	Pin	MIPI60 Signal
1	VREF_DEBUG	2	TMS/TMSC
3	TCK	4	TDO/EXTA
5	TDI/EXTB	6	nRESET
7	RTCK/EXTC	8	TRST_PD
9	nTRST/EXTD	10	EXTE/TRIGIN
11	EXTF/TRIGOUT	12	VERF_TRACE
13	TRC_CLK[0]	14	TRC_CLK[1]
15	Target Presence Detection	16	GND
17	TRC_DATA[0][0]	18	TRC_DATA1[0] / TRC_DATA0[10]
19	TRC_DATA[0][1]	20	TRC_DATA1[1] / TRC_DATA0[21]
21	TRC_DATA[0][2]	22	TRC_DATA1[2] / TRC_DATA0[22]
23	TRC_DATA[0][3]	24	TRC_DATA1[3] / TRC_DATA0[23]
25	TRC_DATA[0][4]	26	TRC_DATA1[4] / TRC_DATA0[24]
27	TRC_DATA[0][5]	28	TRC_DATA1[5] / TRC_DATA0[25]
29	TRC_DATA[0][6]	30	TRC_DATA1[6] / TRC_DATA0[26]
31	TRC_DATA[0][7]	32	TRC_DATA1[7] / TRC_DATA0[27]
33	TRC_DATA[0][8]	34	TRC_DATA1[8] / TRC_DATA0[28]
35	TRC_DATA[0][9]	36	TRC_DATA1[9] / TRC_DATA0[29]
37	TRC_DATA3[0] / TRC_DATA0[10]	38	TRC_DATA2[0] / TRC_DATA1[10] / TRC_DATA0[30]
39	TRC_DATA3[1] / TRC_DATA0[11]	40	TRC_DATA2[1] / TRC_DATA1[11] / TRC_DATA0[31]
41	TRC_DATA3[2] / TRC_DATA0[12]	42	TRC_DATA2[2] / TRC_DATA1[12] / TRC_DATA0[32]
43	TRC_DATA3[3] / TRC_DATA0[13]	44	TRC_DATA2[3] / TRC_DATA1[13] / TRC_DATA0[33]
45	TRC_DATA3[4] / TRC_DATA0[14]	46	TRC_DATA2[4] / TRC_DATA1[14] / TRC_DATA0[34]
47	TRC_DATA3[5] / TRC_DATA0[15]	48	TRC_DATA2[5] / TRC_DATA1[15] / TRC_DATA0[35]
49	TRC_DATA3[6] / TRC_DATA0[16]	50	TRC_DATA2[6] / TRC_DATA1[16] / TRC_DATA0[36]
51	TRC_DATA3[7] / TRC_DATA0[17]	52	TRC_DATA2[7] / TRC_DATA1[17] / TRC_DATA0[37]
53	TRC_DATA3[8] / TRC_DATA0[18]	54	TRC_DATA2[8] / TRC_DATA1[18] / TRC_DATA0[38]
55	TRC_DATA3[9] / TRC_DATA0[19]	56	TRC_DATA2[9] / TRC_DATA1[19] / TRC_DATA0[39]
57	Connect to GND plane	58	GND
59	TRC_CLK[3]	60	TRC_CLK[2]

# 6. System Resources 6.1 System Memory Map

Address Range (hex)	Description
23000000000-23FFFFFFF	PCI Express Root Complex
22000000000-22FFFFFFF	PCI Express Root Complex
22FB8000000-22FFC4FFFF	PCI Express Root Complex
21000000000-21FFFFFFF	PCI Express Root Complex
20000000000-20FFFFFFF	PCI Express Root Complex
20FFFA99000-20FFFA99FFF	CDF ME: HECI#1 – 18D3
20FFFA98000-20FFFA98FFF	CDF ME: HECI#3 – 18D6
20FFFA97000-20FFFA97FFF	SDA Standard Compliant SD Host Controller
20FFFA96000-20FFFA96FFF	Intel USB 3.0 eXtensible Host Controller
20FFFA20000-20FFFA3FFF	CDF PCIe RP[8]-18AD
20FFFA00000-20FFFA1FFF	CDF PCIe RP[9]-18AE
FF000000-FFFFFFFF	Motherboard resource
FED00000-FED003FF	Hight precision event timer
FEC00000-FECFFFFF	Advance programmable interrupt controller
FE200000-FE7FFFF	Motherboard resources
FE000000-FE01FFF	Motherboard resources
FD6F0000-FDFFFFFF	Motherboard resources
FD000000-FD69FFFF	Motherboard resources
E1000000-FB7FFFF	PCI Express Root Complex
C6000000-E0FFFFFF	PCI Express Root Complex
AB000000-C5FFFFFFF	PCI Express Root Complex
90000000-AAFFFFFFF	PCI Express Root Complex
000C8000-000CFFFF	PCI Express Root Complex
000A0000-000BFFFF	PCI Express Root Complex

6.2 I/O Map

Hex Range	Device
00h - 0Fh	DMA controller
00h – CF7h	PCI Express Root Complex
10h - 1Fh	Motherboard resources
20h – 3Dh	Programmable interrupt controller
2Eh - 2Fh4Eh - 4Fh	LPC SIO (IT5121E/AST2500SEC) configuration index/data registers
40h - 43h	System Timer
50h - 53h	System Timer
62h and 66h	ACPI-Compliant Embedded Controller
70h - 77h	Real Time Clock Controller
81h - 83h, 87h, 89h - 8Bh and8Fh	DMA controller
90h - 9Fh	Motherboard resources
A0h - BDh	Programmable interrupt controller
C0h – DFh	Direct memory assess controller
F0h	Numeric data processor
262h – 263h	Generic IPMI Compliant Device
2F8h – 2FFh	Serial port 2 (COM4)
3B0h – 3BBh	CDF PCIeRP[9]-18AE
3C0h – 3CFh	CDF PCIeRP[9]-18AE
3F8h - 3FFh	Serial port 1 (COM1)
400h - 41Fh	Motherboard resources
4D0h – 4D1h	Programmable interrupt controller
500h – A6Fh	Motherboard resources
1000h – 5FFFh	PCI Express Root Complex
4000h – 407Fh	Microsoft Basic display Complex
5020h – 503Fh	SATA AHCI Controller
5070h – 5073h
5080h – 5087h
6000h – 9FFFh	PCI Express Root Complex
A000h - CFFFh	PCI Express Root Complex
D000h - FFFFh	PCI Express Root Complex

6.3 Interrupt Request (IRQ) Lines

IRQ#	Typical Interrupt Resource	Connected to Pin	Available
0	High precision even timer/System timer		No
3	Serial Port 4		No
4	Serial Port 1		No
8	System CMOS/Real time clock		No
11	CDF ME:HECI		No
13	Numeric data processor		No

6.4 PCI Configuration Space Map

Bus Number	Device Number	Function Number	Routing	Description
00h	00h	00h	Internal	Mesh2IIO MMAP/VT-D
00h	00h	01h	Internal	Mesh2IIO PMON
00h	00h	02h	Internal	Mesh2IIO RAS
00h	00h	03h	Internal	Mesh2IIO DFX
00h	00h	04h	Internal	Satellite IEH
00h	00h	05h	Internal	VMD
00h	01h	00h	Internal	CBDMA CH0
00h	01h	01h	Internal	CBDMA CH1
00h	01h	02h	Internal	CBDMA CH2
00h	01h	03h	Internal	CBDMA CH3
00h	01h	04h	Internal	CBDMA CH4
00h	01h	05h	Internal	CBDMA CH5
00h	01h	06h	Internal	CBDMA CH6
00h	01h	07h	Internal	CBDMA CH7
00h	02h	00h	Internal	PECI Out-Of-Band Management Services Module (OOB-MSM)
00h	02h	01h	Internal	PECI OOB-MSM - Performance Monitoring Unit (PMU)
00h	02h	02h	Internal	Reserved
00h	02h	04h	Internal	CPU Intel® Trace Hub
00h	06h	00h	Internal	Virtual Root Port (VRP) for Intel QAT v1.7
00h	00h	PF: 0VF: 0-15	Internal	Intel QAT v1.7 (Bus subordinate to S0 VRPis assigned by BIOS)

00h	0Eh	00h	Internal	SATA Controller 2
00h	0Fh	00h	Internal	Host SMBUS
00h	14h	00h	Internal	PCH PCIe Cluster 2 Root Port 8
00h	15h	00h	Internal	PCH PCIe Cluster 2 Root Port 9
00h	18h	00h	Internal	Intel® ME - HECI 1
00h	18h	04h	Internal	Intel® ME - HECI 3
00h	1Ah	00h	Internal	HSUART 0
00h	1Ah	01h	Internal	HSUART 1
00h	1Ah	02h	Internal	HSUART 2
00h	1Ah	03h	Internal	Reserved
00h	1Ch	00h	Internal	eMMC Controller
00h	1Dh	00h	Internal	Host Bridge
00h	1Eh	00h	Internal	USB xHCI Controller
00h	1Fh	00h	Internal	LPC/eSPI Controller
00h	1Fh	04h	Internal	Legacy SMBUS
00h	1Fh	05h	Internal	SPI Controller
00h	1Fh	07h	Internal	PCH Intel® Trace Hub
01h	00h	00h	Internal	Intel Ethernet controller
02h	00h	00h	Internal	PCI Bridge
03h	00h	00h	External	AST2500
15h	00h	00h	Internal	Mesh2IIO MMAP/VT-D
15h	00h	01h	Internal	Mesh2IIO PMON
15h	00h	02h	Internal	Mesh2IIO RAS
15h	00h	03h	Internal	Mesh2IIO DFX
84h	00h	00h	Internal	Mesh2IIO MMAP/VT-D
84h	00h	01h	Internal	Mesh2IIO PMON
84h	00h	02h	Internal	Mesh2IIO RAS
84h	00h	03h	Internal	Mesh2IIO DFX
84h	00h	04h	Internal	Host Bridge
84	04h	00h	Internal	Virtual Root Port for Network Interface and Scheduler
85h	00h	00h	Internal	Intel Ethernet Controller
85h	00h	01h	Internal	Intel Ethernet Controller
85h	00h	02h	Internal	Intel Ethernet Controller
85h	00h	03h	Internal	Intel Ethernet Controller
85h	00h	04h	Internal	Intel Ethernet Controller
85h	00h	05h	Internal	Intel Ethernet Controller
85h	00h	06h	Internal	Intel Ethernet Controller
85h	00h	07h	Internal	Intel Ethernet Controller
8Ch	00h	00h	Internal	Mesh2IIO MMAP/VT-D
8Ch	00h	01h	Internal	Mesh2IIO PMON
8Ch	00h	02h	Internal	Mesh2IIO RAS
8Ch	00h	03h	Internal	Mesh2IIO DFX
8Ch	00h	04h	Internal	Satellite IEH



FEh	00h	00h	Internal	UBOX - Global Events
FEh	00h	01h	Internal	UBOX
FEh	00h	02h	Internal	UBOX -DEC
FEh	00h	03h	Internal	UBOX - Global IEH
FEh	00h	05h	Internal	MS2UBOX
FEh	0Bh	00h	Internal	SPD0_SMBUS
FEh	0Bh	01h	Internal	SPD1_SMBUS
FEh	0Bh	02h	Internal	VPP_SMBUS
FEh	0Ch	00h	Internal	Mesh2IMC0
FEh	0Dh	00h	Internal	Mesh2IMC0
FEh	1Ah	00h	Internal	IMC0
FEh	1Bh	00h	Internal	IMC0
FFh	00h	00h	Internal	CHA0_GRP1 - UNICAST_GROUP1_CHA
FFh	00h	01h	Internal	CHA1_GRP1 - UNICAST_GROUP1_CHA
FFh	00h	02h	Internal	CHA2_GRP1 - UNICAST_GROUP1_CHA
FFh	00h	03h	Internal	CHA3_GRP1 - UNICAST_GROUP1_CHA
FFh	00h	04h	Internal	CHA4_GRP1 - UNICAST_GROUP1_CHA
FFh	00h	05h	Internal	CHA5_GRP1 - UNICAST_GROUP1_CHA
FFh	0Ah	00h	Internal	CHA0_GRP0 - UNICAST_GROUP0_CHA
FFh	0Ah	01h	Internal	CHA1_GRP0 - UNICAST_GROUP0_CHA
FFh	0Ah	02h	Internal	CHA2_GRP0 - UNICAST_GROUP0_CHA
FFh	0Ah	03h	Internal	CHA3_GRP0 - UNICAST_GROUP0_CHA
FFh	0Ah	04h	Internal	CHA4_GRP0 - UNICAST_GROUP0_CHA
FFh	0Ah	05h	Internal	CHA5_GRP0 - UNICAST_GROUP0_CHA
FFh	1Dh	00h	Internal	CHAALL0 - Multicast DRAM Rules
FFh	1Dh	01h	Internal	CHAALL1 - Multicast MMIO Rules
FFh	1Eh	00h	Internal	PCU
FFh	1Eh	01h	Internal	PCU
FFh	1Eh	02h	Internal	PCU
FFh	1Eh	03h	Internal	PCU
FFh	1Eh	04h	Internal	PCU
FFh	1Eh	05h	Internal	PCU
FFh	1Eh	06h	Internal	PCU
FFh	1Eh	07h	Internal	PCU

6.5 PCI Interrupt Routing Map

INT Line	PCI Express Port 0	Crystal Beach DMA Engine0	Lpc Bridge	HECI #1 on PCH	SMBus controller on PCH	SATA Controller
Int0	INTA:16	INTA:16		INTA:16		INTA:16
Int1	INTB:17				INTB:17
Int2	INTC:18		INTC:18
Int3	INTC:19

INT Line	XHCI Controller	Intel I210
Int0	INTA:16	INTA:16
Int1
Int2
Int3

INT Line	PCIE Port1	PCIE Port 2	PCIE Port 3	PCIE Port 4	PCIE Port 5	PCIE Port 6	PCIE Port 7	PCIE Port 8
Int0	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Int1	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Int2	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Int3	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A

6.6 SMBus Address Table

Device	Address
DDR4 Channel A(SO-DIMM1)	A0h
DDR4 Channel B(SO-DIMM2)	A2h
DDR4 Channel C(SO-DIMM3)	A4h
DDR4 Channel D(SO-DIMM4)	A6h
Thermal Sensor	90h
Thermal Sensor	92h

# 7. BIOS Setup # 7.1 Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table ► indicates a submenu

Main	Platform Configuration	Advanced	Socket Configuration	Server Mgmt	Security
BIOS InformationSystem InformationBoard Information►System DateSystem Time	PCH-IO Configuration►Miscellaneous Configuration►Network Configuration►Server ME Configuration►iRC Firmware Information►System Event Log►Reserve Memory►	Serial Port ConsoleRedirection ►PCI Subsystem Settings ►Power Management ►System Management ►Thermal Management ►Watchdog Timer ►Super IO Configuration ►Miscellaneous ►Network Stack Configuration ►Trusted Computing ►	Processor Configuration►Common RefCode Configuration►Uncore Configuration►Memory Configuration►IIO Configuration►Advanced Power ManagementConfiguration►	BMC SupportIPMI Interface TypeWait for BMCFRB-2 TimerFRB-2 Timer timeoutFRB-2Timer Policy OS WatchdogTimer Serial MuxSystem Event Log►Bmc self test log►BMC network configuration►View System EventLog►BMC User Settings►BMC warm reset	Password DescriptionSecure BootMenu

Boot	Save & Exit
Boot Configuration	Save OptionsDefault OptionsBoot Override

# 8. BIOS Checkpoints, Beep Codes A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. The Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes. Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but the Aptio 5.x core can be configured to send checkpoints to a variety of sources. The Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware. A beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process. ![The image displays a red icon resembling a document or file. It features a thick red outline in the shape of a square with the bottom-right corner folded inward. Inside the outline, there are three horizontal red lines stacked vertically.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/96bbd58f5045bb2253af00fc1df4534c6c7937ae7bcddefccf0036519882b874.jpg) Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify the user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes # Viewing Checkpoints Checkpoints generated by the Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-on cards show the value of I/O port 80h on an LED display. # Aptio V Checkpoint and Beep Codes Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes # 9. Software Support 9.1. Windows Server 2019 64-bit 9.2. Windows 10 IoT Enterprise 64-bit 9.3. Yocto Linux 64-bit (TBC) https://github.com/ADLINK/meta-adlink-x86-64bit (TBC) # 10. Mechanical ![95\n91\n90.73\n91\n26.56\n4\n0\n0 4\n50.24\n72.68\n80\n121\n125\n4](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/86b682f39d3d5cee212df4f5a47f655b3eb9627f2ab969eb563b07a297ae0c81.jpg) ![Top View\n9.25 ±0.25\n2\n8.05 ±0.25\nFront View](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/286df89eeae8ec1925f32436ef42786b0d8e2f6eba3eb297a360803107bf8e18.jpg) ![91\n87.25\nBottom Side RAM\nModule Keepout\n8.35\n125\n121\n86.94\n80\n74.2\n72.676\n50.235\n16.5\n4\n0\n95\n91\n90.73\n26.56\n18\n6\n4\n0](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/14495d273c6f55f445d260bdfe3d2aeb02581658b5564cb6db3baf21ca7df979.jpg) Bottom View All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. Dimensions: mm Figure 5 – Module mechanical dimensions # 11. Thermal # 11.1. Thermal Solutions # 11.1.1 Heatspreader: HTS ![The image displays a technical CAD render of an electronic assembly with multiple orthographic and isometric views. In the top right corner, the text 'Dimensions: mm' is visible.\n\n**Top Row:**\n* **Left:** A side profile view showing vertical dimensions of **15.6** and **4.6**.\n* **Center:** An isometric view of the assembly featuring a central component and heat sinks. An annotation points to fasteners reading '**M2.5 x 4pcs**'.\n* **Right:** An isometric view of the top plate. An annotation points to fasteners reading '**M3 x 4pcs**'.\n\n**Bottom Row:**\n* **Left:** A front view of a rectangular plate with dimensions: total width **80**, total height **110**, horizontal screw spacing **46**, and vertical screw spacing **69.2**.\n* **Center:** A side profile view showing the assembly's thickness and mounting posts.\n* **Right:** A rear view of the plate showing the mounted component and heat sink structure. The dimensions are total width **100** and total height **160**.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/b7a89d48ef5f5fb4bdadcb309c10f5567628decc54e8fbb6cb892410b6a05a44.jpg) Dimensions: mm Figure 6 – Heatspreader: HTS # 11.1.2 Heatsink: THS-BL Dimensions: mm ![The image displays six technical renderings of a rectangular mechanical component, likely a heatsink or electronic module.\n\n* **Top Left:** A side profile view showing vertical fins with dimensions labeled '36.6' for total height and '26' for the upper section height.\n* **Top Center:** An isometric view of the top surface featuring a central blue square, orange pathways, and yellow rectangular components.\n* **Top Right:** An isometric view showing the finned exterior casing.\n* **Bottom Left:** A front view of the fins showing four mounting holes, with dimensions '69.2' indicating vertical spacing and '46' indicating the bottom width.\n* **Bottom Center:** A side profile view showing the device's depth.\n* **Bottom Right:** A rear view showing the internal layout similar to the top view, with dimensions '160' indicating total height and '86' indicating width.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/cb8234f0305b23c44715bd27a0bdbe75012d625e392ed78a1737747d6b535b2c.jpg) Figure 7 – Heatsink: THS-BL # 11.1.3 Heatsink with Fan: THSF Dimensions: mm ![This image displays a technical CAD rendering of a computer cooling system, likely for a graphics card, presented through multiple orthographic and isometric views.\n\n**Top Row:**\n* **Left:** A side elevation view showing the profile of the heatsink and fan assembly. A vertical dimension line indicates a height of **55.1**.\n* **Center:** An isometric view of the heatsink base plate without the fan shroud. It shows copper heat pipes leading from a central blue square (contact area). A label points to the mounting screws with the text '**M2.5 (4)**'.\n* **Right:** An isometric view of the fully assembled cooler, featuring a black shroud housing two blue fans.\n\n**Bottom Row:**\n* **Left:** A front elevation view showing the two blue fans mounted vertically within the black shroud.\n* **Center:** A narrow side profile view showing the fin stack and side mounting plate.\n* **Right:** A top-down view of the heatsink base plate with dimensions labeled:\n * Total height: **160**\n * Total width: **86**\n * Vertical spacing between mounting holes: **69.2**\n * Horizontal spacing between the upper mounting holes: **46**](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/b80acce6f5c6f3694bb8c7bc292cb70664efa7c8f706f12d19d3069c5439eee5.jpg) Figure 8 – Heatsink with Fan: THSF # 11.1.4 Heatsink with Fan: THSF-BL-S Dimensions: mm ![The image displays a technical rendering of a computer cooling system from multiple angles, including dimensions and branding:\n\n* **Top Left:** A side profile view showing internal height dimensions of **19.4** and total height of **29.4**.\n* **Top Center:** An isometric view of the base plate (cold plate) without the fan housing.\n* **Top Right:** An isometric view of the assembled cooler. The text '**COM+HPC™**' is visible on the side.\n* **Bottom Left:** A front view of the heatsink and fan. Vertical dimension lines indicate a spacing of **69.2**, and a horizontal dimension indicates a spacing of **46** between mounting points.\n* **Bottom Center:** A thin side profile view featuring the text '**COM+HPC™**'.\n* **Bottom Right:** A rear view of the heatsink. The overall dimensions are marked as **160** in height and **86** in width.](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/8f9e069f67eb55c0ad1de0a80c20d6e4f649933445487a7b550cc5e6456a7580.jpg) Figure 9 – Heatsink with Fan: THSF-BL-S [🔗 Link to the original document](.com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826/com-hpc-sidh-50m-73103-1000-02-preliminary-manual-240826.pdf)