# cPCI-3510(BL) Series

Performance 3U CompactPCI® PlusIO Intel® Core™ i7/i5 Processor Blade

User's Manual

![Green ADLINK computer motherboard with visible ports, connectors, and a yellow logo (no readable text or symbols beyond branding)](.cpci-3510-50-15095-1040-24/7c46873b8700ad4f04eabb0fe9b4a1f18b270988fc78a1aae3cfd658e4007939.jpg)

Manual Rev.: 2.4

Revision Date: September 24, 2019

Part No: 50-15095-1040

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>26/03/2014</td><td>Initial release</td></tr><tr><td>2.01</td><td>17/11/2014</td><td>Correct Block Diagram SATA device support</td></tr><tr><td>2.02</td><td>11/12/2015</td><td>Add 5th Gen Intel ® CoreTM “BL” SKUs; minor corrections</td></tr><tr><td>2.3</td><td>11/12/2018</td><td>Remove note regarding programming of System LEDs</td></tr><tr><td>2.4</td><td>24/09/2019</td><td>Add layout drawings for cPCI-3510S; update DVI icon on front panels; clarification of “BL” models</td></tr></table>

# Preface

Copyright © 2014, 2015, 2018, 2019 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin with crossed lines indicating no waste or restriction, and a solid rectangle below (no text or labels)](.cpci-3510-50-15095-1040-24/73b553d9a580e7239dc89452401221f7820a62df8f99c550c69dc35b4c07a679.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.cpci-3510-50-15095-1040-24/040eb26a84a4d132877405f581a1bb64ba77f9c4b95eaddcf246e5eab4bb602e.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.cpci-3510-50-15095-1040-24/c9ca5a25b90638a3d6e1ae0db6056b8aee404e120d5c60be0210906c2e0da33c.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cpci-3510-50-15095-1040-24/2e330f231a37b738646c75c28b2794e833ae2c305c6d0c1e2c3bc5740e553ef7.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.cpci-3510-50-15095-1040-24/077ce6c1483c05e189a354452df0f9698241cb46250ef2805efceee23500e5b5.jpg)

廢電池請回收

# California Proposition 65 Warning

![The image displays a standard warning symbol. It features a yellow equilateral triangle with a thick black border. Centered inside the triangle is a large black exclamation point against the yellow background.](.cpci-3510-50-15095-1040-24/5d621a5c94c94a1fe5eca7119cb6a3bb3629e0cc8fb063225380f3d9905fb4b4.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a graphic of a white document or piece of paper with a folded top-right corner. Inside the document, there are faint horizontal lines resembling text or a list. Overlaid on top of the document is a large, bold, red checkmark that runs diagonally from the lower left to the upper right.](.cpci-3510-50-15095-1040-24/5278617f34814db0f463238643d56bff08dbf6af9885f88bc0cb5d75345682c9.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image shows a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. A small segment of a black horizontal line is visible along the very top edge.](.cpci-3510-50-15095-1040-24/dd6519b1a67e063484dbf4d6cae8b8361f28aae1be6aec1bdd082b251a89b600.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a triangular warning sign featuring a dark red triangle pointing upwards with a white exclamation mark centered inside it.](.cpci-3510-50-15095-1040-24/3ec181284b0ee55c66f28120c042699ae7e09b924a38cbb36c0dfa3cc652dab2.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Figures ix

# List of Tables.... xi

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 2
1.3 Model Number Decoder.... 3
1.4 Package Contents 5

# 2 Specifications.... 7

2.1 cPCI-3510(BL) Processor Blade Specifications .... 7
2.2 cPCI-R3P00(T) RTM Specifications 11
2.3 Block Diagrams.... 12
2.4 I/O Connectivity Table 19
2.5 Power Requirements 21

# 3 Functional Description 23

3.1 Processors.... 23
3.2 Chipset 25
3.3 PMC/XMC 25
3.4 Intel® Turbo Boost Technology 26
3.5 Intel® Hyper-Threading Technology 26
3.6 Trusted Platform Module 26
3.7 Battery 27

# 4 Board Interfaces.... 29

4.1 cPCI-3510(BL) Series Board Layout.... 29
4.2 cPCI-3510(BL) Blade Assembly Layout.... 31
4.3 cPCI-3510(BL)D Blade Assembly Layout 32
4.4 cPCI-3510(BL)G Blade Assembly Layout.... 33
4.5 cPCI-3510(BL)L Blade Assembly Layout.... 34
4.6 cPCI-3510(BL)M Blade Assembly Layout.... 35
4.7 cPCI-3510(BL)S Blade Assembly Layout 36
4.8 cPCI-3510(BL) Series Faceplate Layout 37
4.9 cPCI-R3P00(T) RTM Board Layout 40
4.10 cPCI-R3P00(T) RTM Faceplate 41
4.11 Connector Pin Assignments.... 42
4.12 Jumper Settings 67

# 5 Getting Started....69

5.1 CPU and Heatsink 69
5.2 SATA Drive Installation 70
5.3 Installing a CFast Card 73
5.4 Installing the cPCI-3510(BL) to the Chassis 74
5.5 RTM Installation - cPCI-R3P00(T) 75

# 6 Driver Installation.... 77

6.1 cPCI-3510(BL) Drivers.... 77
6.2 Ethernet Controller Driver 78
6.3 USB-to-Serial Converter Driver (RTM) 80

# 7 Watchdog Timer....83

7.1 Setting the Watchdog by IPMI Commands 83

# 8 BIOS Setup Utility 89

8.1 Starting the BIOS 89
8.2 Main Setup.... 94
8.3 Advanced BIOS Setup 95

8.3.1 ACPI Settings 96
8.3.2 Trusted Computing 97

8.3.3 CPU Configuration....98
8.3.4 SATA Configuration....99
8.3.5 PCH-FW Configuration.... 100
8.3.6 Intel ® Anti-Theft Technology Configuration...... 101
8.3.7 AMT Configuration.... 102
8.3.8 USB Configuration.... 103
8.3.9 Hardware Monitor 104
8.3.10 Super IO Configuration 105
8.3.11 Console Redirection 107

8.4 Chipset Setup 110

8.4.1 PCH-IO Configuration.... 111
8.4.2 System Agent (SA) Configuration.... 114

8.5 Boot Settings 118

8.5.1 CSM Parameter 119

8.6 Security Setup 121
8.7 Save & Exit Menu 122

# 9 IPMI User Guide.... 125

9.1 Introduction.... 125
9.2 Summary of Commands Supported by BMR-AVR-cPCI. 125
9.3 OEM Commands Summary Table.... 127
9.4 CompactPCI Address Map 130
9.5 Communications with IPMC.... 131
9.6 IPMI Sensors List.... 131
9.7 Relevant Documents 132

# Important Safety Instructions.... 133

# Getting Service.... 135

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# List of Figures

Figure 2-1: cPCI-3510(BL) Blade Functional Block Diagram...... 12

Figure 2-2: cPCI-3510(BL)D Daughter Board Func. Block Diagram 13

Figure 2-3: cPCI-3510(BL)G Daughter Board Func. Block Diagram 14

Figure 2-4: cPCI-3510(BL)L Daughter Board Func. Block Diagram 15

Figure 2-5: cPCI-3510(BL)M Daughter Board Func. Block Diagram 16

Figure 2-6: cPCI-R3P00 RTM Functional Block Diagram....17

Figure 2-7: cPCI-R3P00T RTM Functional Block Diagram....18

Figure 4-1: cPCI-3510(BL) Series Board Layout (component side). 29

Figure 4-2: cPCI-3510(BL) Series Board Layout (solder side)...... 30

Figure 4-3: cPCI-3510(BL) Blade Assembly Layout .... 31

Figure 4-4: cPCI-3510(BL)D Blade Assembly Layout.... 32

Figure 4-5: cPCI-3510(BL)G Blade Assembly Layout.... 33

Figure 4-6: cPCI-3510(BL)L Blade Assembly Layout .... 34

Figure 4-7: cPCI-3510(BL)M Blade Assembly Layout .... 35

Figure 4-8: cPCI-3510(BL)/D/G Faceplate Layout.... 37

Figure 4-9: cPCI-3510L/M/S Faceplate Layout.... 38

Figure 4-10: cPCI-R3P00(T) RTM Board Layout.... 40

Figure 4-11: cPCI-R3P00(T) RTM Faceplate....41

Figure 7-1: Example for configuring the WDT over serial console... 87

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# List of Tables

Table 2-1: cPCI-3510(BL) Processor Blade Specifications ..... 7

Table 2-2: cPCI-R3P00(T) RTM Specifications .... 11

Table 2-3: cPCI-3510(BL) I/O Connectivity....19

Table 4-1: cPCI-3510(BL) Faceplate System LED Descriptions .... 39

Table 4-2: USB 2.0 Pin Definition 42

Table 4-3: VGA Pin Definition....43

Table 4-4: DisplayPort Pin Definition 43

Table 4-5: DVI-I Connector Pin Definition....44

Table 4-6: RJ-45 GbE Pin Definitions 45

Table 4-7: LAN LED Status Definitions....45

Table 4-8: PS/2 Keyboard/Mouse Pin Definition.... 46

Table 4-9: cPCI-3510(BL)D/P COM1 (DB-9) Pin Definition...... 46

Table 4-10: cPCI-3510(BL)D/P COM1 Mode Selection Settings..... 47

Table 4-11: cPCI-3510(BL)G COM1 (RJ-45) Pin Definition.... 48

Table 4-12: cPCI-3510(BL)G COM1 (DB-9 adapter) Pin Definition.. 48

Table 4-13: RS-422/485 Adapter Dongle Pin Definition .... 49

Table 4-14: cPCI-3510(BL)G COM1 with Dongle Pin Definition...... 49

Table 4-15: cPCI-3510(BL)G COM2 Pin Header Definition....50

Table 4-16: cPCI-R3P00(T) RTM COM4 Pin Definition....50

Table 4-17: cPCI-R3P00(T) RTM COM5 Pin Definition....51

Table 4-18: cPCI-R3P00(T) RTM COM5 with Dongle Pin Def'n..... 51

Table 4-19: cPCI-3510M 100-pin I/O Connector Pin Definition ..... 52

Table 4-20: Serial ATA Connector on RTM 54

Table 4-21: SATA on cPCI-3510(BL) Daughter Board Pin Def'n.....54

Table 4-22: CFast Socket Pin Definition....55

Table 4-23: Layer-2 Daughter Board Connector Pin Definition ..... 56

Table 4-24: Storage Daughter Board Connector Pin Definition...... 57

Table 4-25: cPCI-3510(BL)G Daughter Board Connector Pin Def'n. 58

Table 4-26: PMC/XMC Daughter Board Connector Pin Definition.... 59

Table 4-27: PMC Connector Pin Definitions 60

Table 4-28: XMC Connector Pin Definition....62

Table 4-29: CompactPCI J1 Connector Pin Definition....63

Table 4-30: CompactPCI J2 Connector Pin Definition....64

Table 4-31: cPCI-R3P00 rJ2 Connector Pin Definition....65

Table 4-32: cPCI-R3P00T rJ2 Connector Pin Definition....66

Table 4-33: Load BIOS Default Jumper Settings....67

Table 4-34: XMC VPWR Select Jumper Settings....67

Table 4-35: PMC V(I/O) Select Jumper Settings 67

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# 1 Introduction

# 1.1 Overview

The ADLINK cPCI-3510(BL) Series is a 3U CompactPCI® PlusIO compatible processor blade with soldered DDR3L-1333/1600 ECC memory up to 16GB. The ADLINK cPCI-3510(BL) features an Intel® Core™ i7 processor with Mobile Intel® QM87 Chipset. The cPCI-3510 Series features the 4th Gen Intel® Core™ i7 (formerly "Haswell"), and the cPCI-3510BL Series features the 5th Gen Intel® Core™ i7 (formerly "Broadwell").

The cPCI-3510(BL) Series is a 3U CompactPCI blade available in single-slot (4HP), dual-slot (8HP) or triple-slot (12HP) width form factors with various daughter boards to provide a broad range of I/O requirements. Faceplate I/O in the single-slot (4HP) version includes 1x DVI-I, 2x GbE and 1x USB 3.0 port (these I/O are common to all versions). Faceplate I/O in the dual-slot (8HP) version includes additional 2x USB 2.0, 1x COM, 1x KB/MS and Line-in/Line-out on the cPCI-3510(BL)D or additional 2x DisplayPorts, 1x COM in RJ-45 connector, 1x KB/MS and 1x additional USB2.0 port on the cPCI-3510(BL)G. Two more dual-slot options are the cPCI-3510L with additional 2x GbE, 1x COM and 2x USB and the cPCI-3510M with one 100-pin high density connector supporting additional 2x DVI-I/DP, 2x USB 2.0, 2x COM, 2x KB/MS and Line-in/Line-out ports.

Graphics support is integrated on the CPU and allows 3 independent displays on the faceplate by selecting the cPCI-3510(BL)G with additional 2x DisplayPorts. Storage includes a CFast slot, mSATA socket or a 32GB onboard SSD and 2.5" SATA drive on the layer 2 daughter board [cPCI-3510(BL)D/L/M/P]. One optional PCI 32-bit/66 MHz PMC site or PCIe x1 XMC site is available on the 8HP or 12HP versions [cPCI-3510(BL)S or cPCI-3510(BL)P].

Rear I/O signals to J2 include 4x PCIe x1, 3x SATA 3 Gb/s, and 3x USB 2.0. GPIO and SMBus signals are also routed to the J2 connector. The optional Rear Transition Module (RTM) provides 3x SATA, 2x GbE, 2x USB, 1x COM (Tx/Rx) and 1x VGA port.

The cPCI-3510(BL) is a high performance solution for factory automation and other industrial applications that require superior data transfer capability and advanced computing power. The

ADLINK cPCI-3510(BL) provides high manageability, supports Satellite mode operation as a standalone blade in peripheral slots, and IPMI for system health monitoring. A GbE port on the faceplate supports Intel® AMT 9.0 for remote monitoring.

# 1.2 Features

▶ 3U CompactPCI blade in 4HP, 8HP or 12HP width form factor
▶ 4th/5th Generation Intel® Core™ Processor
▶ Graphics and memory controllers integrated in processor
▶ Compatible with PICMG 2.30 PlusIO (3x SATA, 4x PCIe x1, 3x USB, 2x GbE to J2)
▶ Dual channel DDR3L-1333/1600 soldered SDRAM with ECC, up to 16GB
▶ 32-bit, 33/66MHz CompactPCI Interface based on PCI specifications, universal V(I/O)
▶ Supports Satellite mode operation as a standalone blade in peripheral slots
▶ Optional 32-bit/66MHz PMC or PCIe x1 XMC site
▶ Supports IPMI for system health monitoring
▶ DVI-I port on front with VGA switchable to rear I/O by BIOS setting
▶ Additional two DisplayPorts on layer 2 daughter board [cPCI-3510(BL)G]
▶ Supports 3 independent displays with DirectX 11.1, OpenGL 3.2
▶ Two PCIe Gigabit Ethernet egress ports, one supporting Intel iAMT 9.0
▶ Two additional PCIe Gigabit Ethernet Controllers routed to RTM (cPCI-R3P00)
▶ Additional two Gigabit Ethernet ports on 80mm RTM (cPCI-R3P00T)
▶ Line-in and Line-out ports on faceplate [cPCI-3510(BL)D]
▶ CFast or mSATA socket for SATA interface storage
▶ Optional onboard SSD for SATA interface storage (shares space with CFast socket)
▶ 2.5" SATA connector on 8HP/12HP versions at 6 Gb/s [cPCI-3510(BL)D/G/M/L/P]

# 1.3 Model Number Decoder

# Blades

![cPCI-EX 3510 D / 4700E / M4G / S32\n(A) (B)(C) (D) (E) (F)](.cpci-3510-50-15095-1040-24/3480093e130952cceea04b8a709dadb3d12d50326d2879e794b7a96c903d1e4a.jpg)

# (A) Operating Temperature Code

▷ Blank = -20°C to +70°C
▷ EX= -40°C to +85°C (for CPUs with TDP below 37W only)

# (B) J2 Connector Type Code

▷ 0 = HM connector
▷ 1 = UHM connector (PICMG 2.30 PlusIO compliant)

# (C) Configuration Code

$\triangleright$ Blank = Single slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE
D = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x USB 2.0, COM (RS-232/422/485), PS/2 KB/MS, Line-in, Line-out ports and 2.5" SATA drive space on layer 2
▷ G = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x DisplayPort, RJ-45 COM (RS-232/422/485), PS/2 KB/MS, USB 2.0 ports, onboard SATA connector and 2.5" SATA drive space on layer 2
▷ L = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x GbE, 1x DB-9 COM (RS-232/422/485), 1x USB 2.0 on faceplate, 1x onboard USB 2.0 port and 2.5" SATA drive space on layer 2
M = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 1x 100-pin high density connector supports, 2x DVI/DP, 2x USB 2.0, 2x COM (RS-232/422/485), 1x KB/MS, audio and 2.5" SATA drive space on layer 2
▷ S = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; PMC/XMC site on layer 2
▷ P = Triple slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x USB 2.0, COM (RS-232/422/485), PS/2 KB/MS, Line-in, Line-out ports and 2.5" SATA drive space on layer 2; PMC/XMC site on layer 3

# (D) CPU Code

▷ 5700E = quad-core Intel® CoreTM i7-5700EQ processor
4700E = quad-core Intel® CoreTM i7-4700EQ processor
4402E = dual-core Intel® CoreTM i5-4402E processor

# (E) Memory Size Code

M4 = 2x 2GB DDR3L-1600 soldered SDRAM
M8 = 2x 4GB DDR3L-1600 soldered SDRAM
M16 = 2x 8GB DDR3L-1333 soldered SDRAM

# (F) Storage Board Code

▷ Blank = Default with CFast socket
▶ MS = Equipped with mSATA socket
▷ S32 = Onboard soldered 32GB SSD

# RTMs

![cPCI- R3P00 T\n(A)](.cpci-3510-50-15095-1040-24/bb51f399826ab87e515d425d15f56c42456dc8a95914e324418e6ea07c16487a.jpg)

# (A) Model Code

▷ Blank = dual slot width, 50mm depth 3U RTM with 2x COM, 2x USB, 3x SATA, VGA, 2x GbE (switched from front CPU blade)
▷ T = dual slot width, 80mm depth 3U RTM with 2x COM, 2x USB, 3x SATA, VGA, 2x GbE (independent from front CPU blade)

# 1.4 Package Contents

The cPCI-3510(BL) is packaged with the following components. If any of the following items are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of cPCI-3510(BL) Series non-standard configurations will vary depending on customer requests.

# Processor Blade

The cPCI-3510(BL) Series Processor Blade
▷ CPU and memory specifications will differ depending on options selected
▶ Thermal module is assembled on the board
▶ Y-cable for PS/2 combo port (cPCI-3510(BL)D/P only)
▶ 2.5" SATA drive installation kit (cPCI-3510(BL)D/(BL)G/L/M/P only)
▶ RJ-45 to DB-9 COM adapter cable (cPCI-3510(BL)G version only)
▶ DisplayPort to DVI adapter cable (cPCI-3510(BL)G version only)
▶ User's manual

![This image displays a white document icon with a folded top-left corner and faint horizontal lines running across it. A large, bold red checkmark is superimposed diagonally across the center of the document.](.cpci-3510-50-15095-1040-24/49de944306dfbd88dc93afbe262f40e22fad47fba3411253dd16020efccdbb96.jpg)
NOTE:

No I/O cables are included with the cPCI-3510M version.

![The image displays a digital icon of a white document or sheet of paper. The paper has a folded top-right corner (a 'dog-ear') and features several horizontal grey lines running across it. Superimposed over the document is a large, bold red checkmark (or tick mark) that is tilted diagonally from the bottom left to the top right.](.cpci-3510-50-15095-1040-24/487093b3686a8f96519285edcb98e45347dd75ae832625c037be2b36d18ab45e.jpg)
NOTE:

The contents of non-standard cPCI-3510(BL) configurations may vary depending on the customer's requirements.

# Rear Transition Module

▶ cPCI-R3P00 or cPCI-R3P00T RTM

# Blade Optional Accessories

▶ 2.5" SATA drive installation kit (P/N 58-00176-0000)
▶ Y-cable for PS/2 combo port (P/N 30-01016-2000)
▶ RJ-45 to DB-9 COM adapter cable (P/N 30-01020-0200)
▶ DisplayPort to DVI adapter cable (P/N 30-01120-0000)
▶ DisplayPort to VGA adapter cable (P/N 30-01119-0000)
▶ DisplayPort to HDMI adapter cable (P/N 30-01121-0000)
▶ USB 3.0 Type A male-to-female extension cable (P/N: 30-01175-0000)
▶ SCSI 100-pin IO cable: 2x DVI-D female, 2x DB9 male, 2x USB female, 2x PS/2 female, 2x audio jack (available by request)

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the word 'CAUTION:' is printed in bold, black capital letters.](.cpci-3510-50-15095-1040-24/d78435ed7b0706bf9b66a9203a03909b908ebeee594de4cd56baad6411a09db9.jpg)

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

2.1 cPCI-3510(BL) Processor Blade Specifications

<table><tr><td>CompactPCI®Standards</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev. 2.0PICMG® 2.9 System Management Rev. 1.0PICMG® 2.30 CompactPCI® PlusIO</td></tr><tr><td>Mechanical</td><td>Standard 3U CompactPCI®Board size: 100mm x 160mmSingle slot (4HP, 20.32mm); Dual slot (8HP, 40.64mm); Triple-slot (12HP, 60.96 mm)CompactPCI® with HM type J1 connector, UHM type J2 connector</td></tr><tr><td>Processor</td><td>4-core Intel® CoreTM i7-5700EQ Processor 2.6GHz, 3.4GHz Turbo, 6M cache, 47/37W by cTDP (cPCI-3510BL only)4-core Intel® CoreTM i7-4700EQ Processor 2.4GHz, 3.4GHz Turbo, 6M cache, 47/37W by cTDP2-core Intel® CoreTM i5-4402E Processor 1.6GHz, 2.7GHz Turbo, 3M cache, 25WPassive heatsink</td></tr><tr><td>Chipset</td><td>Mobile Intel® QM87 Chipset</td></tr><tr><td>Memory</td><td>DDR3L-1333 SDRAM ECC soldered, up to 16GB (cPCI-3510BL)DDR3L-1600 SDRAM ECC soldered, up to 8GB (cPCI-3510)</td></tr><tr><td>CompactPCIBus</td><td>PCI 32bit/ 33MHz; 3.3V, 5V universal V(IO)Supports operation in system slot as master or in peripheral slot as standalone blade without connectivity to CompactPCI bus (Satellite mode)</td></tr><tr><td>GigabitEthernet</td><td>One PCIe x1 Intel® I217 GbE PHY and three PCIe x1 Intel® I210 Gigabit Ethernet controllersTwo egress 10/100/1000BASE-T ports on faceplate, one supporting Intel® AMT 9.0 by I217 controllerTwo egress 10/100/1000BASE-T ports routed to rear transition module</td></tr><tr><td>Graphics</td><td>Integrated on Intel® CoreTM processorDVI-I port on faceplate, VGA switchable to J2 (RTM) by BIOS settingAnalog monitor support up to QXGA 2048x1536 @75Hz, 32-bitTwo DisplayPorts on faceplate with resolution up to 2560x1440 @60Hz (cPCI-3510(BL)G only)Up to three independent display</td></tr></table>

Table 2-1: cPCI-3510(BL) Processor Blade Specifications

<table><tr><td>USB</td><td>• Up to three USB faceplate ports</td></tr><tr><td>Serial Ports</td><td>• Up to four serial ports• One RS-232/422/485 serial port on 8HP faceplate (cPCI-3510(BL)D/(BL)G/L)• Additional RS-232 10-pin header on layer-2 board (cPCI-3510(BL)G only)• Up to two RS-232/422/485 COM port (cPCI-3510M only)</td></tr><tr><td>PMC/XMC</td><td>• One 32-bit/66MHz PMC site or PCIe x1 XMC site if PMC/XMC daughter board is installed</td></tr><tr><td>Audio</td><td>• Line-in/Line-out on faceplate by Realtek ALC262 High Definition Audio codec (cPCI-3510(BL)D only)• Line-in/Line-out on faceplate by 100-pin connector (cPCI-3510M only)</td></tr><tr><td>TPM</td><td>Atmel AT97SC3204 TPM (upon request) supporting:• Over/Under voltage detection• Low/High frequency sensor/filter• Reset filter• Memory encryption/decryption</td></tr><tr><td>Storage Interfaces $^{1}$ </td><td>• CFast or mSATA socket on daughter board• Optional onboard SSD on daughter board• One SATA 6Gb/s direct connector for 2.5&quot; SATA drive (8HP/12HP version only)</td></tr><tr><td>BIOS</td><td>• AMI® EFI BIOS, 64Mbit SPI flash memory</td></tr><tr><td>OSCompatibility</td><td>• Microsoft Windows 7 32/64-bit• Microsoft Windows 8 32/64-bit• Red Hat Enterprise Linux 6.4, 64-bit• Fedora 14, 32-bit• VxWorks 6.9• Real Time RTX (MSI)• Other OS support upon request</td></tr><tr><td>Environmental</td><td>• Operating Temperature (with forced air flow) $^{2}$ :Standard: -20°C to 70°CExtreme temperature: -40°C to +85°C (for Intel® CoreTM i5-4402E, i7-4700EQ and i7-5700EQ 47W adjusted to 37W by Intel cTDP and forced air flow)• Storage Temperature: -50°C to 100°C• Humidity: 95% @60°C non-condensing• Shock: 20G peak-to-peak, 11ms duration, non-operating• Vibration $^{3}$ : 2Grms, 5-500Hz, each axis, operating (w/o hard drive)</td></tr><tr><td>EMI</td><td>• CE EN55022• FCC Class A</td></tr></table>

Table 2-1: cPCI-3510(BL) Processor Blade Specifications

<table><tr><td>Faceplate I/O</td><td>4HP cPCI-3510(BL)1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port8HP cPCI-3510(BL)D1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x USB 2.0 portsDB-9 RS-232/422/485/485+ portPS/2 Keyboard/Mouse combo portLine-in and Line-out port8HP cPCI-3510(BL)G1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x DisplayPort1x USB 2.0 portsRJ-45 RS-232/422/485 portPS/2 Keyboard/ Mouse combo port8HP cPCI-3510L1x USB 3.0 ports1x DVI-I port4x 10/100/1000BASE-T Ethernet ports1x USB 2.0 portsDB-9 RS-232/422/485 port8HP cPCI-3510M1x USB 3.0 ports1x DVI-I port2x 10/100/1000BASE-T Ethernet ports1x 100-pin connector supports 2x DVI/DP, Line-in/Line-out, 2x USB 2.0, 2x RS-232/422/485 COM, 1x KB/MS8HP cPCI-3510S1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I portPMC/XMC site</td></tr></table>

Table 2-1: cPCI-3510(BL) Processor Blade Specifications

<table><tr><td>Faceplate I/O</td><td>12HP cPCI-3510P1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x USB 2.0 portsDB-9 RS-232/422/485/485+ portPS/2 Keyboard/Mouse combo portLine-in and Line-out portPMC/XMC site</td></tr></table>

Table 2-1: cPCI-3510(BL) Processor Blade Specifications

1. The storage device limits the operational vibration tolerance. When the application requires higher specification for anti-vibration, it is recommended to use a flash storage device.
2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Sufficient forced air-flow is required. Temperature limits of optional mass storage devices may also affect the thermal specification.

# 2.2 cPCI-R3P00(T) RTM Specifications

<table><tr><td>Mechanical</td><td>Board SizecPCI-R3P00: 100mm x 50mmcPCI-R3P00T: 100mm x 80mmDual-slot (8HP, 40.64mm)(optional single slot upon request)</td></tr><tr><td>Gigabit Ethernet</td><td>cPCI-R3P00: Two GbE ports switched from cPCI-3510(BL)2x independent controller i210cPCI-R3P00T: Two GbE ports from independent Intel 82580DB GbE controller</td></tr><tr><td>Serial Ports</td><td>Two serial ports on I/O panel from pin headerOne port converted from USB supporting RS-232/422/485One port provides Tx, Rx signals only</td></tr><tr><td>Storage Interfaces</td><td>Three 7-pin Serial ATA ports</td></tr><tr><td>Faceplate I/O</td><td>2x USB 2.0 ports2x 10/100/1000BASE-T Ethernet portsAnalog DB-15 VGA port2x COM ports</td></tr></table>

Table 2-2: cPCI-R3P00(T) RTM Specifications

![The image displays a graphic icon of a document or list. It features a white rectangular shape with the top right corner folded down, creating a 'dog-ear' effect. Faint horizontal gray lines run across the lower portion of the paper, suggesting lines of text. Superimposed over the document is a large, bold red checkmark (or tick mark) that extends diagonally from the lower left to the upper right. There is no text in the image.](.cpci-3510-50-15095-1040-24/750a2a0f1bf3f4f24b29f471bb9491336de5b10f2e62886657fae6a3be45cdea.jpg)
NOTE:

Specifications are subject to change without prior notice.

# 2.3 Block Diagrams

cPCI-3510(BL) Blade
![This flowchart depicts a computer architecture centered around an **Intel® Core™ Processor (Haswell / Broadwell)** and an **Intel® QM87 PCH (Lynx Point)**.\n\n**Top-Level Components & Faceplate:**\n*   A yellow bar labeled **Faceplate** contains dashed boxes for **DVH**, **GbE1**, **GbE2**, and **USB**.\n*   Two blocks labeled **ECC, up to 8GB** connect to the Intel Core Processor via **DDR3L-1333/1600**.\n\n**Processor Connections:**\n*   The **Intel® Core™ Processor** connects to the **Intel® QM87 PCH (Lynx Point)** via **DMI** and **FDI**.\n*   It connects to **B2B Conn. #2** via **DP1/DVI**, **DP2/DVI**, and **PCIe x4**.\n*   It outputs **2x PCIe x1** to a summation circle, which routes signals via **DVI** to the **DVH** faceplate connector and via **VGA** to the right.\n\n**PCH (Platform Controller Hub) Connections:**\n*   The **Intel® QM87 PCH** connects to **Intel® I217** and **Intel® I210** (black boxes) via **PCIe x1**. These NICs connect up to **GbE1** and **GbE2** on the Faceplate.\n*   It connects to **USB** on the Faceplate via **USB 3.0**.\n*   It connects to a stack of **SSD**, **CFast**, and **mSATA** via **SATA**.\n*   It connects to **BIOS** (red box) via **SPI** and **Battery** (black box) via **RTC**.\n*   It connects to **SIO** (blue box) via **LPC**.\n*   It connects to **B2B Conn. #1** (orange box) via **COM1, KB/MS** and **2x PCIe x1**.\n*   It connects to a black box labeled **2x Intel® I210** via **2x PCIe x1**.\n\n**Bottom & Intermediate Components:**\n*   **B2B Conn. #2** connects to **SIO** via **COM2** and to a black box labeled **PCIe to PCI Bridge** (arrow points down).\n*   **B2B Conn. #1** connects to **ATMEL® GA128** (blue box) via **COM4**.\n*   **SIO** connects to **ATMEL® GA128** via **COM3**.\n*   **PCIe to PCI Bridge** connects to **J1** (yellow bar) via **PCI 32bit /66MHz**.\n*   **ATMEL® GA128** connects to **J1** via **IPMB 0/1** and to **J2** (yellow bar) via **VGA**.\n*   The **2x Intel® I210** block connects to **J2** via **2x GbE**, **3x USB**, **3x SATA**, and **4x PCIe x1**.](.cpci-3510-50-15095-1040-24/0519c38bf3120b24dff10271e3db0f4b16bd42820feb2b3b89854739f889a81b.jpg)

Figure 2-1: cPCI-3510(BL) Blade Functional Block Diagram

cPCI-3510(BL)D Daughter Board
![This diagram depicts signal connections flowing from a block on the right to a block on the left.\n\n**Labeled Blocks:**\n*   **L2 Front Panel** (Vertical orange block on the left)\n*   **B2B Conn. 1** (Vertical orange block on the right)\n*   **Codec** (Blue rectangular block in the middle)\n*   **2.5' HDD/SDD** (Orange rectangular block in the middle)\n\n**Connections (Arrows pointing left from B2B Conn. 1 to L2 Front Panel):**\n1.  **USB x2**: A direct connection.\n2.  **Line-in, Line-out**: A connection that passes through the **Codec** block.\n3.  **SATA0**: A connection that passes through the **2.5' HDD/SDD** block.\n4.  **PS/2, KB/MS**: A direct connection.\n5.  **COM**: A direct connection.](.cpci-3510-50-15095-1040-24/9c894b7a9b9ce94481e229cb4278a59dcf074c1b76511d9357c8787483928dc2.jpg)

Figure 2-2: cPCI-3510(BL)D Daughter Board Functional Block Diagram

cPCI-3510(BL)G Daughter Board
![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n*   **Left Vertical Bar:** Contains the text 'L2' at the top and 'Front Panel' written vertically below it.\n*   **Right Vertical Bar:** Contains the text 'B2B Conn. 1/2' written vertically.\n*   **Small Center Box (Upper):** Labeled '2.5' HDD/SSD'.\n*   **Small Center Box (Lower):** Labeled '10-pin'.\n\n**Connections:**\nThere are seven black arrows pointing from the right block ('B2B Conn. 1/2') to the left block ('L2 Front Panel'). The connections are labeled as follows (from top to bottom):\n1.  **USB**\n2.  **DVI/DP**\n3.  **SATA0** (The line passes through the '2.5' HDD/SSD' box).\n4.  **DVI/DP**\n5.  **COM1**\n6.  **COM2** (The line passes near the '10-pin' box).\n7.  **KB/MS**](.cpci-3510-50-15095-1040-24/4c3c70f9e233882238c6dbcdec60a597184cada49b51624dc194239f2419d78a.jpg)

Figure 2-3: cPCI-3510(BL)G Daughter Board Functional Block Diagram

cPCI-3510(BL)L Daughter Board
![**Labeled Blocks:**\n*   'L2 FRONT PANEL' (Vertical, left)\n*   'B2B Conn.' (Vertical, right)\n*   'Horizontal Type A' (Center, dashed border)\n*   '2.5' HDD' (Center)\n*   '82574L' (Center-bottom, blue box, appears twice)\n\n**Connections:**\n*   From 'B2B Conn.' to 'L2 FRONT PANEL' labeled 'USB x1'\n*   From 'B2B Conn.' to 'Horizontal Type A' labeled 'USB x1'\n*   From 'B2B Conn.' to 'L2 FRONT PANEL' labeled 'RS232/422/485'\n*   From '2.5' HDD' to 'B2B Conn.' labeled 'SATA0'\n*   From the upper '82574L' block to 'L2 FRONT PANEL' labeled 'GbE 3'\n*   From the upper '82574L' block to 'B2B Conn.' (No label)\n*   From the lower '82574L' block to 'L2 FRONT PANEL' labeled 'GbE 4'\n*   From the lower '82574L' block to 'B2B Conn.' (No label)](.cpci-3510-50-15095-1040-24/09e4ac8e136bae4a75d2af3b20fa4e54b96d1834dce348aa579f0d1c295a2ea1.jpg)

Figure 2-4: cPCI-3510(BL)L Daughter Board Functional Block Diagram

cPCI-3510(BL)M Daughter Board
![The diagram displays three labeled blocks and their connections:\n\n**Blocks:**\n*   **Left Vertical Block:** '100-pin high density connector' and 'FRONT PANEL' (text written vertically).\n*   **Right Vertical Block:** 'B2B Conn.'\n*   **Center Block:** '2.5' HDD/Slim SSD'\n\n**Connections:**\n*   An arrow labeled **Line-in, Line-out** connects 'B2B Conn.' to the '100-pin high density connector'.\n*   An arrow labeled **2x DVI/DP** connects 'B2B Conn.' to the '100-pin high density connector'.\n*   A line labeled **SATA0** connects the '2.5' HDD/Slim SSD' block to the 'B2B Conn.' block.\n*   An arrow labeled **2x USB 2.0** connects 'B2B Conn.' to the '100-pin high density connector'.\n*   An arrow labeled **2x COM (RS232/422/485)** connects 'B2B Conn.' to the '100-pin high density connector'.\n*   An arrow labeled **KB/MS** connects 'B2B Conn.' to the '100-pin high density connector'.](.cpci-3510-50-15095-1040-24/339ed6333f0050a13cbc525fb6b737305f645c4e9d00ace4179c16d69b8113dc.jpg)

Figure 2-5: cPCI-3510(BL)M Daughter Board Functional Block Diagram

cPCI-R3P00 RTM
![The flowchart depicts connections originating from a vertical block labeled **J2** on the left and terminating at a vertical block labeled **Rear Panel** on the right.\n\n**Direct Connections:**\nFour lines connect **J2** directly to the **Rear Panel**:\n*   **COM (Tx, Rx)**\n*   **2x USB**\n*   **GbE 1/2**\n*   **VGA**\n\n**Intermediate Connections:**\n*   **SATA Path:** A line labeled **SATA3/4/5** connects **J2** to three stacked orange blocks labeled **7 pin**.\n*   **Serial Path:** A line labeled **USB3** connects **J2** to a blue block labeled **FT232R**. From the **FT232R** block, a line labeled **RS232/422/485** connects to the **Rear Panel**.](.cpci-3510-50-15095-1040-24/05fdb1e5237f78902c014ce3a2e0ace4ca6f8d6781b54979b80c86add1d5b6d7.jpg)

Figure 2-6: cPCI-R3P00 RTM Functional Block Diagram

cPCI-R3P00T RTM
![Based on the provided image, here is the accurate description of the flowchart:\n\n**Blocks:**\n*   **J2**: A tall yellow vertical bar on the far left.\n*   **Rear Panel**: A tall yellow vertical bar on the far right.\n*   **82580DB**: A blue rectangular block in the upper middle section.\n*   **FT232R**: A blue rectangular block in the lower middle section.\n*   **7 pin**: Three orange square blocks stacked vertically in the lower middle section.\n\n**Connections:**\n*   **J2** to **Rear Panel**: A line labeled **COM (Tx, Rx)**.\n*   **J2** to **Rear Panel**: A line labeled **2x USB**.\n*   **J2** to **82580DB** (labeled **PCIe x4**), then from **82580DB** to **Rear Panel** (labeled **GbE 3/4**).\n*   **J2** to **Rear Panel**: A line labeled **VGA**.\n*   **J2** to the top **7 pin** block (labeled **SATA3/4/5**).\n*   **J2** to **FT232R** (labeled **USB3**), then from **FT232R** to **Rear Panel** (labeled **RS232/422/485**).](.cpci-3510-50-15095-1040-24/6568fa48a63fd046ef5ebd2a7ce84f07ac81f72d273fa6b0f9c2ffb5bbd8c122.jpg)

Figure 2-7: cPCI-R3P00T RTM Functional Block Diagram

# 2.4 I/O Connectivity Table

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-3510(BL)(4HP)</td><td colspan="2">cPCI-3510(BL)D(8HP)</td><td colspan="2">cPCI-3510(BL)G(8HP)</td><td colspan="2">cPCI-3510(BL)L(8HP)</td></tr><tr><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>4 (RJ-45)</td><td></td></tr><tr><td>USB</td><td>1 (3.0)</td><td></td><td>1 (3.0)2 (2.0)</td><td></td><td>1 (3.0)1 (2.0)</td><td></td><td>1 (3.0)1 (2.0)</td><td></td></tr><tr><td>COM</td><td></td><td></td><td>1 (DB9)</td><td></td><td>1 (RJ-45)</td><td>1 (10-pin)</td><td>1(DB9)</td><td></td></tr><tr><td>Display</td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)2 (DP)</td><td></td><td>1 (DVI-I)</td><td></td></tr><tr><td>KB/MS</td><td>Y</td><td></td><td>Y</td><td></td><td>1</td><td></td><td></td><td></td></tr><tr><td>Storage</td><td></td><td>1 (CFast)</td><td></td><td>1 (SATA)1 (CFast)</td><td></td><td>1 (SATA)1 (CFast)</td><td></td><td>1 (SATA)1 (CFast)</td></tr><tr><td>Onboard SSD</td><td></td><td> $optional^{(1)}$ </td><td></td><td> $optional^{(1)}$ </td><td></td><td> $optional^{(1)}$ </td><td></td><td> $optional^{(1)}$ </td></tr><tr><td>Audio</td><td></td><td></td><td></td><td>Line-in Line-out</td><td></td><td></td><td></td><td></td></tr><tr><td>PMC/XM</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

Table 2-3: cPCI-3510(BL) I/O Connectivity

1. Available by replacing CFast or mSATA socket adapter board with onboard SSD adapter board.

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-3510(BL)M (8HP)</td><td colspan="2">cPCI-3510(BL)S (8HP)</td><td colspan="2">cPCI-3510(BL)P (12HP)</td><td colspan="2">R3P00(T) (RTM)</td></tr><tr><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td> $2 (RJ-45)^{(2)}$ </td><td></td></tr><tr><td>USB</td><td>1 (3.0)2 (2.0)</td><td></td><td>1 (3.0)</td><td></td><td>1 (3.0)2 (2.0)</td><td></td><td>2 (2.0)</td><td></td></tr><tr><td>COM</td><td>2 (DB9)</td><td></td><td></td><td></td><td>1 (DB9)</td><td></td><td>2 (DB9)</td><td></td></tr><tr><td>Display</td><td>1 (DVI-I)2 (DVI-D)</td><td></td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)</td><td></td><td> $1 (VGA)^{(3)}$ </td><td></td></tr><tr><td>KB/MS</td><td></td><td></td><td></td><td></td><td>1</td><td></td><td></td><td></td></tr><tr><td>Storage</td><td></td><td>1 (SATA)1 (CFast)</td><td></td><td></td><td></td><td>1 (SATA)1 (CFast)</td><td></td><td>3 (SATA)</td></tr><tr><td>Onboard SSD</td><td></td><td> $optional^{(1)}$ </td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Audio</td><td>Line-in Line-out</td><td></td><td></td><td></td><td>Line-in Line-out</td><td></td><td></td><td></td></tr><tr><td>PMC/XMC</td><td></td><td></td><td></td><td>1</td><td></td><td>1</td><td></td><td></td></tr></table>

Table 2-3: cPCI-3510(BL) I/O Connectivity (cont'd)

1. Available by replacing CFast or mSATA socket adapter board with onboard SSD adapter board.
2. Routed from CPU blade faceplate for cPCI-R3P00; independent of CPU blade for cPCI-R3P00T (GbE controller onboard).
3. VGA switched from faceplate.

# 2.5 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

# Power Consumption

This section provides information on the power consumption of cPCI-3510(BL) Series when using the Intel® Core™ i7 processors with 4GB DDR3L-1600 ECC soldered memory and onboard 64GB SATA flash disk. The cPCI-3510(BL) is powered by 5V and 3.3V. Power consumption at $100\%$ CPU usage was measured using the Intel Thermal Analysis Tool (TAT).

<table><tr><td colspan="4">Intel® CoreTMi7-4700EQ</td></tr><tr><td>OS/Mode</td><td>Current 5V</td><td>Current 3.3V</td><td>Total Power</td></tr><tr><td>DOS/Idle mode</td><td>3.79 A</td><td>0.73 A</td><td>21.4 W</td></tr><tr><td>Windows XP/Idle mode</td><td>3.56 A</td><td>0.71 A</td><td>20.1 W</td></tr><tr><td>Windows® XP, CPU 100% Usage</td><td>6.97 A</td><td>0.71 A</td><td>37.2 W</td></tr></table>

# 3 Functional Description

The following sections describe the cPCI-3510(BL) Series features and functions.

# 3.1 Processors

The Mobile 4th/5th Generation Intel® Core™ Processor Family are 64-bit, multi-core mobile processor built on 22 nanometer process technology. The processor is designed for a two-chip platform consisting of a processor and chipset. The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics and Integrated Memory Controller.

The cPCI-3510(BL) Series supports Intel® Core™ i7/i5 processors. The table below lists the general specifications and power ratings of the CPUs supported by the cPCI-3510(BL) Series.

<table><tr><td>Features</td><td>CoreTM i7-5700EQ</td><td>CoreTM i7-4700EQ</td><td>CoreTM i5-I5-4400E</td><td>CoreTM i5-4402E</td></tr><tr><td>Clock</td><td>2.6GHz</td><td>2.4GHz</td><td>2.7GHz</td><td>1.6 GHz</td></tr><tr><td>Max. Single Core Turbo Freq.</td><td>3.4GHz</td><td>3.4GHz</td><td>-</td><td>-</td></tr><tr><td>Last Level Cache</td><td>6MB</td><td>6MB</td><td>3MB</td><td>3MB</td></tr><tr><td>No. of Core(s)</td><td>4/8</td><td>4/8</td><td>2/4</td><td>2/4</td></tr><tr><td>Max. Power (TDP $^{1}$ )</td><td>47W</td><td>47W</td><td>37W</td><td>25W</td></tr><tr><td>DMI</td><td>5 GT/s</td><td>5 GT/s</td><td>5 GT/s</td><td>5 GT/s</td></tr><tr><td> $T_{junction, MAX}^{2}$ </td><td>105°C</td><td>100°C</td><td>100°C</td><td>100°C</td></tr></table>

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.

2. The maximum supported operating temperature.

Supported Technologies

<table><tr><td>Features</td><td>CoreTM i7-5700EQ</td><td>CoreTM i7-4700EQ</td><td>CoreTM i5-15-4400E</td><td>CoreTM i5-4402E</td></tr><tr><td>Intel® Virtualization Technology for Directed I/O (Intel® VT-d)</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Virtualization Technology (Intel® VT-x)</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® VT-x with Extended Page Tables (EPT)</td><td>Yes</td><td>Yes</td><td>—</td><td>—</td></tr><tr><td>Intel® Hyper-Threading Technology</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® 64 Architecture</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Execute Disable Bit</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Turbo Boost Technology</td><td>2.0</td><td>2.0</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® vPro Technology</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Enhanced Intel SpeedStep® Technology</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Thermal Monitoring Technologies</td><td>Yes</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Identity Protection Technology</td><td>Yes</td><td>Yes</td><td>—</td><td>—</td></tr></table>

# Interfaces

▶ Two channels of DDR3L-1333/1600 memory
▶ DDR3 memory data transfer rates of 1333 MT/s and 1600 MT/s
▶ 64-bit wide channels
▶ DDR3L I/O voltage of 1.35V
▶ 2Gb and 4Gb DDR3 DRAM technologies are supported for x8 and x16 devices (using 4Gb device technologies, the largest memory capacity possible is 8 GB, assuming dual-channel mode with x8, dual-ranked ECC SDRAM)
▶ PCI Express ports are fully-compliant with the PCI Express Base Specification, Revision 2.0.
▶ 5 GT/s point-to-point DMI interface to Chipset is supported

# 3.2 Chipset

The Mobile Intel® QM87 Chipset provides extensive I/O support. Functions and capabilities include:

The QM87 Chipset provides extensive I/O support, functions and capabilities including:
▶ PCI Express Base Specification, Revision 2.0 support for up to eight ports with transfers up to 5 GT/s
▶ ACPI Power Management Logic Support, Revision 4.0a
▶ Enhanced DMA controller, interrupt controller, and timer functions
▶ Integrated Serial ATA host controllers with independent DMA operation on up to six ports
▶ USB host interface with two EHCI high-speed USB 2.0 Host controllers and two rate matching hubs provide support for up to fourteen USB 2.0 ports
▶ Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
▶ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
▶ Supports Intel® High Definition Audio
▶ Supports Intel® Rapid Storage Technology
▶ Supports Intel® Virtualization Technology for Directed I/O
▶ Integrated Clock Controller
▶ Analog and Digital Display ports
▶ Low Pin Count (LPC) interface
▶ Firmware Hub (FWH) interface support
▶ Serial Peripheral Interface (SPI) support

# 3.3 PMC/XMC

The cPCI-3510P/S models support one PMC or XMC site for faceplate I/O expansion. The PMC site provides a maximum 32-bit/66MHz PCI bus link using a Pericom PI7C9X130 PCI-Express-to-PCI bridge and PCI-Express x1 link. The PMC site supports +3.3V signaling only. The XMC site provides a PCI Express x1 lane.

# 3.4 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and/or render clock frequency when there is sufficient power headroom, and the product is within specified temperature and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations. This improves the system responsiveness for short, bursty usage conditions.

Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

# 3.5 Intel® Hyper-Threading Technology

Intel® Hyper-Threading Technology allows an execution core to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support. Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7, Vista, and XP, and disabling Hyper-Threading Technology using the BIOS for all previous versions of Windows operating systems.

# 3.6 Trusted Platform Module

The cPCI-3510(BL) is optionally equipped with an Atmel AT97SC3204 Trusted Platform Module (TPM). The TPM is a secure controller with added cryptographic functionality to provide users a secure environment in e-commerce transactions and Internet communications.

The key features Trusted Platform Module (TPM) offers are:

▶ Fully compliant to the Trusted Computing Group (TCG) Trusted Platform Module (TPM) version 1.2 specification
▶ Hardware hash accelerator for SHA-1 algorithm
▶ Advanced Crypto Engine (ACE) for asymmetric key operations(up to 2048-bit key length) to make hardware protection.
▶ Tick counter to extend the time required to decipher the key
▶ In addition to encryption key created by user. it also provide some security features to protect the integrated circuit itself:
▶ Over/Under-voltage detection to monitor the system stability. If the voltage fluctuates dramatically, this function can block the data transfer and lock the chip.
▶ Low/High frequency sensor to detect the IC clock frequency. If the frequency fluctuates dramatically, this function can block the data transfer and lock the chip.
▶ Reset filter to filter reset signal in order to break the time set by tick counter is received
▶ Memory encryption to protect memory
▶ Physical shield in the IC to protect the die from intruding or hacking by matching the data transferred on the 2 layer metal shield on the IC. If the data is not matched, the IC may be blocked.

# 3.7 Battery

The cPCI-3510(BL) is equipped with a 3.0V "coin cell" lithium battery for the Real Time Clock (RTC). The battery socket is equipped on the storage carrier daughter board. The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. A Rayovac BR2032 is equipped on board by default, and can be optionally equipped with a Gold Capacitor (Panasonic EECS5R5H105).

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# 4 Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the cPCI-3510(BL) Series.

# 4.1 cPCI-3510(BL) Series Board Layout

![LAN1\nCN3\nCPU1\nCN2\nUSB1\nDVI1\nCN1\nPCH\nU2201\nJ2\nJ1](.cpci-3510-50-15095-1040-24/9e600ebdc6345af5c7595422fd08780004066c674255e516036994455815f1d0.jpg)

<table><tr><td>CPU</td><td>Intel® CoreTM Processor</td><td>J1</td><td>CompactPCI connector J1</td></tr><tr><td>PCH</td><td>Intel® QM87 Chipset</td><td>J2</td><td>CompactPCI connector J2 (UHM/HM)</td></tr><tr><td>CN4/5</td><td>Stacked SO-CDIMM socket</td><td>LAN1</td><td>Dual Ethernet connectors</td></tr><tr><td>CN1</td><td>Layer-2 daughter board connector</td><td>DVI1</td><td>DVI connector</td></tr><tr><td>CN2</td><td>Storage daughter board connector</td><td>USB1</td><td>USB port</td></tr><tr><td>CN3</td><td>cPCI-3510(BL)G daughter board connector</td><td>U2201</td><td>Pericom PI7C9X130</td></tr></table>

Figure 4-1: cPCI-3510(BL) Series Board Layout (component side)

![SSSB-5099B\nSW1](.cpci-3510-50-15095-1040-24/f9ac743f9bdc42db96d3c21624768d485e9265103aef4e11b2c669833472e7ff.jpg)

<table><tr><td>SW1</td><td>Reset Button</td></tr></table>

Figure 4-2: cPCI-3510(BL) Series Board Layout (solder side)

# 4.2 cPCI-3510(BL) Blade Assembly Layout

This section describes the final assembly layout of the single slot cPCI-3510(BL) Blade.

![Heatsink\nBT1\nJP1\nJ2\nCFast\nCFast carrier board](.cpci-3510-50-15095-1040-24/bccf5b540953dae0f3d07ce84bb41af59dfa375b98f0a7d23648bd83489895e7.jpg)

Figure 4-3: cPCI-3510(BL) Blade Assembly Layout

<table><tr><td>BT1</td><td>Battery</td><td>CFast</td><td>CFast socket</td></tr><tr><td>JP1</td><td>Clear CMOS jumper</td><td>J2</td><td>CompactPCI connector J2 (UHM/HM)</td></tr></table>

# 4.3 cPCI-3510(BL)D Blade Assembly Layout

The dual-slot width cPCI-3510(BL)D Blade is comprised of the cPCI-3510 single-slot main board and the cPCI-3510(BL)D daughter board to expand I/O connectivity with PS/2, COM, 2x USB ports, Line-in, and Line-out ports.

![COM1\nSATA0\n2.5' SATA HDD\nUSB2\nUSB3\nPS/2\nCN6\nCN7\nCN8\ncPCI-3510(BL)D\ndaughter board](.cpci-3510-50-15095-1040-24/72953e80824c0aae366383aa5def9479ef2a867cdba07e3e2805646c6abb5692.jpg)

<table><tr><td>COM1</td><td>DB-9 COM port</td><td>CN7</td><td>Layer-2 daughter board connector</td></tr><tr><td>USB2/3</td><td>USB connectors</td><td>CN6</td><td>Line-in port</td></tr><tr><td>PS2</td><td>PS/2 KB/Ms combo port</td><td>CN8</td><td>Line-out port</td></tr><tr><td>SATA0</td><td>22-pin SATA connector</td><td></td><td></td></tr></table>

Figure 4-4: cPCI-3510(BL)D Blade Assembly Layout

# 4.4 cPCI-3510(BL)G Blade Assembly Layout

The dual-slot width cPCI-3510(BL)G Blade is comprised of the cPCI-3510 single-slot main board and the cPCI-3510(BL)G daughter board to expand I/O connectivity with PS/2, COM, USB ports, and 2x DisplayPorts.

![DP1\nDP2\nCOM1\nPS2\nUSB9\nCN2\nCOM2\nSATA0\n2.5' SATA HDD\ncPCI-3510(BL)G\ndaughter board](.cpci-3510-50-15095-1040-24/231d278cb846cd8fd9795370e181f7981f1c8181266ace850e531134c91d8df2.jpg)

<table><tr><td>COM1</td><td>RJ-45 COM port</td><td>CN2</td><td>Layer-2 daughter board connector</td></tr><tr><td>COM2</td><td>10-pin COM port</td><td>DP1/2</td><td>DisplayPort connectors</td></tr><tr><td>USB9</td><td>USB connector</td><td>PS2</td><td>PS/2 KB/MS combo port</td></tr><tr><td>SATA0</td><td>22-pin SATA connector</td><td></td><td></td></tr></table>

Figure 4-5: cPCI-3510(BL)G Blade Assembly Layout

# 4.5 cPCI-3510(BL)L Blade Assembly Layout

The dual-slot width cPCI-3510L Blade is comprised of the cPCI-3510 single-slot main board and the cPCI-3510L daughter board, expanding I/O connectivity with 2x LAN, COM, USB.

![LAN1\nSATA1 2.5' SATA HDD\nCOM1\nUSB1\ncPCI-3510L\ndaughter board](.cpci-3510-50-15095-1040-24/52db14388917ddb349fb45822e955a4a70ad50ad04a4b7f1d032b3b32ec29686.jpg)

<table><tr><td>LAN1</td><td>GbE RJ-45 ports</td><td>USB1</td><td>USB connector</td></tr><tr><td>COM1</td><td>DB-9 COM port</td><td>SATA1</td><td>22-pin SATA connector</td></tr></table>

Figure 4-6: cPCI-3510(BL)L Blade Assembly Layout

# 4.6 cPCI-3510(BL)M Blade Assembly Layout

The dual-slot width cPCI-3510M Blade is comprised of the cPCI-3510 single-slot main board and the cPCI-3510M daughter board, expanding I/O connectivity with a 100-pin high density connector.

![CN4\nSATA0\ncPCI-3510M\ndaughter board](.cpci-3510-50-15095-1040-24/79a3a517413df97bfeb2ab3c3e7cc920758bc64734dcc6e27f40a00c7bf061c3.jpg)

<table><tr><td>CN4</td><td>100-pin high density connector</td><td>SATA0</td><td>22-pin SATA connector</td></tr></table>

Figure 4-7: cPCI-3510(BL)M Blade Assembly Layout

# 4.7 cPCI-3510(BL)S Blade Assembly Layout

The dual-slot width cPCI-3510S Blade is comprised of the cPCI-3510 single-slot main board and the DB-3UMC riser card, expanding I/O connectivity with a XMC/PMC connector.

![DB-3UMC\nJN1 JN2\nJN3\nJN4](.cpci-3510-50-15095-1040-24/12393a3c7b397b80d2576d197acd2b77843090ce4f3de1fee1b352b153b79744.jpg)

<table><tr><td>JN3</td><td>XMC connector</td><td>JN1/JN2/JN4</td><td>PCM connectors</td></tr></table>

# 4.8 cPCI-3510(BL) Series Faceplate Layout

cPCI-3510(BL)
![GbE A/B\nUSB 3.0\nDVI\nPower LED\nWDT LED\nHDD LED\nReset Button\nThermal LED\nGP LED](.cpci-3510-50-15095-1040-24/99fe7bc7a67dbd42a4ef14c0369c69436ec70c641bd941c0406fbfb7646c84ad.jpg)

cPCI-3510(BL)D
![10(BL)D\nCOM1\nUSB 2.0\nPS/2\nKB/MS\nLine-in\nLine-out\nPower LED\nWDT LED\nReset Button\nThermal LED\nGP LED\nDVI-I\nCompactc®\nSS←\nHDD LED](.cpci-3510-50-15095-1040-24/eb0f570a4e63fa6ac66e467e43617c4aee4e819ce8a7251a70539f35c2c6b925.jpg)

cPCI-3510(BL)G
![BL)G\nDisplayPorts\nCOM1\nPS/2\nKB/MS\nUSB 2.0\nConnectiPC1®\nPower LED\nWDT LED\nThermal LED\nHDD LED\nReset Button\nGP LED\nDVI-I](.cpci-3510-50-15095-1040-24/9e8081ce1b8f3c3fb251133ed7f4848c6a6cf5ddc292b9ffb00eaba58893014a.jpg)

Figure 4-8: cPCI-3510(BL)/D/G Faceplate Layout

cPCI-3510(BL)L
![10(BL)L\nLAN Connector\nCOM\nC D\nA B\nSS\nPower LED\nReset Button\nWDT LED\nThermal LED\nGP LED\nDVI-I\nHDD LED](.cpci-3510-50-15095-1040-24/b32b515773caeb7baea60a75de97742a8aa9fec27f2eea09f8e3040009fc697f.jpg)

cPCI-3510(BL)M
![100-pin Connector\nMulti I/O\nCompactPCI®\nPower LED\nWDT LED\nReset Button\nGP LED\nDVI-I\nThermal LED\nHDD LED](.cpci-3510-50-15095-1040-24/ce0649d4fb120131c767fb1d8d299fd1e0230cf52e2f3bb17ffe8d415dcda875.jpg)

cPCI-3510(BL)S
![10(BL)S\nXMC Slot\nCompactPC8®\nA\nB\nSS\nLED Definitions\nsame as above\nReset Button\nGP LED\nDVI-I](.cpci-3510-50-15095-1040-24/8d616bbb8d7f0aa1c0f303c6c4a5a413c70962a830736c49fd0de1a5a35d31fd.jpg)

Figure 4-9: cPCI-3510L/M/S Faceplate Layout

cPCI-3510(BL)P: Same faceplate as cPCI-3510(BL)D but with XMC/PMC slot on Layer 3.

System LEDs

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="3">Power[30 80]</td><td rowspan="3">Green/Red</td><td>OFF</td><td>System is off</td></tr><tr><td>Red</td><td>System Power ready (PWGD)</td></tr><tr><td>Green</td><td>Post OK</td></tr><tr><td rowspan="2">WDT&lt;img src="images/e1c51d1adce61e7695a9022e436defbf83d1e823f64aa3d61825fe86f6ad3cbf.jpg"/&gt;</td><td rowspan="2">Orange</td><td>OFF</td><td>No Watchdog event</td></tr><tr><td>Blinking</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">Drive[218C]</td><td rowspan="2">Blue</td><td>OFF</td><td>No CF/CFast/mSATA/SATA activity</td></tr><tr><td>Blinking</td><td>Data read/write in process for CF/CFast/ mSATA/SATA drive</td></tr><tr><td rowspan="2">Overheat&lt;img src="images/38975d96b1f06343e6f970a7501667c1108fbfc5ffaf32b7d84e81cd85a5ec88.jpg"/&gt;</td><td rowspan="2">Red</td><td>OFF</td><td>CPU  $T_{junction}$  temperature is under 100°C</td></tr><tr><td>ON</td><td>CPU  $T_{junction}$  temperature exceeds 100°C</td></tr><tr><td rowspan="2">GP(General Purpose)&lt;img src="images/c123f69adafd2231680a0d0183fc12498069669b9685f9f13295b4f9565c5eb8.jpg"/&gt;</td><td rowspan="2">Yellow</td><td>OFF</td><td>No activity</td></tr><tr><td>ON/Blinking</td><td>Defined by user</td></tr></table>

Table 4-1: cPCI-3510(BL) Faceplate System LED Descriptions

# 4.9 cPCI-R3P00(T) RTM Board Layout

![rJ2\nSATA2\nSATA4\nSATA3\nCOM4\nCOM5\nLAN1/2\nUSB1\nUSB10\nVGA1](.cpci-3510-50-15095-1040-24/256d0d3a1759b2d9c601b15a891d192e083f07ae717c9d76c6b60bf764b33dd1.jpg)

<table><tr><td>COM5*</td><td>RS-232/422/485 port (converted from USB)</td><td>LAN1/2</td><td>Dual Ethernet ports</td></tr><tr><td>COM4</td><td>RS-232 port (Tx, Rx only)</td><td>VGA1</td><td>VGA port</td></tr><tr><td>SATA2/3/4</td><td>SATA ports</td><td>USB1/10</td><td>USB ports</td></tr><tr><td>rJ2</td><td>CompactPCI connector</td><td></td><td></td></tr></table>

(cPCI-R3P00 is 50mm deep and cPCI-R3P00T is 80mm deep)

Figure 4-10: cPCI-R3P00(T) RTM Board Layout
![The image displays a white document icon with a folded top-right corner. Faint gray horizontal lines run across the page, and a large, bold red checkmark is superimposed over the center. There is no text.](.cpci-3510-50-15095-1040-24/e9870c6ecc42e1def75196b3d4f34138695b4ec2d71a4a69d6db7d404b631252.jpg)
NOTE:

\*COM5 is incorrectly labeled COM3 on the A1 vers. PCB silkscreen.

# 4.10 cPCI-R3P00(T) RTM Faceplate

![COM4\nCOM5\nVGA\nUSBx2\nGbE x2](.cpci-3510-50-15095-1040-24/ed50bddcfbe17682cd5c9baa86fd9057b281320ba9e78f408ced5c775f7ef86e.jpg)

Figure 4-11: cPCI-R3P00(T) RTM Faceplate

# 4.11 Connector Pin Assignments

# USB 2.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![4\n3\n2\n1](.cpci-3510-50-15095-1040-24/7bc47f3148eb76cc13dc85e3cb76f9c85c178a86578882a804111717d73758f3.jpg)

Table 4-2: USB 2.0 Pin Definition

# USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.cpci-3510-50-15095-1040-24/bdaf3d32fb72884662dd2e607208399c896791933982fa922b03b2c8cbc02229.jpg)

DB-15 VGA Connector

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>Red</td><td>1</td><td>2</td><td>Green</td></tr><tr><td>Blue</td><td>3</td><td>4</td><td>N.C.</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>+5V.</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>N.C.</td><td>11</td><td>12</td><td>CRTDATA</td></tr><tr><td>HSYNC</td><td>13</td><td>14</td><td>VSYNC</td></tr><tr><td>CRTCLK</td><td>15</td><td></td><td></td></tr></table>

![Technical line drawing of a 16-pin electronic device (no text or symbols)](.cpci-3510-50-15095-1040-24/4950d9cee4785a5e5595bb3eeef4bfb8650ff1e841403d8a6fa64737dc80329c.jpg)

Table 4-3: VGA Pin Definition

DisplayPort Connectors

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>CN_DP0_P</td><td>2</td><td>Ground</td></tr><tr><td>3</td><td>CN_DP0_N</td><td>4</td><td>CN_DP1_P</td></tr><tr><td>5</td><td>Ground</td><td>6</td><td>CN_DP1_N</td></tr><tr><td>7</td><td>CN_DP2_P</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>CN_DP2_N</td><td>10</td><td>CN_DP3_P</td></tr><tr><td>11</td><td>Ground</td><td>12</td><td>CN_DP3_N</td></tr><tr><td>13</td><td>CN_CAD-L</td><td>14</td><td>CN_CEC</td></tr><tr><td>15</td><td>CN_AUX_P</td><td>16</td><td>Ground</td></tr><tr><td>17</td><td>CN_AUX_N</td><td>18</td><td>DDP_HPD</td></tr><tr><td>19</td><td>Ground</td><td>20</td><td>P3V3</td></tr></table>

![1\n2\n19\n20](.cpci-3510-50-15095-1040-24/ad3b6d29f2942348c97f0b9fd84bbb63ad921f4ba192e2d44f9cd8e122359ff9.jpg)

Table 4-4: DisplayPort Pin Definition

# DVI-I Connector

![Front view of a 24-pin D-sub connector (no text or symbols visible)](.cpci-3510-50-15095-1040-24/ce2118a2f6be099ee7664c91f6e13b82f8dc59eb0eec4afa58583bc869d2ecfa.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2-</td><td>16</td><td>Hot Plug Detect</td></tr><tr><td>2</td><td>TMDS Data2+</td><td>17</td><td>TMDS Data0-</td></tr><tr><td>3</td><td>GND</td><td>18</td><td>TMDSData0+</td></tr><tr><td>4</td><td>NC</td><td>19</td><td>GND</td></tr><tr><td>5</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>6</td><td>DDC Clock [SCL]</td><td>21</td><td>NC</td></tr><tr><td>7</td><td>DDC Data [SDA]</td><td>22</td><td>GND</td></tr><tr><td>8</td><td>Analog vertical sync</td><td>23</td><td>TMDS Clock +</td></tr><tr><td>9</td><td>TMDS Data1-</td><td>24</td><td>TMDS Clock -</td></tr><tr><td>10</td><td>TMDS Data1+</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>GND</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>NC</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>NC</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 4-5: DVI-I Connector Pin Definition

# RJ-45 Gigabit Ethernet Connectors

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_TX0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_TX0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_TX1+</td></tr><tr><td>4</td><td>—</td><td>LAN_TX2+</td></tr><tr><td>5</td><td>—</td><td>LAN_TX2-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_TX1-</td></tr><tr><td>7</td><td>—</td><td>LAN_TX3+</td></tr><tr><td>8</td><td>—</td><td>LAN_TX3-</td></tr></table>

Table 4-6: RJ-45 GbE Pin Definitions

Speed Activity
![8\n1](.cpci-3510-50-15095-1040-24/143461bc2dfa0fb808e375e96f51daa263b00c3f274aa30d82f415c7317feba4.jpg)

<table><tr><td colspan="2">Status</td><td>Speed LED (Green/Orange)</td><td>Activity LED (Yellow)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Orange</td><td>ON</td></tr><tr><td>Active</td><td>Orange</td><td>Blinking</td></tr></table>

Table 4-7: LAN LED Status Definitions

![The image displays a white document icon featuring faint horizontal gray lines across it. A large, thick red checkmark is superimposed over the center of the document. The entire graphic is enclosed within a solid black rectangular border.](.cpci-3510-50-15095-1040-24/e1b2c9c9f4dd40aca86c4a715a70c1cc3ddf402004d640b3ffa599d9888dd335.jpg)
NOTE:

The cPCI-R3P00 RTM LAN LED signals are not passed through from the main board and are not displayed on the face-plate LAN LEDs.

# PS/2 Keyboard/Mouse Connector

<table><tr><td>Pin #</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+5V</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

![6\n5\n4\n3\n2 1](.cpci-3510-50-15095-1040-24/75687defca865b1cc327aca8ba3b61ced8516507d03164b3bca57c3709019c23.jpg)

Table 4-8: PS/2 Keyboard/Mouse Pin Definition

# cPCI-3510(BL)D/P Serial Ports

# COM1 Connector (DB-9)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485(+)</td></tr><tr><td>1</td><td>DCD-L</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>RXD</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>TXD</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>DTR-L</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>—</td><td>—</td></tr><tr><td>8</td><td>CTS-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/3af731682c661c482267cbd34825b8dcdf4fea17591c1ea43b1df4e187441b33.jpg)

Table 4-9: cPCI-3510(BL)D/P COM1 (DB-9) Pin Definition
![The image displays a white icon resembling a sheet of paper with a folded top-left corner. The paper has several horizontal grey lines, suggesting text or a list. A large, bold red checkmark is drawn diagonally across the center of the document.](.cpci-3510-50-15095-1040-24/ecf5fdf999aae1a5fe9c45dbc5da0694db86afb43254fc6bb081024c95930c0d.jpg)
NOTE:

The COM mode setting for cPCI-3510(BL)D/P models is set using SW1\~SW4. See “COM1 Mode Selection Switches (SW1\~SW4)” on page 47.

# COM1 Mode Selection Switches (SW1\~SW4)

These switches set the cPCI-3510(BL)D/P COM1 to RS-232 full modem, RS-422, RS-485, or RS-485+ half-duplex mode. Switches SW1\~SW4 are located on the top edge of the cPCI-3510(BL)D daughter board. RS-232 full modem is set by default.

![1\n2\n3\n4\nNO](.cpci-3510-50-15095-1040-24/bd0ace743df5e43b379463218ed8c04b5750d1acb8db6eb720119ce0666eb224.jpg)

SW1

![1\n2\n3\n4\nON](.cpci-3510-50-15095-1040-24/dac9c006d01f3bbc1eac882905c7c63a86650f9874f5b966660a1bbe735abd84.jpg)

SW2

![1\nN\n3\n4\nO](.cpci-3510-50-15095-1040-24/b0e7771e9d55592ad20db8ccc32b114d888036f3ba7061558f0f1a0b24b85129.jpg)

SW3

![1\nN\n3\n4\nN](.cpci-3510-50-15095-1040-24/58831f8fb32e817c2bb9a111954f3ce14504b0717f23c711f6cbbedade64451e.jpg)

SW4

<table><tr><td>Mode</td><td>Pin</td><td>SW1</td><td>SW2</td><td>SW3</td><td>SW4</td></tr><tr><td rowspan="4">RS-232</td><td>1</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>4</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="4">RS-422</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>2</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td rowspan="4">RS-485</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>3</td><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td rowspan="4">RS-485+</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td><td>ON</td></tr><tr><td>3</td><td>ON</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>ON</td></tr></table>

Table 4-10: cPCI-3510(BL)D/P COM1 Mode Selection Switch Settings

![The image displays a standard icon of a white document with a folded top-left corner and horizontal lines representing text, overlaid with a large red checkmark.](.cpci-3510-50-15095-1040-24/f59d2b554794613b30b712161c75fe2ced7a6e6212a6d0f3be4445478d68f8cb.jpg)
NOTE:

The COM mode setting for cPCI-3510(BL)D/P models must be set using the SW1\~SW4 DIP switches above. The cPCI-3510(BL)G/T COM1/2 Output BIOS setting is only used for cPCI-3510(BL)G/T models.

# cPCI-3510(BL)G Serial Ports

COM1 Connector (RJ-45)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>4</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>5</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>6</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>7</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>8</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![The image displays a diagram of an RJ45 connector housing. To the right of the central connector shape, there are horizontal lines representing the pins. The number '1' is positioned at the top right, and the number '6' is positioned near the bottom right.](.cpci-3510-50-15095-1040-24/f7e0c2f8e98b7d581cfd2856f6ad1193dc2a2b40cc2ea0ef99e4d4a9ba588e29.jpg)

Table 4-11: cPCI-3510(BL)G COM1 (RJ-45) Pin Definition
![The image displays a white document icon featuring a folded top-right corner and faint horizontal lines, with a large red checkmark overlaid on it.](.cpci-3510-50-15095-1040-24/9e0a22bb6d517f3027abc9b2399a41f79935bcd25a0a08a824a0deae827a2048.jpg)
NOTE:

The COM mode settings for cPCI-3510(BL)G models are set in the BIOS: see “Output (cPCI-3510(BL)G COM1/2)” on page 106.

# COM1 Connector with DB-9 Adapter

An RJ-45 to DB-9 adapter cable is provided to breakout the COM1 signals.

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>3</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>4</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>5</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>8</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/bf7aba902ec3d20b023b3d9f19983248e5435e478ec2d7a436f90a7922a3cb40.jpg)

Table 4-12: cPCI-3510(BL)G COM1 (DB-9 adapter) Pin Definition

![The image displays a graphic icon of a document. It features a white sheet of paper with a folded top-right corner and a black outline. Several faint horizontal gray lines run across the page, simulating text. A large, bold red checkmark is superimposed over the left side of the document.](.cpci-3510-50-15095-1040-24/73bfd5051110e38d2345b4ed5ba409b219a8e2c8963fd5b644107f8f68b88dd5.jpg)
NOTE:

The cPCI-3510(BL)G COM1 RS-422/485 pin definitions are different from the common DB-9 pin definitions. An RS-422/485 DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions.

# RS-422/485 Adapter Dongle for cPCI-3510(BL)G

A DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions

<table><tr><td>DB-9 (Female) Signal Name</td><td>Pin #</td><td>DB-9 (Male) Signal Name</td></tr><tr><td>NC</td><td>1</td><td>TXD-</td></tr><tr><td>RXD-</td><td>2</td><td>TXD+</td></tr><tr><td>TXD-</td><td>3</td><td>RXD+</td></tr><tr><td>NC</td><td>4</td><td>RXD-</td></tr><tr><td>NC</td><td>5</td><td>NC</td></tr><tr><td>NC</td><td>6</td><td>NC</td></tr><tr><td>TXD+</td><td>7</td><td>NC</td></tr><tr><td>RXD+</td><td>8</td><td>NC</td></tr><tr><td>NC</td><td>9</td><td>NC</td></tr></table>

Table 4-13: RS-422/485 Adapter Dongle Pin Definition

COM1 with RS-422/485 Dongle (DB-9)

<table><tr><td>Pin #</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>—</td><td>—</td></tr><tr><td>6</td><td>—</td><td>—</td></tr><tr><td>7</td><td>—</td><td>—</td></tr><tr><td>8</td><td>—</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/5cc2155729b682273c311a6cc76d03c41db231e16d6776065186bc6aa671d3fa.jpg)

Table 4-14: cPCI-3510(BL)G COM1 with RS-422/485 Dongle Pin Definition

# COM2 Pin Header

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>3</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>4</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>5</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>6</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>7</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>8</td><td>RI-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>10</td><td>NC</td><td>—</td><td>—</td></tr></table>

![1\n2\n9\n10](.cpci-3510-50-15095-1040-24/7c47bc854cab625042fbe349c36c86dfec04aa6ba8b8af4ac8371308a5cde049.jpg)

Table 4-15: cPCI-3510(BL)G COM2 Pin Header Definition
![The image displays a white piece of paper with a folded upper-right corner and faint horizontal lines. A large, red checkmark is superimposed diagonally over the document.](.cpci-3510-50-15095-1040-24/20259065fc11c29c6658daf99df967b99aaada2f52b8addcfb1366132330cf3c.jpg)
NOTE:

The COM mode settings for cPCI-3510(BL)G models are set in the BIOS: see “Output (cPCI-3510(BL)G COM1/2)” on page 106.

# cPCI-R3P00(T) RTM Serial Ports

# COM4 Connector (DB-9))

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>—</td></tr><tr><td>2</td><td>RXD</td></tr><tr><td>3</td><td>TXD</td></tr><tr><td>4</td><td>—</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>—</td></tr><tr><td>7</td><td>—</td></tr><tr><td>8</td><td>—</td></tr><tr><td>9</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/d3f5584912e4fd62a32a4abd3402687f861ccf4632d271984f0863a9b01e29b7.jpg)

Table 4-16: cPCI-R3P00(T) RTM COM4 Pin Definition

# COM5 Connector (DB-9)

![The image features a white document icon with a folded top-right corner. Faint gray horizontal lines run across the lower portion of the page. A large, red checkmark is superimposed diagonally over the center of the document.](.cpci-3510-50-15095-1040-24/6ba010dd3cf4a91b9d1c9659694a707da2025c72155ff00410a983681fc21db2.jpg)
NOTE:

The cPCI-R3P00(T) RTM COM5 RS-422/485 pin definitions are different from the common DB-9 pin definitions. An RS-422/485 DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions. See “RS-422/485 Adapter Dongle for cPCI-3510(BL)G” on page 49

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>3</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>4</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>—</td><td>—</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>8</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/c3c1f653800917e7578e9986623bb973e0e2da5a90591be8d576cdf65f058222.jpg)

Table 4-17: cPCI-R3P00(T) RTM COM5 Pin Definition
COM5 with RS-422/485 Dongle (DB-9)

<table><tr><td>Pin #</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>—</td><td>—</td></tr><tr><td>6</td><td>—</td><td>—</td></tr><tr><td>7</td><td>—</td><td>—</td></tr><tr><td>8</td><td>—</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3510-50-15095-1040-24/246a35bf97498223365cd4a2fa6893197c8e156993906ff25d18cda3f888767b.jpg)

Table 4-18: cPCI-R3P00(T) RTM COM5 with RS-422/485 Dongle Pin Def'n

cPCI-3510M 100-pin I/O Connector (CN4)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>USB9_CN-N</td></tr><tr><td>3</td><td>USB9_CN-P</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB1_CN-N</td><td>6</td><td>USB1_CN-P</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>TMDS_I2C_DATA</td><td>10</td><td>TMDS_I2C_CLK</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>TMDSB_DATA2B</td></tr><tr><td>13</td><td>TMDSB_DATA2</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>TMDSB_DATA1B</td><td>16</td><td>TMDSB_DATA1</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>TMDSB_DATA0B</td></tr><tr><td>19</td><td>TMDSB_DATA0</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>TMDSB_CLKB</td><td>22</td><td>TMDSB_CLK</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>P5V_DVI1</td></tr><tr><td>25</td><td>TMDSB_HPD</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>NC</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>TMDS_I2C_DATA</td></tr><tr><td>31</td><td>TMDS_I2C_CLK</td><td>32</td><td>GND</td></tr><tr><td>33</td><td>TMDSB_DATA2B</td><td>34</td><td>TMDSB_DATA2</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>TMDSB_DATA1B</td></tr><tr><td>37</td><td>TMDSB_DATA1</td><td>38</td><td>GND</td></tr><tr><td>39</td><td>TMDSB_DATA0B</td><td>40</td><td>TMDSB_DATA0</td></tr><tr><td>41</td><td>GND</td><td>42</td><td>TMDSB_CLKB</td></tr><tr><td>43</td><td>TMDSB_CLK</td><td>44</td><td>GND</td></tr><tr><td>45</td><td>P5V_DVI2</td><td>46</td><td>TMDSB_HPD</td></tr><tr><td>47</td><td>GND</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>NC</td><td>50</td><td>GND</td></tr><tr><td>51</td><td>P5V_USB_1_9</td><td>52</td><td>P5V_USB_1_9</td></tr><tr><td>53</td><td>P5V_USB_1_9</td><td>54</td><td>P5V_USB_1_9</td></tr><tr><td>55</td><td>GND</td><td>56</td><td>GND</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>P5V_KBMS</td></tr><tr><td>59</td><td>MSCLK_CN</td><td>60</td><td>MSDATA_CN</td></tr><tr><td>61</td><td>KBCLK_CN</td><td>62</td><td>KBDATA_CN</td></tr></table>

![1\n2\n9 9\n10 0](.cpci-3510-50-15095-1040-24/0c157945938fa4d53df508b5cff5c71f7cc2f3516dcb778d89dd681cb3cdb3e4.jpg)

Table 4-19: cPCI-3510M 100-pin I/O Connector Pin Definition

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>63</td><td>GND</td><td>64</td><td>GND</td></tr><tr><td>65</td><td>COM1_RXD_CN</td><td>66</td><td>COM1_CTS-L_CN</td></tr><tr><td>67</td><td>GND</td><td>68</td><td>COM1_TXD_CN</td></tr><tr><td>69</td><td>COM1_RTS-L_CN</td><td>70</td><td>GND</td></tr><tr><td>71</td><td>COM1_DTR-L_CN</td><td>72</td><td>COM1_DSR-L_CN</td></tr><tr><td>73</td><td>COM1_DCD-L_CN</td><td>74</td><td>GND</td></tr><tr><td>75</td><td>COM2_RXD_CN</td><td>76</td><td>COM2_CTS-L_CN</td></tr><tr><td>77</td><td>GND</td><td>78</td><td>COM2_TXD_CN</td></tr><tr><td>79</td><td>COM2_RTS-L_CN</td><td>80</td><td>GND</td></tr><tr><td>81</td><td>COM2_DTR-L_CN</td><td>82</td><td>COM2_DSR-L_CN</td></tr><tr><td>83</td><td>COM2_DCD-L_CN</td><td>84</td><td>AGND_AU</td></tr><tr><td>85</td><td>NC</td><td>86</td><td>NC</td></tr><tr><td>87</td><td>NC</td><td>88</td><td>NC</td></tr><tr><td>89</td><td>NC</td><td>90</td><td>NC</td></tr><tr><td>91</td><td>NC</td><td>92</td><td>AGND_AU</td></tr><tr><td>93</td><td>L_IN_R</td><td>94</td><td>L_IN_L</td></tr><tr><td>95</td><td>L_IN_JD</td><td>96</td><td>AGND_AU</td></tr><tr><td>97</td><td>HP_R</td><td>98</td><td>HP_L</td></tr><tr><td>99</td><td>HP_JD</td><td>100</td><td>AGND_AU</td></tr></table>

Table 4-19: cPCI-3510M 100-pin I/O Connector Pin Definition

# Serial ATA Connectors on RTM (CN4-R, CN5-R)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX+</td></tr><tr><td>3</td><td>TX-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX-</td></tr><tr><td>6</td><td>RX+</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n7](.cpci-3510-50-15095-1040-24/74a1f9877c72c9ea59af533777b6b26dd8fd8f989e1a1349eba663d1074586ac.jpg)

Table 4-20: Serial ATA Connector on RTM

# SATA Conn. on cPCI-3510(BL)D/(BL)G/M Daughter Board

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>NC</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>NC</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>NC</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-3510-50-15095-1040-24/bdabbc7c1fecc82ea3f3be132ec43fa42d2633c738f561f100f5de1bedc8f8d8.jpg)

Table 4-21: SATA on cPCI-3510(BL)D/G/M Daughter Board Pin Def'n

CFast Socket (on CFast carrier board)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>Ground</td><td>S1</td></tr><tr><td>SATA_TX-P</td><td>S2</td></tr><tr><td>SATA_TX-N</td><td>S3</td></tr><tr><td>Ground</td><td>S4</td></tr><tr><td>SATA_RX-N</td><td>S5</td></tr><tr><td>SATA_RX-P</td><td>S6</td></tr><tr><td>Ground</td><td>S7</td></tr><tr><td>CFast_CDI</td><td>P1</td></tr><tr><td>Ground</td><td>P2</td></tr><tr><td>NC</td><td>P3</td></tr><tr><td>NC</td><td>P4</td></tr><tr><td>NC</td><td>P5</td></tr><tr><td>NC</td><td>P6</td></tr><tr><td>Ground</td><td>P7</td></tr><tr><td>CFast_LED1</td><td>P8</td></tr><tr><td>CFast_LED2</td><td>P9</td></tr><tr><td>NC</td><td>P10</td></tr><tr><td>NC</td><td>P11</td></tr><tr><td>NC</td><td>P12</td></tr><tr><td>P3V3</td><td>P13</td></tr><tr><td>P3V3</td><td>P14</td></tr><tr><td>Ground</td><td>P15</td></tr><tr><td>Ground</td><td>P16</td></tr><tr><td>CFast_CDO</td><td>P17</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.cpci-3510-50-15095-1040-24/4f6e018f55b886dec5480ac710ee0666b205f0fd1eed8170d037aa33fa2fc9d8.jpg)

![24\nP1\nS1](.cpci-3510-50-15095-1040-24/9083c2234564c372ff44f9f744e811a8f80d96caee4400794cc4da0bd56e3947.jpg)

Table 4-22: CFast Socket Pin Definition

Layer-2 Daughter Board Connector (CN1)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>USB2-N</td><td>1</td><td>2</td><td>-12V</td></tr><tr><td>USB2-P</td><td>3</td><td>4</td><td>+12</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>USB3-N</td><td>7</td><td>8</td><td>HDA_SDIN0</td></tr><tr><td>USB3-P</td><td>9</td><td>10</td><td>HDA_R_SDOUT</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>SATA_ICH_RX-N0</td><td>13</td><td>14</td><td>HDA_R_SYNC</td></tr><tr><td>SATA_ICH_RX-P0</td><td>15</td><td>16</td><td>HDA_R_BIT_CLK</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>SATA_TX-P0</td><td>19</td><td>20</td><td>CK_L2_PCIE1-P</td></tr><tr><td>SATA_TX-N0</td><td>21</td><td>22</td><td>CK_L2_PCIE1-N</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCIE_TXN5</td><td>25</td><td>26</td><td>CK_L2_PCIE2-P</td></tr><tr><td>PCIE_TXP5</td><td>27</td><td>28</td><td>CK_L2_PCIE2-N</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCIE_RXN5</td><td>31</td><td>32</td><td>HDA_R_RST-L</td></tr><tr><td>PCIE_RXP5</td><td>33</td><td>34</td><td>SPKR</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>L2_PCIE_RST-L</td></tr><tr><td>PCIE_RXN4</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>PCIE_RXP4</td><td>39</td><td>40</td><td>USB_2_3_OC-L</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>COM1_DCD-L</td></tr><tr><td>PCIE_TXN4</td><td>43</td><td>44</td><td>COM1_RI-L</td></tr><tr><td>PCIE_TXP4</td><td>45</td><td>46</td><td>COM1_CTS-L</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>COM1_DTR-L</td></tr><tr><td>MSCLK</td><td>49</td><td>50</td><td>COM1_RTS-L</td></tr><tr><td>MSDATA</td><td>51</td><td>52</td><td>COM1_DSR-L</td></tr><tr><td>KBCLK</td><td>53</td><td>54</td><td>COM1_SOUT</td></tr><tr><td>KBCDATA</td><td>55</td><td>56</td><td>COM1_SIN</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>+3.3V</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>+3.3V</td></tr></table>

![2\n1\n60\n59](.cpci-3510-50-15095-1040-24/ac84fb86dba4ad784b68904f4edfc5d6a67a2c4427972c6d66f3e0457d368d90.jpg)

Table 4-23: Layer-2 Daughter Board Connector Pin Definition

Storage Daughter Board Connector (CN2)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>PCH_SPKR</td><td>1</td><td>2</td><td>CLK33_TPM</td></tr><tr><td>SIO_SPKR</td><td>3</td><td>4</td><td>LPC_FRAME-L</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>TPM_RST-L</td></tr><tr><td>CN_VCC_RTC</td><td>7</td><td>8</td><td>LPC_AD3</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>LPC_AD2</td></tr><tr><td>NC</td><td>11</td><td>12</td><td>LPC_AD1</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>LPC_AD0</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>TPM_LPCPD</td></tr><tr><td>NC</td><td>17</td><td>18</td><td>PCH_SERIRQ</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>TPM_CLKRUN</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>TPM_GPIO</td></tr><tr><td>NC</td><td>23</td><td>24</td><td>NC</td></tr><tr><td>NC</td><td>25</td><td>26</td><td>NC</td></tr><tr><td>NC</td><td>27</td><td>28</td><td>NC</td></tr><tr><td>NC</td><td>29</td><td>30</td><td>NC</td></tr><tr><td>NC</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>NC</td><td>33</td><td>34</td><td>NC</td></tr><tr><td>NC</td><td>35</td><td>36</td><td>NC</td></tr><tr><td>GND</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>SATA_PCH_RX-N0</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>SATA_PCH_RX-P0</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>GND</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>SATA_PCH_TX-N0</td><td>45</td><td>46</td><td>NC</td></tr><tr><td>SATA_PCH_TX-P0</td><td>47</td><td>48</td><td>NC</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>NC</td></tr><tr><td>CFast_CDI</td><td>51</td><td>52</td><td>NC</td></tr><tr><td>CFast_CDO</td><td>53</td><td>54</td><td>NC</td></tr><tr><td>GND</td><td>55</td><td>56</td><td>NC</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>P3V3</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>P3V3</td></tr></table>

![2\n1\n60\n59](.cpci-3510-50-15095-1040-24/3655ffed120521064de0dd4d9f736e8fc7945ed823c9cb00e541c1f343684286.jpg)

Table 4-24: Storage Daughter Board Connector Pin Definition

cPCI-3510(BL)G Daughter Board Connector (CN3)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>NC</td><td>1</td><td>2</td><td>RS232_COM2_SEL-L</td></tr><tr><td>NC</td><td>3</td><td>4</td><td>COM2_DCD-L</td></tr><tr><td>NC</td><td>5</td><td>6</td><td>COM2_RI-L</td></tr><tr><td>NC</td><td>7</td><td>8</td><td>COM2_CTS-L</td></tr><tr><td>NC</td><td>9</td><td>10</td><td>COM2_DTR-L</td></tr><tr><td>NC</td><td>11</td><td>12</td><td>COM2_RTS-L</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>COM2_DSR-L</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>COM2_SOUT</td></tr><tr><td>NC</td><td>17</td><td>18</td><td>COM2_SIN</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>NC</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>NC</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCH_DDPD_AUXN</td><td>25</td><td>26</td><td>PCH_DDPC_AUXN</td></tr><tr><td>PCH_DDPD_AUXP</td><td>27</td><td>28</td><td>PCH_DDPC_AUXP</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCH_DDPD_0N</td><td>31</td><td>32</td><td>PCH_DDPC_0N</td></tr><tr><td>PCH_DDPD_0P</td><td>33</td><td>34</td><td>PCH_DDPC_0P</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>GND</td></tr><tr><td>PCH_DDPD_1N</td><td>37</td><td>38</td><td>PCH_DDPC_1N</td></tr><tr><td>PCH_DDPD_1P</td><td>39</td><td>40</td><td>PCH_DDPC_1P</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>GND</td></tr><tr><td>PCH_DDPD_2N</td><td>43</td><td>44</td><td>PCH_DDPC_2N</td></tr><tr><td>PCH_DDPD_2P</td><td>45</td><td>46</td><td>PCH_DDPC_2P</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>GND</td></tr><tr><td>PCH_DDPD_3N</td><td>49</td><td>50</td><td>PCH_DDPC_3N</td></tr><tr><td>PCH_DDPD_3P</td><td>51</td><td>52</td><td>PCH_DDPC_3P</td></tr><tr><td>GND</td><td>53</td><td>54</td><td>GND</td></tr><tr><td>DDPD_CTRLCLK</td><td>55</td><td>56</td><td>DDPC_CTRLCLK</td></tr><tr><td>DDPD_CTRLDATA</td><td>57</td><td>58</td><td>DDPC_CTRLDATA</td></tr><tr><td>DDPD_HPD</td><td>59</td><td>60</td><td>DDPC_HPD</td></tr></table>

![2\n1\n60\n59](.cpci-3510-50-15095-1040-24/e27a53b302adca136eece66b34004650c602c9c456d6ebdf5dab98991229c7ea.jpg)

Table 4-25: cPCI-3510(BL)G Daughter Board Connector Pin Definition

# PMC/XMC Daughter Board Connector

(on cPCI-3510(BL)D/(BL)G daughter board)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>NC</td><td>1</td><td>2</td><td>-12V</td></tr><tr><td>NC</td><td>3</td><td>4</td><td>+12V</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>NC</td><td>7</td><td>8</td><td>NC</td></tr><tr><td>NC</td><td>9</td><td>10</td><td>NC</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>NC</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>NC</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>CK_PCIE1_P</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>CK_PCIE1_N</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCIE_TXN2</td><td>25</td><td>26</td><td>CK_PCIE2_P</td></tr><tr><td>PCIE_TXP2</td><td>27</td><td>28</td><td>CK_PCIE2_N</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCIE_R_RXN2</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>PCIE_R_RXP2</td><td>33</td><td>34</td><td>NC</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>PCIE_RST#</td></tr><tr><td>PCIE_R_RXN1</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>PCIE_R_RXP1</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>PCIE_TXN4</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>PCIE_TXP4</td><td>45</td><td>46</td><td>NC</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>NC</td></tr><tr><td>NC</td><td>49</td><td>50</td><td>NC</td></tr><tr><td>NC</td><td>51</td><td>52</td><td>NC</td></tr><tr><td>NC</td><td>53</td><td>54</td><td>NC</td></tr><tr><td>NC</td><td>55</td><td>56</td><td>NC</td></tr><tr><td>+5V</td><td>57</td><td>58</td><td>+3.3V</td></tr><tr><td>+5V</td><td>59</td><td>60</td><td>+3.3V</td></tr></table>

![2\n1\n60\n59](.cpci-3510-50-15095-1040-24/b1858df97aa8bf81577ad38100b3ac78bfffb0834a1c6888bf4ff2e31ded762a.jpg)

Table 4-26: PMC/XMC Daughter Board Connector Pin Definition

# PMC Connector on PMC/XMC Daughter Board (JN1/2)

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td></tr><tr><td>1</td><td>PMC_TCK</td><td>P12V</td></tr><tr><td>2</td><td>N12V</td><td>PMC_TRST-L</td></tr><tr><td>3</td><td>GND</td><td>PMC_TMS</td></tr><tr><td>4</td><td>PCIX_INTA-L</td><td>NC (PMC_TDO)</td></tr><tr><td>5</td><td>PCIX_INTB-L</td><td>PMC_TDI</td></tr><tr><td>6</td><td>PCIX_INTC-L</td><td>GND</td></tr><tr><td>7</td><td>PMC_MOD-L1</td><td>GND</td></tr><tr><td>8</td><td>P5V</td><td>NC</td></tr><tr><td>9</td><td>PCIX_INTD-L</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td></tr><tr><td>11</td><td>GND</td><td>PMC_MOD-L2</td></tr><tr><td>12</td><td>P3V3_PMCAUX</td><td>P3V3</td></tr><tr><td>13</td><td>CLK66_PCIX_PMC</td><td>PMC_RST-L</td></tr><tr><td>14</td><td>GND</td><td>PMC_MOD-L3</td></tr><tr><td>15</td><td>GND</td><td>P3V3</td></tr><tr><td>16</td><td>PCIX_GNT-L0</td><td>PMC_MOD-L4</td></tr><tr><td>17</td><td>PCIX_REQ-L0</td><td>PMC_PME-L</td></tr><tr><td>18</td><td>P5V</td><td>GND</td></tr><tr><td>19</td><td>PMC_VIO</td><td>PCIX_AD30</td></tr><tr><td>20</td><td>PCIX_AD31</td><td>PCIX_AD29</td></tr><tr><td>21</td><td>PCIX_AD28</td><td>GND</td></tr><tr><td>22</td><td>PCIX_AD27</td><td>PCIX_AD26</td></tr><tr><td>23</td><td>PCIX_AD25</td><td>PCIX_AD24</td></tr><tr><td>24</td><td>GND</td><td>PCIX_AD23</td></tr><tr><td>25</td><td>GND</td><td>PMC_IDSEL</td></tr><tr><td>26</td><td>PCIX_CBE-L3</td><td>PCIX_AD23</td></tr><tr><td>27</td><td>PCIX_AD22</td><td>P3V3</td></tr><tr><td>28</td><td>PCIX_AD21</td><td>PCIX_AD20</td></tr><tr><td>29</td><td>PCIX_AD19</td><td>PCIX_AD18</td></tr><tr><td>30</td><td>P5V</td><td>GND</td></tr><tr><td>31</td><td>PCIX_FRAME-L</td><td>PCIX_AD16</td></tr><tr><td>32</td><td>PCIX_AD17</td><td>PCIX_CBE-L2</td></tr></table>

![64\n63\n2\n1](.cpci-3510-50-15095-1040-24/528dad5a50f31bf7521c351f0df3278d803f4d95bfe0ed1d7dae5a7783d6fde7.jpg)

Table 4-27: PMC Connector Pin Definitions

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td></tr><tr><td>33</td><td>PCIX_FRAME-L</td><td>GND</td></tr><tr><td>34</td><td>GND</td><td>NC</td></tr><tr><td>35</td><td>GND</td><td>PCIX_TRDY-L</td></tr><tr><td>36</td><td>PCIX_IRDY-L</td><td>P3V3</td></tr><tr><td>37</td><td>PCIX_DEVSEL-L</td><td>GND</td></tr><tr><td>38</td><td>P5V</td><td>PCIX_STOP-L</td></tr><tr><td>39</td><td>PCIX_PCIXCAP</td><td>PCIX_PERR-L</td></tr><tr><td>40</td><td>PCIX_LOCK-L</td><td>GND</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td></tr><tr><td>42</td><td>NC</td><td>PCIX_SERR-L</td></tr><tr><td>43</td><td>PCIX_PAR</td><td>PCIX_CBE-L1</td></tr><tr><td>44</td><td>GND</td><td>GND</td></tr><tr><td>45</td><td>PMC_VIO</td><td>PCIX_AD14</td></tr><tr><td>46</td><td>PCIX_AD15</td><td>PCIX_AD13</td></tr><tr><td>47</td><td>PCIX_AD12</td><td>PCIX_M66EN</td></tr><tr><td>48</td><td>PCIX_AD11</td><td>PCIX_AD10</td></tr><tr><td>49</td><td>PCIX_AD9</td><td>PCIX_AD8</td></tr><tr><td>50</td><td>P5V</td><td>P3V3</td></tr><tr><td>51</td><td>GND</td><td>PCIX_AD7</td></tr><tr><td>52</td><td>PCIX_CBE-L0</td><td>NC</td></tr><tr><td>53</td><td>PCIX_AD6</td><td>P3V3</td></tr><tr><td>54</td><td>PCIX_AD5</td><td>NC</td></tr><tr><td>55</td><td>PCIX_AD4</td><td>NC</td></tr><tr><td>56</td><td>GND</td><td>GND</td></tr><tr><td>57</td><td>PMC_VIO</td><td>NC</td></tr><tr><td>58</td><td>PCIX_AD3</td><td>NC</td></tr><tr><td>59</td><td>PCIX_AD2</td><td>GND</td></tr><tr><td>60</td><td>PCIX_AD1</td><td>NC</td></tr><tr><td>61</td><td>PCIX_AD0</td><td>PCIX_ACK64-L</td></tr><tr><td>62</td><td>P5V</td><td>P3V3</td></tr><tr><td>63</td><td>GND</td><td>GND</td></tr><tr><td>64</td><td>PCIX_REQ64-L</td><td>NC</td></tr></table>

Table 4-27: PMC Connector Pin Definitions (cont'd)

XMC Connector on PMC/XMC Daughter Board (JN3)
![F1\nA1\nF19\nA19](.cpci-3510-50-15095-1040-24/876841d49df93baeb3e85c2979971b0ecb368026853b3d1a49e8be18e89a0ab7.jpg)

<table><tr><td>Pin#</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>RXP</td><td>RXN</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>PCIE_RST-L</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>5</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>+12V</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>-12V</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>TXP</td><td>TXN</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>13</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>15</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>17</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>19</td><td>CK-P</td><td>CK-N</td><td>Not used</td><td>Not used</td><td>Not used</td><td>Not used</td></tr></table>

Table 4-28: XMC Connector Pin Definition

CompactPCI J1 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>CPCI_AD1</td><td>+5V</td><td>CPCI_VIO</td><td>CPCI_AD0</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>CPCI_AD4</td><td>CPCI_AD3</td><td>+5V</td><td>CPCI_AD2</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>CPCI_AD7</td><td>GND</td><td>+3.3V</td><td>CPCI_AD6</td><td>CPCI_AD5</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>CPCI_AD9</td><td>CPCI_AD8</td><td>CPCI_M66EN</td><td>CPCI_CBE-L0</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_AD12</td><td>GND</td><td>VIO</td><td>CPCI_AD11</td><td>CPCI_AD10</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>CPCI_AD15</td><td>CPCI_AD14</td><td>GND</td><td>CPCI_AD13</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>CPCI_SERR-L</td><td>GND</td><td>+3.3V</td><td>CPCI_PAR</td><td>CPCI_CBE-L1</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>NC</td><td>NC</td><td>GND</td><td>CPCI_PERR-L</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>CPCI_DEVSEL-L</td><td>CPCI_PCIXCAP</td><td>VIO</td><td>CPCI_STOP-L</td><td>CPCI_LOCK-L</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>CPCI_FRAME-L</td><td>CPCI_IRDY-L</td><td>NC</td><td>CPCI_TRDY-L</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>CPCI_AD18</td><td>CPCI_AD17</td><td>CPCI_AD16</td><td>GND</td><td>CPCI_CBE-L2</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>CPCI_AD21</td><td>GND</td><td>+3.3V</td><td>CPCI_AD20</td><td>CPCI_AD19</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CPCI_CBE-L3</td><td>NC</td><td>CPCI_AD23</td><td>GND</td><td>CPCI_AD22</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>CPCI_AD26</td><td>GND</td><td>VIO</td><td>CPCI_AD25</td><td>CPCI_AD24</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CPCI_AD30</td><td>CPCI_AD29</td><td>CPCI_AD28</td><td>GND</td><td>CPCI_AD27</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CPCI_REQ-L0</td><td>GND</td><td>+3.3V</td><td>CPCI_CLK0</td><td>CPCI_AD31</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_RESET-L</td><td>GND</td><td>CPCI_GNT-L0</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>CPCI_HEALTHY-L</td><td>VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_IRQA-L</td><td>CPCI_IRQB-L</td><td>CPCI_IRQC-L</td><td>+5V</td><td>CPCI_IRQD-L</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>cPCI_TCK-L</td><td>+5V</td><td>cPCI_TMS-L</td><td>NC</td><td>cPCI_TDI-L</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>NC</td><td>cPCI_TRST-L</td><td>+12V</td><td>+5V</td><td>GND</td></tr></table>

Table 4-29: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PCI_CLK6</td><td>GND</td><td>LAN2_TXDP1</td><td>LAN1_TXDP3</td><td>LAN1_TXDP1</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PCI_CLK5</td><td>GND</td><td>LAN2_TXDN1</td><td>LAN1_TXDN3</td><td>LAN1_TXDN1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>LAN2_TXDP0</td><td>LAN1_TXDP2</td><td>LAN1_TXDP0</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LAN2_TXDP3</td><td>LAN2_TXDP2</td><td>LAN2_TXDN0</td><td>LAN1_TXDN2</td><td>LAN1_TXDN0</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LAN2_TXDN3</td><td>LAN2_TXDN2</td><td>J2_RSTJ</td><td>CPCI_REQ_L6</td><td>CPCI_GNT_L6</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>CLK_PCIE8_N</td><td>CLK_PCIE6_P</td><td>DEGJ</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>CLK_PCIE8_P</td><td>CLK_PCIE6_N</td><td>FALJ</td><td>CPCI_REQ_L5</td><td>CPCI_GNT_L5</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>3PE_CLK-</td><td>CLK_PCIE5_P</td><td>PCIE_RST-L</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>3PE_CLK+</td><td>CLK_PCIE5_N</td><td>PCIE_RST-L</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>PCIE8_RX_P</td><td>PCIE_RST-L</td><td>PCIE_RST-L</td><td>VGA_VSY</td><td>SATA_RX-P2</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>PCIE8_RX_N</td><td>PCIE_TXP8</td><td>COM4_TX</td><td>SATA_TX-P2</td><td>SATA_RX-N2</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>PCIE7_RX_P</td><td>PCIE_TXN8</td><td>COM4_RX</td><td>SATA_TX-N2</td><td>SATA_RX-P3</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>PCIE7_RX_N</td><td>PCIE_TXP7</td><td>USB_0P</td><td>SATA_TX-P3</td><td>SATA_RX-N3</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>PCIE6_RX_P</td><td>PCIE_TXN7</td><td>USB_0N</td><td>SATA_TX-N3</td><td>SATA_RX-P4</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>PCIE6_RX_N</td><td>PCIE_TXP6</td><td>USB_3P</td><td>SATA_TX-P4</td><td>SATA_RX-N4</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>PCIE5_RX_P</td><td>PCIE_TXN6</td><td>USB_3N</td><td>SATA_TX-N4</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>PCIE5_RX_N</td><td>PCIE_TXP5</td><td>USB_10P</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>VIO</td><td>PCIE_TXN5</td><td>USB_10N</td><td>USB_OC0</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr></table>

Table 4-30: CompactPCI J2 Connector Pin Definition

<table><tr><td></td><td>Ethernet port</td></tr><tr><td></td><td>VGA</td></tr><tr><td></td><td>Serial ATA</td></tr><tr><td></td><td>PCI-Express</td></tr><tr><td></td><td>Serial port</td></tr><tr><td></td><td>USB port</td></tr></table>

cPCI-R3P00 rJ2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>NC</td><td>GND</td><td>2_ETH_B+</td><td>1_ETH_D+</td><td>1_ETH_B+</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>GND</td><td>2_ETH_B-</td><td>1_ETH_D-</td><td>1_ETH_B-</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>2_ETH_A+</td><td>1_ETH_C+</td><td>1_ETH_A+</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>2_ETH_D+</td><td>2_ETH_C+</td><td>2_ETH_A-</td><td>1_ETH_C-</td><td>1_ETH_A-</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>2_ETH_D-</td><td>2_ETH_C-</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>VGA_VSY</td><td>2_SATA_RX+</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>NC</td><td>NC</td><td>COM4_TX</td><td>2_SATA_TX+</td><td>2_SATA_RX-</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>NC</td><td>NC</td><td>COM4_RX</td><td>2_SATA_TX-</td><td>3_SATA_RX+</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>NC</td><td>NC</td><td>0_USB+</td><td>3_SATA_TX+</td><td>3_SATA_RX-</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>NC</td><td>NC</td><td>0_USB-</td><td>3_SATA_TX-</td><td>4_SATA_RX+</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>NC</td><td>NC</td><td>1_USB+</td><td>4_SATA_TX+</td><td>4_SATA_RX-</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>NC</td><td>NC</td><td>1_USB-</td><td>4_SATA_TX-</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>10_USB+</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>NC</td><td>10_USB-</td><td>USB1_10_OC</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr></table>

Table 4-31: cPCI-R3P00 rJ2 Connector Pin Definition

![Ethernet port\nVGA\nSerial ATA\nPCI-Express\nSerial port\nUSB port](.cpci-3510-50-15095-1040-24/b9a8fb6c2e510afd6d23eec42e1d0ee10583f5fa03109180b8c8247918ca33f3.jpg)

cPCI-R3P00T rJ2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>4PE_CLK-</td><td>2_PE_CLK+</td><td>NC</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>4PE_CLK+</td><td>2_PE_CLK-</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>3PE_CLK+</td><td>1_PE_CLK+</td><td>4_PE_CLKE#</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>3PE_CLK-</td><td>1_PE_CLK-</td><td>3_PE_CLKE#</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>4PE_RX00+</td><td>1_PE_CLKE#</td><td>2_PE_CLKE#</td><td>VGA_VSY</td><td>2_SATA_RX+</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>4PE_RX00-</td><td>4PE_TX00+</td><td>COM4_TX</td><td>2_SATA_TX+</td><td>2_SATA_RX-</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>3PE_RX00+</td><td>4PE_TX00-</td><td>COM4_RX</td><td>2_SATA_TX-</td><td>3_SATA_RX+</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>3PE_RX00-</td><td>3PE_TX00+</td><td>0_USB+</td><td>3_SATA_TX+</td><td>3_SATA_RX-</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>2PE_RX00+</td><td>3PE_TX00-</td><td>0_USB-</td><td>3_SATA_TX-</td><td>4_SATA_RX+</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>2PE_RX00-</td><td>2PE_TX00+</td><td>1_USB+</td><td>4_SATA_TX+</td><td>4_SATA_RX-</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>1PE_RX00+</td><td>2PE_TX00-</td><td>1_USB-</td><td>4_SATA_TX-</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>1PE_RX00-</td><td>1PE_TX00+</td><td>10_USB+</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>1PE_TX00-</td><td>10_USB-</td><td>USB1_10_OC</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr></table>

Table 4-32: cPCI-R3P00T rJ2 Connector Pin Definition

![VGA\nSerial ATA\nPCI-Express\nSerial port\nUSB port](.cpci-3510-50-15095-1040-24/74c14c911c24161eb5ea2723c34883c4e4bf3884f32d15e3e47a4b070d9f2a1d.jpg)

# 4.12 Jumper Settings

# Load BIOS Default Jumper (JP1)

The cPCI-3510(BL) Load BIOS Default Jumper is located on the CF/CFast storage board. To load the default BIOS settings, short pins 2-3 on JP1, then reinstall the jumper cap to pins 1-2.

<table><tr><td>BIOS Setting</td><td>Connection</td><td>JP1</td></tr><tr><td>Normal</td><td>1 – 2</td><td>&lt;img src="images/6490c932d0f590076fff3feb7150143b891a2ec9634c04fe8c155db6396fc22c.jpg"/&gt;</td></tr><tr><td>Load default BIOS</td><td>2 – 3</td><td>&lt;img src="images/7003878f3b0c202151ebe6833786a88c2ae7c0a337bc32583fed4cc55487a5c1.jpg"/&gt;</td></tr></table>

Table 4-33: Load BIOS Default Jumper Settings

# XMC VPWR Select Jumper (JPX1)

This jumper is located on the PMC/XMC daughter board near JN1/2 and selects the XMC VPWR setting. 5V is set by default.

<table><tr><td>Mode</td><td>Connection</td><td>JPX1</td></tr><tr><td>+5V (Default)</td><td>1 – 2</td><td>&lt;img src="images/05e1ceeaa29b71477c317611f5cbf10ca889c04c54dbfbf26b140456989df21c.jpg"/&gt;</td></tr><tr><td>+12V</td><td>2 – 3</td><td>&lt;img src="images/dc6f8b539df5b2c172f109a28f09276159bd5a932812aa494c734ced4ec7301d.jpg"/&gt;</td></tr></table>

Table 4-34: XMC VPWR Select Jumper Settings

# PMC V(I/O) Select Jumper (JPX2)

This jumper is located on the PMC/XMC daughter board near JN1/2 and selects the PMC V(I/O) setting. 3.3V is set by default.

<table><tr><td>Mode</td><td>Connection</td><td>JPX2</td></tr><tr><td>+5V</td><td>1 – 2</td><td>&lt;img src="images/e8b863a8f6c3c90d68662fffce200a9c3cefcd885f5a30cb1cf0d7f89cea7eb3.jpg"/&gt;</td></tr><tr><td>+3.3V (Default)</td><td>2 – 3</td><td>&lt;img src="images/e819a08cd54ef09b1385bd79be45b902696ba7a4df4b6cf7bf115ca27f4ec58f.jpg"/&gt;</td></tr></table>

Table 4-35: PMC V(I/O) Select Jumper Settings

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# 5 Getting Started

This chapter describes the following installation procedures for the cPCI-3510(BL) and rear transition module:

▶ CPU and Heatsink
▶ 2.5" SATA storage drive
▶ CFast card
▶ PCI Mezzanine Card
▶ Processor blade installation to chassis
▶ RTM installation to chassis

# 5.1 CPU and Heatsink

The cPCI-3510(BL) Series come with CPU and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance.

# 5.2 SATA Drive Installation

The cPCI-3510(BL)D/G/L/M/P 2/3-slot versions provide space to install a slim type 2.5" Serial-ATA storage drive.

# Installing a SATA Drive - cPCI-3510(BL)D/G/L/M/P

1. A 2.5" SATA drive can be assembled in the location marked as below.

![Close-up of an electronic circuit board with a green PCB and labeled components (no readable text or symbols beyond labels)](.cpci-3510-50-15095-1040-24/2dbb1303409a3aa92cc811ab57a6f190746083340630a05093fc0e9faf1b062b.jpg)

2. 2.Prepare a 2.5" SATA drive and locate the brackets and screws in the accessory kit.

![Exterior view of a silver ADLINK SSD device with metal hardware and screws, placed on a plain surface (no text or symbols visible on the device itself)](.cpci-3510-50-15095-1040-24/ff6942680b0249d3ff0010cd87f7c3fbb0e4047aeef9c65a5f9aa927c42396af.jpg)

3. Screw the brackets to the 2.5" SATA drive.

![ADLINK\nSATA SSD](.cpci-3510-50-15095-1040-24/6e86629d2a11eb74b49f532da9659d5058f98ad5e248b8549f0f92c6d1558c1b.jpg)

4. Align the drive assembly with the cPCI-3510(BL) and insert it into the onboard SATA connector until it is properly seated.

![SATA SSD\nADLINK](.cpci-3510-50-15095-1040-24/ded8a84744091d0fdc891260be49bd90f1e6639e9dc40039c4e00ee704bdfbfe.jpg)

5. Secure the hard drive assembly to the cPCI-3510(BL) with four M2.5 screws provided.

![S55D\nSATA\nADLINK\nGP\n1.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000](.cpci-3510-50-15095-1040-24/eeb217a653f33c7f2efa9112cfe13552076e21eb592e6f1fd8542005a4e79e9d.jpg)

# 5.3 Installing a CFast Card

To install a CFast card, locate the CFast connector on the CFAST storage board and insert the card until it is properly seated.

![Close-up of an electronic circuit board with a highlighted component (no readable text or symbols)](.cpci-3510-50-15095-1040-24/c6d999e4abd1dda7ac9b31794f8ec74314e6da389fac30445adaab16da0e8c17.jpg)

# 5.4 Installing the cPCI-3510(BL) to the Chassis

The cPCI-3510(BL) may be installed in a system or peripheral slot of a 3U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.
2. Remove the blank face cover from the selected slot, if necessary.
3. Press down on the release catches of the cPCI-3510(BL) ejector handles.

4. Remove the black plastic caps securing the mounting screws to the faceplate.

5. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.

6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module faceplate.

7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

# 5.5 RTM Installation - cPCI-R3P00(T)

The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-3510(BL) Series and related RTMs, make sure the RTM is the correct matching model.

![The image displays an icon of a white document or page with a folded top-left corner. Faint horizontal grey lines run across the page, resembling text or a list. A large, bold red checkmark is superimposed over the center of the document.](.cpci-3510-50-15095-1040-24/afa8bacc8a84b3cf1bc781367d1e945e6462fd0e4718de80d2c7f5008cb16ac4.jpg)
NOTE:

You must install the correct RTM to enable functions (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs.

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# 6 Driver Installation

The cPCI-3510(BL) drivers are available from the ADLINK website (http://www.adlinktech.com/PD/web/PD\_detail.php?cKind=&pid=1291). ADLINK provides validated drivers for Windows 764-bit. We recommend using these drivers to ensure compatibility. The VxWorks BSP can be downloaded from the cPCI-3510(BL) product page on the ADLINK website

# 6.1 cPCI-3510(BL) Drivers

The following describes the cPCI-3510(BL) driver installation procedures for Windows 7 64-bit. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.

1. Before beginning Windows installation, save the AHCI driver to a USB flash drive. During Windows installation, install the AHCI driver from the USB flash drive when prompted.
2. Install the chipset driver by extracting and running the program in ...\Chipset\Intel Chipset Device Software\_All OS\_9.4.0.1017.zip.
3. Install the graphics driver and utilities by extracting and running the program in ...\Graphics\Intel® HD Graphics 4600\_Win7\_64bit\_9.18.10.3220.zip.
4. Install the Ethernet Controller driver by following the steps described in "6.2 Ethernet Controller Driver" on page 78.
5. Install the Management Engine (ME) driver and utilities by extracting and running the program in ...\Chipset\Intel Management Engine Interface 9.0.0.1209.zip.
6. Install the TPM driver by extracting and running the program in ...\TPM\Infineon\_Trusted\_Platform\_Module\_2.1.1.0.zip.
7. Install the audio driver and utilities by extracting and running the program in ...\Audio\Realtek\_High Definition Audio\_Win7\_8\_64\_6.0.1.6873.zip.

# 6.2 Ethernet Controller Driver

1. Extract the contents of ...\LAN\Intel® I210 Gigabit Network connection\_Win7 64bit\_12.7.28.0.zip.
2. Open the Device Manager and go to Other Devices. You will see a "question mark" next to Ethernet Controller R-click on Ethernet Controller and choose "Update Driver Software...".

![Device Manager\nFile Action View Help\n3510-PC\nComputer\nDisk drives\nDisplay adapters\nHuman Interface Devices\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nOther devices\nEthernet Control\nEthernet Control\nEthernet Control\nFT232R USB UA\nPCI Serial Port\nPCI Simple Con\nUniversal Serial\nPortable Devices\nPorts (COM & LPT)\nProcessors\nSound, video and game controllers\nSystem devices\nUniversal Serial Bus controllers\nUpdate Driver Software...\nDisable\nUninstall\nScan for hardware changes\nProperties\nLaunches the Update Driver Software Wizard for the selected device.](.cpci-3510-50-15095-1040-24/5da11db1e8b01f5b1377639a79f5be9afcf16db70d1d5c16e09b82a5bbeec9ac.jpg)

# 3. Click "Browse my computer for driver software".

![Update Driver Software - Ethernet Controller\nHow do you want to search for driver software?\n→ Search automatically for updated driver software\nWindows will search your computer and the Internet for the latest driver software\nfor your device, unless you've disabled this feature in your device installation\nsettings.\n→ Browse my computer for driver software\nLocate and install driver software manually.\nCancel](.cpci-3510-50-15095-1040-24/7a522a4e26d9e7ea14303442bc87f648011724beb15365679af107f60d9e290b.jpg)

# 4. Navigate to the folder where you extracted the contents of the zip file and click "OK". Click "Next" to install the driver.

![Device Manager\nFile  Action  View  Help\n3510- \nC\nDi\nDi\nH\nID\nKe\nM\nM\nO\nT\nInclude subfolders\nBrowse for driver\nSearch for driver software\nC:\Users\3510\Docum\nLet me pick for\nThis list will show\nsoftware in the s\nBrowse For Folder\nSelect the folder that contains drivers for your hardware.\nNetwork\n3510 pic\ncPCI-3510 driver\nCDM 2.08.28 WHQL Certified-x64\nIntel_USB_3.0_xHC_Driver_AllOS_2.0.0.102\nIntel® Chipset Device Software_All OS_9.4\nIntel® HD Graphics 4600_Win7_64bit_9.18\nIntel® I210 Gigabit Network connection_\nIntel® I210 Gigabit Network connection\nIntel® I210 Gigabit Network connection_Win7 64bit_12.4.36.0\nDate created: 3/24/2014 12:59 PM\nFolder:\nIntel® I210 Gigabit Network connection_Win7 64bit_12.4.36.0\nOK  Cancel\nNext  Cancel](.cpci-3510-50-15095-1040-24/e727817bf5b6c329e6d71018e77f0b8873f4934818d896547f74c62c0a318996.jpg)

# 6.3 USB-to-Serial Converter Driver (RTM)

The COM5 serial port on the cPCI-R3P00(T) is converted from the USB3 port by a USB-to-serial converter (see "cPCI-R3P00 RTM" on page 17). To install the driver for the converter, follow the procedure below.

1. Extract the contents of ...\cPCI-3510\COM\CDM 2.08.28 WHQL Certified-x64.zip.
2. Open the Device Manager and go to Other Devices. You will see a "question mark" next to FT2332R USB UART. R-click on FT2332R USB UART and choose "Update Driver Software...".

![Device Manager\nFile Action View Help\n3510-PC\nComputer\nDisk drives\nDisplay adapters\nHuman Interface Devices\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nOther devices\nFT232P USD UART\nPortable D\nPorts (CO)\nProcessors\nSound, video\nSystem de\nUniversal S\nUpdate Driver Software...\nDisable\nUninstall\nScan for hardware changes\nProperties\nLaunches the Update Driver Software Wizard for the selected device.](.cpci-3510-50-15095-1040-24/d6340945fc7d1631129f70218ce995a75d060cbfe239543c397084a088b0a69a.jpg)

# 3. Click "Browse my computer for driver software".

![Update Driver Software - FT232R USB UART\nHow do you want to search for driver software?\n→ Search automatically for updated driver software\nWindows will search your computer and the Internet for the latest driver software for your device, unless you've disabled this feature in your device installation settings.\n→ Browse my computer for driver software\nLocate and install driver software manually.\nCancel](.cpci-3510-50-15095-1040-24/e9c22b8177e081470df671c316cfdd6f94021922ab214b7766e6f9069c6cde26.jpg)

# 4. Navigate to the folder where you extracted the contents of the zip file and click "OK". Click "Next" to install the driver

![Device Manager\nFile Action View Help\nBrowse For Folder\nSelect the folder that contains drivers for your hardware.\nDesktop\nLibraries\n3510\nComputer\nNetwork\n3510 pic\ncPCI-3510 driver\nCDM 2.08.28 WHQL Certified-x64\nCDM v2.08.28 Certified\nFolder: CDM 2.08.28 WHQL Certified-x64\nOK Cancel\nNext Cancel\n3510\nUpdate Driver So\nBrowse for driv\nSearch for driver soft\nC:\Users\3510\Desk\nInclude subfolder\nLet me pick\nThis list will show installed driver software compatible with the device, and all driver\nsoftware in the same category as the device.](.cpci-3510-50-15095-1040-24/d863c6ecb05ac36f17504cff7657fc27183b8ded2a5ccbb8b15fedd490facf6c.jpg)

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# 7 Watchdog Timer

This section describes the operation of the cPCI-3510's watchdog timer (WDT). The primary function of the WDT is to monitor the cPCI-3510's operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

▶ enabling and disabling
▶ set and get current configuration
▶ reloading timeout value

The cPCI-3510(BL) custom WDT functionality is implemented using an Intelligent Platform Management Controller (IPMC) and controlled using Intelligent Platform Management Interface (IPMI) commands.

# 7.1 Setting the Watchdog by IPMI Commands

The following section describes how to set the WDT functions using IPMI commands. For more detailed information about IPMI commands, please refer to IPMI specification: Intelligent Platform Management Interface Specification Second Generation v2.0.

# WDT Commands

These commands enable the watchdog function, set the count-down period, and reload the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after the counter reaches zero.

<table><tr><td>Command</td><td>NetFn Code</td><td>Cmd Code</td></tr><tr><td>Reset Watchdog Timer</td><td>App (18h)</td><td>22h</td></tr><tr><td>Set Watchdog Timer</td><td>App (18h)</td><td>24h</td></tr><tr><td>Get Watchdog Timer</td><td>App (18h)</td><td>25h</td></tr></table>

# Reset Watchdog Timer

This command is used to reload the WDT.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>22h</td><td>Defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# Set Watchdog Timer

This command is used to start and restart the Watchdog Timer using the specified countdown value.

\*Note: don't stop timer: If the WDT is already running, the countdown value will get set to the specified value and countdown will continue from that point. If timer is already stopped, it will remain stopped. If the pre-timeout interrupt bit is set, it will get cleared.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="4">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>24h</td><td>Defined command</td></tr><tr><td>2</td><td>[7] - 1b = don’t log[6] - 1b = don’t stop timer*[5:3] - reserved[2:0] - timer use000b = reserved001b = BIOS FRB2010b = BIOS/POST011b = OS Load100b = SMS/OS101b = OEM110b -111b = reserved</td><td>Timer Use</td></tr><tr><td>3</td><td>[7] - reserved[6:4] - pre-timeout interrupt000b = none001b = SMI (optional)010b = NMI / DiagnosticInterrupt (optional)011b = Messaging Interrupt100b,111b = reserved[3] - reserved[2:0] - timeout action000b = no action001b = Hard Reset010b = Power Down011b = Power Cycle100b,111b = reserved</td><td>Timer Actions</td></tr><tr><td rowspan="4">Request</td><td>4</td><td>1h~ffh (‘1h’ based.)</td><td>Pre-timeout interval in seconds.</td></tr><tr><td>5</td><td>[7] - reserved[6] - reserved[5] - OEM[4] - SMS/OS[3] - OS Load[2] - BIOS/POST[1] - BIOS FRB2[0] - reserved0b = leave alone1b = clear timer useexpiration bit</td><td>Timer Use Expiration flags clear</td></tr><tr><td>6</td><td>00h~ffh ,LS byte (100 ms/ count)</td><td>Initial countdown value</td></tr><tr><td>7</td><td>00h~ffh ,MS byte (100 ms/ count)</td><td>Initial countdown value</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# Get Watchdog Timer

This command is used to get the current WDT configuration.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>25h</td><td>Defined command</td></tr><tr><td rowspan="2">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>[7] - 1b = don’t log[6] - 1b = don’t stop timer[5:3] - reserved[2:0] - timer use000b = reserved001b = BIOS FRB2010b = BIOS/POST011b = OS Load100b = SMS/OS101b = OEM110b -111b = reserved</td><td>Timer Use</td></tr><tr><td rowspan="7">Response</td><td>2</td><td>[7] - reserved[6:4] - pre-timeout interrupt000b = none001b = SMI (optional)010b = NMI / DiagnosticInterrupt (optional)011b = Messaging Interrupt100b,111b = reserved[3] - reserved[2:0] - timeout action000b = no action001b = Hard Reset010b = Power Down011b = Power Cycle100b,111b = reserved</td><td>Timer Actions</td></tr><tr><td>3</td><td>1h~ffh (‘1h’ based.)</td><td>Pre-timeout interval in seconds.</td></tr><tr><td>4</td><td>[7] - reserved[6] - reserved[5] - OEM[4] - SMS/OS[3] - OS Load[2] - BIOS/POST[1] - BIOS FRB2[0] - reserved0b = leave alone1b = clear timer useexpiration bit</td><td>Timer Use Expiration flags clear</td></tr><tr><td>5</td><td>00h~ffh ,LS byte (100 ms/ count)</td><td>Initial countdown value</td></tr><tr><td>6</td><td>00h~ffh ,MS byte (100 ms/ count)</td><td>Initial countdown value</td></tr><tr><td>7</td><td>00h~ffh ,LS byte (100 ms/ count)</td><td>Present countdown value</td></tr><tr><td>8</td><td>00h~ffh ,MS byte (100 ms/ count)</td><td>Present countdown value</td></tr></table>

# Example WDT Programming Procedure

Configuration of the watchdog timer is via serial interface. A detailed description of the WDT IPMI commands can be found above. The following example shows the procedure for configuring the WDT works over a serial console. See “Communications with IPMC” on page 131. for more information.

```txt
[18 00 24 43 01 01 08 50 00] => Step 1: Set parameters to WDT
[1C 00 24 00] => Step 1: Response of setting OK.

[18 00 22] => Step 2: Trigger WDT
[1C 00 22 00] => Step 2: Response of trigger OK.

[18 00 25] => Get current configuration
[1C 00 25 00 43 01 01 00 50 00 28 00] => Response during WDT countdown

&lt;A&gt;: BMC Watchdog expired
&lt;A&gt;: Reset alert

[18 00 25] => Get current configuration
[1C 00 25 00 03 01 01 08 50 00 00 00 ] => Response after Reset
```
Figure 7-1: Example procedure for configuring the WDT over serial console

1. Configure the WDT by using the raw IPMI command "Set Watchdog Timer" described above.

"Set Watchdog Timer" Command:
```yaml
[18 00 24 43 01 01 08 50 00]
Description:
0x18: Net function. Defined in IPMI specification
0x00: Bus ID. Usually "0x00".
0x24: Command. Defined in IPMI specification.
0x43: Set "Don't stop timer" and "OS Load".
0x01: Hard Reset.
0x01: Pre-timeout interval in seconds.
0x08: Timer Use Expiration flags cleared by OS Load.
0x50: Initial countdown value. Sets the interval before watchdog timer expires.
80 count: 100ms * 80 = 8000 ms = 8 seconds
Successful response to command:
[1C 00 24 00]
```

2. Reload the WDT counter by using the raw IPMI command "Reset Watchdog Timer".

"Reset Watchdog Timer" Command:

[18 00 22]

Successful response to Command:

[1C 00 22 00]

3. Get the WDT configuration by using the "Get Watchdog Timer" command.

"Get Watchdog Timer" Command:

[18 00 25]

Successful response to Command:

[1C 00 25 00 43 01 01 00 50 00 28 00]

0x18: Net function. Defined in IPMI specification

0x00: Bus ID. Usually "0x00".

0x25: Command. Defined in IPMI specification.

0x43: Get timer operation status and "OS Load".

The first nibble is "4". This means the timer is running. If the first nibble is "0", then the watchdog timer has timed out and stopped. The second nibble is "Timer Use". A value of "3" means the option is set to "OS Load".

0x01: Hard Reset.

0x01: Pre-timeout interval in seconds.

0x00: Timer Use Expiration flags clear.

0x50: Initial countdown value. The current interval before the watchdog timer expires.

80 count. 100ms \* 80 = 8000ms = 8 seconds.

0x10: Present countdown value. How much time is left before timer expires.

16 count: 100ms \* 16 = 1600ms = 1.6 seconds

# 8 BIOS Setup Utility

The following chapter describes basic navigation for the AMI EFI BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt; Press DEL to run Setup &gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![American\nMegatrends\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.\ncPCI-3510 REV:0.90\nPress (CTRL + P) to Enter MEBX setup menu\nPress (DEL) or (ESC) to enter setup.](.cpci-3510-50-15095-1040-24/4406e273c65c5c22f013dfbd589b9f009f64f711ffe7b7caadd2e5f21d607272.jpg)

Note: In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

<table><tr><td colspan="2">Main Advanced Chipset Boot Security Save &amp; Exit</td></tr><tr><td colspan="2">BIOS Information
BIOS Vendor American Megatrends
Core Version 4.6.5.4
Compliancy UEFI 2.3.1; PI 1.2
Project Version C3510 0.90 x64
Build Date and Time 03/15/2013 14:21:00</td></tr><tr><td colspan="2">System Date [Mon 03/18/2013]
System Time [18:02:23]</td></tr><tr><td colspan="2">Access Level Administrator</td></tr><tr><td></td><td>Set the Time. Use Tab to switch between Time elements.
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![**BIOS Setup Utility** connects via a downward arrow to **Screens**.\n\n*   A box labeled **Left and Right Keys to Select a Setup Screen** connects via a dotted arrow to **Screen 1**.\n*   **Screen 1** connects horizontally to **Screen 2**, which connects to **Screen 3**, which connects to **Screen 4**, which connects to **Screen 5**.\n*   A downward arrow from the center of the screens row leads to the text **Items**.\n\nBelow **Items** is a grid structure:\n*   A box labeled **Tab Key to Select Fields** connects via a dotted arrow to the first box in the top row (containing the ± symbol).\n*   The top row consists of three boxes containing the ± symbol, connected horizontally to each other.\n*   A box labeled **± To Change Field Values** connects via a dotted arrow to the third box in the top row.\n*   A bracket labeled **Fields** encompasses the two rows of boxes.\n*   Between the top and bottom rows of boxes, there is a downward arrow and an upward arrow.\n*   A box labeled **Up and Down Keys to Select a Setup Item** connects via a dotted arrow to the upward arrow.](.cpci-3510-50-15095-1040-24/e388d1150c38e748815ded191fdfa41533a2b5c88dcd98faf5ec50bb46a94e64.jpg)

![The image displays a white document icon featuring horizontal lines and a folded top-left corner. A large red checkmark is superimposed over the document.](.cpci-3510-50-15095-1040-24/38ec181c73de3acabd5f15135287ad94b60fc8ef790c8642d4c8e3c8b5a7f80e.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

The &lt; F8 &gt; key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the &lt; F8 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

# Hotkey Descriptions

# Enter

The &lt;Enter&gt; key allows you to display or change the setup option listed for a particular setup item. The &lt;Enter&gt; key can also allow you to display the setup sub-screens.

F1

The &lt; F1 &gt; key allows you to display the General Help screen. Press the &lt; F1 &gt; key to open the General Help screen.

![General Help\n↑↓++ : Move\nEnter : Select\n+/- : Value\nESC : Exit\nF1 : General Help\nF2 : Previous Values\nF3 : Optimized Defaults\nF4 : Save & Exit Setup\n(K) : Scroll help area upwards\n(M) : Scroll help area downwards\nOk](.cpci-3510-50-15095-1040-24/1423fa4ec26591caaca22de5d0197b8b62c9763cf50a4447e2d8a35030b1a3c9.jpg)

F2 The &lt; F2 &gt; key on your keyboard is the previous values key. It is not displayed on the key legend by default. To set the previous values settings of the BIOS, press the &lt; F2 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The previous values settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

![Load Previous Values\nLoad Previous Values?\nYes No](.cpci-3510-50-15095-1040-24/e69599ebd010745852e64703c7288c46da89db25905f0e73ddf6b1e9d8bcf498.jpg)

F3 The &lt; F3 &gt; key on your keyboard is the optimized defaults key. To set the optimized defaults settings of the BIOS, press the &lt; F3 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The optimized defaults settings allow the motherboard to boot up with the optimized defaults of options set. This can lessen the probability of conflicting settings.

![Load Optimized Defaults\nLoad Optimized Defaults?\nYes	No](.cpci-3510-50-15095-1040-24/65c78e37bd347f6ecbda3899532ad85994fad9c64e30607d221525d046883dba.jpg)

F4 The &lt; F4 &gt; key allows you to save any changes you have made and exit Setup. Press the &lt; F10 &gt; key to save your changes. The following screen will appear:

![Save & Exit Setup\nSave configuration and exit?\nYes	No](.cpci-3510-50-15095-1040-24/dbbddfc0bc007711051cc37648b1d6e02621cdb2af47eda6e422611580fd41e5.jpg)

Press the &lt;Enter&gt; key to save the configuration and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

ESC The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. The following screen will appear:

![Exit Without Saving\nQuit without saving?\nYes No](.cpci-3510-50-15095-1040-24/938c6f502373b28782be9d225a7df463f21ee5ffb3ab5abdb3d9d00c9603f755.jpg)

Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

# 8.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.

<table><tr><td colspan="2">Main Advanced Chipset Boot Security Save &amp; Exit</td></tr><tr><td colspan="2">BIOS Information
BIOS Vendor American Megatrends
Core Version 4.6.5.4
Compliancy UEFI 2.3.1; PI 1.2
Project Version C3510 0.90 x64
Build Date and Time 03/15/2013 14:21:00</td></tr><tr><td colspan="2">System Date [Mon 03/18/2013]
System Time [18:02:23]</td></tr><tr><td colspan="2">Access Level Administrator</td></tr><tr><td></td><td>Set the Time. Use Tab to switch between Time elements.
+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# System & Board Info

The Main BIOS setup screen reports BIOS and Board version information.

# System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the &lt;Arrow&gt; keys. Enter new values using the keyboard. Press the &lt;Tab&gt; key or the &lt;Arrow&gt; keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

![The image displays a digital icon of a white document or piece of paper with a folded top-left corner. Faint gray horizontal lines run across the page, simulating text. A large, bold red checkmark is centered on the document.](.cpci-3510-50-15095-1040-24/7cf2b624ce3b166f52ba2ad3e7a606f79cb868e23ed71fe12690649a210318f1.jpg)
NOTE:

The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

# 8.3 Advanced BIOS Setup

Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Advanced BIOS Setup screen is shown below.

The sub menus are described on the following pages.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nMain Advanced Chipset Boot Security Save & Exit\nVGA Output (Front)\n► Trusted Computing\n► CPU Configuration\n► SATA Configuration\n► PCH-FW Configuration\n► Intel(R) Anti-Theft Technology Configuration\n► AMT Configuration\n► USB Configuration\n► Hardware Monitor\n► IT8783F Super IO Configuration\n► Serial Port Console Redirection\nControl VGA Output.\nFront = VGA will output from\nfront panel\nRear = VGA will output from\nrear panel.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/f66bb3b00c3d26a326b3340513606a299a2bde9dd57b5c4a4c09782a3f00c9dd.jpg)

# 8.3.1 ACPI Settings

You can use this screen to select options for the ACPI Advanced Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on this page. The screen is shown below.

![Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.\nAdvanced\nACPI Settings\nSelect ACPI sleep state the\nsystem will enter when the\nSUSPEND button is pressed.\nACPI Sleep State (S1 only(CPU Stop C...))\n×: Select Screen\n^v: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/0afd1c825e53260bb19f533fee73e9c041a192414ef77e9f6e48a7b9b5c71a7c.jpg)

# ACPI Sleep State

Select the highest ACPI sleep state the system will enter, when the SUSPEND button is pressed. Set this value to S1 only, Suspend Disable.

# S1 only (CPU Stop Clock)

Power On Suspend - Under this setting the CPU is not executing instructions, all power resources that supply system level reference of S0 are off, system memory context is maintained, devices that reference power resources that are on are on, and devices that can wake-up the system can cause the CPU to continue to execute from where it left off.

# 8.3.2 Trusted Computing

Trusted Computing is an industry standard to make personal computers more secure through a dedicated hardware chip, called a Trusted Platform Module (TPM). This option allows you to enable or disable the TPM support.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.</td></tr><tr><td>Configuration
Security Device Support [Disable]</td><td rowspan="2">Enables or Disables BIOS support for security device.
O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>Current Status Information
SUPPORT TURNED OFF</td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# Security Device Support

OS will not show TPM. Reset of platform is required. Set this value to Enabled/Disabled.

# TPM State

Determine whether TPM state change requires Password Authentication. Set this value to Enabled/Disabled.

# Pending TPM operation

Schedule TPM operation. The settings for this value are Enable, Disable and Clear.

# 8.3.3 CPU Configuration

You can use this screen to select options for the CPU Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.</td></tr><tr><td>Advanced</td><td></td></tr><tr><td>CPU Configuration Genuine Intel(R) CPU 0000 @ 2.00GHz CPU Signature 306c2 Microcode Patch ffff0006 Max CPU Speed 2000 MHz Min CPU Speed 800 MHz CPU Speed 2300 MHz Processor Cores 4 Hyper-threading [Enabled] Active Processor Cores [All] Intel Virtualization Technology [Enabled] EIST [Enabled] Turbo Mode [Enabled]</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled. +: Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F3: Optimized Defaults F4: Save &amp; Exit ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# Hyper-Threading

▶ Enabled: for Windows and Linux (OS optimized for Hyper-Threading Technology).
▶ Disabled: for other OS (OS not optimized for Hyper-Threading Technology).

# Intel Virtualization Tech

When enabled, a VMM can utilize the additional hardware capability provided by Vanderpool Technology. Set this value to Enabled/Disabled.

# EIST

Set this value to Enabled/Disabled.

# Turbo Mode

Set this value to Enabled/Disabled.

# 8.3.4 SATA Configuration

You can use this screen to select options for the SATA Configuration Settings. An example of the SATA Configuration screen is shown below.

<table><tr><td>SATA Controller(s)</td><td>[Enabled]</td><td rowspan="12">Enable or disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>[AHCI]</td></tr><tr><td>Serial ATA Port 0</td><td>Empty</td></tr><tr><td>Port 0</td><td>[Enabled]</td></tr><tr><td>Hot Plug</td><td>[Disabled]</td></tr><tr><td>Serial ATA Port 1</td><td>Empty</td></tr><tr><td>Port 1</td><td>[Enabled]</td></tr><tr><td>Hot Plug</td><td>[Disabled]</td></tr><tr><td>Serial ATA Port 2</td><td>Empty</td></tr><tr><td>Port 2</td><td>[Enabled]</td></tr><tr><td>Hot Plug</td><td>[Disabled]</td></tr><tr><td>Serial ATA Port 3</td><td>ST9250315AS (250.0GB)</td></tr><tr><td>Port 3</td><td>[Enabled]</td><td rowspan="5">+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Hot Plug</td><td>[Disabled]</td></tr><tr><td>Serial ATA Port 4</td><td>Empty</td></tr><tr><td>Port 4</td><td>[Enabled]</td></tr><tr><td>Hot Plug</td><td>[Disabled]</td></tr></table>

# SATA Controller(s)

Enable or disable SATA device.

# SATA Mode Selection

The SATA can be configured as a legacy IDE, RAID and AHCI mode.

# SATA Port 0\~4

Display SATA device name string. Set this value to Enabled/Disabled.

# Hot Plug

Appears when SATA mode is AHCI. SATA port Hot Plug support. Set this value to Enabled/Disabled.

# 8.3.5 PCH-FW Configuration

# Intel TXT(LT) Configuration

You can use this screen to view ME related information. For example, ME FW Version, ME Firmware Mode, ME Firmware Type, ME Firmware SKU..etc. An example of the ME screen is shown below.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc. Advanced</td></tr><tr><td>ME FW Version 9.0.0.1272
ME Firmware Mode Normal Mode
ME Firmware Type Full Sku Firmware
ME Firmware SKU 5MB
PTT Capability / State 0 / 0</td><td></td></tr><tr><td></td><td>+: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# 8.3.6 Intel ® Anti-Theft Technology Configuration

You can use this screen to select options for the Intel AT Configuration Settings. An example of the Intel AT Configuration screen is shown below.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nIntel(R) Anti-Theft Technology Configuration\nIntel(R) Anti-Theft Technology (Enabled)\nEnter Intel(R) AT Suspend Mode (Disabled)\nEnable/Disable Intel(R) AT in BIOS for testing only.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/4f738ecd6b8181513f70a5a1c4f3c2240d6c2e6f478986d3c1f97288075229a6.jpg)

# Intel® Anti-Theft Support

Set this value is Enable/Disable.

# 8.3.7 AMT Configuration

You can use this screen to select options for the AMT settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc. Advanced</td></tr><tr><td>Intel AMT [Enabled]</td><td>Enable/Disable Intel (R) Active Management Technology BIOS Extension. Note : iAMT H/W is always enabled. This option just controls the BIOS extension execution. If enabled, this requires additional firmware in the SPI device</td></tr><tr><td></td><td>+: Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F3: Optimized Defaults F4: Save &amp; Exit ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236, Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# Intel AMT

Intel AMT feature. Set this value to Enabled/Disabled.

# 8.3.8 USB Configuration

You can use this screen to select options for the USB Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. The screen is shown below.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nUSB Configuration\nUSB Devices:\n  1 Drive, 1 Keyboard, 1 Mouse, 2 Hubs\nLegacy USB Support    (Enabled)\nEnables Legacy USB support.\nAUTO option disables legacy\nsupport if no USB devices are\nconnected. DISABLE option will\nkeep USB devices available\nonly for EFI applications.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.15.1236, Copyright (C) 2012 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/112ee7a14e0ea8c5120d02045319ee9fa3d35a7d8838e940a9abc865efd8247a.jpg)

# Legacy USB Support

Enables legacy USB support. Auto option disables legacy support if no USB devices are connected. Disable option will keep USB devices available only for EFI applications. Set this value to Enabled/Disabled/Auto.

# 8.3.9 Hardware Monitor

This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.</td></tr><tr><td>Advanced</td><td></td></tr><tr><td>Pc Health Status</td><td></td></tr><tr><td>CPU temperature : +50 Degree C System temperature : +33 Degree C 3.3V : +3.210 V 5V : +4.800 V 12V : +11.870 V</td><td></td></tr><tr><td></td><td>+: Select Screen ↑↓: Select Item Enter: Select +/-: Change Opt. F1: General Help F2: Previous Values F3: Optimized Defaults F4: Save &amp; Exit ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# CPU Temperature

Displays current CPU temperature.

# System Temperature

Displays current system temperature.

# 3.3V

Displays current system 3.3V voltage.

# 5V

Displays current system 5V voltage.

# 12V

Displays current system 12V voltage.

# 8.3.10 Super IO Configuration

You can use this screen to select options for the Super IO Configuration settings.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nIT8783F Super IO Configuration\nIT8783F Super IO Chip IT8783F\n► Serial Port 1 Configuration\n► Serial Port 2 Configuration\n► Serial Port 3 Configuration\n► Serial Port 4 Configuration\nUSB to Serial Port COM6 (RS232)\nSet Parameters of Serial Port 1\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.15.1236, Copyright (C) 2012 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/ed3c84c2cade6a75f7c0ae67446d7255b094d368d1547686728ac655dcfe37b3.jpg)

# Serial Port 1,2,3,4 Configuration

Set Parameters of Serial Port 1,2,3,4 (COM 1,2,3,4). COM1/2: faceplate; COM3: IPMI interface; COM4: RTM.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nSerial Port 1 Configuration\nSerial Port (Enabled)\nDevice Settings IO=3F8h; IRQ=4;\nOutput (RS232)\nEnable or Disable Serial Port\n(COM)](.cpci-3510-50-15095-1040-24/7a6c25eb9d999543ca1a9c5e975eb9a0332deeb713efa17271578d5fab7a53ef.jpg)

# Serial Port

Enable/Disable serial port 1,2,3,4 (COM1,2,3,4). Set this value to Enable or Disable.

# Output (cPCI-3510(BL)G COM1/2)

Set the mode of serial port 1,2,(COM1,2). Set this value to RS232 or RS422/RS485.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nSerial Port 1 Configuration\nSerial Port          (Enabled)\nDevice Settings      IO=3F8h; IRQ=4;\nOutput           (RS232)\nOutput\n          RS232\n          RS422/RS485\nControl COM Port Output mode.\nRS232 = COM Port will output\nRS232 mode\nRS422/485 = COM Port will\noutput RS422/485 mode.\n+: Select Screen\n↑↓: Select Item\nEnter: Select\n+/-: Change Opt.](.cpci-3510-50-15095-1040-24/7820c85af1e30383f604669fb0d18c371a4e5176e7dc868fc65146fa3e182e66.jpg)

![The image displays a graphic icon of a white sheet of paper with a folded top-left corner. Several faint horizontal gray lines appear near the bottom of the page, suggesting text. A large, red checkmark is drawn diagonally across the center of the document. There is no text in the image.](.cpci-3510-50-15095-1040-24/5dd41d67930e81e0153ed6d9394e332828f43232e25ae30ce1f4535dcc373b41.jpg)
NOTE:

The cPCI-3510(BL)G COM1/2 Output BIOS setting is only used for cPCI-3510(BL)G models. The COM mode setting for cPCI-3510(BL)D/P models must be set using the “COM1 Mode Selection Switches (SW1\~SW4)” on page 47.

# USB to Serial Port

Set the mode of COM5 on the cPCI-R3P00(T) RTM. Options: RS232 and RS422/RS485 ("COM6" will be corrected to "COM5" in the next BIOS revision).

# 8.3.11 Console Redirection

You can use this screen to select options for the serial port console redirection settings. An example of the Serial Port Console Redirection screen is shown below.

![Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.\nAdvanced\nCOM1\nConsole Redirection (Disabled)\n► Console Redirection Settings\nCOM2\nConsole Redirection (Disabled)\n► Console Redirection Settings\nCOM4\nConsole Redirection (Disabled)\n► Console Redirection Settings\nConsole Redirection Enable or\nDisable.\n+: Select Screen\n↑: Select Item\nEnter: Select\n+/-: Change Opt.\nF1: General Help\nF2: Previous Values\nF3: Optimized Defaults\nF4: Save & Exit\nESC: Exit\nVersion 2.15.1236, Copyright (C) 2012 American Megatrends, Inc.](.cpci-3510-50-15095-1040-24/bee26d09b00a70b4e3b291dae2caef0f8384a50c415de7dc203fa1ce980d5d7f.jpg)

# Console Redirection

Set this value to Enabled/Disabled.

# Console Redirection Settings

The settings specify how the host computer and the remote computer will exchange data. Both computers should have the same or compatible settings. The screen is shown below.

Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.

Advanced

<table><tr><td colspan="2">COM1Console Redirection Settings</td><td rowspan="12">Emulation: ANSI: ExtendedASCII char set. VT100: ASCIIchar set. VT100+: ExtendsVT100 to support color, function keys, etc. VT-UTF8:Uses UTF8 encoding to mapUnicode chars onto 1 or more bytes.</td></tr><tr><td>Terminal Type</td><td>[ANSI]</td></tr><tr><td>Bits per second</td><td>[115200]</td></tr><tr><td>Data Bits</td><td>[8]</td></tr><tr><td>Parity</td><td>[None]</td></tr><tr><td>Stop Bits</td><td>[1]</td></tr><tr><td>Flow Control</td><td>[None]</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>[Enabled]</td></tr><tr><td>Recorder Mode</td><td>[Disabled]</td></tr><tr><td>Resolution 100x31</td><td>[Disabled]</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>[80x24]</td></tr><tr><td>Putty KeyPad</td><td>[VT100]</td></tr><tr><td></td><td></td><td>+: Select Screen↑↓: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF3: Optimized DefaultsF4: Save &amp; ExitESC: Exit</td></tr></table>

Version 2.15.1236. Copyright (C) 2012 American Megatrends, Inc.

# Terminal Type

VT100+ is the preferred terminal type for out-of-band management. Configuration options: VT100, VT100+, VT-UTF8, ANSI.

# Bits per second

Select the bits per second you want the serial port to use for console redirection. The options are 115200, 57600, 38400, 19200, 9600.

# Data Bits

Select the data bits you want the serial port to use for console redirection. Set this value to 7, 8.

# Parity

Set this option to select Parity for console redirection. The settings for this value are None, Even, Odd, Mark, Space.

# Stop Bits

Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit. Set this value to 1 and 2.

# Flow Control

Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware RTS/CTS.

# VT-UTF8 Combo Key Support

Enables VT-UTF8 combination key support for ANSI/VT100 terminals. Set this value to Enabled/Disabled.

# Recorder Mode

When this mode is enabled, only text will be sent. This is to capture terminal data. Set this value to Enabled/Disabled.

# Resolution 100x31

Set this option to extended terminal resolution. Set this value to Enabled/Disabled.

# Legacy OS Redirection

On legacy OS, the number of rows and columns supported for redirection. Set this value to 80x24, 80x25.

# Putty Key Pad

Select FunctionKey and KeyPad on Putty. Set this value to VT100, LINUX, XTERMR6, SCO, ESCN, VT400.

# 8.4 Chipset Setup

Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of Chipset BIOS Setup options by highlighting it using the &lt;Arrow&gt; keys. The Chipset BIOS Setup screen is shown below.

<table><tr><td colspan="2">Main Advanced Chipset Boot Security Save &amp; Exit</td></tr><tr><td>&gt; PCH-IO Configuration
&gt; System Agent (SA) Configuration</td><td>PCH Parameters</td></tr><tr><td></td><td>×: Select Screen
^y: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# 8.4.1 PCH-IO Configuration

<table><tr><td colspan="3">Chipset Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.</td></tr><tr><td>Intel PCH RC Version</td><td>1.2.0.1</td><td>Enable or disable onboard NIC.</td></tr><tr><td>Intel PCH SKU Name</td><td>QM77</td><td></td></tr><tr><td>Intel PCH Rev ID</td><td>04/C1</td><td></td></tr><tr><td>PCH LAN Controller</td><td>[Enabled]</td><td></td></tr><tr><td>HD Audio</td><td>[Enabled]</td><td></td></tr><tr><td>&gt; PCI Express Configuration</td><td></td><td></td></tr><tr><td>&gt; USB Configuration</td><td></td><td></td></tr><tr><td></td><td></td><td>&lt;: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="3">Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# PCH LAN Controller

Enable or disable onchip NIC. Set this value to Enabled/Disabled

# HD Audio

Enable or disable the onboard HDA controller. Set this value to Enabled/Disabled.

# PCI Express Configuration

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc. Chipset</td></tr><tr><td rowspan="27">PCI Express ConfigurationPCI Express Clock Gating [Enabled]DMI Link ASPM Control [Enabled]Subtractive Decode [Disabled]PCIE Port 1 is assigned to LAN&gt; PCI Express Root Port 2 (LAN1)&gt; PCI Express Root Port 3 (LAN3)&gt; PCI Express Root Port 4 (LAN4)&gt; PCI Express Root Port 5 (BRIDGE)</td><td>Enable or disable PCI ExpressClock Gating for each root port.</td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td></td></tr><tr><td>&lt;&lt;: Select Screen^v: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF3: Optimized DefaultsF4: Save &amp; ExitESC: Exit</td></tr><tr><td colspan="2">Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# PCI Express Clock Gating

Enable or disable XHCI Pre-Boot Driver support. Set this value to Enabled/Disabled.

# DMI Link ASPM Control

Mode of operation of xHCI controller. Set this value to Enabled/Disabled.

# Subtractive Decode

Mode of operation of xHCI controller. Set this value to Enabled/Disabled.

# PCI Express Root Port 2\~5

Control the PCI Express Root Ports 2\~5

# USB Configuration

<table><tr><td colspan="3">Chipset</td></tr><tr><td colspan="2">USB Configuration</td><td>Enable or disable XHCI
Pre-Boot Driver support.</td></tr><tr><td>XHCI Pre-Boot Driver</td><td>[Enabled]</td><td></td></tr><tr><td>xHCI Mode</td><td>[Smart Auto]</td><td></td></tr><tr><td>HS Port #1 Switchable</td><td>[Enabled]</td><td></td></tr><tr><td>HS Port #2 Switchable</td><td>[Enabled]</td><td></td></tr><tr><td>HS Port #3 Switchable</td><td>[Enabled]</td><td></td></tr><tr><td>HS Port #4 Switchable</td><td>[Enabled]</td><td></td></tr><tr><td>xHCI Streams</td><td>[Enabled]</td><td></td></tr><tr><td>EHCI1</td><td>[Enabled]</td><td></td></tr><tr><td>EHCI2</td><td>[Enabled]</td><td></td></tr><tr><td>USB Ports Per-Port Disable Control</td><td>[Disabled]</td><td>&lt;&lt;: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr></table>

# XHCI Pre-Boot Driver

Enable or disable XHCI Pre-Boot Driver support. Set this value to Enabled/Disabled.

# XHCI Mode

Mode of operation of xHCI controller. Set this value to Enabled/Disabled.

# HS Port #1/2/3/4 Switchable

Allows for HS port switching between xHCI and EHCI. If disabled, port is routed to EHCI. If HS port is routed to xHCI, the corresponding SS port is enabled. Set this value to Enabled/Disabled.

# xHCI Stream

Enable or disable xHCI Maximum Primary Stream Array Size. Set this value to Enabled/Disabled.

# EHCI1/2

Control the USB EHCI (USB 2.0) functions. One EHCI controller must always be enabled. Set this value to Enabled/Disabled.

# USB Ports Per-Port Disable Control

Control the per-port disabling of USB ports 0\~13. Set this value to Enabled/Disabled.

# 8.4.2 System Agent (SA) Configuration

<table><tr><td colspan="3">Chipset Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.</td></tr><tr><td>System Agent Bridge Name</td><td>IvyBridge</td><td rowspan="6">Check to enable VT-d function on MCH.</td></tr><tr><td>System Agent RC Version</td><td>1.2.0.0</td></tr><tr><td>VT-d Capability</td><td>Supported</td></tr><tr><td>VT-d</td><td>[Enabled]</td></tr><tr><td>&gt; Graphics Configuration</td><td></td></tr><tr><td>&gt; Memory Configuration</td><td></td></tr><tr><td></td><td></td><td>&lt;: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="3">Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# VT-d

The Intel Virtualization Technology for Directed I/O. Set this value to Enabled/Disabled.

# Graphics Configuration

<table><tr><td colspan="3">Chipset</td></tr><tr><td>Graphics ConfigurationIGFX VBIOS VersionIGfx Frequency</td><td>2132350 MHz</td><td rowspan="2">Select which of IGFX/PEG/PCI Graphics device should be Primary Display Or select SG for Switchable Gfx.</td></tr><tr><td>Primary DisplayInternal GraphicsGTT SizeAperture SizeDVMT Pre-AllocatedDVMT Total Gfx Mem</td><td>[Auto][Auto][2MB][256MB][64M][256M]</td></tr><tr><td></td><td></td><td>&lt;: Select Screen^v: Select ItemEnter: Select+/-: Change Opt.F1: General HelpF2: Previous ValuesF3: Optimized DefaultsF4: Save &amp; ExitESC: Exit</td></tr></table>

# Primary Display

Select which graphics device should be the primary display. Set this value to Auto, IGFX, PCI.

# Internal Graphics

Keep IGD enabled based on the setup options. Set this value to Auto, Enabled, Disabled.

# GTT Size

Select the GTT size. Set this value to 1MB, 2MB.

# Aperture Size

Select the aperture size. Set this value to 128MB, 256MB, 512MB.

# DVMT Pre-Allocated

Select DVMT 5.0 Pre-Allocated (fixed) graphics memory size used by the internal graphics device. Configuration options as below:

![/---- DVMT Pre-Allocated ----/\n| 0M                  ^ |\n| 32M                 * |\n| 64M                 *\n| 96M                 *\n| 128M                *\n| 160M                *\n| 192M                *\n| 224M                *\n| 256M                +\n| 288M                +\n| 320M                +\n| 352M                v\n----/](.cpci-3510-50-15095-1040-24/c5a4853aaf93b15feb4c69990f9e21e6ac7ebaf75a19f88c890a92baa83bc5a7.jpg)

# DVMT Total Gfx Memory

Select DVMT 5.0 total graphic memory size used by the internal graphics device. Configuration options as below:

![----- DVMT Total GFX Mem ---\\n| 128M\n| 256M\n| MAX\n- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -](.cpci-3510-50-15095-1040-24/8de97400ac337bee355b05b5c3e45ce7ad75e4a4c60ce15a409ab16d39f6126b.jpg)

# Memory Configuration

<table><tr><td colspan="3">Chipset Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.</td></tr><tr><td>Memory Information</td><td></td><td rowspan="11">Enable or disable memory remap above 4G.</td></tr><tr><td>Memory RC Version</td><td>1.2.0.0</td></tr><tr><td>Memory Frequency</td><td>1333 Mhz</td></tr><tr><td>Total Memory</td><td>4096 MB (DDR3)</td></tr><tr><td>DIMM#0</td><td>4096 MB (DDR3)</td></tr><tr><td>DIMM#2</td><td>Not Present</td></tr><tr><td>CAS Latency (tCL)</td><td>9</td></tr><tr><td>Minimum delay time</td><td></td></tr><tr><td>CAS to RAS (tRCDmin)</td><td>9</td></tr><tr><td>Row Precharge (tRPmin)</td><td>9</td></tr><tr><td>Active to Precharge (tRASmin)</td><td>24</td></tr><tr><td>ECC Support</td><td>[Enabled]</td><td rowspan="2">×: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Memory Remap</td><td>[Enabled]</td></tr></table>

# Memory Remap

Enable or disable memory remap above 4G. Set this value to Enabled/Disabled.

# 8.5 Boot Settings

Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Boot Settings screen is shown below:

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.</td></tr><tr><td colspan="2">Main Advanced Chipset Boot Security Save &amp; Exit</td></tr><tr><td>Boot Configuration
Bootup NumLock State [On]</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot [Enabled]
Fast Boot [Disabled]</td><td></td></tr><tr><td>Driver Option Priorities</td><td></td></tr><tr><td>Boot Option Priorities</td><td></td></tr><tr><td>&gt;CSM parameter</td><td></td></tr><tr><td></td><td>×: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.15.1226. Copyright (C) 2012 American Megatrends, Inc.</td></tr></table>

# Quiet Boot

▶ Disabled - Set this value to allow the computer system to display the POST messages.
▶ Enabled - Set this value to allow the computer system to display the OEM logo.

# Fast Boot

Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options. Set this value to Enabled/Disabled.

# Set Boot Priority

Set Boot Option #1 \~2 boot priority.

# Hard Disk Drive BBS Priorities

Specifies the boot device priority sequence from available hard drives.

# 8.5.1 CSM Parameter

OpROM execution, boot option filter, etc.

<table><tr><td colspan="3">Aptio Setup Utility - Copyright (C) 2012 American Megatrends, Inc.</td></tr><tr><td>Boot</td><td></td><td></td></tr><tr><td>Launch CSM</td><td>[Always]</td><td rowspan="6">This option controls if CSM will be launched</td></tr><tr><td>Boot option filter</td><td>[UEFI and Legacy]</td></tr><tr><td>Launch PXE OpROM policy</td><td>[Do not launch]</td></tr><tr><td>Launch Storage OpROM policy</td><td>[Legacy only]</td></tr><tr><td>Launch Video OpROM policy</td><td>[Legacy only]</td></tr><tr><td>Other PCI device ROM priority</td><td>[Legacy OpROM]</td></tr></table>

# Launch CSM

This option controls if CSM will be launched. Set this value to Always, Never.

# Boot option filter

This option controls what devices system can boot to. Set this value to UEFI and Legacy, Legacy only, UEFI only.

# Launch PXE OpROM policy

This option controls the execution of UEFI and Legacy PXE OpROM. Set this value to Do not launch, Legacy only.

# Launch Storage OpROM policy

This option controls the execution of UEFI and Legacy Storage OpROM. Set this value to Do not launch, UEFI only, Legacy only.

# Launch Video OpROM policy

This option controls the execution of UEFI and Legacy Video OpROM. Set this value to Do not launch, UEFI only, Legacy only.

# Other PCI device ROM priority

For PCI devices other than Network, Mass storage or Video defines which OpROM to launch. Set this value to UEFI OpROM, Legacy OpROM.

# 8.6 Security Setup

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.</td></tr><tr><td>Main Advanced Chipset Boot Security Save &amp; Exit</td><td></td></tr><tr><td>Password Description</td><td>Set Administrator Password</td></tr><tr><td>If ONLY the Administrator&#x27;s password is set, then this only limits access to Setup and is only asked for when entering Setup.</td><td></td></tr><tr><td>If ONLY the User&#x27;s password is set, then this is a power on password and must be entered to boot or enter Setup. In Setup the User will have Administrator rights.</td><td></td></tr><tr><td>The password length must be in the following range:</td><td></td></tr><tr><td>Minimum length 3</td><td></td></tr><tr><td>Maximum length 20</td><td></td></tr><tr><td>Administrator Password User Password</td><td>×: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td colspan="2">Version 2.14.1219 Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# Administrator, User Password

If only the administrator's password is set, then this only limits access to setup and is only asked for when entering setup.

If only the user's password is set, then this is a power on password and must be entered to boot or enter setup. In setup the user will have administrator rights.

# 8.7 Save & Exit Menu

Select the Save & Exit tab from the setup screen to enter the Save & Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Save & Exit BIOS Setup screen is shown below.

<table><tr><td colspan="2">Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.</td></tr><tr><td>Main Advanced Chipset Boot Security Save &amp; Exit</td><td></td></tr><tr><td>Save Changes and Reset</td><td rowspan="2">Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td></tr><tr><td>Save Options</td><td></td></tr><tr><td>Save Changes</td><td></td></tr><tr><td>Discard Changes</td><td></td></tr><tr><td>Restore Defaults</td><td></td></tr><tr><td>Save as User Defaults</td><td></td></tr><tr><td>Restore User Defaults</td><td></td></tr><tr><td>Boot Override</td><td></td></tr><tr><td>SanDisk</td><td></td></tr><tr><td>UEFI: SanDisk</td><td rowspan="2">+: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save &amp; Exit
ESC: Exit</td></tr><tr><td>Launch EFI Shell from filesystem device</td></tr><tr><td colspan="2">Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.</td></tr></table>

# Save Changes and Reset

Reset the system after saving the changes.

![Save & reset\nSave configuration and reset?\nYes	No](.cpci-3510-50-15095-1040-24/11c0b43ba842be5a81b626ef7908a1f96365f3befaaaa95104ad53a01cf380af.jpg)

# Discard Changes and Reset

Reset system setup without saving any changes.

![- Reset Without Saving\nReset without saving?\n----\nYes No](.cpci-3510-50-15095-1040-24/9e9e211fe4ef57ec557237b424566b6bcdf3ddd3452800b65954f1ec5e39f17a.jpg)

# Save Changes

Save changes done so far to any of the setup options.

![- Save Setup Values -\nSave configuration?\n-\nYes No](.cpci-3510-50-15095-1040-24/67a231705ac6190e2671e4d0e94386062f89120f189ff1e45c2dad9dbdc9c3b7.jpg)

# Discard Changes

Discard changes done so far to any of the setup options.

![- Load Previous Values\nLoad Previous Values?\n-\nYes No](.cpci-3510-50-15095-1040-24/9d870f4668b809d12e151863d6a36ec836ac26abfcdbf1f1be27725f798f449d.jpg)

# Restore Changes

Restore/Load Defaults values for all the setup options.

![Load Optimized Defaults -\nLoad Optimized Defaults?\nYes No](.cpci-3510-50-15095-1040-24/32d46b2a4f75fcb2343f08fe3e854b6798f3fed986a6877a830854d1c987bfb7.jpg)

# Save as User Defaults

Save the changes done so far as user defaults..

![Save Values as User Defaults\nSave configuration?\nYes	No](.cpci-3510-50-15095-1040-24/ab10c7473e7fe60c1f63d67a1fd89ba873aa2eea2b7cfb9cf678ec59e25b74b5.jpg)

# Restore User Defaults

Save changes done so far to any of the setup options.

![Restore User Defaults -\nRestore User Defaults?\n----\nYes No](.cpci-3510-50-15095-1040-24/b8a2e34c30082a6dfdc0f5494270c8aef73fb618edf508a63fd9f72db4140f9f.jpg)

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# 9 IPMI User Guide

# 9.1 Introduction

This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 1.5. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.

# 9.2 Summary of Commands Supported by BMR-AVR-cPCI

The table below lists all the commands supported by the BMR-AVR-cPCI. The rightmost column indicates if the command is required by PICMG 3.0/ PICMG 2.9, or is optional.

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>IPM Controller Req (PICMG 2.9)</td></tr><tr><td colspan="5">IPM Device “Global” Commands</td></tr><tr><td>Get Device ID</td><td>17.1</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td>Cold Reset</td><td>17.2</td><td>App</td><td>02h</td><td>Optional</td></tr><tr><td>Warm Reset</td><td>17.3</td><td>App</td><td>03h</td><td>Optional</td></tr><tr><td>Get Self Test Results</td><td>17.4</td><td>App</td><td>04h</td><td>Mandatory</td></tr><tr><td>Get Device GUID</td><td>17.8</td><td>App</td><td>08h</td><td>Optional</td></tr><tr><td>Broadcast “Get Device ID”</td><td>17.9</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td colspan="5">IPMI Messaging Support Commands</td></tr><tr><td>Send Message</td><td>18.7</td><td>App</td><td>34h</td><td>Optional</td></tr><tr><td colspan="5">BMC Watchdog Timer</td></tr><tr><td>Reset Watchdog Timer</td><td>21.5</td><td>App</td><td>22h</td><td>Optional</td></tr><tr><td>Set Watchdog Timer</td><td>21.6</td><td>App</td><td>24h</td><td>Optional</td></tr><tr><td>Get Watchdog Timer</td><td>21.7</td><td>App</td><td>25h</td><td>Optional</td></tr><tr><td colspan="5">Event Commands</td></tr><tr><td>Set Event Receiver</td><td>23.1</td><td>S/E</td><td>00h</td><td>Optional</td></tr><tr><td>Get Event Receiver</td><td>23.2</td><td>S/E</td><td>01h</td><td>Optional</td></tr><tr><td>Platform Event (a.k.a. “Event Message”)</td><td>23.3</td><td>S/E</td><td>02h</td><td>Optional</td></tr><tr><td colspan="5">Sensor Device Commands</td></tr><tr><td>Get Device SDR Info</td><td>29.2</td><td>S/E</td><td>20h</td><td>Optional</td></tr><tr><td>Get Device SDR</td><td>29.3</td><td>S/E</td><td>21h</td><td>Optional</td></tr><tr><td>Reserve Device SDR Repository</td><td>29.4</td><td>S/E</td><td>22h</td><td>Optional</td></tr><tr><td>Set Sensor Hysteresis</td><td>29.6</td><td>S/E</td><td>24h</td><td>Optional</td></tr><tr><td>Get Sensor Hysteresis</td><td>29.7</td><td>S/E</td><td>25h</td><td>Optional</td></tr><tr><td>Set Sensor Threshold</td><td>29.8</td><td>S/E</td><td>26h</td><td>Optional</td></tr><tr><td>Get Sensor Threshold</td><td>29.9</td><td>S/E</td><td>27h</td><td>Optional</td></tr><tr><td>Set Sensor Event Enable</td><td>29.10</td><td>S/E</td><td>28h</td><td>Optional</td></tr><tr><td>Get Sensor Event Enable</td><td>29.11</td><td>S/E</td><td>29h</td><td>Optional</td></tr><tr><td>Get Sensor Event Status</td><td>29.13</td><td>S/E</td><td>2Bh</td><td>Optional</td></tr><tr><td>Get Sensor Reading</td><td>29.14</td><td>S/E</td><td>2Dh</td><td>Optional</td></tr><tr><td>Get Sensor Type</td><td>29.16</td><td>S/E</td><td>2Fh</td><td>Optional</td></tr><tr><td colspan="5">FRU Device Commands</td></tr><tr><td>Get FRU Inventory Area Info</td><td>28.1</td><td>Storage</td><td>10h</td><td>Optional</td></tr><tr><td>Read FRU Data</td><td>28.2</td><td>Storage</td><td>11h</td><td>Optional</td></tr><tr><td>Write FRU Data</td><td>28.3</td><td>Storage</td><td>12h</td><td>Optional</td></tr></table>

# 9.3 OEM Commands Summary Table

<table><tr><td>Command</td><td>NetFn Code</td><td>Cmd Code</td></tr><tr><td>OemShowRevision</td><td>OEM (C0h)</td><td>12h</td></tr><tr><td>OemRescanGaInput</td><td>OEM (C0h)</td><td>22h</td></tr><tr><td>OemTestFunction</td><td>OEM (C0h)</td><td>30h</td></tr><tr><td>OemReportGeoAddress</td><td>OEM (C0h)</td><td>F0h</td></tr><tr><td>OemEnableSmbus</td><td>OEM (C0h)</td><td>F2h</td></tr><tr><td>OemDisableSmbus</td><td>OEM (C0h)</td><td>F3h</td></tr><tr><td>OemDispDebugVariable</td><td>OEM (C0h)</td><td>F4h</td></tr><tr><td>OemResetHost</td><td>OEM (C0h)</td><td>F5h</td></tr><tr><td>OemPowerOff</td><td>OEM (C0h)</td><td>F6h</td></tr><tr><td>OemPowerOn</td><td>OEM (C0h)</td><td>F7h</td></tr></table>

# OemShowRevision

This command is used to show the current information of the firmware including the firmware revision, the product ID, and additional features.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>12h</td><td>OEM defined command</td></tr><tr><td rowspan="11">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>A5h</td><td>Internal check byte. Always A5h</td></tr><tr><td>2</td><td>Firmware Rev</td><td>‘V’ in ASCII code for verification</td></tr><tr><td>3</td><td>Firmware Rev</td><td>Revision info high byte</td></tr><tr><td>4</td><td>Firmware Rev</td><td>Revision info low byte</td></tr><tr><td>5</td><td>Product ID</td><td>‘P’ in ASCII code for verification</td></tr><tr><td>6</td><td>Product ID</td><td>Product info high byte</td></tr><tr><td>7</td><td>Product ID</td><td>Product info low byte</td></tr><tr><td>8</td><td>Special info</td><td>‘S’ in ASCII code for verification</td></tr><tr><td>9</td><td>Special info</td><td>Addition info byte</td></tr><tr><td>10</td><td>5Ah</td><td>Internal check byte. Always 5Ah</td></tr></table>

# OemRescanGaInput

This command is used to rescan the geo-address input pins and reset the IPMB address according to the input value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>22h</td><td>OEM defined command</td></tr><tr><td rowspan="2">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>New IPMB address</td><td>New IPMB address value</td></tr></table>

# OemTestFunction

Internal test purposes only.

# OemReportGeoAddress

This command can report the IPMB address, the GA pin input status, and the event forwarding control value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F0h</td><td>OEM defined command</td></tr><tr><td rowspan="4">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>IPMB address</td><td>IPMB address value</td></tr><tr><td>2</td><td>GA value</td><td>GA pin input status</td></tr><tr><td>3</td><td>Control value</td><td>Current control value of event forwarding</td></tr></table>

# OemEnableSmbus

This command is used to turn on the I2C bus when it is off during boot up process. Usually BIOS will perform this command after booting in boards with ServerWorks chipset.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F2h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDisableSmbus

This command is used to shut down I2C bus access.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F3h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDispDebugVariable

This command can report up to 5 interval values for debug purposes. For developers only.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F4h</td><td>OEM defined command</td></tr><tr><td rowspan="6">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>*Debug variable 1</td><td></td></tr><tr><td>2</td><td>*Debug variable 2</td><td></td></tr><tr><td>3</td><td>*Debug variable 3</td><td></td></tr><tr><td>4</td><td>*Debug variable 4</td><td></td></tr><tr><td>5</td><td>*Debug variable 5</td><td></td></tr></table>

![The image displays an icon of a white document page with a folded top-right corner and faint horizontal lines resembling text. A large, bold red checkmark is superimposed over the center of the document.](.cpci-3510-50-15095-1040-24/423767c5ddedd613a1ae7a16646a1495f9fdd12acd1bf871b2c77c6a61c2422a.jpg)
NOTE:

\*Reserved for customized IPMI debugging purposes. Contact your ADLINK representative for details.

# OemResetHost

This command is implemented to control the system's status if rebooting is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F5h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOff

This command is implemented to control the system's status if power-off is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F6h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOn

This command is implemented to control the system's status if power-on is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F7h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# 9.4 CompactPCI Address Map

Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.

<table><tr><td colspan="4">CompactPCI Peripheral Address Mapping</td></tr><tr><td>Geo. Addr.</td><td>IPMB Addr.</td><td>Geo. Addr.</td><td>IPMB Addr.</td></tr><tr><td>0</td><td>Disabled</td><td>16</td><td>D0h</td></tr><tr><td>1</td><td>B0h</td><td>17</td><td>D2h</td></tr><tr><td>2</td><td>B2h</td><td>18</td><td>D4h</td></tr><tr><td>3</td><td>B4h</td><td>19</td><td>D6h</td></tr><tr><td>4</td><td>B6h</td><td>20</td><td>D8h</td></tr><tr><td>5</td><td>B8h</td><td>21</td><td>DAh</td></tr><tr><td>6</td><td>Bah</td><td>22</td><td>DCh</td></tr><tr><td>7</td><td>BCh</td><td>23</td><td>DEh</td></tr><tr><td>8</td><td>BEh</td><td>24</td><td>E0h</td></tr><tr><td>9</td><td>Coh</td><td>25</td><td>E2h</td></tr><tr><td>10</td><td>C4h</td><td>26</td><td>E4h</td></tr><tr><td>11</td><td>C6h</td><td>27</td><td>E6h</td></tr><tr><td>12</td><td>C8h</td><td>28</td><td>E8h</td></tr><tr><td>13</td><td>CAh</td><td>29</td><td>EAh</td></tr><tr><td>14</td><td>CCh</td><td>30</td><td>ECh</td></tr><tr><td>15</td><td>CEh</td><td>31</td><td>Disabled</td></tr></table>

# 9.5 Communications with IPMC

Operating systems need to use a serial port to communicate with the IPMC. The resource setting of the serial port must be IO:0x2E0 and IRQ:7. The communication setting of the serial port must be BaudRate: 9600, DataBit: 8, ParityCheck: None, StopBit: 1, and FlowControl: None. In Windows XP, use "COM3" to communicate with the IPMC.

# 9.6 IPMI Sensors List

<table><tr><td>Sensor Number</td><td>Sensor name</td><td>Normal Reading</td><td>Remark</td></tr><tr><td>00h</td><td>BMC Watchdog</td><td></td><td></td></tr><tr><td>01h</td><td>3.3V</td><td>3.3 V</td><td></td></tr><tr><td>02h</td><td>5V</td><td>5 V</td><td></td></tr><tr><td>03h</td><td>12V</td><td>12 V</td><td></td></tr><tr><td>04h</td><td>CPU Temp</td><td>40°C</td><td></td></tr><tr><td>05h</td><td>System Temp</td><td>25°C</td><td></td></tr><tr><td>06h</td><td>P_CPU_VCORE</td><td>1.8 V</td><td></td></tr><tr><td>07h</td><td>P_CPU_VTT</td><td>1.5 V</td><td></td></tr><tr><td>08h</td><td>P_CPU_VSA</td><td>1.5 V</td><td></td></tr><tr><td>09h</td><td>P_CPU_VDD</td><td>1.5 V</td><td></td></tr><tr><td>0ah</td><td>P1V8_BG</td><td>1.8 V</td><td></td></tr><tr><td>0bh</td><td>P1V5_SSB</td><td>1.5 V</td><td></td></tr><tr><td>0ch</td><td>P1V1_SSB</td><td>1.1 V</td><td></td></tr></table>

# 9.7 Relevant Documents

<table><tr><td>Document Title</td><td>Revision</td><td>Source</td></tr><tr><td>Intelligent Platform Management Interface Specification v1.5</td><td>Document Revision 1.1 February 20, 2002</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr><tr><td>PICMG 2.9 D1.0 CompactPCI System Management Specification</td><td>January 21, 2000</td><td></td></tr><tr><td>Intelligent Platform Management Bus Communications Protocol Specification v0.9</td><td>Document Revision 0.15 June 24, 1997</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a vertical, maroon-red triangle containing a white exclamation point in its center. Below the triangle, the word 'WARNING:' is printed in black, capital letters.](.cpci-3510-50-15095-1040-24/de8813a17e8a65bc0b2ef2b34fc0ee2968f331d67e5144dde52d5a9f4b50ae90.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

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Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

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Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

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Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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