# cPCI-3520 Series

Performance 3U CompactPCI® Processor Blade Intel® Xeon® E, 8th/9th Gen Intel® Core™

User’s Manual

![Electronic circuit board with various components and connectors, no visible text or symbols](.cpci-3520-50m-00036-1000-10-07102024/ba6e9aebec7d3b07792ac031ebfe5be467d9b4af4b71bdde542e39bcc4eb02cc.jpg)

Manual Rev.: 1.0

Revision Date: May 5, 2022

Part No: 50M-00036-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2022-05-05</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2022 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines, no text or labels present](.cpci-3520-50m-00036-1000-10-07102024/16ce769f4135caf2243284c4e3a7dd3f764460722222b178c6df20466b72fa00.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.cpci-3520-50m-00036-1000-10-07102024/f89683edc1c23ac7e7e12bc5d96d4bd6ac86d7b87deb58900a343d80c5385cc1.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.cpci-3520-50m-00036-1000-10-07102024/cf462518f31625ba8c6cfae8a5306a584e40698d9008148457d2796eb620cfb0.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cpci-3520-50m-00036-1000-10-07102024/9b7516d08ff113b52dcf505eed8bf5cc57a0a324820a5676a1ac1e746eac67e2.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.cpci-3520-50m-00036-1000-10-07102024/dd42c25fca973c62f322afa5742fdd42d1bb05f428d71f7e3b7b58774d51fc8a.jpg)

ᑜ㔚ᳰ⺧࿁ᡴ

# California Proposition 65 Warning

![The image displays a standard triangular warning sign featuring a bright yellow interior enclosed by a thick black border. Centered inside the triangle is a black exclamation point. The background surrounding the sign is white.](.cpci-3520-50m-00036-1000-10-07102024/62564484ad4884c9d99a2ab510c0f87fca11b6f087c652ae0981610600819acf.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white sheet of paper with faint horizontal lines running across it, resembling a document or list. A large, bold red checkmark is drawn diagonally across the center of the page, extending from the bottom left to the top right. The top right corner of the paper is folded down.](.cpci-3520-50m-00036-1000-10-07102024/7b19cbdc1f9b26b17550c861323f432f4860bb2aa0e3982634512e7fdddd3370.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a thick black border. Centered inside the triangle is a large black exclamation point. A thick black horizontal line runs across the bottom edge of the image.](.cpci-3520-50m-00036-1000-10-07102024/f1abe52f55dad78a33514952e3158f0d2b7367d2fd22c3274faf62dafb022efc.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a red triangle pointing upward containing a white exclamation mark in its center. Above the triangle is a horizontal black line, and the background is white.](.cpci-3520-50m-00036-1000-10-07102024/403d1f98b4f8728a5f7a1f670a4842f2fb1f5352c8d870fcb759d0dd5f1581d0.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History....... ii

# Preface ......... iii

# List of Figures ...... ix

# List of Tables ........ ... xi

# 1 Introduction .... 1

1.1 Overview ...... 1
1.2 Features...... 2
1.3 Model Number Decoder... 3
1.4 Package Contents .. 5

# 2 Specifications ........ 7

2.1 cPCI-3520 Processor Blade Specifications ..... 7
2.2 cPCI-R3P00(T) RTM Specifications ..... 11
2.3 Block Diagrams.. . 12
2.4 I/O Connectivity Table . 19
2.5 Power Requirements .. 22

# 3 Functional Description ....... 2 5

3.1 Processors.. 25
3.2 Chipset... 27
3.3 PMC/XMC.... 27
3.4 Intel® Turbo Boost Technology . 27
3.5 Intel® Hyper-Threading Technology...... 28
3.6 Trusted Platform Module . 28
3.7 Battery ..... 29
3.8 Watchdog Timer ..... 29

# 4 Board Interfaces......... 31

4.1 cPCI-3520 Series Board Layout . . 31
4.2 cPCI-3520 Blade Assembly Layout ... 33
4.3 cPCI-3520D Blade Assembly Layout... 34
4.4 cPCI-3520G Blade Assembly Layout... 35
4.5 cPCI-3520L Blade Assembly Layout ... 36
4.6 cPCI-3520M Blade Assembly Layout ... 37
4.7 cPCI-3520S Blade Assembly Layout.... . 38
4.8 cPCI-3520 Series Faceplate Layout ... 39
4.9 cPCI-R3P00(T) RTM Board Layout ... 42
4.10 cPCI-R3P00(T) RTM Faceplate.. 4 3
4.11 Connector Pin Assignments... 4 4
4.12 Jumper Settings ...... . 70

# 5 Getting Started ....... .. 71

5.1 CPU and Heatsink ... . 71
5.2 SATA Drive Installation.. 72
5.3 Installing a CFast Card . 75
5.4 Installing the cPCI-3520 to the Chassis.. 76
5.5 RTM Installation - cPCI-R3P00(T) ...... 77

# 6 Driver Installation....... 79

6.1 cPCI-3520 Drivers..... . 79
6.2 USB-to-Serial Converter Driver (RTM) ... . 80

# 7 BIOS Setup Utility .......... .... 83

7.1 Starting the BIOS .... . 83
7.2 Main Setup....... 85
7.2.1 BIOS Information .. 86
7.2.2 System Information... .. 86
7.2.3 System Date and Time .. .. 86

7.3 Advanced.... . 87

7.3.1 CPU Configuration. .... 87

7.3.2 Power Management.. . 88

7.3.3 USB Configuration ..... .. 89
7.3.4 AMT Configuration..... .. 89
7.3.5 CMS Configuration .... . 90
7.3.6 Super IO Configuration.. .. 90
7.3.7 Serial Console Redirection .... . 93
7.3.8 Miscellaneous.. .. 95
7.3.9 Network Stack Configuration .... .. 96
7.3.10Intel I210 Gigabit Network Connection / Ethernet Connection (7) I219-LM [MAC Address] .... 96

7.4 Chipset.. 98

7.4.1 System Agent (SA) Configuration.. . 98
7.4.2 PCH-IO Configuration.. .. 102

7.5 Security ...... . 107

7.5.1 Password Description.. .. 107

7.6 Boot ... . 108
7.7 Save & Exit ... . 109
7.8 Server Mgmt . 110

# 8 IPMI User Guide........ 111

8.1 Introduction ..... . 111
8.2 Summary of Commands Supported by BMR-AVR-cPCI . 111
8.3 CompactPCI Address Map ...... . 117
8.4 Communications with IPMC... . 117
8.5 IPMI Sensors List.. 118
8.6 Relevant Documents 118

# Important Safety Instructions ....... . 119

# Getting Service........ . 121

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# List of Figures

Figure 2-1: cPCI-3520 Processor Blade Functional Block Diagram 12

Figure 2-2: cPCI-3520D Daughter Board Functional Block Diagram13

Figure 2-3: cPCI-3520G Daughter Board Functional Block Diagram14

Figure 2-4: cPCI-3520L Daughter Board Functional Block Diagram15

Figure 2-5: cPCI-3520M Daughter Board Functional Block Diagram16

Figure 2-6: cPCI-R3P00 RTM Functional Block Diagram ................ 17

Figure 2-7: cPCI-R3P00T RTM Functional Block Diagram.............. 18

Figure 4-1: cPCI-3520 Series Board Layout (component side) ....... 31

Figure 4-2: cPCI-3520 Series Board Layout (solder side) ............... 32

Figure 4-3: cPCI-3520 Blade Assembly Layout .. . 33

Figure 4-4: cPCI-3520D Blade Assembly Layout.. .. 34

Figure 4-5: cPCI-3520G Blade Assembly Layout .. .. 35

Figure 4-6: cPCI-3520L Blade Assembly Layout .. .. 36

Figure 4-7: cPCI-3520M Blade Assembly Layout . .. 37

Figure 4-8: cPCI-3520/D/G Faceplate Layout.. . 39

Figure 4-9: cPCI-3520L/M/S Faceplate Layout.. .. 40

Figure 4-10: cPCI-R3P00(T) RTM Board Layout... .. 42

Figure 4-11: cPCI-R3P00(T) RTM Faceplate.. .. 43

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# List of Tables

Table 2-1: cPCI-3520 Processor Blade Specifications . . 7

Table 2-2: cPCI-R3P00(T) RTM Specifications . 11

Table 2-3: cPCI-3520 I/O Connectivity . . 19

Table 2-4: R3P00(T) RTM I/O Connectivity. . 21

Table 4-1: cPCI-3520 Faceplate System LED Descriptions ........... 41

Table 4-2: USB 2.0 Pin Definition . .. 44

Table 4-3: VGA Pin Definition ... ... 45

Table 4-4: DisplayPort Pin Definition .. .. 45

Table 4-5: DVI-I Connector Pin Definition.. .. 46

Table 4-6: RJ-45 GbE Pin Definitions.. .. 47

Table 4-7: LAN LED Status Definitions.. ... 47

Table 4-8: PS/2 Keyboard/Mouse Pin Definition.... .. 48

Table 4-9: cPCI-3520D/P COM1 (DB-9) Pin Definition.. .. 48

Table 4-10: cPCI-3520D/P COM1 Mode Selection Switch Settings. 49

Table 4-11: cPCI-3520G COM1 (RJ-45) Pin Definition ..... .. 50

Table 4-12: cPCI-3520G COM1 (DB-9 adapter) Pin Definition......... 50

Table 4-13: RS-422/485 Adapter Dongle Pin Definition ............ ... 51

Table 4-14: cPCI-3520G COM1 with RS-422/485 Dongle Pin Def’n 51

Table 4-15: cPCI-3520G COM2 Pin Header Definition...... .. 52

Table 4-16: cPCI-R3P00(T) RTM COM4 Pin Definition..... .. 52

Table 4-17: cPCI-R3P00(T) RTM COM5 Pin Definition...... .. 53

Table 4-18: cPCI-R3P00(T) RTM COM5 with Dongle Pin Def’n....... 53

Table 4-19: cPCI-3520M 100-pin I/O Connector Pin Definition ........ 54

Table 4-20: Serial ATA Connector on RTM . 56

Table 4-21: SATA on cPCI-3520D/G/M Daughter Board Pin Def’n.. 56

Table 4-22: CFast Socket Pin Definition.. . 57

Table 4-23: Layer-2 Daughter Board Connector Pin Definition ........ 58

Table 4-24: Storage Daughter Board Connector Pin Definition........ 59

Table 4-25: cPCI-3520G Daughter Board Connector Pin Definition. 60

Table 4-26: PMC/XMC Daughter Board Connector Pin Definition.... 61

Table 4-27: PMC Connector Pin Definitions .. . 62

Table 4-28: XMC Connector Pin Definition.. .. 64

Table 4-29: GPIO MMIO Addresses. .. 65

Table 4-30: CompactPCI J1 Connector Pin Definition... .. 66

Table 4-31: CompactPCI J2 Connector Pin Definition.. .. 67

Table 4-32: cPCI-R3P00 rJ2 Connector Pin Definition.......... ... 68

Table 4-33: cPCI-R3P00T rJ2 Connector Pin Definition..... .. 69

Table 4-34: XMC VPWR Select Jumper Settings... . 70

Table 4-35: PMC V(I/O) Select Jumper Settings .. . 70

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# 1 Introduction

# 1.1 Overview

The ADLINK cPCI-3520 Series is a 3U CompactPCI® processor blade with soldered DDR4-2666 ECC memory up to 32GB. The ADLINK cPCI-3520 features the Intel® Xeon® E, 8th/9th Gen Intel® Core™ processor with Mobile Intel® CM246 Chipset.

The cPCI-3520 Series is a 3U CompactPCI blade available in single-slot (4HP), dual-slot (8HP) or triple-slot (12HP) width form factors with various daughter boards to provide a broad range of I/O requirements. Faceplate I/O in the single-slot (4HP) version includes 1x DVI-I, 2x GbE and 1x USB 3.0 port (these I/O are common to all versions). Faceplate I/O in the dual-slot (8HP) version includes additional 2x USB 2.0, 1x COM, 1x KB/MS and Line-in/Line-out on the cPCI-3520D or additional 2x DisplayPorts, 1x COM in RJ-45 connector, 1x KB/MS and 1x additional USB 2.0 port on the cPCI-3520G. Two more dual-slot options are the cPCI-3520L with additional 2x GbE, 1x COM and 2x USB and the cPCI-3520M with one 100-pin high density connector supporting additional 2x DVI-D, 2x USB 2.0, 2x COM, 2x KB/MS and Line-in/Line-out ports.

Graphics support is integrated on the CPU and allows 3 independent displays on the faceplate by selecting the cPCI-3520G with additional 2x DisplayPorts. Storage includes a CFast slot, mSATA socket or a 32GB onboard SSD and 2.5" SATA drive on the layer 2 daughter board (cPCI-3520D/L/M/P). One optional PCI 32-bit/66MHz PMC site or PCIe x1 XMC site is available on the 8HP or 12HP versions (cPCI-3520S or cPCI-3520P).

Rear I/O signals to J2 include 4x PCIe x1, 3x SATA 3 Gb/s, and 3x USB 2.0. 3x GPIO and SMBus signals are also routed to the J2 connector. The optional Rear Transition Module (RTM) provides 3x SATA, 2x GbE, 2x USB, 1x COM (Tx/Rx), and 1x VGA port.

The cPCI-3520 is a high performance solution for factory automation and other industrial applications that require superior data transfer capability and advanced computing power. The ADLINK cPCI-3520 provides high manageability, supports Satellite mode operation as a standalone blade in peripheral slots, and IPMI for system health monitoring. A GbE port on the faceplate supports Intel® AMT 9.0 for remote monitoring.

# 1.2 Features

 3U CompactPCI blade in 4HP, 8HP or 12HP width form factor
 Intel® Xeon® E, 8th/9th Gen Intel® Core™ Processor
 Graphics and memory controllers integrated in processor
 Dual channel DDR4-2666 soldered SDRAM with ECC, up to 32GB
 32-bit, 33/66MHz CompactPCI Interface based on PCI specifications, universal V(I/O)
 Supports Satellite mode operation as a standalone blade in peripheral slots
 Optional 32-bit/66MHz PMC or PCIe x1 XMC site
 Supports IPMI for system health monitoring
 DVI-I port on front with VGA switchable to rear I/O by BIOS setting
 Additional two DisplayPorts on layer 2 daughter board (cPCI-3520G)
 Supports 3 independent displays
 Two PCIe Gigabit Ethernet egress ports
Two additional PCIe Gigabit Ethernet Controllers routed to RTM (cPCI-R3P00)
 Additional two Gigabit Ethernet ports on 80mm RTM (cPCI-R3P00T)
 Line-in and Line-out ports on faceplate (cPCI-3520D)
 CFast or mSATA socket for SATA interface storage
 Optional onboard SSD for SATA interface storage (shares space with CFast socket)
 2.5" SATA connector on 8HP/12HP versions at 6 Gb/s (cPCI-3520D/G/M/L/P)

# 1.3 Model Number Decoder

# Blades

![cPCI-EX 3520 D / 9850HL / 32G / S32\n(A) (B) (C) (D) (E)](.cpci-3520-50m-00036-1000-10-07102024/c63bcdd61653332d2c8fb27b881f532432dea66ce9ebf7a1830640ef8abe7741.jpg)

# (A) Operating Temperature Code

 Blank = -20°C to +70°C
 EX= -40°C to +85°C (for CPUs with TDP 25W only)

# (B) Configuration Code

 Blank = Single slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE
 D = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x USB 2.0, COM (RS-232/422/485), PS/2 KB/MS, Line-in, Line-out ports and 2.5" SATA drive space on layer 2
 G = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x DisplayPort, RJ-45 COM (RS-232/422/485), PS/2 KB/MS, USB 2.0 ports, onboard SATA connector and 2.5" SATA drive space on layer 2
 L = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x GbE, 1x DB-9 COM (RS-232/422/485), 1x USB 2.0 on faceplate, and 2.5" SATA drive space on layer 2
 M = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 1x 100-pin high density connector supports, 2x DVI-D, 2x USB 2.0, 2x COM (RS-232/422/485), 1x KB/MS, audio and 2.5" SATA drive space on layer 2
 P =Triple slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; 2x USB 2.0, COM (RS-232/422/485), PS/2 KB/MS, Line-in, Line-out ports and 2.5" SATA drive space on layer 2; PMC/XMC site on layer 3
 S = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE on layer 1; PMC/XMC site on layer 2
 T = Dual slot width with CFast socket, 1x DVI-I, 1x USB 3.0, 2x GbE via RJ45 on layer 1; 2x GbE via M12, 1x DB-9 COM (RS-232/422/485), 1x onboard USB 2.0 port and 2.5" SATA drive space on layer 2

# (C) CPU Code

 2276ML= 6-core Intel® Xeon® E-2276ML w/ ECC
 9850HL = 6-core Intel® Core™ i7-9850HL
 8400HL = 4-core Intel® Core™ i5-8400H
 9100HL= 4-core Intel® Core™ i3-9100HL w/ ECC

# (D) Memory Size Code

 M8 = 8GB DDR3L-2666 soldered SDRAM
 M16 = 2x 8GB DDR3L-2666 soldered SDRAM
 M32 = 2x 16GB DDR4-2666 soldered SDRAM

# (E) Storage Board Code

 Blank = Default with CFast socket
 MS = Equipped with mSATA socket
 S32 = Onboard soldered 32GB SSD

# RTMs

![cPCI- R3P00 T\n(A)](.cpci-3520-50m-00036-1000-10-07102024/90a2fb145db7220ee0c93aae0a86945a5dce5686e0466830569190c92d6a609d.jpg)

# (A) Model Code

 Blank = dual slot width, 50mm depth 3U RTM with 2x COM, 2x USB, 3x SATA, VGA, 2x GbE (switched from front CPU blade)
 T = dual slot width, 80mm depth 3U RTM with 2x COM, 2x USB, 3x SATA, VGA, 2x GbE (independent from front CPU blade)

# 1.4 Package Contents

The cPCI-3520 is packaged with the following components. If any of the following items are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of cPCI-3520 Series non-standard configurations will vary depending on customer requests.

# Processor Blade

 The cPCI-3520 Series Processor Blade
 CPU and memory specifications will differ depending on options selected
 Thermal module is assembled on the board
 Y-cable for PS/2 combo port (cPCI-3520D/P only)
 $2 . 5 "$ SATA drive installation kit (cPCI-3520D/G/L/M/P only)
 RJ-45 to DB-9 COM adapter cable (cPCI-3520G version only)
 DisplayPort to DVI adapter cable (cPCI-3520G version only)l

![The image displays a document icon featuring horizontal gray lines representing text, overlaid with a large, bold red checkmark on the right side.](.cpci-3520-50m-00036-1000-10-07102024/c7e4f53f2b2a233ac8741aff0e8f12f0e709f9e9542fc0034a84b799c39d30c2.jpg)
NOTE:

No I/O cables are included with the cPCI-3520M version.

![A white document icon featuring faint horizontal lines and a large red checkmark superimposed on top, with the top left corner folded down.](.cpci-3520-50m-00036-1000-10-07102024/e8fc4744026208626cf3e297b8ad958c9bc3247d28e51c6f45d6a2c82103acf1.jpg)
NOTE:

The contents of non-standard cPCI-3520 configurations may vary depending on the customer’s requirements.

# Rear Transition Module

 cPCI-R3P00 or cPCI-R3P00T RTM

# Blade Optional Accessories

 2.5” SATA drive installation kit (P/N 58-00176-0000)
 Y-cable for PS/2 combo port (P/N 30-01016-2000)
 RJ-45 to DB-9 COM adapter cable (P/N 30-01020-0200)
 DisplayPort to DVI adapter cable (P/N 30-01120-0000)
 DisplayPort to VGA adapter cable (P/N 30-01119-0000)
 DisplayPort to HDMI adapter cable (P/N 30-01121-0000)
 USB 3.0 Type A male-to-female extension cable (P/N: 30-01175-0000)
SCSI 100-pin IO cable: 2x DVI-D female, 2x DB9 male, 2x USB female, 2x PS/2 female, 2x audio jack (available by request)

![A yellow triangular warning sign with a black border containing a large black exclamation point and a small black dot near the bottom. Below the triangle, the text 'CAUTION:' appears in black capital letters.](.cpci-3520-50m-00036-1000-10-07102024/2c769679df4cbf5ad888c27b36ce5e6d9efd0c90f35f65a973cce0c08d71782e.jpg)

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

2.1 cPCI-3520 Processor Blade Specifications

<table><tr><td>CompactPCI®Standards</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.9 System Management Rev. 1.0 (IPMI v1.5)</td></tr><tr><td>Mechanical</td><td>Standard 3U CompactPCI®Board size: 100mm x 160mmSingle slot (4HP, 20.32mm); Dual slot (8HP, 40.64mm); Triple slot (12HP, 60.96 mm)CompactPCI® with HM type J1 connector, UHM type J2 connector</td></tr><tr><td>Processor</td><td>6-core Intel® Xeon® E-2276ME Processor 2.8GHz, 4.5GHz Turbo, 12M cache, 45W (35W by cTDP)6-core Intel® Xeon® E-2276ML Processor 2GHz, 4.2GHz Turbo, 12M cache, 25W6-core Intel® CoreTM i7-9850HE Processor 2.7GHz, 4.4GHz Turbo, 9M cache, 45W (35W by cTDP)6-core Intel® CoreTM i7-9850HL Processor 1.9GHz, 4.1GHz Turbo, 9M cache, 25W4-core Intel® CoreTM i5-8400H Processor 2.5GHz, 4.2GHz Turbo, 8M cache, 45W (35W by cTDP)4-core Intel® CoreTM i3-9100HL Processor 1.6GHz, 2.9GHz Turbo, 6M cache, 25WPassive heatsink</td></tr><tr><td>Chipset</td><td>Mobile Intel® CM246 Chipset</td></tr><tr><td>Memory</td><td>Dual channel DDR4-2666 SDRAM ECC soldered, up to 32GBDRAM configuration 32GB/16GB/8GB</td></tr><tr><td>CompactPCIBus</td><td>PCI 32-bit 33/66MHz; 3.3V, 5V universal V(IO)Supports operation in system slot as master or in peripheral slot as standalone blade without connectivity to CompactPCI bus (Satellite mode)</td></tr><tr><td>GigabitEthernet</td><td>One PCIe x1 Intel® I219LM GbE PHY and three PCIe x1 Intel® Ethernet Controllers I210ITTwo egress 10/100/1000BASE-T ports on faceplate, one supporting Intel® AMT by I219LMTwo egress 10/100/1000BASE-T ports routed to rear transition moduleTwo additional egress 10/100/1000BASE-T ports on faceplate (cPCI-3520L and cPCI-3520T)</td></tr></table>

Table 2-1: cPCI-3520 Processor Blade Specifications

<table><tr><td>Graphics</td><td>Integrated on Intel® CoreTM processorDVI-I port on faceplate, VGA switchable to J2 (RTM) by BIOS settingAnalog monitor support up to QXGA 2048x1536 @75Hz, 32-bitTwo DisplayPorts on faceplate with resolution up to 2560x1440 @60Hz (cPCI-3520G only)Up to three independent displays</td></tr><tr><td>USB</td><td>Front:4HP: 1x USB 3.1 Gen2 Type A port8HP: Up to two USB 2.0 on riser card(cPCI-3520D/P: 1x USB 3.1 Gen2 + 2x USB 2.0)(cPCI-3520G: 1x USB 3.1 Gen2 + 1x USB 2.0)(cPCI-3520L: 1x USB 3.1 Gen2 + 1x USB 2.0)Rear:Up to 3x USB2.0</td></tr><tr><td>Serial Ports</td><td>Front:4HP: no serial port8HP: 1x RS-232/422/485One RS-232/422/485 serial port on 8HP faceplate (cPCI-3520D/L/P: 1x DB-9 COM, cPCI-3520G: 1x RJ-45 COM)Additional RS-232 10-pin header on layer-2 board (cPCI-3520G only)Rear:1x Tx/Rx to J2</td></tr><tr><td>PMC/XMC</td><td>One 32-bit/66MHz PMC site or PCIe x1 XMC site if PMC/XMC daughter board is installed</td></tr><tr><td>Audio</td><td>Line-in/Line-out on faceplate by Realtek ALC262 High Definition Audio codec (cPCI-3520D only)</td></tr><tr><td>GPIO</td><td>3x GPIO signals from chipset: GPP_E0, GPP_E1 and GPP_E2</td></tr><tr><td>TPM</td><td>TPM 2.0</td></tr><tr><td>Storage Interfaces $^{1}$ </td><td>CFast or mSATA socket on daughter boardOptional onboard SSD on daughter boardOne SATA 6Gb/s direct connector for 2.5&quot; SATA drive (8HP/12HP version only)</td></tr><tr><td>BIOS</td><td>AMI® UEFI BIOS, SPI flash memory</td></tr><tr><td>OS Compatibility</td><td>Microsoft Windows 10 IOT Enterprise 64-bitVxWorks 7.0Other OS support upon request</td></tr></table>

Table 2-1: cPCI-3520 Processor Blade Specifications

<table><tr><td>Environmental</td><td>Operating Temperature (with forced air flow) $^{2}$ :Standard: -20°C to 70°CExtreme temperature: -40°C to +85°CStorage Temperature: -50°C to 100°CHumidity: 95% @60°C non-condensingShock: 20G peak-to-peak, 11ms duration, non-operatingVibration $^{3}$ : 2Grms, 5-500Hz, each axis, operating (w/o hard drive)</td></tr><tr><td>Safety &amp; EMI</td><td>CE/FCC</td></tr><tr><td>Faceplate I/O</td><td>4HP cPCI-35201x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port8HP cPCI-3520D1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x USB 2.0 portsDB-9 RS-232/422/485/485+ portPS/2 Keyboard/Mouse combo portLine-in and Line-out port8HP cPCI-3520G1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x DisplayPort1x USB 2.0 portsRJ-45 RS-232/422/485 portPS/2 Keyboard/ Mouse combo port8HP cPCI-3520L1x USB 3.0 ports1x DVI-I port4x 10/100/1000BASE-T Ethernet ports1x USB 2.0 portsDB-9 RS-232/422/485 port8HP cPCI-3520M1x USB 3.0 ports1x DVI-I port2x 10/100/1000BASE-T Ethernet ports1x 100-pin connector supports 2x DVI-D, Line-in/Line-out, 2x USB 2.0, 2x RS-232/422/485 COM, 1x KB/MS</td></tr></table>

Table 2-1: cPCI-3520 Processor Blade Specifications

<table><tr><td rowspan="3">Faceplate I/O (cont&#x27;d)</td><td>8HP cPCI-3520S1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I portPMC/XMC site</td></tr><tr><td>8HP cPCI-3520T1x USB 3.0 ports1x DVI-I port4x 10/100/1000BASE-T Ethernet ports (2x RJ-45, 2x M12)DB-9 RS-232/422/485 port</td></tr><tr><td>12HP cPCI-3520P1x USB 3.0 ports2x 10/100/1000BASE-T Ethernet ports1x DVI-I port2x USB 2.0 portsDB-9 RS-232/422/485/485+ portPS/2 Keyboard/Mouse combo portLine-in and Line-out portPMC/XMC site</td></tr></table>

Table 2-1: cPCI-3520 Processor Blade Specifications

1. The storage device limits the operational vibration tolerance. When the application requires higher specification for anti-vibration, it is recommended to use a flash storage device.
2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Sufficient forced air-flow is required. Temperature limits of optional mass storage devices may also affect the thermal specification.

# 2.2 cPCI-R3P00(T) RTM Specifications

<table><tr><td>Mechanical</td><td>Board Size• cPCI-R3P00: 100mm x 50mm• cPCI-R3P00T: 100mm x 80mmDual-slot (8HP, 40.64mm)(optional single slot upon request)</td></tr><tr><td>Gigabit Ethernet</td><td>• cPCI-R3P00: Two GbE ports switched from cPCI-3520 2x Intel® Ethernet Controllers I210• cPCI-R3P00T: Two GbE ports from independent Intel® 82580DB GbE controller</td></tr><tr><td>Serial Ports</td><td>• Two serial ports on I/O panel from pin header• One port converted from USB supporting RS-232/422/485• One port provides Tx, Rx signals only</td></tr><tr><td>Storage Interfaces</td><td>• Three 7-pin Serial ATA ports</td></tr><tr><td>Faceplate I/O</td><td>• 2x USB 2.0 ports• 2x 10/100/1000BASE-T Ethernet ports• Analog DB-15 VGA port• 2x COM ports</td></tr></table>

Table 2-2: cPCI-R3P00(T) RTM Specifications

![The image displays a white document icon with its top-left corner folded down. Horizontal gray lines run across the page. A large, bold red checkmark is superimposed over the document, slanting upwards from the bottom left to the top right.](.cpci-3520-50m-00036-1000-10-07102024/57612574974bc5d9a3c22a13321c823e193a89e6b1afb029e5248dc4d691a35e.jpg)
NOTE:

Specifications are subject to change without prior notice.

# 2.3 Block Diagrams

# cPCI-3520 Processor Blade

![**Top Level and Memory:**\n*   **Faceplate** connects to dashed boxes labeled **DVI-I**, **GbE1**, **GbE2**, and **USB**.\n*   Two blocks labeled **ECC, up to 16GB** connect to each other via **DDR4-2133**.\n*   The bottom **ECC, up to 16GB** block connects to **Intel® Coffee Lake-H** via **DDR4-2133**.\n\n**Central Processing and Chipset:**\n*   **Intel® Coffee Lake-H** connects to **Intel® CM246 Chipset** via **DMI**.\n*   **Intel® Coffee Lake-H** connects to **DVI** (leading to **DVI-I**) and **VGA** (leading to the Faceplate).\n*   **Intel® Coffee Lake-H** connects to **B2B Conn. #2** via **DP1/DVI** and **DP2/DVI**.\n\n**Chipset Connections (Intel® CM246 Chipset):**\n*   Connects to **Intel® I219** (labeled **PCIe x1**) and **Intel® I210** (labeled **PCIe x1**), which lead to **GbE1** and **GbE2** respectively.\n*   Connects to **USB** (via **USB 3.0**).\n*   Connects to **SSD**, **CFast**, and **mSATA** (via **SATA**).\n*   Connects to **Battery** (via **RTC**) and **BIOS** (via **SPI**).\n*   Connects to **SIO** (via **LPC** and **COM1, KB/MS**).\n*   Connects to **B2B Conn. #1** (via **SATA, HDA, 2x USB 2.0** and **2x PCIe x1**).\n*   Connects to **2x Intel® I210** (via **2x PCIe x1**).\n*   Connects to **J2** (via **4x PCIe x1** and **3x GPIO**).\n\n**Middle and Lower Logic Blocks:**\n*   **SIO** connects to **B2B Conn. #2** (via **COM2**) and **B2B Conn. #1** (unlabeled connection).\n*   **SIO** connects to **Atmel GA128** (via **COM3**).\n*   **B2B Conn. #2** connects to **PCIe to PCI Bridge** (via **PCIe x4**).\n*   **PCIe to PCI Bridge** (labeled **PCI 32-bit 33/66MHz**) connects to **J1**.\n*   **Atmel GA128** connects to **J1** (via **IPMB 0/1**) and **J2** (via **VGA**).\n\n**Bottom Connectors (J1 and J2):**\n*   **B2B Conn. #1** connects to **J2** (via **COM4**).\n*   **2x Intel® I210** connects to **J2** (via **2x GbE**, **3x USB**, and **3x SATA**).](.cpci-3520-50m-00036-1000-10-07102024/4de8a2e774be3355e5697a31483791c441e583c704ae0a5b89cecb524ab88be1.jpg)

Figure 2-1: cPCI-3520 Processor Blade Functional Block Diagram

cPCI-3520D Daughter Board (DB-3610L2)
![The diagram displays a connection layout between two vertical blocks: a yellow block labeled **'L2 Front Panel'** on the left and an orange block labeled **'B2B Conn. 1'** on the right.\n\nFive horizontal lines connect the right block to the left block, indicated by arrows pointing toward the 'L2 Front Panel.' From top to bottom, the connections are:\n\n1.  **USB x2**: A direct line connecting the two blocks.\n2.  **Line-in, Line-out**: A line passing through a blue block labeled **'Codec'**.\n3.  **SATA0**: A line passing through an orange block labeled **'2.5' HDD/SDD'**.\n4.  **PS/2, KB/MS**: A direct line connecting the two blocks.\n5.  **COM**: A direct line connecting the two blocks.](.cpci-3520-50m-00036-1000-10-07102024/71d0e1d2030be9cb410f5d1116d9a35374b4f814ac251636b42deffd4485d53d.jpg)

Figure 2-2: cPCI-3520D Daughter Board Functional Block Diagram

cPCI-3520G Daughter Board (DB-3970L2)
![**Labeled Blocks:**\n*   **Left Vertical Block:** A tall yellow rectangle labeled 'L2' at the top and 'Front Panel' running vertically down the center.\n*   **Right Vertical Block:** A tall orange rectangle labeled 'B2B Conn. 1/2'.\n*   **Middle Block (Top):** A small orange rectangle labeled '2.5' HDD/SSD'.\n*   **Middle Block (Bottom):** A small orange rectangle labeled '10-pin'.\n\n**Connections:**\nSeven horizontal black lines connect the right block ('B2B Conn. 1/2') to the left block ('L2 Front Panel'). Each line features an arrow pointing to the left. The lines are labeled from top to bottom as follows:\n1.  **USB**\n2.  **DVI/DP**\n3.  **SATA0** (Runs beneath the '2.5' HDD/SSD' block)\n4.  **DVI/DP**\n5.  **COM1**\n6.  **COM2** (Runs beneath the '10-pin' block)\n7.  **KB/MS**](.cpci-3520-50m-00036-1000-10-07102024/2f70f9154a185a266fc89e9b1ce5d2056af2d190a3a2635986b38f6919f30252.jpg)

Figure 2-3: cPCI-3520G Daughter Board Functional Block Diagram

cPCI-3520L Daughter Board (DB-LAN2-S)
![Based on the provided flowchart, here is the accurate description of the blocks and connections:\n\n**Labeled Blocks:**\n*   **L2 FRONT PANEL** (Vertical yellow bar on the left)\n*   **B2B Conn.** (Vertical yellow bar on the right)\n*   **Horizontal Type A** (Orange box with a dashed border, top center)\n*   **2.5' HDD** (Orange box, center)\n*   **82574L** (Blue box, lower left-center)\n*   **82574L** (Blue box, lower right-center)\n\n**Connections:**\n*   **USB x1**: Connects **B2B Conn.** to **L2 FRONT PANEL** (Arrow points left).\n*   **USB x1**: Connects **B2B Conn.** to **Horizontal Type A** (Arrow points left).\n*   **RS232/422/485**: Connects **B2B Conn.** to **L2 FRONT PANEL** (Arrow points left).\n*   **SATA0**: Connects **B2B Conn.** to **2.5' HDD** (Arrow points left).\n*   **GbE 3**: Connects **B2B Conn.** to the upper **82574L** block, and then from the upper **82574L** block to **L2 FRONT PANEL** (Arrow points left).\n*   **GbE 4**: Connects **B2B Conn.** to the lower **82574L** block, and then from the lower **82574L** block to **L2 FRONT PANEL** (Arrow points left).](.cpci-3520-50m-00036-1000-10-07102024/2b2d8ad858788f7745903aece9af2a84c7b7b59ee92931ea12de835b8b096f7b.jpg)

Figure 2-4: cPCI-3520L Daughter Board Functional Block Diagram

cPCI-3520M Daughter Board (DB-Max)
![The diagram depicts a connectivity layout involving three primary labeled blocks:\n\n**Labeled Blocks:**\n*   **Left Block:** A tall vertical rectangle labeled '**100-pin high density connector**' with the text '**F R O N T P A N E L**' running vertically down its center.\n*   **Middle Block:** A smaller rectangle labeled '**2.5' HDD/Slim SSD**'.\n*   **Right Block:** A tall vertical rectangle labeled '**B2B Conn.**'.\n\n**Connections:**\nArrows and lines originate from the '**B2B Conn.**' block and connect to the other two blocks with the following labels:\n*   '**Line-in, Line-out**' connects to the '**100-pin high density connector**'.\n*   '**2x DVI-D**' connects to the '**100-pin high density connector**'.\n*   '**SATA0**' connects to the '**2.5' HDD/Slim SSD**'.\n*   '**2x USB 2.0**' connects to the '**100-pin high density connector**'.\n*   '**2x COM (RS232/422/485)**' connects to the '**100-pin high density connector**'.\n*   '**KB/MS**' connects to the '**100-pin high density connector**'.](.cpci-3520-50m-00036-1000-10-07102024/b5d9592e7215fcffa4d33febf258f2162b905ea8451bfc153cd6c9558e15776f.jpg)

Figure 2-5: cPCI-3520M Daughter Board Functional Block Diagram

cPCI-R3P00 RTM
![This flowchart depicts connections between a vertical block labeled **J2** on the left and a vertical block labeled **Rear Panel** on the right.\n\n**Direct Connections:**\n*   A line labeled **COM (Tx, Rx)** connects **J2** to the **Rear Panel**.\n*   A line labeled **2x USB** connects **J2** to the **Rear Panel**.\n*   A line labeled **GbE 1/2** connects **J2** to the **Rear Panel**.\n*   A line labeled **VGA** connects **J2** to the **Rear Panel**.\n\n**SATA Connection:**\n*   A line labeled **SATA3/4/5** connects **J2** to a stack of three smaller blocks, each labeled **7 pin**.\n\n**Serial/USB Connection:**\n*   A line labeled **USB3** connects **J2** to a blue block labeled **FT232R**.\n*   The line continues from the **FT232R** block to the **Rear Panel** with the label **RS232/422/485**.](.cpci-3520-50m-00036-1000-10-07102024/03541ac91e1b1c721257f8ba20e803ea1348c05f1d7593bdcccab3e62097c554.jpg)

Figure 2-6: cPCI-R3P00 RTM Functional Block Diagram

cPCI-R3P00T RTM
![This flowchart depicts connections between a vertical block on the left labeled **J2** and a vertical block on the right labeled **Rear Panel**.\n\nThe connections are arranged from top to bottom as follows:\n\n*   A line labeled **COM (Tx, Rx)** connects directly from J2 to the Rear Panel.\n*   A line labeled **2x USB** connects directly from J2 to the Rear Panel.\n*   A line labeled **PCIe x4** connects to a blue block labeled **82580DB**, which then connects via a line labeled **GbE 3/4** to the Rear Panel.\n*   A line labeled **VGA** connects directly from J2 to the Rear Panel.\n*   A line labeled **SATA3/4/5** points to a stack of three orange blocks, each labeled **7 pin**.\n*   A line labeled **USB3** connects to a blue block labeled **FT232R**, which then connects via a line labeled **RS232/422/485** to the Rear Panel.](.cpci-3520-50m-00036-1000-10-07102024/d7d1ee73f205ef16f3220eb1462ef92587300705db5bfeb8a1832f405b5463c2.jpg)

Figure 2-7: cPCI-R3P00T RTM Functional Block Diagram

# 2.4 I/O Connectivity Table

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-3520(4HP)</td><td colspan="2">cPCI-3520D(8HP)</td><td colspan="2">cPCI-3520G(8HP)</td><td colspan="2">cPCI-3520L(8HP)</td></tr><tr><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>4 (RJ-45)</td><td></td></tr><tr><td>USB</td><td>1 (3.0)</td><td></td><td>1 (3.0)2 (2.0)</td><td></td><td>1 (3.0)1 (2.0)</td><td></td><td>1 (3.0)1 (2.0)</td><td></td></tr><tr><td>COM</td><td></td><td></td><td>1 (DB9)</td><td></td><td>1 (RJ-45)</td><td>1 (10-pin)</td><td>1(DB9)</td><td></td></tr><tr><td>Display</td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)2 (DP)</td><td></td><td>1 (DVI-I)</td><td></td></tr><tr><td>KB/MS</td><td>Y</td><td></td><td>Y</td><td></td><td>1</td><td></td><td></td><td></td></tr><tr><td>Storage</td><td></td><td>1 CFast</td><td></td><td>1 SATA1 CFast</td><td></td><td>1 SATA1 CFast</td><td></td><td>1 SATA1 CFast</td></tr><tr><td>Onboard SSD</td><td></td><td> $optional^1$ </td><td></td><td> $optional^1$ </td><td></td><td> $optional^1$ </td><td></td><td> $optional^1$ </td></tr><tr><td>Audio</td><td></td><td></td><td>Line-in Line-out</td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PMC/XM</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

Table 2-3: cPCI-3520 I/O Connectivity

1. Available by replacing CFast or mSATA socket adapter board with onboard SSD adapter board.

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-3520M(8HP)</td><td colspan="2">cPCI-3520S(8HP)</td><td colspan="2">cPCI-3520T(8HP)</td><td colspan="2">cPCI-3520P(12HP)</td></tr><tr><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)</td><td></td><td>2 (RJ-45)2(M12)</td><td></td><td>2 (RJ-45)</td><td></td></tr><tr><td>USB</td><td>1 (3.0)2 (2.0)</td><td></td><td>1 (3.0)</td><td></td><td>1 (3.0)</td><td></td><td>1 (3.0)2 (2.0)</td><td></td></tr><tr><td>COM</td><td>2 (DB9)</td><td></td><td></td><td></td><td>1 (DB9)</td><td></td><td>1 (DB9)</td><td></td></tr><tr><td>Display</td><td>1 (DVI-I)2 (DVI-D)</td><td></td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)</td><td></td><td>1 (DVI-I)</td><td></td></tr><tr><td>KB/MS</td><td></td><td></td><td></td><td></td><td>1</td><td></td><td>1</td><td></td></tr><tr><td>Storage</td><td></td><td>1 SATA1 CFast</td><td></td><td></td><td></td><td>1 SATA1 CFast</td><td></td><td>1 SATA1 CFast</td></tr><tr><td>Onboard SSD</td><td></td><td> $optional^1$ </td><td></td><td></td><td></td><td> $optional^{1,2}$ </td><td></td><td></td></tr><tr><td>Audio</td><td>Line-inLine-out</td><td></td><td></td><td></td><td>Line-inLine-out</td><td></td><td>Line-inLine-out</td><td></td></tr><tr><td>PMC/XMC</td><td></td><td></td><td></td><td>1</td><td></td><td>1</td><td></td><td>1</td></tr></table>

Table 2-3: cPCI-3520 I/O Connectivity (cont’d)

1. Available by replacing CFast or mSATA socket adapter board with onboard SSD adapter board.
2. When select cPCI-3520T with mSATA daughter board, strongly recommend to pre-installed mSATA module during production.

<table><tr><td rowspan="2">Function</td><td colspan="2">R3P00(T)(RTM)</td></tr><tr><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>2 (RJ-45) $^1$ </td><td></td></tr><tr><td>USB</td><td>2 (2.0)</td><td></td></tr><tr><td>COM</td><td>2 (DB9)</td><td></td></tr><tr><td>Display</td><td>1 (VGA) $^2$ </td><td></td></tr><tr><td>KB/MS</td><td></td><td></td></tr><tr><td>Storage</td><td></td><td>3 SATA</td></tr><tr><td>Onboard SSD</td><td></td><td></td></tr><tr><td>Audio</td><td></td><td></td></tr><tr><td>PMC/XMC</td><td></td><td></td></tr></table>

Table 2-4: R3P00(T) RTM I/O Connectivity

1. Routed from CPU blade faceplate for cPCI-R3P00; independent of CPU blade for cPCI-R3P00T (GbE controller onboard).
2. VGA switched from faceplate.

# 2.5 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

# Power Consumption

This section provides information on the power consumption of cPCI-3520 Series when using the Intel® Core™ i7 and Intel® Xeon® E processors with 32GB DDR4-2666 SO-DIMM memory and 500GB SATA SSD. The cPCI-3520 is powered by +5 V and +3.3V.

<table><tr><td colspan="4">Intel® CoreTM i7-9850HE</td></tr><tr><td>OS/Mode</td><td>Current 5V</td><td>Current 3.3V</td><td>Total Power</td></tr><tr><td>Windows 10 x64 Idle Mode $^{1}$ </td><td>1.48A</td><td>1.72A</td><td>13.076W</td></tr><tr><td>Windows 10 x64 Typical Mode $^{2}$ </td><td>7.42A</td><td>1.77A</td><td>42.941W</td></tr><tr><td>Windows 10 x64 Maximum Mode $^{3}$ </td><td>6.52A</td><td>1.76A</td><td>38.408W</td></tr></table>

<table><tr><td colspan="4">Intel® Xeon E-2276ML</td></tr><tr><td>OS/Mode</td><td>Current 5V</td><td>Current 3.3V</td><td>Total Power</td></tr><tr><td>Windows 10 x64 Idle Mode $^{1}$ </td><td>2.47A</td><td>2.58A</td><td>20.86W</td></tr><tr><td>Windows 10 x64 Typical Mode $^{2}$ </td><td>6.34A</td><td>2.65A</td><td>40.45W</td></tr><tr><td>Windows 10 x64 Maximum Mode $^{3}$ </td><td>6.34A</td><td>2.64A</td><td>40.41W</td></tr></table>

# Notes:

1. The system set to idle mode and stays idle for 10 minutes.
2. Run BurnInTest™ that includes CPU, memory, video and 2D/3D graphics. Set all test items to 100% loading and run for 10 minutes.
3. Run Intel® Thermal Analysis Tool that includes CPU, graphics and memory. Set all test items to 100% loading and run for 10 minutes.

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# 3 Functional Description

The following sections describe the cPCI-3520 Series features and functions.

# 3.1 Processors

The Mobile 8th/9th Generation Intel® Core™ Processor Family, and Intel® Xeon® E Processor are 64-bit, multi-core mobile processor built on 14 nanometer process technology. The processor is designed for a two-chip platform consisting of a processor and chipset. The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics and Integrated Memory Controller.

The cPCI-3520 Series supports Intel® Core™ i7/i5/i3 and Xeon® E processors. The table below lists the general specifications and power ratings of the CPUs supported by the cPCI-3520 Series.

<table><tr><td>Features</td><td>Xeon®E-2276ME</td><td>Xeon®E-2276ML</td><td>CoreTM i7-9850HE</td><td>CoreTM i7-9850HL</td><td>CoreTM i5-8400H</td><td>CoreTM i3-9100HL</td></tr><tr><td>Clock</td><td>2.8GHz</td><td>2.0GHz</td><td>2.7GHz</td><td>1.9GHz</td><td>2.5GHz</td><td>1.6GHz</td></tr><tr><td>Max. Single Core Turbo Freq.</td><td>4.5GHz</td><td>4.2GHz</td><td>4.4GHz</td><td>4.1GHz</td><td>4.2GHz</td><td>2.9GHz</td></tr><tr><td>Last Level Cache</td><td>12MB</td><td>12MB</td><td>9MB</td><td>9MB</td><td>8MB</td><td>6MB</td></tr><tr><td>No. of Cores/Threads</td><td>6/12</td><td>6/12</td><td>6/12</td><td>6/12</td><td>4/8</td><td>4/4</td></tr><tr><td>Max. Power (TDP $^{1}$ )</td><td>45W</td><td>25W</td><td>45W</td><td>25W</td><td>45W</td><td>25W</td></tr><tr><td>DMI</td><td>8 GT/s</td><td>8 GT/s</td><td>8 GT/s</td><td>8 GT/s</td><td>8 GT/s</td><td>8 GT/s</td></tr><tr><td> $T_{junction, MAX}^{2}$ </td><td>100°C</td><td>100°C</td><td>100°C</td><td>100°C</td><td>100°C</td><td>100°C</td></tr></table>

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.

2. The maximum temperature allowed at the processor die.

Supported Technologies

<table><tr><td>Features</td><td>Xeon® E-2276MEXeon® E-2276MLCoreTM i7- 9850HLCoreTM i7- 9850HLCoreTM i5- 8400HCoreTM i3- 9100HL</td></tr><tr><td>Intel® Virtualization Technology for Directed I/O (Intel® VT-d)</td><td>Yes</td></tr><tr><td>Intel® Virtualization Technology (Intel® VT-x)</td><td>Yes</td></tr><tr><td>Intel® VT-x with Extended Page Tables (EPT)</td><td>Yes</td></tr><tr><td>Intel® Hyper-Threading Technology</td><td>Yes</td></tr><tr><td>Intel® 64 Architecture</td><td>Yes</td></tr><tr><td>Execute Disable Bit</td><td>Yes</td></tr><tr><td>Intel® Turbo Boost Technology</td><td>2.0</td></tr><tr><td>Intel® vPro Technology</td><td>Yes</td></tr><tr><td>Enhanced Intel SpeedStep® Technology</td><td>Yes</td></tr><tr><td>Thermal Monitoring Technologies</td><td>Yes</td></tr><tr><td>Intel® Identity Protection Technology</td><td>Yes</td></tr></table>

# Interfaces

 Two channels of DDR4-2666 memory
 Theoretical maximum memory bandwidth of
 37.5 GB/s in dual-channel mode assuming 2400 MT/s
 41.6 GB/s in dual-channel mode assuming 2666 MT/s
 64-bit wide channels
 DDR4 I/O voltage of 1.2V
 Standard 4-Gb, 8-Gb technologies and addressing are supported for x8 and x16 devices, 16-Gb technologies and addressing supported for x8 device.
 PCI Express ports are fully-compliant with the PCI Express Base Specification, Revision 3.0.
 8 GT/s point-to-point DMI interface to Chipset is supported

# 3.2 Chipset

The Mobile Intel® C240 Series Chipset provides extensive I/O support. Functions and capabilities include:

 PCI Express Base Specification, Revision 3.0
 ACPI Power Management Logic Support, Revision 4.0a
 Interrupt controller and timer functions
Integrated Serial ATA host controller 3.2, supports data transfer rates up to 6Gb/s on all ports
 XHCI USB 3.1 Controller
 Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
 Supports Intel® High Definition Audio
 Supports Intel® Rapid Storage Technology
 Supports Intel® Virtualization Technology for Directed I/O
 Integrated Clock Controller
 Analog and Digital Display ports
 Low Pin Count (LPC) interface
 Firmware Hub (FWH) interface support
 Serial Peripheral Interface (SPI) support

# 3.3 PMC/XMC

The cPCI-3520P/S models support one PMC or XMC site for faceplate I/O expansion. The PMC site provides a maximum 32-bit/66MHz PCI bus link using a Pericom PI7C9X130 PCI-Express-to-PCI bridge and PCI-Express x1 link. The PMC site supports +3.3V signaling only. The XMC site provides a PCI Express x1 lane.

# 3.4 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and/or render clock frequency when there is sufficient power headroom, and the product is within specified temperature and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations. This improves the system responsiveness for short, bursty usage conditions.

Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

# 3.5 Intel® Hyper-Threading Technology

Intel® Hyper-Threading Technology allows an execution core to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support. Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7, Vista, and XP, and disabling Hyper-Threading Technology using the BIOS for all previous versions of Windows operating systems.

# 3.6 Trusted Platform Module

The cPCI-3520 is optionally equipped with an Infineon SLB 9665TT2.0 Trusted Platform Module (TPM). The TPM is a secure controller with added cryptographic functionality to provide users a secure environment in e-commerce transactions and Internet communications.

The key features the Trusted Platform Module (TPM) offers are:

 Compliant to TPM 2.0 Rev. 01.16
 Pin compatible to SLB9660
 Low Pin Count (LPC) to allow easy system integration
 TCG and Common Criteria certified with EAL4+
 FIPS 140-2 certified FW available via FW update
 Full personalization with Endorsement Key (EK) and EK certificate
 1280 byte I/O buffer

# 3.7 Battery

The cPCI-3520 is equipped with a 3.0V "coin cell" lithium battery for the Real Time Clock (RTC). The battery socket is equipped on the storage carrier daughter board. The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. A Rayovac BR2032 is equipped on board by default, and can be optionally equipped with a Gold Capacitor (Panasonic EECS5R5H105).

# 3.8 Watchdog Timer

The watchdog timer function on the cPCI-3520 is supported by IPMI commands. Please refer to Section 8.2 “Summary of Commands Supported by BMR-AVR-cPCI” on page 111.

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# 4 Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the cPCI-3520 Series.

# 4.1 cPCI-3520 Series Board Layout

![LAN1\nCN3\nAmphenol\nUSB1\nCPU\nDV11\nCN1\nCN2\nJ2\nJ1](.cpci-3520-50m-00036-1000-10-07102024/b18fc636b5ede8786c719d755617f002b6b5874676c84a96791be9cab4f203b6.jpg)

<table><tr><td>CPU</td><td>Intel® CoreTM Processor</td><td>J1</td><td>CompactPCI connector J1</td></tr><tr><td>CN1</td><td>Layer-2 daughter board connector</td><td>J2</td><td>CompactPCI connector J2 (UHM/HM)</td></tr><tr><td>CN2</td><td>Storage daughter board connector</td><td>LAN1</td><td>Dual Ethernet connectors</td></tr><tr><td>CN3</td><td>cPCI-3520G daughter board connector</td><td>USB1</td><td>USB port</td></tr><tr><td>DVI1</td><td>DVI connector</td><td></td><td></td></tr></table>

Figure 4-1: cPCI-3520 Series Board Layout (component side)

![SW1](.cpci-3520-50m-00036-1000-10-07102024/99e852d5cf3c59da0bd572cfc729a19c4e5ccde121ea4d8fa6e5415c7b005b39.jpg)

<table><tr><td>SW1</td><td>Reset Button</td></tr></table>

Figure 4-2: cPCI-3520 Series Board Layout (solder side)

# 4.2 cPCI-3520 Blade Assembly Layout

This section describes the final assembly layout of the single slot cPCI-3520 Blade.

![Heatsink\nAmphenol\nJ2\nJP1\nSSD\nBTI\nJ1](.cpci-3520-50m-00036-1000-10-07102024/32834372f518160fdd23ff427087cdfc9573c466aa96e9bad1dccc5b6ff5e291.jpg)

Figure 4-3: cPCI-3520 Blade Assembly Layout

<table><tr><td>BT1</td><td>Battery</td><td>J1</td><td>CompactPCI connector J1</td></tr><tr><td>JP1</td><td>Clear CMOS jumper</td><td>J2</td><td>CompactPCI connector J2</td></tr></table>

# 4.3 cPCI-3520D Blade Assembly Layout

The dual-slot width cPCI-3520D Blade is comprised of the cPCI-3520 single-slot main board and the cPCI-3520D daughter board to expand I/O connectivity with PS/2, COM, 2x USB ports, Line-in, and Line-out ports .

![COM1\nSATA0\nUSB2\nUSB3\nPS/2\nCN6\nCN7\nCN8\n2.5' SATA HDD\ncPCI-3520D\ndaughter board](.cpci-3520-50m-00036-1000-10-07102024/0e229f4f7633b7b92259f5d8b730e71cfc076444a8de2fb4452fd5fa58a67664.jpg)

<table><tr><td>COM1</td><td>DB-9 COM port</td><td>CN7</td><td>Layer-2 daughter board connector</td></tr><tr><td>USB2/3</td><td>USB connectors</td><td>CN6</td><td>Line-in port</td></tr><tr><td>PS2</td><td>PS/2 KB/Ms combo port</td><td>CN8</td><td>Line-out port</td></tr><tr><td>SATA0</td><td>22-pin SATA connector</td><td></td><td></td></tr></table>

Figure 4-4: cPCI-3520D Blade Assembly Layout

# 4.4 cPCI-3520G Blade Assembly Layout

The dual-slot width cPCI-3520G Blade is comprised of the cPCI-3520 single-slot main board and the cPCI-3520G daughter board to expand I/O connectivity with PS/2, COM, USB ports, and 2x DisplayPorts.

![DP1\nDP2\nCOM1\nPS2\nUSB9\nCN2\nCOM2\nSATA0\n2.5' SATA HDD\ncPCI-3520G\ndaughter board](.cpci-3520-50m-00036-1000-10-07102024/a8fcea85dccf7365babe5233c5287834dca055cd4ba8ccf6d29ed5d53a331546.jpg)

<table><tr><td>COM1</td><td>RJ-45 COM port</td><td>CN2</td><td>Layer-2 daughter board connector</td></tr><tr><td>COM2</td><td>10-pin COM port</td><td>DP1/2</td><td>DisplayPort connectors</td></tr><tr><td>USB9</td><td>USB connector</td><td>PS2</td><td>PS/2 KB/MS combo port</td></tr><tr><td>SATA0</td><td>22-pin SATA connector</td><td></td><td></td></tr></table>

Figure 4-5: cPCI-3520G Blade Assembly Layout

# 4.5 cPCI-3520L Blade Assembly Layout

The dual-slot width cPCI-3520L Blade is comprised of the cPCI-3520 single-slot main board and the cPCI-3520L daughter board, expanding I/O connectivity with 2x LAN, COM, USB.

![LAN1\nSATA1 2.5' SATA HDD\nCOM1\nUSB1\ncPCI-3520L\ndaughter board](.cpci-3520-50m-00036-1000-10-07102024/4bfb8c2f2a1263fb754356b294ac0b02d864a043b663b2c8efbd4e4cf46129b1.jpg)

<table><tr><td>LAN1</td><td>GbE RJ-45 ports</td><td>USB1</td><td>USB connector</td></tr><tr><td>COM1</td><td>DB-9 COM port</td><td>SATA1</td><td>22-pin SATA connector</td></tr></table>

Figure 4-6: cPCI-3520L Blade Assembly Layout

# 4.6 cPCI-3520M Blade Assembly Layout

The dual-slot width cPCI-3520M Blade is comprised of the cPCI-3520 single-slot main board and the cPCI-3520M daughter board, expanding I/O connectivity with a 100-pin high density connector.

![CN4\nSATA0\ncPCI-3520M\ndaughter board](.cpci-3520-50m-00036-1000-10-07102024/60a9d397d28ddb12e000d0871dada3766e08bcdc304c5cf23a9c8385232eea09.jpg)

<table><tr><td>CN4</td><td>100-pin high density connector</td><td>SATA0</td><td>22-pin SATA connector</td></tr></table>

Figure 4-7: cPCI-3520M Blade Assembly Layout

# 4.7 cPCI-3520S Blade Assembly Layout

The dual-slot width cPCI-3520S Blade is comprised of the cPCI-3520 single-slot main board and the DB-3UMC riser card, expanding I/O connectivity with a XMC/PMC connector.

![DB-3UMC\nJN1 JN2\nJN3\nJN4](.cpci-3520-50m-00036-1000-10-07102024/5a7140eb141465d5f9992bf6581f88e54d0ff6909724e37bf2bbf7e009cfb605.jpg)

<table><tr><td>JN3</td><td>XMC connector</td><td>JN1/JN2/JN4</td><td>PCM connectors</td></tr></table>

# 4.8 cPCI-3520 Series Faceplate Layout

cPCI-350
![GbE A/B\nUSB 3.0\nDVI\nPower LED\nWDT LED\nHDD LED\nThermal LED\nReset Button\nGP LED](.cpci-3520-50m-00036-1000-10-07102024/09621881aae02103478357ee0d2cee58d4ef0fa2a8de6e377753890d21799a23.jpg)

cPCI-35
![20D\nCOM1\nUSB 2.0\nPS/2\nKB/MS\nLine-in\nLine-out\nPower LED\nWDT LED\nReset Button\nThermal LED\nGP LED\nDVI-I\nCompactor®\nSS](.cpci-3520-50m-00036-1000-10-07102024/9756d6a2828564306d511f7bc4465443baa0e2b9f14ad339692d4bc8c42856e6.jpg)

cPCI-350G
![DisplayPorts\nCOM1\nPS/2\nKB/MS\nUSB 2.0\nPower LED\nWDT LED\nThermal LED\nHDD LED\nReset Button\nGP LED\nDVI-I\nSS-](.cpci-3520-50m-00036-1000-10-07102024/bae2c24dcb5ae146438bf41cbe993958463b40747b1867d51d889fa96872974d.jpg)

Figure 4-8: cPCI-3520/D/G Faceplate Layout

cPCI-350
![20L\nLAN Connector\nCOM\nC D\nA B\nSS\nCompactPer*\nPower LED\nReset Button\nWDT LED\nThermal LED\nGP LED\nDVI-I\nHDD LED](.cpci-3520-50m-00036-1000-10-07102024/7c5c59016b97d5c237ec3fa31558717e0edc3aebbf593f3bb83a4833ce1ee883.jpg)

cPCI-350M
![COMPACTPCI®\nMulti I/O\n100-pin Connector\nPower LED\nWDT LED\nHDD LED\nReset Button\nGP LED\nDVI-I](.cpci-3520-50m-00036-1000-10-07102024/7f772db37718473360706fd0f054f0cd2156b0672d2550981912f80bf4b6b315.jpg)

cPCI-35
![20S\nXMC Slot\nCompactPCY®\nA\nB\nSS-\nLED Definitions\nsame as above\nReset Button\nGP LED\nDVI-I](.cpci-3520-50m-00036-1000-10-07102024/090ad00d5e23bc9521491c0c6afa1d193c25ff90f31b573c387b6880d9e1e9bc.jpg)

Figure 4-9: cPCI-3520L/M/S Faceplate Layout

cPCI-3520P: Same faceplate as cPCI-3520D but with XMC/PMC slot on Layer 3.

System LEDs

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="3">Power&lt;img src="images/fdc7aa14c077d9ec80ca89f99f39308fac4686bdab1e9be85df0f5b888e21e11.jpg"/&gt;</td><td rowspan="3">Green/Red</td><td>OFF</td><td>System is off</td></tr><tr><td>Red</td><td>System Power ready (PWGD)</td></tr><tr><td>Green</td><td>Post OK</td></tr><tr><td rowspan="2">WDT&lt;img src="images/e1c51d1adce61e7695a9022e436defbf83d1e823f64aa3d61825fe86f6ad3cbf.jpg"/&gt;</td><td rowspan="2">Orange</td><td>OFF</td><td>No Watchdog event</td></tr><tr><td>Blinking</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">Drive&lt;img src="images/17848b19274dea894ab5665eccb895459b9038af0bafcc473c1d1aa4b3b4808c.jpg"/&gt;</td><td rowspan="2">Blue</td><td>OFF</td><td>No CF/CFast/mSATA/SATA activity</td></tr><tr><td>Blinking</td><td>Data read/write in process for CF/CFast/ mSATA/SATA drive</td></tr><tr><td rowspan="2">Overheat&lt;img src="images/38975d96b1f06343e6f970a7501667c1108fbfc5ffaf32b7d84e81cd85a5ec88.jpg"/&gt;</td><td rowspan="2">Red</td><td>OFF</td><td>CPU  $T_{junction}$  temperature is under 100°C</td></tr><tr><td>ON</td><td>CPU  $T_{junction}$  temperature exceeds 100°C</td></tr><tr><td rowspan="2">GP(General Purpose)&lt;img src="images/3a33c10a967a0220c4039ab99f081e55bbc31c9ca6397db3c8352f4e0c2428d6.jpg"/&gt;</td><td rowspan="2">Yellow</td><td>OFF</td><td>No activity</td></tr><tr><td>ON/Blinking</td><td>Defined by user</td></tr></table>

Table 4-1: cPCI-3520 Faceplate System LED Descriptions

# 4.9 cPCI-R3P00(T) RTM Board Layout

![rJ2\nLAN1/2\nSATA2\nUSB1\nSATA4\nUSB10\nSATA3\nVGA1\nCOM4\nCOM5](.cpci-3520-50m-00036-1000-10-07102024/a75ea0909eec03c44dccd93df13479cec938b53a9965978809c2ad46edd204b0.jpg)

<table><tr><td>COM5*</td><td>RS-232/422/485 port (converted from USB)</td><td>LAN1/2</td><td>Dual Ethernet ports</td></tr><tr><td>COM4</td><td>RS-232 port (Tx, Rx only)</td><td>VGA1</td><td>VGA port</td></tr><tr><td>SATA2/3/4</td><td>SATA ports</td><td>USB1/10</td><td>USB ports</td></tr><tr><td>rJ2</td><td>CompactPCI connector</td><td></td><td></td></tr></table>

(cPCI-R3P00 is 50mm deep and cPCI-R3P00T is 80mm deep)

Figure 4-10: cPCI-R3P00(T) RTM Board Layout
![The image displays a graphic icon of a white document with a folded top-left corner. It features several grey horizontal lines resembling text and is overlaid with a large, bold red checkmark.](.cpci-3520-50m-00036-1000-10-07102024/54d66175cdf4cd8d71c6702cc02cf88769d23fce5c692a638b5eea715323ecda.jpg)

\*COM5 is incorrectly labeled COM3 on the A1 vers. PCB silkscreen.

# 4.10 cPCI-R3P00(T) RTM Faceplate

![COM4\nCOM5\nVGA\nUSBx2\nGbE x2](.cpci-3520-50m-00036-1000-10-07102024/051f5d44a58ff0cdc65db6dcc0b1a6d509a9d884b121942535727729deeeedbf.jpg)

Figure 4-11: cPCI-R3P00(T) RTM Faceplate

# 4.11 Connector Pin Assignments

# USB 2.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![4\n3\n2\n1](.cpci-3520-50m-00036-1000-10-07102024/f6dc07b665cfb6d665727d603e82219211e7d4f74ec062aa5d9a6eec8b4a8022.jpg)

Table 4-2: USB 2.0 Pin Definition

# USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.cpci-3520-50m-00036-1000-10-07102024/6f2bb2e6188d00b638b8336b51bcb4a4a6bd31d215c78730ad649543d505c9a8.jpg)

DB-15 VGA Connector

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>Red</td><td>1</td><td>2</td><td>Green</td></tr><tr><td>Blue</td><td>3</td><td>4</td><td>N.C.</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>+5V.</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>N.C.</td><td>11</td><td>12</td><td>CRTDATA</td></tr><tr><td>HSYNC</td><td>13</td><td>14</td><td>VSYNC</td></tr><tr><td>CRTCLK</td><td>15</td><td></td><td></td></tr></table>

![Technical line drawing of a 16-pin electronic device (no text or symbols)](.cpci-3520-50m-00036-1000-10-07102024/c35f5b261b0d98b03088f110f49c6957665ac2e9c95f82128c8705ee447d36b4.jpg)

Table 4-3: VGA Pin Definition

DisplayPort Connectors

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>CN_DP0_P</td><td>2</td><td>Ground</td></tr><tr><td>3</td><td>CN_DP0_N</td><td>4</td><td>CN_DP1_P</td></tr><tr><td>5</td><td>Ground</td><td>6</td><td>CN_DP1_N</td></tr><tr><td>7</td><td>CN_DP2_P</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>CN_DP2_N</td><td>10</td><td>CN_DP3_P</td></tr><tr><td>11</td><td>Ground</td><td>12</td><td>CN_DP3_N</td></tr><tr><td>13</td><td>CN_CAD-L</td><td>14</td><td>CN_CEC</td></tr><tr><td>15</td><td>CN_AUX_P</td><td>16</td><td>Ground</td></tr><tr><td>17</td><td>CN_AUX_N</td><td>18</td><td>DDP_HPD</td></tr><tr><td>19</td><td>Ground</td><td>20</td><td>P3V3</td></tr></table>

![1\n2\n19\n20](.cpci-3520-50m-00036-1000-10-07102024/4f23cb894b5d929f6f3a03877d3a66ebde37026043b6ec65a5b4318a4ee511fa.jpg)

Table 4-4: DisplayPort Pin Definition

# DVI-I Connector

![Front view of a 24-pin D-sub connector (no text or symbols visible)](.cpci-3520-50m-00036-1000-10-07102024/aae643278c2a94d145321ec19023f95a3be1a73052dcbf93be1ff113101f03e4.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2-</td><td>16</td><td>Hot Plug Detect</td></tr><tr><td>2</td><td>TMDS Data2+</td><td>17</td><td>TMDS Data0-</td></tr><tr><td>3</td><td>GND</td><td>18</td><td>TMDSData0+</td></tr><tr><td>4</td><td>NC</td><td>19</td><td>GND</td></tr><tr><td>5</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>6</td><td>DDC Clock [SCL]</td><td>21</td><td>NC</td></tr><tr><td>7</td><td>DDC Data [SDA]</td><td>22</td><td>GND</td></tr><tr><td>8</td><td>Analog vertical sync</td><td>23</td><td>TMDS Clock +</td></tr><tr><td>9</td><td>TMDS Data1-</td><td>24</td><td>TMDS Clock -</td></tr><tr><td>10</td><td>TMDS Data1+</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>GND</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>NC</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>NC</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 4-5: DVI-I Connector Pin Definition

# RJ-45 Gigabit Ethernet Connectors

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_TX0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_TX0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_TX1+</td></tr><tr><td>4</td><td>—</td><td>LAN_TX2+</td></tr><tr><td>5</td><td>—</td><td>LAN_TX2-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_TX1-</td></tr><tr><td>7</td><td>—</td><td>LAN_TX3+</td></tr><tr><td>8</td><td>—</td><td>LAN_TX3-</td></tr></table>

Table 4-6: RJ-45 GbE Pin Definitions

Speed Activity
![8\n1](.cpci-3520-50m-00036-1000-10-07102024/eea5be7d3a8d6ae471d6d10ab52df1a778e540299ba56c879d989d6da0a59494.jpg)

<table><tr><td colspan="2">Status</td><td>Speed LED (Green/Orange)</td><td>Activity LED (Yellow)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Orange</td><td>ON</td></tr><tr><td>Active</td><td>Orange</td><td>Blinking</td></tr></table>

Table 4-7: LAN LED Status Definitions

![A white document icon featuring faint horizontal gray lines and a curled top-right corner. A large, bold red checkmark is superimposed over the center of the page.](.cpci-3520-50m-00036-1000-10-07102024/a61c78e48bc54cb0b81dc1189c20c84b83becf4be8158fc1de2a63d2449350f3.jpg)
NOTE:

The cPCI-R3P00 RTM LAN LED signals are not passed through from the main board and are not displayed on the faceplate LAN LEDs.

# PS/2 Keyboard/Mouse Connector

<table><tr><td>Pin #</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+5V</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

![6\n5\n4\n3\n2 1](.cpci-3520-50m-00036-1000-10-07102024/6990ee41a9b1fe5ec46a8294ff8b13d324297c5deb6e5d961413c3acfad8da94.jpg)

Table 4-8: PS/2 Keyboard/Mouse Pin Definition

# cPCI-3520D/P Serial Ports

# COM1 Connector (DB-9)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485(+)</td></tr><tr><td>1</td><td>DCD-L</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>RXD</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>TXD</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>DTR-L</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>—</td><td>—</td></tr><tr><td>8</td><td>CTS-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/d086e14ec6012aaa4aacb0adb5c24dd3233040d3309116e0a2b77196e40bcf97.jpg)

Table 4-9: cPCI-3520D/P COM1 (DB-9) Pin Definition
![The image displays an icon featuring a white document with horizontal lines and a large red checkmark superimposed over it.](.cpci-3520-50m-00036-1000-10-07102024/dd89b06db442197c2826eb31248c9ff42ae54737826b4385a7971db9388ed672.jpg)
NOTE:

The COM mode setting for cPCI-3520D/P models is set using SW1\~SW4. See “COM1 Mode Selection Switches (SW1-SW4)” on page 49.

# COM1 Mode Selection Switches (SW1-SW4)

These switches set the cPCI-3520D/P COM1 to RS-232 full modem, RS-422, RS-485, or RS-485+ half-duplex mode. Switches SW1\~SW4 are located on the top edge of the cPCI-3520D daughter board. RS-232 full modem is set by default.

![1\n2\n3\n4\nNO](.cpci-3520-50m-00036-1000-10-07102024/8797b5f3ace8488d7f6fb41dfe33b3a80e276a10716a1aa7ea69b504b5500d8c.jpg)

SW1

![1\n2\n3\n4\nON](.cpci-3520-50m-00036-1000-10-07102024/d3892c355f76fbdb7f08cbaaf58fc31dd3563125cd9dbb40c2f116764f6488fc.jpg)

SW2

![1\nN\n3\n4\nO](.cpci-3520-50m-00036-1000-10-07102024/6695395fb42fe810bb9a76c7621758dc1e166db1e41f70872005cf7c3beb685e.jpg)

SW3

![1\nN\n3\n4\nN](.cpci-3520-50m-00036-1000-10-07102024/f79a5a67c0aa15b7f7cf12cd3bd94db8c644b4b88e0f0f10622046e345f37895.jpg)

SW4

<table><tr><td>Mode</td><td>Pin</td><td>SW1</td><td>SW2</td><td>SW3</td><td>SW4</td></tr><tr><td rowspan="4">RS-232</td><td>1</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>4</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="4">RS-422</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>2</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td rowspan="4">RS-485</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>3</td><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td rowspan="4">RS-485+</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>2</td><td>OFF</td><td>ON</td><td>ON</td><td>ON</td></tr><tr><td>3</td><td>ON</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>4</td><td>OFF</td><td>ON</td><td>ON</td><td>ON</td></tr></table>

Table 4-10: cPCI-3520D/P COM1 Mode Selection Switch Settings

![The image displays a standard icon of a document or file. It features a white rectangular shape with a folded upper-left corner. Faint gray horizontal lines run across the document to simulate text. A large, bold red checkmark is superimposed over the document, slanting upwards from the bottom left to the top right.](.cpci-3520-50m-00036-1000-10-07102024/a383f27148ab1f4315f8d19572ce944cf7b7f2e727df2e5b72ecba7fea08d821.jpg)
NOTE:

The COM mode setting for cPCI-3520D/P models must be set using the SW1\~SW4 DIP switches above. The cPCI-3520G COM1/2 Output BIOS setting is only used for cPCI-3520G models.

# cPCI-3520G Serial Ports

COM1 Connector (RJ-45)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>4</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>5</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>6</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>7</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>8</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![This image is a black-and-white technical line drawing of an RJ45 connector. It depicts a rectangular outer housing with a central shape representing the plug body. To the right of the plug, there are eight horizontal lines representing the metal contact pins. On the far right, the number '1' is aligned with the top contact line, and the number '6' is aligned with the bottom contact line, indicating the pin numbering sequence.](.cpci-3520-50m-00036-1000-10-07102024/b52f6370fd6b8eee95d2bde33d719db84200758125ca03680b169f4c20c47fcd.jpg)

Table 4-11: cPCI-3520G COM1 (RJ-45) Pin Definition
![This image depicts a stylized icon of a white document with a folded top-right corner. Faint grey horizontal lines represent text on the page, and a large red checkmark is overlaid diagonally across the document.](.cpci-3520-50m-00036-1000-10-07102024/03fe2226f9a52fc90f076986c1d46bd03bb34861dfd83518abf279b3466e1e19.jpg)
NOTE:

The COM mode settings for cPCI-3520G models are set in the BIOS: see “Super IO Configuration” on page 90.

# COM1 Connector with DB-9 Adapter

An RJ-45 to DB-9 adapter cable is provided to breakout the COM1 signals.

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>3</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>4</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>5</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>8</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/1a2b4c20ec952c4f68ff3fcb3f1796f78ba30cd61e38c1eba8983481530b3186.jpg)

Table 4-12: cPCI-3520G COM1 (DB-9 adapter) Pin Definition

![The image shows a simple icon of a white sheet of paper with a folded top-right corner. Faint horizontal lines are visible near the bottom of the page, resembling text or a list. A large, bold red checkmark is superimposed over the document, extending from the bottom left to the top right.](.cpci-3520-50m-00036-1000-10-07102024/52cc51ed36722de93ed368bf9ab1cd1c561282d770748ae42d029beeb675665a.jpg)
NOTE:

The cPCI-3520G COM1 RS-422/485 pin definitions are different from the common DB-9 pin definitions. An RS-422/485 DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions.

# RS-422/485 Adapter Dongle for cPCI-3520G

A DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions

<table><tr><td>DB-9 (Female) Signal Name</td><td>Pin #</td><td>DB-9 (Male) Signal Name</td></tr><tr><td>NC</td><td>1</td><td>TXD-</td></tr><tr><td>RXD-</td><td>2</td><td>TXD+</td></tr><tr><td>TXD-</td><td>3</td><td>RXD+</td></tr><tr><td>NC</td><td>4</td><td>RXD-</td></tr><tr><td>NC</td><td>5</td><td>NC</td></tr><tr><td>NC</td><td>6</td><td>NC</td></tr><tr><td>TXD+</td><td>7</td><td>NC</td></tr><tr><td>RXD+</td><td>8</td><td>NC</td></tr><tr><td>NC</td><td>9</td><td>NC</td></tr></table>

Table 4-13: RS-422/485 Adapter Dongle Pin Definition

COM1 with RS-422/485 Dongle (DB-9)

<table><tr><td>Pin #</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>—</td><td>—</td></tr><tr><td>6</td><td>—</td><td>—</td></tr><tr><td>7</td><td>—</td><td>—</td></tr><tr><td>8</td><td>—</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/887eab69ef3ba72249d2a2dff3c09d8795123da83eece4cf87844b4d58bfc5c7.jpg)

Table 4-14: cPCI-3520G COM1 with RS-422/485 Dongle Pin Definition

COM2 Pin Header

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>3</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>4</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>5</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>6</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>7</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>8</td><td>RI-L</td><td>—</td><td>—</td></tr><tr><td>9</td><td>Ground</td><td>—</td><td>—</td></tr><tr><td>10</td><td>NC</td><td>—</td><td>—</td></tr></table>

![1\n2\n9\n10](.cpci-3520-50m-00036-1000-10-07102024/2bb069727534393ae5c0e38700c26f3514a6d8280cd7f36fa10d3c56b75774ad.jpg)

Table 4-15: cPCI-3520G COM2 Pin Header Definition
![The image displays a white icon resembling a sheet of paper or document with its top-right corner folded down. Faint horizontal lines appear near the bottom of the page. A large, red checkmark is superimposed over the center of the document. There is no text in the image.](.cpci-3520-50m-00036-1000-10-07102024/bf12f3df12b97427f4888eac16712bffb9e1a0756b1dac1c25e9e9f84ed43609.jpg)
NOTE:

The COM mode settings for cPCI-3520G models are set in the BIOS: see “Super IO Configuration” on page 90.

# cPCI-R3P00(T) RTM Serial Ports

COM4 Connector (DB-9))

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>—</td></tr><tr><td>2</td><td>RXD</td></tr><tr><td>3</td><td>TXD</td></tr><tr><td>4</td><td>—</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>—</td></tr><tr><td>7</td><td>—</td></tr><tr><td>8</td><td>—</td></tr><tr><td>9</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/d07a63934246eb889756df46dcb387a6f92d3ab9fcedeb639d0e48f88be2a7bb.jpg)

Table 4-16: cPCI-R3P00(T) RTM COM4 Pin Definition

# COM5 Connector (DB-9)

![The image displays a graphic icon of a white document with a folded top-right corner and horizontal grey lines. A large red checkmark is superimposed over the center of the document.](.cpci-3520-50m-00036-1000-10-07102024/f0c17fa1e1062d6960f26e3d79e29265a8111ab66b91a92c5a85a1e9b35817a5.jpg)
NOTE:

The cPCI-R3P00(T) RTM COM5 RS-422/485 pin definitions are different from the common DB-9 pin definitions. An RS-422/485 DB-9 male-female adapter dongle allows compatibility with common RS-422/485 pin definitions. See “RS-422/485 Adapter Dongle for cPCI-3520G” on page 51

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD-L</td><td>—</td><td>—</td></tr><tr><td>2</td><td>RXD</td><td>RXD-</td><td>—</td></tr><tr><td>3</td><td>TXD</td><td>TXD-</td><td>TXD-</td></tr><tr><td>4</td><td>DTR-L</td><td>—</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>—</td><td>—</td></tr><tr><td>6</td><td>DSR-L</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS-L</td><td>TXD+</td><td>TXD+</td></tr><tr><td>8</td><td>CTS-L</td><td>RXD+</td><td>—</td></tr><tr><td>9</td><td>RI-L</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/5e4ced5b2f11d58bf7a076ed29737c8aaef4d6af2967433f546f8f5c44c4d8ba.jpg)

Table 4-17: cPCI-R3P00(T) RTM COM5 Pin Definition

# COM5 with RS-422/485 Dongle (DB-9)

<table><tr><td>Pin #</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>TXD-</td><td>TXD-</td></tr><tr><td>2</td><td>TXD+</td><td>TXD+</td></tr><tr><td>3</td><td>RXD+</td><td>—</td></tr><tr><td>4</td><td>RXD-</td><td>—</td></tr><tr><td>5</td><td>—</td><td>—</td></tr><tr><td>6</td><td>—</td><td>—</td></tr><tr><td>7</td><td>—</td><td>—</td></tr><tr><td>8</td><td>—</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-3520-50m-00036-1000-10-07102024/86eaca5957b8c4ffc3bb339de3b5304cfb87071aa13a5146cb5715033841db6b.jpg)

Table 4-18: cPCI-R3P00(T) RTM COM5 with RS-422/485 Dongle Pin Def’n

cPCI-3520M 100-pin I/O Connector (CN4)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>USB9_CN-N</td></tr><tr><td>3</td><td>USB9_CN-P</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB1_CN-N</td><td>6</td><td>USB1_CN-P</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>TMDS_I2C_DATA</td><td>10</td><td>TMDS_I2C_CLK</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>TMDSB_DATA2B</td></tr><tr><td>13</td><td>TMDSB_DATA2</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>TMDSB_DATA1B</td><td>16</td><td>TMDSB_DATA1</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>TMDSB_DATA0B</td></tr><tr><td>19</td><td>TMDSB_DATA0</td><td>20</td><td>GND</td></tr><tr><td>21</td><td>TMDSB_CLKB</td><td>22</td><td>TMDSB_CLK</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>P5V_DVI1</td></tr><tr><td>25</td><td>TMDSB_HPD</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>NC</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>TMDS_I2C_DATA</td></tr><tr><td>31</td><td>TMDS_I2C_CLK</td><td>32</td><td>GND</td></tr><tr><td>33</td><td>TMDSB_DATA2B</td><td>34</td><td>TMDSB_DATA2</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>TMDSB_DATA1B</td></tr><tr><td>37</td><td>TMDSB_DATA1</td><td>38</td><td>GND</td></tr><tr><td>39</td><td>TMDSB_DATA0B</td><td>40</td><td>TMDSB_DATA0</td></tr><tr><td>41</td><td>GND</td><td>42</td><td>TMDSB_CLKB</td></tr><tr><td>43</td><td>TMDSB_CLK</td><td>44</td><td>GND</td></tr><tr><td>45</td><td>P5V_DVI2</td><td>46</td><td>TMDSB_HPD</td></tr><tr><td>47</td><td>GND</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>NC</td><td>50</td><td>GND</td></tr><tr><td>51</td><td>P5V_USB_1_9</td><td>52</td><td>P5V_USB_1_9</td></tr><tr><td>53</td><td>P5V_USB_1_9</td><td>54</td><td>P5V_USB_1_9</td></tr><tr><td>55</td><td>GND</td><td>56</td><td>GND</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>P5V_KBMS</td></tr><tr><td>59</td><td>MSCLK_CN</td><td>60</td><td>MSDATA_CN</td></tr><tr><td>61</td><td>KBCLK_CN</td><td>62</td><td>KBDATA_CN</td></tr></table>

![1\n2\n9 9\n10 0](.cpci-3520-50m-00036-1000-10-07102024/1b17e0613a11e868a400eaaa13ff4bf36ab727781397f187d6c76939069f7972.jpg)

Table 4-19: cPCI-3520M 100-pin I/O Connector Pin Definition

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>63</td><td>GND</td><td>64</td><td>GND</td></tr><tr><td>65</td><td>COM1_RXD_CN</td><td>66</td><td>COM1_CTS-L_CN</td></tr><tr><td>67</td><td>GND</td><td>68</td><td>COM1_TXD_CN</td></tr><tr><td>69</td><td>COM1_RTS-L_CN</td><td>70</td><td>GND</td></tr><tr><td>71</td><td>COM1_DTR-L_CN</td><td>72</td><td>COM1_DSR-L_CN</td></tr><tr><td>73</td><td>COM1_DCD-L_CN</td><td>74</td><td>GND</td></tr><tr><td>75</td><td>COM2_RXD_CN</td><td>76</td><td>COM2_CTS-L_CN</td></tr><tr><td>77</td><td>GND</td><td>78</td><td>COM2_TXD_CN</td></tr><tr><td>79</td><td>COM2_RTS-L_CN</td><td>80</td><td>GND</td></tr><tr><td>81</td><td>COM2_DTR-L_CN</td><td>82</td><td>COM2_DSR-L_CN</td></tr><tr><td>83</td><td>COM2_DCD-L_CN</td><td>84</td><td>AGND_AU</td></tr><tr><td>85</td><td>NC</td><td>86</td><td>NC</td></tr><tr><td>87</td><td>NC</td><td>88</td><td>NC</td></tr><tr><td>89</td><td>NC</td><td>90</td><td>NC</td></tr><tr><td>91</td><td>NC</td><td>92</td><td>AGND_AU</td></tr><tr><td>93</td><td>L_IN_R</td><td>94</td><td>L_IN_L</td></tr><tr><td>95</td><td>L_IN_JD</td><td>96</td><td>AGND_AU</td></tr><tr><td>97</td><td>HP_R</td><td>98</td><td>HP_L</td></tr><tr><td>99</td><td>HP_JD</td><td>100</td><td>AGND_AU</td></tr></table>

Table 4-19: cPCI-3520M 100-pin I/O Connector Pin Definition

# Serial ATA Connectors on RTM (CN4-R, CN5-R)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX+</td></tr><tr><td>3</td><td>TX-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX-</td></tr><tr><td>6</td><td>RX+</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n7](.cpci-3520-50m-00036-1000-10-07102024/44ea0b059b49a3a2b7eac7b6cccf4bff8eb273e6579c46535764123267d3ed46.jpg)

Table 4-20: Serial ATA Connector on RTM

# SATA Conn. on cPCI-3520D/G/M Daughter Board

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>NC</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>NC</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>NC</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-3520-50m-00036-1000-10-07102024/3697156c67b6fb4f34b4f05e320bf2cc957b53c135cba3cfd083fa3f245f3c54.jpg)

Table 4-21: SATA on cPCI-3520D/G/M Daughter Board Pin Def’n

CFast Socket (on CFast carrier board)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>Ground</td><td>S1</td></tr><tr><td>SATA_TX-P</td><td>S2</td></tr><tr><td>SATA_TX-N</td><td>S3</td></tr><tr><td>Ground</td><td>S4</td></tr><tr><td>SATA_RX-N</td><td>S5</td></tr><tr><td>SATA_RX-P</td><td>S6</td></tr><tr><td>Ground</td><td>S7</td></tr><tr><td>CFast_CDI</td><td>P1</td></tr><tr><td>Ground</td><td>P2</td></tr><tr><td>NC</td><td>P3</td></tr><tr><td>NC</td><td>P4</td></tr><tr><td>NC</td><td>P5</td></tr><tr><td>NC</td><td>P6</td></tr><tr><td>Ground</td><td>P7</td></tr><tr><td>CFast_LED1</td><td>P8</td></tr><tr><td>CFast_LED2</td><td>P9</td></tr><tr><td>NC</td><td>P10</td></tr><tr><td>NC</td><td>P11</td></tr><tr><td>NC</td><td>P12</td></tr><tr><td>P3V3</td><td>P13</td></tr><tr><td>P3V3</td><td>P14</td></tr><tr><td>Ground</td><td>P15</td></tr><tr><td>Ground</td><td>P16</td></tr><tr><td>CFast_CDO</td><td>P17</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.cpci-3520-50m-00036-1000-10-07102024/beced6e09b466ee358a8e5f7c6cef64616e5efbc669aebc2b699f2a48d43fae4.jpg)

![24\nP1\nS1](.cpci-3520-50m-00036-1000-10-07102024/0807a00d997ef8abee16415506ec7e70fbef3f07a252e2cd53e4fc99398c6958.jpg)

Table 4-22: CFast Socket Pin Definition

Layer-2 Daughter Board Connector (CN1)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>USB2-N</td><td>1</td><td>2</td><td>-12V</td></tr><tr><td>USB2-P</td><td>3</td><td>4</td><td>+12</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>USB3-N</td><td>7</td><td>8</td><td>HDA_SDIN0</td></tr><tr><td>USB3-P</td><td>9</td><td>10</td><td>HDA_R_SDOUT</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>SATA_ICH_RX-N0</td><td>13</td><td>14</td><td>HDA_R_SYNC</td></tr><tr><td>SATA_ICH_RX-P0</td><td>15</td><td>16</td><td>HDA_R_BIT_CLK</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>SATA_TX-P0</td><td>19</td><td>20</td><td>CK_L2_PCIE1-P</td></tr><tr><td>SATA_TX-N0</td><td>21</td><td>22</td><td>CK_L2_PCIE1-N</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCIE_TXN5</td><td>25</td><td>26</td><td>CK_L2_PCIE2-P</td></tr><tr><td>PCIE_TXP5</td><td>27</td><td>28</td><td>CK_L2_PCIE2-N</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCIE_RXN5</td><td>31</td><td>32</td><td>HDA_R_RST-L</td></tr><tr><td>PCIE_RXP5</td><td>33</td><td>34</td><td>SPKR</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>L2_PCIE_RST-L</td></tr><tr><td>PCIE_RXN4</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>PCIE_RXP4</td><td>39</td><td>40</td><td>USB_2_3_OC-L</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>COM1_DCD-L</td></tr><tr><td>PCIE_TXN4</td><td>43</td><td>44</td><td>COM1_RI-L</td></tr><tr><td>PCIE_TXP4</td><td>45</td><td>46</td><td>COM1_CTS-L</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>COM1_DTR-L</td></tr><tr><td>MSCLK</td><td>49</td><td>50</td><td>COM1_RTS-L</td></tr><tr><td>MSDATA</td><td>51</td><td>52</td><td>COM1_DSR-L</td></tr><tr><td>KBCLK</td><td>53</td><td>54</td><td>COM1_SOUT</td></tr><tr><td>KBCDATA</td><td>55</td><td>56</td><td>COM1_SIN</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>+3.3V</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>+3.3V</td></tr></table>

![2\n1\n60\n59](.cpci-3520-50m-00036-1000-10-07102024/417d6609699173148175fa462ef3aea24d22aa67e75a6d73001fac6680c349fc.jpg)

Table 4-23: Layer-2 Daughter Board Connector Pin Definition

Storage Daughter Board Connector (CN2)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>PCH_SPKR</td><td>1</td><td>2</td><td>CLK33_TPM</td></tr><tr><td>SIO_SPKR</td><td>3</td><td>4</td><td>LPC_FRAME-L</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>TPM_RST-L</td></tr><tr><td>CN_VCC_RTC</td><td>7</td><td>8</td><td>LPC_AD3</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>LPC_AD2</td></tr><tr><td>NC</td><td>11</td><td>12</td><td>LPC_AD1</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>LPC_AD0</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>TPM_LPCPD</td></tr><tr><td>NC</td><td>17</td><td>18</td><td>PCH_SERIRQ</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>TPM_CLKRUN</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>TPM_GPIO</td></tr><tr><td>NC</td><td>23</td><td>24</td><td>NC</td></tr><tr><td>NC</td><td>25</td><td>26</td><td>NC</td></tr><tr><td>NC</td><td>27</td><td>28</td><td>NC</td></tr><tr><td>NC</td><td>29</td><td>30</td><td>NC</td></tr><tr><td>NC</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>NC</td><td>33</td><td>34</td><td>NC</td></tr><tr><td>NC</td><td>35</td><td>36</td><td>NC</td></tr><tr><td>GND</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>SATA_PCH_RX-N0</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>SATA_PCH_RX-P0</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>GND</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>SATA_PCH_TX-N0</td><td>45</td><td>46</td><td>NC</td></tr><tr><td>SATA_PCH_TX-P0</td><td>47</td><td>48</td><td>NC</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>NC</td></tr><tr><td>CFast_CDI</td><td>51</td><td>52</td><td>NC</td></tr><tr><td>CFast_CDO</td><td>53</td><td>54</td><td>NC</td></tr><tr><td>GND</td><td>55</td><td>56</td><td>NC</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>P3V3</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>P3V3</td></tr></table>

![2\n1\n60\n59](.cpci-3520-50m-00036-1000-10-07102024/36ea7ca7b9fb761294b749b6e5c2c7f3071ead5d2d8a2b0ab0787ab3f5d2f673.jpg)

Table 4-24: Storage Daughter Board Connector Pin Definition

cPCI-3520G Daughter Board Connector (CN3)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>NC</td><td>1</td><td>2</td><td>RS232_COM2_SEL-L</td></tr><tr><td>NC</td><td>3</td><td>4</td><td>COM2_DCD-L</td></tr><tr><td>NC</td><td>5</td><td>6</td><td>COM2_RI-L</td></tr><tr><td>NC</td><td>7</td><td>8</td><td>COM2_CTS-L</td></tr><tr><td>NC</td><td>9</td><td>10</td><td>COM2_DTR-L</td></tr><tr><td>NC</td><td>11</td><td>12</td><td>COM2_RTS-L</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>COM2_DSR-L</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>COM2_SOUT</td></tr><tr><td>NC</td><td>17</td><td>18</td><td>COM2_SIN</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>NC</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>NC</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCH_DDPD_AUXN</td><td>25</td><td>26</td><td>PCH_DDPC_AUXN</td></tr><tr><td>PCH_DDPD_AUXP</td><td>27</td><td>28</td><td>PCH_DDPC_AUXP</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCH_DDPD_0N</td><td>31</td><td>32</td><td>PCH_DDPC_0N</td></tr><tr><td>PCH_DDPD_0P</td><td>33</td><td>34</td><td>PCH_DDPC_0P</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>GND</td></tr><tr><td>PCH_DDPD_1N</td><td>37</td><td>38</td><td>PCH_DDPC_1N</td></tr><tr><td>PCH_DDPD_1P</td><td>39</td><td>40</td><td>PCH_DDPC_1P</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>GND</td></tr><tr><td>PCH_DDPD_2N</td><td>43</td><td>44</td><td>PCH_DDPC_2N</td></tr><tr><td>PCH_DDPD_2P</td><td>45</td><td>46</td><td>PCH_DDPC_2P</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>GND</td></tr><tr><td>PCH_DDPD_3N</td><td>49</td><td>50</td><td>PCH_DDPC_3N</td></tr><tr><td>PCH_DDPD_3P</td><td>51</td><td>52</td><td>PCH_DDPC_3P</td></tr><tr><td>GND</td><td>53</td><td>54</td><td>GND</td></tr><tr><td>DDPD_CTRLCLK</td><td>55</td><td>56</td><td>DDPC_CTRLCLK</td></tr><tr><td>DDPD_CTRLDATA</td><td>57</td><td>58</td><td>DDPC_CTRLDATA</td></tr><tr><td>DDPD_HPD</td><td>59</td><td>60</td><td>DDPC_HPD</td></tr></table>

![2\n1\n60\n59](.cpci-3520-50m-00036-1000-10-07102024/786657a3bcaead2aef33b33c0de6c44d1aac1a3c2036fc881c455ef6a97644ca.jpg)

Table 4-25: cPCI-3520G Daughter Board Connector Pin Definition

# PMC/XMC Daughter Board Connector

(on cPCI-3520D/G daughter board)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>NC</td><td>1</td><td>2</td><td>-12V</td></tr><tr><td>NC</td><td>3</td><td>4</td><td>+12V</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>NC</td><td>7</td><td>8</td><td>NC</td></tr><tr><td>NC</td><td>9</td><td>10</td><td>NC</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>NC</td><td>13</td><td>14</td><td>NC</td></tr><tr><td>NC</td><td>15</td><td>16</td><td>NC</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>NC</td><td>19</td><td>20</td><td>CK_PCIE1_P</td></tr><tr><td>NC</td><td>21</td><td>22</td><td>CK_PCIE1_N</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PCIE_TXN2</td><td>25</td><td>26</td><td>CK_PCIE2_P</td></tr><tr><td>PCIE_TXP2</td><td>27</td><td>28</td><td>CK_PCIE2_N</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>PCIE_R_RXN2</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>PCIE_R_RXP2</td><td>33</td><td>34</td><td>NC</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>PCIE_RST#</td></tr><tr><td>PCIE_R_RXN1</td><td>37</td><td>38</td><td>NC</td></tr><tr><td>PCIE_R_RXP1</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>PCIE_TXN4</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>PCIE_TXP4</td><td>45</td><td>46</td><td>NC</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>NC</td></tr><tr><td>NC</td><td>49</td><td>50</td><td>NC</td></tr><tr><td>NC</td><td>51</td><td>52</td><td>NC</td></tr><tr><td>NC</td><td>53</td><td>54</td><td>NC</td></tr><tr><td>NC</td><td>55</td><td>56</td><td>NC</td></tr><tr><td>+5V</td><td>57</td><td>58</td><td>+3.3V</td></tr><tr><td>+5V</td><td>59</td><td>60</td><td>+3.3V</td></tr></table>

![2\n1\n60\n59](.cpci-3520-50m-00036-1000-10-07102024/58f6269cac600de45b28f5d6b537884643d99e105f4e4053341af784b017928a.jpg)

Table 4-26: PMC/XMC Daughter Board Connector Pin Definition

# PMC Connector on PMC/XMC Daughter Board (JN1/2)

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td></tr><tr><td>1</td><td>PMC_TCK</td><td>P12V</td></tr><tr><td>2</td><td>N12V</td><td>PMC_TRST-L</td></tr><tr><td>3</td><td>GND</td><td>PMC_TMS</td></tr><tr><td>4</td><td>PCIX_INTA-L</td><td>NC (PMC_TDO)</td></tr><tr><td>5</td><td>PCIX_INTB-L</td><td>PMC_TDI</td></tr><tr><td>6</td><td>PCIX_INTC-L</td><td>GND</td></tr><tr><td>7</td><td>PMC_MOD-L1</td><td>GND</td></tr><tr><td>8</td><td>P5V</td><td>NC</td></tr><tr><td>9</td><td>PCIX_INTD-L</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td></tr><tr><td>11</td><td>GND</td><td>PMC_MOD-L2</td></tr><tr><td>12</td><td>P3V3_PMCAUX</td><td>P3V3</td></tr><tr><td>13</td><td>CLK66_PCIX_PMC</td><td>PMC_RST-L</td></tr><tr><td>14</td><td>GND</td><td>PMC_MOD-L3</td></tr><tr><td>15</td><td>GND</td><td>P3V3</td></tr><tr><td>16</td><td>PCIX_GNT-L0</td><td>PMC_MOD-L4</td></tr><tr><td>17</td><td>PCIX_REQ-L0</td><td>PMC_PME-L</td></tr><tr><td>18</td><td>P5V</td><td>GND</td></tr><tr><td>19</td><td>PMC_VIO</td><td>PCIX_AD30</td></tr><tr><td>20</td><td>PCIX_AD31</td><td>PCIX_AD29</td></tr><tr><td>21</td><td>PCIX_AD28</td><td>GND</td></tr><tr><td>22</td><td>PCIX_AD27</td><td>PCIX_AD26</td></tr><tr><td>23</td><td>PCIX_AD25</td><td>PCIX_AD24</td></tr><tr><td>24</td><td>GND</td><td>PCIX_AD23</td></tr><tr><td>25</td><td>GND</td><td>PMC_IDSEL</td></tr><tr><td>26</td><td>PCIX_CBE-L3</td><td>PCIX_AD23</td></tr><tr><td>27</td><td>PCIX_AD22</td><td>P3V3</td></tr><tr><td>28</td><td>PCIX_AD21</td><td>PCIX_AD20</td></tr><tr><td>29</td><td>PCIX_AD19</td><td>PCIX_AD18</td></tr><tr><td>30</td><td>P5V</td><td>GND</td></tr><tr><td>31</td><td>PCIX_FRAME-L</td><td>PCIX_AD16</td></tr><tr><td>32</td><td>PCIX_AD17</td><td>PCIX_CBE-L2</td></tr></table>

![64\n63\n2\n1](.cpci-3520-50m-00036-1000-10-07102024/7cb52f906857d4cbd747eb571512339f7f9e0d328515803bf9087a10111c563b.jpg)

Table 4-27: PMC Connector Pin Definitions

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td></tr><tr><td>33</td><td>PCIX_FRAME-L</td><td>GND</td></tr><tr><td>34</td><td>GND</td><td>NC</td></tr><tr><td>35</td><td>GND</td><td>PCIX_TRDY-L</td></tr><tr><td>36</td><td>PCIX_IRDY-L</td><td>P3V3</td></tr><tr><td>37</td><td>PCIX_DEVSEL-L</td><td>GND</td></tr><tr><td>38</td><td>P5V</td><td>PCIX_STOP-L</td></tr><tr><td>39</td><td>PCIX_PCIXCAP</td><td>PCIX_PERR-L</td></tr><tr><td>40</td><td>PCIX_LOCK-L</td><td>GND</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td></tr><tr><td>42</td><td>NC</td><td>PCIX_SERR-L</td></tr><tr><td>43</td><td>PCIX_PAR</td><td>PCIX_CBE-L1</td></tr><tr><td>44</td><td>GND</td><td>GND</td></tr><tr><td>45</td><td>PMC_VIO</td><td>PCIX_AD14</td></tr><tr><td>46</td><td>PCIX_AD15</td><td>PCIX_AD13</td></tr><tr><td>47</td><td>PCIX_AD12</td><td>PCIX_M66EN</td></tr><tr><td>48</td><td>PCIX_AD11</td><td>PCIX_AD10</td></tr><tr><td>49</td><td>PCIX_AD9</td><td>PCIX_AD8</td></tr><tr><td>50</td><td>P5V</td><td>P3V3</td></tr><tr><td>51</td><td>GND</td><td>PCIX_AD7</td></tr><tr><td>52</td><td>PCIX_CBE-L0</td><td>NC</td></tr><tr><td>53</td><td>PCIX_AD6</td><td>P3V3</td></tr><tr><td>54</td><td>PCIX_AD5</td><td>NC</td></tr><tr><td>55</td><td>PCIX_AD4</td><td>NC</td></tr><tr><td>56</td><td>GND</td><td>GND</td></tr><tr><td>57</td><td>PMC_VIO</td><td>NC</td></tr><tr><td>58</td><td>PCIX_AD3</td><td>NC</td></tr><tr><td>59</td><td>PCIX_AD2</td><td>GND</td></tr><tr><td>60</td><td>PCIX_AD1</td><td>NC</td></tr><tr><td>61</td><td>PCIX_AD0</td><td>PCIX_ACK64-L</td></tr><tr><td>62</td><td>P5V</td><td>P3V3</td></tr><tr><td>63</td><td>GND</td><td>GND</td></tr><tr><td>64</td><td>PCIX_REQ64-L</td><td>NC</td></tr></table>

Table 4-27: PMC Connector Pin Definitions (cont’d)

XMC Connector on PMC/XMC Daughter Board (JN3)
![F1\nA1\nF19\nA19](.cpci-3520-50m-00036-1000-10-07102024/0fad979fa91179ba36d327ad02ece8036c5f8650ba53d2199e11a72452861ace.jpg)

<table><tr><td>Pin#</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>RXP</td><td>RXN</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>PCIE_RST-L</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>5</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>+12V</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>-12V</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>TXP</td><td>TXN</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>13</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>15</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>17</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>19</td><td>CK-P</td><td>CK-N</td><td>Not used</td><td>Not used</td><td>Not used</td><td>Not used</td></tr></table>

Table 4-28: XMC Connector Pin Definition

GPIO MMIO Addresses

<table><tr><td>Pin # on J2</td><td>Chipset Signal</td><td>DW0 Register Address</td><td>DW1 Register Address</td></tr><tr><td>GPIO0</td><td>GPP_E0</td><td>0xFD6B0900</td><td>0xFD6B0904</td></tr><tr><td>GPIO1</td><td>GPP_E1</td><td>0xFD6B0910</td><td>0xFD6B0914</td></tr><tr><td>GPIO2</td><td>GPP_E2</td><td>0xFD6B0920</td><td>0xFD6B0924</td></tr></table>

Table 4-29: GPIO MMIO Addresses

CompactPCI J1 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>CPCI_AD1</td><td>+5V</td><td>CPCI_VIO</td><td>CPCI_AD0</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>CPCI_AD4</td><td>CPCI_AD3</td><td>+5V</td><td>CPCI_AD2</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>CPCI_AD7</td><td>GND</td><td>+3.3V</td><td>CPCI_AD6</td><td>CPCI_AD5</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>CPCI_AD9</td><td>CPCI_AD8</td><td>CPCI_M66EN</td><td>CPCI_CBE-L0</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_AD12</td><td>GND</td><td>VIO</td><td>CPCI_AD11</td><td>CPCI_AD10</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>CPCI_AD15</td><td>CPCI_AD14</td><td>GND</td><td>CPCI_AD13</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>CPCI_SERR-L</td><td>GND</td><td>+3.3V</td><td>CPCI_PAR</td><td>CPCI_CBE-L1</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>NC</td><td>NC</td><td>GND</td><td>CPCI_PERR-L</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>CPCI_DEVSEL-L</td><td>CPCI_PCIXCAP</td><td>VIO</td><td>CPCI_STOP-L</td><td>CPCI_LOCK-L</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>CPCI_FRAME-L</td><td>CPCI_IRDY-L</td><td>NC</td><td>CPCI_TRDY-L</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>CPCI_AD18</td><td>CPCI_AD17</td><td>CPCI_AD16</td><td>GND</td><td>CPCI_CBE-L2</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>CPCI_AD21</td><td>GND</td><td>+3.3V</td><td>CPCI_AD20</td><td>CPCI_AD19</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CPCI_CBE-L3</td><td>NC</td><td>CPCI_AD23</td><td>GND</td><td>CPCI_AD22</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>CPCI_AD26</td><td>GND</td><td>VIO</td><td>CPCI_AD25</td><td>CPCI_AD24</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CPCI_AD30</td><td>CPCI_AD29</td><td>CPCI_AD28</td><td>GND</td><td>CPCI_AD27</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CPCI_REQ-L0</td><td>GND</td><td>+3.3V</td><td>CPCI_CLK0</td><td>CPCI_AD31</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_RESET-L</td><td>GND</td><td>CPCI_GNT-L0</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>CPCI_HEALTHY-L</td><td>VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_IRQA-L</td><td>CPCI_IRQB-L</td><td>CPCI_IRQC-L</td><td>+5V</td><td>CPCI_IRQD-L</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>cPCI_TCK-L</td><td>+5V</td><td>cPCI_TMS-L</td><td>NC</td><td>cPCI_TDI-L</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>NC</td><td>cPCI_TRST-L</td><td>+12V</td><td>+5V</td><td>GND</td></tr></table>

Table 4-30: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PCI_CLK6</td><td>GND</td><td>LAN4_MDI1_P</td><td>LAN3_MDI3_P</td><td>LAN3_MDI1_P</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PCI_CLK5</td><td>GND</td><td>LAN4_MDI1_N</td><td>LAN3_MDI3_N</td><td>LAN3_MDI1_N</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>LAN4_MDI0_P</td><td>LAN3_MDI2_P</td><td>LAN3_MDI0_P</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LAN4_MDI3_P</td><td>LAN4_MDI2_P</td><td>LAN4_MDI0_N</td><td>LAN3_MDI2_N</td><td>LAN3_MDI0_N</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LAN4_MDI3_N</td><td>LAN4_MDI2_N</td><td>J2_RSTJ</td><td>CPCI_REQ_L6</td><td>CPCI_GNT_L6</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PCIE4_CLK8_N</td><td>PCIE2_CLK6_P</td><td>DEGJ</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PCIE4_CLK8_P</td><td>PCIE2_CLK6_N</td><td>FALJ</td><td>CPCI_REQ_L5</td><td>CPCI_GNT_L5</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>PCIE3_CLK7_N</td><td>PCIE1_CLK5_P</td><td>PCIE_RST-L</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>PCIE3_CLK7_P</td><td>PCIE1_CLK5_N</td><td>GPIO2</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>PCIE4_RXP</td><td>GPIO0</td><td>GPIO1</td><td>VGA_VSY</td><td>SATA_RX-P1</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>PCIE4_RXN</td><td>PCIE4_TXP</td><td>COM3_TX</td><td>SATA_TX-P1</td><td>SATA_RX-N1</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>PCIE3_RXP</td><td>PCIE4_TXN</td><td>COM3_RX</td><td>SATA_TX-N1</td><td>SATA_RX-P2</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>PCIE3_RXN</td><td>PCIE3_TXP</td><td>USB 2_2P</td><td>SATA_TX-P2</td><td>SATA_RX-N2</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>PCIE2_RXP</td><td>PCIE3_TXN</td><td>USB 2_2N</td><td>SATA_TX-N2</td><td>SATA_RX-P3</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>PCIE2_RXN</td><td>PCIE2_TXP</td><td>USB 2_3P</td><td>SATA_TX-P3</td><td>SATA_RX-N3</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>PCIE1_RXP</td><td>PCIE2_TXN</td><td>USB 2_3N</td><td>SATA_TX-N3</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>PCIE1_RXN</td><td>PCIE1_TXP</td><td>USB 2_4P</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>VIO</td><td>PCIE1_TXN</td><td>USB 2_4N</td><td>USB 2_OC1</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr></table>

Table 4-31: CompactPCI J2 Connector Pin Definition

![Ethernet port\nVGA\nSerial ATA\nPCI-Express\nSerial port\nUSB port](.cpci-3520-50m-00036-1000-10-07102024/e8c41f779487be41ad36593b13280a0a1118718bdac1075c9b5f9b93432b47ea.jpg)

cPCI-R3P00 rJ2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>NC</td><td>GND</td><td>2_ETH_B+</td><td>1_ETH_D+</td><td>1_ETH_B+</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>GND</td><td>2_ETH_B-</td><td>1_ETH_D-</td><td>1_ETH_B-</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>2_ETH_A+</td><td>1_ETH_C+</td><td>1_ETH_A+</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>2_ETH_D+</td><td>2_ETH_C+</td><td>2_ETH_A-</td><td>1_ETH_C-</td><td>1_ETH_A-</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>2_ETH_D-</td><td>2_ETH_C-</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>VGA_VSY</td><td>2_SATA_RX+</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>NC</td><td>NC</td><td>COM4_TX</td><td>2_SATA_TX+</td><td>2_SATA_RX-</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>NC</td><td>NC</td><td>COM4_RX</td><td>2_SATA_TX-</td><td>3_SATA_RX+</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>NC</td><td>NC</td><td>0_USB+</td><td>3_SATA_TX+</td><td>3_SATA_RX-</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>NC</td><td>NC</td><td>0_USB-</td><td>3_SATA_TX-</td><td>4_SATA_RX+</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>NC</td><td>NC</td><td>1_USB+</td><td>4_SATA_TX+</td><td>4_SATA_RX-</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>NC</td><td>NC</td><td>1_USB-</td><td>4_SATA_TX-</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>10_USB+</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>NC</td><td>10_USB-</td><td>USB1_10_OC</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr></table>

Table 4-32: cPCI-R3P00 rJ2 Connector Pin Definition

![| Port Type       | Color  |\n| --------------- | ------ |\n| Ethernet port   | Cyan   |\n| VGA             | Orange |\n| Serial ATA      | Pink   |\n| PCI-Express     | Green  |\n| Serial port     | Yellow |\n| USB port        | Purple |](.cpci-3520-50m-00036-1000-10-07102024/672344b3258477c4db139dc12fea88a2c51f996ab34a31b970588fab363e1c7e.jpg)

cPCI-R3P00T rJ2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>4PE_CLK-</td><td>2_PE_CLK+</td><td>NC</td><td>GND</td><td>+5V</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>4PE_CLK+</td><td>2_PE_CLK-</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>3PE_CLK+</td><td>1_PE_CLK+</td><td>4_PE_CLKE#</td><td>DDC_DAT</td><td>+5V</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>3PE_CLK-</td><td>1_PE_CLK-</td><td>3_PE_CLKE#</td><td>VGA_HSY</td><td>DDC_CLK</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>4PE_RX00+</td><td>1_PE_CLKE#</td><td>2_PE_CLKE#</td><td>VGA_VSY</td><td>2_SATA_RX+</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>4PE_RX00-</td><td>4PE_TX00+</td><td>COM4_TX</td><td>2_SATA_TX+</td><td>2_SATA_RX-</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>3PE_RX00+</td><td>4PE_TX00-</td><td>COM4_RX</td><td>2_SATA_TX-</td><td>3_SATA_RX+</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>3PE_RX00-</td><td>3PE_TX00+</td><td>0_USB+</td><td>3_SATA_TX+</td><td>3_SATA_RX-</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>2PE_RX00+</td><td>3PE_TX00-</td><td>0_USB-</td><td>3_SATA_TX-</td><td>4_SATA_RX+</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>2PE_RX00-</td><td>2PE_TX00+</td><td>1_USB+</td><td>4_SATA_TX+</td><td>4_SATA_RX-</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>1PE_RX00+</td><td>2PE_TX00-</td><td>1_USB-</td><td>4_SATA_TX-</td><td>RGB_RED</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>1PE_RX00-</td><td>1PE_TX00+</td><td>10_USB+</td><td>RS232_COM5_SEL-L</td><td>RGB_GREEN</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>1PE_TX00-</td><td>10_USB-</td><td>USB1_10_OC</td><td>RGB_BLUE</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr></table>

Table 4-33: cPCI-R3P00T rJ2 Connector Pin Definition

![| Category       | Value |\n| -------------- | ----- |\n| VGA            | 10    |\n| Serial ATA     | 8     |\n| PCI-Express    | 7     |\n| Serial port    | 6     |\n| USB port       | 5     |](.cpci-3520-50m-00036-1000-10-07102024/2a0529f682ebf7cb55f0fabfd7b1751da92a3775788e545774aca97171ae16fc.jpg)

# 4.12 Jumper Settings

# XMC VPWR Select Jumper (JPX1)

This jumper is located on the PMC/XMC daughter board near JN1/2 and selects the XMC VPWR setting. 5V is set by default.

<table><tr><td>Mode</td><td>Connection</td><td>JPX1</td></tr><tr><td>+5V (Default)</td><td>1 – 2</td><td>&lt;img src="images/a8f6361201bef32b69640b39d9c45cb2cda61b65bb75e3f94b99275182171a4f.jpg"/&gt;</td></tr><tr><td>+12V</td><td>2 – 3</td><td>&lt;img src="images/5109f6b71ca888c8d510221793e4765f1b604b9e097f3159a57c19335d40e01e.jpg"/&gt;</td></tr></table>

Table 4-34: XMC VPWR Select Jumper Settings

# PMC V(I/O) Select Jumper (JPX2)

This jumper is located on the PMC/XMC daughter board near JN1/2 and selects the PMC V(I/O) setting. 3.3V is set by default.

<table><tr><td>Mode</td><td>Connection</td><td>JPX2</td></tr><tr><td>+5V</td><td>1 – 2</td><td>&lt;img src="images/93eb6b15ee0f8f4ed46db1062bbf39cd697368b45147d383454433f677c5794b.jpg"/&gt;</td></tr><tr><td>+3.3V (Default)</td><td>2 – 3</td><td>&lt;img src="images/82ea8c8ae35e56291baaf23ce75dba455f89de23bb9bbdf3f6e314cfe45e55d0.jpg"/&gt;</td></tr></table>

Table 4-35: PMC V(I/O) Select Jumper Settings

# 5 Getting Started

This chapter describes the following installation procedures for the cPCI-3520 and rear transition module:

 CPU and Heatsink
 2.5" SATA storage drive
 CFast card
 PCI Mezzanine Card
 Processor blade installation to chassis
 RTM installation to chassis

# 5.1 CPU and Heatsink

The cPCI-3520 Series come with CPU and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance.

# 5.2 SATA Drive Installation

The cPCI-3520D/G/L/M/P 2/3-slot versions provide space to install a slim type 2.5" Serial-ATA storage drive.

# Installing a SATA Drive - cPCI-3520D/G/L/M/P

1. A 2.5" SATA drive can be assembled in the location marked as below.

![Close-up of an electronic circuit board with a green PCB and a red rectangular annotation highlighting a component (no readable text or symbols)](.cpci-3520-50m-00036-1000-10-07102024/0a70b83036aef60d0bec18ee04343b855e05e523229412e18975d5714fdd3494.jpg)

2. 2.Prepare a 2.5" SATA drive and locate the brackets and screws in the accessory kit.

![Exterior view of a silver ADLINK SSD device with metal hardware and screws, placed on a plain surface (no text or symbols visible on the device itself)](.cpci-3520-50m-00036-1000-10-07102024/9a0971cbe10f5013729a8a09226722e3fee351eba4659d0ab1bc6c4d9c56cc4c.jpg)

3. Screw the brackets to the 2.5" SATA drive.

![ADLINK\nSATA SSD](.cpci-3520-50m-00036-1000-10-07102024/65f33d3fe8b8f3fb76a8dce27d3248e9516169bf3bfc5294fb5d351c125ab39c.jpg)

4. Align the drive assembly with the cPCI-3520 and insert it into the onboard SATA connector until it is properly seated.

![SATA SSD\nADLINK](.cpci-3520-50m-00036-1000-10-07102024/597050de1ca1447ad96807665d79955f0de7bc04eabb186e1a685dcca0a64f8a.jpg)

5. Secure the hard drive assembly to the cPCI-3520 with four M2.5 screws provided.

![S55D\nSATA\nADLINK\nGP\n1.043081007\n2.043081007\n2.043081007\n2.043081007\n2.043081007\n2.043081007\n2.043081007\n2.043081007\n2.043081007\n2.046](.cpci-3520-50m-00036-1000-10-07102024/2b2e1af8611765ccdbf93b2210160ecf22720c2dc2f830f3e91826d64ffa1bdf.jpg)

# 5.3 Installing a CFast Card

To install a CFast card, locate the CFast connector on the CFAST storage board and insert the card until it is properly seated.

![Close-up of an electronic circuit board with a highlighted component (no readable text or symbols)](.cpci-3520-50m-00036-1000-10-07102024/9031f55c94dca7f4353bf450bf5165477db6619490a864cc640db71806f51780.jpg)

# 5.4 Installing the cPCI-3520 to the Chassis

The cPCI-3520 may be installed in a system or peripheral slot of a 3U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.
2. Remove the blank face cover from the selected slot, if necessary.
3. Press down on the release catches of the cPCI-3520 ejector handles.
4. Remove the black plastic caps securing the mounting screws to the faceplate.
5. Align the module’s top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board’s connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.
6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module faceplate.
7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

# 5.5 RTM Installation - cPCI-R3P00(T)

The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-3520 Series and related RTMs, make sure the RTM is the correct matching model.

![The image displays a white document icon featuring faint gray horizontal lines. A large, bold red checkmark is overlaid on the document, running diagonally from the bottom left to the top right.](.cpci-3520-50m-00036-1000-10-07102024/6799a3ec913e56f53386b28773aa7166b2e3d67de80f734739cafc0937154456.jpg)
NOTE:

You must install the correct RTM to enable functions (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs.

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# 6 Driver Installation

The cPCI-3520 drivers are available from the ADLINK website (https://www.adlinktech.com/Products/CompactPCI/3UCompact PCI2\_0Blades/cPCI-3520\_Series). ADLINK provides validated drivers for Windows 10 64-bit. We recommend using these drivers to ensure compatibility.

# 6.1 cPCI-3520 Drivers

The following describes the cPCI-3520 driver installation procedures for Windows 10 64-bit. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.

1. Install the chipset driver by extracting and running the program in ...\Chipset\Chipset\_10.1.18121.8164.zip.
2. Install the graphics driver and utilities by extracting and running the program in ...\Graphics\igfx\_win10\_100.9466.zip.
3. Install the Management Engine (ME) driver and utilities by extracting and running the program in ...\ME\Intel Management Engine Interface 12.0.34.1425.zip.
4. Install the Ethernet Controller driver by extracting and running the program in …\Network\PROWinx64.zip.

# 6.2 USB-to-Serial Converter Driver (RTM)

The COM5 serial port on the cPCI-R3P00(T) is converted from the USB3 port by a USB-to-serial converter (see " cPCI-R3P00 RTM” on page 17). To install the driver for the converter, follow the procedure below.

1. Extract the contents of …\COM\CDM 2.08.28 WHQL Certified-x64.zip.
2. Open the Device Manager and go to Other Devices. You will see a "question mark" next to FT2332R USB UART. R-click on FT2332R USB UART and choose "Update Driver Software…".

![Device Manager\nFile Action View Help\n3510-PC\nComputer\nDisk drives\nDisplay adapters\nHuman Interface Devices\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nOther devices\nFT232P HDUART\nPortable D\nPorts (COI)\nProcessors\nSound, video\nSystem de\nUniversal S\nUpdate Driver Software...\nDisable\nUninstall\nScan for hardware changes\nProperties\nLaunches the Update Driver Software Wizard for the selected device.](.cpci-3520-50m-00036-1000-10-07102024/475e1e4d1dabee12705093cd042dfbfb291e3d8c2e97cd6e895c8a881f6a3bb0.jpg)

# 3. Click “Browse my computer for driver software”.

![Update Driver Software - FT232R USB UART\nHow do you want to search for driver software?\n→ Search automatically for updated driver software\nWindows will search your computer and the Internet for the latest driver software for your device, unless you've disabled this feature in your device installation settings.\n→ Browse my computer for driver software\nLocate and install driver software manually.\nCancel](.cpci-3520-50m-00036-1000-10-07102024/2834ceab80daf65037109be95e2153b77102261ee6bf3bce5863958404706bc3.jpg)

# 4. Navigate to the folder where you extracted the contents of the zip file and click “OK”. Click “Next” to install the driver

![Device Manager\nFile  Action  View  Help\nBrowse For Folder\nSelect the folder that contains drivers for your hardware.\nDesktop\nLibraries\n3510\nComputer\nNetwork\n3510 pic\ncPCI-3510 driver\nCDM 2.08.28 WHQL Certified-x64\nCDM v2.08.28 Certified\nFolder: CDM 2.08.28 WHQL Certified-x64\nOK  Cancel\nNext  Cancel\n3510\nUpdate Driver So\nBrowse for drive\nSearch for driver soft\nC:\Users\3510\Desk\nInclude subfolder\nLet me pick\nThis list will show installed driver software compatible with the device, and all driver\nsoftware in the same category as the device.](.cpci-3520-50m-00036-1000-10-07102024/386a620657fd8e9df811dc7394eda1c13e4a02f8708a200689cbbca22d898bb6.jpg)

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# 7 BIOS Setup Utility

The following chapter describes basic navigation for the AMI EFI BIOS setup utility.

# 7.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt: &lt; Press DEL to run Setup &gt;
3. After you press the &lt; Delete &gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![The image displays a white document icon featuring a folded top-left corner and faint horizontal grey lines. A large, bold red checkmark is superimposed over the center of the document.](.cpci-3520-50m-00036-1000-10-07102024/da8e4cdc73659360c60032a59566b93b9a2a5416748794dab1838508fa98ac7a.jpg)
NOTE:

In most cases, the &lt; Delete &gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt; F1 &gt;, &lt; F2 &gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   BIOS Setup Utility\n*   Screens\n*   Left and Right Keys to Select a Setup Screen\n*   Screen 1\n*   Screen 2\n*   Screen 3\n*   Screen 4\n*   Screen 5\n*   Items\n*   Tab Key to Select Fields\n*   ± (appearing in six separate boxes arranged in two rows)\n*   ± To Change Field Values\n*   Up and Down Keys to Select a Setup Item\n*   Fields\n\n**Connections:**\n*   A downward arrow connects **BIOS Setup Utility** to **Screens**.\n*   A dotted downward arrow connects **Left and Right Keys to Select a Setup Screen** to **Screen 1**.\n*   Double-headed horizontal arrows connect **Screen 1** to **Screen 2**, **Screen 2** to **Screen 3**, **Screen 3** to **Screen 4**, and **Screen 4** to **Screen 5**.\n*   A downward arrow connects **Screens** to **Items**.\n*   A dotted arrow connects **Tab Key to Select Fields** to the top-left box containing **±**.\n*   Double-headed horizontal arrows connect the top row of **±** boxes (left to middle, and middle to right).\n*   A dotted arrow connects **± To Change Field Values** to the top-right box containing **±**.\n*   Down and Up arrows are positioned between the top and bottom rows of **±** boxes.\n*   A dotted arrow connects **Up and Down Keys to Select a Setup Item** to the Up/Down arrows.\n*   Arrows connect **Fields** to the bottom row of **±** boxes.\n*   Double-headed horizontal arrows connect the bottom row of **±** boxes (left to middle, and middle to right).](.cpci-3520-50m-00036-1000-10-07102024/5025149e0b8056ad1914450b1476459b0cd94f2ef22aceefe5c71e15e5f59e6d.jpg)

![The image displays a graphic icon of a white document with the top-right corner folded down. Faint horizontal grey lines run across the document. A large, bold red checkmark is superimposed over the center of the paper.](.cpci-3520-50m-00036-1000-10-07102024/4426146433e1e6c88a1eeeae0b8a02be44290e9f787291d6b10d7f248338db6e.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

![The image displays a simple black line drawing on a white background. It features two horizontal lines extending outward from a central point, where two arrowheads point inward toward each other. This symbol is commonly used in user interfaces to indicate horizontal resizing.](.cpci-3520-50m-00036-1000-10-07102024/aaf2fefadbffbe5e98ed8876e52b22438d3bf844374ffa07449dc4d5853ea384.jpg)

Left/Right. The Left and Right &lt; Arrow &gt; keys allow you to select a setup screen. For example: Main screen, Advanced screen, Chipset screen, and so on.

![The image displays two black arrows on a white background. On the left, an arrow points vertically upward. On the right, an arrow points vertically downward.](.cpci-3520-50m-00036-1000-10-07102024/f649c4983c5448f0dddbc6c67daaed63d50b0d1091220dfbd40b27a29775ab24.jpg)

Up/Down The Up and Down &lt; Arrow &gt; keys allow you to select a setup item or sub-screen.

![The image displays the text '+.-'.](.cpci-3520-50m-00036-1000-10-07102024/6240b1fd50e06e8e981124888a31e73186c2887f4cdc59aac4c400bd5c583e3a.jpg)

Plus/Minus The Plus and Minus &lt; Arrow &gt; keys allow you to change the field value of a particular setup item. For example: Date and Time.

![The image displays the word 'Tab' in a bold, black, sans-serif font centered on a white background.](.cpci-3520-50m-00036-1000-10-07102024/251cc57f904465f905d6c247f18932a01a4624b8357fe0e5a38a0610a59c973a.jpg)

The &lt; Tab &gt; key allows you to select setup fields.

![The image features the capital letters 'ESC' written in a bold, black sans-serif font against a plain white background.](.cpci-3520-50m-00036-1000-10-07102024/4a965a70a7a6fa042817ffca610bf2e32a59ef5ac927f4da9834aa8e1ba6828f.jpg)

The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. Press the &lt; Enter &gt; key to discard changes and exit. You can also use the &lt; Arrow &gt; key to select Cancel and then press the &lt; Enter &gt; key to abort this function and return to the previous screen.

# 7.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main BIOS Setup menu is shown below.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td><td>Server Mgmt</td></tr><tr><td>-BIOS Information-System Information-System Date-System Time</td><td>-CPU ▶Configuration-Power ▶Management-USB ▶Configuration-AMT ▶Configuration-CSM ▶Configuration-Super IO ▶Configuration-Serial Console Redirection ▶-Miscellaneous-Network ▶Stack Configuration-Intel ® I210 ▶Gigabit Network Connection – [MAC Address]-Intel ® I210 ▶Gigabit Network Connection – [MAC Address]-Intel ® Ethernet Connection (7) I219-LM – [MAC Address] ▶</td><td>-System ▶Agent (SA) Configuration-PCH-IO ▶Configuration</td><td>-Administrator Password-User Password-Secure Boot Menu ▶- HDD Security Configuration</td><td>-Boot Configuration</td><td>-Save Options-Boot Override</td><td>-BMC Self Test Status-BMC Device ID-BMC Device Revision-BMC Firmware Revision-IPMI Version-BMC Intreface(s)-BMC Support-OS Watchdog Timer</td></tr></table>

![The image displays a white document icon with a folded top-right corner. Faint horizontal lines are visible on the page, resembling text. A large, bold red checkmark is drawn diagonally across the center of the document.](.cpci-3520-50m-00036-1000-10-07102024/eab20107a4d82cb21deb3dc6861aa35159c48df6e57d04317dd607039362703f.jpg)
NOTE:

► indicates a submenu Gray text indicates info only

# 7.2.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display Core Version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Date the BIOS was built</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Platform MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Platform GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Intel Management Engine Version</td></tr><tr><td>BIOS Boot Source</td><td>Info only</td><td>First BIOS</td></tr></table>

# 7.2.2 System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU Board Version</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display Intel CPU Brand Information</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU Stepping</td></tr><tr><td>GT Info</td><td>Info only</td><td>Display GT info</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU Frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Current System installed Memory Size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency Information</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH Version</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display PCH Stepping</td></tr></table>

# 7.2.3 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX).</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds.</td></tr></table>

# 7.3 Advanced

This menu contains the settings for most of the user interfaces in the system.

7.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Manufacturer, model</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU Information</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision</td></tr><tr><td>Speed</td><td>Info only</td><td>Display CPU Speed.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display L1 Data Cache size</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display L1 Instruction Cache size</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display L2 Data Cache size</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display L3 Data Cache size</td></tr><tr><td>L4 Cache</td><td>Info ony</td><td>Display L4 Data Cache size</td></tr><tr><td>Boot performance mode</td><td>Max Battery Max Non-Turbo Performance Turbo Perfromance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled or Disabled Hyper-Threading Technology</td></tr><tr><td>Active Processor Cores</td><td>All 1 2 3 4 5 6 7</td><td>Number of cores to enable in each processor package</td></tr><tr><td>Intel® SpeedStepTM</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported</td></tr><tr><td>Intel® Speed Shift Technology</td><td>Disabled Enabled</td><td>Enable/Disable Intel® Speed Shift Technology support.</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable/Disable processor Turbo Mode</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal Deactivate</td><td>Configurable TDP Mode as Nominal/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled Enabled</td><td>When a processor thermal sensor trips (either core), the PROCHOT# will be driven. If bi-direction is enabled, external agents can drive PROCHOT# to throttle the processor</td></tr><tr><td>C state</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Package C State Limit</td><td>C0/C1C2C3C6C7C7SC8C9C10CPU DefaultAuto</td><td>Maximum Package C State Limit Setting.CPU Default: Leaves to Factory default value.Auto: Initializes to deepest available Package C State Limit</td></tr><tr><td>Active Processor Cores</td><td>All12345</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>Enable/Disable VT-d capability</td></tr><tr><td>DTS SMM</td><td>DisabledEnabledCritical TempReporting (Out of spec)</td><td>Disabled: ACPI thermal management uses EC reported temperature values.Enabled: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.Out of Spec: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enable/Disable utilization of additional hardware capabilities provided by Intel® Trusted Execution Technology. Changes require a full power cycle to take effect.</td></tr></table>

# 7.3.2 Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables or Disables BIOS ACPI Auto Confuriation</td></tr></table>

# 7.3.3 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module version</td><td>Info only</td><td></td></tr><tr><td>USB Controllers:</td><td>Info only</td><td></td></tr><tr><td>USB Devices:</td><td>Info only</td><td>.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable/Disable USB Mass Storage Driver Support</td></tr><tr><td>XHCI Compliance Mode</td><td>EnabledDisabled</td><td>Option to enable Compliance Mode. Default is to disable Compliance Mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>xDCI Support</td><td>EnabledDisabled</td><td>Enable/Disable xDCI (USB OTG device)</td></tr><tr><td>USB Port Disable Override</td><td>Disable LinkSelect Per-Pin</td><td>Select to Enable/Disable the corresponding USB port from reporting a Device Connection to the Controller.</td></tr></table>

# 7.3.4 AMT Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>AMT BIOS Features</td><td>DisabledEnabled</td><td>When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup.Note: This option does not disable Manageability Features in FW.</td></tr><tr><td>MEBx Hotkey Pressed</td><td>DisabledEnabled</td><td>OME Flag Bit 1:Enable automatic MEBx hotkey press.</td></tr></table>

7.3.5 CMS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>DisabledEnabled</td><td>Enable/Disable CSM Support.</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td></td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>UPON REQUEST - GA20 can be disabled using BIOS services. ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>Boot Option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls Legacy/UEFI ROMs priority.</td></tr><tr><td>Option ROM execution</td><td>Info only</td><td></td></tr><tr><td>Network</td><td>Do not launchLegacyUEFI</td><td>Controls the execution of UEFI and Legacy Network OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Storage OpROM</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI devices</td><td>Do not launchUEFILegacy</td><td>Determines OpROM execution policy for devices other than Network, Storage, or Video.</td></tr></table>

7.3.6 Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT6106D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 3 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 4 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 5 Configuration</td><td>Submenu</td><td></td></tr></table>

Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=3F8h; IRQ=4</td><td>Fixed configuration of serial port.</td></tr><tr><td>Device Mode</td><td>RS232 ModeRS422/RS485Mode</td><td>Change the Serial Port mode.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4;IO=3F8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2F8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=3E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;</td><td>Select an optimal setting for Super IO Device</td></tr></table>

Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=2F8h; IRQ=3</td><td>Fixed configuration of serial port.</td></tr><tr><td>Device Mode</td><td>RS232 ModeRS422/RS485 Mode</td><td>Change the Serial Port mode.</td></tr><tr><td>Change Settings</td><td>AutoIO=2F8h; IRQ=3;IO=3F8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2F8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=3E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;</td><td>Select an optimal setting for Super IO Device</td></tr></table>

![The image shows a graphic icon of a white document with horizontal lines and a folded top-left corner. A large, bold red checkmark is superimposed over the center of the document. There is no text present.](.cpci-3520-50m-00036-1000-10-07102024/586799b9b226d1cd7c9274092044accc8f8a8777077b197f2208c542d87b72f5.jpg)
NOTE:

Device Mode settings are for cPCI-3520G only. For cPCI-3520D/P models, set the Device Mode using SW1\~SW4. See “COM1 Mode Selection Switches (SW1-SW4)” on page 49..

Super IO Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 3Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=3E8h; IRQ=5</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3E8h; IRQ=7;IO=3E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2F0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;</td><td>Select an optimal setting for Super IO Device</td></tr></table>

Super IO Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 4Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=2E8h; IRQ=7</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=2E8h; IRQ=7;IO=3E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2F0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;</td><td>Select an optimal setting for Super IO Device</td></tr></table>

Super IO Configuration > Serial Port 5 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 5Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>IO=2F0h; IRQ=6</td><td>Fixed configuration of serial port.</td></tr><tr><td>Change Settings</td><td>AutoIO=2E0h; IRQ=7;IO=3E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E8h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2F0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;IO=2E0h; IRQ=3, 4, 5,6, 7, 9, 10, 11, 12;</td><td>Select an optimal setting for Super IO Device</td></tr></table>

7.3.7 Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Console Redirection</td><td>Info only</td><td></td></tr><tr><td colspan="3">COM1~4</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection enable or disable</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1&#x27;s in the data bits is even. Odd: parity bit is 0 if num of 1&#x27;s in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet.(A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a &#x27;stop&#x27; signal can be sent to stop the data flow. Once the buffers are empty, a &#x27;start&#x27; signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

# 7.3.8 Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Trusted Computing</td><td>Submenu</td><td>Trusted Computing Settings</td></tr><tr><td>NVMe Configuration</td><td>Submenu</td><td>NVMe Device Options Settings</td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>ATX: OS will turn off system power when shutdown.AT mode will not support S3 &amp; S4 &amp; S5, so it will change Power Loss State to Power On.</td></tr><tr><td>Network</td><td>Do not launchUEFILegacy</td><td>Controls the execution of UEFI Network OpROM</td></tr><tr><td>VGA Switch</td><td>FrontRTM</td><td>Change the VGA output. Selectoroutput</td></tr></table>

# Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>DisabledEnabled</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr></table>

# NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NVMe Configuration</td><td>Info only</td><td></td></tr></table>

# 7.3.9 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>IPv4 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv4 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.</td></tr><tr><td>IPv6 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>IPv6 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>IPSEC Certificate</td><td>Enabled</td><td>Support to Enable/Disable IPSEC certificate for Ikev.</td></tr><tr><td>PXE boot wait time</td><td>0</td><td>Wait time in seconds to press ESC key to abort the PXE boot.Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>1</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

# 7.3.10 Intel I210 Gigabit Network Connection / Ethernet Connection (7) I219-LM [MAC Address]

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NIC Configuration</td><td>Submenu</td><td>Click to configure the device network device port</td></tr><tr><td>UEFI Driver</td><td>Info only</td><td></td></tr><tr><td>Adpater PBA</td><td>Info only</td><td></td></tr><tr><td>Device Name</td><td>Info only</td><td></td></tr><tr><td>Chip Type</td><td>Info only</td><td></td></tr><tr><td>PCI Device ID</td><td>Info only</td><td></td></tr><tr><td>PCI Address</td><td>Info only</td><td></td></tr><tr><td>Link Status</td><td>Info only</td><td></td></tr><tr><td>MAC Address</td><td>Info only</td><td></td></tr><tr><td>Virtual MAC Address</td><td>Info only</td><td></td></tr></table>

NIC Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Link Speed</td><td>Auto Negotiated10 Mbps Half10 Mbps Full100 Mbps Half100 Mbps Full</td><td>Specifies the port speed used for the selected boot protocol</td></tr><tr><td>Wake On LAN</td><td>DisabledEnabled</td><td>Enables the server to be powered on using an in-band magic packet.</td></tr></table>

# 7.4 Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>Submenu</td><td>System Agent (SA) Parameters</td></tr><tr><td>PCH-IO Configuration</td><td>Submenu</td><td>PCH parameters</td></tr></table>

# 7.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info only</td><td>Displaye SA PCIe code revision</td></tr><tr><td>VT-d</td><td>Info only</td><td>Display VT-d supported or not</td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td>Memory parameters</td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td>Graphics parameters</td></tr><tr><td>PEG Port Configuration</td><td>Submenu</td><td>PEG port parameters</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>EnabledDisabled</td><td>Enable/Disable above 4GB memory mapped BIOS assignment.</td></tr></table>

# Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display RC version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency</td></tr><tr><td>Memory Voltage</td><td>Info only</td><td>Display memory voltage</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Display memory timing parameters</td></tr><tr><td>Channel 0 Slot 0</td><td>Info only</td><td>Display memory Size</td></tr><tr><td>Channel 1 Slot 0</td><td>Info only</td><td>Display memory Size</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067, 1200..., 5867</td><td>Maximum memory frequency selections in MHz. Valid values should match the refclk, i.e. divided by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB, 1.25GB...3.5GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller.</td></tr></table>

Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>DisabledEnabled</td><td>If Enabled, it will not scan for External Gfx card on PEG and PCH PCIE ports</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIe</td><td>Select which IGFX/PEG/PCI Graphics device should be Primary Display.</td></tr><tr><td>Select PCIe Card</td><td>AutoElk Creek 4PEG Eval</td><td>Select the card used on the platformAuto: Skip GPIO based power enable to dGPU Elk Creek 4: dGPU Power Enable = ActiveLow PEG Eval: dGPU Power Enable = ActiveHigh</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture SizeNote: Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM support.</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M64M4M8M12M16M20M24M28M32M/F736M40M44M48M52M56M60M</td><td>Select DVMT 5.0 pre-allocated (fixed) graphics memory size used by the internal graphics device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMax</td><td>Select DVMT5.0 total graphics memory used by the internal graphics device.</td></tr></table>

PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">PEG 0:1:0 / 0:1:1 / 0:1:2 / 0:6:0</td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or disable this root port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:0 max speed</td></tr><tr><td>PEG0 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG0/1/2/3 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG0/1/2/3 Physical Slot Number</td><td>1</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td colspan="3"></td></tr><tr><td>Gen3 RxCTLE Control</td><td>Submenu</td><td>Gen3 RxCTLE Control per Bundle</td></tr><tr><td>PCIe Rx CEM Test Mode</td><td>DisabledEnabled</td><td>Enable/Disable PEG Rx CEM Loopback Mode</td></tr><tr><td>PCIe Spread Spectrum Clocking</td><td>EnabledDisabled</td><td>Allows disabling Spread Spectrum Clocking for compliance testing</td></tr></table>

Gen3 RxCTLE Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Bundle0</td><td>0</td><td>Gen3 RxCTLE setting for Bundle0 (Lane0, Lane1)</td></tr><tr><td>Bundle1</td><td>0</td><td>Gen3 RxCTLE setting for Bundle1 (Lane2, Lane3)</td></tr><tr><td>Bundle2</td><td>0</td><td>Gen3 RxCTLE setting for Bundle2 (Lane4, Lane5)</td></tr><tr><td>Bundle3</td><td>0</td><td>Gen3 RxCTLE setting for Bundle3 (Lane6, Lane7)</td></tr><tr><td>Bundle4</td><td>0</td><td>Gen3 RxCTLE setting for Bundle4 (Lane8, Lane9)</td></tr><tr><td>Bundle5</td><td>0</td><td>Gen3 RxCTLE setting for Bundle5 (Lane10, Lane11)</td></tr><tr><td>Bundle6</td><td>0</td><td>Gen3 RxCTLE setting for Bundle6 (Lane12, Lane13)</td></tr><tr><td>Bundle7</td><td>0</td><td>Gen3 RxCTLE setting for Bundle7 (Lane14, Lane15)</td></tr><tr><td>PEG10 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG0 RxCTLE adaptive behaviour</td></tr><tr><td>PEG11 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG1 RxCTLE adaptive behavior</td></tr><tr><td>PEG12 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG2 RxCTLE adaptive behavior</td></tr><tr><td>DMI RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides DMI RxCTLE adaptive behavior</td></tr></table>

7.4.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuraiton</td><td>Submenu</td><td>Configure Serial IRQ Mode.</td></tr><tr><td>SATA And RST Configuration</td><td>Submenu</td><td>Enable/Disable SMBus Support.</td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td>Select the target OS.</td></tr><tr><td>PCH LAN Controller</td><td>EnabledDisabled</td><td>Enable/Disable onboard NIC</td></tr><tr><td>Wake on LAN for S5 Enable</td><td>EnabledDisabled</td><td>Enable/Disable integrated LAN to wake the system only for S5.</td></tr><tr><td>Serial IRQ Mode</td><td>QuietContinuous</td><td>Configure Serial IRQ Mode</td></tr><tr><td>High Precision Timer</td><td>EnabledDisabled</td><td>Enable or Disable the High Precision Event Timer</td></tr><tr><td>PCIE PLL SSC</td><td>Auto0.1%~2.0%</td><td>PCIe PLL SSC percentage. Auto – Keep HW default, no BIOS override. Range is 0.0%-2.0%</td></tr><tr><td>SPD Write Disable</td><td>TrueFalse</td><td>Enable/Disable setting SPD write disable.</td></tr></table>

PCIe Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Configuration</td><td colspan="2">Info only</td></tr><tr><td>PCI Express Clock Gating</td><td>Disabled Enabled</td><td>PCI Express Clock Gating Enable/Disable for each root port</td></tr><tr><td>DMI Link ASPM Control</td><td>Disabled Enabled</td><td>The control of Active State Power Management of the DMI Link</td></tr><tr><td>PCIE Port assigned to LAN</td><td>Read only</td><td></td></tr><tr><td>Compliance Test Mode</td><td>Disabled Enabled</td><td>Enable when using Compliance Load Board</td></tr><tr><td>PCIe-USB Glitch W/A</td><td>Disabled Enabled</td><td>PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG port.</td></tr><tr><td>PCIe function swap</td><td>Disabled Enabled</td><td>When Disabled, prevents PCIE root port function swap. If any function other than  $0^{th}$  is enabled,  $0^{th}$  will become visible.</td></tr><tr><td>PCIe Express Root Port1~11, 17~20</td><td>Submenu</td><td>PCI Express Root Port Settings</td></tr></table>

PCIe Express Configuration > PCI Express Root PortX

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Express Root PortX</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear.Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisableL0sL1L0sL1Auto</td><td>Set the ASPM Level:Force L0s – Force all inks to L0s StateAuto – BIOS auto configureDisable – Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 substates settings.</td></tr><tr><td>Gen3 Eq Phase3 Method</td><td>HardwareStatic Coeff.</td><td>PCIe Gens3 Equalization Phase 3 Method</td></tr><tr><td>UPTP</td><td>Info only</td><td>Upstream Port Transmitter Preset</td></tr><tr><td>DPTP</td><td>Info only</td><td>Downstream Port Transmitter Preset</td></tr><tr><td>ACS</td><td>EnabledDisabled</td><td>Enable/Disable Access Control ServicesExtended Capability</td></tr><tr><td>PTM</td><td>EnabledDisabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>EnabledDisabled</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>EnabledDisabled</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>EnabledDisabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>EnabledDisabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>EnabledDisabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable</td></tr><tr><td>CER</td><td>EnabledDisabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable</td></tr><tr><td>CTO</td><td>EnabledDisabled</td><td>PCI Express Completion Timer TO Enable/Disable.</td></tr><tr><td>SEFE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable</td></tr><tr><td>SENFE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable</td></tr><tr><td>PME SCI</td><td>EnabledDisabled</td><td>PCI Express PME SCI Enable/Disable</td></tr><tr><td>Hot Plug</td><td>EnabledDisabled</td><td>PCI Express Hot Plug Enable/Disable</td></tr><tr><td>Advanced Error Reporting</td><td>EnabledDisabled</td><td>Advanced Error Reporting Enable/Disable</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable</td></tr><tr><td>Detect Timeout</td><td>Info only</td><td>The number of milliseconds reference code will wait for link to exit Detect State for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>Info only</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge</td></tr><tr><td>Reserved Memory</td><td>Info only</td><td>Resreved Memory for this Root Bridge (1-20) MB</td></tr><tr><td>Reserved I/O</td><td>Info only</td><td>Reserved I/O (4K/8K/12K/16K/20K) range for this root bridge</td></tr><tr><td colspan="3">PCH PCIe LTR Configuration</td></tr><tr><td>LTR</td><td>EnabledDisabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Force LTR Override</td><td>DisabledEnabled</td><td>Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced. Enabled: LTR override values will be forced and LTR messages from the device will be ignored.</td></tr><tr><td>LRT Lock</td><td>DisabledEnabled</td><td>PCIE LTR configuration lock</td></tr></table>

SATA And RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA And RST Configuration</td><td colspan="2">Info only</td></tr><tr><td>SATA Controller(s)</td><td colspan="2">DisabledEnabled</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST PremiumWith Intel OptaneSystem Acceleration</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back)</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td>RST Legacy OROM/RST UEFI driver will refer to the SWFM configuration to enable/disable the storage features.</td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support</td></tr><tr><td>Serial ATA Port X, X = 0-7</td><td colspan="2">Info only</td></tr><tr><td>Software Preserve</td><td colspan="2">Info only</td></tr><tr><td>Port X</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port.</td></tr><tr><td>Hot Plug Capability</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable</td></tr><tr><td>Configured as eSATA</td><td colspan="2">Info only</td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to solid state drive or hard disk drive</td></tr><tr><td>SATA Port X DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port X DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>DTTO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO configuration</td></tr><tr><td>DITO Value</td><td>Info only</td><td>Display DITO value</td></tr><tr><td>DM Value</td><td>Info only</td><td>Display DM value</td></tr></table>

HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD-Audio Support</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HAD will be unconditionally enabled.</td></tr></table>

# 7.5 Security

7.5.1 Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Set Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Set user Password</td></tr><tr><td>Secure Boot Menu</td><td>Submenu</td><td>Customizable Secure Boot settings</td></tr><tr><td>HDD Security Configuration</td><td>Enter User PasswordEnter MasterPassword</td><td>Set HDD User PasswordSet HDD Master Password</td></tr></table>

Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Mode</td><td>Info only</td><td>Show system mode.</td></tr><tr><td>Secure Boot</td><td>Info only</td><td>Show Secure Boot status.</td></tr><tr><td>Secure Boot Control</td><td>Disabled Enabled</td><td>Secure Boot activated when platform Key (PK) is enrolled, system mode is User/Deployed, and CSM function is disabled.</td></tr><tr><td>Secure Boot Mode</td><td>Standard Custom</td><td>Secure Boot mode options:If Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr></table>

7.6 Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state after system boot.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or disables Quiet Boot option.</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll SATA Devices</td><td>If Last Boot SATA Devices Only, Only last boot SATA device will be available in Post.If All SATA Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>VGA Support</td><td>Auto EFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo will NOT be shown during post. EFI driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>Disabled Full Initial Partial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Deivces Support</td><td>Disabled Enabled</td><td>If Disabled, PS2 devices will be skipped.</td></tr><tr><td>Network Stack Driver Support</td><td>Disabled Enabled</td><td>If Disabled, Network Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>Disabled Enabled</td><td>If disable, Redirection function will be disabled.</td></tr><tr><td>Boot mode select</td><td>Legacy UEFI</td><td>Select boot mode LEGACY/UEFI.</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr></table>

# 7.7 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Reset</td><td>Save changes and reset the system.</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system without saving any changes.</td><td>Exit system setup without saving the changes.</td></tr><tr><td>Save Changes and Reset</td><td>Reset the system with saving any changes.</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system and discard any changes.</td><td>Reset the system after without the changes.</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Default</td><td></td><td>Restore/Load the Default values for all the setup options.</td></tr><tr><td>Save as User Default</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Default</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>UEFI: Built-in EFI Shell</td><td></td><td></td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td></td></tr></table>

# 7.8 Server Mgmt

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BMC Self Test Status</td><td>Info only</td><td></td></tr><tr><td>BMC Device ID</td><td>Info only</td><td></td></tr><tr><td>BMC Device Revision</td><td>Info only</td><td></td></tr><tr><td>BMC Firmware Revision</td><td>Info only</td><td></td></tr><tr><td>IPMI Version</td><td>Info only</td><td></td></tr><tr><td>BMC Interface(s)</td><td>Info only</td><td></td></tr><tr><td>BMC Support</td><td>EnabledDisabled</td><td>Enable/Disable interfaces to communicate with BMC</td></tr><tr><td>OS Watchdog Timer</td><td>DisabledEnabled</td><td>If enabled, starts a BIOS timer which can only be shut off by Management Software after the OS loads. Helps determine that the OS successfully loaded or follows the OS Boot Watchdog Timer policy</td></tr><tr><td>OS Wtd Timer Timeout</td><td>5 minutes10 minutes15 minutes20 minutes</td><td>Configure the length of the OS Boot Watchdog Timer. Not available if OS Boot Watchdog Timer is disabled.</td></tr><tr><td>OS Wtd Timer Policy</td><td>Do NothingResetPower DownPower Cycle</td><td>Configure how the system should respond if the OS Boot Watchdog Timer expires. Not available if OS Boot Watchdog Timer is disabled.</td></tr></table>

# 8 IPMI User Guide

# 8.1 Introduction

This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 2.0. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.

# 8.2 Summary of Commands Supported by BMR-AVR-cPCI

The table below lists all the commands supported by the BMR-AVR-cPCI.

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>Description(Req'd by PICMG 3.0/2.9)</td></tr><tr><td colspan="5">IPM Device “Global” Commands</td></tr><tr><td>Get Device ID</td><td>20.1</td><td>App</td><td>01h</td><td>This command is used to retrieve the Intelligent Device's Hardware Revision, Firmware/ Software Revision, and Sensor and Event Interface Command specification revision information.</td></tr><tr><td>Cold Reset</td><td>20.2</td><td>App</td><td>02h</td><td>This command directs the Responder to perform a ‘Cold Reset’ of itself.(Optional/Optional)</td></tr><tr><td>Warm Reset</td><td>20.3</td><td>App</td><td>03h</td><td>This command directs the Responder to perform a ‘Warm Reset’ of itself.</td></tr><tr><td>Get Self Test Results</td><td>20.4</td><td>App</td><td>04h</td><td>This command directs the device to return its Self Test results, if any.(Mandatory/Mandatory)</td></tr><tr><td>Get Device GUID</td><td>20.8</td><td>App</td><td>08h</td><td>This command returns a GUID (Globally Unique ID), also referred to as a UUID (Universally Unique IDentifier), for the management controller. (Optional/Optional)</td></tr><tr><td>Broadcast "Get Device ID"</td><td>20.9</td><td>App</td><td>01h</td><td>This is a broadcast version of the 'Get Device ID' command that is provided for the 'discovery' of Intelligent Devices on the IPMB. (Mandatory/Mandatory)</td></tr><tr><td colspan="5">IPMI Messaging Support Commands</td></tr><tr><td>Send Message</td><td>22.7</td><td>App</td><td>34h</td><td>The Send Message command is used for bridging IPMI messages between channels, and between the system management software (SMS) and a given channel. (Optional/Optional)</td></tr><tr><td colspan="5">BMC Watchdog Timer</td></tr><tr><td>Reset Watchdog Timer</td><td>27.5</td><td>App</td><td>22h</td><td>The Reset Watchdog Timer command is used for starting and restarting the Watchdog Timer from the initial countdown value that was specified in the Set Watchdog Timer command. (Mandatory/Optional)</td></tr><tr><td>Set Watchdog Timer</td><td>27.6</td><td>App</td><td>24h</td><td>The Set Watchdog Timer command is used for initializing and configuring the watchdog timer. The command is also used for stopping the timer. (Mandatory/Optional)</td></tr><tr><td>Get Watchdog Timer</td><td>27.7</td><td>App</td><td>25h</td><td>This command retrieves the current settings and present countdown of the watchdog timer. (Mandatory/Optional)</td></tr><tr><td colspan="5">Event Commands</td></tr><tr><td>Set Event Receiver</td><td>29.1</td><td>S/E</td><td>00h</td><td>This global command tells a controller where to send Event Messages.(Mandatory/Optional)</td></tr><tr><td>Get Event Receiver</td><td>29.2</td><td>S/E</td><td>01h</td><td>This global command is used to retrieve the present setting for the Event Receiver Slave Address and LUN. This command is only applicable to management controllers that act as IPMB Event Generators.(Mandatory/Optional)</td></tr><tr><td>Platform Event Message</td><td>29.3</td><td>S/E</td><td>02h</td><td>This command may be thought of as a request for the BMC to process the event data that the command contains. Typically, the data will be logged to the System Event Log (SEL).(Mandatory/Optional)</td></tr><tr><td colspan="5">Sensor Device Commands</td></tr><tr><td>Get Device SDR Info</td><td>35.2</td><td>S/E</td><td>20h</td><td>This command returns general information about the collection of sensors in a Dynamic Sensor Device.(Mandatory/Optional)</td></tr><tr><td>Get Device SDR</td><td>35.3</td><td>S/E</td><td>21h</td><td>The ‘Get Device SDR’ command allows SDR information for sensors for a Sensor Device (typically implemented in a satellite management controller) to be returned. (Mandatory/Optional)</td></tr><tr><td>Reserve Device SDR Repository</td><td>35.4</td><td>S/E</td><td>22h</td><td>This command is used to obtain a Reservation ID.(Mandatory/Optional)</td></tr><tr><td>Set Sensor Hysteresis</td><td>35.6</td><td>S/E</td><td>24h</td><td>This command provides a mechanism for setting the hysteresis values associated with the thresholds of a sensor that has threshold based event generation. (Optional/Optional)</td></tr><tr><td>Get Sensor Hysteresis</td><td>35.7</td><td>S/E</td><td>25h</td><td>This command retrieves the present hysteresis values for the specified sensor. (Optional/Optional)</td></tr><tr><td>Set Sensor Threshold</td><td>35.8</td><td>S/E</td><td>26h</td><td>This command is used to set the specified threshold for the given sensor. (Optional/Optional)</td></tr><tr><td>Get Sensor Threshold</td><td>35.9</td><td>S/E</td><td>27h</td><td>This command retrieves the threshold for the given sensor. (Optional/Optional)</td></tr><tr><td>Set Sensor Event Enable</td><td>35.10</td><td>S/E</td><td>28h</td><td>This command provides the ability to disable or enable Event Message Generation for individual sensor events. The command is also used to enable or disable sensors in their entirety using the disable scanning bit. (Optional/Optional)</td></tr><tr><td>Get Sensor Event Enable</td><td>35.11</td><td>S/E</td><td>29h</td><td>This command returns the enabled/disabled state for Event Message Generation from the selected sensor. The command also returns the enabled/disabled state for scanning on the sensor. (Optional/Optional)</td></tr><tr><td>Get Sensor Event Status</td><td>35.13</td><td>S/E</td><td>2Bh</td><td>The Get Sensor Event Status command is provided to support systems where sensor polling is used in addition to, or instead of, Event Messages for event detection. (Optional/Optional)</td></tr><tr><td>Get Sensor Reading</td><td>35.14</td><td>S/E</td><td>2Dh</td><td>This command returns the present reading for sensor. The sensor device may return a stored version of a periodically updated reading, or the sensor device may scan to obtain the reading after receiving the request. (Mandatory/Optional)</td></tr><tr><td>Get Sensor Type</td><td>35.16</td><td>S/E</td><td>2Fh</td><td>This command is used to retrieve the Sensor Type and Event/Reading Type for the specified sensor. (Optional/Optional)</td></tr><tr><td colspan="5">FRU Device Commands</td></tr><tr><td>Get FRU Inventory Area Info</td><td>34.1</td><td>Storage</td><td>10h</td><td>Returns overall the size of the FRU Inventory Area in this device, in bytes. (Mandatory/Optional)</td></tr><tr><td>Read FRU Data</td><td>34.2</td><td>Storage</td><td>11h</td><td>The command returns the specified data from the FRU Inventory Info area. (Mandatory/Optional)</td></tr><tr><td>Write FRU Data</td><td>34.3</td><td>Storage</td><td>12h</td><td>The command writes the specified byte or word to the FRU Inventory Info area. (Mandatory/Optional)</td></tr><tr><td colspan="5">OEM Commands</td></tr><tr><td>GET BIOS SEL</td><td>N/A</td><td>0x30</td><td>0x39</td><td>GET BIOS ROM SELECT (Read Only)1: BIOS ROM02: BIOS ROM1</td></tr><tr><td>ME Lock/Unlock</td><td>N/A</td><td>0x30</td><td>0xF8</td><td>This command select ME lock or unlock0: ME Lock1: ME UnLock</td></tr><tr><td>LED TEST</td><td>N/A</td><td>0x30</td><td>0xF9</td><td>This command controls LED status0:TBD LED ON1:TBD LED OFF2:THERMAL LED ON3:THERMAL LED OFF4:WDT LED ON5:WDT LED OFF</td></tr><tr><td>BIOS SEL</td><td>N/A</td><td>0x30</td><td>0xFA</td><td>BIOS ROM SELECT0: BIOS ROM01: BIOS ROM1</td></tr><tr><td>Operating time</td><td>N/A</td><td>0x30</td><td>0xFB</td><td>This command reads the Total Ontime Seconds counter. The returned value specifies the total time in seconds the system has been running in S0 state (4 Byte Ready only). Used ipmitool to verify, LSB on the left</td></tr><tr><td>Number of power on cycle</td><td>N/A</td><td>0x30</td><td>0xFC</td><td>This command reads the Power Cycle Counter. The returned value specifies the number of times the external power supply has been shut down (including standby voltage, 4 Byte Ready only). Used ipmitool to verify, LSB on the left</td></tr><tr><td>Monitor reset causes</td><td>N/A</td><td>0x30</td><td>0xFD</td><td>This command returns the cause of the last system restart 0:UNKNOWN (In addition to the following options)1:WDT reset2:WDT.power down3:WDT power cycle4:HW reset5:IPMC payload reset6:Chassis reset</td></tr><tr><td>Get System Power State</td><td>N/A</td><td>0x30</td><td>0xFE</td><td>Get System Power status0: S01: S5</td></tr><tr><td>Payload reset</td><td>N/A</td><td>0x30</td><td>0xFF</td><td>Payload reset</td></tr></table>

# 8.3 CompactPCI Address Map

Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.

<table><tr><td colspan="4">CompactPCI Peripheral Address Mapping</td></tr><tr><td>Geo. Addr.</td><td>IPMB Addr.</td><td>Geo. Addr.</td><td>IPMB Addr.</td></tr><tr><td>0</td><td>Disabled</td><td>16</td><td>D0h</td></tr><tr><td>1</td><td>B0h</td><td>17</td><td>D2h</td></tr><tr><td>2</td><td>B2h</td><td>18</td><td>D4h</td></tr><tr><td>3</td><td>B4h</td><td>19</td><td>D6h</td></tr><tr><td>4</td><td>B6h</td><td>20</td><td>D8h</td></tr><tr><td>5</td><td>B8h</td><td>21</td><td>DAh</td></tr><tr><td>6</td><td>Bah</td><td>22</td><td>DCh</td></tr><tr><td>7</td><td>BCh</td><td>23</td><td>DEh</td></tr><tr><td>8</td><td>BEh</td><td>24</td><td>E0h</td></tr><tr><td>9</td><td>Coh</td><td>25</td><td>E2h</td></tr><tr><td>10</td><td>C4h</td><td>26</td><td>E4h</td></tr><tr><td>11</td><td>C6h</td><td>27</td><td>E6h</td></tr><tr><td>12</td><td>C8h</td><td>28</td><td>E8h</td></tr><tr><td>13</td><td>CAh</td><td>29</td><td>EAh</td></tr><tr><td>14</td><td>CCh</td><td>30</td><td>ECh</td></tr><tr><td>15</td><td>CEh</td><td>31</td><td>Disabled</td></tr></table>

# 8.4 Communications with IPMC

Operating systems need to use a serial port to communicate with the IPMC. The resource setting of the serial port must be IO: 0x2F0 and IRQ:6. The communication setting of the serial port must be BaudRate: 115200, DataBit: 8, ParityCheck: None, Stop-Bit: 1, and FlowControl: None. In Windows 10, use “COM5” to communicate with the IPMC.

# 8.5 IPMI Sensors List

<table><tr><td>Sensor Number</td><td>Sensor name</td><td>Normal Reading</td><td>Remark</td></tr><tr><td>01h</td><td>BMC Watchdog</td><td></td><td></td></tr><tr><td>06h</td><td>3.3V</td><td>3.3 V</td><td></td></tr><tr><td>03h</td><td>5V</td><td>5 V</td><td></td></tr><tr><td>02h</td><td>12V</td><td>12 V</td><td></td></tr><tr><td>0Fh</td><td>CPU Temp</td><td>40°C</td><td></td></tr><tr><td>0Eh</td><td>System Temp</td><td>25°C</td><td></td></tr></table>

# 8.6 Relevant Documents

<table><tr><td>Document Title</td><td>Revision</td><td>Source</td></tr><tr><td>Intelligent Platform Management Interface Specification Second Generation v2.0</td><td>Document Revision 1.1 October 1, 2013</td><td>https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html</td></tr><tr><td>PICMG 2.9 D1.0 CompactPCI System Management Specification</td><td>January 21, 2000</td><td></td></tr><tr><td>Intelligent Platform Management Bus Communications Protocol Specification v0.9</td><td>Document Revision 0.15 June 24, 1997</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this user’s manual for future reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 When installing/mounting or uninstalling/removing equipment:
 Turn off power and unplug any power cords/cables.
 To avoid electrical shock and/or damage to equipment:
 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);
 Make sure to use recommended voltage and power source settings;
 Always install and operate equipment near an easily accessible electrical socket-outlet;
 Secure the power cord (do not place any object on/over the power cord);
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a maroon warning triangle containing a white exclamation point in the center. Below the triangle, the text 'WARNING:' appears in black capital letters.](.cpci-3520-50m-00036-1000-10-07102024/072c60a618842e5ec288edf048a9559387afddcdabe6a5d0c0b0eb2aa1ca1445.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

 Equipment must be serviced by authorized technicians when:

 The power cord or plug is damaged;
 Liquid has penetrated the equipment;
 It has been exposed to high humidity/moisture;
 It is not functioning or does not function according to the user’s manual;
 It has been dropped and/or damaged; and/or,
 It has an obvious sign of breakage.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

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Email: service@adlinktech.com

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Tel: +1-408-360-0200

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Tel: +86-21-5132-8988

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Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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