# cPCI-3840 Series

3U CompactPCI Pentium(R) M

CPU Module

User's Manual

Manual Rev. 2.01

Revision Date: January 25, 2007

Part No: 50-15034-100

![The image displays a white recycling symbol centered on a solid black circular background. The symbol consists of three arrows arranged in a triangular formation, each pointing clockwise towards the next. Each arrow features a distinct design with three horizontal stripes on its tail section.](.cpci-3840-manual-10/50f1229570b3edaff53cb8d5268783397a6fc5c0157e9f019653907689aae9b3.jpg)
Recycled Paper

Copyright 2007 ADLINK TECHNOLOGY INC.

All Rights Reserved.

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance.

# ADLINK TECHNOLOGY INC.

Web Site: http://www.adlinktech.com

Sales & Service: Service@adlinktech.com

TEL: +886-2-82265877

FAX: +886-2-82265717

Address: 9F, No. 166, Jian Yi Road, Chungho City,

Taipei, 235 Taiwan

Please email or FAX this completed service form for prompt and satisfactory service.

<table><tr><td colspan="2">Company Information</td></tr><tr><td>Company/Organization</td><td></td></tr><tr><td>Contact Person</td><td></td></tr><tr><td>E-mail Address</td><td></td></tr><tr><td>Address</td><td></td></tr><tr><td>Country</td><td></td></tr><tr><td>TEL</td><td>FAX:</td></tr><tr><td>Web Site</td><td></td></tr><tr><td colspan="2">Product Information</td></tr><tr><td>Product Model</td><td></td></tr><tr><td>Environment</td><td>OS:M/B: CPU:Chipset: Bios:</td></tr></table>

Please give a detailed description of the problem(s):

# Table of Contents

# Table of Contents...... i

# List of Tables...... iii

# List of Figures ...... iv

# 1 Introduction ...... 1

1.1 Features.... 4
1.2 Main Functions 5

CompactPCI Bus Interface 5
IDE Interfaces 5
Gigabit Ethernet Ports 6
Universal Serial Bus (USB) 6
Serial I/O 6
SATA 6
Watchdog Timer 7
Hardware Monitoring 7
Operating System Support 7

1.3 Specifications.... 8

Specifications of the cPCI-3840 CPU Module 8
cPCI-R3840 RTM Specifications 11
I/O Connectivity Table 12

1.4 Unpacking Checklist 13

# 2 Jumpers and Connectors.... 15

2.1 cPCI-3840 Board Outline 16
2.2 cPCI-3840 Connector Pin Assignments 17

USB Connectors 17
Ethernet (RJ-45) Connector 17
VGA Connector 18
RS-232 DB-9 Serial Port Connector (COM1) 19
SATA Connector 19
IDE Connector 20
CompactFlash Connector 21
General Purpose LED Definitions 21
CompactPCI J2 Pin Assignment 22
CompactPCI J3 Pin Assignment 23

2.3 Switch and Jumper Setting 23

Reset Button (SW1) 24

CF Master/Slave Setting (CN5) 24

Clear CMOS (JP2) 24

2.4 cPCI-R3840 RTM Board Outline 26

2.5 cPCI-R3840 RTM Connector Pin Assignments 28

DVI Connector 28

cPCI-R3840 RJ2 Pin Assignment 29

# 3 Getting Started 31

3.1 Installing the CPU 32

3.2 Memory Module Installation 33

Installing the First Memory Module 33

Removing the CPU Core Module 34

Installing the Second Memory Module 35

3.3 CF Card Installation 36

3.4 CPU Core Module Installation.... 36

3.5 Heat Sink Installation 36

3.6 2.5" HDD Installation.... 40

3.7 cPCI-3840 CPU Module Installation 42

3.8 RTM Installation 43

# 4 Windows Driver Installation.... 45

4.1 Chipset Drivers Installation 46

4.2 VGA Driver Installation.... 46

4.3 LAN Driver Installation 47

4.4 Audio Codec Driver Installation.... 47

# 5 Utilities.... 49

5.1 Watchdog Timer.... 49

WDT Overview 49

Configuration Registers 50

GPIO Control Registers 52

WDT Programming Procedure 53

Utilities 53

5.2 Intel® Preboot Execution Environment (PXE) 54

# Warranty Policy 55

# List of Tables

Table 1-1: Mean Power Consumption 11

Table 1-2: I/O Connectivity 12

Table 2-1: Jumper and Connector Locations 16

Table 2-2: Ethernet LED Status 18

Table 2-3: Switches and Jumpers 23

Table 2-4: CN5 CF Master/Slave Setting 24

Table 2-5: JP2 Clear CMOS 25

# List of Figures

Figure 1-1: cPCI-3840 Architecture.... 3

Figure 2-1: cPCI-3840 Front View and Top View.... 16

Figure 2-2: cPCI-3840 Carrier Board Top View 16

Figure 2-3: cPCI-R3840 Front View and Top View 26

Figure 2-4: Side View of cPCI-R3840 27

Figure 3-1: CPU Installation.... 32

Figure 3-2: Memory Module Installation, Pt 1. 33

Figure 3-3: CPU Core Module Removal. 34

Figure 3-4: Memory Module Installation, Pt. 2. 35

Figure 3-5: Thermal Pad 37

Figure 3-6: Heat Sink Fitting 38

Figure 3-7: Heat Sink Screws 39

Figure 3-8: HDD and Mounting Bracket Installation.... 41

Figure 5-1: WDT Overview.... 49

# 1 Introduction

The cPCI-3840 is designed to be a high performance dual slot 3U CompactPCI CPU Module. It features a single Intel® Pentium® M processor with 1MB L2 cache in a 478-pin Micro-FCPGA package, and is validated with the Intel® 855GME chipset that supports 144-bit wide PC2100/2700 (266/333 MHz) registered ECC DDR DIMM up to a maximum of 2GB. The cPCI-3840 also features the Intel® 82546EB Dual Port Gigabit Ethernet Controller and supports one ATA33/66/100 IDE channel, one Compact Flash type I/II connector, and 2 ports SATA for high volume storage applications.

The Intel® Pentium® M is a high performance, low power mobile processor with several micro-architecture enhancements over existing Intel Mobile processors. Intel® Pentium® M supports Intel® Architecture with Dynamic Execution, on-die primary 32-KB instruction cache and 32-KB write-back data cache, on-die 1-MB second level cache with Advanced Transfer Cache Architecture, Advanced Branch Prediction and Data Prefetch Logic, Streaming SIMD Extensions 2 (SSE2), a 400-MHz Source-Synchronous processor system bus, and Advanced Power Management features including Enhanced Intel® SpeedStep® technology.

The Intel® Pentium® M processor system bus supports AGTL+ bus driver technology with integrated GTL termination resistors, (gated AGTL+ receivers for reduced power), 32-bit AGTL+ bus addressing (no support for 36-bit address extension), 400MT/s BPSB (100MHz), 2X address, 4X data, and 12 deep in-order queues.

The Intel® 855GME chipset north bridge contains a Graphics Memory Controller Hub (GMCH) component for embedded platforms. The GMCH provides the processor interface, system memory interface (DDR SDRAM), hub interface, CRT, and a DVO interface. The GMCH also supports 128-MB, 256-MB, and 512-MB memory technologies, 16 simultaneous open pages, and 64-bit data interface (72-bit with ECC).

Furthermore, the 855GME features a 350 MHz integrated 24bit RAMDAC supporting analog display with pixel resolution up to 1600x1200 at 85Hz and 2048x1536 at 75Hz, dual independent display pipe supporting concurrent or simultaneous display on each display device, digital video output with 165 MHz output clock on a 12-bit interface via one port DVO supporting pixel resolution up to 1600x1200 at 85Hz, Tri-view support through a LFP interface, DVO and CRT, and a maximum of 64 MB of dynamic video memory allocation.

The cPCI-3840 is equipped with the highly integrated, multi-functional Intel® 6300ESB I/O Controller Hub that provides the interface to the PCI bus, PCIX bus, and integrates miscellaneous I/O functions for legacy devices. The 855GMEand 6300ESB communicate over a dedicated hub interface (HI-1.5). The 6300ESB's functions and capabilities include an 8-Bit Hub Interface, a PCI-X bus which supports 64-bit/66MHz operations, a PCI Local Bus which supports 32-bit/33MHz operations, an integrated IDE controller which supports Ultra ATA100/66/33, integrated Serial ATA Host Controllers, two USB UHCI host interfaces with support for 4 USB ports, ACPI Power Management Logic Support, an enhanced DMA Controller, Interrupt Controller, Timer Functions, System Management Bus (SMBus) Specification v2.0 with support for I2C devices, Low Pin Count (LPC) interface, and a Watchdog Timer.

Please refer to the following block diagram for the cPCI-3840 architecture.

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **Front Panel** (Header)\n    *   LEDs Reset\n    *   CRT Output\n    *   Giga LAN Output\n    *   USB x 2\n    *   COM Output\n    *   Power Output\n    *   SATA Output\n    *   Line-Out\n    *   MIC In\n*   **CPU Intel Pentium M**\n*   **North Bridge Intel 855GM/GME**\n*   **DDR SO-DIMM**\n*   **Intel 82546EB Dual-Giga**\n*   **South Bridge Intel 6300ESB**\n*   **Hardware Monitor**\n*   **J2 To Rear**\n*   **J1 PCI Bus**\n*   **FWH BIOS**\n*   **ALC 203 Codec**\n*   **USB (note) Connector**\n*   **SATA Connector**\n*   **CF Socket**\n*   **IDE (44 Pin)**\n*   **DVO to DVI CH7301A**\n\n**Connections:**\n*   **CPU Intel Pentium M** \$\leftrightarrow\$ **North Bridge Intel 855GM/GME**: Labeled 'System Bus'.\n*   **North Bridge Intel 855GM/GME** \$\leftrightarrow\$ **DDR SO-DIMM**: Labeled 'DDR 200/266 DDR 333 (GME)'.\n*   **North Bridge Intel 855GM/GME** \$\rightarrow\$ **CRT Output**: Labeled 'CRT (R,G,B)'.\n*   **North Bridge Intel 855GM/GME** \$\rightarrow\$ **DVO to DVI CH7301A**: Labeled 'DVO'.\n*   **DVO to DVI CH7301A** \$\rightarrow\$ **J2 To Rear**: Labeled 'DVI'.\n*   **North Bridge Intel 855GM/GME** \$\leftrightarrow\$ **South Bridge Intel 6300ESB**: Labeled 'Hub I/F 1.5'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **Intel 82546EB Dual-Giga**: Labeled 'PCI-X Bus 64bit/66MHz'.\n*   **Intel 82546EB Dual-Giga** \$\rightarrow\$ **Giga LAN Output**: Labeled 'LAN 1'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **USB x 2**: Labeled 'USB 1,2'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **COM Output**: Labeled 'COM 1'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **SATA Output**: Labeled 'SATA 1'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **Hardware Monitor**: Labeled 'SM Bus'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **J2 To Rear**: Labeled 'LAN 2', 'USB 3', and 'COM 2'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **J1 PCI Bus**: Labeled 'LPC' and 'PCI Bus 32bit/33MHz'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **ALC 203 Codec**: Labeled 'AC97 Interface'.\n*   **ALC 203 Codec** \$\rightarrow\$ **Line-Out**: Labeled 'Line Out'.\n*   **ALC 203 Codec** \$\rightarrow\$ **MIC In**: Labeled 'MIC In'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **USB (note) Connector**: Labeled 'USB4'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **SATA Connector**: Labeled 'SATA 2'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **CF Socket**: Labeled 'PIDE'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **IDE (44 Pin)**: Labeled 'SIDE'.\n*   **South Bridge Intel 6300ESB** \$\rightarrow\$ **FWH BIOS**: Connected via an unlabeled arrow.\n\n*(Note: The blocks 'LEDs Reset', 'Power Output' have no connections shown in the diagram.)*](.cpci-3840-manual-10/4d061759adcd254fa1a47fd59dc75a495b211b826579bd9396ed1826d991c10f.jpg)

Figure 1-1: cPCI-3840 Architecture

# 1.1 Features

The features of the cPCI-3840 are as follows:

▶ Designed for Micro-FCPGA478/ Micro-FCBGA479 Pentium-M 400MHz PSB processor with 1MB L2 cache
▶ Supports up to two double-sided 200-pin SODIMMs with up to a total of 2GB of RAM with unbuffered PC2100/PC2700 DDR-SDRAM with or without ECC (64-bit data interface with ECC SODIMM, 72-bit with ECC SODIMM)
▶ One VGA output supports resolution up to 1600 x 1200 at 85Hz and up to 2048 x 1536 at 75Hz.
▶ Digital display interface supports one port DVO with 165MHz output clock on each 12-bit interface.
▶ Hardware Monitoring for system voltages and CPU temperature.
▶ Supports analog display (RGB) and digital display (DVO).
▶ Up to 64MB of dynamic video memory allocation
▶ Supports Intel® Architecture with Dynamic Execution
▶ CPU temperature monitoring.

# 1.2 Main Functions

The cPCI-3840 CPU Module is designed for the Intel® Pentium® M and Celeron® M Processors. The standard cPCI-3840 CPU Module comes with a CPU socket which can be installed with a Micro-FC-PGA package CPU, including the following options:

▶ Pentium® M 1.3GHz, 1.4GHz, 1.5GHz and 1.6GHz
▶ Celeron® M 1.3GHz

The Low Voltage (LV) or Ultra Low Voltage (ULV) versions of the Pentium® M or Celeron® M Processors in the Micro-FCBGA2 package can also be mounted on the cPCI-3840 CPU Module. However, Micro-FCBGA package support is reserved for OEM programs only. The possible CPU options include:

▶ LV Pentium® M 1.1, 1.2, 1.3GHz
▶ ULV Celeron® M 600MHz

# CompactPCI Bus Interface

The Intel® 6300ESB south bridge chipset supports one PCI 33MHz / 32bits interface compliant with the PCI Local Bus Specification, Revision 2.2. The throughput of this PCI bus interface is 132 MB/s, and it supports 44 bit addressing using DAC protocol.

The 6300ESB also supports one PCIX 66MHz / 64-bits interface which is compliant with the PCIX Bus specification, revision 1.0 and is also compliant with the PCI Local Bus Specification, Revision 2.2. The throughput of this PCIX bus is up to 480 MB/s. It supports 64-bit addressing on PCI-X using DAC protocol.

# IDE Interfaces

The cPCI-3840 supports dual Ultra ATA33/66/100 IDE channels. The primary IDE is implemented to CompactFlash (CF) interface and the secondary IDE is connected to a 40-pin slim-type IDE connector. The 6300ESB IDE controller supports both legacy mode and native mode IDE interfaces. In native mode, the IDE controller is a fully PCI compliant software interface and does not use any legacy I/O or interrupt resources. Note that for Ultra ATA100/66 mode operations, the proper cables must be installed.

# Gigabit Ethernet Ports

The cPCI-3840 has two 10/100/1000Mbps Ethernet (GbE) ports. Every port is assigned a unique static MAC Address. The BIOS menu can be setup to disable or enable these two LAN ports.

The onboard Intel® 82546EB Dual Port Gigabit Ethernet Controller provides two Ethernet ports. The 82546EB is implemented on the 64-bit/66-MHz PCI-X bus to achieve the full communication. The 82546EB supports IEEE 802.3x compliant flow control and IEEE 802.3ab compliant 10/100/1000 Mbps auto-negotiation. One port is connected to the front panel and the other to rear panel via J2 (see Chapter 2, Jumpers and Connectors).

# Universal Serial Bus (USB)

The cPCI-3840 employs one EHCI USB 2.0 Host Controller that compliments the UHCI interfaces on the south bridge for a total of five USB ports. Two USB ports are on the front panel, one is internal, and the remaining two are connected to the rear panel. Overcurrent detection on all USB ports is supported. USB legacy devices, such as keyboard, mouse and floppy drive are supported and can be enabled/disabled in BIOS options. In addition, USB devices boot feature is also implemented on all USB ports.

# Serial I/O

The serial port consists of a UART which supports all functions of a standard 16550 UART, including hardware flow control interface. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the processor.

# SATA

The 6300ESB I/O Controller Hub SATA controller features two sets of interface signals that may be independently enabled, tri-stated or driven low. Each interface is supported by an independent DMA controller. The controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions.

# Watchdog Timer

The cPCI-3840 implements a 2-stage Watchdog Timer (WDT) that is embedded on the 6300ESB and can be enabled/disabled in BIOS options. The WatchDog Timer supports selectable prescaler: approximately 1 MHz (1 us to 1 s) and approximately 1 KHz (1 ms to 10 min). The 2-stage WDT mode performs the following steps when the programmed time is up. First, it generates IRQ, SMI, or SCI interrupts. Second, it drives WDT\_OUT# low and resets the cPCI-3840.

# Hardware Monitoring

The onboard Winbond W83L784R Hardware Monitor tracks critical hardware parameters, including system and CPU voltages and system temperature. All hardware health status can be accessed in the BIOS options menu and using run-time utilities. In addition, once the preset thresholds of the hardware conditions are met, the W83L784R will alert the system or reset the entire system in critical situations. The The onboard Analog Devices ADM1032 is an ACPI compliant two-channel digital thermometer and under/over temperature alarm that allows the cPCI-3840 to be programmable for under/over temperature limits.

# Operating System Support

The cPCI-3840 is compatible with Windows XP/2000/NT/Server 2003, and Linux Red Hat 9.0. The device drivers for Windows are included in the ADLINK All-in-One CD. For other Linux support and VxWorks BSP, please contact ADLINK.

# 1.3 Specifications

# Specifications of the cPCI-3840 CPU Module

# CompactPCI Compliancy

▶ PCI Rev. 2.1 compliant
▶ PICMG 2.0 CompactPCI Rev. 3.0 Compliant
▶ PICMG 2.1 CompactPCI Hot Swap Specification R2.0 Compliant

# Form Factor

▶ Standard 3U CompactPCI: 160 mm x 100 mm board size
▶ Dual Slot, 8TE/HP width

# CPU/Cache

▶ Single Intel® Pentium® M 1.3/1.4/1.5/1.6 GHz or Celeron M 1.3 GHz Processors with Micro-FC-PGA package
▶ 1MB on die L2 cache, 400MHz FSB

# Chipset

Intel® 855GME Graphic Memory Controller Hub (GMCH)
Intel® 6300ESB I/O Hub Controller

# Host Memory

▶ Two SODIMM sockets, 2GB maximum
▶ Supports DDR266/333 SDRAM with ECC capability

# BIOS

▶ Phoenix/Award Plug and Play BIOS with 4MB Flash ROM
▶ System BIOS flash, SST 49LF004A, in 4MB capacity, is compatible with Intel® 82802 Firmware Hub (FWH) device.
▶ BIOS write protection, provides anti-virus capability
▶ Bootable from USB storage devices including USB-Floppy, USB-ZIP, USB-CD-ROM, and USB-HDD.

▶ On-board Ethernet ports can be disabled using BIOS settings. BIOS write-protect function can be enabled/disabled in the BIOS options menu.

# CompactPCI Bus Controller

Intel® 6300ESB PCI Bus Interface Controller

▶ PCI Local Bus Specification Revision 2.2 compaliant

▶ Support 32-bit/33MHz

# Graphic

▶ Integrated in 855GME Graphics Memory Control Hub.
▶ Shared memory, up to 32MB
▶ Dual Channel Display
▶ Front Panel analog VGA DB-15 connector is available

# Gigabit Ethernet

▶ Dual 10/100/1000bps Gigabit Ethernet ports provided by Intel® 82546EB Ethernet controller on local 66MHz/64-bit PCI-X bus; front panel and RTM rear access

# Onboard Peripherals

▶ Integrated in Intel® 6300ESB south bridge
▶ Bus master IDE controller supports ultra ATA-100 interface
▶ Primary IDE on SBC with 44-pin IDE connector. A 2.5" IDE HDD can be mounted
▶ All USB ports are USB Spec Rev. 2.0 compliant
▶ USB 1, 2 are on the front panel
▶ USB 3 is on the RTM Panel
▶ USB ports support 0.5A@5V for peripherals with individual over-current protection
▶ Supports DB-9 COM1 Serial Port on the front panel and DB-9 COM2 on the RTM
▶ Supports one RJ-45 GbE port on the front panel and one RJ-45 GbE port on RTM
▶ Supports one SATA port and external power connector on the front panel
▶ Speaker out and MIC IN ports provided on the front panel

# Front Panel LED Indicators and Reset

▶ 4 LEDs on the front panel including storage access LED (red), Power LED (green), General Purpose Status (Blue), and Watchdog timer LED (Yellow)
▶ Flush tact switch for system reset

# Real -Time Clock and Nonvolatile Memory

Built-in Intel® 6300ESB south bridge RTC
▶ Battery-backed memory used for BIOS configurationm
▶ Separate 3V coin cell CR2032 battery used for RTC and nonvolatile memory

# Environment

▶ Operating ambient temperature: -5 to 55 °C
▶ Storage temperature: -20 to 80 °C
▶ Humidity: 5% to 95% non-condensed
▶ Shock: 15G peak-to-peak, 11ms duration, non-operation
▶ Vibration:

▶ Non-operation: 1.88Grms, 5-500Hz, each axis
Operation: 0.5Grms, 5-500Hz, each axis, with 2.5" HDD

# Safety Certificate and Test

▶ CE, FCC Class B
▶ All plastic material, PCB and batteries used are UL-94V0 certified
▶ Designed for NEBS 3.0 requirements

Power Requirements

<table><tr><td>Full Loading</td><td>+5V</td><td>+3.3V</td><td>Total Power</td></tr><tr><td>Pentium® M1.6GHz CPU,512MB x 2 DDR, 40G HD</td><td>3.16A</td><td>2.39A</td><td>23.6878 W</td></tr><tr><td>Pentium® M1.1GHz CPU,512MB x 2 DDR, 40G HD</td><td>1.875A</td><td>1.746A</td><td>15.1368 W</td></tr><tr><td>Celeron M1.3GHz CPU,512MB x 2 DDR, 40G HD</td><td>2.44A</td><td>1.683A</td><td>17.7539 W</td></tr><tr><td>Dothan1.8GHz CPU,512MB x 2 DDR, 40G HD</td><td>3.334A</td><td>1.524A</td><td>21.6992 W</td></tr></table>

Table 1-1: Mean Power Consumption

# cPCI-R3840 RTM Specifications

The cPCI-R3840 is a rear transition module designed for the cPCI-3840. It comes with one LAN port, one USB port, one DVI connector, and one DB-9 serial port.

# Form Factor

▶ Standard 3U CompactPCI rear I/O
▶ 2 Slot (8TE/HP, 40.64 mm) wide

# Faceplate I/O Connectors

▶ One GbE ports on RJ-45 connector
▶ One DVI connector
▶ One COM2 port on DB-9 connector
▶ One USB port

I/O Connectivity Table

<table><tr><td rowspan="2">I/O</td><td colspan="2">cPCI-3840</td><td colspan="2">cPCI-R3840</td></tr><tr><td>Face-plate</td><td>On-board</td><td>Face-plate\</td><td>On-board</td></tr><tr><td>Serial Port (COM1)</td><td>DB-9</td><td>--</td><td>--</td><td>--</td></tr><tr><td>Serial Port (COM2)</td><td>--</td><td>--</td><td>DB-9</td><td>--</td></tr><tr><td>USB (port 1, port 2)</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>USB (port 3)</td><td>--</td><td>--</td><td>Y</td><td>--</td></tr><tr><td>Gigabit Ethernet Port 1</td><td>RJ-45</td><td>--</td><td>RJ-45</td><td>--</td></tr><tr><td>Gigabit Ethernet Port 2</td><td>--</td><td>--</td><td>--</td><td>--</td></tr><tr><td>IDE</td><td>--</td><td>44-pin</td><td>--</td><td>--</td></tr><tr><td>General Purpose LED</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>Reset button</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>Speaker Out</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>MIC In</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>VGA</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>SATA</td><td>Y</td><td>Y</td><td>--</td><td>--</td></tr><tr><td>SATA Power Connector</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>CF Socket</td><td>--</td><td>Y</td><td>--</td><td>--</td></tr><tr><td>DVI-D</td><td>--</td><td>--</td><td>Y</td><td>--</td></tr></table>

Table 1-2: I/O Connectivity

# 1.4 Unpacking Checklist

Before opening the product box, please check the shipping carton for any damages. If the shipping carton and contents are damaged, notify the dealer for a replacement. Retain the shipping carton and packing material for inspection by the dealer. Obtain authorization before returning any product to ADLINK.

Check the following items are included in the package, if there are any missing items, contact your dealer:

# CPU Module:

The cPCI-3840 CPU Module (CPU, RAM, and HDD specifications will differ depending on options selected)
▶ Heat sink kit (incl. thermal pad and heat sink paste)
▶ HDD bracket
▶ SATA Cable and SATA power cable
▶ 44-pin IDE cable
▶ ADLINK All-in-One CD
This user's manual

# RTM:

▶ cPCI-R3840 RTM

Note: The packing contents of cPCI-3840 OEM non-standard configurations may vary and is dependent on customer requests.

![A yellow triangular warning sign with a black border and a red exclamation mark in the center.](.cpci-3840-manual-10/2b66dd4ea661592df3e8a2e42c7477c887c54300a7d5a84af70c574c70a8bb7e.jpg)

: This board must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the board. Wear a wrist strap grounded through one of the system's ESD Ground jacks when servicing system components.

# 2 Jumpers and Connectors

This chapter illustrates the board layout, connector pin assignments, and jumper setup. Users should familiarize themselves with the products before use. The following sections are included:

▶ cPCI-3840 board outline
▶ cPCI-3840 connectors pin assignments
▶ cPCI-3840 jumpers setting
▶ cPCI-R3840 RTM board outline
▶ cPCI-R3840 RTM connectors pin assignments

# 2.1 cPCI-3840 Board Outline

![40.2\n128.7 122.625\n25.41\n100\n162.54](.cpci-3840-manual-10/7c38800d2e1b32fd11bc61c8b9757a1ddcebaf7dc40ee9f9b9a884c63cd75e8d.jpg)

Figure 2-1: cPCI-3840 Front View and Top View
![B\nC\nD\nA](.cpci-3840-manual-10/a60a5ad9f4ea2f7640b971fb078e52c3d5ede0a3a526b764443c232c5fab22a2.jpg)

Figure 2-2: cPCI-3840 Carrier Board Top View

<table><tr><td>A</td><td>Clear CMOS jumper (JP2)</td><td>C</td><td>CF connector (IDE0)</td></tr><tr><td>B</td><td>Slim-type IDE (IDE1)</td><td>D</td><td>CF master/slave (CN5)</td></tr></table>

Table 2-1: Jumper and Connector Locations

# 2.2 cPCI-3840 Connector Pin Assignments

# USB Connectors

![4\n3\n2\n1](.cpci-3840-manual-10/417418feda73471bc325dc33a7a8336b7382470e34d796faaff64cc929017d98.jpg)

<table><tr><td>PIN</td><td>SIGNAL</td></tr><tr><td>1</td><td>VCC</td></tr><tr><td>2</td><td>USB-</td></tr><tr><td>3</td><td>USB+</td></tr><tr><td>4</td><td>Ground</td></tr></table>

# Ethernet (RJ-45) Connector

Yellow / Amber LED
![Pin 1\nPin 2\nPin 3\nPin 8](.cpci-3840-manual-10/e0fbb4388c3d34d67dbbd3e0d9d21a61e2f011e7298f36f844bb2a5c8eab3359.jpg)

Amber LED

<table><tr><td>Pin #</td><td>Signal Name</td><td>Function</td></tr><tr><td>1</td><td>LAN_TDP1</td><td>Transmit Data1 +</td></tr><tr><td>2</td><td>LAN_TDN1</td><td>Transmit Data1 -</td></tr><tr><td>3</td><td>LAN_RDP2</td><td>Receive Data2 +</td></tr><tr><td>4</td><td>LAN_RDP3</td><td>Receive Data3 +</td></tr><tr><td>5</td><td>LAN_RDN3</td><td>Receive Data3 -</td></tr><tr><td>6</td><td>LAN_RDN2</td><td>Receive Data2 +</td></tr><tr><td>7</td><td>LAN_TDP4</td><td>Transmit Data4 +</td></tr><tr><td>8</td><td>LAN_TDN4</td><td>Transmit Data4 -</td></tr></table>

<table><tr><td colspan="2">Status</td><td>Left LED (Amber)</td><td>Right LED (Yellow or Amber)</td></tr><tr><td colspan="2">Network link is not established</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps (10 BaseT)</td><td>Link</td><td>Amber</td><td>OFF</td></tr><tr><td>Active</td><td>Blinking Amber</td><td>OFF</td></tr><tr><td rowspan="2">100 Mbps (100 BaseTX)</td><td>Link</td><td>Amber</td><td>Yellow</td></tr><tr><td>Active</td><td>Blinking Amber</td><td>Yellow</td></tr></table>

<table><tr><td rowspan="2">1000 Mbps(1000 BaseT)</td><td>Link</td><td>Amber</td><td>Amber</td></tr><tr><td>Active</td><td>Blinking Amber</td><td>Amber</td></tr></table>

Table 2-2: Ethernet LED Status

# VGA Connector

![5\n10\n15\n11](.cpci-3840-manual-10/6f5cb1699fbb05702adc62f2a05b3a78089a2f7f1b07d6ebdd7fe210a2507f09.jpg)

<table><tr><td>Signal Name</td><td>Pin</td><td>Pin</td><td>Signal Name</td></tr><tr><td>Red</td><td>1</td><td>2</td><td>Green</td></tr><tr><td>Blue</td><td>3</td><td>4</td><td>N.C.</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>+5V</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>N.C.</td><td>11</td><td>12</td><td>DDCDAT</td></tr><tr><td>HSYNC</td><td>13</td><td>14</td><td>VSYNC</td></tr><tr><td>DDCCLK</td><td>15</td><td></td><td></td></tr></table>

# RS-232 DB-9 Serial Port Connector (COM1)

![6\n1\n5](.cpci-3840-manual-10/ea9c371ea66e0464c577aed1da7a410e9e8500c94bbb2b819d2e37fffb57580b.jpg)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD, Data carrier detect</td></tr><tr><td>2</td><td>RXD, Receive data</td></tr><tr><td>3</td><td>TXD, Transmit data</td></tr><tr><td>4</td><td>DTR, Data terminal ready</td></tr><tr><td>5</td><td>IsoGND, Isolated ground</td></tr><tr><td>6</td><td>DSR, Data set ready</td></tr><tr><td>7</td><td>RTS, Request to send</td></tr><tr><td>8</td><td>CTS, Clear to send</td></tr><tr><td>9</td><td>RI, Ring indicator</td></tr></table>

# SATA Connector

![6\n5\n3\n2\n7\n4\n1](.cpci-3840-manual-10/cef9b776741e208008be8f16d435e0a73eab3b823c904ebc9ce3d5e2329d30c7.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>5</td><td>RXN</td></tr><tr><td>2</td><td>TXP</td><td>6</td><td>RXP</td></tr><tr><td>3</td><td>TXN</td><td>7</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td></td><td></td></tr></table>

# IDE Connector

![1\n2\n43\n44](.cpci-3840-manual-10/e45355ee3aa12a773d61e2d442c33beed679ab2456af815e0333296d84c53c81.jpg)

<table><tr><td>Signal Name</td><td>Pin</td><td>Pin</td><td>Signal Name</td></tr><tr><td>BRSTDRVJ</td><td>1</td><td>2</td><td>GND</td></tr><tr><td>DDP7</td><td>3</td><td>4</td><td>DDP8</td></tr><tr><td>DDP6</td><td>5</td><td>6</td><td>DDP9</td></tr><tr><td>DDP5</td><td>7</td><td>8</td><td>DDP10</td></tr><tr><td>DDP4</td><td>9</td><td>10</td><td>DDP11</td></tr><tr><td>DDP3</td><td>11</td><td>12</td><td>DDP12</td></tr><tr><td>DDP2</td><td>13</td><td>14</td><td>DDP13</td></tr><tr><td>DDP1</td><td>15</td><td>16</td><td>DDP14</td></tr><tr><td>DDP0</td><td>17</td><td>18</td><td>DDP15</td></tr><tr><td>GND</td><td>19</td><td>20</td><td>NC</td></tr><tr><td>PDDREQ</td><td>21</td><td>22</td><td>GND</td></tr><tr><td>PDIOWJ</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>PDIORJ</td><td>25</td><td>26</td><td>GND</td></tr><tr><td>PIORDY</td><td>27</td><td>28</td><td>PCSEL</td></tr><tr><td>PDDACKJ</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>IRQ14</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>DAP1</td><td>33</td><td>34</td><td>DIAG</td></tr><tr><td>DAP0</td><td>35</td><td>36</td><td>DAP2</td></tr><tr><td>CS1P</td><td>37</td><td>38</td><td>CS3PJ</td></tr><tr><td>IDEACTPJ</td><td>39</td><td>40</td><td>GND</td></tr><tr><td>+5V</td><td>41</td><td>42</td><td>+5V</td></tr><tr><td>GND</td><td>43</td><td>44</td><td>NC</td></tr></table>

# CompactFlash Connector

![10\n25\n27 26\n2 2](.cpci-3840-manual-10/b78dd013d362d8ddddaee0f3e1aecf93f55b49b1122665503195743203b35491.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>18</td><td>DA2</td><td>35</td><td>SDIOWJ</td></tr><tr><td>2</td><td>DD3</td><td>19</td><td>DA1</td><td>36</td><td>5V</td></tr><tr><td>3</td><td>DD4</td><td>20</td><td>DA0</td><td>37</td><td>IRQ15</td></tr><tr><td>4</td><td>DD5</td><td>21</td><td>DD0</td><td>38</td><td>5V</td></tr><tr><td>5</td><td>DD6</td><td>22</td><td>DD1</td><td>39</td><td>PCSEL</td></tr><tr><td>6</td><td>DD7</td><td>23</td><td>DD2</td><td>40</td><td>NC</td></tr><tr><td>7</td><td>CS1J</td><td>24</td><td>IOIS16J</td><td>41</td><td>BRSTDRVJ</td></tr><tr><td>8</td><td>GND</td><td>25</td><td>GND</td><td>42</td><td>SDIORDY</td></tr><tr><td>9</td><td>GND</td><td>26</td><td>GND</td><td>43</td><td>NC</td></tr><tr><td>10</td><td>GND</td><td>27</td><td>DD11</td><td>44</td><td>SDACKJ</td></tr><tr><td>11</td><td>GND</td><td>28</td><td>DD12</td><td>45</td><td>IDEACTJ</td></tr><tr><td>12</td><td>GND</td><td>29</td><td>DD13</td><td>46</td><td>DIAG</td></tr><tr><td>13</td><td>5V</td><td>30</td><td>DD14</td><td>47</td><td>DD8</td></tr><tr><td>14</td><td>GND</td><td>31</td><td>DD15</td><td>48</td><td>DD9</td></tr><tr><td>15</td><td>GND</td><td>32</td><td>CS3J</td><td>49</td><td>DD10</td></tr><tr><td>16</td><td>GND</td><td>33</td><td>GND</td><td>50</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>34</td><td>SDIORJ</td><td></td><td></td></tr></table>

# General Purpose LED Definitions

<table><tr><td>LED</td><td>Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="2">IDE Media Access</td><td rowspan="2">Red</td><td>OFF</td><td>IDE idle</td></tr><tr><td>ON</td><td>IDE access</td></tr><tr><td rowspan="2">Power OK</td><td rowspan="2">Green</td><td>OFF</td><td>System is not power-on or power failed</td></tr><tr><td>ON</td><td>Power ON</td></tr><tr><td rowspan="2">Hot-swap status</td><td rowspan="2">Blue</td><td>OFF</td><td>Board inserted and power on OK.</td></tr><tr><td>ON</td><td>Board inserted but not power on yet.</td></tr><tr><td rowspan="2">WDT LED</td><td rowspan="2">Yellow</td><td>OFF</td><td>WDT is not enabled</td></tr><tr><td>Blinking</td><td>WDT is enabled</td></tr></table>

CompactPCI J2 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>GA4(2)</td><td>GA3(2)</td><td>GA2(2)</td><td>GA1(2)</td><td>GA0(2)</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>BRSV(1)</td><td>BRSV(1)</td><td>BRSV(1)</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>BRSV(1)</td><td>GND</td><td>BRSV(1)</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>ICMBSDA(1)</td><td>ICMBSCL(1)</td><td>ICMBALR(1)</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>BRSV(1)</td><td>BRSV(1)</td><td>BRSV(1)</td><td>GND</td><td>BRSV(1)</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>BRSV(1)</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>BRSV(1)</td><td>BRSV(1)</td><td>DEG#</td><td>GND</td><td>BRSV(1)</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>BRSV(1)</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD [35]</td><td>AD [34]</td><td>AD [33]</td><td>GND</td><td>AD [32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD [38]</td><td>GND</td><td>V (I/O)(1)</td><td>AD [37]</td><td>AD [36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD [42]</td><td>AD [41]</td><td>AD [40]</td><td>GND</td><td>AD [39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD [45]</td><td>GND</td><td>V (I/O)(1)</td><td>AD [44]</td><td>AD [43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD [49]</td><td>AD [48]</td><td>AD [47]</td><td>GND</td><td>AD [46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD [52]</td><td>GND</td><td>V (I/O)(1)</td><td>AD [51]</td><td>AD [50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD [56]</td><td>AD [55]</td><td>AD [54]</td><td>GND</td><td>AD [53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD [59]</td><td>GND</td><td>V (I/O)(1)</td><td>AD [58]</td><td>AD [57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD [63]</td><td>AD [62]</td><td>AD [61]</td><td>GND</td><td>AD [60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE [5]\#</td><td>GND</td><td>V (I/O)(1)</td><td>C/BE [4]\#</td><td>PAR 64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V (I/O)(1)</td><td>BRSV(1)</td><td>C/BE [7]\#</td><td>GND</td><td>C/BE [6]\#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ#4</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr></table>

CompactPCI J3 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LPA_DA+</td><td>LPA_DA-</td><td>GND</td><td>LPA_DC+</td><td>LPA_DC-</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LPA_DB+</td><td>LPA_DB-</td><td>GND</td><td>LPA_DD+</td><td>LPA_DD-</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>LPB_DA+</td><td>LPB_DA-</td><td>GND</td><td>LPB_DC+</td><td>LPB_DC-</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>LPB_DB+</td><td>LPB_DB-</td><td>GND</td><td>LPB_DD+</td><td>LPB_DD-</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GND</td><td>2.5V</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>LANA_1G#</td><td>LANA_100#</td><td>ACTA#</td><td>LINKA#</td><td>LANB_1G#</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>LINKB#</td><td>LANB_100#</td><td>ACTB#</td><td>5V(1)</td><td>5V(1)</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>IYAM0</td><td>IYAM1</td><td>IYAM2</td><td>IYAM3</td><td>ICLKAM</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>IYAP0</td><td>IYAP1</td><td>IYAP2</td><td>IYAP3</td><td>ICLKAP</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>IYBM0</td><td>IYBM1</td><td>IYBM2</td><td>IYBM3</td><td>ICLKBM</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>IYBP0</td><td>IYBP1</td><td>IYBP2</td><td>IYBP3</td><td>ICLKBP</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CTS#</td><td>DSR#</td><td>RTS#</td><td>DTR#</td><td>NC</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>HSYNC</td><td>VSYNC</td><td>SIN</td><td>SOUT</td><td>DCD#</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>RED</td><td>GREEN</td><td>BLUE</td><td>DDCDATA</td><td>DDCCLK</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>TMDS1_TX1N</td><td>TMDS1_TX2N</td><td>TMDS1_TX3N</td><td>TMDS1_TXCN</td><td>TMDS_I2CC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>TMDS1_TX1P</td><td>TMDS1_TX2P</td><td>TMDS1_TX3P</td><td>TMDS1_TXCP</td><td>TMDS_I2CD</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>LVDS_VDDEN</td><td>LVDS_TEN</td><td>LVDS_TCTL</td><td>NC</td><td>HTPLG</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>KBCLK</td><td>KBDATA</td><td>MSCLK</td><td>MSDATA</td><td>3.3V(1)</td><td>GND</td></tr></table>

# 2.3 Switch and Jumper Setting

The following table lists the switch and jumpers on the cPCI-3840.

<table><tr><td>Switch</td><td>Function</td></tr><tr><td>SW1</td><td>Reset</td></tr><tr><td>CN5</td><td>CF Master/Slave</td></tr><tr><td>JP2</td><td>Clear CMOS Content</td></tr></table>

Table 2-3: Switches and Jumpers

# Reset Button (SW1)

SW1 is a push-button on the front panel. Pressing SW1 generates a hard reset.

# CF Master/Slave Setting (CN5)

CN5 is 3-pin jumper that can select CF device to be IDE master/slave (see Figure 1b above for its location on the carrier board).

<table><tr><td>Status</td><td>CN5</td></tr><tr><td>Slave (Default)</td><td>1 2 3&lt;img src="images/186e05163f15f456b0a2bce3073086a83ec9190ac38f032d73e6da720cbb02d4.jpg"/&gt;</td></tr><tr><td>Master</td><td>1 2 3&lt;img src="images/dbf103416e0acb3d2ab494d9ba2508d7d9b50457ee51eb67a7b40b983eb9ee86.jpg"/&gt;</td></tr></table>

Table 2-4: CN5 CF Master/Slave Setting

# Clear CMOS (JP2)

JP2 is 3-pin jumper that can be used to clear the CMOS memory (see Figure above for its location on the carrier board). The CMOS RAM stores the real time clock (RTC) information, BIOS configuration, and default BIOS setting. The CMOS is powered by the button cell battery when the system is powered off.

Please follow the following steps to erase the CMOS RAM data:

1. Remove the cPCI-3840 CPU Module from chassis.
2. Short pins 2 and 3 of JP2, then reinstall the jumper to normal location.
3. Insert the CPU Module back into the chassis.

<table><tr><td>Status</td><td>JP2</td></tr><tr><td>Normal operation (Default)</td><td>&lt;img src="images/82c1d2de2e71a4ad5b024071422deff3798d1720a3485c511c646bee2aaf4299.jpg"/&gt;</td></tr><tr><td>Clear CMOS</td><td>&lt;img src="images/3a6d58f45660618c9807efb72dd4403d1b001edca72869bb357d570fc8fd44f1.jpg"/&gt;</td></tr></table>

Table 2-5: JP2 Clear CMOS

# 2.4 cPCI-R3840 RTM Board Outline

The cPCI-R3840 is a rear transition module designed for the cPCI-3840. It comes with one LAN port, one USB port, one DVI connector, and one DB-9 serial port.

![CompuoFCI®\nCOM2\nTX1\nCANE LAN2\nUSB0](.cpci-3840-manual-10/2517ee82a876384723ca88499829d4bcace1d611c259857f668d5cfb68c7056b.jpg)

Figure 2-3: cPCI-R3840 Front View and Top View

![Technical line drawing of a mechanical assembly (no text or symbols)](.cpci-3840-manual-10/5f8c043d6dd5a072fc2f3c3da6100903a4e76c67c4cd0d5ed98a8fe91e74234b.jpg)

Figure 2-4: Side View of cPCI-R3840

# 2.5 cPCI-R3840 RTM Connector Pin Assignments

The connector pin assignments of the cPCI-R3840 Rear Transition Module's RJ-45 GbE port, USB port, and DB-9 serial port COM2 are identical to those of the cPCI-3840 CPU Module. Please refer to Section 2.2.

The pin assignments for the DVI connector and RJ2 connector are as follows:

# DVI Connector

![1 0200000000000\n9 0200000000000\n17 0200000000000\no29\no25o36\no27o28\no30](.cpci-3840-manual-10/600f208ceb6bdffcf242630b968fa624278581447bcc8f963c88999f9ce3ead8.jpg)

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>TX2-</td><td>13</td><td>NC</td></tr><tr><td>2</td><td>TX2+</td><td>14</td><td>+5V</td></tr><tr><td>3</td><td>GND</td><td>15</td><td>GND</td></tr><tr><td>4</td><td>NC</td><td>16</td><td>HTPLG</td></tr><tr><td>5</td><td>NC</td><td>17</td><td>TX0-</td></tr><tr><td>6</td><td>I2CCLK</td><td>18</td><td>TX0+</td></tr><tr><td>7</td><td>I2CDATA</td><td>19</td><td>GND</td></tr><tr><td>8</td><td>VSYNC</td><td>20</td><td>NC</td></tr><tr><td>9</td><td>TX1-</td><td>21</td><td>NC</td></tr><tr><td>10</td><td>TX1+</td><td>22</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>23</td><td>TXC+</td></tr><tr><td>12</td><td>NC</td><td>24</td><td>TXC-</td></tr></table>

cPCI-R3840 RJ2 Pin Assignment

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>RJ2-22</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>RJ2-21</td><td>CLK6</td><td>GND</td><td>ICLKAP</td><td>1000LEDJ</td><td>IYAP3</td><td>GND</td></tr><tr><td>RJ2-20</td><td>CLK5</td><td>GND</td><td>ICLKAM</td><td>GND</td><td>IYAM3</td><td>GND</td></tr><tr><td>RJ2-19</td><td>GND</td><td>GND</td><td>SMBDATA</td><td>SMBCLK</td><td>SMBALERT</td><td>GND</td></tr><tr><td>RJ2-18</td><td>IYAP1</td><td>IYAP2</td><td>IYAM2</td><td>GND</td><td>100LEDJ</td><td>GND</td></tr><tr><td>RJ2-17</td><td>IYAM1</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>RJ2-16</td><td>IYAP0</td><td>ACLEDJ</td><td>DEG#</td><td>GND</td><td>LILEDJ</td><td>GND</td></tr><tr><td>RJ2-15</td><td>IYAM0</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>RJ2-14</td><td>COM2_RIJ</td><td>COM2_TXD</td><td>COM2_DTRJ</td><td>GND</td><td>GL_MDIB2-</td><td>GND</td></tr><tr><td>RJ2-13</td><td>COM2_RXD2</td><td>GND</td><td>VIO</td><td>GL_MDIB3-</td><td>GL_MDIB2+</td><td>GND</td></tr><tr><td>RJ2-12</td><td>COM2_CTSJ</td><td>COM2_DCDJ</td><td>COM2_DSRJ</td><td>GND</td><td>GL_MDIB3+</td><td>GND</td></tr><tr><td>RJ2-11</td><td>COM2_RTSJ</td><td>GND</td><td>VIO</td><td>GL_MDIB0+</td><td>GL_MDIB0-</td><td>GND</td></tr><tr><td>RJ2-10</td><td>TMDS_TXCP</td><td>TMDS_TXCN</td><td>RESERVE</td><td>GND</td><td>GL_MDIB1+</td><td>GND</td></tr><tr><td>RJ2-9</td><td>TMDS_HPDET</td><td>GND</td><td>VIO</td><td>NC</td><td>GL_MDIB1-</td><td>GND</td></tr><tr><td>RJ2-8</td><td>TMDS_TX3P</td><td>TMDS_TX3N</td><td>PANEL_I2CD</td><td>GND</td><td>USB_OCJ3</td><td>GND</td></tr><tr><td>RJ2-7</td><td>PANEL_I2CC</td><td>GND</td><td>VIO</td><td>USBP3+</td><td>USBP3-</td><td>GND</td></tr><tr><td>RJ2-6</td><td>TMDS_TX2N</td><td>TMDS_TX1P</td><td>TMDS_TX1N</td><td>GND</td><td>R_GB_+2.5V</td><td>GND</td></tr><tr><td>RJ2-5</td><td>TMDS_TX2P</td><td>GND</td><td>VIO</td><td>NC</td><td>PAR64</td><td>GND</td></tr><tr><td>RJ2-4</td><td>VIO</td><td>BRSV</td><td>R_+3.3V</td><td>GND</td><td>R_+5V</td><td>GND</td></tr><tr><td>RJ2-3</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>RJ2-2</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>RJ2-1</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr></table>

# 3 Getting Started

This chapter provides information on how to install necessary components for the cPCI-3840 and cPCI-R3840 RTM, including:

▶ CPU installation
▶ Memory module installation
▶ CF installation
▶ CPU Core Module removal and installation
▶ Heat sink and 2.5" HDD installation
▶ cPCI-3840 CPU Module installation
▶ cPCI-3840 RTM installation

Depending on the options selected for your cPCI-3840, installation of the CPU, RAM, heat sink, and HDD may or may not be required. Please skip over any unnecessary steps.

# 3.1 Installing the CPU

The cPCI-3840 supports the Intel® Pentium® M and Celeron® M processors. The CPU socket is located in the middle of the CPU Core Module as shown in Figure 4 below.

Remove the CPU from its packaging and place it carefully in the CPU socket as shown in Figure 4 below. Be sure to align the gold triangle on the corner of the chip with the corner of the socket that is missing a pin. Press down gently on the chip to ensure that it is securely in place, and then use a small flathead screwdriver to lock the CPU into position.

![Gold Triangle\nCPU\nCPU Socket\nCPU Lock Actuator\nCPU Core Module\nLocked Unlocked](.cpci-3840-manual-10/0cd09a622b3db2b917c15f5860ac795ead1dc8b96a67a1da6b741bc01432d78d.jpg)

Figure 3-1: CPU Installation.

# 3.2 Memory Module Installation

The cPCI-3840 CPU Module supports 144-bit wide PC2100/PC2700 registered/unregistered ECC DDR DIMM up to 2GB maximum. Two memory sockets are located on the CPU Core Module (one on each side). If memory modules are pre-installed when the package is received, this section may be skipped.

# Installing the First Memory Module

Please refer to the figure below to install the first memory module. Insert the module at a 30 degree angle and push the module firmly but gently into the slot until the security latches on the sockets have locked into place on each side of the module. (Note: There is a middle alignment key on 144 pin memory module which should help users with installation.)

![Memory Module\nMemory Socket\nCPU Core Module](.cpci-3840-manual-10/de2717cbdfbee400cd033e4ca9186871f90fc97eb94915ffd7dd460dc894d60c.jpg)

Figure 3-2: Memory Module Installation, Pt 1.
Note: Second memory socket is on underside of CPU Core Module – see below.

# Removing the CPU Core Module

The second memory socket is located on the underside of the CPU Core Module. If installation of a second memory socket is necessary, first remove the CPU Core Module by loosening the 4 screws that attach it to the carrier board. Then carefully lift it upwards by grasping it with thumb and forefinger at the points marked GRIP HERE shown in Figure 5b. This will prevent damage to the connector attaching the CPU Core Module to the carrier board.

![CPU Core Module\nGRIP HERE\nGRIP HERE\nCF Eject Button\nCF Card Socket\nBoard-to-Board Connector\nCarrier Board](.cpci-3840-manual-10/8345a171696c4d4cb02304a9186d740c29558878768c69ffc49caa32350119bd.jpg)

Figure 3-3: CPU Core Module Removal.

# Installing the Second Memory Module

Insert the second memory module into the slot shown in the figure below using the same procedure as described above for installation of the first memory module.

![CPU Core Module\nMemory Socket\nCF Card Socket\nCarrier Board](.cpci-3840-manual-10/95b1549e4590f7099998b5d4042faa223d0085bb7ec9fbbfc894d838c5ea5f5a.jpg)

Figure 3-4: Memory Module Installation, Pt. 2.

# 3.3 CF Card Installation

The CF card slot is located on the carrier board of the cPCI-3840. The CF card can be inserted and ejected with the CPU Core Module in place. However, if you are installing a second memory module, it is easier to install the CF card when the CPU Core Module has been removed.

# 3.4 CPU Core Module Installation

If you have removed the CPU Core Module to install a second memory module, you must reattach it to the carrier board. Align the 4 screw holes as shown in the figure above so that the board-to-board connector sockets of the CPU Core Module and carrier board meet properly. Then gently press down on the CPU Core Module at the points marked GRIP HERE shown in Figure 5b until it is firmly seated on the carrier board. Do not replace the screws until after you have installed the heat sink as described in Section 3.5 below.

# 3.5 Heat Sink Installation

In order to properly dissipate heat from the CPU, a heat sink is provided and must be installed before using the cPCI-3840 CPU Module. First, remove the transparent Mylar film from the white side of the thermal pad provided, and apply to the CPU as shown in the figure below. Then remove the Mylar film from the pink side of the thermal pad. (If you haven't removed the screws attaching the CPU Core Module to the carrier board, do so now – Section 3.2, Figure 5b.)

Next, remove the Mylar film from the raised block on the underside of the heat sink, being careful to leave the gray thermal pad in place. Place the heat sink over the CPU Core Module, being sure to align it so that the raised block is over the 855GME north bridge. Note that the cut-outs on the cooling fins are facing the front panel of the cPCI-3840 CPU Module. Attach the screws as shown.

Reserve the Heat Sink Paste for future use if the thermal pads should deteriorate after repeated removal and reinstallation of the heat sink.

![Mylar Film (pink)\nThermal Pad\nMylar Film (white)](.cpci-3840-manual-10/024c01d51179da800b83800feb8ac5bdbcc03142e43a601f6457f28d4dd1a13e.jpg)

Figure 3-5: Thermal Pad

Apply the thermal pad to the CPU (white side down) and remove the Mylar film from the top (pink) side of the thermal pad.

![Remove Mylar Film\ncovering gray thermal\npad on raised block\n\n855GME North Bridge](.cpci-3840-manual-10/8707f75760d63809e68922f0b072ec2a1575b1029acbd258ecc3bf3225d60348.jpg)

Figure 3-6: Heat Sink Fitting

Remove the Mylar Film covering the gray thermal pad on raised block. (Note orientation of heat sink to 855GME North Bridge.)

![Cut-out\nCut-out](.cpci-3840-manual-10/eab12c7afd486a39f83f2e4abdcbe75a0dfada564ec8954aebde4e2b42386e52.jpg)

Figure 3-7: Heat Sink Screws

Remove the Mylar Film covering the gray thermal pad on raised block. (Note orientation of heat sink to 855GME North Bridge.)

# 3.6 2.5" HDD Installation

To install a 2.5" hard drive, it is first necessary to install the mounting brackets. Follow the figure below for the installation procedure.

Then attach the IDE connector.

![Mounting Bracket\nMounting Bracket\nIDE Connector\nHDD](.cpci-3840-manual-10/d190dae763e9ce377964756830e5ced0f5afbe25ccdf54f948462bbb0d8008a6.jpg)

Figure 3-8: HDD and Mounting Bracket Installation

# 3.7 cPCI-3840 CPU Module Installation

Use the following procedure to install the cPCI-3840 CPU Module to its CompactPCI chassis.

1. Refer to the relevant chassis user manual for pre-preparation of the chassis before installing the main board. Users need to assign a slot to the board. Be sure to select the correct slot (system or peripheral) depending on the operational purpose of the board. Turn off system power at both front and rear of the chassis.
2. Remove the blank face panel from the slot.
3. Align the top and bottom edges of the board with the card guides on the chassis then slide the board into the chassis until resistance is felt.
4. Move the locking handle in an inward direction until it is fully latched. Note that slight resistance will be felt while inserting the board. If this resistance is more than under normal conditions, check to ensure that there are no bent pins on the backplane and that the board's connector pins are aligned properly with the connectors on the backplane.
5. Verify that the board is seated properly. Secure the two screws hidden behind the upper and lower ejector; connect the proper cables to the board. The system can now be powered on.

# 3.8 RTM Installation

The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-3840 series and related RTMs, make sure the RTM is the correct matching model.

Note: Use the correct RTM to enable functions (I/O interfaces) on rear side. The RTM or system board can be damaged if the incorrect RTM is used.

Some I/O ports are supported on both the front board and the RTM, including Keyboard, Mouse, VGA and USB. These I/O ports can be connected either via the front or rear modules but DO NOT access these ports on both front and rear simultaneously.

# 4 Windows Driver Installation

The following sections show the driver installation procedures for Windows 2000, Windows XP and Windows Server 2003. When installing the Windows drivers, we recommend the following steps:

1. Fully install Windows properly before installing any driver. Most of the standard I/O device drivers are included in Windows.
2. Install the chipset driver.
3. Install the graphics driver and utilities.
4. Install the LAN drivers.

It is recommended that the chipset, graphics, and LAN drivers provided on the ADLINK All-in-One CD be used to ensure compatibility. Please contact ADLINK for support for Linux drivers and VxWorks BSP.

# 4.1 Chipset Drivers Installation

1. Ensure Windows 2000/XP/Server 2003 is fully installed and running prior to executing the "Intel Chipset Software Installation Utility".
2. Close any running applications.
3. The files are stored in an integrated application setup program. This program is designed for Windows 2000, XP and Server 2003.
4. Locate the directory X:\cPCI\cPCI-3840\Chipset in the CD-ROM, and then run Intel-Inf-v5111002.exe.
5. Click 'Next' on the Welcome screen to read and agree to the license agreement. Click Yes if you agree to continue. NOTE: If you click No, the program will terminate.
6. Click 'Next' on the Readme Information screen to install INF files.
7. Click 'Finish' to restart the system when prompted to do so.
8. Follow the screen instructions and use the default settings to complete setup when Windows 2000/XP/Server 2003 re-starts. Upon re-start, Windows may display that it has found new hardware and is installing drivers for them. Select Yes, if prompted to re-start Windows 2000/XP/Server 2003.

# 4.2 VGA Driver Installation

1. Run win2k\_xp142.exe located in the following directory: X:\cPCI\cPCI-3840\VGA.
2. Click 'Next' on the Welcome screen. Select 'Typical' on the setup type screen and click Next'.
3. Use the default program folders on Select Program Folder screen. Click 'Next' to install driver.
4. Finally, click 'Finish' to restart.

# 4.3 LAN Driver Installation

This section describes the LAN driver installation for the Intel® 82546EB onboard Ethernet controllers.

1. Run pro2kxp.exe located in the following directory: X:\cPCI\cPCI-3840\LAN.
2. Read the license agreement. Click 'I accept the terms in the license agreement' if you agree to continue.
3. Location to Save Files, click Next to save files in folder.
4. Intel® PRO Network Connections. Click Install Software to install drivers and Intel® PROSet.

# 4.4 Audio Codec Driver Installation

This section describes the LAN driver installation for the Intel® 82546EB onboard Ethernet controllers.

1. The driver is included in the driver CD. Run wdm\_a357.exe located in the following directory: X:\cPCI\cPCI-3840\Audio.
2. Click 'Next' on the Welcome audio setup screen to install driver..
3. Finally, click 'Finish' to re-start.

# 5 Utilities

# 5.1 Watchdog Timer

This section explains the operation of the cPCI-3840's watchdog timer. It provides an overview of watchdog operation and features, as well as a sample code to help you learn how the watchdog timer works.

# WDT Overview

The primary function of the watchdog timer is to monitor the cPCI-3840's operation and to generate IRQs or reset the system if the software fails to function as programmed. The major features of the watchdog timer are:

▶ Enabled and disabled through software control
▶ Armed and strobed through software control

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   PCI\n*   PCI Configuration Registers\n*   Preload Value 1\n*   Preload Value 2\n*   Down-Counter\n*   Reset/Interrupt Control Logic\n*   WDT_TOUT# (External)\n*   IRQ/SMI (Internal)\n\n**Connections:**\n*   **PCI** connects bidirectionally to **PCI Configuration Registers**.\n*   **PCI Configuration Registers** has output arrows pointing to **Preload Value 1**, **Preload Value 2**, and **Down-Counter**.\n*   **Preload Value 1** has an output arrow pointing to **Down-Counter**.\n*   **Preload Value 2** has an output arrow pointing to **Down-Counter**.\n*   **Down-Counter** has an output arrow pointing to **Reset/Interrupt Control Logic**.\n*   **Down-Counter** has an output arrow pointing back to **PCI Configuration Registers**.\n*   **Reset/Interrupt Control Logic** has an output arrow pointing back to **PCI Configuration Registers**.\n*   **Reset/Interrupt Control Logic** has output arrows pointing to **WDT_TOUT# (External)** and **IRQ/SMI (Internal)**.](.cpci-3840-manual-10/8e00f073f2be9d384e1299de56d5679be5e709b93d257cbf582d6a91d5d4dc2d.jpg)

Figure 5-1: WDT Overview

The cPCI-3840's custom watchdog timer circuit is integrated into the south bridge 6300ESB.

The Intel® 6300ESB ICH includes a two-stage Watchdog Timer (WDT) that provides a resolution ranging from one micro second to ten minutes. The timer uses a 35-bit Down-Counter. The counter is loaded with the value from the first Preload register. The timer is then enabled and it starts counting down. The time at which the WDT first starts counting down is called the first stage. If the host fails to reload the WDT before the 35-bit down counter reaches zero the WDT generates an internal interrupt. After the interrupt is generated, the WDT loads the value from the second Preload register into the WDT's 35-bit Down-Counter and starts counting down. The WDT is now in the second stage. If the host still fails to reload the WDT before the second timeout, the WDT drives the WDT\_TOUT# pin low. The WDT\_TOUT# pin is held low until the system is reset.

The WDT of 6300ESB also supports multiple modes: WDT and free-running. Free-running mode is a one stage timer and it will toggle WDT\_TOUT# after programmable time. WDT mode is a two stage timer and its operation is described as above.

# Configuration Registers

The Intel® 6300ESB ICH WDT, appears to BIOS as PCI Bus 0, Device 29, Function 4, and has the standard set of PCI Configuration register. The configuration registers is described below.

# Offset 10H: Base Address Register (BAR)

This register determines the memory base for WDT down-counter setting. It will be used to set Preload value 1 register, Preload value 2 register, General Interrupt Status register and Reload register.

# Preload Value 1 & 2 registers

These two registers are used to hold the preload value for the WDT timer. Its value will be automatically transferred into the down-counter every time the WDT enters the first stage and second stage. Preload Value 1 register locates at Base + 00H and Preload Value 2 register locates at Base + 04H. Only bit [19:0] are settable.

The register unlocking sequence is necessary when writing to the Preload registers. The following is the procedure of how to write a value into preload value 1 and 2 register.

1. Write 80H to offset BAR + 0CH.
2. Write 86H to offset BAR + 0CH.
3. Write desired value to preload register. (BAR + 00H or BAR + 04H)

# General Interrupt Status Register

This register is at Base + 08H. Bit 0 is set when the first stage of down-counter reaches zero.

▶ Bit 0 = 0 – No Interrupt
▶ Bit 1 = 1 – Interrupt Active

Note: This bit is not set in free running mode.

# Reload Register

This register is at Base + 0CH. Write 1 to bit 8 will reload the down-counter's value. Following is the procedure of how to prevent a timeout.

1. Write 80H to offset BAR + 0CH
2. Write 86H to offset BAR + 0CH
3. Write a '1' to RELOAD[8] of the reload register

# Offset 60 - 61H: WDT Configuration Register

Bit 5 indicates whether or not the WDT will toggle the WDT\_TOUT# pin when WDT times out. (0 = Enabled, 1 = Disabled)

Bit 2 provides two options for prescaling the main down-counter. (0 = 1ms - 10min, 1 = 1us - 1sec)

Bit [1:0] allows the user to choose the type of interrupt desired when the WDT reached the end of the first stage without being reset. (00 = IRQ, 01 = reserved, 10 = SMI, 11 = Disabled)

Note: Now, the WDT does not support SMI. IRQ uses APIC 1, INT 10 and it is active low, level triggered.

# Offset 68H: WDT Lock Register

Bit 2 is used to choose the functionality of the timer. (0 = Watchdog Timer mode, 1 = Free running mode) The free running mode ignores the first stage and only uses Preload Value 2. In free running mode it is not necessary to reload the timer as it is done automatically every time the down counter reaches zero.

Bit 1 enables or disables the WDT. (0 = Disabled, 1 = Enabled)

Bit 0 will lock the values of this register until a hard reset occurs or power is cycled. (0 = unlocked, 1 = locked) The default is Unlocked.

# GPIO Control Registers

There are three GPIOs on the cPCI-3840 related to the watchdog timer. They are listed as follows. The GPIO control base port is 480H.

# WDT\_TOUT# pin selection

The WDT\_TOUT# signal is multiplexed with GPIO32. When using WDT, this signal must be switched to WDT\_TOUT# function. It uses bit 0 of GPIOBASE + 30H to set WDT\_TOUT function. (0 = WDT\_TOUT#, 1 = GPIO32)

# RESET hardware circuit selection

GPO24 of the 6300ESB is designed to control the reset circuit. When GPO24 is low, the system will reset according to the level of the WDT\_TOUT# signal. When GPO24 is high, the system will not be reset by WDT\_TOUT#. Set bit 24 of GPIOBASE + 04H to 0 for output use. Bit 24 of GPIOBASE + 0CH determines the level of GPO24. (0 = Low, 1 = High) There already exists a setting in BIOS setup menu. (Integrated Peripherals page) The user can set this item before programming WDT.

# WDT LED Control

GPO25 of the 6300ESB is designed to control WDT LED. Two features of the WDT LED are supported on cPCI-3840. WDT LED lights or blinks.

▶ WDT LED lights: Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE + 0CH determines the state of WDT LED. (0=light, 1=dark)

▶ WDT LED blinks: Set bit 25 of GPIOBASE + 04H to 0. Bit 25 of GPIOBASE + 18H enables WDT LED blinking function. (0=function normally, 1=enable blinking) The high and low times have approximately 0.5 seconds each.

# WDT Programming Procedure

1. Make sure WDT\_TOUT# signal is functional. (Not GPIO32 function).
2. Set WDT output enable, presecaler and interrupt type into WDT configuration register.
3. Obtain control base from Base Address register.
4. Program Preload register's value according to unlocking sequence.
5. Set WDT timer mode into WDT Lock Register.
6. Enable WDT from WDT Lock register and program the functionality of WDT LED.

To prevent the timer from causing an interrupt or driving WDT\_TOUT#, the timer must be reloaded periodically. The frequency of reloads required is dependent on the value of the preload values. To reload the down-counter, the register unlocking sequence must be performed.

If the user wishes to disable WDT, set bit 1 of WDT Lock Register to 0.

# Utilities

ADLINK provide a demo DOS utility, HRWDT.EXE. It is included in the driver CD. Run "hrwdt /?" in the following directory for a more detailed description: X:\CHIPDRV\WDT\HRWDT

The user can also download the Intel® WDT demo windows application from the Intel® driver download center.

# 5.2 Intel® Preboot Execution Environment (PXE)

The cPCI-3840 series supports Intel® Preboot Execution Environment (PXE), which provides the capability of boot up or executing an OS installation through the Ethernet ports. There should be a DHCP server in the network with one or more servers running PXE and MTFTP services. It could be a Windows NT or Windows 2000 server running DHCP, PXE and MTFTP service or a dedicated DHCP server with one or more additional server running PXE and MTFTP service. This section describes the major items required for building a network environment with PXE support.

1. Setup a DHCP server with PXE tag configuration.
2. Install the PXE and MTFTP services
3. Make boot image file on PXE server (that is the boot server).
4. Enable the PXE boot function on the client computer.

For further details, please refer to the pdkrel30.pdf in the directory X:\Utility\PXE\_PDK.

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully.

1. Before using ADLINK's products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http://rma.adlinktech.com/policy/home.htm/.
2. All ADLINK products come with a limited two-year guarantee, one year for products bought in China:

The warranty period starts on the day the product is shipped from ADLINK's factory.
▶ Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
For products containing storage devices (hard drives, flash cards, etc.), please back up your data before sending them for repair. ADLINK is not responsible for loss of data.
▶ Please ensure the use of properly licensed software with our systems. ADLINK does not condone the use of pirated software and will not service systems using such software. ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user.
For general repairs, please do not include peripheral accessories. If peripherals need to be included, be certain to specify which items you sent on the RMA Request & Confirmation Form. ADLINK is not responsible for items not listed on the RMA Request & Confirmation Form.

3. Our repair service is not covered by ADLINK's guarantee in the following situations:

▶ Damage caused by not following instructions in the User's Manual.
▶ Damage caused by carelessness on the user's part during product transportation.
▶ Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
▶ Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
▶ Damage caused by leakage of battery fluid during or after change of batteries by customer/user.
▶ Damage from improper repair by unauthorized ADLINK technicians.
▶ Products with altered and/or damaged serial numbers are not entitled to our service.
▶ This warranty is not transferable or extendible.
▶ Other categories not protected under our warranty.

4. Customers are responsible for shipping costs to transport damaged products to ADLINK.

If you have any further questions, please email our FAE staff: service@adlinktech.com.
[🔗 Link to the original document](.cpci-3840-manual-10/cpci-3840-manual-10.pdf)