# cPCI-3920 Series

3U CompactPCI Blade with Intel® Core™2 Duo, Core™ Duo, Celeron® M Processor

# User's Manual

![Interior view of an electronic device chassis showing external components including CPU, RAM slots, and a green circuit board (no visible text or labels)](.cpci-3920-50-15064-1020-220/730a3ddb9c0c53222825ad4523d8badd810290be25a4b7d478882953cd818549.jpg)

Manual Rev. 2.20

Revision Date: August 30, 2010

Part No: 50-15064-1020

![Circular black-and-white recycling symbol with three white arrows forming a triangle (no text or symbols)](.cpci-3920-50-15064-1020-220/1136f71ce016bfea3d843932dd0794807bfeed6048acc83df5b0df8269baee1a.jpg)

Recycled Paper

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2008/07/07</td><td>Initial Release</td></tr><tr><td>2.10</td><td>2008/09/04</td><td>Update BIOS chapter</td></tr><tr><td>2.20</td><td>2010/08/30</td><td>Correct pin definitions (SATA0, J2, COM2, rJ2); update BIOS</td></tr></table>

# Preface

# Copyright 2010 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Using this Manual

# Audience and Scope

The cPCI-3920 User's Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating industrial grade CompactPCI modules.

# Manual Organization

This manual is organized as follows:

Chapter 1, Overview: Introduces the cPCI-3920 and package contents.

Chapter 2, Specifications: Presents detailed specification information, power consumption, and mechanical layout.

Chapter 3, Functional Description: Describes the cPCI-3920 main functions and board interfaces.

Chapter 4, Getting Started: Describes the installation instructions of the cPCI-3920.

Chapter 5, Driver Installation: Describes the driver installation procedures.

Chapter 6, Watchdog Timer: Describes the Watchdog Timer functionality.

Chapter 7, BIOS Setup Utility: Describes the AMIBIOS®8 BIOS setup utility.

Important Safety Instructions: Presents safety instructions all users must follow for the proper setup, installation and usage of equipment and/or software.

Getting Service: Contact information for ADLINK's worldwide offices.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a graphic icon of a white document with horizontal lines and a folded top-left corner. A large, red checkmark is superimposed diagonally across the center of the document.](.cpci-3920-50-15064-1020-220/9fdadfeb731b7438c59fa3e105fe4d6295e30c0eef4c22b78aaa3b83373f3a51.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a standard safety warning sign. It features a yellow triangle with a thick black border. Centered inside the triangle is a large, black exclamation mark.](.cpci-3920-50-15064-1020-220/691073647a7f7904e9fc54b48b77bd0361419aed11b6ceddf284494e080041af.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning sign consisting of a red equilateral triangle pointing upwards. Inside the triangle is a large white exclamation mark (!) centered vertically and horizontally. The background surrounding the triangle is white.](.cpci-3920-50-15064-1020-220/81594b946d1b3c329f6acaecd98324c18553052a3d148e04508f43c22619a6bb.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

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# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Tables ix

# List of Figures ...... xi

# 1 Overview .... 1

1.1 Introduction.... 1
1.2 Features.... 2
1.3 Block Diagram 3
1.4 Product List.... 4
1.5 Package Contents 5

# 2 Specifications.... 7

2.1 CPU, memory, and chipset.... 7
2.2 Interfaces 7
2.3 Software 9
2.4 Mechanical....9
2.5 Environmental....9
2.6 I/O Connectivity Table 10
2.7 Power Requirements 11
2.8 Mechanical Dimensions.... 15
2.9 Board Layout 17

# 3 Functional Description 23

3.1 CPU, Memory and Chipset 23
3.2 Peripherals.... 30
3.3 Board Interfaces 34
3.4 Board Interfaces on RTM.... 51

# 4 Getting Started 57

4.1 Safety Requirements 57
4.2 Installing the USB Flash Disk 58
4.3 Installing the Hard Disk Drive (cPCI-3290B only).... 59
4.4 Installing the cPCI-3920 to the Chassis.... 60
4.5 RTM (cPCI-R3920) Installation 61
4.6 Hot Swap Procedures.... 61

5 Driver Installation.... 63
6 Watchdog Timer.... 65

6.1 WDT Overview.... 65

6.2 Using the Watchdog Timer in an Application 66

7 BIOS Setup Utility 71

7.1 Starting the BIOS.... 71
7.2 Main Setup.... 75
7.3 Advanced BIOS Setup 77
7.4 PCI/PnP Setup 89
7.5 Boot Setup 90
7.6 Security Setup.... 94
7.7 Chipset Setup 97
7.8 Exit Menu 99

Important Safety Instructions.... 101

Getting Service 103

# List of Tables

Table 2-1: I/O Connectivity 10

Table 2-2: CompactPCI input voltage characteristics ..... 11

Table 2-3: Power consumption of Core™ 2 Duo LV (L7400) .. 12

Table 2-4: Power consumption of Core™ 2 Duo LV (U2500) .. 13

Table 2-5: Power consumption of Celeron M LV(423) ...... 14

Table 3-1: Supported Processors, Power Dissipation ..... 25

Table 3-2: SMBus Devices and Addresses 32

Table 3-3: LED Function Descriptions 33

Table 3-4: Front Panel USB Connector Pin Definition ...... 34

Table 3-5: Onboard USB Connector Pin Definition 35

Table 3-6: VGA Connector CN3 Pin Definition 38

Table 3-7: Gigabit Connector CN7/CN8 Pin Definitions ..... 39

Table 3-8: Ethernet LED Status Definitions 40

Table 3-9: Board-to-Board Connector Pin Definition 41

Table 3-10: PS/2 Keyboard/Mouse Connector Pin Definition .... 42

Table 3-11: COM3 Serial Port Connector Pin Definition ..... 43

Table 3-12: COM4 Serial Port Connector Pin Definition ..... 43

Table 3-13: COM4 Mode Switch Settings 44

Table 3-14: SATA0 Connector Pin Definition 46

Table 3-15: CompactPCI J1 Pin Assignment 48

Table 3-16: CompactPCI J2 Pin Assignment 50

Table 3-17: RTM USB Connector Pin Definitions 51

Table 3-18: RTM Gigabit Connector Pin Definitions 52

Table 3-19: COM1 Serial Port Connector Pin Definition ..... 53

Table 3-20: COM2 Serial Port Connector Pin Definition ..... 53

Table 3-21: SATA1-3 Connectors Pin Definition 54

Table 3-22: CompactPCI rJ2 Pin Assignment 56

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# List of Figures

Figure 1-1: cPCI-3920 Block Diagram 3
Figure 2-1: cPCI-3920 Mechanical Dimensions.... 15
Figure 2-2: cPCI-R3920 Mechanical Dimensions....16
Figure 2-3: cPCI-3920 Board Layout 17
Figure 2-4: cPCI-3920A Assembly and Front Panel 18
Figure 2-5: DB-3920L2 Daughter Board Layout 19
Figure 2-6: cPCI-3920B Assembly and Front Panel 20
Figure 2-7: cPCI-R3920(T) Board Layout and Front Panel ..... 21
Figure 3-1: Intel® 3100 Chipset Block Diagram.... 26
Figure 3-2: USB Flash Disk Mechanical Layout 36
Figure 6-1: cPCI-3920 Watchdog Timer Architecture 65

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# 1 Overview

# 1.1 Introduction

The cPCI-3920 is a highly integrated 3U CompactPCI SBC in single slot (4HP) or dual slot (8HP) width form factor. It has been designed to support Intel® lower power Core™ 2 Duo, Core™ Duo and Celeron® M processors in FC-BGA package with a range of 1.0GHz to 1.5GHz at FSB 533MHz to 667MHz. They deliver optimized power-efficient computing and outstanding dual core performance with lower power consumption.

The cPCI-3920 is based on the server-class Intel® 3100 chipset (Whitmore Lake) which combines Memory Controller Hub and I/O Controller Hubs into a single component, significantly conserving board real estate and power consumption. The Intel® 3100 chipset is the first Integrated Intel® chipset optimized for embedded, communications, and storage applications.

The cPCI-3920 supports registered ECC type, single channel DDR2 400MHz soldered onboard memory with a maximum capacity of up to 2GB. The board supports one 32-bit/33MHz CompactPCI interface acting as system master CPU only.

The cPCI-3920 offers versatile I/O ports like two Gigabit Ethernet ports, two COM ports, up to three USB 2.0 ports, PS/2 Keyboard/Mouse, and VGA port on the front panel. A Rear Transition Module (RTM) is also available and provides an additional two USB 2.0 ports, two COM ports, and two Gigabit Ethernet ports switched from the front panel.

Storage features of the cPCI-3920 include a pin header and mounting space for an onboard USB NAND flash module, and one Serial ATA interface with mounting space for a 2.5" HDD in the 8HP version. There are also three 7-pin Serial ATA interfaces available on the RTM for additional storage expansion.

Designed for stability and packaged in a rugged format, the cPCI-3920 is suitable for long life applications situated in industrial environments, including I/O intensive applications where only one slot is available for the CPU. Components which have high temperature tolerance have been selected from embedded technology programs, and therefore offer long-term availability.

# 1.2 Features

▶ 3U CompactPCI SBC in 4HP or 8HP width form factor
▶ Low power Intel Core 2 Duo 1.5GHz, Core™ Duo 1.2GHz, Celeron® M 1.0GHz processors
Intel® 3100 chipset (Memory and I/O Hub integrated chip)
▶ Single channel DDR2 registered and ECC memory at 400MHz
▶ Two PCI-Express Gigabit Ethernet ports in the front or RTM
▶ Support USB 2.0 NAND flash module, up to 8GB
▶ Supports one 2.5" Serial ATA hard drive onboard and three Serial ATA interfaces on RTM
▶ Up to five USB ports and four serial ports

# 1.3 Block Diagram

![Based on the provided block diagram, here is the accurate description of the labeled blocks and connections:\n\n**Central Component**\n*   **Block:** Intel® 3100 Chipset (Whitmore Lake) (Large yellow block in the center)\n\n**Top Connection**\n*   **Block:** Intel® Core 2 Duo (Merom)\n*   **Connection:** A bidirectional arrow labeled 'FSB 533/677' connects the central chipset to the CPU block.\n\n**Left-Side Connections**\n*   **GbE Path:** A line labeled 'GbE 1/2' originates from the central block. It connects to a blue block labeled '82571EB' (with text 'PCI-E x4' next to it). From '82571EB', an arrow points to a grey block labeled 'GbE 1/2'.\n*   **USB Path 2:** A line labeled 'USB 2' connects to a yellow block labeled 'USB'.\n*   **USB Path 1:** A line labeled 'USB 1' connects to a grey block labeled 'USB'.\n*   **LPC Cluster:**\n    *   A line labeled 'LPC' connects to a blue block labeled 'F71858D'.\n    *   From 'F71858D', an arrow points to a yellow block labeled 'KB/MS'.\n    *   From 'F71858D', a line connects upwards to a blue block labeled 'F8126'.\n    *   From 'F8126', an arrow points to a yellow block labeled 'COM 3/4'.\n    *   From 'F8126', a line connects to a blue block labeled 'FWH'.\n*   **VGA Path:** A line labeled 'PCI-E x1' connects to a blue block labeled 'Volari Z11'. From 'Volari Z11', an arrow points to a grey block labeled 'VGA'.\n*   **SATA Path:** A line connects from the central block to a yellow block labeled 'SATA'.\n\n**Right-Side Connections**\n*   **USB Path 3:** A line labeled 'USB 3' connects to a blue block labeled 'HUB'. From 'HUB', an arrow points to a yellow block labeled 'USB' (with text 'USB x2' above the arrow).\n*   **J2 Connections:**\n    *   A line labeled 'PCI-E x4 (1x) or x1 (4x)' points to a grey block labeled 'J2'.\n    *   A line labeled 'COM 1/2' points to the grey block 'J2'.\n    *   A line labeled 'SATA (3x)' points to the grey block 'J2'.\n    *   A line labeled 'SMbus' connects to a blue block labeled 'W83792AG'. From 'W83792AG', an arrow points to the grey block 'J2'.\n*   **USB 0:** A line labeled 'USB 0' connects to a grey block labeled 'pin header'.\n*   **Memory:** A line labeled 'DDR2-400 REG/ECC' connects to a blue block labeled 'Soldered'.\n*   **PCI:** A line labeled 'PCI 32-bit/33MHz' points to a grey block labeled 'J1'.\n\n**Legend**\n*   **Yellow Rounded Rectangle:** I/O for 8HP\n*   **Grey/Blue Rounded Rectangle:** I/O for 4HP](.cpci-3920-50-15064-1020-220/63d158fb63c6623b917562357dd9408a4355d15f0fb0ec8bb6e0f0ef32717175.jpg)

Figure 1-1: cPCI-3920 Block Diagram

# 1.4 Product List

Products included in the cPCI-3920 Series include:

# SBC

▶ cPCI-3920A: single-slot (4HP) width 3U CompactPCI featuring Intel LV Core 2 Duo 1.5GHz, Core Duo 1.2GHz or ULV Celeron 1.0GHz processors; 512MB, 1GB or 2GB onboard memory; optional USB flash disk module
▶ cPCI-3920B: dual-slot(8HP) width 3U CompactPCI featuring Intel LV Core 2 Duo 1.5GHz, Core Duo 1.2GHz or ULV Celeron 1.0GHz processors; 512MB, 1GB or 2GB onboard memory; optional USB flash disk module and 2.5" SATA hard drive

# Rear Transition Module

▶ cPCI-R3920: Rear Transition Module for cPCI-3920 SBCs with 50mm width
▶ cPCI-R3920T: Rear Transition Module for cPCI-3920 SBCs with 80mm width

# Accessories

▶ USB flash disk module, optional 2GB, 4GB or 8GB

▶ 2.5" Serial ATA hard drive

Contact your ADLINK representative to purchase accessories.

# 1.5 Package Contents

The cPCI-3920 is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the cPCI-3920 Series are non-standard configurations and may vary depending on customer requests.

# CPU module

▶ The cPCI-3920 Series CPU Module
▷ CPU, RAM, and HDD specifications will differ depending on options selected
▷ Thermal module is assembled on the board
▶ Battery daughter board is assembled on the board
▷ HDD bracket is assembled on the 8HP version
▶ Four screws for hard drive
▶ Y-cable for PS/2 combo port (8HP version only)
▶ ADLINK All-in-One CD
▶ User's manual

# Rear Transition Module

▶ cPCI-R3920 or cPCI-R3920T

![The image displays a white document icon featuring horizontal lines representing text, overlaid with a large, bold red checkmark.](.cpci-3920-50-15064-1020-220/fb8a97e0231cbbea9f0c52141aede70fcc6b2e11f4d06fbdfff58731bc8b7348.jpg)
NOTE:

The contents of non-standard cPCI-3920 configurations may vary depending on the customer's requirements.

CAUTION: This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

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# 2 Specifications

# 2.1 CPU, memory, and chipset

<table><tr><td rowspan="3">Processor</td><td>uFC-BGA Intel® CoreTM 2 Duo LV (L7400) 1.5 GHz, FSB 667MHz, 4 MB L2 cache</td></tr><tr><td>uFC-BGA Intel Intel® CoreTM Duo ULV (U2500) 1.2 GHz, FSB 533MHz, 2 MB L2 cache</td></tr><tr><td>uFC-BGA Intel Intel® Celeron® M ULV (423) 1.06 GHz, FSB 533MHz, 1 MB L2 cache</td></tr><tr><td>Chipset</td><td>Intel® 3100 chipset</td></tr><tr><td>Memory</td><td>Single channel soldered onboard registered ECC DDR2 SDRAM at 400MHz up to 2GB</td></tr></table>

# 2.2 Interfaces

<table><tr><td>CompactPCI Standard</td><td>PICMG® 2.0 R3.0 PICMG® 2.1 R2.0</td></tr><tr><td>CompactPCI Bus</td><td>32-bit/33MHz PCI bus</td></tr><tr><td>Display</td><td>XGI Volari Z11 PCI-Express x1 Graphics Controller32MB DDR2-400 SDRAM memoryUp to 1600x1200@70Hz 24bit color</td></tr><tr><td>Ethernet</td><td>PCI-Express x4 Intel® 82571EB dual port Ethernet controllerTwo GbE egress ports on the front panel or on the rear panel by BIOS selection</td></tr><tr><td rowspan="5">USB</td><td>4x USB channels from 3100 chipset</td></tr><tr><td>Channel 0 is for 9 pin header, space reserved for horizontal USB flash disk module</td></tr><tr><td>Channel 1 is connected to the front panel</td></tr><tr><td>Channel 2 is connected to the front panel (8HP only)</td></tr><tr><td>Channel 3 is connected to 4-port hub controller with one channel routed to the 8HP front panel and two channels routed to the RTM</td></tr><tr><td rowspan="3">Serial Port</td><td>4x serial ports</td></tr><tr><td>Two DB-9 ports on the front panel, one RS-232 and one RS-232/422/485/485+ (8HP only)</td></tr><tr><td>Two ports are routed to RTM with one DB-9 port on rear panel and one pin header onboard</td></tr><tr><td rowspan="3">Serial ATA</td><td>4x Serial ATA channels:</td></tr><tr><td>One SATA connector onboard, 2.5" HDD space reserved (8HP only)</td></tr><tr><td>Three channels are routed to RTM with pin headers onboard</td></tr><tr><td rowspan="11">Front panel I/O</td><td>cPCI-3920 main board</td></tr><tr><td>1x USB 2.0 port</td></tr><tr><td>1x VGA port</td></tr><tr><td>2x GbE port</td></tr><tr><td>1x system reset button</td></tr><tr><td>Power, WDT, CPU over-temperature LED</td></tr><tr><td>DB-3920L2 daughter board (8HP only)</td></tr><tr><td>1x RS-232 port</td></tr><tr><td>1x RS-232/422/485/485+ selectable port</td></tr><tr><td>1x PS/2 combo port for keyboard and mouse</td></tr><tr><td>2x USB 2.0 port</td></tr><tr><td rowspan="7">Board I/O Interfaces</td><td>cPCI-3920 main board</td></tr><tr><td>1x pin header for USB flash disk module</td></tr><tr><td>DB-3920L2 daughter board (8HP only)</td></tr><tr><td>1x SATA port (signal and power for onboard HDD)</td></tr><tr><td>cPCI-R3920 rear transition module</td></tr><tr><td>3x SATA ports (7-pin)</td></tr><tr><td>10-pin RS232 port</td></tr><tr><td rowspan="3">Rear panel I/O</td><td>2x USB 2.0 port</td></tr><tr><td>2x GbE port (share the same channels with front panel GbE ports, selected by BIOS setting)</td></tr><tr><td>1x RS-232 port</td></tr></table>

# 2.3 Software

<table><tr><td>BIOS</td><td>AMI 16Mbit FWH</td></tr><tr><td rowspan="5">Supported OS</td><td>Microsoft® Windows® XP Professional</td></tr><tr><td>Microsoft® Windows® Server 2003</td></tr><tr><td>Microsoft® Windows® Vista Enterprise, 32-bit version</td></tr><tr><td>RedHat Fedora Core 8</td></tr><tr><td>Contact ADLINK for other OS availability</td></tr></table>

# 2.4 Mechanical

<table><tr><td rowspan="2">Form factor</td><td>cPCI-3920: 3U 4HP/8HP CompactPCI</td></tr><tr><td>cPCI-R3920(T): 3U 4HP CompactPCI</td></tr><tr><td rowspan="3">Dimensions</td><td>cPCI-3920: 100mmx 160mm (LxW)</td></tr><tr><td>cPCI-R3920: 100mm x 50mm (LxW)</td></tr><tr><td>cPCI-R3920T: 100mmx 80mm (LxW)</td></tr></table>

# 2.5 Environmental

<table><tr><td rowspan="2">Operating temperature</td><td>Standard: 0 to 60°C</td></tr><tr><td>Extended temperature: -20 to 70°C</td></tr><tr><td>Storage temperature</td><td>-40°C to 85°C</td></tr><tr><td>Humidity</td><td>5% to 95% non-condensing</td></tr><tr><td>Shock</td><td>15G peak-to-peak, 11ms duration, non-operation</td></tr><tr><td rowspan="2">Vibration</td><td>Non-operating: 1.88G rms, 5 to 500 Hz, each axis</td></tr><tr><td>Operating: 1.88G rms. 5 to 500Hz, each axis, with USB flash disk (without HDD)</td></tr><tr><td>Compliance</td><td>CE, FCC Class A</td></tr></table>

# 2.6 I/O Connectivity Table

<table><tr><td></td><td colspan="2">cPCI-3920A</td><td colspan="2">cPCI-3920B</td><td colspan="2">cPCI-R3920(T)</td></tr><tr><td></td><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td><td colspan="2">Faceplate</td></tr><tr><td>GbE</td><td>Y x2</td><td>--</td><td>Y x2</td><td>--</td><td>Yx2</td><td>--</td></tr><tr><td>USB</td><td>Y</td><td>Y (9-pin)</td><td>Y x3</td><td>Y (9-pin)</td><td>Yx2</td><td>--</td></tr><tr><td>VGA</td><td>Y</td><td>--</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>COM</td><td>--</td><td>--</td><td>Y(DB-9) x2</td><td>--</td><td>Y (DB-9)</td><td>Y(10-pin)</td></tr><tr><td>SATA</td><td>--</td><td>--</td><td>--</td><td>Y</td><td>--</td><td>Y x3(7-pin)</td></tr><tr><td>PS/2KB/MS</td><td>--</td><td>--</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr><tr><td>LED</td><td>Y x3</td><td>--</td><td>Y x3</td><td>--</td><td>--</td><td>--</td></tr><tr><td>ResetButton</td><td>Y</td><td>--</td><td>Y</td><td>--</td><td>--</td><td>--</td></tr></table>

Table 2-1: I/O Connectivity

# 2.7 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

Table 2-2: CompactPCI input voltage characteristics

# Power Consumption

The following tables provide information on the power consumption of cPCI-3920.

Processor: Intel® Core™ 2 Duo LV (L7400) 1.5GHz, FSB 667MHz, 4MB L2 cache

<table><tr><td>Function</td><td colspan="3">Configuration</td></tr><tr><td>Memory</td><td colspan="3">DDR2 400 1GB</td></tr><tr><td>SATA Hard Drive</td><td colspan="3">External 3.5”HDD</td></tr><tr><td>Backplane</td><td colspan="3">ADLINK cBP-3208R Rev.B2</td></tr><tr><td>Power Supply</td><td colspan="3">ZIPPY HG2-6350P 350W</td></tr><tr><td colspan="4">DOS</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.53</td><td>4.41</td><td></td></tr><tr><td>Watts (W)</td><td>5.05</td><td>22.05</td><td>27.10</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Linux, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.63</td><td>3.53</td><td></td></tr><tr><td>Watts (W)</td><td>5.38</td><td>17.65</td><td>23.03</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.62</td><td>4.63</td><td></td></tr><tr><td>Watts (W)</td><td>5.35</td><td>23.15</td><td>28.50</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, CPU 100% Usage</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.61</td><td>6.02</td><td></td></tr><tr><td>Watts (W)</td><td>5.31</td><td>30.10</td><td>35.41</td></tr></table>

Table 2-3: Power consumption of Core™ 2 Duo LV (L7400)

Processor: Intel® Core™ Duo (U2500) 1.2GHz, FSB 533MHz, 2MB L2 cache

<table><tr><td>Function</td><td colspan="3">Configuration</td></tr><tr><td>Memory</td><td colspan="3">DDR2 400 1GB</td></tr><tr><td>SATA Hard Drive</td><td colspan="3">External 3.5”HDD</td></tr><tr><td>Backplane</td><td colspan="3">ADLINK cBP-3208R Rev.B2</td></tr><tr><td>Power Supply</td><td colspan="3">ZIPPY HG2-6350P 350W</td></tr><tr><td colspan="4">DOS</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.54</td><td>3.50</td><td></td></tr><tr><td>Watts (W)</td><td>5.08</td><td>17.50</td><td>22.58</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Linux, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.64</td><td>3.30</td><td></td></tr><tr><td>Watts (W)</td><td>5.41</td><td>16.50</td><td>21.91</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.68</td><td>3.71</td><td></td></tr><tr><td>Watts (W)</td><td>5.38</td><td>18.55</td><td>23.93</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, CPU 100% Usage</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.63</td><td>4.30</td><td></td></tr><tr><td>Watts (W)</td><td>5.38</td><td>21.50</td><td>26.88</td></tr></table>

Table 2-4: Power consumption of Core™ 2 Duo LV (U2500)

Processor: Intel® Celeron M LV(423) 1.07GHz, FSB 533MHz, 1MB L2 cache

<table><tr><td>Function</td><td colspan="3">Configuration</td></tr><tr><td>Memory</td><td colspan="3">DDR2 400 1GB</td></tr><tr><td>SATA Hard Drive</td><td colspan="3">External 3.5”HDD</td></tr><tr><td>Backplane</td><td colspan="3">ADLINK cBP-3208R Rev.B2</td></tr><tr><td>Power Supply</td><td colspan="3">ZIPPY HG2-6350P 350W</td></tr><tr><td colspan="4">DOS</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.51</td><td>3.27</td><td></td></tr><tr><td>Watts (W)</td><td>4.98</td><td>16.35</td><td>21.33</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Linux, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.60</td><td>3.12</td><td></td></tr><tr><td>Watts (W)</td><td>5.28</td><td>15.60</td><td>20.88</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, Idle</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.59</td><td>3.36</td><td></td></tr><tr><td>Watts (W)</td><td>5.25</td><td>16.80</td><td>22.05</td></tr><tr><td colspan="4"></td></tr><tr><td colspan="4">Windows® XP, CPU 100% Usage</td></tr><tr><td>Power requirement</td><td>+3.3V</td><td>+5V</td><td>Total</td></tr><tr><td>Current (A)</td><td>1.59</td><td>3.64</td><td></td></tr><tr><td>Watts (W)</td><td>5.25</td><td>18.20</td><td>23.45</td></tr></table>

Table 2-5: Power consumption of Celeron M LV(423)

# 2.8 Mechanical Dimensions

cPCI-3920A
![This image is a technical line drawing (schematic) of a CompactPCI motherboard, showing both a side view of the I/O panel and a top-down view of the PCB layout.\n\n**Text and Labels:**\n*   **Top Left (I/O Panel Header):** 'CompactPCI®'\n*   **I/O Panel Labels (from top to bottom):**\n    *   'USB' (next to a USB Type-A port)\n    *   'RS232' (next to a DB9 serial port)\n    *   'VGA' (next to a VGA D-sub port)\n    *   'HDMI' (next to an HDMI port)\n    *   'GIG2' (next to the upper RJ45 Ethernet port)\n    *   'GIG1' (next to the lower RJ45 Ethernet port)\n    *   'PWR' (next to a power connector)\n*   **Dimensions:**\n    *   Top horizontal dimension: '162.54'\n    *   Right vertical dimension: '99.85±0.15'\n\n**Visual Elements:**\n*   **Left Side:** A detailed vertical strip showing the rear I/O connectors and mounting screw holes.\n*   **Center/Main Body:** The main motherboard layout featuring:\n    *   Two large square outlines (likely CPU or cache sockets).\n    *   A rectangular connector area near the top right.\n    *   Four small rectangular outlines at the bottom right (likely capacitors or chips).\n    *   Several circular mounting holes.\n    *   A bracket or standoff mechanism at the bottom left.](.cpci-3920-50-15064-1020-220/db0aa2ad2201b86ae254f2d79719aa10198e7e73b8531b55137459de8ad3b5cb.jpg)

cPCI-3920B
![This image displays a technical line drawing of an electronic device, likely an industrial computer motherboard, featuring two views: a detailed I/O panel view on the left and a top-down chassis layout on the right.\n\n**Dimensions:**\n- A horizontal dimension at the top reads '162.54'.\n- A vertical dimension on the right side reads '99.85 ±0.15'.\n\n**Left Panel (I/O View):**\nThis section lists various ports and labels from top to bottom:\n- Top left corner text: 'CompactPCI' (with a triangle logo above the 'P').\n- Labels near the top: 'RST' and 'HOT' (with an arrow).\n- Port labels: 'USB', 'COM3', 'VGA', 'KB/MS', 'USB', 'COM4'.\n- Bottom port labels: 'WOL', 'LAN2', 'LAN1', 'PWR'.\n\n**Right Panel (Chassis View):**\nThis section shows the internal layout of the circuit board with various rectangular outlines representing components like the CPU socket, memory slots, expansion slots, and connectors, but contains no additional text labels.](.cpci-3920-50-15064-1020-220/0d62ddf87136b1d525e481fc21e6531524e57410bedbfcf36818773cb5836dc7.jpg)

Figure 2-1: cPCI-3920 Mechanical Dimensions

cPCI-R3920
![99.85±0.15\n52.54](.cpci-3920-50-15064-1020-220/3486e1ce1cfef6ade9d831411e747242bb186a9f9ba2d5aea0e72e4c0522ae3e.jpg)

![RS232\nGbE1 GbE2\nUSB](.cpci-3920-50-15064-1020-220/59b59ff9f5a592dfb73647ab5f93fa9ff8ab0bd9b2d64e22fa97acd461d01e4d.jpg)

cPCI-R3920T
![99.85±0.15\n82.54](.cpci-3920-50-15064-1020-220/5d5a2af1a2c2398ab98e73b67b2cb62ec3f27db947b0694989eb14306edff8f8.jpg)

![RS232\nGbE2\nGbE1\nUSB](.cpci-3920-50-15064-1020-220/24861855bed072be7d4b892be7760c9a41a4d7c2dc22abcaac0a6f2639f32154.jpg)

Figure 2-2: cPCI-R3920 Mechanical Dimensions

# 2.9 Board Layout

cPCI-3920 Board Layout
![CN2\nCN3\nCN4\nU6\nU7\nU5\nJ2\nCN5\nCN7\nU19 U15\nCN8\nU25\nJ1](.cpci-3920-50-15064-1020-220/df366834819683cd0ebd2cec85ebb5c43ef261fe7629d93cbf1b7bc64ff9ebe1.jpg)

<table><tr><td>U6</td><td>Processor</td><td>CN2</td><td>USB port</td></tr><tr><td>U7</td><td>Chipset</td><td>CN3</td><td>VGA port</td></tr><tr><td>U5</td><td>Transformer</td><td>CN7</td><td>Ethernet port</td></tr><tr><td>U15</td><td>Graphics controller</td><td>CN8</td><td>Ethernet port</td></tr><tr><td>U19</td><td>Ethernet controller</td><td>CN4</td><td>DB-3920L2 daughter board connector</td></tr><tr><td>U25</td><td>SDRAM</td><td>CN5</td><td>USB pin header</td></tr><tr><td>J1</td><td>CompactPCI J1 connector</td><td>J2</td><td>CompactPCI J2 connector</td></tr></table>

Figure 2-3: cPCI-3920 Board Layout

cPCI-3920A Assembly Outline
![Thermal Module\nUSB flash\ndisk (optional)\nBattery](.cpci-3920-50-15064-1020-220/4de2e64b88392c832873aca4e0e10bc9020d256f5d5a000863f1f15447f620fd.jpg)

cPCI-3920A Front Panel
![USB\nVGA\nQ9F2\nQ9E1\nRST\nPHOT\nWSTP\nPWR\nSpeed ACT](.cpci-3920-50-15064-1020-220/104ccdaca8fedf518d1b0e30bf5a8701a6a6851aec37edbe5cd006bba4b7df41.jpg)

Figure 2-4: cPCI-3920A Assembly and Front Panel

# Reset Button

▶ RST

# Temperature LED

▶ Hot (red): CPU Overtemperature Status, connected to the CPU signal PROCHOT

# Status LEDs

▶ WDT (yellow): Watchdog Status
▶ PWR (green): Power Supply Status

# Gigabit Ethernet LEDs

▶ SPEED ON (green): 1000Mbps
▶ SPEED OFF: 10Mbps or 100Mbps
▶ ACT (yellow): Ethernet Link Activity

# DB-3920L2 Daughter Board Components Layout

The DB-3920L2 Daughter Board extends the cPCI-3920 from 4HP (cPCI-3920A) to 8HP (cPCI-3920B) version. This additional capability opens up the broadest range of expansion possibilities. The DB-3920L2 module has been designed to include two COM ports, a PS/2 keyboard and mouse port, two USB 2.0 interfaces and a 2.5" SATA hard disk interface.

![63.57\nCN1-2\nCN2-2\nCN4-2\nCN5-2\nCN6-2\nCN3-2\nSW\n95](.cpci-3920-50-15064-1020-220/61ddec469c0610abb13aac77fbb9efd9012e4bb73657cbb74991d2889d5961fc.jpg)

<table><tr><td>CN1-2</td><td>Serial port</td><td>CN5-2</td><td>USB port</td></tr><tr><td>CN2-2</td><td>PS/2 Keyboard/ Mouse</td><td>CN6-2</td><td>Serial port</td></tr><tr><td>CN3-2</td><td>Serial ATA connector</td><td>SW</td><td>COM4 mode switches</td></tr><tr><td>CN4-2</td><td>USB port</td><td></td><td></td></tr></table>

Figure 2-5: DB-3920L2 Daughter Board Layout

cPCI-3920B Assembly Outline
![2.5' SATA\nhard drive](.cpci-3920-50-15064-1020-220/63c53856d176c0b5ca97cd23c319e01b7e63d35406b1d5d125ccaefa190d8984.jpg)

cPCI-3920B Front Panel

![COM3\nKB/MS\nUSB\nCOM4\nUSB\nVGA\nGbE2\nGbE1\nRST\nHOT\nWDT\nPWR](.cpci-3920-50-15064-1020-220/f340107df565de33e2fda78fab52da2926c1a148b15fd7ae956b3afab1f87976.jpg)

Figure 2-6: cPCI-3920B Assembly and Front Panel

# cPCI-R3920(T) Board Layout

The cPCI-3920 Series offer two version rear transition modules with the same functionality but different dimensions. The cPCI-R3920 is designed with a 50mm width and the cPCI-R3920T is designed with a 80mm width

![The image displays two technical line drawings of circuit boards side-by-side, annotated with red labels and blue dimension lines.\n\n**Left Diagram:**\n*   **Bottom Label:** cPCI-R3920T\n*   **Dimensions:** Height is labeled '99.85±0.15' and width is labeled '82.54'.\n*   **Labels:**\n    *   'rJ2' (inside a rectangular outline)\n    *   'CN1-R' (top connector)\n    *   'CN2-R', 'CN4-R', 'CN5-R' (middle connectors)\n    *   'CN3-R' (vertical connector on the right edge)\n    *   'CN6-R' (lower connector)\n    *   'CN8-R' and 'CN7-R' (bottom right connectors)\n\n**Right Diagram:**\n*   **Bottom Label:** cPCI-R3920\n*   **Dimensions:** Height is labeled '99.85±0.15' and width is labeled '52.54'.\n*   **Labels:**\n    *   'rJ2' (inside a rectangular outline)\n    *   'CN1-R' (top connector)\n    *   'CN2-R', 'CN4-R', 'CN5-R' (middle connectors)\n    *   'CN3-R' (vertical connector on the right edge)\n    *   'CN6-R' (lower connector)\n    *   'CN8-R' and 'CN7-R' (bottom right connectors)](.cpci-3920-50-15064-1020-220/3fbee9f870a1633c0900a8b5c57dae0612d107180ee75ce9d4daf29ff0294662.jpg)

<table><tr><td>CN1-R</td><td>10 pin RS-232 port</td><td>CN5-R</td><td>SATA port</td></tr><tr><td>CN2-R</td><td>SATA port</td><td>CN6-R</td><td>Dual Ethernet ports</td></tr><tr><td>CN3-R</td><td>RS232 port</td><td>CN7-R</td><td>USB port</td></tr><tr><td>CN4-R</td><td>SATA port</td><td>CN8-R</td><td>USB port</td></tr></table>

cPCI-R3920(T) Front Panel
![USB\nGbE1\nGbE2\nRS232](.cpci-3920-50-15064-1020-220/c27299a537bb0102de4ff58270be7420bb5d707ba118a03cc8586407998d80e1.jpg)

Figure 2-7: cPCI-R3920(T) Board Layout and Front Panel

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# 3 Functional Description

The following sections describe the cPCI-3920 main functions and board interfaces.

# 3.1 CPU, Memory and Chipset

# CPU: Intel® Core™ Duo and Intel® Core™2 Duo

The cPCI-3920 supports the latest Intel® Core™ Duo and Intel® Core™2 Duo processor family up to speeds of 1.5 GHz with up to 667 MHz FSB. The Intel® Core™ Duo consists of two cores and up to 2 MB L2 cache shared by both cores. The Intel® Core™2 Duo consists of two cores, up to 4 MB L2 cache shared by both cores, Intel Extended Memory 64 Technology (Intel EM64T), and enhanced address range for up to 64 GB memory. The Intel® Core™ Duo and the Intel® Core™2 Duo processors deliver optimized power-efficient computing and outstanding dual-core performance with low power consumption.

The Intel® Core™ Duo and the Intel® Core™2 Duo support the latest Intel's Virtualization Technology (VT), which allows a platform to run multiple operating systems and applications in independent partitions, such as performing system upgrades and maintenance without interrupting the system or the application, keeping software loads and virus attacks separate, combining multiple servers in one system, etc. With processor and I/O enhancements to Intel's various platforms, Intel Virtualization Technology improves the performance and robustness of today's software-only virtual machine solutions.

Furthermore, the Intel® Core™ Duo and the Intel® Core™2 Duo also support the Intel SpeedStep technology which enables real-time dynamic switching of the voltage and frequency between several modes. This is achieved by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system.

The following list sets out some of the key features of the Intel® Core™ Duo and the Intel® Core™2 Duo processors:

▶ Two mobile execution cores in one single processor
▶ Support of Intel's Virtualization Technology (Vanderpool)
▶ Support of Intel Architecture with Dynamic Execution
▶ Outstanding dual-core performance with low power consumption
▶ On die, primary 32 KB instruction cache and 32KB write-back data cache
▶ On die, L1 and L2 cache with Advanced Transfer Cache Architecture
Intel® Core™ Duo processor (ULV), 1.2 GHz, 533 MHz FSB, 2 MB L2 cache
Intel® Core™2 Duo processor (LV), 1.5 GHz, 667 MHz FSB, 4 MB L2 cache
▶ Advanced Branch Prediction and Data Prefetch Logic
▶ Streaming SIMD Extensions 3 (SSE3)
▶ Up to 667 MHz, Source-Synchronous Front Side Bus (FSB)
▶ Advanced Power Management features including Enhanced Intel SpeedStep technology
Intel Extended Memory 64 Technology for 64-bit computing (only with the Intel® Core™2 Duo)
▶ Enhanced address range for up to 64 GB memory (only with the Intel® Core™ Duo)

# Intel® Celeron® M

The cPCI-3920 supports the low power 1.07 GHz Intel® Celeron® M processor with 533 MHz FSB. The Intel® Celeron® M consists of one core and 1 MB L2 cache.

The following list sets out some of the key features of the Intel® Celeron® M processor:

▶ Supports Intel architecture with dynamic execution
▶ High-performance, low-power core featuring architectural innovations like micro-ops fusion and advanced stack man-

agement that reduce the number of micro-ops handled by the processor.

▶ On-die, primary 32-kB instruction cache and 32-kB, write-back, data cache
▶ On-die, 1 MB second level cache with Advanced Transfer Cache architecture
▶ Advanced branch prediction and data prefetch logic
▶ Streaming SIMD extensions 2 (SSE2) that enables breakthrough levels of performance in multimedia applications including 3D graphics, video decoding/encoding, and speech recognition.
▶ 533-MHz, source-synchronous front side bus (FSB)
▶ Advanced power management features
- Maintained support for MMX\_ technology (technology designed to accelerate multimedia and communications software)
▶ Compatible with IA-32 software

# Supported Processors, Maximum Power Dissipation

The following tables indicate the processors supported on the cPCI-3920 and their maximum power dissipation.

<table><tr><td>Speed</td><td>Intel® Celeron® M 1.07 GHz (ULV(2))</td><td>Intel® Core Duo 1.2GHz (ULV(2))</td><td>Intel® Core 2 Duo 1.5GHz (LV(1))</td></tr><tr><td>Package</td><td>μFCBGA</td><td>μFCBGA</td><td>μFCBGA</td></tr><tr><td>L2 Cache</td><td>1MB</td><td>2MB</td><td>4MB</td></tr><tr><td>FSB</td><td>533 MHz</td><td>533 MHz</td><td>667 MHz</td></tr></table>

(1) LV: Low Voltage
(2) ULV: Ultra low Voltage

<table><tr><td>Frequency Mode</td><td>Intel® Celeron® M 1.07 GHz (ULV) 1MB L2 Cache</td><td>Intel® Core Duo 1.2GHz (ULV) 2MB L2 Cache</td><td>Intel® Core 2 Duo 1.5GHz (LV) 4MB L2 Cache</td></tr><tr><td>Maximum Power HFM(3)</td><td>5.5W</td><td>9W</td><td>17W</td></tr></table>

(3) HFM: High Frequency Mode (maximum frequency of the CPU)

Table 3-1: Supported Processors, Power Dissipation

# Memory

The cPCI-3920 supports a single soldered channel DDR2 memory with Error Checking and Correcting (ECC) running at 400 MHz. The available memory module configuration is 1 GB. 2 GB available on request, please contact your ADLINK representative.

![A white document icon with a folded top-left corner and faint horizontal lines, featuring a large red checkmark in the center.](.cpci-3920-50-15064-1020-220/0945f14b3379eeaae5642fd0cbd912780f57a57094ecfb22348a1fa9e6d6c357.jpg)
NOTE:

Memory configuration changes can only be performed at the factory. Failure to comply with the above may result in damage to your board or improper operation.

# Intel® 3100 Chipset Overview

The Intel® 3100 Chipset is a single integrated chip that contains the functionality of a Memory Controller Hub and an I/O Controller Hub. In this document the Memory Controller Hub unit and I/O Controller Hub unit in the Intel® 3100 Chipset are referenced as IMCH (Integrated Memory Controller Hub) and IICH (Integrated I/O Controller Hub) respectively.

![This diagram depicts the architecture of an Intel chipset system. The central component is a large green block labeled **Intel® 3100 Chipset**, which is vertically divided into two sections: **IICH** (left) and **IMCH** (right). Within the IMCH section, a dark green sub-block is labeled **EDMA**.\n\nThe connections are as follows:\n\n*   **Processor Connection:** A double-headed arrow labeled **FSB** connects the central chipset to a block at the top labeled **Processor**.\n*   **Peripheral Connections (Left):** A column of eight blocks on the left connects to the **IICH** section via double-headed arrows. Listed from top to bottom, they are:\n    *   **WDT**\n    *   **Serial ATA 6 Drives**\n    *   **SM Bus x2**\n    *   **PCI 32/33**\n    *   **2 UART**\n    *   **4 USB-2**\n    *   **38 GPIOs**\n    *   **LPC**\n*   **Memory Connection:** A double-headed arrow labeled **ECC** connects the **IMCH** section to a block on the right labeled **Registered ECC DDR2 400**.\n*   **Expansion Connections (Bottom):** Two dashed-line blocks at the bottom connect to the chipset:\n    *   A blue double-headed arrow labeled **Port B** connects the **IICH** section to a block labeled **PCI Express 1x4 or 4x1**.\n    *   A green double-headed arrow labeled **Port A** connects the **EDMA** section to a block labeled **PCI Express 1x8 configurable as 2x4 or 2x1**.](.cpci-3920-50-15064-1020-220/4d78ec71d6cbaacbf38550a2326b45471815179d4c50edac5c3676870c78376a.jpg)

Figure 3-1: Intel® 3100 Chipset Block Diagram

# PCI Express

The Intel 3100 Chipset provides one configurable x8 PCI Express interface with a maximum theoretical bandwidth of 4 GByte/s. The x8 PCI Express interface may alternatively be configured as two independent x4 PCI Express interfaces with a maximum theoretical bandwidth of 2 GBytes/s each. The Intel® 3100 Chipset also supports an additional x4 PCI Express interface with a maximum theoretical bandwidth of 2 GBytes/s which may alternatively be configured as four independent x1 PCI Express interfaces.

# IICH

I/O Controller Hub (IICH) functions are integrated into the Intel® 3100 Chipset, eliminating the requirement for a legacy I/O bridge.

# I/O Controller Hub Feature set comprises:

▶ PCI Express Interface
▶ Low Pin Count (LPC) Interface
▶ Firmware Hub (FWH) Interface
▶ Integrated Serial ATA (SATA) Host Controllers:
▷ Independent DMA operation on six ports
- Four ports in SATA 1.0a and AHCI mode
- Six ports in AHCI mode only
▷ Data transfer rates up to 150 Mbyte/s
▶ Two controllers with up to four USB 2.0 ports:
One EHCI USB 2.0 Host Controller to support a total of four ports (shared with the UHCI ports)
▶ Two UHCI Host Controllers to support a total of four ports (shared with the EHCI ports)
▶ Interrupt Controller
▶ Power Management Logic
▶ DMA Controller
▶ Timers Based on 82C54
▶ High Precision Event Timers (HPET)
▶ Real Time Clock with 256-byte Battery-backed CMOS RAM

▶ System TCO Reduction Circuits
▶ SMBus
▶ Watchdog Timers
▶ PCI 2.3 Interface
▶ Two fully functional serial ports
▶ 38 General Purpose I/Os (GPIO)

# IMCH

The Intel® 3100 Chipset provides an integrated memory controller for direct-connection to one channel of DDR2-400 (unstacked) registered memory devices with ECC. Peak theoretical memory data bandwidth using DDR2-400 is 3.2 GByte/s

# Volari™ Z11 Graphics Controller

Volari™ Z11 GPU is the extreme programmable GPU of the XGI 2D GPU family. The Volari™ Z11 integrates a PCI-Express 1x controller and a 64-bit 2D graphics engine. It offers a flexible 16-bit DDR-II memory interface. The Z11 also incorporates a configurable 3.3V DVO digital interface to support a third party LVDS/TMDS transmitter. It can achieve high 2D performance with a memory interface supporting a bandwidth of up to 1 GB/s (DDR-II @250MHz).

Volari™ Z11 GPU main features:

▶ PCI-Express 1x Bus Interface
▶ Supports PCI-E local bus standard Revision 1.1 compliant
▶ High Performance 2D Accelerator
▶ Built-in hardware command queue
▶ Built-in Direct Draw Accelerator
▶ Built-in GDI 2000 Accelerator
▶ Built-in an 1T pipelined 64-bit BITBLT graphics engine
▶ Supports memory-mapped, zero wait-state, burst engine write
▶ Built-in 64x64x2 bit-mapped mono hardware cursor

▶ High Efficient BroadBahn™ Memory Architecture

▶ Supports DDR-II SDRAM memory
▷ 32 MB memory configuration
▶ Supports VGA BIOS auto memory size detection

▶ High Performance Flat Panel Display Interface

▶ Supports graphics mode up to 1600x1200@70Hz 16M colors

▶ High Integration

Built-in CRT FIFO to support ultra high resolution graphics modes and reduce CPU wait-state

Built-in programmable 24-bit true-color RAMDAC with 230 MHz pixel clock

▶ Resolution, Color & Frame Rate

▶ Supports 230 MHz pixel clock
▶ Supports VESA standard super high resolution graphics modes
4:3 resolution up to 1600x1200 256/32K/64K/16M colors 70Hz
Wide Screen resolution modes
Low resolution modes

▶ Supports virtual screen up to 4096x4096

▶ Power Management

▶ Supports power management for VGA monitor

▶ Multimedia Application

▶ Supports DDC1, DDC2B and DDC 3.0 specifications

▶ Supports RAMDAC snoop fir multimedai applications

▶ Miscellaneous

▷ Lead-free package

▶ RoHS compliance

![The image displays a white document icon with the top-right corner folded down. It features several horizontal gray lines representing text and a large, thick red checkmark superimposed over the center.](.cpci-3920-50-15064-1020-220/9774131bd19933496ef108f1127f54431f0bdc163f192909f50c12f2bec76f9e.jpg)
NOTE:

The Z11 doesn't support the Linux X11 performance bench test, which changes display mode frequently during every screen page. The display flickers when performing the X11 performance bench test under Linux.

# 3.2 Peripherals

The following standard peripherals are available on the cPCI-3920 board:

# Timer

The cPCI-3920 is equipped with the following timers:

# Real-Time Clock

The IICH contains real-time clock with 256-byte of battery-backed RAM.

The real-time clock performs timekeeping functions and includes 256 bytes of general purpose battery-backed CMOS RAM. Features include an alarm function, programmable periodic interrupt and a 100-year calendar. All battery-backed CMOS RAM data remains stored in an additional EEPROM. This prevents data loss in case the cPCI-3920 is operated without battery.

# Counter/Timer

Three 8254-style counter/timers are included on the cPCI-3920 as defined for the PC/AT (System Timer, Refresh Request, Speaker Tone Output).

In addition to the three 8254-style counters, the IICH includes three High Precision Event Timers (HPET) that may be used by the operating system. They are implemented as a single counter each with its own comparator and value register. They support One-shot and periodic interrupts.

# Watchdog Timer

The cPCI-3920 provides a Watchdog Timer that is programmable for a timeout period ranging from 1 ms to 1050 sec. Failure to trigger the Watchdog Timer in time results in a system reset, an interrupt, or NMI. In the dual-stage mode, a combination of both NMI, and reset if the Watchdog is not serviced. A hardware status flag will be provided to determine if the Watchdog Timer generated the reset.

# Battery

The cPCI-3920 is provided with a 3.0 V “coin cell” lithium battery for the RTC. To replace the battery, proceed as follows:

▶ Turn off power
▶ Remove the battery
▶ Place the new battery in the socket.
▶ Make sure that you insert the battery the right way round. The plus pole must be on the top!

The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. Suitable batteries include the Varta CR2025 and Panasonic BR2020.

![The image displays a white document icon with a folded top-left corner and faint horizontal lines resembling a list or form. A large, bold red checkmark is superimposed over the document, slanting upwards from the bottom left to the top right. The entire graphic is enclosed within a thin black border.](.cpci-3920-50-15064-1020-220/66b9b3d959ba0b9b01f1fa99938e1834a44dbed8e7bded778e46892390b0e523.jpg)
NOTE:

The user must be aware that the battery's operational temperature range is less than that of the cPCI-3920's storage temperature range. For exact range information, refer to the battery manufacturer's specifications.

![The image displays a white document icon with a folded top-right corner and horizontal gray lines. A large red checkmark is superimposed over the document. The text '2008' is visible in the bottom right corner.](.cpci-3920-50-15064-1020-220/ba3265989c97ed483aab3454078240daa31a2152bae7e6e8db93c7f0b2568a5d.jpg)
NOTE:

Care must be taken to ensure that the battery is correctly replaced. The battery should be replaced only with an identical or equivalent type recommended by the manufacturer. Dispose of used batteries according to the manufacturer's instructions. The typical life expectancy of a 225 mAh battery (Varta CR2032) is 4-5 years with an average on-time of 8 hours per working day at an operating temperature of $30^{\circ}$ C. However, this typical value varies considerably because the life expectancy is dependent on the operating temperature and the standby time (shutdown time) of the system in which it operates. To ensure that the lifetime of the battery has not been exceeded, it is recommended to exchange the battery after 3-4 years.

# Reset

A reset will be generated by the following conditions:

▶ Pressing the front panel reset button
▶ Watchdog overflow
▶ CompactPCI backplane PRST# input (CompactPCI connector J2, pin C17)

# SMBus Devices

The cPCI-3920 provides a System Management Bus (SMBus) for access to several system monitoring and configuration functions. The SMBus consists of a two-wire I2C bus interface.

The following table describes the function and address of every onboard SMBus device.

<table><tr><td>Device</td><td>SMBus Address</td></tr><tr><td>Clock Buffer</td><td>DCh</td></tr><tr><td>Clock Generator</td><td>D2h</td></tr><tr><td>SPD</td><td>A0h</td></tr><tr><td>EEPROM (Board VPD)</td><td>AEh</td></tr></table>

Table 3-2: SMBus Devices and Addresses

# Thermal Management / System Monitoring

The W83792AG can be used to monitor several critical hardware parameters of the system, including power supply voltages and temperatures, all of which are very important for the proper operation and stability of a high-end computer system.

The voltages +12 V, +5 V, +3.3 V, and Vcore are supervised. The temperature sensors monitor the CPU temperature and the ambient temperature to ensure that the system is operating at a safe temperature level. If the CPU temperature is too high, the sensor automatically reduces the CPU clock frequency, depending on the mode chosen in the BIOS settings.

# FWH Flash Memory

For simple BIOS updating a standard onboard 16 Mbit Firmware Hub device is used. The FWH stores both the system BIOS and graphics BIOS. It can be updated as new versions of the BIOS become available.

# LED Functions

There are three LEDs on the front panel, below table shows the function of LEDs.

<table><tr><td>Name</td><td>Color</td><td>Status</td><td>Function description</td></tr><tr><td rowspan="2">HOT</td><td rowspan="2">Red</td><td>BLINK</td><td>CPU reaches or exceeds max. operating temperature</td></tr><tr><td>OFF</td><td>CPU below max. operating temperature</td></tr><tr><td rowspan="2">WDT</td><td rowspan="2">Yellow</td><td>ON</td><td>WDT function enable</td></tr><tr><td>OFF</td><td>WDT function disable</td></tr><tr><td rowspan="2">PWR</td><td rowspan="2">Green</td><td>ON</td><td>Power on</td></tr><tr><td>OFF</td><td>Power off</td></tr></table>

Table 3-3: LED Function Descriptions

# 3.3 Board Interfaces

# USB Interfaces

The cPCI-3920 supports six USB 2.0 ports:

▶ one front I/O
▶ two front I/O on DB-3920L2 module
▶ one onboard to connect a Flash disk
▶ two on the Rear I/O module.

On the USB 2.0 front panel port, USB cable with up to 5 meters in length can be used.

On the USB 2.0 Rear I/O ports, it is strongly recommended to use a cable below 3 meters in length for USB 2.0 devices.

The USB 2.0 ports are high-speed, full-speed, and low-speed capable. Hi-speed USB 2.0 allows data transfers of up to 480 Mb/s - 40 times faster than a full-speed USB (USB 1.1). One USB peripheral may be connected to each port.

To connect more USB devices than there are available ports, an external hub is required.

Front Panel USB Connectors (CN2, CN4 -2, CN5-2)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![4\n3\n2\n1](.cpci-3920-50-15064-1020-220/be47d0a2441514fdd0e308074a1db54839ebf00cd2f2edd6d06978e69b0acfa7.jpg)

Table 3-4: Front Panel USB Connector Pin Definition

![The image displays a standard icon featuring a white document or sheet of paper with a folded top-right corner. Faint grey horizontal lines run across the lower portion of the paper, simulating text. Superimposed over the document is a large, bold red checkmark that runs diagonally from the bottom left to the top right.](.cpci-3920-50-15064-1020-220/83644d1db652cefcd7d3e3fff1b87b4275f72ac1383b97db33ccb1813f253678.jpg)
NOTE:

The cPCI-3920 host interfaces can be used with maximum 500 mA continuous load current as specified in the Universal Serial Bus Specification, Revision 2.0. Short-circuit protection is provided. All the signal lines are EMI-filtered.

# Onboard USB Pin Header (CN5)

The onboard USB device (CN5 pin header, 2.54mm pitch) is used to connect a USB Flash Disk.

The following figure and table provide pinout information for the onboard USB pin header CN5:

<table><tr><td>Pin</td><td>Signal</td><td>Function</td><td>I/O</td></tr><tr><td>1</td><td>Vcc</td><td>VCC</td><td>--</td></tr><tr><td>2</td><td>Uv0-</td><td>Differential USB-</td><td>I/O</td></tr><tr><td>3</td><td>Uv0+</td><td>Differential USB+</td><td>I/O</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>--</td></tr><tr><td>5</td><td>--</td><td>Not connected</td><td>--</td></tr><tr><td>6</td><td>--</td><td>Not used</td><td>--</td></tr><tr><td>7</td><td>GND</td><td>GND</td><td>--</td></tr><tr><td>8</td><td>--</td><td>Not used</td><td>--</td></tr><tr><td>9</td><td>--</td><td>Not used</td><td>--</td></tr><tr><td>10</td><td>--</td><td>Not used</td><td>--</td></tr></table>

![10\n6\n1\n5](.cpci-3920-50-15064-1020-220/ca0734f098fdfe9b0489ae2eb3bdc8ee885e660c0497e21814299ee871e87c4c.jpg)

Table 3-5: Onboard USB Connector Pin Definition

# USB Flash Disk Mechanical Layout

▶ Maximum space reserved for USB flash disk is 50mm x 30mm (LxW)
▶ The distance between the centers of connector and screw hole is 27.3mm\~27.9mm
▶ Maximum allowable connector height is 9.78mm (under 4HP)

![CVB9\n71T2\n340WA\nMax. 50mm\nMax. 30mm\n27.3 ~ 27.9 mm](.cpci-3920-50-15064-1020-220/dd124be444797d2fea7c5fb6f995e455c12e6d66c5d443ee0da8f7b93cce812e.jpg)

Figure 3-2: USB Flash Disk Mechanical Layout

# Graphics Controller

The Volari™ Z11 graphics controller incorporates a powerful 64-bit graphics engine to enhance the performance of 2D operations. The capabilities of the graphics engine include, but are not limited to BitBlt, Color Expansion, Enhanced Color Expansion, Line Drawing, Transparent BitBlt, and Rectangle Fill.

For all enhanced 256 color (8 bpp), 32k & 64k hi-color (16 bpp), and 16M true color (32 bpp) graphics modes, the 2D engine supports the following functions:

▶ 256 raster operations
▶ Rectangle fill
▶ Color expansion
▶ Enhanced Color expansion
▶ Line drawing with styled pattern
▶ Built-in bytes pattern registers
▶ Built-in 8x8 mask registers
▶ Rectangle Clipping Transparent BitBlt with source and destination keys
▶ Source data in command queue Bitblt

The engine also supports new GDI 2000 functions

# PCI Bus Interface

The Volari™ Z11 GPU is a native PCI-E device which connects directly to the PCI-E bus onboard the motherboard. The Z11 decodes 32-bit addresses and configures the device based on the applicable control lines between the target and initiator. The GPU can execute both I/O and memory access instructions as a 32-bit device.

# BroadBahn™ Memory Architecture

The internal memory controller of the Z11 generates the timing parameters for display memory. It supports the DDRII SDRAM timing specifications

The frequency of the Volari™ Z11 memory controller interface is synchronous with the 2D engine at 125MHz with the I/O interface at 250MHz. It can support up to a 1GB/s bandwidth, with a 16-bit DDRII SDRAM interface.

A DRAM capacity of 32MB is currently supported on cPCI-3920 boards.

# VGA Analog Interface and Connector (CN3)

The 15-pin female connector CN3 is used to connect a VGA analog monitor to the cPCI-3920 board.

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>Red</td><td>1</td><td>2</td><td>Green</td></tr><tr><td>Blue</td><td>3</td><td>4</td><td>N.C.</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>+5V.</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>N.C.</td><td>11</td><td>12</td><td>CRTDATA</td></tr><tr><td>HSYNC</td><td>13</td><td>14</td><td>VSYNC</td></tr><tr><td>CRTCLK</td><td>15</td><td></td><td></td></tr></table>

![10\n5\n15\n11\n6\n1](.cpci-3920-50-15064-1020-220/8b5039f13f29f3fc82e93c3dd52ce2560fe440c48f9aec4c838693608e37335b.jpg)

Table 3-6: VGA Connector CN3 Pin Definition

# Dual Gigabit Ethernet

The cPCI-3920 board includes two 10Base-T/100Base-TX/1000Base-T Ethernet ports based on the Dual Gigabit Ethernet controller, which is connected to the x4 PCI Express interfaces of the Intel® 3100.

The Intel® 82571EB Dual Gigabit Ethernet Controller's architecture is optimized to deliver high performance with the lowest power consumption. The controller's architecture includes independent transmit and receive queues and a PCI Express interface that maximizes the use of bursts for efficient bus usage.

The Boot from LAN feature is supported.

![The image displays an icon of a white document with faint horizontal lines and a large red checkmark overlaid on the left side.](.cpci-3920-50-15064-1020-220/ef44419bc6339cb1843288e3bcc3c6ff410b66983081d9cf5c7c2e80392f7fdb.jpg)
NOTE:

The Ethernet transmission can operate effectively using a CAT5 cable or higher specifications.

# Gigabit Connector RJ-45 Pin Definitions (CN7/CN8)

The CN7/CN8 connector supplies the 10Base-T, 100Base-TX and 1000Base-T interfaces to the Ethernet controller.

CN7
![The image displays the numbers 1 and 8 at the top, positioned above a black square frame. Inside the square, a row of small yellow rectangular dashes is centered near the top. At the bottom, a green oval is positioned on the left side, and a yellow oval is positioned on the right side.](.cpci-3920-50-15064-1020-220/eb83684e41a6c514d30c97053df3f8bdb324604fe875acb1795a81dff0e52864.jpg)
CN8

![A simple line drawing of a window frame. Inside the upper pane, there is a string of asterisks: ***********. Below the window sill, there are two small rectangular shapes, one with a green top and one with a yellow top.](.cpci-3920-50-15064-1020-220/4a3ba5028ee5f3b50f05d9bc3c5bfabc09875cf9d7882f2d24c13c9a67dbdfe8.jpg)
Speed Act

<table><tr><td colspan="2">10BASE--T</td><td colspan="2">100BASE--TX</td><td colspan="2">1000BASE--T</td><td>PIN</td></tr><tr><td>I/O</td><td>SIGNAL</td><td>I/O</td><td>SIGNAL</td><td>I/O</td><td>SIGNAL</td><td></td></tr><tr><td>O</td><td>TX+</td><td>O</td><td>TX+</td><td>I/O</td><td>BI_DA+</td><td>1</td></tr><tr><td>O</td><td>TX-</td><td>O</td><td>TX-</td><td>I/O</td><td>BI_DA-</td><td>2</td></tr><tr><td>I</td><td>RX+</td><td>I</td><td>RX+</td><td>I/O</td><td>BI_DB+</td><td>3</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DC+</td><td>4</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DC-</td><td>5</td></tr><tr><td>I</td><td>TX--</td><td>I</td><td>RX--</td><td>I/O</td><td>BI_DB-</td><td>6</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DD+</td><td>7</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DD-</td><td>8</td></tr></table>

Table 3-7: Gigabit Connector CN7/CN8 Pin Definitions

# Ethernet LED Status

SPEED (green):

When green it indicates a 1000BASE-TX connection. When not lit and the ACT-LED is active, the connection is operating at 100BASE-T.

ACT (yellow):

This LED monitors network connection and activity. The LED lights up when a valid link (cable connection) has been established. The LED goes temporarily off if network packets are being sent or received through the RJ-45 port. When this LED remains off, a valid link has not been established due to a missing or a fault connection.

<table><tr><td colspan="2">Status</td><td>Speed LED</td><td>Act LED</td></tr><tr><td colspan="2">Network link is not established</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10/100 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blink</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>ON</td><td>ON</td></tr><tr><td>Active</td><td>ON</td><td>Blink</td></tr></table>

Table 3-8: Ethernet LED Status Definitions

# Board-to-Board Connector

The 60-pin female Board-to-Board Connector (CN4) connects the main board to the DB-3920L2 daughter board, allowing I/O expansion and HDD connectivity for the cPCI-3920B 8HP version. The DB-3920L2 provides the following interfaces:

▶ Two USB2.0 ports
▶ Low pin count bus
▶ PS/2 Keyboard Mouse port
▶ SATA port with power
▶ XDP debug port

Legend for CN4 Pin Assignment

<table><tr><td>USBx</td><td>USB Interface and power</td></tr><tr><td>SATAx</td><td>Serial ATA port</td></tr><tr><td>LPCx</td><td>Low pin count interface</td></tr><tr><td>Kx, Mx</td><td>KB/MS port</td></tr><tr><td>XDPx</td><td></td></tr><tr><td>BPMx</td><td>XDP related signals</td></tr><tr><td>Tx</td><td></td></tr></table>

CN4 Pin Assignment

<table><tr><td>SIGNAL</td><td>PIN</td><td>PIN</td><td>SIGNAL</td></tr><tr><td>GND</td><td>1</td><td>2</td><td>LPC_FRAME#</td></tr><tr><td>USB3-D-</td><td>3</td><td>4</td><td>LPC_AD[3]</td></tr><tr><td>USB3-D+</td><td>5</td><td>6</td><td>LPC_AD[2]</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>LPC_AD[1]</td></tr><tr><td>USB2_D-</td><td>9</td><td>10</td><td>LPC_AD[0]</td></tr><tr><td>USB2_D+</td><td>11</td><td>12</td><td>PCIRST</td></tr><tr><td>GND</td><td>13</td><td>14</td><td>CLK33</td></tr><tr><td>SATA0_RX-</td><td>15</td><td>16</td><td>GND</td></tr><tr><td>SATA0_RX+</td><td>17</td><td>18</td><td>+5V</td></tr><tr><td>GND</td><td>19</td><td>20</td><td>+5V</td></tr><tr><td>SATA0_TX+</td><td>21</td><td>22</td><td>+5V</td></tr><tr><td>SATA0_TX-</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>+3.3V</td></tr><tr><td>USB3_PWR</td><td>27</td><td>28</td><td>+3.3V</td></tr><tr><td>USB2_PWR</td><td>29</td><td>30</td><td>B2B_IN#</td></tr><tr><td>LPC_LDRQ0#</td><td>31</td><td>32</td><td>KB_CLK</td></tr><tr><td>A20GATE</td><td>33</td><td>34</td><td>KB_DAT</td></tr><tr><td>SERIRQ#</td><td>35</td><td>36</td><td>MS_CLK</td></tr><tr><td>KBD_RST#</td><td>37</td><td>38</td><td>MS_DAT</td></tr><tr><td>CPU_PWRGD</td><td>39</td><td>40</td><td>BPM[0]#</td></tr><tr><td>XDP_DBRESET#</td><td>41</td><td>42</td><td>BPM[1]#</td></tr><tr><td>TDI</td><td>43</td><td>44</td><td>BPM[2]#</td></tr><tr><td>TMS</td><td>45</td><td>46</td><td>BPM[3]#</td></tr><tr><td>TRST#</td><td>47</td><td>48</td><td>BPM[4]#</td></tr><tr><td>TCK</td><td>49</td><td>50</td><td>BPM[5]#</td></tr><tr><td>TDO</td><td>51</td><td>52</td><td>CPU_RST#</td></tr><tr><td>+1.05V</td><td>53</td><td>54</td><td>Reserved</td></tr><tr><td>+1.5V</td><td>55</td><td>56</td><td>Reserved</td></tr><tr><td>CLK100_ITP+</td><td>57</td><td>58</td><td>Reserved</td></tr><tr><td>CLK100_ITP-</td><td>59</td><td>60</td><td>Reserved</td></tr></table>

Table 3-9: Board-to-Board Connector Pin Definition

# Keyboard/ Mouse Interface

The keyboard controller is located on the cPCI-3920B and is 8042 software compatible.

The PC/AT standard keyboard/mouse connector is a PS/2-type 6-pin shielded Mini-DIN connector.

A Y-cable to connect a mouse device and/or a keyboard to the PS/2 connector is included in the package of cPCI-3920B.

PS/2 Keyboard/Mouse Connector

<table><tr><td>Pin #</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+5V</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

![6\n5\n4\n3\n2 1](.cpci-3920-50-15064-1020-220/b0d8835416d051b230adbf80517ea4db3cd580eb9d92e558e531f4e05448d4a9.jpg)

Table 3-10: PS/2 Keyboard/Mouse Connector Pin Definition
![An icon depicting a white document with horizontal grey lines and a folded top-left corner, overlaid with a large red checkmark.](.cpci-3920-50-15064-1020-220/0319e16147f51196afc1740b8dc0d76b673494faa5965a048ff290b8d32b9329.jpg)
NOTE:

The PS/2 power supply provides short-circuit protection and all the signal lines are EMI-filtered.

# Universal Serial Ports

Two PC-compatible serial RS-232, 9-pin D-Sub ports are available and fully compatible with the 16C550 controller. These port includes a complete set of handshaking and modem control signals. Data transfer rates up to 115.2 kB/s are supported.

The COM3 interface is routed to the connector CN1.

COM3 DB-9 Serial Port Connector (CN1)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD, Data carrier detect</td></tr><tr><td>2</td><td>RXD, Receive data</td></tr><tr><td>3</td><td>TXD, Transmit data</td></tr><tr><td>4</td><td>DTR, Data terminal ready</td></tr><tr><td>5</td><td>GND, Ground</td></tr><tr><td>6</td><td>DSR, Data set ready</td></tr><tr><td>7</td><td>RTS, Request to send</td></tr><tr><td>8</td><td>CTS, Clear to send</td></tr><tr><td>9</td><td>RI, Ring indicator</td></tr></table>

![6\n1\n5](.cpci-3920-50-15064-1020-220/863b67aa33b36cd3e573fef60fe142a16620c6657690d3eb582ccfcf2fb087f9.jpg)

Table 3-11: COM3 Serial Port Connector Pin Definition

The COM4 interface is routed to the connector CN6-2. The COM4 interface supports RS-232/422/485/485+.

COM4 DB-9 Serial Port Connector (CN6-2)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS422/485+</td><td>RS485</td></tr><tr><td>1</td><td>DCD, Data carrier detect</td><td>TXD-</td><td>Data-</td></tr><tr><td>2</td><td>RXD, Receive data</td><td>TXD+</td><td>Data+</td></tr><tr><td>3</td><td>TXD, Transmit data</td><td>RXD+</td><td>--</td></tr><tr><td>4</td><td>DTR, Data terminal ready</td><td>RXD</td><td>--</td></tr><tr><td>5</td><td>IsoGND, Isolated ground</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>DSR, Data set ready</td><td>--</td><td>--</td></tr><tr><td>7</td><td>RTS, Request to send</td><td>--</td><td>--</td></tr><tr><td>8</td><td>CTS, Clear to send</td><td>--</td><td>--</td></tr><tr><td>9</td><td>RI, Ring indicator</td><td>--</td><td>--</td></tr></table>

Table 3-12: COM4 Serial Port Connector Pin Definition

COM4 Mode Switch Settings

<table><tr><td></td><td>Location</td><td>SW1</td><td>SW2</td><td>SW3</td><td>SW4</td></tr><tr><td rowspan="4">RS232 Full Modem</td><td>1</td><td>ON</td><td>ON</td><td>OFF</td><td>ON</td></tr><tr><td>2</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>3</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td>4</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="4">RS422 Half Duplex</td><td>1</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>ON</td><td>ON</td><td>ON</td><td>ON</td></tr><tr><td>3</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>4</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="4">RS485 Half Duplex</td><td>1</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>2</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>4</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="4">RS485+ Half Duplex</td><td>1</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>2</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td>3</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>4</td><td>ON</td><td>ON</td><td>ON</td><td>ON</td></tr></table>

Table 3-13: COM4 Mode Switch Settings

# Serial ATA Interfaces

The cPCI-3920 provides up to four SATA interfaces. Three SATA ports, SATA1, SATA2 and SATA3, can be used only on the Rear Transition Module I/O interface. All SATA ports can be used simultaneously.

<table><tr><td>SATA Port</td><td>Connector</td><td>Usage</td></tr><tr><td>SATA0</td><td>CN3-2 on the cPCI-3920B</td><td>Onboard 2.5” DATA HDD drive mounted on CPCI-3920B</td></tr><tr><td>SATA1</td><td>CN5-R on the cPCI-R3920(T)</td><td>External SATA HDD drives, e.g. 2.5” or 3.5” SATA HDDs</td></tr><tr><td>SATA2</td><td>CN4-R on the cPCI-R3920(T)</td><td>External SATA HDD drives, e.g. 2.5” or 3.5” SATA HDDs</td></tr><tr><td>SATA3</td><td>CN2-R on the cPCI-R3920(T)</td><td>External SATA HDD drives, e.g. 2.5” or 3.5” SATA HDDs</td></tr></table>

The SATA connector, CN3-2, on the cPCI-3920B module is provided for connecting a 2.5\~ SATA HDD to the cPCI-3920B module. The SATA connector is divided into two segments, a signal segment and a power segment.

SATA0 Connector, CN3-2
![Signal\nSegment\nS1\nS7\nP1\nPower\nSegment\nP15](.cpci-3920-50-15064-1020-220/4c7525e88c254ef1ce0b058f984c80c0a07f583e966f9146e101515c5d72fd60.jpg)

SATA0 Connector, CN3-2

<table><tr><td>PIN</td><td>SIGNAL</td><td>FUNCTION</td><td>I/O</td></tr><tr><td colspan="4">Signal Segment Key</td></tr><tr><td>S1</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>S2</td><td>SATA_TX2+</td><td>Differential Transmit+</td><td>O</td></tr><tr><td>S3</td><td>SATA_TX2-</td><td>Differential Transmit-</td><td>O</td></tr><tr><td>S4</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>S5</td><td>SATA_RX2-</td><td>Differential Receive-</td><td>I</td></tr><tr><td>S6</td><td>SATA_RX2+</td><td>Differential Receive+</td><td>I</td></tr><tr><td>S7</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td colspan="4">Signal Segment &quot;L&quot;</td></tr><tr><td colspan="4">Central Connector Polarizer</td></tr><tr><td colspan="4">Power Segment &quot;L&quot;</td></tr><tr><td>P1</td><td>NC (3.3V)</td><td>Not connected</td><td>--</td></tr><tr><td>P2</td><td>NC (3.3V)</td><td>Not connected</td><td>--</td></tr><tr><td>P3</td><td>NC (3.3V)</td><td>Not connected</td><td>--</td></tr><tr><td>P4</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>P5</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>P6</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>P7</td><td>5V</td><td>5V power</td><td>--</td></tr><tr><td>P8</td><td>5V</td><td>5V power</td><td>--</td></tr><tr><td>P9</td><td>5V</td><td>5V power</td><td>--</td></tr><tr><td>P10</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>P11</td><td>RES</td><td>Reserved</td><td>--</td></tr><tr><td>P12</td><td>GND</td><td>Ground signal</td><td>--</td></tr><tr><td>P13</td><td>12V</td><td>12V power</td><td>--</td></tr><tr><td>P14</td><td>12V</td><td>12V power</td><td>--</td></tr><tr><td>P15</td><td>12V</td><td>12V power</td><td>--</td></tr><tr><td colspan="4">Power Segment Key</td></tr></table>

Table 3-14: SATA0 Connector Pin Definition

# CompactPCI Bus Interfaces

The complete CompactPCI connector configuration comprises two connectors named J1 and J2. Their function is as follows:

J1: 32-bit CompactPCI interface with PCI bus signals, arbitration, clock and power
▶ J2: has optional Rear I/O interface functionality or 64-bit termination

The board is capable of driving up to seven CompactPCI slots, with individual arbitration and clock signals. The cPCI-3920 is not hot-swappable but supports the addition or removal of other boards whilst in a powered-up state.

The cPCI-3920 is designed for a CompactPCI bus architecture. The CompactPCI standard is electrically identical to the PCI local bus. However, these systems are enhanced to operate in rugged industrial environments and to support multiple slots.

CompactPCI Connectors J1/J2
![F\nE\nD\nC\nB\nA\nZ\n1\nJ1\n25\n1\nJ2\n22](.cpci-3920-50-15064-1020-220/1154604c01e521ff8230e9343fde85e398389bdd800561f79d0c6baf5c5c64d1.jpg)

![The image features a line-drawing icon of a document with a folded top-right corner and three horizontal lines near the bottom. A large, red checkmark is superimposed over the document. Below the graphic, the text 'NOTE:' is written in black capital letters.](.cpci-3920-50-15064-1020-220/2581724e6d8f5524e48411b5e2410aa9c0cae1d7f96da33b686844d02c569224.jpg)

Pin rows F and Z are GND pins.

CompactPCI J1 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>+5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD[4]</td><td>AD[3]</td><td>+5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>+3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN(2)</td><td>C/ BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>C/ BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>N.C.</td><td>N.C.</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td>GND</td><td colspan="5">Key</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/ BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>+3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>+3.3V</td><td>CLK0</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>N.C.</td><td>N.C.</td><td>PCIRST#</td><td>GND</td><td>GNT[0]#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>GND</td><td>V(I/O)</td><td>INTP(1)</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>+5V</td><td>INTD#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>+5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#(3)</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td></td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Table 3-15: CompactPCI J1 Pin Assignment

# CompactPCI J2 Pin Assignment

The cPCI-3920 board provides Rear I/O connectivity for special compact systems. Some standard PC interfaces are implemented and assigned to the front panel and to the rear connector J2.

When the Rear I/O module is used, the signals of some of the main board/front panel connectors are routed to the Rear I/O module interface. Thus the Rear I/O module makes it much easier to remove the CPU in the rack as there is practically no cabling on the CPU board.

For the system Rear I/O feature a special backplane is necessary. The cPCI-3920 with Rear I/O is compatible with all standard CompactPCI passive backplanes with Rear I/O support on the system slot.

The cPCI-3920 Rear I/O provides the following interfaces:

▶ 32-bit/33 MHz CompactPCI (J1) and Rear I/O (J2)
▶ Two USB 2.0 ports
▶ Two Gigabit Ethernet ports without LED signals
▶ Three SATA ports
▶ Two COM ports
▶ Seven GPIOs

![The image displays a graphic icon of a white document or file with a folded top corner and faint horizontal lines. Superimposed over the center of the document is a large, bold red checkmark.](.cpci-3920-50-15064-1020-220/828fd4617fe1be40a5fc80541d9d03631704e466cbe5478a628244b0148245c8.jpg)
NOTE:

To support the Rear I/O feature a special backplane is necessary. Do not plug a Rear I/O configured board in a non-system slot Rear I/O backplane. Failure to comply with the above will result in damage to your board.

Legend for J2 Pin Assignment

<table><tr><td>USBx</td></tr><tr><td>ETHx</td></tr><tr><td>SATAx</td></tr><tr><td>COMx</td></tr><tr><td>GPIO x</td></tr><tr><td>PEX_RX0Lx</td></tr><tr><td>PEX_TX0Lx</td></tr></table>

USB interface and power

Gigabit Ethernet port

Serial ATA port

COM port

GPIO

1 x4 or 4 x1 PCI-Express

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>N.C</td><td>GA[4]</td><td>GA[3]</td><td>GA[2]</td><td>GA[1]</td><td>GA[0]</td><td>GND</td></tr><tr><td>21</td><td>N.C</td><td>CLK[6]</td><td>GND</td><td>COM1_RXD</td><td>COM2_RXD</td><td>GPIO7</td><td>GND</td></tr><tr><td>20</td><td>N.C</td><td>CLK[5]</td><td>GND</td><td>COM1_TXD</td><td>COM2_TXD</td><td>GPIO6</td><td>GND</td></tr><tr><td>19</td><td>N.C</td><td>GND/CLK100+</td><td>GND/CLK100+</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT</td><td>GND</td></tr><tr><td>18</td><td>N.C</td><td>SATA3_TX+</td><td>SATA3_TX-</td><td>GND</td><td>SATA3_RX+</td><td>SATA3_RX-</td><td>GND</td></tr><tr><td>17</td><td>N.C</td><td>USB4_D+</td><td>USB4_D</td><td>RST_BP#</td><td>N.C.</td><td>GNT[6]#pull</td><td>GND</td></tr><tr><td>16</td><td>N.C</td><td>USB4_PWR</td><td>USB5_PWR</td><td>DEGXB</td><td>GND</td><td>GPIO5</td><td>GND</td></tr><tr><td>15</td><td>N.C</td><td>USB5_D+</td><td>USB5_D</td><td>FALXB</td><td>N.C.</td><td>GNT[5]#pull</td><td>GND</td></tr><tr><td>14</td><td>N.C</td><td>SATA2_TX+</td><td>SATA2_TX-</td><td>GND</td><td>SATA2_RX+</td><td>SATA2_RX-</td><td>GND</td></tr><tr><td>13</td><td>N.C</td><td>SATA1_TX+</td><td>SATA1_TX-</td><td>GND</td><td>SATA1_RX+</td><td>SATA1_RX-</td><td>GND</td></tr><tr><td>12</td><td>N.C</td><td>PEX_RX0L0+</td><td>PEX_RX0L0-</td><td>GND</td><td>PEX_TX0L0</td><td>PEX_TX0L0-</td><td>GND</td></tr><tr><td>11</td><td>N.C</td><td>PEX_RX0L1+</td><td>PEX_RX0L1-</td><td>GND</td><td>PEX_TX0L1</td><td>PEX_TX0L1-</td><td>GND</td></tr><tr><td>10</td><td>N.C</td><td>PEX_RX0L2+</td><td>PEX_RX0L2-</td><td>GND</td><td>PEX_TX0L2</td><td>PEX_TX0L2-</td><td>GND</td></tr><tr><td>9</td><td>N.C</td><td>PEX_RX0L3+</td><td>PEX_RX0L3-</td><td>GND</td><td>PEX_TX0L3</td><td>PEX_TX0L3-</td><td>GND</td></tr><tr><td>8</td><td>N.C</td><td>ETH0_DA+</td><td>ETH0_DA-</td><td>GND</td><td>ETH0_DC+</td><td>ETH0_DC-</td><td>GND</td></tr><tr><td>7</td><td>N.C</td><td>ETH0_DB+</td><td>ETH0_DB-</td><td>GND</td><td>ETH0_DD+</td><td>ETH0_DD-</td><td>GND</td></tr><tr><td>6</td><td>N.C</td><td>ETH1_DA+</td><td>ETH1_DA-</td><td>GND</td><td>ETH1_DC+</td><td>ETH1_DC-</td><td>GND</td></tr><tr><td>5</td><td>N.C</td><td>ETH1_DB+</td><td>ETH1_DB-</td><td>GND</td><td>ETH1_DD+</td><td>ETH1_DD-</td><td>GND</td></tr><tr><td>4</td><td>N.C</td><td>V(I/O)</td><td>GPIO1</td><td>GPIO2</td><td>GPIO3</td><td>GPIO4</td><td>GND</td></tr><tr><td>3</td><td>N.C</td><td>CLK[4]</td><td>GND</td><td>GNT[3]#</td><td>N.C.</td><td>GNT[4]#pull</td><td>GND</td></tr><tr><td>2</td><td>N.C</td><td>CLK[2]</td><td>CLK[3]</td><td>SYSEN#</td><td>GNT[2]#</td><td>REQ[3]#</td><td>GND</td></tr><tr><td>1</td><td>N.C</td><td>CLK[1]</td><td>GND</td><td>REQ[1]#</td><td>GNT[1]#</td><td>REQ[2]#</td><td>GND</td></tr></table>

Table 3-16: CompactPCI J2 Pin Assignment

# 3.4 Board Interfaces on RTM

There are two identical USB interfaces on the CPCI-R3920(T) RTM, each with a maximum transfer rate of 480 Mb!s provided for connecting USB devices. One USB peripheral may be connected to each port. To connect more USB devices than there are available ports, an external hub is required.

# USB Connectors CN7-R and CN8-R

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![1\n2\n3\n4](.cpci-3920-50-15064-1020-220/8d8068bda707adda6b8b5a23fcf39945aa3b59f7e501c7ea69c645b192360abb.jpg)

Table 3-17: RTM USB Connector Pin Definitions

![The image displays a white document icon with a large red checkmark superimposed over it.](.cpci-3920-50-15064-1020-220/b1a0f053bc13057af503504e5885a71051bb5ac76eea7f6ee931de08d3288b3c.jpg)
NOTE:

The CPCI-R3920(T) host interfaces can be used with maximum 500 mA continuous load current as specified in the Universal Serial Bus Specification, Revision 2.0. Short-circuit protection is provided. All the signal lines are EMI-filtered. The Rear I/O interface supports the USB 1.1 and USB 2.0 standards. For USB 2.0 it is strongly recommended to use a cable length not exceeding 3 meters.

# Gigabit Ethernet Interfaces

Gigabit Ethernet signals are available either on the front R-J45 connector or on the Rear I/O interface due the implemented switches on the cPCI-3920. Both Gigabit Ethernet channels are individually switchable to front or Rear I/O. Switching over from front to Rear I/O or vice versa is effected using the BIOS settings or the board-specific registers (default: front I/O). For further information on the BIOS settings, refer to Chapter BIOS.

The interfaces provide automatic detection and switching between 10Base-T, 100Base-TX and 1000Base-T data transmission (Auto-Negotiation).

The CN6-R connector supplies the 10Base-T, 100Base-TX and 1000Base-T interfaces to the Ethernet controller.

# Gigabit Connector RJ-45 Pin Definitions (CN6-R)

The CN7/CN8 connector supplies the 10Base-T, 100Base-TX and 1000Base-T interfaces to the Ethernet controller.

<table><tr><td colspan="2">10BASE--T</td><td colspan="2">100BASE--TX</td><td colspan="2">1000BASE--T</td><td>PIN</td></tr><tr><td>I/O</td><td>SIGNAL</td><td>I/O</td><td>SIGNAL</td><td>I/O</td><td>SIGNAL</td><td></td></tr><tr><td>O</td><td>TX+</td><td>O</td><td>TX+</td><td>I/O</td><td>BI_DA+</td><td>1</td></tr><tr><td>O</td><td>TX-</td><td>O</td><td>TX-</td><td>I/O</td><td>BI_DA-</td><td>2</td></tr><tr><td>I</td><td>RX+</td><td>I</td><td>RX+</td><td>I/O</td><td>BI_DB+</td><td>3</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DC+</td><td>4</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DC-</td><td>5</td></tr><tr><td>I</td><td>TX--</td><td>I</td><td>RX--</td><td>I/O</td><td>BI_DB-</td><td>6</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DD+</td><td>7</td></tr><tr><td>--</td><td>--</td><td>--</td><td>--</td><td>I/O</td><td>BI_DD-</td><td>8</td></tr></table>

Table 3-18: RTM Gigabit Connector Pin Definitions

![The image displays a white document icon featuring horizontal black lines, overlaid with a large red checkmark.](.cpci-3920-50-15064-1020-220/fb7082e26021b0867850e9b9aeea6960acaf35df0dc9fa9f48a5a38164222665.jpg)
NOTE:

The Ethernet transmission can operate effectively using a CAT5 cable or higher specifications.

# COM1 and COM2 Interfaces

The CPCI-R3920(T) provides two COM ports from the Intel® 3100 chipset for connecting RS-232 devices to the CPCI-R3920(T).

The following tables provide pinout information for the 9-pin D-Sub COM connector CN3-R located on the front panel and the onboard COM connector CN1-R.

# COM1 DB-9 Serial Port Connector (CN3-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>not used</td></tr><tr><td>2</td><td>RXD, Receive data</td></tr><tr><td>3</td><td>TXD, Transmit data</td></tr><tr><td>4</td><td>not used</td></tr><tr><td>5</td><td>GND, Ground</td></tr><tr><td>6</td><td>not used</td></tr><tr><td>7</td><td>not used</td></tr><tr><td>8</td><td>not used</td></tr><tr><td>9</td><td>not used</td></tr></table>

![6\n1\n5](.cpci-3920-50-15064-1020-220/251726a29bae0557ac92fc4ed5a534cafd454d87d9a99e9a10f7bedc1c8fe9ef.jpg)

Table 3-19: COM1 Serial Port Connector Pin Definition

# COM2 Onboard Serial Port Connector (CN1-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>not used</td></tr><tr><td>2</td><td>not used</td></tr><tr><td>3</td><td>RXD, Receive data</td></tr><tr><td>4</td><td>not used</td></tr><tr><td>5</td><td>TXD, Transmit data</td></tr><tr><td>6</td><td>not used</td></tr><tr><td>7</td><td>not used</td></tr><tr><td>8</td><td>not used</td></tr><tr><td>9</td><td>GND, Ground</td></tr><tr><td>10</td><td>NC</td></tr></table>

![9\n1\n10\n2](.cpci-3920-50-15064-1020-220/95b714ccbfdd5425a3b5b4348b4bbcbf5f30bd2d614e1828de612fe79f5221f7.jpg)

Table 3-20: COM2 Serial Port Connector Pin Definition
![The image shows a white document icon with a folded top-right corner and faint horizontal lines. A large, red checkmark is superimposed over the center of the document.](.cpci-3920-50-15064-1020-220/21020b55de0a9955f26e57c5e0d36daee4affb211bf290ed0e8a7a0fb86a3f6d.jpg)
NOTE:

The serial ports of Intel® 3100 Chipset are not 100 percent compatible with other 16550 standard devices. If any system or software designer assumes that they are compatible with other 16550 standard devices and does not follow the specifications for the Serial I/O Unit in the Intel® 3100 Chipset Datasheet, errors or undesired behaviors may be observed.

# Serial ATA Interfaces - SATA1-3

The onboard Serial ATA connectors CN2-R, CN4-R and CN5-R allow the connection of standard HDDs and other Serial ATA devices to the cPCI-3920 Rear Transition Module.

The following figure and table provide pinout information for the SATA connectors CN2-R, CN4-R and CN5-R.

# SATA1-3 Connectors CN2-R, CN4-R and CN5-R

![6\n5\n3\n2\n7\n4\n1](.cpci-3920-50-15064-1020-220/46fd81795553b9655912e5f85be59c5fe2e63b366aac7f6625d09afcd908efe7.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>5</td><td>RX-</td></tr><tr><td>2</td><td>TX+</td><td>6</td><td>RX+</td></tr><tr><td>3</td><td>TX-</td><td>7</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td></td><td></td></tr></table>

Table 3-21: SATA1-3 Connectors Pin Definition

# Rear I/O Interfaces on CompactPCI Connector rJ2

The cPCI-3920 Rear Transition Module conducts a wide range of I/O signals through the Rear I/O connector rJ2.

To support the Rear I/O feature a special backplane is necessary. Do not plug a Rear I/O configured board in a non-system slot Rear I/O backplane. Failure to comply with the above may result in damage to your board.

CompactPCI Connector rJ2
![22\nrJ2\n1\nABCDE\nZ F](.cpci-3920-50-15064-1020-220/3a325b2b58c76439ba9b699b71677072f9bbe95ea2c3711e4dec8b41e6ffadb2.jpg)

# CompactPCI rJ2 Pin Assignment

# Legend for rJ2 Pin Assignment

USBx

ETHx

SATAx

COMx

USB interface and power

Gigabit Ethernet port

Serial ATA port

COM port

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>N.C.</td><td>GA[4]</td><td>GA[3]</td><td>GA[2]</td><td>GA[1]</td><td>GA[0]</td><td>GND</td></tr><tr><td>21</td><td>N.C.</td><td>CLK[6]</td><td>GND</td><td>COM1_RXD</td><td>COM2_RXD</td><td>N.C.</td><td>GND</td></tr><tr><td>20</td><td>N.C.</td><td>CLK[5]</td><td>GND</td><td>COM1_TXD</td><td>COM2_TXD</td><td>N.C.</td><td>GND</td></tr><tr><td>19</td><td>N.C.</td><td>GND/CLK100</td><td>GND/CLK100</td><td>SMB_SDA</td><td>SMB_SCL</td><td>SMB_ALERT</td><td>GND</td></tr><tr><td>18</td><td>N.C.</td><td>SATA3_TX+</td><td>SATA3_TX-</td><td>GND</td><td>SATA3_RX+</td><td>SATA3_RX-</td><td>GND</td></tr><tr><td>17</td><td>N.C.</td><td>USB4_D+</td><td>USB4_D</td><td>RST_BP#</td><td>N.C.</td><td>GNT[6]#pull</td><td>GND</td></tr><tr><td>16</td><td>N.C.</td><td>USB4_PWR</td><td>USB5_PWR</td><td>DEGXB</td><td>GND</td><td>GPIO5</td><td>GND</td></tr><tr><td>15</td><td>N.C.</td><td>USB5_D+</td><td>USB5_D</td><td>FALXB</td><td>N.C.</td><td>GNT[5]#pull</td><td>GND</td></tr><tr><td>14</td><td>N.C.</td><td>SATA2_TX+</td><td>SATA2_TX-</td><td>GND</td><td>SATA2_RX+</td><td>SATA2_RX-</td><td>GND</td></tr><tr><td>13</td><td>N.C.</td><td>SATA1_TX+</td><td>SATA1_TX-</td><td>GND</td><td>SATA1_RX+</td><td>SATA1_RX-</td><td>GND</td></tr><tr><td>12</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>GND</td><td>N.C.</td><td>N.C.</td><td>GND</td></tr><tr><td>11</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>GND</td><td>N.C.</td><td>N.C.</td><td>GND</td></tr><tr><td>10</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>GND</td><td>N.C.</td><td>N.C.</td><td>GND</td></tr><tr><td>9</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>GND</td><td>N.C.</td><td>N.C.</td><td>GND</td></tr><tr><td>8</td><td>N.C.</td><td>ETH0_DA+</td><td>ETH0_DA-</td><td>GND</td><td>ETH0_DC+</td><td>ETH0_DC-</td><td>GND</td></tr><tr><td>7</td><td>N.C.</td><td>ETH0_DB+</td><td>ETH0_DB-</td><td>GND</td><td>ETH0_DD+</td><td>ETH0_DD-</td><td>GND</td></tr><tr><td>6</td><td>N.C.</td><td>ETH1_DA+</td><td>ETH1_DA-</td><td>GND</td><td>ETH1_DC+</td><td>ETH1_DC-</td><td>GND</td></tr><tr><td>5</td><td>N.C.</td><td>ETH1_DB+</td><td>ETH1_DB-</td><td>GND</td><td>ETH1_DD+</td><td>ETH1_DD-</td><td>GND</td></tr><tr><td>4</td><td>N.C.</td><td>V(I/O)</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>N.C.</td><td>GND</td></tr><tr><td>3</td><td>N.C.</td><td>CLK[4]</td><td>GND</td><td>GNT[3]#</td><td>N.C.</td><td>GNT[4]#pull</td><td>GND</td></tr><tr><td>2</td><td>N.C.</td><td>CLK[2]</td><td>CLK[3]</td><td>SYSEN#</td><td>GNT[2]#</td><td>REQ[3]#</td><td>GND</td></tr><tr><td>1</td><td>N.C.</td><td>CLK[1]</td><td>GND</td><td>REQ[1]#</td><td>GNT[1]#</td><td>REQ[2]#</td><td>GND</td></tr></table>

Table 3-22: CompactPCI rJ2 Pin Assignment

# 4 Getting Started

The cPCI-3920 has been designed for easy installation. However, the following standard precautions, installation procedures, and general information must be observed to ensure proper installation and to preclude damage to the board, other system components, or injury to personnel.

# 4.1 Safety Requirements

The following safety precautions must be observed when installing or operating the cPCI-3920. ADLINK assumes no responsibility for any damage resulting from failure to comply with these requirements.

Exercised due care when handling the board as the heat sink can get very hot. Do not touch the heat sink when installing or removing the board. The board should not be placed on any surface or in any form of storage container until the board and heat sink have cooled down to room temperature.

If your board type is not specifically qualified as being hot swap capable, switch off the CompactPCI system power before installing the board in a free CompactPCI slot. Failure to do so could endanger your life or health and may damage your board or system.

Certain CompactPCI boards require bus master and/or Rear I/O capability. If you are in doubt whether such features are required for the board you intend to install, please check your specific board and/or system documentation to make sure that your system is provided with an appropriate free slot in which to insert the board.

This CompactPCI board contains electrostatically sensitive devices. Please observe the necessary precautions to avoid damage to your board:

▶ Discharge your clothing before touching the assembly. Tools must be discharged before use.

▶ Do not touch components, connector-pins or traces.

▶ If working at an anti-static workbench with professional discharging equipment, please do not omit to use it.

# 4.2 Installing the USB Flash Disk

The cPCI-3920 supports an onboard USB Flash Disk module via the CN5 pin header. To install a USB Flash Disk, follow the procedure below.

1. Secure the standoff to the underside of the module with the screw provided.
2. Align the module with the CN5 pin header and mounting hole as shown.

![bel-06118\n5550-5999\n-BA-F](.cpci-3920-50-15064-1020-220/7a4728c33991b78c7c8b47016961384551fca4282073efee2eae81cebab1aab4.jpg)

3. Insert the module onto the pin header and secure with the screw provided from the back side of the cPCI-3290.

![Close-up of a green circuit board with heat sink and sensor components, no visible text or symbols](.cpci-3920-50-15064-1020-220/30dc0d54f17f95440d77f497dde3af079db06bccd713e135aaf42f1055440e2b.jpg)

# 4.3 Installing the Hard Disk Drive (cPCI-3290B only)

The cPCI-3920B supports a slim-type 2.5" SATA HDD. If the cPCI-3920 comes with a pre-installed HDD, proceed to the next section.

To install the hard disk drive:

1. Place the HDD into the bracket as shown.

![Interior view of a hard disk drive with visible circuit board and internal components (no readable text or symbols)](.cpci-3920-50-15064-1020-220/f74d60cda0174fabd45f66ad475a74720ad91ff0f4fb4faa12e59d2b80965602.jpg)

2. Insert the HDD into the CN3-2 SATA signal/power connector.

![CN3-2](.cpci-3920-50-15064-1020-220/c7b4d8891582eb9a4ca07f4fc2c28dcda4e018a9f1c102b5148a33088ff5aaa1.jpg)

3. Tighten all four bracket screws to secure the HDD in place.

# 4.4 Installing the cPCI-3920 to the Chassis

To install the cPCI-3920 module to a CompactPCI chassis:

1. Refer to the chassis documentation before installing the cPCI-3920.
2. Turn off the power in both chassis front and rear.
3. Assign a system slot for the board. Make sure you assign the correct slot.
4. Remove the panel cover of the slot you have selected.
5. Remove the black plastic caps securing the mounting screws to the front panel.
6. Align the top and bottom edges of the board with the card guides on the chassis, then push the board until it is completely flushed on the chassis.
7. Move the locking handle inward until it is fully-latched. A slight resistance may be felt when inserting the board. If the resistance is too strong, check if there are bent pins on the backplane or if the board's connector pins are properly aligned with the connectors on the backplane.
8. Check if the board is seated properly on the slot. Secure the board with mounting screws (behind the upper and lower ejector)
9. Connect the cables and peripherals to the board, then turn the chassis on.

# 4.5 RTM (cPCI-R3920) Installation

Follow the typical cPCI board installation and removal procedures for the RTM. However, be careful when when inserting or removing RTMs to the chassis as these are shorter than front boards.

Refer to previous sections when connecting or installing peripherals to the RTM. Make sure that the RTMs you are installing are compatible with the cPCI-3920 Series.

![An icon of a white document with a folded top-right corner and faint horizontal lines. A large red checkmark is drawn diagonally across the paper.](.cpci-3920-50-15064-1020-220/526b048b10c53d4abf9e02a771297528ce9deb9ebbbd0aae0b26068cafb584ed.jpg)
NOTE:

You must install the correct RTM to enable some functionalities (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs.

# 4.6 Hot Swap Procedures

The cPCI-3920 is not designed for hot swap operation. Do not attempt to hot swap this board. However, the cPCI-3920 supports the addition or removal of other boards whilst in a powered-up state.

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# 5 Driver Installation

The cPCI-3920 drivers are available from the ADLINK All-In-One CD at X:\cPCI\cPCI-3920\, or from the ADLINK website (http://www.adlinktech.com). The following describes the driver installation procedures for Windows® 2000, Windows® XP or Windows® Server 2003:

1. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.
2. Install the chipset driver by running the program ...\Chipset\Inflnst\_AUTOL.exe.
3. Install the VGA driver and utilities by running the program ...\VGA\R1.09.05\_WHQL\_Windows\XGIRun.exe.
4. Install the LAN drivers by running the program ...\LAN\PRO2KXP.exe.

We recommend using the chipset, VGA, and LAN drivers provided on the ADLINK All-in-One CD or downloaded from the ADLINK website to ensure compatibility. Contact ADLINK to get support for Linux and VxWorks BSP drivers.

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# 6 Watchdog Timer

# 6.1 WDT Overview

This section explains the operation of the cPCI-3920's Watchdog Timer (WDT). The primary function of the WDT is to monitor the cPCI-3920 operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

▶ enabled and disabled
▶ reloading timeout value

![Based on the provided image, here is the accurate and concise description of the flowchart/block diagram:\n\n**Labeled Blocks:**\n*   LPC Interface\n*   Preload Value 1\n*   Preload Value 2\n*   Down-Counter\n*   Timeout/ Interrupt Control Logic\n\n**External Labels:**\n*   WDT_TOUT# (External)\n*   WDT_INT (Internal)\n\n**Connections:**\n*   **LPC Interface** connects to **Preload Value 1** and **Preload Value 2** (arrows point from LPC Interface to the Preload Values).\n*   **Preload Value 1** and **Preload Value 2** connect back to **LPC Interface** (arrows point from the Preload Values to the LPC Interface).\n*   **Preload Value 1** and **Preload Value 2** connect to **Down-Counter** (arrows point downwards).\n*   **Down-Counter** connects to **Timeout/ Interrupt Control Logic** (arrow points downwards).\n*   **Down-Counter** connects back to **LPC Interface** (arrow points left/upwards).\n*   **Timeout/ Interrupt Control Logic** connects back to **LPC Interface** (arrow points upwards/leftwards).\n*   **Timeout/ Interrupt Control Logic** connects to **WDT_TOUT# (External)** and **WDT_INT (Internal)** (arrows point downwards).](.cpci-3920-50-15064-1020-220/3f8c8286c2400fe50bbb1f0e6e80bce9dbda22f170fecdfb99cb0ab351d6500a.jpg)

Figure 6-1: cPCI-3920 Watchdog Timer Architecture

The cPCI-3920 implements the internal WDT unit of the Intel 3100 chipset and its LPC interface. It contains registers of device6 at the internal IO to control the WDT and retrieve its status. The basic functions of the WDT include:

▶ Setting the watchdog timeout interval
▶ Starting the timer countdown
▶ Selecting 1 step or 2 step WDT
▶ Enabling or disabling WDT
▶ Reloading the timeout value to keep the watchdog from timing out
▶ Setting the range of the timeout period from 1 $\mu$ s to 1 second, or from 1 ms to 1050 seconds

When the watchdog times out, it will send a RESET signal to the system.

# 6.2 Using the Watchdog Timer in an Application

The following section describes the WDT functions in an application. The WDT reset function is explained in the previous section. This can be controlled through the registers in the WDT unit of the Intel 3100 chipset.

An application using the reset feature enables the watchdog function, sets the count-down period, and reloads the timeout value periodically to keep it from resetting the system. If the timer count-down value is not reloaded, the watchdog resets the system hardware after its counter registers zero.

A detailed programming sample is provided below:

```c
#include&lt;dos.h&gt;
#include&lt;conio.h&gt;
#include&lt;stdio.h&gt;
#include&lt;stdlib.h&gt;

#defineconfig_port_index0x4E
#defineconfig_port_data0x4F

/* Pre-declaration */
/* access configuration registers routines */
void enter_config_mode();
void exit_config_mode();
```

```c
void write_config_data_byte(unsigned char, unsigned char);
unsigned char read_config_data_byte(unsigned char);
unsigned int read_wdt_io_base(); /* access wdt I/O registers routines */
void write_preload_val2_reg(unsigned long int);
void clear_preload_val1_reg();
void unlocking_reg();
/* Global parameter */
unsigned int wdt_io_base;
void main(void)
{
    // unsigned int wdt_io_base;
    unsigned long int time_out_val = 0;

    wdt_io_base = read_wdt_io_base();

    printf("Intel 3100 Chipset Watch-Dog Timer test utility.\n");
    printf("Intel 3100 WDT IO Base Address == 0x%x\n", wdt_io_base);

    while (1) //
    (time_out_val == 0) || (time_out_val > 1050)) {
    // 3sec printf("Please input the time to count down (1 - 1050 sec): ");
    // 3sec scanf("%d", &time_out_val);
    }

    // 3sectime_out_val = time_out_val * 1000; // transfer to msec unit.
    time_out_val = time_out_val + 3000; // 3sec clear_preload_val1_reg(); // we don't need preload_val1 caused internal interrupt.

    write_preload_val2_reg(time_out_val); // write preload_val2, it will cause external interrupt.(WDT_TOUT#)
```

```c
outportb(wdt_io_base+0x18,2);//watchdog
timer enable!!
printf("\nPlease waiting for Watch-Dog Timer
time-out!!");
}
/******************************/
unsigned int read_wdt_io_base()
{
    unsigned char_wdt_io_base[2];
    int *p_wdt_io_base;
    p_wdt_io_base=&_wdt_io_base;

    enter_config_mode();

    write_config_data_byte(0x07,6);//select
logic 6 - WDT

    _wdt_io_base[1]=read_config_data_byte(0x60);
    _
    _wdt_io_base[0]=read_config_data_byte(0x61);
    ;

    exit_config_mode();

    return (*p_wdt_io_base);
}
/******************************/
void enter_config_mode()
{
    outportb(config_port_index,0x80);

    outportb(0xeb,00); //io delay

    outportb(config_port_index,0x86);
}
/******************************/
void exit_config_mode()
{
    outportb(config_port_index,0x68);
```

```c
outportb(0xeb,00); //io delay
outportb(config_port_index,0x08);
}
/******************************/
unsigned char read_config_data_byte(unsigned char _index)
{
    unsigned char r_data;
    outportb(config_port_index,_index);
    outportb(0xeb,00); //io delay
    r_data=inportb(config_port_data);
    return(r_data);
}
/******************************/
void write_config_data_byte(unsigned char _index,unsigned char _data)
{
    outportb(config_port_index,_index);
    outportb(0xeb,00); //io delay
    outportb(config_port_data,_data);
}
/******************************/
void write_preload_val2_reg(unsigned long int _time_out_val)
{
    unsigned char *p_data;
    // "unsigned char" declaration --> p_data++ = addr. BYTE increased.
    p_data=&_time_out_val;
    printf("%x\n",*p_data);

    unlocking_reg();
    outportb(wdt_io_base+4,*p_data);
    p_data++;
    printf("%x\n",*p_data);
```

```c
unlocking_reg();
outportb(wdt_io_base+5,*p_data);
p_data++;
// printf("%x\n",*p_data);

unlocking_reg();
outportb(wdt_io_base+6,*p_data);
}
/**************************/
void clear_preload_val1_reg()
{
    unlocking_reg();
    outportb(wdt_io_base,0x00);

    unlocking_reg();
    outportb(wdt_io_base+1,0x00);

    unlocking_reg();
    outportb(wdt_io_base+2,0x00);

}
/**************************/
void unlocking_reg()
{
    outportb(wdt_io_base+12,0x80);

    outportb(0xeb,00); //io delay

    outportb(wdt_io_base+12,0x86);
```

# 7 BIOS Setup Utility

The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility.

# 7.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt; Press DEL to run Setup &gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.

![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST3B410A 007A](.cpci-3920-50-15064-1020-220/5edb12be5b206c18d2522280fe01cac4c0b80be4da9060e880912e85e9c5b726.jpg)

![The image features a white document icon with horizontal ruling lines and a large red checkmark superimposed on it. Below the graphic, the text 'NOTE:' appears in black capital letters.](.cpci-3920-50-15064-1020-220/44f0f5feb3ac4e30b326c9d613ee3b9c79508d0e92db1c60b4aef3c27cd3d029.jpg)

In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="6">System Overview</td><td rowspan="5">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Date.</td></tr><tr><td colspan="6">AMIBIOS</td></tr><tr><td colspan="6">Version :08.00.14Build Date:08/26/10ID:C3920B32</td></tr><tr><td colspan="6">Processor</td></tr><tr><td colspan="6">Speed :255MHzCount :255</td></tr><tr><td colspan="6">System MemorySize :1024MB</td><td rowspan="2">← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">System Time[00:00:51]System Date[Tue 01/01/2002]Input UUID</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

These keys include &lt;F1&gt;, &lt;F10&gt;, &lt;Enter&gt;, &lt;ESC&gt;, &lt;Arrow&gt; keys, and so on.

![This flowchart describes the navigation structure of a BIOS Setup Utility.\n\n**Labeled Blocks:**\n*   **BIOS Setup Utility** (Top center box)\n*   **Screens** (Text label below the top box)\n*   **Left and Right Keys to Select a Setup Screen** (Box on the left)\n*   **Screen 1**, **Screen 2**, **Screen 3**, **Screen 4**, **Screen 5** (Horizontal row of boxes)\n*   **Items** (Text label below the screen row)\n*   **Tab Key to Select Fields** (Box on the left)\n*   **±** (Symbol inside six boxes arranged in two rows of three)\n*   **+ To Change Field Values** (Box on the right)\n*   **Fields** (Text label on the left)\n*   **Up and Down Keys to Select a Setup Item** (Box on the right)\n\n**Connections:**\n*   A downward arrow connects **BIOS Setup Utility** to **Screens**.\n*   A dotted arrow connects **Left and Right Keys to Select a Setup Screen** to **Screen 1**.\n*   Double-headed horizontal arrows connect the screen row sequentially: **Screen 1** \$\leftrightarrow\$ **Screen 2** \$\leftrightarrow\$ **Screen 3** \$\leftrightarrow\$ **Screen 4** \$\leftrightarrow\$ **Screen 5**.\n*   A downward arrow connects the screen row (specifically from under **Screen 3**) to **Items**.\n*   A dotted arrow connects **Tab Key to Select Fields** to the top-left **±** box.\n*   Double-headed horizontal arrows connect the top row of **±** boxes.\n*   A dotted arrow connects **+ To Change Field Values** to the top-middle **±** box.\n*   Double-headed vertical arrows (one pointing down, one pointing up) connect the top row of **±** boxes to the bottom row.\n*   A dotted arrow connects **Up and Down Keys to Select a Setup Item** to the upward-pointing arrow between the rows.\n*   Arrows from **Fields** point to the left side of both the top and bottom rows of **±** boxes.\n*   Double-headed horizontal arrows connect the bottom row of **±** boxes.](.cpci-3920-50-15064-1020-220/c029879daedf48019ec06a9587c5de1ca38e40ab9448d72d1322d82023d5e291.jpg)

![The image displays a standard icon representing a document or file. It features a white sheet of paper with the top-left corner folded down. Faint horizontal lines run across the paper, suggesting text. Superimposed over the document is a large, bold red checkmark, indicating approval, completion, or verification.](.cpci-3920-50-15064-1020-220/42be21b5a800ac1e98219950bcc36f9e9c842f443098878e32f28d6f81d1ac6e.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

The &lt; F8 &gt; key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the &lt; F8 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

# Hotkey Descriptions

F1 The &lt; F1 &gt; key allows you to display the General Help screen.

Press the &lt; F1 &gt; key to open the General Help screen.

<table><tr><td colspan="4">General Help</td></tr><tr><td>←→</td><td>Select Screen</td><td>↓↑</td><td>Select Item</td></tr><tr><td>+-</td><td>Change Screen</td><td>Enter</td><td>Go to Sub Screen</td></tr><tr><td>PGDN</td><td>Next Page</td><td>PGUP</td><td>Previous Page</td></tr><tr><td>Home</td><td>Go to Top of the Screen</td><td>End</td><td>Go to Bottom of Screen</td></tr><tr><td>F2/F3</td><td>Change Colors</td><td>F7</td><td>Discard Changes</td></tr><tr><td>F8</td><td>Load Failsafe Defaults</td><td>F9</td><td>Load Optimal Defaults</td></tr><tr><td>F10</td><td>Save and Exit</td><td>ESC</td><td>Exit</td></tr><tr><td colspan="4">[Ok]</td></tr></table>

F10 The &lt; F10 &gt; key allows you to save any changes you have made and exit Setup. Press the &lt; F10 &gt; key to save your changes. The following screen will appear:

<table><tr><td colspan="2">Save configuration changes and exit now?</td></tr><tr><td>[Ok]</td><td>[Cancel]</td></tr></table>

Press the &lt;Enter&gt; key to save the configuration and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

ESC The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. The following screen will appear:

<table><tr><td colspan="2">Discard changes and exit setup now?</td></tr><tr><td>[Ok]</td><td>[Cancel]</td></tr></table>

Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

Enter The &lt; Enter &gt; key allows you to display or change the setup option listed for a particular setup item. The &lt; Enter &gt; key can also allow you to display the setup sub-screens.

# 7.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main BIOS Setup screen is shown below.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="6">System Overview</td><td rowspan="5">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Date.</td></tr><tr><td colspan="6">AMIBIOS</td></tr><tr><td colspan="6">Version :08.00.14Build Date:08/26/10ID:C3920B32</td></tr><tr><td colspan="6">Processor</td></tr><tr><td colspan="6">Speed :255MHzCount :255</td></tr><tr><td colspan="6">System MemorySize :1024MB</td><td rowspan="2">← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">System Time [00:00:51]System Date [Tue 01/01/2002]Input UUID</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the &lt;Arrow&gt; keys. Enter new values using the keyboard. Press the &lt;Tab&gt; key or the &lt;Arrow&gt; keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

![The image displays a white document icon with a folded top-right corner. Faint gray horizontal lines appear across the lower section. A large red checkmark is superimposed over the document.](.cpci-3920-50-15064-1020-220/199da5f199c6fda2b4d6da32fd149d80e8653a739d6a5f68e3d4911f58f510e7.jpg)
NOTE:

The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

# Input UUID

Use this function to set a unique Universally Unique Identifier (UUID) for the system.

# Main

UUID Configuration

WARNING: The UUID will be updated after boot.

System UUID : A4E399AE8DF5ADFBF4D4F2FA35F70AE1

UUID Byte 0-7 [ ]

UUID Byte 8-F [ ]

← Select Screen

↑↓ Select Item

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

UUID Byte 0-7

This field sets bytes 0-7 of the UUID.

UUID Byte 8-F

This field sets bytes 8-F of the UUID.

# 7.3 Advanced BIOS Setup

Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Advanced BIOS Setup screen is shown below.

The sub menus are described on the following pages.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="6">Advanced SettingsWARNING: Setting wrong values in below sections may cause system to malfunction.CPU ConfigurationIDE ConfigurationAHCI ConfigurationRemote Access ConfigurationUSB ConfigurationSystem Hardware HealthConfigure CPU.← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# CPU Configuration

You can use this screen to select options for the CPU Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. CPU Configuration screens for the available CPUs are shown below.

# Intel® Core™2 Duo L7400

# BIOS SETUP UTILITY

# Advanced

# Configure advanced CPU settings

Module Version:3F.02

Manufacturer:Intel

Frequency :255MHz

FSB Speed :113MHz

Cache L1 :0 KB

Cache L2 :0 KB

Ratio Actual Value:9

Hardware Prefetcher [Enabled]

Adjacent Cache Line Prefetch [Enabled]

Intel(R) Virtualization Tech [Enabled]

Intel(R) SpeedStep(tm) tech [Enabled]

ACPI T-STATE tech [Enabled]

This should be enabled in order to enable or disable the Hardware Prefetcher Disable Feature.

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Hardware Prefetcher

The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads.

When Enabled, the processor's hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor. When Disabled, the processor's hardware prefetcher will be disabled.

# Adjacent Cache Line Prefetch

The processor has a hardware adjacent cache line prefetch mechanism that automatically fetches an extra 64-byte cache line whenever the processor requests for a 64-byte cache line.

This reduces cache latency by making the next cache line immediately available if the processor requires it as well.

When Enabled, the processor will retrieve the currently requested cache line, as well as the subsequent cache line. When Disabled, the processor will only retrieve the currently requested cache line.

# Intel® Virtualization Technology

This option is used to enable or disable the Intel® Virtualization Technology (IVT) extension, which is also known by the development code name of Vanderpool. It allows multiple operating systems to run simultaneously on the same system. It does this by creating virtual machines, each running its own x86 operating system. When Enabled, the IVT extensions will be enabled, allowing for hardware-assisted virtual machine management. When Disabled, the IVT extensions will be disabled. However, software virtual machine managers like VMware can still be used if virtualization is required.

# Intel® SpeedStep™ Technology

Allows you to Enable or Disable Intel® SpeedStep™ Technology. If SpeedStep is disabled, the CPU Frequency on XP/Linux option will become visible.

<table><tr><td>Hardware Prefetcher [Enabled]Adjacent Cache Line Prefetch [Enabled]Intel(R) Virtualization Tech [Enabled]Intel(R) SpeedStep(tm) tech [Disabled]ACPI T-STATE tech [Enabled]CPU Frequency on XP/Linux [1500MHz]</td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# ACPI T-State Tech

This option allows you to Enable or Disable ACPI throttling.

# CPU Frequency on XP/Linux

This option is used to manually set the CPU frequency on XP and Linux operating systems. The following options are available: 1500MHz, 1333MHz, 1166MHz, and 1000MHz.

Intel® Core™ Duo U2500

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>Configure advanced CPU settingsModule Version:3F.02Manufacturer:IntelFrequency :255MHzFSB Speed :113MHzCache L1 :0 KBCache L2 :0 KBRatio Actual Value:9Intel(R) Virtualization Tech [Enabled]Intel(R) SpeedStep(tm) tech [Enabled]</td><td>Disable: Disable GU3Enable: Enable GU3← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Intel® Virtualization Technology

This is used to enable or disable the Intel® Virtualization Technology (IVT) extension, which is also known by the development code name of Vanderpool. It allows multiple operating systems to run simultaneously on the same system. It does this by creating virtual machines, each running its own x86 operating system. When enabled, the IVT extensions will be enabled, allowing for hardware-assisted virtual machine management. When disabled, the IVT extensions will be disabled. However, software virtual machine managers like VMware can still be used if virtualization is required.

# Intel® SpeedStep™ Technology

This allows you to enable or disable Intel® SpeedStep™ Technology.

# Intel® Celeron® M ULV 423

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>Configure advanced CPU settingsModule Version:3F.02Manufacturer:IntelFrequency :255MHzFSB Speed :127MHzCache L1 :0 KBCache L2 :0 KBRatio Actual Value:8</td><td>← Select Screen↑↓ Select ItemF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# IDE Configuration

You can use this screen to select options for the IDE Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.

<table><tr><td colspan="3">BIOS SETUP UTILITY</td></tr><tr><td colspan="3">Advanced</td></tr><tr><td colspan="2">IDE Configuration</td><td rowspan="4">Select whether the IDE channels should be initialized in Compatible or Enhanced mode of operation.</td></tr><tr><td>ATA/IDE Configuration Configure SATA as</td><td>[Enhanced] [IDE]</td></tr><tr><td>Primary IDE MasterPrimary IDE SlaveSecondary IDE MasterSecondary IDE Slave</td><td>: [Not Detected]: [Not Detected]: [Not Detected]: [Not Detected]</td></tr><tr><td>Hard Disk Write ProtectIDE Detect Time Out (Sec)</td><td>[Disabled][35]</td></tr><tr><td></td><td></td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="3">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# ATA/IDE Configuration

This item specifies whether the IDE channels should be initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced.

# Configure SATA as

This item specifies SATA channels transport to what kind of channels. The settings are IDE mode and AHCI mode.

# Primary IDE Master, Primary IDE Slave, Secondary IDE Master, Secondary IDE Slave

Select one of the hard disk drives to configure it. Press &lt;Enter&gt; to access its sub menu.

# Hard Disk Write Protect

This will be affective only if device is accessed through BIOS. The settings are Enabled and Disabled.

# IDE Detect Time Out (Sec)

Select the time out value for detecting ATA/ATAPI devices. The settings are 0 sec, 5 sec, 10 sec, 15 sec, 20 sec, 25sec, 30 sec, and 35 sec.

# AHCI Configuration

While entering setup BIOS auto detects the presence of IDE devices.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>AHCI Settings</td><td rowspan="5">While entering setup,BIOS auto detects the presence of IDE devices. This displays the status of auto detection of IDE devices.</td></tr><tr><td>▶ AHCI Port0 [Not Detected]</td></tr><tr><td>▶ AHCI Port1 [Not Detected]</td></tr><tr><td>▶ AHCI Port2 [Not Detected]</td></tr><tr><td>▶ AHCI Port3 [Not Detected]</td></tr><tr><td></td><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Hardware Health Configuration

This option displays the current status of all of the monitored hardware devices / components such as voltages and temperatures.

<table><tr><td colspan="3">BIOS SETUP UTILITY</td></tr><tr><td colspan="3">Advanced</td></tr><tr><td colspan="2">System Hardware Health</td><td rowspan="3"></td></tr><tr><td colspan="2">CPU Temperature :39°C/102°FSystem Temperature :-12°C/53°F</td></tr><tr><td rowspan="2" colspan="2">VCORE :0.964 UVINO(+3.3V) :3.340 UVIN1(+1.8V) :1.824 UVIN2(+1.5V) :1.532 UVIN3(+12v) :11.976 UVCC :4.890 UVUSB :4.848 UVBAT :3.328 U</td></tr><tr><td>← Select Screen↑↓ Select ItemF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="3">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Remote Access Configuration

Remote Access Configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td colspan="2">Configure Remote Access type and parameters</td></tr><tr><td>Remote Access</td><td>[Enabled]</td></tr><tr><td>Serial port number</td><td>[COM1]</td></tr><tr><td>Base Address, IRQ</td><td>[3F8h, 4]</td></tr><tr><td>Serial Port Mode</td><td>[115200 8,n,1]</td></tr><tr><td>Flow Control</td><td>[None]</td></tr><tr><td>Redirection After BIOS POST</td><td>[Always]</td></tr><tr><td>Terminal Type</td><td>[ANSI]</td></tr><tr><td>UT-UTF8 Combo Key Support</td><td>[Enabled]</td></tr><tr><td>Sredir Memory Display Delay</td><td>[No Delay]</td></tr><tr><td></td><td></td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Remote Access

Select this option to Enabled or Disabled the BIOS remote access feature.

# Serial Port Number

Select the serial port you want to use for the remote access interface. You can set the value for this option to either COM1 or COM2. The Base Address and IRQ of the selected serial port is displayed.

# Serial Port Mode

Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1.

# Flow Control

Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software.

# Terminal Type

This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8.

# VT-UTF8 Combo Key Support

This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled.

# Sredir Memory Display Delay

This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec.

# USB Configuration

You can use this screen to select options for the USB Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>USB ConfigurationModule Version - 2.24.3-13.4USB Devices Enabled :1 Keyboard, 1 Hub, 1 DriveLegacy USB Support [Enabled]Port 64/60 Emulation [Disabled]USB 2.0 Controller [Enabled]► USB Mass Storage Device Configuration</td><td>Enables support for legacy USB. AUTO option disables legacy support if no USB devices are connected.&lt; Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Legacy USB Support

Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is not enabled, any attached USB mouse or USB keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or USB keyboard can control the system even when there are no USB drivers loaded on the system. Set this value to enable or disable Legacy USB Support.

Disabled Set this value to prevent the use of any USB device in DOS or during system boot.

Enabled Set this value to allow the use of USB devices during boot and while using DOS.

Auto This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS.

# Port 64/60 Emulation

It uses USB to receive the IO port 64/60 trap to emulate the legacy keyboard controller.

# USB 2.0 Controller Mode

The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps).

# 7.4 PCI/PnP Setup

Select the PCI/PnP tab from the setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Plug and Play BIOS Setup screen is shown below.

<table><tr><td colspan="5">BIOS SETUP UTILITY</td></tr><tr><td colspan="5">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td colspan="3">Advanced PCI/PnP Settings</td><td rowspan="15">▲</td><td rowspan="15">Available: Specified
IRQ is available to be
used by PCI/PnP
devices.
Reserved: Specified
IRQ is reserved for
use by Legacy ISA
devices.</td></tr><tr><td colspan="3">WARNING: Setting wrong values in below sections
may cause system to malfunction.</td></tr><tr><td>IRQ3</td><td colspan="2">[Available]</td></tr><tr><td>IRQ4</td><td colspan="2">[Available]</td></tr><tr><td>IRQ5</td><td colspan="2">[Available]</td></tr><tr><td>IRQ7</td><td colspan="2">[Available]</td></tr><tr><td>IRQ9</td><td colspan="2">[Available]</td></tr><tr><td>IRQ10</td><td colspan="2">[Available]</td></tr><tr><td>IRQ11</td><td colspan="2">[Available]</td></tr><tr><td>IRQ14</td><td colspan="2">[Available]</td></tr><tr><td>IRQ15</td><td colspan="2">[Available]</td></tr><tr><td>DMA Channel 0</td><td colspan="2">[Available]</td></tr><tr><td>DMA Channel 1</td><td colspan="2">[Available]</td></tr><tr><td>DMA Channel 3</td><td colspan="2">[Available]</td></tr><tr><td>DMA Channel 5</td><td colspan="2">[Available]</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# IRQ

Set this value to allow the IRQ settings to be modified. Available – This setting allows the specified IRQ to be used by a PCI/PnP device. Reserved – This setting allows the specified IRQ to be used by a legacy ISA device.

# DMA Channel

Set this value to allow the MDA settings to be modified. Available – This setting allows the specified DMA to be used by a PCI/PnP device. Reserved – This setting allows the specified DMA to be used by a legacy ISA device.

# 7.5 Boot Setup

Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. Select an item on the Boot Setup screen to access the sub menu for:

▶ Boot Settings Configuration
▶ Boot Device Priority
▶ Removable Devices

The Boot Settings screen is shown below:

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Boot Settings</td><td rowspan="2" colspan="2">Configure Settings during System Boot.← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="5">▶ Boot Settings Configuration▶ Boot Device Priority▶ Hard Disk Drives</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Boot Setting Configuration

Use this screen to select options for the Boot Settings Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

# BIOS SETUP UTILITY

# Boot

# Boot Settings Configuration

Quick Boot

[Enabled]

![Options\nDisabled\nEnabled](.cpci-3920-50-15064-1020-220/9645e8c9533be7a656af86133224a705bc3bdcf49cb46b60caa7fa32a3b6c2f9.jpg)

Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Quick Boot

Disabled – Set this value to allow the BIOS to perform all POST tests. Enabled – Set this value to allow the BIOS to skip certain POST tests to boot faster.

# Boot Device Priority

![BIOS SETUP UTILITY\nBoot\nBoot Device Priority\n1st Boot Device (USB:Generic STORAG)\nOptions\nUSB:Generic STORAGE DEVICE\nDisabled\nSpecifies the boot\nsequence from the\navailable devices.\nA device enclosed in\nparenthesis has been\ndisabled in the\ncorresponding type\nmenu.\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.cpci-3920-50-15064-1020-220/9f3b66f6a71eef563c4207c07350b787221b9ac39a1599eb4efa9e296ba0b128.jpg)

# Boot Devices Priority

This specifies the boot sequence from the available devices.

The 1st Boot Device is primary device.

# Removable Drives

![BIOS SETUP UTILITY\nBoot\nRemovable Drives\n1st Drive (USB:Generic STORAGE)\nOptions\nUSB:Generic STORAGE DEVICE\nDisabled\nSpecifies the boot\nsequence from the\navailable devices.\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit](.cpci-3920-50-15064-1020-220/aa5b6277065e60237495013f93b3c04119a89e60621ba49ddc6b0b152fd5fefd.jpg)

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Removable Drives

This specifies the Boot Device Priority sequence from available Removable Drives. Disabled – Set this menu to allow the BIOS to remove device on Boot Device Priority. Device name – Set this menu to allow the BIOS to stay device on Boot Device Priority

# 7.6 Security Setup

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Security Settings</td><td rowspan="2" colspan="2">Install or Change the password.</td></tr><tr><td rowspan="2" colspan="5">Supervisor Password :Not InstalledUser Password :Not InstalledChange Supervisor PasswordChange User PasswordClear User Password</td></tr><tr><td colspan="2">← Select Screen↑↓ Select ItemEnter ChangeF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="7">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Password Support

# Two Levels of Password Protection

Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password.

The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure.

# Remember the Password

Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM.

To access the sub menu for the following items, select the item and press &lt; Enter&gt;:

▶ Change Supervisor Password
▶ Change User Password
▶ Clear User Password

# Supervisor Password

Indicates whether a supervisor password has been set.

# User Password

Indicates whether a user password has been set.

# Change Supervisor Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the supervisor password.

# Change User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the user password.

# Clear User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to clear the user password.

# Change Supervisor Password

Select Change Supervisor Password from the Security Setup menu and press &lt; Enter &gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# Change User Password

Select Change User Password from the Security Setup menu and press &lt;Enter&gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# 7.7 Chipset Setup

Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display a Chipset BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Chipset BIOS Setup screen is shown below.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Advanced Chipset SettingsWARNING: Setting wrong values in below sections may cause system to malfunction.► SouthBridge Configuration</td><td>Configure South Bridge features.← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# South Bridge Configuration

You can use this screen to select options for the South Bridge Configuration. South Bridge is a chipset on the motherboard that controls the basic I/O functions, USB ports, audio functions, modem functions, IDE channels, and PCI slots. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option.

# BIOS SETUP UTILITY

# Chipset

# South Bridge Chipset Configuration

82571EB PCIE connect to

Onboard LAN Boot ROM control

On Board VGA

[RTM]

[Disabled]

[Enabled]

# Options

GigaLAN

RTM

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# 82571EB PCIE connect to

Set the onboard LAN to connect to either J2/RTM or Front I/O. The settings are RTM (J2) and GigaLAN (Front I/O).

# Onboard LAN Boot ROM control

Set this value to enable/disable the LAN Controller PXE function. The PXE function allows system boot from a network environment.

# Onboard VGA

You can use this option to control the onboard VGA. The settings are Enabled and Disabled.

# 7.8 Exit Menu

Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Exit BIOS Setup screen is shown below.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Exit OptionsSave Changes and ExitDiscard Changes and ExitDiscard ChangesLoad Optimal DefaultsLoad Failsafe Defaults</td><td colspan="2">Exit system setup after saving the changes.F10 key can be used for this operation.&lt; Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Save Changes and Exit

When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect.

Save Configuration Changes and Exit Now?

[Ok] [Cancel]

appears in the window. Select Ok to save changes and exit.

# Discard Changes and Exit

Select this option to quit Setup without making any permanent changes to the system configuration.

Discard Changes and Exit Setup Now?

[Ok] [Cancel]

appears in the window. Select Ok to discard changes and exit.

# Discard Changes

Select Discard Changes from the Exit menu and press &lt; Enter &gt;.

Select Ok to discard changes.

# Load Optimal Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems.

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Select Load Optimal Defaults from the Exit menu and press &lt;Enter&gt;.

Select Ok to load optimal defaults.

# Load Failsafe Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the FailSafe Setup options if your computer is experiencing system configuration problems.

Select Load Fail-Safe Defaults from the Exit menu and press &lt;Enter&gt;.

Load FailSafe Defaults?

[Ok] [Cancel]

appears in the window. Select Ok to load FailSafe defaults.

# Important Safety Instructions

Please read and follow all instructions marked on the product and in the documentation before operating the system. Retain all safety and operating instructions for future use.

▶ Please read these safety instructions carefully.
$\triangleright$ Please keep this User's Manual for future reference.
▶ The equipment should be operated within the recommended operating temperature.
The equipment should be operated only from the type of power source indicated on the rating label. Make sure the voltage of the power source is correct when connecting the equipment to the power outlet.
If the user's equipment has a voltage selector switch, make sure that the switch is set to the proper position for the area. The voltage selector switch is set at the factory to the correct voltage.
▶ For pluggable equipment, ensure they are installed near a socket-outlet that is easily accessible.
- Secure the power cord to prevent unnecessary accidents. Do not place anything over the power cord.
▶ If the equipment will not be in use for long periods of time, disconnect the equipment from mains to avoid being damaged by transient overvoltage.
▶ All cautions and warnings on the equipment should be noted.
▶ Please keep this equipment away from humidity.
▶ Do not use this equipment near water or a heat source.
▶ Place this equipment on a reliable surface when installing. A drop or fall could cause injury.
▶ Never pour any liquid into the opening, this could cause fire or electrical shock.

▶ Openings in the case are provided for ventilation. Do not block or cover these openings. Make sure there is adequate space around the system for ventilation when setting up the work area. Never insert objects of any kind into the ventilation openings.
▶ To avoid electrical shock, always unplug all power and modem cables from the wall outlets before removing covers.
▶ Lithium Battery provided (real time clock battery)

"CAUTION - Risk of explosion if battery is replaced by an incorrect type. Dispose used batteries as instructed in the instructions"

▶ The equipment should be checked by service personnel if one of the following situation arises:

The power cord or plug is damaged.
▷ Liquid has penetrated the equipment.
The equipment has been exposed to moisture.
The equipment is not functioning or does not function according to the user's manual.
The equipment has been dropped and damaged.
▷ If the equipment has obvious sign of breakage.

▶ Never open the equipment. For safety reasons, the equipment should only be opened by qualified service personnel.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan
台北縣中和市建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
Rm. 801, Power Creative E, No. 1, B/D
Shang Di East Rd., Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8625

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园
A1 栋 2 楼 C 区 (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,
High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

Tel: +49-211-495-5552

Fax: +49-211-495-5557

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 151-0072 東京都渋谷区幡ヶ谷
1-1-2 朝日生命幡ヶ谷ビル 8F
Asahiseimei Hatagaya Bldg. 8F
1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5333-6040

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 서울시 서초구 서초동 1506-25 한도 B/D 2 층
2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu,
Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India

Tel: +91-80-65605817

Fax: +91-80-22443548

Email: india@adlinktech.com
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