# cPCI-6636 Series

Value 6U CompactPCI®

Intel® Xeon® E3, Core™ i7/i3 Processor Blade

User’s Manual

![Back view of a green printed circuit board with various components and connectors (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/1dd90adddab86bfee4e95b4e30fea8dcf684baf673d52c910b6af8bcf5790c9b.jpg)

![Back view of a computer motherboard with visible circuit boards, connectors, and ventilation slots (no text or symbols)](.cpci-6636-50m-15111-2000-03/d544ab7ae0de5566e127dc0e69066fcda4bb22d5f64b7196a6e8e22d5614fa47.jpg)

![Back view of a green printed circuit board with multiple ports and connectors (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/9f3024297d8da1f337edcf62eaee50d49e9a1199406ea3d3aad7f5ac3e966943.jpg)

Manual Rev.: 0.3 Preliminary

Revision Date: January 10, 2025

Part No: 50M-15111-2000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>0.1</td><td>2018-08-20</td><td>Preliminary release</td></tr><tr><td>0.2</td><td>2020-01-03</td><td>Add Chapters 5-9; update Power Requirements</td></tr><tr><td>0.3</td><td>2025-01-10</td><td>Update BIOS settings</td></tr></table>

# Preface

# Copyright © 2025 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line, no text or labels present](.cpci-6636-50m-15111-2000-03/d9404ee61ba17215a251695bc0d723d1d23b061ee5f75cbb7444a5e21c9f65f9.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.cpci-6636-50m-15111-2000-03/cd1552367895bea7bff08b0d9b81916bffc38219f5b1d6fbd28e2c75e4a895f4.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.cpci-6636-50m-15111-2000-03/1d113de189019f61d2e033d704b0862e3264d0e17f9cdb1eaea07d2b39aac58b.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cpci-6636-50m-15111-2000-03/f3cbf15ce9f31e78711e7eb3310c916244c98390fff4109af9ae9e44f3f61885.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.cpci-6636-50m-15111-2000-03/c77ff5e1bde8c6e7a3b7e723baf0eb405df71d47fc81d8007e135411e45c1e3b.jpg)

ᑜ㔚ᳰ⺧࿁ᡴ

# California Proposition 65 Warning

![A yellow triangular warning sign with a black border and a black exclamation point in the center.](.cpci-6636-50m-15111-2000-03/54eeabeff111beb0e82e2f788d5c5fb1784f902a32ff3223c044e519cb5685ec.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a square icon featuring a white document with horizontal grey lines. The top-left corner of the document is folded over. A large, thick red checkmark is drawn diagonally across the center of the document. The entire graphic is enclosed within a thin black border.](.cpci-6636-50m-15111-2000-03/a561eddd0df2255da349bbf1a4109adf8e023064ea3978dceeaa4545cca56419.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a black border containing a black exclamation point in the center.](.cpci-6636-50m-15111-2000-03/1246176d659b85bab925fb3d773afdd1ee54183fdb08e22ada8c403d084b5483.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a red triangular warning sign with a thin white border. Centered within the red triangle is a black exclamation mark (!).](.cpci-6636-50m-15111-2000-03/76576048e8a1d75c8ac9a41b09e80206593606b689645a5cd819d1f828c9a6c1.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History.......... ii

# Preface ............ iii

# List of Figures ........ ix

# List of Tables ........ . xi

# 1 Introduction .........

1.1 Overview... 1
1.2 Features... 2
1.3 Model Number Decoder.... 4
1.4 Package Contents . 5

# 2 Specifications ......... 7

2.1 cPCI-6636 Series Specifications . 7
2.2 Block Diagrams.. 10
2.3 I/O Connectivity Table .. 11
2.4 Power Requirements .... 12

# 3 Functional Description ........ 15

3.1 Processors.... 15
3.2 Chipset.. 18
3.3 XMC .... 19
3.4 Intel® Turbo Boost Technology .... 19
3.5 Intel® Hyper-Threading Technology..... 20
3.6 Battery .. 20

# 4 Board Interfaces ....... . 21

4.1 cPCI-6636(D) Component Side Layout ... . 21
4.2 cPCI-6636D/DZ Assembly Layoutt . 22

4.3 cPCI-6636(D/DZ) Faceplate I/O... 23
4.4 Connector Pin Assignments.... 2 5
4.5 Switches and Buttons ... 38

# 5 Getting Started ...... . 43

5.1 CPU and Heatsink .. 43
5.2 CFast Card Installation ... 44
5.3 2.5" SATA Drive Installation.... 47
5.4 XMC Installation (cPCI-6636D/DZ only) .... 5 0
5.5 Installing the cPCI-6636(D/DZ) to the Chassis .. 55

# 6 Driver Installation...... .. 57

6.1 cPCI-6636 Drivers... 57

# 7 Utilities ........ . 59

7.1 Watchdog Timer.... 59

# 8 BIOS Setup Utility .......... ...... 65

8.1 Starting the BIOS .. 65
8.2 Main Setup...... 67

8.2.1 BIOS Information .. 68
8.2.2 Processor Information. .. 68
8.2.3 PCH Information .. .. 68
8.2.4 SPI Clock Frequency .. .. 69
8.2.5 System Management. .. 69
8.2.6 System Date and Time .. . 72

8.3 Advanced.. 73

8.3.1 Trusted Computing . . 73
8.3.2 AMT Configuration..... .. 73
8.3.3 PCH-FW Configuration .. .. 74
8.3.4 IT8786 Super IO Configuration.. .. 74
8.3.5 Serial Port Console.. . 76
8.3.6 CPU Configuration..... . 79
8.3.7 SATA Configuration ..... . 80

8.3.8 Network Stack Configuration .... . 82
8.3.9 CSM Configuration .... .. 83
8.3.10USB .. .. 84

8.4 Chipset.. 85

8.4.1 PCH-IO Configuration... . 87

8.5 Security ...... 89

8.5.1 Password Description.. . 89
8.5.2 \*Secure Boot Menu.... . 89

8.6 Boot .... 90

8.7 Save & Exit ... 91

8.7.1 Save Options .... . 91

# 9 Checkpoints & Beep Codes ....... . 93

9.1 Checkpoint Ranges ..... 93
9.2 Standard Checkpoints .. 93
9.3 OEM-Reserved Checkpoint Ranges... . 102

# Important Safety Instructions ...... . 103

# Getting Service....... 105

# List of Figures

Figure 2-1: cPCI-6636 Series Functional Block Diagram... ... 10
Figure 4-1: cPCI-6636(D) Component Side Layout . .. 21
Figure 4-2: cPCI-6636D/DZ Assembly Layout.. . 22
Figure 4-3: cPCI-6636(D/DZ) Faceplate I/O . 23
Figure 4-4: cPCI-6636 Series Switch Locations - Component Side. 38
Figure 4-5: cPCI-6636 Series Switch Locations - Solder Side......... 39

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# List of Tables

Table 2-1: cPCI-6636 Series Specifications ... 7

Table 2-2: cPCI-6636(D/DZ) I/O Connectivity...... .. 11

Table 4-1: cPCI-6636(D) Front Panel System LED Descriptions ... 24

Table 4-2: LAN1/2 RJ-45 GbE Pin Definitions.. . 25

Table 4-3: LAN LED Status Definitions.. . 25

Table 4-4: USB 3.0 Pin Definitions . . 26

Table 4-5: cPCI-6636(D) COM Pin Definitions . . 26

Table 4-6: cPCI-6636(D) COM RJ-45 to DB-9 Cable Pin Definitions27

Table 4-7: cPCI-6636DZ COM1/2 Pin Definitions... .. 27

Table 4-8: cPCI-6636DZ COM3/4 Pin Definitions... .. 28

Table 4-9: cPCI-6636DZ COM5/6 Pin Definitions... .. 28

Table 4-10: cPCI-6636DZ COM RJ-45 to 2x DB-9 Cable Pin Definitions 29

Table 4-11: DVI-I Connector Pin Definition.. . 30

Table 4-12: Serial ATA 7-pin Connector Pin Definition... .. 31

Table 4-13: Serial ATA Connector with power Pin Definition............ 31

Table 4-14: CFast Socket Pin Definition. . 32

Table 4-15: XMC Connector Pin Definition.. . 33

Table 4-16: CompactPCI J1 Connector Pin Definition... .. 34

Table 4-17: CompactPCI J2 Connector Pin Definition... .. 35

Table 4-18: CompactPCI J3 Connector Pin Definition.. .. 36

Table 4-19: CompactPCI J5 Connector Pin Definition.... . 37

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# 1 Introduction

# 1.1 Overview

The ADLINK cPCI-6636 Series is a 6U CompactPCI® processor blade based on the Intel® Xeon® E3 and 6th Generation Intel® Core™ i7/i3 Processors with Intel® HM170 or CM236 Chipsets. When paired with the Intel® CM236, the cPCI-6636 supports ECC memory. The cPCI-6636 supports up to 16GB onboard DDR4-2133 memory and 16GB DDR4-2133 via SODIMM. Total memory capacity is up to 32GB of DDR4-2133. The cPCI-6636 is a highly integrated processor blade fit for mission critical applications in industries ranging from automation to defence.

The cPCI-6636 Series supports flexible I/O interfaces with the cPCI-6636 in single-slot (4HP) and cPCI-6636D/DZ in dual slot (8HP) width form factors. Faceplate I/O for the cPCI-6636 (4HP) includes 2x GbE supported by an Intel® i219LM PHY controller and Intel® i210IT Ethernet controller, 3x USB 3.0, 1x RJ-45 serial port, and 1x DVI-I. Onboard I/O includes one 2.5" SATA drive space, one 7-pin SATA connector, and one CFast slot by adapter board. The cPCI-6636D (8HP) has identical I/O to the single-slot version, except that an XMC connector via PCIe x8 adapter board is supported in place of the CFast slot. A third configuration, the cPCI-6636DZ, supports 8x USB 3.0, 2x GbE, 6x serial TX/RX and 2x VGA on the faceplate, and the same onboard I/O as the two-slot "D" version. The cPCI-6636 Series supports with 66/64-bit PCI signaling. Additional signals including additional 3x SATA, up to 4x Ethernet ports, USB 2.0, PCIe x4, audio, display, and serial signals to rear J3 and J5 (DZ version supports no rear I/O). Graphics support is integrated on the Intel® processor with VGA and DVI-I options. Rear display output signal is reserved to J3 and J5 as option.

Rear I/O signals are available on cPCI-6636 and cPCI-6636D which are equipped with CompactPCI J3 and J5 connectors. Available to the RTM are up to 2x GbE to J3 by Intel® I210IT Ethernet controllers for PICMG 2.16, and an additional 2x GbE switchable to rear from the front panel for a total of up to 4x Ethernet to rear J3 and J5. Also available are 1x VGA to J3, 1x TMDS to J5, 2x SATA 1.5 Gb/s to J3, 1x SATA 1.5 Gb/s to J5, 6x USB 2.0 to

J3, 10x GPIO to J3 and J5, HDA and KB/MS to J3, and serial ports to J5. For PCIe expansion, the cPCI-6636 offers one PCIe x4 or 4x PCIe x1 to J5.

The ADLINK 8HP cPCI-6636DZ only supports operation in host slots, whereas the cPCI-6636 and cPCI-6636D operate independently in both host and peripheral slots without CompactPCI bus communication (satellite mode), making it ideal for high density computing platforms. Moreover, the cPCI-6636 supports remote manageability by SEMA for system health monitoring over the Internet.

The cPCI-6636 Series offers outstanding computing power from the latest Intel® processors and is an ideal solution for military, automation and other robust computing applications that require the highest computing power in a rugged, reliable CompactPCI system.

# 1.2 Features

 6U CompactPCI blade in 4/8HP width form factor
 14nm uFC-BGA Intel® Processor
 Intel ® Xeon® E3-1505M v5, 2.8/3.7GHz, 4C/8T, GT2, 8M, 45W (35W by cTDP)
 Intel ® Core™ i7-6820EQ 2.8/3.5GHz, 4C/8T, GT2, 8M, 45W
 Intel ® Core™ i3-6100E 2.7GHz, 2C/4T, GT2, 3M, 35W

 One channel DDR4-2133 soldered SDRAM with ECC up to 16GB; one channel with one socket SO-DIMM DDR4-2133 ECC memory up to 16GB (ECC is supported by default on cPCI-6636 and cPCI-6636D, Core™ i7 SKUs do not support ECC)

 Supports up to two independent displays
 cPCI-6636, cPCI-6636D support one DVI-I on front panel, additional 2x DVI routed to J3 and J5
 cPCI-6636DZ support 2x VGA on front panel, no rear I/O graphics
? 64-bit/66MHz CompactPCI interface based on PCI specifications, universal V(I/O)
 cPCI-6636DZ supports operation in host slot only

cPCI-6636, cPCI-6636D support satellite mode operation in host and peripheral slots
 One PCIe x8 Gen3 XMC site on cPCI-6636D and cPCI-6636DZ
 Supports SEMA for system health monitoring
 2x Gigabit Ethernet egress ports on faceplate provided by an Intel® I219LM and I210IT GbE controller via PCIe x1 and two additional Gigabit Ethernet ports Intel® I210IT routed to J3 (PICMG 2.16 compliant); all four GbE can be routed to rear
 1x 2.5" SATA drive space and one 7-pin SATA on all cPCI-6636 Series
 1x CFast slot on cPCI-6636 single-slot version
 1x XMC slot on cPCI-6636D and cPCI-6636DZ
 2x SATA 1.5 Gb/s to J3, 1x SATA 1.5 Gb/s to J5
 6x USB 2.0, HDA, KB/MS, RS-232 to J3
 RS-232 TX/RX to J5
 10x GPIO to J3 and J5
 TPM 2.0 support (Infineon SLB 9665XT2.0), not supported by cPCI-6636DZ

# 1.3 Model Number Decoder

cPCI-ET 6636SLXX/6820E/M X-X/X

(A )

(D)(E)(F)

(A) Operating Temperature Code

Blank = 0°C to +60°C

ET= -20°C to +70°C (for CPUs with TDP below 37W only)

(B) Configuration Code

Blank = cPCI-6636 single slot with I/O (DVI-I, COM, USB 3.0 x3, GbE x2), CFast slot, and J3/J5

D = cPCI-6636D dual slot with I/O (DVI-I, COM, USB 3.0 x3, GbE x2), XMC slot, and J3/J5

DZ = cPCI-6636DZ dual slot with I/O (VGA x2, COM x6, USB 3.0 x8, GbE x2) and XMC slot, without J3/J5

(C) CPU Code

1505Mv5= Xeon® E3-1505M v5

6820E = Core™ i7 6820EQ

6100E = Core™ i3 6100E

(D) Onboard Memory Capacity Code

M4 = 4GB onboard memory

M8 = 8GB onboard memory

M16 = 16GB onboard memory

(E) SODIMM Memory Capacity Code

4 = 4GB SODIMM

8 = 8GB SODIMM

16 = 16GB SODIMM

(F) Other information

# 1.4 Package Contents

The cPCI-6636 is packaged with the following components. If any of the following items are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of cPCI-6636 Series non-standard configurations will vary depending on customer requests.

# cPCI-6636(D) Processor Blade

 Processor Blade
 CPU and memory specifications will differ depending on options selected
 Thermal module is assembled on the board
 RJ-45 to DB-9 COM adapter cable (P/N: 30-01020-0200)
 2.5" SATA drive accessory pack (P/N: 58-99097-0010)
 2.5” SATA adapter board (P/N: 59-37571-0000)
 CFast accessory pack (P/N: 58-99300-0000, cPCI-6636 only)
? DB-CFAST adapter board (P/N: 59-37572-0000, cPCI-6636 only)

# cPCI-6636DZ Processor Blade

 Processor Blade
 CPU and memory specifications will differ depending on options selected
 Thermal module is assembled on the board

 2x RJ-45 to DB-9 COM adapter cable (P/N: 30-25044-1020)

 2.5" SATA drive accessory pack (P/N: 58-99097-0010)

 2.5” SATA adapter board (P/N: 59-37571-0000)

# Rear Transition Module

 Dependent on the module selected

![The image displays a white document icon with a folded upper-right corner and faint horizontal lines running across the page. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6636-50m-15111-2000-03/41f6dd5db6d2316adda49f347bc0638d1c28ce5123af72d3607533bcf4d64a3f.jpg)
NOTE:

The contents of non-standard cPCI-6636 configurations may vary depending on the customer’s requirements.

![This image displays a standard warning sign featuring a yellow equilateral triangle with a thick black border. Inside the triangle is a large black exclamation point. Below the triangle, the word 'CAUTION:' is printed in black, uppercase letters.](.cpci-6636-50m-15111-2000-03/0ac18ab84a26e64868737e885ddcf01c6284eba26acc1a79c47812af5aaeaf2b.jpg)

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

2.1 cPCI-6636 Series Specifications

<table><tr><td>CompactPCI®Standards</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev. 2.0PICMG® 2.16 Packet Switching Backplane Rev. 1.0</td></tr><tr><td>Mechanical</td><td>Standard 6U CompactPCI®Board size: 233mm x 160mmSingle/dual-slot (4/8HP, 20.32/40.64mm)CompactPCI® connectors: J1, J2, J3, J5 (cPCI-6636, cPCI-6636D)CompactPCI® connectors with J1, J2 connectors (cPCI-6636DZ)</td></tr><tr><td>Processor</td><td>Intel® Xeon® E3-1505M v5 Processor, dual core, dual thread, 2.7 GHz, 3MB Smart Cache, TDP 35WIntel® CoreTM i7-6820EQ Processor, quad core, eight thread, 2.8 GHz (3.5 GHz Turbo), 8MB Smart Cache, TDP 45W (Note: does not support ECC)Intel® CoreTM i3-6100E Processor, dual core, four thread, 2.7 GHz, 3MB Smart Cache, TDP 35WPassive heatsink</td></tr><tr><td>Chipset</td><td>cPCI-6636(D): Mobile Intel® CM236 Chipset (w/ ECC)cPCI-6636DZ: Mobile Intel® HM170 Chipset (w/o ECC)</td></tr><tr><td>Memory</td><td>Dual channel DDR4-2133 SDRAM, up to 32GB non-ECC memory via 2x SODIMMsOne channel soldered onboard up to 16GB; one channel ion SO-DIMM socket, up to 16GBECC supported by CM236 PCH on cPCI-6636(D) only (Note: CoreTM i7 SKUs do not support ECC)</td></tr><tr><td>Graphics</td><td>Intel® HD Graphics 530 integrated on Intel® CoreTM i7-6820EQ and CoreTM i3-6100E processorsIntel® HD Graphics P530 integrated on Intel® Xeon® processor E3-1505M v51-slot versions: one DVI-I port2-slot version: two VGA ports on front panel</td></tr></table>

Table 2-1: cPCI-6636 Series Specifications

<table><tr><td>Gigabit Ethernet</td><td>One PCIe x1 Intel® I2199LM GbE PHY and two three PCIe x1 Intel® I210IT Gigabit Ethernet controllersThree Two egress 10/100/1000BASE-T ports on front panel, one supporting Intel® AMT 9.0 by I219LM PHY controllerTwo 10/100/1000BASE-T ports to rear by defaultand tTheTwo front two 10/100/1000BASE-T ports switchable to rear for PICMG 2.16. (Total up to four GbE ports to rear total)</td></tr><tr><td>CompactPCI Bus</td><td>PCI 64-bit/66MHz; 3.3V, 5V universal V I/OAll models support Host mode operation as a master in host slots and cPCI-6636(D) support Satellite mode operation as a standalone computer without connection to the PCI bus</td></tr><tr><td>Serial Ports</td><td>cPCI-6636DZ: three RJ-45 on faceplate (converts to 6x RS-232 TX/RX by adapter)cPCI-6636(D): one RJ-45 RS-232/422/485, one RS-232 TX/RX to J3, one RS-232 TX/RX to J5</td></tr><tr><td>USB 3.0</td><td>cPCI-6636(D): three USB 3.0 ports on faceplatecPCI-6636DZ: eight USB 3.0 ports on faceplate</td></tr><tr><td>XMC</td><td>cPCI-6636D and cPCI-6636DZ: one XMC site</td></tr><tr><td>Audio</td><td>High definition audio routed to J3</td></tr><tr><td>Storage Interfaces $^{1}$ </td><td>One onboard 2.5&quot; SATA connector supporting SATA 6Gb/s drive on all models1-slot cPCI-6636 supports onboard CFast slotOne SATA 3Gb/s 7-pin connector onboard on all modelscPCI-6636(D): two SATA 3Gb/s channels routed to J3</td></tr><tr><td>BIOS</td><td>AMI UEFI BIOS, 128Mbit SPI flash memory</td></tr><tr><td>OS Compatibility</td><td>Microsoft Windows 7 64-bitMicrosoft Windows 10 64-bitUbuntu 16.10.64-bitFedora 22, 64-bitOther OS support upon request</td></tr></table>

Table 2-1: cPCI-6636 Series Specifications

<table><tr><td rowspan="3">Faceplate I/O</td><td>cPCI-6636 (4HP)3x 10/100/1000BASE-T Ethernet ports1x DVI-I port &amp; 1x DVI-D port3x USB 3.0 ports1x USB 2.0 port1x RJ-45 serial port supporting RS-232/422/485</td></tr><tr><td>cPCI-6636D (8HP)2x 10/100/1000BASE-T Ethernet ports1x DVI-I port3x USB 3.0 ports1x RJ-45 serial port supporting RS-232/422/4851x XMC slot</td></tr><tr><td>cPCI-6636DZ (8HP)2x 10/100/1000BASE-T Ethernet ports2x VGA ports8x USB 3.0 ports3x RJ-45 serial port supporting 6x RS-232 TX/RX1x XMC slot</td></tr><tr><td>Environmental</td><td>Operating Temperature (with forced air flow) $^{2}$ :Standard: -20°C to +60°CExtended: -20°C to +70°C with forced air flowStorage Temperature: -50°C to 100°CHumidity: 95% @60°C non-condensingShock: 20G peak-to-peak, 11ms duration, non-operatingVibration $^{1}$ : 2Grms, 5-500Hz, each axis, operating (w/o hard drive)</td></tr><tr><td>EMI</td><td>FCC Class ACE EN55032</td></tr></table>

Table 2-1: cPCI-6636 Series Specifications

1. The storage device limits the operational vibration tolerance. When the application requires higher specification for anti-vibration, it is recommended to use a flash storage device.
2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Sufficient forced air-flow is required. Temperature limits of optional mass storage devices may also affect the thermal specification.

# 2.2 Block Diagrams

# cPCI-6636 Series Processor Blade

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Main Blocks:**\n*   Skylake-H Core i7\n*   Skylake-H HM170\n*   Super IO\n\n**Connections for Skylake-H Core i7:**\n*   Connected to: DDR4-2133 soldered Up to 16GB\n*   Connected to: DDR4-2133 SODIMM Up to 16GB\n*   Connected to: J1/J2 via PCI 64B/66M -) PCIe to PCI bridge -) PCIe x 4\n*   Connected to: DMI Gen3 (8GT/s) -) Skylake-H HM170\n*   Connected to: DP -) NXP PTN3355 -) Front VGA (DZ)\n*   Connected to: DP -) NXP PTN3355 -) Front DVI-H (DZ: VGA) -) VGA -) J3\n*   Connected to: 1x DVI, PCIe x4 -) J5\n*   Connected to: J5 (via switch icon)\n\n**Connections for Skylake-H HM170:**\n*   Connected to: DMI Gen3 (8GT/s) -) Skylake-H Core i7\n*   Connected to: i PC -) Super IO\n*   Connected to: SPI -) BIOS\n*   Connected to: SMBus -) SEMA 3.0\n*   Connected to: SATA 0 -) 2.5' SATA drive\n*   Connected to: SATA 1 -) CFast\n*   Connected to: SATA 2 -) 7-pin SATA\n*   Connected to: SATA 3, GPIO x10 -) J5\n*   Connected to: SATA x2 -) J3\n*   Connected to: D/Z only -) XMC (via PCIe x8)\n*   Connected to: J3 -) HDA, 6x USB 2.0, 4x GPIO\n*   Connected to: PCIe x1 -) i219LM -) RJ-45 GbE (switchable to rear J5)\n*   Connected to: PCIe x1 -) i210IT -) RJ-45 GbE (switchable to rear J5)\n*   Connected to: PCIe x1 -) i210IT -) J3\n*   Connected to: PCIe x1 -) i210IT -) J3\n*   Connected to: USB 3.0 -) USB 3.0 -) USB 3.0\n*   Connected to: USB 3.0 -) USB 3.0 -) USB 3.0\n*   Connected to: USB 3.0 (dashed box DZ only) -) USB 3.0\n*   Connected to: PCIe x1 -) XHCL -) USB 3.0\n*   Connected to: PCIe x1 -) XHCL -) USB 3.0\n*   Connected to: PCIe x1 -) XHCL -) USB 3.0\n*   Connected to: PCIe x1 -) XHCL -) USB 3.0\n\n**Connections for Super IO:**\n*   Connected to: i PC -) Skylake-H HM170\n*   Connected to: J3 -) KB.MS, 2x COM RS-232\n*   Connected to: J5 -) 1x COM RS-232 (TX/RX)\n*   Connected to: 2x RS-232(TX, RX) -) RJ-45 COM DZ only\n*   Connected to: 2x RS-232(TX, RX) -) RJ-45 COM\n*   Connected to: 1x RS-232/422/485 -) RJ-45 COM](.cpci-6636-50m-15111-2000-03/2abe96836c0458d73e384a7e5592faa03bfa4955b5f14124261d511c0477acb0.jpg)

Figure 2-1: cPCI-6636 Series Functional Block Diagram

# 2.3 I/O Connectivity Table

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-6636(4HP)</td><td colspan="2">cPCI-6636D(8HP)</td><td colspan="2">cPCI-6636DZ(8HP)</td></tr><tr><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>Y x2</td><td></td><td>Y x2</td><td></td><td>Y x2</td><td></td></tr><tr><td>COM</td><td>Y x1(RJ-45)</td><td></td><td>Y x1(RJ-45)</td><td></td><td>Y x3(RJ-45)</td><td></td></tr><tr><td>USB 3.0</td><td>Y x3</td><td></td><td>Y x3</td><td></td><td>Y x8</td><td></td></tr><tr><td>DVI-I</td><td>Y x1</td><td></td><td>Y x1</td><td></td><td></td><td></td></tr><tr><td>VGA</td><td></td><td></td><td></td><td></td><td>Y x2</td><td></td></tr><tr><td>SATA</td><td></td><td>Y x2 (one for 2.5&quot; drive, one 7-pin SATA connector)</td><td></td><td>Y x2 (one for 2.5&quot; drive, one 7-pin SATA connector)</td><td></td><td>Y x2 (one for 2.5&quot; drive, one 7-pin SATA connector)</td></tr><tr><td>CFast</td><td></td><td>CFast</td><td></td><td></td><td></td><td></td></tr><tr><td>XMC</td><td></td><td></td><td></td><td>Y x1</td><td></td><td>Y x1</td></tr><tr><td>LEDs</td><td>Y x3</td><td></td><td>Y x3</td><td></td><td>Y x3</td><td></td></tr><tr><td>Reset Button</td><td>Y</td><td></td><td>Y</td><td></td><td>Y</td><td></td></tr></table>

Table 2-2: cPCI-6636(D/DZ) I/O Connectivity

# 2.4 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5V, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

# Power Consumption

Intel® Core i7™-6820EQ: BIOS EIST Enabled, cTDP Normal

<table><tr><td>OS/Mode</td><td>Current @ 3.3V</td><td>Current @ 5V</td><td>Total Power</td></tr><tr><td>Windows 10/Idle mode</td><td>1.66 A</td><td>1.1 A</td><td>10.97 W</td></tr><tr><td>Windows typical mode</td><td>1.74 A</td><td>11.94 A</td><td>65.44 W</td></tr><tr><td>Windows max mode</td><td>1.70 A</td><td>11.8 A</td><td>61.51W</td></tr></table>

Intel® Xeon® CPU E3-1505M v5: BIOS EIST Enabled, cTDP Normal

<table><tr><td>OS/Mode</td><td>Current @ 3.3V</td><td>Current @ 5V</td><td>Total Power</td></tr><tr><td>Windows 10/Idle mode</td><td>1.80 A</td><td>0.70 A</td><td>9.44 W</td></tr><tr><td>Windows typical mode</td><td>1.85 A</td><td>12.48 A</td><td>68.51 W</td></tr><tr><td>Windows max mode</td><td>1.85 A</td><td>10.83 A</td><td>60.26 W</td></tr></table>

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# 3 Functional Description

The following sections describe the cPCI-6636 Series features and functions.

# 3.1 Processors

The 6th Generation Intel® Core™ processor family is the state of art 64-bit, multi-core mobile processor built on 14 nanometer process technology. Based on the advanced microarchitecture, the processor is designed for a two-chip platform. The two-chip platform consists of a processor and platform controller hub (PCH). The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an integrated display engine, processor graphics and integrated memory controller.

<table><tr><td>Features</td><td>Xeon® E3-1505M v5</td><td>CoreTM i7-6820EQ</td><td>CoreTM i3-6100E</td></tr><tr><td>Clock Speed</td><td>2.8 GHz</td><td>2.8GHz</td><td>2.7 GHz</td></tr><tr><td>Max. Single Core Turbo Freq.</td><td>3.7 GHz</td><td>3.5GHz</td><td>NA</td></tr><tr><td>Last Level Cache</td><td>8MB Smart Cache</td><td>8MB Smart Cache</td><td>3MB Smart Cache</td></tr><tr><td>No. of Core/Thread</td><td>4/8</td><td>4/8</td><td>2/4</td></tr><tr><td>Maximum Power (TDP(1))</td><td>45W/35W by cTDP</td><td>45W</td><td>35W</td></tr><tr><td>DMI</td><td>8 GT/s DMI3</td><td>8 GT/s DMI3</td><td>8 GT/s DMI3</td></tr><tr><td> $T_{junction,MAX}^{(2)}$ </td><td>100°C</td><td>100°C</td><td>100°C</td></tr><tr><td>Socket Supported</td><td>FCBGA1440</td><td>FCBGA1440</td><td>FCBGA1440</td></tr><tr><td>Processor Graphics</td><td>Intel® HD Graphics P530</td><td>Intel® HD Graphics 530</td><td>Intel® HD Graphics 530</td></tr><tr><td>Graphics Base/Max Freq.</td><td>350 MHz / 1.05 GHz</td><td>350 MHz /1 GHz</td><td>350 MHz /950 MHz</td></tr><tr><td>Graphics Video Max Memory</td><td>1.7 GB</td><td>64 GB</td><td>64 GB</td></tr><tr><td>DirectX</td><td>12</td><td>12</td><td>12</td></tr><tr><td>OpenGL</td><td>4.4</td><td>4.5</td><td>4.5</td></tr></table>

(see notes on next page)

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.

2. The maximum supported operating temperature.

Supported Technologies

<table><tr><td>Feature</td><td>Xeon® E3-1505M v5</td><td>CoreTM i7-6820EQ</td><td>CoreTM i3-6100E</td></tr><tr><td>Intel® Turbo Boost Technology</td><td>2.0</td><td>2.0</td><td>No</td></tr><tr><td>Intel® vPro Technology</td><td>Yes</td><td>Yes</td><td>No</td></tr><tr><td>Intel® Hyper-Threading Technology</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Virtualization Technology (Intel® VT-x)</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Virtualization Technology for Directed I/O (Intel® VT-d)</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® VT-x with Extended Page Tables (EPT)</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® TSX-NI</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® 64 Architecture</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Instruction Set</td><td>64-bit</td><td>64-bit</td><td>64-bit</td></tr><tr><td>Instruction Set Extensions</td><td>Intel® SSE4.1, Intel® SSE4.2, Intel® AVX2</td><td>Intel® SSE4.1, Intel® SSE4.2, Intel® AVX2</td><td>Intel® SSE4.1, Intel® SSE4.2, Intel® AVX2</td></tr><tr><td>Enhanced Intel SpeedStep® Technology</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Thermal Monitoring Technologies</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel Flex Memory Technologies</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Identity Protection Technology</td><td>Yes</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Stable Image Platform Program (SIPP)</td><td>Yes</td><td></td><td></td></tr><tr><td>Intel® Smart Response Technology</td><td>Yes</td><td></td><td></td></tr></table>

# Interfaces

? Two channels of DDR4-2133 ECC memory(cPCI-6636(D) only, Core™ i7 SKUs do not support ECC)
 Memory DDR4 data transfer rates of 2133 MT/s
 64-bit wide channels
 DDR4 I/O Voltage of 1.2V
4Gb, and 8Gb DDR4 DRAM technologies are supported for x8 devices. Using 8Gb device technologies, the largest memory capacity possible is 16 GB
 The PCI Express port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0.
 8 GT/s point-to-point DMI interface to PCH is supported

# Graphics

The Intel® HD Graphics 530 for Core™ i7 and Core™ i3 and Intel® HD Graphics P530 for Xeon® E3-1505M v5 is integrated in the processor enabling substantial gains in performance and lower power consumption.

 DX12 support
 OpenGL 4.4/4.5, OpenCL 1.2 support
 Graphics Base Frequency: 3500 MHz
Graphics Max Dynamic Frequency: 1.05 GHz for Xeon® E3-1505M v5, Core™ i7 and 950MHz 1GHz for Core™ i37 and 950MHz for Core™ i3Celeron®
 Graphics Video Max Memory: Uup to 64GB
Supports Intel® InTru™ 3D Technology, Intel® Quick Sync Video, Intel® Clear Video HD Technology, Intel® Clear Video Technology

# 3.2 Chipset

The cPCI-6636(D) are equipped with Mobile Intel® CM236 Chipset and cPCI-6636DZ is equipped with Mobile Intel® HM170 Chipset. Functions and capabilities include:

<table><tr><td>Feature</td><td>Mobile Intel® CM236 Chipset</td><td>Mobile Intel® HM170 Chipset</td></tr><tr><td>Bus Speed</td><td>8 GT/s DMI3</td><td>8 GT/s DMI3</td></tr><tr><td>TDP</td><td>3.67 W</td><td>2.6 W</td></tr><tr><td># of DIMMs per channel</td><td>2</td><td>2</td></tr><tr><td>Intel® Clear Video Technology</td><td>Yes</td><td>Yes</td></tr><tr><td>PCI Support</td><td>No</td><td>No</td></tr><tr><td>PCI Express Revision</td><td>3.0</td><td>3.0</td></tr><tr><td>PCI Express Configurations</td><td>x1, x2, x4</td><td>x1, x2, x4</td></tr><tr><td>Max # of PCI Express Lanes</td><td>20</td><td>16</td></tr><tr><td>RAID Configuration</td><td>0/1/5/10</td><td>0/1/5/10</td></tr><tr><td>Intel® Virtualization Technology for Directed I/O (VT-d)</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® vProTM Technology</td><td>Yes</td><td>No</td></tr><tr><td>Intel® ME Firmware Version</td><td>11.0</td><td>11.0</td></tr><tr><td>Intel® HD Audio Technology</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Rapid Storage Technology</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Rapid Storage Technology enterprise</td><td>Yes</td><td>No</td></tr><tr><td>Intel® Smart Response Technology</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Stable Image Platform Program (SIPP)</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Smart Sound Technology</td><td>Yes</td><td>Yes</td></tr><tr><td>Intel® Trusted Execution Technology</td><td>Yes</td><td>No</td></tr></table>

# 3.3 XMC

The cPCI-6636D/DZ supports one PCIe x8 XMC site for front panel I/O expansion.

# 3.4 Intel® Turbo Boost Technology

Intel® Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and/or render clock frequency when there is sufficient power headroom, and the product is within specified temperature and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations. This improves the system responsiveness for short, bursty usage conditions.

Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

# 3.5 Intel® Hyper-Threading Technology

Intel® Hyper-Threading Technology allows an execution core to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support. Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7, and disabling Hyper-Threading Technology using the BIOS for all previous versions of Windows operating systems.

# 3.6 Battery

The cPCI-6636(D/DZ) is equipped with a 3.0V "coin cell" lithium battery for the real time clock (RTC). The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. A Rayovac BR2032 is equipped on board by default.

# 4 Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the cPCI-6636 Series.

4.1 cPCI-6636(D) Component Side Layout
![RJ1\nUSB1\nUSB3\nUSB5\nCOM1\nSO_DIMM1\nDVI1\nPCH1\nB2B_CONN1\nCF_CN1\nCPU1\nSATA2\nSATA1\nJ5\nJ3\nJ2\nJ1](.cpci-6636-50m-15111-2000-03/7a0ef2cea130f88ab054601a6931361eee88507cb7f8d8056cfff5dd73a55318.jpg)

<table><tr><td>CPU1</td><td>Intel® processor</td><td>PCH1</td><td>Intel® PCH</td></tr><tr><td>SO_DIMM1</td><td>Memory socket</td><td>J1/J2/J3/5</td><td>CompactPCI connectors</td></tr><tr><td>CF_CN1 (CPCI-6636)</td><td>CFast board-to-board connector</td><td>B2B_CONN1 (cPCI-6636D/DZ)</td><td>XMC board-to-board connector</td></tr><tr><td>SATA1</td><td>7-pin SATA connector</td><td>SATA2</td><td>SATA board-to-board connector</td></tr></table>

Figure 4-1: cPCI-6636(D) Component Side Layout

# 4.2 cPCI-6636D/DZ Assembly Layoutt

![SATA Drive\nAssembly\nDB-6636XMC\nXMC Adapter\nCPU Heatsink](.cpci-6636-50m-15111-2000-03/112a9784223bbe0ec69ebfad684012c3ca79fa38910a35b24b659537eeca3e76.jpg)

Figure 4-2: cPCI-6636D/DZ Assembly Layout

# 4.3 cPCI-6636(D/DZ) Faceplate I/O

cPCI-6636
![GbE x2\nUSB 3.0 x3\nSerial Port\nDVI-I\nReset\nButton\nPower LED\nHDD LED\nWDT LED](.cpci-6636-50m-15111-2000-03/407265bf791d10c058a6a422350b73589e7460c4d482c96beae3315ff00d5d4a.jpg)

cPCI-6636D
![GbE x2\nUSB 3.0 x3\nSerial Port\nXMC\nDVI-I\nReset Button\nPower LED\nHDD LED\nWDT LED](.cpci-6636-50m-15111-2000-03/936d4ce11218f4012545df6d767bf065d77cb19a0c11803408871a597931ae80.jpg)

cPCI-6636DZ

![USB 3.0 x8\nGbE x2\nXMC\nVGA\nReset Button\nPower LED\nSerial Port x3\nHDD LED\nWDT LED\nVGA](.cpci-6636-50m-15111-2000-03/36dda3c8d1c599e6ce03cdfd993bcf4cb1463596e6924ce342f800d8da50d65c.jpg)

Figure 4-3: cPCI-6636(D/DZ) Faceplate I/O

System LEDs

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="3">Power[6X24]</td><td rowspan="3">Green/Red</td><td>Off</td><td>System is off</td></tr><tr><td>Red</td><td>System Power ready (PWGD)</td></tr><tr><td>Green</td><td>Post OK</td></tr><tr><td rowspan="2">WDT[22 XC]</td><td rowspan="2">Orange</td><td>Off</td><td>No Watchdog event</td></tr><tr><td>Blinking</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">HDD[TYKW]</td><td rowspan="2">Yellow</td><td>Off</td><td>No CF/CFast/SATA HDD activity</td></tr><tr><td>Blinking</td><td>Data read/write in process for CFast/SATA drive</td></tr></table>

Table 4-1: cPCI-6636(D) Front Panel System LED Descriptions

# 4.4 Connector Pin Assignments

LAN1/2 RJ-45 GbE Connectors

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_TX0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_TX0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_TX1+</td></tr><tr><td>4</td><td>—</td><td>LAN_TX2+</td></tr><tr><td>5</td><td>—</td><td>LAN_TX2-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_TX1-</td></tr><tr><td>7</td><td>—</td><td>LAN_TX3+</td></tr><tr><td>8</td><td>—</td><td>LAN_TX3-</td></tr></table>

Table 4-2: LAN1/2 RJ-45 GbE Pin Definitions

![Speed\nActivity\n8\n1](.cpci-6636-50m-15111-2000-03/9b02d69b8088d71683ab5d7962c10fe53a73901746485c083718832e077a4e8b.jpg)

<table><tr><td colspan="2">Status</td><td>Speed LED (Green/Amber)</td><td>Activity LED (Yellow)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Amber</td><td>ON</td></tr><tr><td>Active</td><td>Amber</td><td>Blinking</td></tr></table>

Table 4-3: LAN LED Status Definitions

# USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>VCC</td></tr><tr><td>2</td><td>Data-</td></tr><tr><td>3</td><td>Data+</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX_N</td></tr><tr><td>6</td><td>RX_P</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>TX_N</td></tr><tr><td>9</td><td>TX_P</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.cpci-6636-50m-15111-2000-03/2e95f3cad4a6321c892ebb98ed895eaf4f28c5026202b80ac902a16ce669156e.jpg)

Table 4-4: USB 3.0 Pin Definitions

# cPCI-6636(D) COM1 (RJ-45)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>TX-</td><td>Data-</td></tr><tr><td>2</td><td>RTS#</td><td>—</td><td>—</td></tr><tr><td>3</td><td>DSR#</td><td>—</td><td>—</td></tr><tr><td>4</td><td>TXD</td><td>RX+</td><td>—</td></tr><tr><td>5</td><td>RXD</td><td>TX+</td><td>Data+</td></tr><tr><td>6</td><td>GND</td><td>—</td><td>—</td></tr><tr><td>7</td><td>CTS#</td><td>—</td><td>—</td></tr><tr><td>8</td><td>DTR#L</td><td>RX-</td><td>—</td></tr></table>

![The image shows a schematic diagram of a grey connector, resembling an RJ45 jack, centered within a square outline. Two black lines point to the bottom corners of the grey connector shape. Below the left pointing line is the number '8,' and below the right pointing line is the number '1.'](.cpci-6636-50m-15111-2000-03/1019d385964d6c832502dc63fb4e4eae65b592f58663d3837326d176b7181a20.jpg)
Table 4-5: cPCI-6636(D) COM Pin Definitions

# cPCI-6636(D) COM RJ-45 to DB-9 Cable

(P/N: 30-01020-0200)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>TX-</td><td>Data-</td></tr><tr><td>2</td><td>RXD</td><td>TX+</td><td>Data+</td></tr><tr><td>3</td><td>TXD</td><td>RX+</td><td>—</td></tr><tr><td>4</td><td>DTR#L</td><td>RX-</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>—</td><td>—</td></tr><tr><td>6</td><td>DSR#</td><td>—</td><td>—</td></tr><tr><td>7</td><td>RTS#</td><td>—</td><td>—</td></tr><tr><td>8</td><td>CTS#</td><td>—</td><td>—</td></tr><tr><td>9</td><td>—</td><td>—</td><td>—</td></tr></table>

![6\n1\n5](.cpci-6636-50m-15111-2000-03/3cc53f8066287512e450cd46d5f183b1aa95d0af2552edce279c206d7fe519eb.jpg)

Table 4-6: cPCI-6636(D) COM RJ-45 to DB-9 Cable Pin Definitions

# cPCI-6636DZ COM1-6 (RJ-45)

The three RJ-45 ports on the cPCI-6636DZ carry two sets of RX/ TX signals each. From right to left: COM1/2, COM3/4 and COM5/6.

COM1/2

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>P5V</td></tr><tr><td>2</td><td>COM1_RX</td></tr><tr><td>3</td><td>COM1_TX</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>P5V</td></tr><tr><td>6</td><td>COM2_RX</td></tr><tr><td>7</td><td>COM2_TX</td></tr><tr><td>8</td><td>GND</td></tr></table>

![The image displays a square outline with rounded corners containing a gray-shaded icon resembling a camera. Two black lines extend from the bottom corners of the camera icon downwards. The line on the left is labeled with the number '8' and the line on the right is labeled with the number '1'.](.cpci-6636-50m-15111-2000-03/08e6248c647f46d559b2058212e28dc70f4f0f2864dcbd99131e75db64668436.jpg)
Table 4-7: cPCI-6636DZ COM1/2 Pin Definitions

# COM3/4

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>P5V</td></tr><tr><td>2</td><td>COM3_RX</td></tr><tr><td>3</td><td>COM3_TX</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>P5V</td></tr><tr><td>6</td><td>COM4_RX</td></tr><tr><td>7</td><td>COM4_TX</td></tr><tr><td>8</td><td>GND</td></tr></table>

![The image displays a schematic diagram of an RJ45 network jack enclosed within a square border. Inside the border is a grey-filled shape representing the connector housing. Two thin black lines extend from the bottom corners of the inner shape downwards. Below the left line is the number '8', and below the right line is the number '1'.](.cpci-6636-50m-15111-2000-03/6b50fb0dd2944433886a3241e8b32750bce7dfa0fa00c571c6c3dd3fd1ae0ae9.jpg)
Table 4-8: cPCI-6636DZ COM3/4 Pin Definitions

# COM5/6

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>P5V</td></tr><tr><td>2</td><td>COM3_RX</td></tr><tr><td>3</td><td>COM3_TX</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>P5V</td></tr><tr><td>6</td><td>COM4_RX</td></tr><tr><td>7</td><td>COM4_TX</td></tr><tr><td>8</td><td>GND</td></tr></table>

![The image displays a square outline containing a central grey shape that resembles a rectangular block with a smaller, raised rectangular section on top. Two lines extend downward from the bottom corners of this grey shape. Below the left line is the number '8', and below the right line is the number '1'.](.cpci-6636-50m-15111-2000-03/8ee02f0411c485c898beccd359029e74d0e5b208fe436545ac4f2d557cf9e82b.jpg)
Table 4-9: cPCI-6636DZ COM5/6 Pin Definitions

# cPCI-6636DZ COM RJ-45 to 2x DB-9 Cable

(P/N: 30-25044-1020)

![Diagram of a USB connector showing two connected modules (no text or symbols)](.cpci-6636-50m-15111-2000-03/39e117b1d76f45d52e75f9ba694e498c9255ae593e92778e08f256717c602077.jpg)

The DB-9 connectors are labeled $" 0 1 "$ and $" 0 2 "$ . Connector $^ { \mathfrak { w } } 0 1 ^ { \mathfrak { n } }$ corresponds to the odd numbered COM signal on the RJ-45 connector, and connector “02” corresponds to the even numbered COM signal $( { \mathsf { i . e . } } \ { } ^ { * } { \mathsf { a } } ^ { \prime \prime } = { } ^ { * } { \mathsf { o d d } } ^ { \prime \prime } , \ { } ^ { * } { \mathsf { b } } ^ { \prime \prime } = { } ^ { * } { \mathsf { e v e n } } ^ { \prime \prime } )$ .

<table><tr><td>Pin #</td><td>DB-9 “01”</td><td>DB-9 “02”</td></tr><tr><td>1</td><td>-</td><td>-</td></tr><tr><td>2</td><td>COMa_RX</td><td>COMb_RX</td></tr><tr><td>3</td><td>COMa_TX</td><td>COMb_TX</td></tr><tr><td>4</td><td>-</td><td>-</td></tr><tr><td>5</td><td>GNDa</td><td>GNDb</td></tr><tr><td>6</td><td>-</td><td>-</td></tr><tr><td>7</td><td>-</td><td>-</td></tr><tr><td>8</td><td>-</td><td>-</td></tr><tr><td>9</td><td>-</td><td>-</td></tr></table>

![6\n1\n5](.cpci-6636-50m-15111-2000-03/cd396ce1aae91e13d658f01f0fc629a7ca4cac65a0676e34a0bea7fa2c9fda5f.jpg)

Table 4-10: cPCI-6636DZ COM RJ-45 to 2x DB-9 Cable Pin Definitions

# DVI-I Connector

![Front view of a D-sub connector with pinout diagram (no text or symbols)](.cpci-6636-50m-15111-2000-03/69fa65692945a8af111609ad4e63870756bb399a434d44c389aad71dddce6fc1.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2-</td><td>16</td><td>Hot Plug Detect</td></tr><tr><td>2</td><td>TMDS Data2+</td><td>17</td><td>TMDS Data0-</td></tr><tr><td>3</td><td>GND</td><td>18</td><td>TMDSData0+</td></tr><tr><td>4</td><td>NC</td><td>19</td><td>GND</td></tr><tr><td>5</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>6</td><td>DDC Clock [SCL]</td><td>21</td><td>NC</td></tr><tr><td>7</td><td>DDC Data [SDA]</td><td>22</td><td>GND</td></tr><tr><td>8</td><td>Analog vertical sync</td><td>23</td><td>TMDS Clock +</td></tr><tr><td>9</td><td>TMDS Data1-</td><td>24</td><td>TMDS Clock -</td></tr><tr><td>10</td><td>TMDS Data1+</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>GND</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>NC</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>NC</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 4-11: DVI-I Connector Pin Definition

Serial ATA 7-pin Connector (SATA1)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX+</td></tr><tr><td>3</td><td>TX-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX-</td></tr><tr><td>6</td><td>RX+</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n7](.cpci-6636-50m-15111-2000-03/6e9c01f64d0014475bb074ad0aa37fb2ca1757c0907385fbad59abbf2aa73ca3.jpg)

Table 4-12: Serial ATA 7-pin Connector Pin Definition

# Serial ATA Connector with Power

2.5” SATA adapter board (P/N: 59-37571-0000)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>NC</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>NC</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>NC</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-6636-50m-15111-2000-03/df29b2e220bd6698cc874bf6d612a563cda2fe86b30d9e9e2b9a7864d616b3ca.jpg)

Table 4-13: Serial ATA Connector with power Pin Definition

# CFast Socket

DB-CFast adapter board (P/N: 59-37572-0000)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>Ground</td><td>S1</td></tr><tr><td>SATA_TX-P</td><td>S2</td></tr><tr><td>SATA_TX-N</td><td>S3</td></tr><tr><td>Ground</td><td>S4</td></tr><tr><td>SATA_RX-N</td><td>S5</td></tr><tr><td>SATA_RX-P</td><td>S6</td></tr><tr><td>Ground</td><td>S7</td></tr><tr><td>CFast_CDI</td><td>P1</td></tr><tr><td>Ground</td><td>P2</td></tr><tr><td>NC</td><td>P3</td></tr><tr><td>NC</td><td>P4</td></tr><tr><td>NC</td><td>P5</td></tr><tr><td>NC</td><td>P6</td></tr><tr><td>Ground</td><td>P7</td></tr><tr><td>CFast_LED1</td><td>P8</td></tr><tr><td>CFast_LED2</td><td>P9</td></tr><tr><td>NC</td><td>P10</td></tr><tr><td>NC</td><td>P11</td></tr><tr><td>NC</td><td>P12</td></tr><tr><td>+3.3V</td><td>P13</td></tr><tr><td>+3.3V</td><td>P14</td></tr><tr><td>Ground</td><td>P15</td></tr><tr><td>Ground</td><td>P16</td></tr><tr><td>CFast_CDO</td><td>P17</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.cpci-6636-50m-15111-2000-03/c76372594a66a34984237d3efff67ae712a06e263aa9925d307b09fc8d68b587.jpg)

![24\nP1\nS1](.cpci-6636-50m-15111-2000-03/ebdb115c418238aef283a5101ad8d4aa9637287f2a6e685105a7ce3cbdf07a89.jpg)

Table 4-14: CFast Socket Pin Definition

# XMC Connector on Daughter Board

cPCI-6636D/DZ only.

![F1\nA1\nF19\nA19](.cpci-6636-50m-15111-2000-03/c179004a9e7cf30e6db333908e2e26af7185dfe5cc72e79c8aabcfae4527d084.jpg)

<table><tr><td>Pin#</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>RXP</td><td>RXN</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>PCIE_RST-L</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>5</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>+12V</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>-12V</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>TXP</td><td>TXN</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>13</td><td>NC</td><td>NC</td><td>3.3V</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>15</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>17</td><td>NC</td><td>NC</td><td>Not used</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>Not used</td><td>GND</td><td>GND</td><td>Not used</td></tr><tr><td>19</td><td>CK-P</td><td>CK-N</td><td>Not used</td><td>Not used</td><td>Not used</td><td>Not used</td></tr></table>

Table 4-15: XMC Connector Pin Definition

CompactPCI J1 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>P5V</td><td>CPCI_REQ64-L</td><td>CPCI_ENUM-L</td><td>P3V3</td><td>P5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>CPCI_AD1</td><td>P5V</td><td>CPCI_VIO_STB</td><td>AD0</td><td>CPCI_ACK64-L</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>P3V3</td><td>CPCI_AD4</td><td>CPCI_AD3</td><td>P5V</td><td>CPCI_AD2</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>CPCI_AD7</td><td>GND</td><td>P3V3</td><td>CPCI_AD6</td><td>CPCI_AD5</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>P3V3</td><td>CPCI_AD9</td><td>CPCI_AD8</td><td>CPCI_M66EN</td><td>CPCI_CBE-L0</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_AD12</td><td>GND</td><td>CPCI_VIO_STB</td><td>CPCI_AD11</td><td>CPCI_AD10</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>P3V3</td><td>CPCI_AD15</td><td>CPCI_AD14</td><td>GND</td><td>CPCI_AD13</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>CPCI_SERR-L</td><td>GND</td><td>P3V3</td><td>CPCI_PAR</td><td>CPCI_CBE-L1</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>P3V3</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td><td>CPCI_PERR-L</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>CPCI_DEVSEL-L</td><td>GND</td><td>CPCI_VIO_STB</td><td>CPCI_STOP-L</td><td>CPCI_LOCK-L</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>P3V3</td><td>CPCI_FRAME-L</td><td>CPCI_IRDY-L</td><td>CPCI_BDSEL-L</td><td>CPCI_TRDY-L</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key Area</td></tr><tr><td>11</td><td>GND</td><td>CPCI_AD18</td><td>CPCI_AD17</td><td>CPCI_AD16</td><td>GND</td><td>CPCI_CBE-L2</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>CPCI_AD21</td><td>GND</td><td>P3V3</td><td>CPCI_AD20</td><td>CPCI_AD19</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CPCI_CBE-L3</td><td>CPCI_IDSEL</td><td>CPCI_AD23</td><td>GND</td><td>CPCI_AD22</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>CPCI_AD26</td><td>GND</td><td>CPCI_VIO_STB</td><td>CPCI_AD25</td><td>CPCI_AD24</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CPCI_AD30</td><td>CPCI_AD29</td><td>CPCI_AD28</td><td>GND</td><td>CPCI_AD27</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CPCI_REQ-L0</td><td>CPCI_PRESENT-L</td><td>P3V3</td><td>CPCI_CLK0</td><td>CPCI_AD31</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_RET-L</td><td>GND</td><td>CPCI_GNT-L0</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>P5V_IPMB</td><td>CPCI_HEALTHY-L</td><td>CPCI_VIO_STB</td><td>CPCI_INTP</td><td>CPCI_INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_INTA-L</td><td>CPCI_INTB-L</td><td>CPCI_INTC-L</td><td>P5V</td><td>CPCI_INTD-L</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>P5V</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>P5V</td><td>N12V</td><td>NC</td><td>P12V</td><td>P5V</td><td>GND</td></tr></table>

Table 4-16: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CPCI_CLK6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_CLK5</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>IPMB_DAT</td><td>IPMB_CLK</td><td>IPMB_PWR</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>GND</td><td>J2_RST-L</td><td>CPCI_REQ-L6</td><td>CPCI_GNT-L6</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_DEG-L</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_FAL-L</td><td>CPCI_REQ-L5</td><td>CPCI_GNT-L5</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>CPCI_AD35</td><td>CPCI_AD34</td><td>CPCI_AD33</td><td>GND</td><td>CPCI_AD32</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>CPCI_AD38</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD37</td><td>CPCI_AD36</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>CPCI_AD42</td><td>CPCI_AD41</td><td>CPCI_AD40</td><td>GND</td><td>CPCI_AD39</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>CPCI_AD45</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD44</td><td>CPCI_AD43</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>CPCI_AD49</td><td>CPCI_AD48</td><td>CPCI_AD47</td><td>GND</td><td>CPCI_AD46</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CPCI_AD52</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD51</td><td>CPCI_AD50</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>CPCI_AD56</td><td>CPCI_AD55</td><td>CPCI_AD54</td><td>GND</td><td>CPCI_AD53</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CPCI_AD59</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD58</td><td>CPCI_AD57</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CPCI_AD63</td><td>CPCI_AD62</td><td>CPCI_AD61</td><td>GND</td><td>CPCI_AD60</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>CPCI_CBE-L5</td><td>CPCI_DEV64-L</td><td>CPCI_VIO</td><td>CPCI_CBE-L4</td><td>CPCI_PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>CPCI_CBE-L7</td><td>GND</td><td>CPCI_CBE-L6</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_CLK4</td><td>GND</td><td>CPCI_GNT-L3</td><td>CPCI_REQ-L4</td><td>CPCI_GNT-L4</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CPCI_CLK2</td><td>CPCI_CLK3</td><td>SYSEN-L</td><td>CPCI_GNT-L2</td><td>CPCI_REQ-L3</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CPCI_CLK1</td><td>GND</td><td>CPCI_REQ-L1</td><td>CPCI_GNT-L1</td><td>CPCI_REQ-L2</td><td>GND</td></tr></table>

Table 4-17: CompactPCI J2 Connector Pin Definition

CompactPCI J3 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>19</td><td>GND</td><td>P5V</td><td>P5V</td><td>P12V</td><td>P5V</td><td>P5V</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LAN4_MDI0_P</td><td>LAN4_MDI0_N</td><td>GND</td><td>LAN4_MDI2_P</td><td>LAN4_MDI2_N</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LAN4_MDI1_P</td><td>LAN4_MDI1_N</td><td>GND</td><td>LAN4_MDI3_P</td><td>LAN4_MDI3_N</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>LAN3_MDI0_P</td><td>LAN3_MDI0_N</td><td>GND</td><td>LAN3_MDI2_P</td><td>LAN3_MDI2_N</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>LAN3_MDI1_P</td><td>LAN3_MDI1_N</td><td>GND</td><td>LAN3_MDI3_P</td><td>LAN3_MDI3_N</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>USB_OC5-L</td><td>USB_OC6-L</td><td>USB_OC7-L</td><td>USB_OC8-L</td><td>USB_OC9-L</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>USB8-P</td><td>USB8-N</td><td>GND</td><td>USB9-P</td><td>USB9-N</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>USB6-P</td><td>USB6-N</td><td>GND</td><td>USB7-P</td><td>USB7-N</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>USB4-P</td><td>USB4-N</td><td>GND</td><td>USB5-P</td><td>USB5-N</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>USB_OC4-L</td><td>CRT_CLK</td><td>CRT_DAT</td><td>CRT_HSYNC</td><td>CRT_VSYNC</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>COM3_CTS-L</td><td>COM3_RI-L</td><td>CRT_BLUE</td><td>CRT_RED</td><td>CRT_GREEN</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>COM3_RXD</td><td>COM3_TXD</td><td>COM3_DTR-L</td><td>COM3_DSR-L</td><td>COM3_RTS-L</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>COM4_TX</td><td>COM4_RX</td><td>COM3_DCD-L</td><td>GPIO</td><td>GPIO</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>SATA1_RXPC</td><td>SATA1_RXNC</td><td>GND</td><td>SATA0_RXPC</td><td>SATA0_RXNC</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>SATA1_TXPC</td><td>SATA1_TXNC</td><td>GND</td><td>SATA0_TXPC</td><td>SATA0_TXNC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>KBDATA</td><td>KBCLK</td><td>GPIO2</td><td>MSDATA</td><td>MSCLK</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>A_HDA_SDIN1</td><td>AUD_SDIN2</td><td>NC</td><td>AUD_DOCK_EN-L</td><td>AUD_DOCK_RST-L</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>A_HDA_RST-L</td><td>A_HDA_SYNC</td><td>A_HDA_BIT_CLK</td><td>A_HDA_SDOUT</td><td>A_HDA_SDIN0</td><td>GND</td></tr><tr><td></td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Table 4-18: CompactPCI J3 Connector Pin Definition

CompactPCI J5 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>LAN2_MDI_P0</td><td>LAN2_MDI_N0</td><td>GND</td><td>LAN2_MDI_P2</td><td>LAN2_MDI_N2</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>LAN2_MDI_P1</td><td>LAN2_MDI_N1</td><td>GND</td><td>LAN2_MDI_P3</td><td>LAN2_MDI_N3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>LAN1_MDI_P0</td><td>LAN1_MDI_N0</td><td>GND</td><td>LAN1_MDI_P2</td><td>LAN1_MDI_N2</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>LAN1_MDI_P1</td><td>LAN1_MDI_N1</td><td>GND</td><td>LAN1_MDI_P3</td><td>LAN1_MDI_N3</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>DVID_CLKP</td><td>DVID_CLKN</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>DVID_TXP1</td><td>DVID_TXN1</td><td>GND</td><td>COM2_TX</td><td>COM2_RX</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DVID_SDA</td><td>DVID_SCL</td><td>DVID_HPD</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>DVID_TXP2</td><td>DVID_TXN2</td><td>GND</td><td>SATA_RX3_P_C</td><td>SATA_RX3_N_C</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>DVID_TXP0</td><td>DVID_TXN0</td><td>GND</td><td>SATA-TX3_P_C</td><td>SATA-TX3_N_C</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>LAN3_LED_100-L</td><td>LAN4_LED_100-L</td><td>REAR_GPIO6</td><td>LAN4_LED_1000-L</td><td>LAN3_LED_1000-L</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>DVI_SDA_RTM</td><td>DVI_SCL_RTM</td><td>DVI_HPD_RTM</td><td>RTM_HDD_LED</td><td>RTM_WDT_LED</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>DVIB_TX2_P_C</td><td>DVIB_TX2_N_C</td><td>GND</td><td>DVIB_CLK_P_C</td><td>DVIB_CLK_N_C</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>DVIB_TX0_P_C</td><td>DVIB_TX0_N_C</td><td>GND</td><td>DVIB_TX1_P_C</td><td>DVIB_TX1_N_C</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>REAR_GPIO1</td><td>REAR_GPIO2</td><td>REAR_GPIO3</td><td>REAR_GPIO4</td><td>REAR_GPIO5</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>LAN3_ACT-L</td><td>REAR_GPIO7</td><td>LAN4_ACT-L</td><td>REAR_GPIO8</td><td>REAR_GPIO9</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>GND</td><td>GND</td><td>BAT_RTM</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CLK_REAR-P</td><td>CLK_REAR-N</td><td>GND</td><td>PLTRST_REAR-L</td><td>GPIO</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>PCIE_TX8-P</td><td>PCIE_TX8-N</td><td>GND</td><td>PCIE_RX8-P</td><td>PCIE_RX8-N</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PCIE_TX7-P</td><td>PCIE_TX7-N</td><td>GND</td><td>PCIE_RX7-P</td><td>PCIE_RX7-N</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PCIE_TX6-P</td><td>PCIE_TX6-N</td><td>GND</td><td>PCIE_RX6-P</td><td>PCIE_RX6-N</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PCIE_TX5-P</td><td>PCIE_TX5-N</td><td>GND</td><td>PCIE_RX5-P</td><td>PCIE_RX5-N</td><td>GND</td></tr><tr><td></td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Table 4-19: CompactPCI J5 Connector Pin Definition

![The image displays an icon of a white document with a folded top-right corner. Horizontal lines are visible on the paper, and a large red checkmark is superimposed over the center. There is no text present.](.cpci-6636-50m-15111-2000-03/f1c5f6dfcfa301c731d1a7cdfbae0def629546bf2bc41511a27147af4dba7301.jpg)
NOTE:

GPIO signals to J5 are from the PCH. Contact ADLINK for information on how to control these GPIO.

# 4.5 Switches and Buttons

![SW3\nSW1\nSW2](.cpci-6636-50m-15111-2000-03/800712bf982daa7fe0e044c16b2736d4f379790bbbf3747f41fd5de8ab436a06.jpg)

Figure 4-4: cPCI-6636 Series Switch Locations - Component Side

![SW5\nSW4\nSW6](.cpci-6636-50m-15111-2000-03/3921615d9971fb76e58aa5daca4091c9b8b581c7244358af4b92e878635e30bd.jpg)

Figure 4-5: cPCI-6636 Series Switch Locations - Solder Side

# VGA Signal Front/Rear Switch (SW1 Pin 1, Reserved)

VGA functionality is controlled by BIOS.

# BIOS Protection Switch (SW1 Pin 2)

Enabling BIOS protection prevents changes to be made to the BIOS settings (disabled by default).

![ON\n1 2](.cpci-6636-50m-15111-2000-03/e7a72680e8b9c3b537e1b584c0ae4c34a11f6b59faabe69dfc00147c5b719541.jpg)

<table><tr><td>SW1 Pin</td><td>ON</td><td>OFF</td></tr><tr><td>1</td><td>Reserved</td><td>Reserved (default)</td></tr><tr><td>2</td><td>BIOS Protection Disabled (default)</td><td>BIOS Protection Enabled</td></tr></table>

# Debug Switch (SW2, Reserved)

The default setting for SW2 is 1 OFF, 2 OFF. Do not change the settings unless instructed by ADLINK.

![ON\n1 2](.cpci-6636-50m-15111-2000-03/23970fd7404f024a93a9e2d286bd5031d65b54a2b4477c14e7d0cbf08f09c2b7.jpg)

# LAN (RJ1) Front/Rear Switch (SW3, Reserved)

Default all OFF.

![ON\n1 2](.cpci-6636-50m-15111-2000-03/d2c60b78a3d73771d17bbb6bd70cd373245fb542cdd8c0dd0068c2d5fc9ddfbc.jpg)

# COM1 Mode Switch (SW4)

cPCI-6636(D) only.

<table><tr><td>Pin</td><td>Function</td></tr><tr><td>1 OFF, 2 ON (default)</td><td>RS-232</td></tr><tr><td>1 ON, 2 OFF</td><td>RS-485</td></tr><tr><td>1 ON, 2 ON</td><td>RS-422</td></tr><tr><td>3</td><td>OFF (Reserved)</td></tr><tr><td>4</td><td>OFF (Reserved)</td></tr></table>

![ON\n1 2 3 4](.cpci-6636-50m-15111-2000-03/688210405953a8649f0933fb9ab3fc3acb200a5bbf73a42692e6296d09b6da86.jpg)

# System Reset Button (SW5)

Press switch SW5 to reset the system.

![Simple diagram showing a black rectangle with a red arrow pointing to it, no text or symbols present.](.cpci-6636-50m-15111-2000-03/b31daea139015d3bda0bb5530d50736a1f68e37602c5fcdc7d3d025ff7925774.jpg)

# Force Ejector Handle Closed Switch (SW6)

Switch SW6 allows the ejector handle state to be forced "closed" so that blades without ejector handles (e.g. conduction cooled) will power on when inserted into the chassis.

<table><tr><td>Pin</td><td>ON</td><td>OFF</td></tr><tr><td>1</td><td>Force the ejector handle state to &quot;closed&quot; (default)</td><td>On/Off state is controlled by the ejector handle</td></tr><tr><td>2</td><td>NC</td><td>NC (default)</td></tr></table>

![ON\n1 2](.cpci-6636-50m-15111-2000-03/2741d91cbe50471a2cc1f9592c768596fad3a93e70e80444f230465ff0b19ed1.jpg)

![The image displays a white document icon with faint gray horizontal lines running across it. A large, bold red checkmark is superimposed over the document, running diagonally from the bottom left to the top right. The document is slightly tilted to the left.](.cpci-6636-50m-15111-2000-03/6d10d72bc6083169207750b0fe65be5e1eaac94077c7dc4626e233a143438c5e.jpg)
NOTE:

When the On/Off state is controlled by the ejector handle (Pin 1 OFF), make sure to properly shut down the OS before opening the handle. If the ejector handle is opened while the OS is operating, power will be cut immediately, resulting in possible system corruption and data loss.

# 5 Getting Started

This chapter describes the following installation procedures for the cPCI-6636(D):

 CFast card (cPCI-6636 only)
 2.5” SATA drive
 XMC module

# 5.1 CPU and Heatsink

The cPCI-6636 Series come with CPU and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance.

# 5.2 CFast Card Installation

The cPCI-6636 provides space to install a CFast card or a Compact-Flash card (optional). Follow the instructions below to install a CFast to the cPCI-6636(D/DZ).

1. A CFast card can be installed in the location marked below.

![Interior view of an electronic circuit board with visible components and a close-up of a green circuit board (no readable text or symbols)](.cpci-6636-50m-15111-2000-03/4858f65f94a356d432b270c2e1bbe71f7ce69c8c50df2941b742bf0e925d66d8.jpg)

2. Insert the CFast card into the slot on the DB-CFast daughter board.

![CFast 3SE\nP/N: DECFA-32GDSSWBQB\nBCA1160107000029\n32GB\nMade in Taiwan\nRoHS](.cpci-6636-50m-15111-2000-03/26b26a22f7a9fa67e86fcb00e3a425c7d464d4398b4b8e91ec5d568f16e32f39.jpg)

3. Turn the DB-CFast daughter board assembly over and place it on top of retention bracket with the holes aligned as shown. Secure the bracket with two of the six screws included in the kit (M2.5, L4 P/N: 33-01007-0040).

![CFast 3SE\nPAN: DECFA32G0085VB2B\nBCA1160137022002B\n32GB\nMade in Taiwan\nHCC 2.0ns](.cpci-6636-50m-15111-2000-03/c326cc51af33f94623af3462e94a904864cf07e5fca1f25a0649fbd23cd68231.jpg)

![Green printed circuit board with three circular annotations highlighting specific components (no text or symbols present)](.cpci-6636-50m-15111-2000-03/b865af28c48c29f8f891fc56380b1101da7222679dcdb97cb8791dbef10313b2.jpg)

4. Install the CFast daughter board assembly to the cPCI-6636 main board by pressing it onto the board-to-board connector in the location shown below. Secure it with the remaining 4 screws (M2.5, L4, P/N: 33-01007-0040).

![Interior view of an electronic circuit board with green components and red circular annotations highlighting specific areas (no readable text or symbols)](.cpci-6636-50m-15111-2000-03/98ee33ed4495a745dd893c5c59684e531f053521e29e9e09237bde71f5374c4a.jpg)

# 5.3 2.5" SATA Drive Installation

The cPCI-6636(D/DZ) provides space to install a $_ { 2 . 5 " }$ SATA drive.

1. A 2.5” SATA drive can be installed on the cPCI-6636(D/DZ) in the location shown below. The items in the $2 . 5 '$ SATA drive accessory pack are shown on the left.

![Overhead view of an electronic circuit board with components and connectors, no visible text or symbols](.cpci-6636-50m-15111-2000-03/9758f4897756dd417ac332a674d5760b16ce511d940d986fc145cadd1dfdc3c2.jpg)

2. Secure the $2 . 5 "$ SATA drive to the drive bracket by fastening two screws on each side of the bracket as indicated below (M3 L4, P/N: 33-03104-0040).

![Close-up of a gloved hand holding a metal mechanical component with two red-circled holes, next to a small electronic component (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/40f36f806ed9a3eb47b84f14d355de7fcf7af835c37673b8f47c4e605c912e95.jpg)

3. Attach the SATA adapter board to the connectors on the SATA drive.

![Exterior view of a ADLINK TECHNOLOGY INC SATA SSD device with visible circuit board and soldered components (no text or symbols on the main body)](.cpci-6636-50m-15111-2000-03/3ce048c1fb10cedc3952248ac70befbb12ac3c6782e96fc5f73fcee1bebd8f7b.jpg)

4. Install the SATA drive bracket assembly onto the cPCI-6630(D/DZ) by pressing it onto the board-to-board connector in the location shown below. Fasten two screws as circled as below (M2.5 L6, round head, P/N: 33-01200-0060).

![Top-down view of an electronic circuit board with visible components and connectors (no readable text or symbols)](.cpci-6636-50m-15111-2000-03/77e19a3f65772856c1860316fcaf2a73ec8b88e00867194403a69cb2a11ee176.jpg)

5. Turn the board over and finish securing the SATA drive bracket assembly by fastening the remaining two screws (M2.5 L6, round head, P/N: 33-01200-0060) as shown below.

![Top-down view of a green printed circuit board with visible traces and components, no readable text or symbols present.](.cpci-6636-50m-15111-2000-03/9743e0a9f8905fe8c9534a67b50ec041196f62b73c1a93fc4e88341da601c5bd.jpg)

# 5.4 XMC Installation (cPCI-6636D/DZ only)

The cPCI-6636D/DZ provides space to install one XMC module. Follow the steps below to install an XMC module.

1. An XMC module can be installed on the cPCI-6636D/DZ in the location indicated below.

![Internal view of a computer motherboard with heat sinks and a highlighted green PCB component (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/430c995c51b4c69953b1d6856cd7234b3b330e55fffc95a327f0394bbe771894.jpg)

2. Remove the XMC filler plate and the screws securing two brackets to the front panel as shown below.

![Close-up of a server rack with two Ethernet ports and two labeled connectors, showing internal network topology (no readable text or symbols)](.cpci-6636-50m-15111-2000-03/2217cb012c653e630f517d17e331a7a61e8c86ef53d61d759081568804034650.jpg)

![Close-up of a network device rear panel showing Ethernet ports, I/O ports, and a metal rack with connectors (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/a4ebb843f9fdf1a43b1f437c9092196d234cbc5814fc22b797c6a06cb3511d94.jpg)

3. Secure the two brackets removed in Step 2 above to the XMC card as shown below.

![Green printed circuit board with various electronic components and connectors, no visible text or symbols](.cpci-6636-50m-15111-2000-03/12e75f404301272d3ab847593293dc5593af2a4cefa177b08fe196cd782e5d59.jpg)

![MAC1 000106 004D2A\nMAC3 000106 004D2B\nMAC5 000106 004D2C\nMAC4 000106 004D2D\nMAC10 000106 004D2E\nMAC13 000106 004D2F\nMAC14 000106 004D2G\nMAC15 000106 004D2H\nMAC16 000106 004D2I\nMAC17 000106 004D2J\nMAC18 000106 004D2K\nMAC19 000106 004D2L\nMAC20 000106 004D2M\nMAC21 000106 004D2N\nMAC22 000106 004D2O\nMAC23 000106 004D2P\nMAC24 000106 004D2Q\nMAC25 000106 004D2R\nMAC26 000106 004D2S\nMAC27 000106 004D2T\nMAC28 000106 004D2U\nMAC29 000106 004D2V\nMAC30 000106 004D2W\nMAC31 000106 004D2X\nMAC32 000106 004D2Y\nMAC33 000106 004D2Z\nMAC34 000106 004D2A\nMAC35 000106 004D2B\nMAC36 000106 004D2C\nMAC37 000106 004D2D\nMAC38 000106 004D2E\nMAC39 000106 004D2F\nMAC40 000106 004D2G\nMAC41 000106 004D2H\nMAC42 000106 004D2I\nMAC43 000106 004D2J\nMAC44 000106 004D2K\nMAC45 000106 004D2L\nMAC46 000106 004D2M\nMAC47 5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5x5.5:ETHERNET](.cpci-6636-50m-15111-2000-03/b937022c88b0568226e841ea6a8f5bdb6cbf503016ac53efa50d12efe00f5c43.jpg)

4. Align the connector on the XMC card with the connector on the XMC daughter board, press down firmly, and secure it with two screws as indicated below.

![Internal view of an electronic device showing a green circuit board, cooling fans, and a power strip (no visible text or symbols)](.cpci-6636-50m-15111-2000-03/cca5d4f958d9c181c27726e922aae0c7505d8c529dfdb2f66c688c18d22193ec.jpg)

![DATA 51-37571.04\nXTL628000000000000000000000000000000000000000000000000000000000000000000000000000000\nXDLINK\nTECHNOLOGY INC\nTXMC655-19R-C1\nV1.0 D\nCE\n95684-5\nLINK\nSSD\nOxy Inc](.cpci-6636-50m-15111-2000-03/9f1e16c764477e5f06a2528862304cdf1986f1dfc25d33634be86de22712a821.jpg)

5. Fasten the two screws removed in Step 2 above to the front panel to complete securing the XMC card to the cPCI-6636D/DZ. Set aside the XMC filler plate so it can be replaced if the XMC card is uninstalled.

![TXMCBB5\nPORT1\nPORT2\nPORT3\nPORT4\nEthernet\n1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80\n100\n101\n102\n103\n104\n105\n106\n107\n108\n109\n110\n111\n112\n113\n114\n115\n116\n117\n118\n119\n120\n121\n122\n123\n124\n125\n126\n127\n128\n129\n130\n131\n132\n133\n134\n135\n136\n137\n138\n139\n140\n141\n142\n143\n144\n145\n146\n147\n148\n149\n150\n151\n152\n153\n154\n155\n156\n157\n158\n159\n160\n161\n162\n163\n164\n165\n166\n167\n168\n169\n170\n171\n172\n173\n174\n175\n176\n177\n178\n179\n180](.cpci-6636-50m-15111-2000-03/b296ffc781236c18cd1e91bc6f1f35776e584de64e0500dceb7fadcd0012de3f.jpg)

# 5.5 Installing the cPCI-6636(D/DZ) to the Chassis

The 8HP cPCI-6636DZ only supports operation in host slots, whereas the cPCI-6636 and cPCI-6636D can operate independently in both host and peripheral slots without CompactPCI bus communication (satellite mode). These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.
2. Remove the blank face cover from the selected slot, if necessary.
3. Press down on the release catches of the cPCI-6636 ejector handles.
4. Remove the black plastic caps securing the mounting screws to the front panel.
5. Align the module’s top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board’s connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.
6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module front panel.
7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

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# 6 Driver Installation

The cPCI-6636 drivers can be downloaded from the ADLINK website (http://www.adlinktech.com). ADLINK provides validated drivers for Windows 7 and Windows 10. We recommend using these drivers to ensure compatibility. VxWorks BSP and QNX BSP can also be downloaded from the cPCI-6636 product page on the ADLINK website.

# 6.1 cPCI-6636 Drivers

The driver installation procedure for Windows 10 is described below. Note that since Intel does not support EHCI on the 6th generation Intel® Core™ platform (formerly "Skylake"), it is recommended to use a PS/2 KB/MS to install the Windows OS.

1. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.
2. Install the chipset driver by extracting and running the program in ...\Intel\_Chipset\_Win10x64\_v10.1.1.38\_public.zip.
3. Install the graphics driver and utilities by extracting and running the program in ...\Intel\_Graphics\_Win10x64\_ v23.20.16.5018.zip.
4. Install the LAN drivers by extracting and running the program in …\Intel\_Chipset\_Win10x64\_v23.1.zip.
5. Install the Intel Rapid Storage Technology Utility by extracting and running the program in …\Intel\_RST\_Win10x64\_ v15.2.0.1020.zip.
6. Install the Intel® Management Engine Interface driver for Intel® AMT support by extracting and running the program in …\Intel\_ME\_Win10x64\_11.8.50.3425.zip.
7. Install the audio driver and utilities by extracting and running the program in …\Realtek\_Audio\_Win10x64\_v.R279.zip.

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# 7 Utilities

# 7.1 Watchdog Timer

This section describes the operation of the cPCI-6636’s watch dog timer (WDT). The primary function of the WDT is to monitor the cPCI-6636 operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

 enabling and disabling
 reloading timeout value

The cPCI-6636 custom WDT circuit is implemented using the internal IO of the ITE Super I/O IT8786 which is at 2Eh of LPC. The basic functions of the WDT include:

 Starting the timer countdown.
 Enabling or disabling WDT.
 Enable or disable WDT countdown LED ON.
 Reloading the timeout value to keep the watch dog from timing out.
 Setting the range of the timeout period from 1 to 15300 seconds.
 Sending a RESET signal to system when the watch dog times out

# Using the Watchdog in an Application

The following section describes the WDT functions in an application. These can be controlled through the registers in the cPCI-6636 Super I/O.

An application using the reset feature enables the watchdog function, sets the count-down period, and reloads the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after its counter reaches zero.

Sample Code
```c
#include &lt;stdio.h&gt;
#include &lt;stdlib.h&gt;

typedefunsigned charBYTE;

void EnterConfig()
{
    outportb(SIO_CONFIG_INDEX, 0x87);
    outportb(SIO_CONFIG_INDEX, 0x01);
    outportb(SIO_CONFIG_INDEX, 0x55);
    outportb(SIO_CONFIG_INDEX, 0x55);
}

void ExitConfig()
{
    outportb(SIO_CONFIG_INDEX, 0x02);
    outportb(SIO_CONFIG_DATA, 0x02);
}

void LDNSelection(BYTE LDN)
{
    outportb(SIO_CONFIG_INDEX, 0x07);
    outportb(SIO_CONFIG_DATA, LDN);
}

void SIOBasicIORead(
    BYTE LDN,
    BYTE Register,
    BYTE *Data)
{
    LDNSelection(LDN);
    outportb(SIO_CONFIG_INDEX, Register);
    *Data = inportb(SIO_CONFIG_DATA);
}

void SIOBasicIOWrite(
    BYTE LDN,
    BYTE Register,
    BYTE Data)
{
```

```c
LDNSelection(LDN);
outportb(SIO_CONFIG_INDEX, Register);
outportb(SIO_CONFIG_DATA, Data);
}

BOOL StringToByte(char *string, BYTE *value)
{
    BYTE i, temp;
    *value = 0;
    for(i=0; string[i]!=NULL; ++i) {
    if(i>1) { printf("Digital count error!\n");
    return 0; }
    *value &lt;&lt;= 4;
    temp = toupper(string[i]);
    if(temp &gt;= '0' && temp &lt;= '9')
    *value += temp - '0';
    else if(temp &gt;= 'A' && temp &lt;= 'F')
    *value += temp - 'A' + 0x0a;
    else {
    printf("Input char[%c] is illegal!\n", string[i]);
    return 0;
    }
    }
    return1;
}

BOOL StringToWORD_Dec(char *string, WORD *value)
{
    BYTE i;
    WORD temp;

    *value = 0;
    for(i=0; string[i]!=NULL; ++i) {
    if(i&gt;4) { printf("Digital count error!\n");
    return 0; }
    *value *= 10;
    temp = toupper(string[i]);
    if(temp >= '0' && temp &lt;= '9')
    *value += temp - '0';
    else {
```

```c
printf("Input char[%c] is illegal!\n", string[i]);
return 0;
}
if(temp &gt; 65535) {
    printf("Input number is large than 65535!\n");
}
return1;
int IT8786_WatchDog(int argc, char *argv[])
{
BYTE bTemp, bUnit;
WORD wWdtimer;

printf("ADLINK WatchDog DOS Utility [Version 1.00]\n\n");
if((argc != 3) && strcmp(argv[1], "/?")) {
    printf("Invalid command, please type /? to get the details.\n");
    return 0;
}
if(!strcmp(argv[1], "/?")) {
    printf("WatchDog [argument1][argument2]\n\n");
    printf("argument1 :\n");
    printf(" 1 - Second\n");
    printf(" 0 - Minute\n");
    printf("argument2 :\n");
    printf(" Time-out value\n\n");
    printf("Example below for 10 seconds.\n");
    printf(" WatchDog 1 10\n");
    printf("Example below for 3 minutes.\n");
    printf(" WatchDog 0 3\n");
    return 0;
}

StringToByte(argv[1], &bUnit);
if((bUnit != 0) && (bUnit != 1)) {
```

```c
printf("Argument1 is a invalid number[%d].\n", bUnit);
return 1;
}

StringToWORD_Dec(argv[2], &wWdtimer);

EnterConfig();

// Implement Watch Dog
SIOBasicIORead(0x07, 0x29, &bTemp);
bTemp &= ~BIT6; // default function = KRST
SIOBasicIOWrite(0x07, 0x29, bTemp);

// Config settings
if(bUnit) {
    bTemp = 0xd0; // second
} else {
    bTemp = 0x50; // minute
}
SIOBasicIOWrite(0x07, 0x72, bTemp);

// Set timer value
SIOBasicIOWrite(0x07, 0x74,
(BYTE)(wWdtimer>>8));
SIOBasicIOWrite(0x07, 0x73, (BYTE)wWdtimer);

// Program led blinking
SIOBasicIORead(0x07, 0x25, &bTemp);
bTemp |= BIT2;
SIOBasicIOWrite(0x07, 0x25, bTemp);

SIOBasicIOWrite(0x07, 0xF8, 0x0A);

ExitConfig();

return 0;
}
```

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# 8 BIOS Setup Utility

The following chapter describes basic navigation for the AMI EFI BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt: &lt; Press DEL to run Setup &gt;
3. After you press the &lt; Delete &gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![The image displays an icon of a white document with a folded upper corner and faint horizontal lines, featuring a large red checkmark on the right side.](.cpci-6636-50m-15111-2000-03/519c07c0b6c84012a1493387a8cc2767f31291844ae581562c462651815817c7.jpg)
NOTE:

In most cases, the &lt; Delete &gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt; F1 &gt;, &lt; F2 &gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![The flowchart begins at the top with a box labeled **'BIOS Setup Utility'**. An arrow points downward to the text **'Screens'**.\n\nBelow this, a horizontal sequence of boxes reads: **'Screen 1'** (-) **'Screen 2'** (-) **'Screen 3'** (-) **'Screen 4'** (-) **'Screen 5'** (connected by double-headed arrows). To the left, a box labeled **'Left and Right Keys to Select a Setup Screen'** has a dotted arrow pointing to **'Screen 1'**.\n\nAn arrow points downward from **'Screen 3'** to the text **'Items'**.\n\nFrom **'Items'**, an arrow points downward to a section labeled **'Fields'** on the far left. This section consists of two rows of boxes:\n*   The top row contains three boxes with the symbol **'±'**, connected by double-headed arrows.\n    *   A box labeled **'Tab Key to Select Fields'** has a dotted arrow pointing to the first box in this row.\n    *   A box labeled **'± To Change Field Values'** has a dotted arrow pointing to the third box in this row.\n*   Below this row are vertical arrows (one pointing down, one pointing up). A box labeled **'Up and Down Keys to Select a Setup Item'** has a dotted arrow pointing to these vertical arrows.\n*   The bottom row contains three boxes with the symbol **'±'**, connected by double-headed arrows.](.cpci-6636-50m-15111-2000-03/b55f3e49bcb4af2df3090203ecc4b543594caa72755a8f9017a8fe92fc3506ce.jpg)

![The image displays a white document icon with a curled top-right corner. A large, bold red checkmark is centered on the page. Faint horizontal lines run across the document.](.cpci-6636-50m-15111-2000-03/3c274ad3dcffb2cfdd437e1e514e703870cfecc171119d9964a96781359f6ba4.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

→← Left/Right. The Left and Right &lt; Arrow &gt; keys allow you to select a setup screen. For example: Main screen, Advanced screen, Chipset screen, and so on.
↑↓ Up/Down The Up and Down &lt; Arrow &gt; keys allow you to select a setup item or sub-screen.
+- Plus/Minus The Plus and Minus &lt; Arrow &gt; keys allow you to change the field value of a particular setup item. For example: Date and Time.
Tab The &lt; Tab &gt; key allows you to select setup fields.
ESC The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. Press the &lt; Enter &gt; key to discard changes and exit. You can also use the &lt; Arrow &gt; key to select Cancel and then press the &lt; Enter &gt; key to abort this function and return to the previous screen.

# 8.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main BIOS Setup menu is shown below.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>- BIOS Information- Processor Information- PCH Information- SPI Clock Frequency- System ▶ Management- System Date- System Time</td><td>- *Trusted ▶ Computing- AMT ▶ Configuration- PCH-FW ▶ Configuration- IT8786 ▶ Super IO Configuration- Serial Port Console Redirection- CPU ▶ Configuration- SATA ▶ Configuration- Network Stack Configuration▶- CSM ▶ Configuration- USB ▶ Configuration</td><td>- System ▶ Agent (SA) Configuration- PCH-IO ▶ Configuration</td><td>- Administrator Password- User Password</td><td>- Boot Configuration- Boot Option Priorities- Driver Option Priorites</td><td>- Save ▶ Options- Default ▶ Options- Boot ▶ Override</td></tr></table>

![The image displays a white document icon with a folded upper-right corner. Horizontal lines suggest text on the page. Superimposed over the document is a large, bold red checkmark.](.cpci-6636-50m-15111-2000-03/6959e29730bcf245b2ac6158dc23dd987fa60559ad2b2dd77a64de2d97644e79.jpg)
NOTE:

► indicates a submenu Gray text indicates info only

# 8.2.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BISO Vendor</td><td>Info only</td><td>BIOS vendor</td></tr><tr><td>Core Version</td><td>Info only</td><td>Vendor BIOS version</td></tr><tr><td>Compliancy</td><td>Info only</td><td>Compliance with UEFI specification</td></tr><tr><td>Project Name</td><td>Info only</td><td>ADLINK product name</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>ADLINK BIOS version.</td></tr><tr><td>Build Date and Time</td><td>Info only</td><td>Date the BIOS was built</td></tr><tr><td>Access Level</td><td>Info only</td><td>User access level</td></tr></table>

# 8.2.2 Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Display CPU Brand Name.</td></tr><tr><td>Brand String</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>Frequency</td><td>Info only</td><td>Display CPU Frequency.</td></tr><tr><td>Processor ID</td><td>Info only</td><td>Display CPU ID.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display CPU Stepping.</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Display number of Processors.</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision.</td></tr><tr><td>GT Info</td><td>Info only</td><td>Display GT info of Intel Graphics.</td></tr><tr><td>IGFX VBIOS Version</td><td>Info only</td><td>Display VBIOS Version.</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display Memory RC Version.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr></table>

# 8.2.3 PCH Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH Name</td><td>Info only</td><td>Display PCH name.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH SKU.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display PCH stepping.</td></tr><tr><td>LAN PHY Revision</td><td>Info only</td><td>Displays LAN PHY Revision.</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display version of ME.</td></tr><tr><td>ME Firmware SKU</td><td>Info only</td><td>Display ME Firmware Kit SKU number.</td></tr><tr><td>System Management</td><td>Submenu</td><td></td></tr></table>

# 8.2.4 SPI Clock Frequency

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>DOFR Support</td><td>Info only</td><td>Display DOFR support status</td></tr><tr><td>Read Status Clock Frequency</td><td>Info only</td><td>Displays the Read Status Clock Frequency.</td></tr><tr><td>Write Status Clock Frequency</td><td>Info only</td><td>Displays the Write Status Clock Frequency.</td></tr><tr><td>Fast Read Status Clock Frequency</td><td>Info only</td><td>Displays the Fast Read Clock Frequency.</td></tr></table>

# 8.2.5 System Management

PCH Information System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info only</td><td></td></tr><tr><td>Version</td><td>Info only</td><td>Display version.</td></tr></table>

Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>SEMA Firmware</td><td>Read only</td><td>Display SEMA Firmware.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SEMA firmware build date.</td></tr><tr><td>SEMA Boot loader</td><td>Read only</td><td>Display SEMA boot loader.</td></tr><tr><td>Build Date</td><td>Read only</td><td>Display SEMA boot loader build date.</td></tr><tr><td>Hardware Version</td><td>Read only</td><td>Display SEMA hardware Version.</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SEMA serial Number.</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SEMA manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SEMA last repair date.</td></tr><tr><td>MAC ID</td><td>Read only</td><td>Display SEMA MAC ID</td></tr></table>

Temperatures and Fan Speed

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures and Fan</td><td colspan="2">Info only</td></tr><tr><td>CPU Temperature</td><td colspan="2">Info only</td></tr><tr><td>Current</td><td>Read only</td><td>Display CPU current temperature.</td></tr><tr><td>Startup</td><td>Read only</td><td>Display CPU startup temperature.</td></tr><tr><td>Min</td><td>Read only</td><td>Display CPU min temperature.</td></tr><tr><td>Max</td><td>Read only</td><td>Display CPU max temperature.</td></tr><tr><td>Board Temperatures</td><td>Info only</td><td></td></tr><tr><td>Current</td><td>Read only</td><td>Display board current temperature.</td></tr><tr><td>Startup</td><td>Read only</td><td>Display board startup temperature.</td></tr><tr><td>Min</td><td>Read only</td><td>Display board min temperature.</td></tr><tr><td>Max</td><td>Read only</td><td>Display board max temperature.</td></tr></table>

Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td colspan="2">Info only</td></tr><tr><td>Current Input Current</td><td>Read only</td><td>Display input current.</td></tr><tr><td>Current Input Second Current</td><td>Read only</td><td>Display input second current.</td></tr><tr><td>Current Input Power</td><td>Read only</td><td>Display input power.</td></tr><tr><td>VCC_CORE</td><td>Read only</td><td>Display actual voltage of the VCC_CORE.</td></tr><tr><td>VCC_GT</td><td>Read only</td><td>Display actual voltage of the VCC_GT.</td></tr><tr><td>1V0_A</td><td>Read only</td><td>Display actual voltage of the 1V0_A.</td></tr><tr><td>VDDQ</td><td>Read only</td><td>Display actual voltage of the VDDQ.</td></tr><tr><td>VRTC</td><td>Read only</td><td>Display actual voltage of the VRTC.</td></tr><tr><td>V3P3S</td><td>Read only</td><td>Display actual voltage of the V3P3S.</td></tr><tr><td>V3P3A</td><td>Read only</td><td>Display actual voltage of the V3P3A.</td></tr><tr><td>V5_S</td><td>Read only</td><td>Display actual voltage of the V5_S.</td></tr><tr><td>VCCST</td><td>Read only</td><td>Display actual voltage of the VCCST</td></tr><tr><td>0V95_VCCIO</td><td>Read only</td><td>Display actual voltage of the 0V95_VCCIO</td></tr><tr><td>1V0_VCCSTG</td><td>Read only</td><td>Display actual voltage of the 1V0_VCCSTG</td></tr><tr><td>VCCSA</td><td>Read only</td><td>Display actual voltage of the VCCSA</td></tr><tr><td>V5VSB</td><td>Read only</td><td>Display actual voltage of the V5VSB</td></tr><tr><td>V12</td><td>Read only</td><td>Display actual voltage of the V12</td></tr></table>

Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Runtime Statistics</td><td colspan="2">Info only</td></tr><tr><td>Total Runtime</td><td>Read only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Read only</td><td>The returned value specifies the time in seconds the system is running in S0 state.This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Read only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Read only</td><td>The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Read only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Flags</td><td colspan="2">Info only</td></tr><tr><td>BMC Flags</td><td>Read only</td><td></td></tr><tr><td>BIOS Select</td><td>Read only</td><td>Display the selection of current BIOS ROM.</td></tr><tr><td>ATX/AT-Mode</td><td>Read only</td><td>Display ATX/AT-Mode.</td></tr><tr><td>Exception Code</td><td>Read only</td><td>System exception reason.</td></tr></table>

Power Up

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Up</td><td colspan="2">Info only</td></tr><tr><td>Power Up watchdog Attention: F12 disables the Power Up Watchdog.</td><td>Enabled Disabled</td><td>The Power-Up Watchdog resets the system after a certain amount of time after power-up.</td></tr></table>

# 8.2.6 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday,MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr></table>

# 8.3 Advanced

This menu contains the settings for most of the user interfaces in the system.

8.3.1 Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>EnabledDisabled</td><td>Enables or Disables BIOS support for security device. When disabled OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available</td></tr><tr><td>Active PCR banks</td><td colspan="2">Info only</td></tr><tr><td>Available PCR banks</td><td colspan="2">Info only</td></tr><tr><td>SHA-1 PCR Bank</td><td>EnabledDisabled</td><td>Enable or Disable SHA-1 PCR Bank</td></tr><tr><td>SHA256 PCR Bank</td><td>EnabledDisabled</td><td>Enable or Disable SHA256 PCR Bank</td></tr><tr><td>Pending operation</td><td>NoneTPM Clear</td><td>Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Platform Hierarchy</td><td>EnabledDisabled</td><td>Enable or Disable Platform Hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>EnabledDisabled</td><td>Enable or Disable Storage Hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>EnabledDisabled</td><td>Enable or Disable Endorsement Hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2TCG_2</td><td>Select the TCG2 Spec VersionSupport,\n\r\rTCG_1_2: the Compatible mode for Win8/Win10,\n\r\nrTCG_2: Support new TCG2 protocol and event format for Win10 or later</td></tr><tr><td>Physical Presence Spec Version</td><td>1.21.3</td><td>Select to Tell O.S. to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.</td></tr><tr><td>TPM 20 InterfaceType</td><td>TIS</td><td>Select the Communication Interface to TPM 20 Device.</td></tr><tr><td>Device Select</td><td>AutoTPM 1.2TPM 2.0</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated</td></tr></table>

Note: This feature is not supported by cPCI-6636DZ.

8.3.2 AMT Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel AMT</td><td>EnabledDisabled</td><td>Enable/Disable Intel(R) Active Management Technology BIOS Extension.Note: iAMT H/W is always enabled.This option controls the BIOS extension execution.If enabled, additional firmware is required in the SPI device.</td></tr></table>

# 8.3.3 PCH-FW Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display version of ME.</td></tr><tr><td>ME Firmware Mode</td><td>Info only</td><td>Display ME Firmware mode status.</td></tr><tr><td>ME Firmware Type</td><td>Info only</td><td>Display ME Firmware type.</td></tr><tr><td>ME Firmware SKU</td><td>Info only</td><td>Display ME Firmware Kit SKU number.</td></tr><tr><td>PTT Capability / State</td><td>Info only</td><td>Display PTT Capability and State.</td></tr><tr><td>NFC Support</td><td>Info only</td><td>Display NFC Support status.</td></tr></table>

# 8.3.4 IT8786 Super IO Configuration

Note: \* These items are only supported by cPCI-6636DZ.

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Chip</td><td colspan="2">Info only</td></tr><tr><td>Serial Port 1ConfigurationSerial PortDevice SettingsChange Settings $^{1}$ </td><td>EnabledDisabledIO=3F8h;IRQ=4AutoIO=3F8h;IRQ=4IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 2ConfigurationSerial PortDevice SettingsChange Settings $^{1}$ </td><td>EnabledDisabledIO=2F8h;IRQ=3AutoIO=2F8h;IRQ=3IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7.10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 3 Configuration Serial PortDevice SettingsChange Settings $^{1}$ </td><td>EnabledDisabledIO=3E8h; IRQ=5AutoIO=3E8h; IRQ=5IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12IO=2F0h; IRQ=3,4,5,6,7,10,11,12IO=2E0h; IRQ=3,4,5,6,7,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 4 Configuration Serial PortDevice SettingsChange Settings $^{1}$ </td><td>EnabledDisabledIO=2E8h; IRQ=7AutoIO=2E8h; IRQ=7IO=3E8h; IRQ=3,4,5,6,7,10,11,12IO=2E8h; IRQ=3,4,5,6,7,10,11,12IO=2F0h; IRQ=3,4,5,6,7,10,11,12IO=2E0h; IRQ=3,4,5,6,7.10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>* Serial Port 5 Configuration Serial PortDevice Settings</td><td>EnabledDisabledIO=2E0h; IRQ=6</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.</td></tr><tr><td>* Serial Port 6 Configuration Serial PortDevice Settings</td><td>EnabledDisabledIO=2E8h; IRQ=7</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.</td></tr></table>

# 8.3.5 Serial Port Console

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port Console</td><td colspan="2">Info only</td></tr><tr><td>COM1</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM2</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM3</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM4</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM5*</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM6*</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

Note: \* These items are only supported by cPCI-6636DZ.

Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Select Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>Select Parity.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Select number of stop bits.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Select flow control.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Legacy OS Redirection</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS Post</td><td>Always EnabledBootLoader</td><td>The settings specify if BootLoader is selected than Legacy console redirection is disabled before booting to Legacy OS. Default value is Always Enable which means Legaacy console Redirection is enabled for Legacy OS.</td></tr></table>

Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td rowspan="6">Legacy Serial Redirection Port</td><td>COM1</td><td rowspan="6">Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages.</td></tr><tr><td>COM2</td></tr><tr><td>COM3</td></tr><tr><td>COM4</td></tr><tr><td>*COM5</td></tr><tr><td>*COM6</td></tr></table>

Note: \* These items are only supported by cPCI-6636DZ.

Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Out-of-Band Mgmt Port</td><td>COM1COM2COM3*COM4*COM5*COM6</td><td>Microsoft Windows Emergency Management Services (EMS) allows for remote management of a Windows Server OS through a serial port.</td></tr><tr><td>Terminal</td><td>VT100VT100+VT-UTF8ANSI</td><td></td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTSSoftware Xon/Xoff</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a &#x27;stop&#x27; signal can be sent to stop the data flow. Once the buffers are empty, a &#x27;start&#x27; signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>Data Bits</td><td>Info only</td><td></td></tr><tr><td>Parity</td><td>Info only</td><td></td></tr><tr><td>Stop Bits</td><td>Info only</td><td></td></tr></table>

Note: \* These items are only supported by cPCI-6636DZ.

8.3.6 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU</td><td>Info only</td><td>Manufacturer, model, speed</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>Microcode Patch</td><td>Info only</td><td>Display Microcode Patch.</td></tr><tr><td>Max CPU Speed</td><td>Info only</td><td>Display CPU Max Speed.</td></tr><tr><td>Min CPU Speed</td><td>Info only</td><td>Display CPU Min Speed.</td></tr><tr><td>CPU Speed</td><td>Info only</td><td>Display CPU Speed.</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Display Number of cores</td></tr><tr><td>Hyper Threading Technology</td><td>Info only</td><td>Display Hyper Threading Technology</td></tr><tr><td>Intel VT-X Technology</td><td>Info only</td><td>Display Intel VT-X Technology support or not.</td></tr><tr><td>Intel SMX Technology</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>64-bit</td><td>Info only</td><td>Display 64-bit support or not.</td></tr><tr><td>EIST Technology</td><td>Info only</td><td>Display EIST Technology support or not.</td></tr><tr><td>CPU C3 state</td><td>Info only</td><td>Display CPU C3 state support or not.</td></tr><tr><td>CPU C8 state</td><td>Info only</td><td>Display CPU C8 state support or not.</td></tr><tr><td>CPU C7 state</td><td>Info only</td><td>Display CPU C7 state support or not.</td></tr><tr><td>CPU C8 state</td><td>Info only</td><td>Display CPU C8 state support or not.</td></tr><tr><td>CPU C9 state</td><td>Info only</td><td>Display CPU C9 state support or not.</td></tr><tr><td>CPU C10 state</td><td>Info only</td><td>Display CPU C10 state support or not.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>Hyper-threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.</td></tr><tr><td>Active Processor Cores</td><td>All 1</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Intel Virtualization Technology</td><td>Disabled Enabled</td><td>Enable/Disable support for the Intel virtualization technology.</td></tr><tr><td>Intel(R) SpeedStep(TM)</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable/Disable turbo mode.</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal Down Disabled</td><td>Configure TDP Mode as Nominal/Down/Disabled. Disabled option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>CPU C states</td><td>Disabled Enabled</td><td>Enable or disable CPU C states</td></tr></table>

8.3.7 SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enable/Disable SATA Device.</td></tr><tr><td>SATA Mode Selection</td><td>AHCIRAID</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>Serial ATA Port 0</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 0</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>Serial ATA Port 1</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 1</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>Serial ATA Port 2</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 2</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>Serial ATA Port 3</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 3</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>*Serial ATA Port 4</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 4</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr><tr><td>*Serial ATA Port 5</td><td>Info only</td><td></td></tr><tr><td>Software Preserve</td><td>Info only</td><td></td></tr><tr><td>Port 5</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port.</td></tr></table>

Note: \* These items are not supported by cPCI-6636DZ.

Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RAID0</td><td>EnabledDisabled</td><td>Enable or disable RAID0 feature.</td></tr><tr><td>RAID1</td><td>EnabledDisabled</td><td>Enable or disable RAID1 feature.</td></tr><tr><td>RAID10</td><td>EnabledDisabled</td><td>Enable or disable RAID10 feature.</td></tr><tr><td>RAID5</td><td>EnabledDisabled</td><td>Enable or disable RAID5 feature.</td></tr><tr><td>Intel Rapid Recovery Technology</td><td>EnabledDisabled</td><td>Enable or disable Intel Rapid Recovery Technology.</td></tr><tr><td>OROM UI and BANNER</td><td>EnabledDisabled</td><td>If enable, then the OROM UI is shown. Otherwise, no OROM banner or information will be displayed if all disks and RAID volumes are Normal.</td></tr><tr><td>HDD Unlock</td><td>EnabledDisabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>EnabledDisabled</td><td>If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.</td></tr><tr><td>IRRT Only on eSATA</td><td>EnabledDisabled</td><td>If enabled, then only IRRT volumes can span internal and eSATA drives. If disabled, then any RAID volume can span internal and eSATA drives.</td></tr><tr><td>Smart Response Technology</td><td>EnabledDisabled</td><td>Enable or disable Smart Response Technology.</td></tr><tr><td>OROM UI Normal Delay</td><td>2 Seconds4 Seconds6 Seconds8 Seconds</td><td>Select the delay time of the OROM UI Splash Screen in a normal status.</td></tr><tr><td>RST Force Form</td><td>EnabledDisabled</td><td>Enable/Disable Form for Intel Rapid Storage Technology.</td></tr></table>

8.3.8 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>*Network Stack</td><td>EnabledDisabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>Ipv4 PXE Support</td><td>EnabledDisabled</td><td>Enable lpv4 PXE Boot Support. If disabled IPV4 PXE boot option will not be created&quot;</td></tr><tr><td>Ipv6 PXE Support</td><td>EnabledDisabled</td><td>Enable lpv6 PXE Boot Support. If disabled IPV6 PXE boot option will not be created&quot;</td></tr><tr><td>PXE boot wait time</td><td>Info only</td><td>Wait time to press ESC key to abort the PXE boot</td></tr><tr><td>Media detect count</td><td>Info only</td><td>Number of times presence of media will be checked</td></tr></table>

Note: \* These items are not supported by cPCI-6636DZ.

8.3.9 CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>EnabledDisable</td><td>This option controls if CSM will be launched.</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td>Display CSM16 Module version.</td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>Upon Request: GA20 can be disabled using BIOS services. ALWAYS: do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>Option ROM Messages</td><td>Force BIOSKeep Current</td><td>Set display mode for Option ROM.</td></tr><tr><td>INT19 Trap Response</td><td>ImmediatePostponed</td><td>BIOS reaction on INT19 trapping by Option ROM</td></tr><tr><td>Boot Option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls what devices system can to boot.</td></tr><tr><td>Option ROM execution</td><td>Info only</td><td></td></tr><tr><td>Network</td><td>Do not launchLegacy onlyUEFI only</td><td>Controls the execution of UEFI and Legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFI onlyLegacy</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFI onlyLegacy</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI devices</td><td>Do not launchUEFILegacy</td><td>For PCI devices other than Network, Mass storage or Video defines which OpROM to launch.</td></tr></table>

8.3.10 USB

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module Version</td><td>Info only</td><td></td></tr><tr><td>USB Controllers</td><td>Info only</td><td></td></tr><tr><td>USB Devices</td><td>Info only</td><td>X Drive, X Keyboards, X Mouse, X Hubs</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications and setup.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI OS driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>EnabledDisabled</td><td>Enable/Disable USB Mass Storage Driver Support.</td></tr></table>

# 8.4 Chipset

System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent Bridge Name</td><td colspan="2">Info only</td></tr><tr><td>SA PCIe Code Version</td><td colspan="2">Info only</td></tr><tr><td>VT-d</td><td>Info only</td><td>Check VT-d function support status.</td></tr><tr><td>VT-d</td><td>EnabledDisabled</td><td>VT-d capability</td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td></td></tr><tr><td>PEG Port Configuration</td><td>Submenu</td><td></td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td></td></tr></table>

Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info only</td><td></td></tr><tr><td>IGFX VBIOS Version</td><td>Info only</td><td>Display VBIOS Version.</td></tr><tr><td> $^*$  VGA Channel Switch  $^{1}$ </td><td>RearFront</td><td>Change VGA channel to front or rear.</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIE</td><td>Select which of IGFX/PEG/PCIE Graphics device should be Primary Display or select SG for Switchable Gfx.</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnable</td><td>Keep IGD enabled based on the setup options.</td></tr></table>

Note: \* These items are not supported by cPCI-6636DZ.

PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG Port Configuration</td><td>Info only</td><td></td></tr><tr><td>PEG 0:1:0</td><td>Info only</td><td>Display PEG root port present status.</td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Change VGA channel to front or rear.</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:0 Max speed.</td></tr><tr><td>PEG 0:1:1</td><td>Info only</td><td>Display PEG root port present status.</td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Change VGA channel to front or rear.</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:1 Max speed.</td></tr></table>

Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display Memory Reference Code Version.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Total Memory.</td></tr><tr><td>VDD</td><td>Info only</td><td>Display VDD value (mVolts)</td></tr><tr><td>DIMM#0</td><td>Info only</td><td>Display Memory in the DIMM.</td></tr><tr><td>DIMM#2</td><td>Info only</td><td>Display Memory in the DIMM.</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Display Memory Timings</td></tr><tr><td>XMP Profile 1</td><td>Info only</td><td>Display XMP support status.</td></tr><tr><td>XMP Profile 2</td><td>Info only</td><td>Display XMP support status.</td></tr></table>

# 8.4.1 PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel PCH RC Version</td><td>Info only</td><td>Display PCH RC version.</td></tr><tr><td>Intel PCH SKU Name</td><td>Info only</td><td>Display PCH SKU.</td></tr><tr><td>Intel PCH Rev ID</td><td>Info only</td><td>Display PCH Rev ID</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>*HD Audio Configuration1</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN I219LM Controller</td><td>EnabledDisabled</td><td>Enable or disable onboard NIC.</td></tr><tr><td>*LAN#1 (Intel I219LM) 1</td><td>RearFront</td><td>LAN Select. Front: LAN to Front (Default). Rear: LAN to RTM.</td></tr><tr><td>*LAN#1 (Intel I210TI) 1</td><td>RearFront</td><td>LAN Select. Front: LAN to Front (Default). Rear: LAN to RTM.</td></tr><tr><td>High Precision Timer</td><td>EnabledDisabled</td><td>Enable or Disable the High Precision Event Timer.</td></tr></table>

Note: \* These items are not supported by cPCI-6636DZ.

# PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 1</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 2-3 $^{1}$ </td><td>Submenu</td><td></td></tr><tr><td>PCI Port 4 is assigned to LAN I219LM</td><td>Info only</td><td></td></tr><tr><td>PCIE Port 5-8 Configuration $^{1}$ </td><td>4x1 Port1x4 Port</td><td>To configure PCI-E Port 5-7 of PCH.[4X1]:Port 5-8 (x1) and Port 8 (x1) / [1x2 2x1]:Port 5 (x2), Port 6 (disabled), Ports 7 and Port 8 (x1).</td></tr><tr><td>PCI Express Root Port 5-8 $^{1}$ </td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 11-14 $^{2}$ </td><td>Submenu</td><td></td></tr></table>

Notes: 1These items are not supported by cPCI-6636DZ. 2These items are only supported by cPCI-6636DZ.

PCI Express Configuration > PCI Express Root Port x

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port x</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Select PCI Express port speed.</td></tr></table>

\*HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>DisabledEnabledAuto</td><td>Control Detection of the HD-Audio device. Disabled: HDA will be unconditionally disabled. Enabled: HDA will be unconditionally enabled. Auto: HDA will be enabled if present, disabled otherwise.</td></tr></table>

Note: \* This item is not supported by cPCI-6636DZ.

# 8.5 Security

# 8.5.1 Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td></td></tr><tr><td>User Password</td><td>Enter password</td><td></td></tr><tr><td>Secure Boot menu</td><td>Submenu</td><td></td></tr></table>

# 8.5.2 \*Secure Boot Menu

<table><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>Vender Keys</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Disabled Enabled</td><td>Secure Boot can be enabled if 1.System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled</td></tr><tr><td>Secure Boot Mode</td><td>Standard Custom</td><td>Secure Boot mode selector. &#x27;Custom&#x27; Mode enables users to change Image Execution policy and manage Secure Boot Keys</td></tr></table>

Note: \* This item is not supported by cPCI-6636DZ.

# 8.6 Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2"></td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Enable/Disable the onboard SATA controllers.</td></tr><tr><td>Bootup NumLock State</td><td>On</td><td>Select SATA controller mode.</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enables or Disables Quiet Boot option.</td></tr><tr><td>Boot Option Priorities</td><td colspan="2"></td></tr><tr><td>Fast Boot</td><td>DisabledEnable</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>Driver Option Priorities</td><td colspan="2"></td></tr><tr><td>New Boot Option Policy</td><td>DefaultPlace FirstPlace Last</td><td>Controls the placement of newly detected UEFI boot options.</td></tr></table>

# 8.7 Save & Exit

8.7.1 Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset the system without saving any changes.</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr></table>

# 9 Checkpoints & Beep Codes

The eight User LEDs on the front panel display port 80h POST codes in hexadecimal during boot up. Users can use the POST codes to identify issues during the BIOS POST process.

9.1 Checkpoint Ranges

<table><tr><td>Status Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xCF</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# 9.2 Standard Checkpoints

SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# SEC Beep Codes

None

PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB – 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

DXE Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td>DXE Error Codes</td><td></td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

ACPI/ASL Checkpoints

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0x72</td><td>System is entering S5 sleep statue.</td></tr><tr><td>0x84 (xhci mode enabled)</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0x84 (xhci mode enabled)</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr><tr><td>0x83 (xhci mode disabled)</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0x83 (xhci mode disabled)</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

9.3 OEM-Reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this user’s manual for future reference.
 Read the specifications section of this manual for detailed information on the operating environment of this equipment.
? When installing/mounting or uninstalling/removing equipment:

 Turn off power and unplug any power cords/cables.

 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);

 Make sure to use recommended voltage and power source settings;

 Always install and operate equipment near an easily accessible electrical socket-outlet;

 Secure the power cord (do not place any object on/over the power cord);

 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a vertical warning sign. At the top is a red equilateral triangle containing a white exclamation point in its center. Directly below the triangle is a white rectangular box containing the word 'WARNING' in black, capital letters.](.cpci-6636-50m-15111-2000-03/b861b01c990e48f60ea9f2ac7dfca71d424e225d6e763aba80261e9fcf485001.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

 Equipment must be serviced by authorized technicians when:

 The power cord or plug is damaged;
 Liquid has penetrated the equipment;
 It has been exposed to high humidity/moisture;
 It is not functioning or does not function according to the user’s manual;
 It has been dropped and/or damaged; and/or,
 It has an obvious sign of breakage.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No.66 Huaya 1st Rd., Guishan District

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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