# cPCI-6640

Performance 6U CompactPCI®

8th/9th Gen Intel® Core™ i7/i5/i3 Processor Blade

User's Manual

![Green circuit board with various ports and connectors, no visible text or symbols](.cpci-6640-50m-00112-1000-10/c25fdd9726d6699424ad785c21f0697400bc3878fbf1a807c3b49766bfad30b2.jpg)

Manual Rev.: 1.0

Revision Date: March 27, 2023

Part Number: 50M-00112-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2023-03-27</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2023 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines, no text or labels present](.cpci-6640-50m-00112-1000-10/a9877bd82492a307e67cfe2493d092b61cd62999f29169f31c045ae132c68943.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.cpci-6640-50m-00112-1000-10/1cb9a53f8b0039c382e1f05e57d111e90f1d4d7e3bafe6194efa3c96cc65648d.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.cpci-6640-50m-00112-1000-10/03d3c86c0dab0dca7bab77d9c2b1b51d3167190f939144c287bb7335d4012f1f.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.cpci-6640-50m-00112-1000-10/56be17aa1d35afb2bf45f8fc95df81905eee498c160655f4958383a2c2f65cf6.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.cpci-6640-50m-00112-1000-10/8bdd27d1977d780c1c69023cc187ba1beef1fe97b03cc50ac2a416b799881ee7.jpg)

廢電池請回收

# California Proposition 65 Warning

![A yellow triangular warning sign with a black border containing a black exclamation mark in the center.](.cpci-6640-50m-00112-1000-10/664c315f98ef42153845231979ee233537670b6a59c0164ca48bd05c7df3ce20.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP),

1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a graphic icon of a document. It shows a white piece of paper with a folded top-left corner and faint gray horizontal lines running across it. A large, red checkmark is drawn diagonally across the center of the page.](.cpci-6640-50m-00112-1000-10/91190ffee14757b2fa2b1d2147c8bb46f8f772045b52356c06ee3433f5430db0.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a black border. In the center of the triangle is a large black exclamation mark.](.cpci-6640-50m-00112-1000-10/99e5a158cf43d4de290c89426897e3dbc1d654eb06e198839240181ad843605f.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image features a red triangular warning sign with a white border. Centered inside the triangle is a black exclamation point. A thin black horizontal line runs across the very top edge of the sign.](.cpci-6640-50m-00112-1000-10/c626866192bd61dd1c8ab49205ef3a1ef06b4fee7771e078bf9b30b69654bf1e.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 2
1.3 Package Contents 3

# 2 Specifications.... 5

2.1 cPCI-6640 Processor Blade Specifications 5
2.2 Block Diagrams.... 7
2.3 I/O Connectivity Table 8
2.4 Power Requirements 9

# 3 Board Interfaces.... 11

3.1 cPCI-6640 Board Layout 11
3.2 cPCI-6640 Front Panel 13
3.3 Connector Pin Assignments 14
3.4 Jumpers and Switches.... 22

# 4 Getting Started 23

4.1 CPU and Heatsink 23
4.2 CFast Card Installation 24
4.3 2.5" SATA Drive Installation.... 26
4.4 Installing the cPCI-6640 to the Chassis.... 29
4.5 Power Sequence 30

# 5 Driver Installation.... 33

5.1 cPCI-6640 Drivers.... 33

# 6 BIOS Setup Utility 35

6.1 Starting the BIOS 35
6.2 Main Setup.... 37
6.3 Advanced 40
6.4 Chipset 48
6.5 Security 57
6.6 Boot 58
6.7 Save & Exit 59

# Important Safety Instructions.... 61

# Getting Service 63

# List of Figures

Figure 2-1: cPCI-6640 Processor Blade Functional Block Diagram .. 7
Figure 3-1: cPCI-6640 Board Layout 12
Figure 3-2: cPCI-6640 Front Panel Layout 13

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# List of Tables

Table 2-1: cPCI-6640 Processor Blade Specifications .... 5

Table 2-2: cPCI-6640 I/O Connectivity 8

Table 3-1: cPCI-6640 Front Panel System LED Descriptions ..... 13

Table 3-2: RJ-45 GbE Pin Definitions....14

Table 3-3: LAN LED Status Definitions....14

Table 3-4: COM DB-9 Pin Definition....15

Table 3-5: COM Pin Header Definition .... 15

Table 3-6: USB 3.0 Pin Definition 16

Table 3-7: Serial ATA Connector with Power Pin Definition ..... 17

Table 3-8: CFast Socket Pin Definition....18

Table 3-9: DVI-I Connector Pin Definition....19

Table 3-10: CompactPCI J1 Connector Pin Definition....20

Table 3-11: CompactPCI J2 Connector Pin Definition....21

Table 3-12: RTC Reset 22

Table 3-13: ME Lock Jumper Settings....22

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# 1 Introduction

# 1.1 Overview

The ADLINK cPCI-6640 is a 6U CompactPCI® processor blade featuring an 8th/9th Gen Intel® Core™ (formerly Coffee Lake-H) with Mobile Intel® CM246 Chipset. Dual SO-DIMM slots provide up to 64GB of DDR4-2666 dual-channel memory (2x 32GB modules). ECC memory is also available when paired with a supporting CPU.

The cPCI-6640 processor blade comes in dual-slot (8HP) width form factor. Front panel I/O for the cPCI-6640 includes 2x DVI-D, 8x GbE (2x configurable as PoE ports by BOM option), 6x USB 3.0 ports, and 2x RS232 serial ports.

Graphics support is integrated on the CPU and supports 2 independent displays. Storage includes a CFAST slot and a 22-pin direct connector for 2.5" SATA 6Gb/s drive.

The cPCI-6640 offers outstanding performance provided by the Intel® processor, and is an ideal solution for military, aerospace, transportation and other industrial applications that require best value per watt computing power.

# 1.2 Features

▶ 6U CompactPCI blade in 8HP width form factor
▶ 8th/9th Gen Intel® Core™ with Mobile Intel® CM246 Chipset
▶ Graphics and memory controllers integrated in processor
▶ Dual channel DDR4-2666 memory with available ECC up to 64GB
▶ 32bit/33MHz CompactPCI Interface based on PCI specifications, universal V(I/O)
▶ Supports host mode operation
▶ Dual DVI ports on front panel
▶ Seven RJ45 Gigabit Ethernet ports by Intel® Ethernet Controller I210IT on front panel; two RJ45 ports can optionally support PoE functions (7W per port, 14W total)
▶ One RJ45 Gigabit Ethernet via Intel® i219LM
▶ Optional Infineon SLB9672 TPM support

# 1.3 Package Contents

The cPCI-6640 is packaged with the following components. If any of the following items are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of cPCI-6640 non-standard configurations will vary depending on customer requests.

# CPU module

▶ The cPCI-6640 Processor Blade

▷ CPU and memory specifications will differ depending on options selected

▷ Thermal module is assembled on the board

▶ 2.5" SATA drive accessory pack

# Rear Transition Module

▶ Dependent on the module selected

![The image displays a simple icon of a white document with a folded top-right corner. Faint horizontal grey lines run across the page, suggesting text. Overlaid on the right side of the document is a large, bold red checkmark.](.cpci-6640-50m-00112-1000-10/0b64feb80e9ff6bf6a4272381e4c3d42ef8deeec41775c16b3ecdd841000a5eb.jpg)
NOTE:

The contents of non-standard cPCI-6640 configurations may vary depending on the customer's requirements.

![The image displays a standard warning sign consisting of a yellow triangle with a thick black border. Centered inside the triangle is a large black exclamation point. The sign is set against a plain white background.](.cpci-6640-50m-00112-1000-10/60366fadcc9159ec23cfd61b9a8cd9a42ad3e77b2a14bf816292a8c0d8f26625.jpg)
CAUTION:

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

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# 2 Specifications

2.1 cPCI-6640 Processor Blade Specifications

<table><tr><td>CompactPCI Standards</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev. 2.0PICMG® 2.9 System Management (IPMI Rev. 1.5)PICMG® 2.16 Packet Switching Backplane Rev. 1.0</td></tr><tr><td>Mechanical</td><td>Standard 6U CompactPCI®Board size: 233mm x 160mmDual slot (8HP)CompactPCI® connectors: J1, J2</td></tr><tr><td>Processor</td><td>Intel® CoreTM i7-9850HE processor, 6-cores/12-threads, 9MB cache, 2.7/4.4GHz, 45/35W by cTDP, Intel® UHD Graphics 630Intel® CoreTM i7-9850HL processor, 6-cores/12-threads, 9MB cache, 1.9/4.1GHz, 25W TDP, Intel® UHD Graphics 630Intel® CoreTM i5-8400H processor, 4-cores/8-threads, 8M cache, 2.5/4.2GHz, 45/35W by cTDP, Intel® UHD Graphics 630Intel® CoreTM i3-9100HL processor, 4-cores/4-threads, 6MB cache, 1.6/2.9GHz, 25W, Intel® UHD Graphics 630</td></tr><tr><td>Chipset</td><td>Mobile Intel® CM246 Chipset</td></tr><tr><td>Memory</td><td>Dual-channel DDR4-2666 SODIMM sockets, up to 64GB (2x 32GB modules)ECC memory is available when paired with supporting CPU.</td></tr><tr><td>CompactPCI Bus</td><td>One PCIe x1 Pericom PI7C9X113 PCIe-to-PCI bridgePCI 32-bit/33MHz to J1, J2; universal V I/OSupports host mode</td></tr><tr><td>Gigabit Ethernet</td><td>7x RJ45 ports via Intel® i210-IT Ethernet controllers (two configurable as PoE by BOM option)1x RJ45 port via Intel® i219LM Ethernet controller</td></tr><tr><td>Display</td><td>2x DVI-I ports on front panel</td></tr><tr><td>Serial Ports</td><td>2x RS-232 ports on front panel</td></tr><tr><td>USB</td><td>6x USB 3.0 on front panel</td></tr><tr><td>TPM</td><td>TPM 2.0: SLB9672</td></tr><tr><td>Storage Interfaces $^{1}$ </td><td>1x onboard 2.5” SATA connector supporting SATA 6Gb/s drive1x CFast slot</td></tr></table>

Table 2-1: cPCI-6640 Processor Blade Specifications

<table><tr><td>Faceplate I/O</td><td>8x 10/100/1000BASE-T Ethernet ports2x DVI-I ports6x USB 3.0 ports2x DB9 serial port</td></tr><tr><td>OS Compatibility</td><td>Windows 10 Enterprise 2004 64-bit(Please contact ADLINK for other OS support)</td></tr><tr><td>Environmental</td><td>Operating Temperature (with forced air flow) $^{2}$ :Standard: 0°C to +60°CExtreme temperature: -40°C to +85°CStorage Temperature: -40°C to +85°CHumidity: 95% @60°C non-condensingShock: 20G peak-to-peak, 11ms duration, non-operatingVibration $^{1}$ : 2Grms, 5-500Hz, each axis, operating (w/o hard drive)</td></tr><tr><td>EMI</td><td>EMC: EN 55032/35EMI: CISPR 32, FCC Part 15B Class AEMS:IEC 61000-4-11IEC 61000-4-2 ESD: Contact: 4 kV; Air: 8 kVIEC 61000-4-3 RS: 80 MHz to 1 GHz: 10 V/mIEC 61000-4-4 EFT: Power: 2 kV; Signal: 1 kVIEC 61000-4-5 Surge: Power: 2 kV; Signal: 1 kVIEC 61000-4-6 CS: 1 VIEC 61000-4-8 PFM</td></tr></table>

Table 2-1: cPCI-6640 Processor Blade Specifications

1. The storage device limits the operational vibration tolerance. When the application requires higher specification for anti-vibration, it is recommended to use a flash storage device.
2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Sufficient forced air-flow is required. Temperature limits of optional mass storage devices may also affect the thermal specification.

# 2.2 Block Diagrams

# cPCI-6640 Processor Blade

![Based on the provided flowchart, here is an accurate and concise description of the labeled blocks and their connections:\n\n**Top Section: Coffee Lake-H (CPU1)**\n*   **Connections:**\n    *   **DVI-I (DVI2)** connects to **PTN3355 (U5)**, which connects to **DDI3(D)** (labeled 'DVI with PCH:DDPD').\n    *   **DVI-I (DVI1)** connects to **PTN3355 (U3)**, which connects to **DDI2(C)** (labeled 'DVI with DDPC') and **DDI1(B)** (labeled 'DP with DDI3_AUX'). There is also a connection labeled **eDP(E)**.\n    *   Line **0** connects to **SODIMM 1 (w/wo ECC) (DIMM1)**.\n    *   Line **1** connects to **SODIMM 2 (w/wo ECC) (DIMM2)**.\n    *   **DMI** connects the CPU to the **Intel CM246 chipset (U2)**. A label **PCI** is visible near this connection.\n\n**Middle Section: Intel CM246 chipset (U2)**\n*   **Left Side Connections (from top to bottom):**\n    *   **PCIe L12** connects to **I12 (U13)**, which connects to **2 x RJ-45 (with PoE) (RJ1)**.\n    *   **PCIe L9** connects to **I120 (U15)**.\n    *   **PCIe L7** connects to **I120 (U17)**, which connects to **2 x RJ-45 (RJ2)**.\n    *   **PCIe L13** connects to **I120 (U19)**.\n    *   **PCIe L11** connects to **I120 (U11)**, which connects to **RJ-45 2 x USB (CN9)**. The line is labeled **2 x USB3.0/2.0 U3 (L4_L9) U12 (_1_9)**.\n    *   **PCIe L6** connects to **I120 (U9)**, which connects to **RJ-45 2 x USB (CN8)**. The line is labeled **2 x USB3.0/2.0 U3(L5_L2) U12 (_7_5)**.\n    *   **PCIe L8** connects to **I120 (U7)**, which connects to **RJ-45 2 x USB (CN7)**. The line is labeled **2 x USB3.0/2.0 U21(L1_L0) U12 (_1_3)**.\n    *   **GbE L10** connects to **I129 (U21)**, which connects to **RJ-45 (CN10)**.\n*   **Right Side Connections (from top to bottom):**\n    *   **L20** connects to **SATA**, which connects to **HDD (CN11)**.\n    *   **L21** connects to **SATA**, which connects to **CFAST (CN12)**.\n    *   **L15** connects to **PCIe**, which connects to **PI7C9X113 (U22)**. This connects via **PCI 32bit/33MHz** to **J1 (J1)** and **J2 (J2)**.\n    *   **SPI** connects to **BIOS (U26)** and **TPM 2.0 (TPM1)**.\n*   **Bottom Connections:**\n    *   **LPC** connects to **LPC TO UART NCT5124D (U26) (0x4E)**.\n    *   **SATALED-L** connects to the HDD LED.\n    *   **GPO** connects to the Power and WDT LEDs.\n\n**Bottom Left Section: UART Connections**\n*   **DB9** connects to **COM_A**, which connects to **HEADER (CN13)**.\n*   **DB9** connects to **COM_B**, which connects to **HEADER (CN14)** via **By cable**.\n*   Both headers connect to **LPC TO UART NCT5124D (U26) (0x4E)**.\n\n**Bottom Right Section: LEDs**\n*   **LED** legend lists:\n    *   **HDD (yellow)** connected to **SATALED-L**.\n    *   **Power (green)** connected to **GPO** via **BY HW**.\n    *   **WDT (red)** connected to **GPO**.](.cpci-6640-50m-00112-1000-10/5d485d1aa9b147bfa8b909f05fb1c749fa09ef89c64bd056797dc348b75d0494.jpg)

Figure 2-1: cPCI-6640 Processor Blade Functional Block Diagram

# 2.3 I/O Connectivity Table

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-6640 (8HP)</td></tr><tr><td>Faceplate</td><td>Onboard</td></tr><tr><td>GbE</td><td>Y (RJ45 x8)</td><td>-</td></tr><tr><td>COM</td><td>Y (DB9 x2)</td><td>-</td></tr><tr><td>USB 3.0</td><td>Y x6</td><td>-</td></tr><tr><td>DVI</td><td>Y x2</td><td>-</td></tr><tr><td>Serial ATA</td><td>-</td><td>Y x1</td></tr><tr><td>CFast</td><td>-</td><td>Y x1</td></tr><tr><td>LED</td><td>Y x3</td><td>-</td></tr><tr><td>Reset Button</td><td>Y</td><td>-</td></tr></table>

Table 2-2: cPCI-6640 I/O Connectivity

# 2.4 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>120 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>120 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

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# 3 Board Interfaces

3.1 cPCI-6640 Board Layout
![2x LAN\n2x LAN\n1x LAN\n2x USB3\n1x LAN\n2x USB3\n1x LAN\n2x USB3\n1x LAN\n1x DVI-I\n1x RS-232\n1x DVI-I\n1x RS-232\nUDIE\nCFast\nRTC Socket\nCN4\nCN2\nCN1\nCN6\nCN14\nCN13\nDIMM1\nDIMM2\nChipset\nCPU\nJ2\nJ1](.cpci-6640-50m-00112-1000-10/da55376dcacc639ae3d1673183865f329c6223cd1c411ef6000fdcbb3d770c78.jpg)

<table><tr><td>CPU</td><td>Intel® Processor</td><td>DVI-I</td><td>DVI-I connectors</td></tr><tr><td>Chipset</td><td>Intel® CM246 Chipset</td><td>J1-J2</td><td>CompactPCI connectors</td></tr><tr><td>CN1</td><td>RTC reset jumper</td><td>LAN</td><td>RJ45 Ethernet connectors</td></tr><tr><td>CN2/CN4</td><td>Debug headers*</td><td>RS-232</td><td>COM port connectors</td></tr><tr><td>CN6</td><td>ME Lock Jumper</td><td>RTC socket</td><td>RTC battery socket</td></tr><tr><td>CN13/14</td><td>COM port headers</td><td>USB3</td><td>USB 3.0 connectors</td></tr><tr><td>CFast</td><td>CFast slot</td><td>2.5” Drive</td><td>2.5” SATA device connector</td></tr><tr><td>DIMM1/DIMM2</td><td>Memory sockets</td><td></td><td></td></tr></table>

Figure 3-1: cPCI-6640 Board Layout

![The image displays a digital icon of a document. It features a white piece of paper with a folded top-left corner and faint horizontal gray lines running across the surface. A large, bold red checkmark is drawn diagonally across the center of the document, slanting upwards from left to right.](.cpci-6640-50m-00112-1000-10/4efc9f30b35c36a7b8a08af9fd896ab3b56ecae7b7f3bfc166a06abe9c38c729.jpg)
NOTE:

Note: Debug Headers (CN2/CN4) are for ADLINK use only and may not be present on all boards.

# 3.2 cPCI-6640 Front Panel

Front Panel Layout
![LAN1 LAN3 LAN5 LAN6 LAN7 COM2 COM1\nLAN 2 LAN 4 USB3.0 LAN5 LAN6 LAN7 LAN8 COM2 COM1\nRST PW WD HD DVI-I 2 DVI-I 1\nLAN2 LAN4](.cpci-6640-50m-00112-1000-10/093480bacdd32e07554cec517c44c150d67ce6bb72e446a6b84e851b86aee950.jpg)

Figure 3-2: cPCI-6640 Front Panel Layout

Note: LAN1 and LAN2 support PoE (by BOM option).

System LEDs

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="2">Power Status (PW)</td><td rowspan="2">Green/Red</td><td>Off</td><td>System is off</td></tr><tr><td>Steady On</td><td>Post OK</td></tr><tr><td rowspan="2">Watchdog (WD)</td><td rowspan="2">Red</td><td>Off</td><td>No Watchdog event</td></tr><tr><td>Steady On</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">Drive Status (HD)</td><td rowspan="2">Yellow</td><td>Off</td><td>No drive activity</td></tr><tr><td>Blinking</td><td>Drive activity</td></tr></table>

Table 3-1: cPCI-6640 Front Panel System LED Descriptions

# 3.3 Connector Pin Assignments

RJ-45 Gigabit Ethernet Connectors

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>LAN_TX0+</td></tr><tr><td>2</td><td>TX-</td><td>LAN_TX0-</td></tr><tr><td>3</td><td>RX+</td><td>LAN_TX1+</td></tr><tr><td>4</td><td>—</td><td>LAN_TX2+</td></tr><tr><td>5</td><td>—</td><td>LAN_TX2-</td></tr><tr><td>6</td><td>RX-</td><td>LAN_TX1-</td></tr><tr><td>7</td><td>—</td><td>LAN_TX3+</td></tr><tr><td>8</td><td>—</td><td>LAN_TX3-</td></tr></table>

Table 3-2: RJ-45 GbE Pin Definitions

Speed Activity
![8\n1](.cpci-6640-50m-00112-1000-10/f4f81dc26118beac457f69882675d4482c7f9272f68d8f6ff04c62862c1ca820.jpg)

<table><tr><td colspan="2">Status</td><td>Speed LED (Green/Orange)</td><td>Activity LED (Yellow)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Orange</td><td>ON</td></tr><tr><td>Active</td><td>Orange</td><td>Blinking</td></tr></table>

Table 3-3: LAN LED Status Definitions

# COM DB-9

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD-L</td></tr><tr><td>2</td><td>RXD</td></tr><tr><td>3</td><td>TXD</td></tr><tr><td>4</td><td>DTR-L</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>DSR-L</td></tr><tr><td>7</td><td>RTS-L</td></tr><tr><td>8</td><td>CTS-L</td></tr><tr><td>9</td><td>RI-L</td></tr></table>

![6\n1\n5](.cpci-6640-50m-00112-1000-10/ce18c397f9606bbcd187edefc5d84aabe979425c37f5c4cab204e139c354adee.jpg)

Table 3-4: COM DB-9 Pin Definition

# COM Pin Header

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD-L</td></tr><tr><td>2</td><td>DSR-L</td></tr><tr><td>3</td><td>RXD</td></tr><tr><td>4</td><td>RTS-L</td></tr><tr><td>5</td><td>TXD</td></tr><tr><td>6</td><td>CTS-L</td></tr><tr><td>7</td><td>DTR-L</td></tr><tr><td>8</td><td>RI-L</td></tr><tr><td>9</td><td>Ground</td></tr><tr><td>10</td><td>NC</td></tr></table>

![1\n2\n9\n10](.cpci-6640-50m-00112-1000-10/1e1448e602c91518f12b7007aef6957086fef86fe3a7dda400e72602dbfe6996.jpg)

Table 3-5: COM Pin Header Definition

USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_N</td></tr><tr><td>3</td><td>USB2_P</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_RXN</td></tr><tr><td>6</td><td>USB3A_RXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_TXN</td></tr><tr><td>9</td><td>USB3A_TXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.cpci-6640-50m-00112-1000-10/306aeefbb5003998cec4137f0f0c953fed495bd1a5bfece84dfc37e40cfb94b2.jpg)

Table 3-6: USB 3.0 Pin Definition

SATA Connector with Power (for 2.5" drive)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>3.3V</td></tr><tr><td>P2</td><td>3.3V</td></tr><tr><td>P3</td><td>3.3V</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>NC</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>NC</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-6640-50m-00112-1000-10/6c522d64c0f1ad6baba3a7282d74e4f28b48a0dc079e7f03154985036f44620f.jpg)

Table 3-7: Serial ATA Connector with Power Pin Definition

# CFast Socket

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>S1</td><td>Ground</td></tr><tr><td>S2</td><td>SATA_TX-P</td></tr><tr><td>S3</td><td>SATA_TX-N</td></tr><tr><td>S4</td><td>Ground</td></tr><tr><td>S5</td><td>SATA_RX-N</td></tr><tr><td>S6</td><td>SATA_RX-P</td></tr><tr><td>S7</td><td>Ground</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>Ground</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>NC</td></tr><tr><td>P5</td><td>NC</td></tr><tr><td>P6</td><td>NC</td></tr><tr><td>P7</td><td>Ground</td></tr><tr><td>P8</td><td>NC</td></tr><tr><td>P9</td><td>NC</td></tr><tr><td>P10</td><td>NC</td></tr><tr><td>P11</td><td>NC</td></tr><tr><td>P12</td><td>NC</td></tr><tr><td>P13</td><td>P3V3</td></tr><tr><td>P14</td><td>P3V3</td></tr><tr><td>P15</td><td>Ground</td></tr><tr><td>P16</td><td>Ground</td></tr><tr><td>P17</td><td>NC</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.cpci-6640-50m-00112-1000-10/070c1fda368bf70716467b5ea8b8456fdc2b13e8aff0a020ab57a6670000cce2.jpg)

![24\nP1\nS1](.cpci-6640-50m-00112-1000-10/df2a73680e1eb8c7adbe9352aa8ed9ee5484dd402082ebd1fcc3530d655eae77.jpg)

Table 3-8: CFast Socket Pin Definition

# DVI-I Connector

![Front view of a 24-pin D-sub connector (no text or symbols visible)](.cpci-6640-50m-00112-1000-10/6c2dc304306f61dcb31d73e2ab759f1923953cc5293fa7a72506675d268452fc.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2-</td><td>16</td><td>Hot Plug Detect</td></tr><tr><td>2</td><td>TMDS Data2+</td><td>17</td><td>TMDS Data0-</td></tr><tr><td>3</td><td>GND</td><td>18</td><td>TMDSData0+</td></tr><tr><td>4</td><td>NC</td><td>19</td><td>GND</td></tr><tr><td>5</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>6</td><td>DDC Clock [SCL]</td><td>21</td><td>NC</td></tr><tr><td>7</td><td>DDC Data [SDA]</td><td>22</td><td>GND</td></tr><tr><td>8</td><td>Analog vertical sync</td><td>23</td><td>TMDS Clock +</td></tr><tr><td>9</td><td>TMDS Data1-</td><td>24</td><td>TMDS Clock -</td></tr><tr><td>10</td><td>TMDS Data1+</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>GND</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>NC</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>NC</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 3-9: DVI-I Connector Pin Definition

CompactPCI J1 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>NC, pull 4.7kOhm</td><td>NC, pull 10kOhm</td><td>P3V3_STB</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>CPCI_AD1</td><td>+5V</td><td>CPCI_VIO</td><td>CPCI_AD0</td><td>NC, pull 4.7kOhm</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>P3V3_STB</td><td>CPCI_AD4</td><td>CPCI_AD3</td><td>+5V</td><td>CPCI_AD2</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>CPCI_AD7</td><td>GND</td><td>P3V3_STB</td><td>CPCI_AD6</td><td>CPCI_AD5</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>P3V3_STB</td><td>CPCI_AD9</td><td>CPCI_AD8</td><td>CPCI_M66EN</td><td>CPCI_CBE-L0</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_AD12</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD11</td><td>CPCI_AD10</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>P3V3_STB</td><td>CPCI_AD15</td><td>CPCI_AD14</td><td>GND</td><td>CPCI_AD13</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>CPCI_SERR-L</td><td>GND</td><td>P3V3_STB</td><td>CPCI_PAR</td><td>CPCI_CBE-L1</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>P3V3_STB</td><td>NC</td><td>NC</td><td>GND</td><td>CPCI_PERR-L</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>CPCI_DEVSEL-L</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_STOP-L</td><td>CPCI_LOCK-L</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>P3V3_STB</td><td>CPCI_FRAME-L</td><td>CPCI_IRDY-L</td><td>CPCI_BDSEL#</td><td>CPCI_TRDY-L</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>CPCI_AD18</td><td>CPCI_AD17</td><td>CPCI_AD16</td><td>GND</td><td>CPCI_CBE-L2</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>CPCI_AD21</td><td>GND</td><td>P3V3_STB</td><td>CPCI_AD20</td><td>CPCI_AD19</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CPCI_CBE-L3</td><td>CPCI_IDSEL</td><td>CPCI_AD23</td><td>GND</td><td>CPCI_AD22</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>CPCI_AD26</td><td>GND</td><td>CPCI_VIO</td><td>CPCI_AD25</td><td>CPCI_AD24</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>CPCI_AD30</td><td>CPCI_AD29</td><td>CPCI_AD28</td><td>GND</td><td>CPCI_AD27</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>CPCI_REQ_L0</td><td>CPCI_PRESENT-L</td><td>P3V3_STB</td><td>CPCI_CLK0</td><td>CPCI_AD31</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_RST-L</td><td>GND</td><td>CPCI_GNT_L0</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>+5V_IPMB</td><td>IPMC_HEALTHY-L</td><td>CPCI_VIO</td><td>NC, pull 1kOhm</td><td>NC, pull 1kOhm</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_TCK</td><td>CPCI_INTB-L</td><td>CPCI_INTC-L</td><td>+5V</td><td>CPCI_TDI</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>+5V</td><td>CPCI_TMS</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>NC</td><td>CPCI_TRST-L</td><td>NC</td><td>+5V</td><td>GND</td></tr></table>

Table 3-10: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CPCI_CLK6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CPCI_CLK5</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>GND</td><td>J2_RST-L</td><td>CPCI_REQ-L6</td><td>CPCI_GNT-L6</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>CPCI_DEG-L</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_FAL-L</td><td>CPCI_REQ-L5</td><td>CPCI_GNT-L5</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>CPCI_VIO</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CPCI_CLK4</td><td>GND</td><td>CPCI_GNT-L3</td><td>CPCI_REQ-L4</td><td>CPCI_GNT-L4</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CPCI_CLK2</td><td>CPCI_CLK3</td><td>SYSEN-L</td><td>CPCI_GNT-L2</td><td>CPCI_REQ-L3</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CPCI_CLK1</td><td>GND</td><td>CPCI_REQ-L1</td><td>CPCI_GNT-L1</td><td>CPCI_REQ-L2</td><td>GND</td></tr></table>

Table 3-11: CompactPCI J2 Connector Pin Definition

# 3.4 Jumpers and Switches

Refer to "cPCI-6640 Board Layout" on page 11 for jumper locations.

RTC Reset Jumper (CN1)

<table><tr><td>Pin #</td><td>Behavior</td></tr><tr><td>1-2</td><td>Normal operation (default)</td></tr><tr><td>2-3</td><td>Reset RTC</td></tr></table>

Table 3-12: RTC Reset

ME Lock Jumper (CN6)

<table><tr><td>Pin #</td><td>Behavior</td></tr><tr><td>1-2</td><td>ME locked (default)</td></tr><tr><td>2-3</td><td>ME unlocked</td></tr></table>

Table 3-13: ME Lock Jumper Settings

# System Reset Button

The cPCI-6640 has a system reset button on the front panel. See "cPCI-6640 Front Panel Layout" on page 13 for the button location.

![Simple diagram showing a red arrow pointing to a black rectangle, no text or symbols present](.cpci-6640-50m-00112-1000-10/e7c7782481d9434bee59ddc47f60a4e70edee1a043f1453e1714f5ba6cf85202.jpg)

# 4 Getting Started

This chapter describes the following installation procedures for the cPCI-6640 and rear transition module:

▶ CPU and Heatsink
▶ CFast card
▶ 2.5" SATA drive

# 4.1 CPU and Heatsink

The cPCI-6640 come with CPU and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance.

# 4.2 CFast Card Installation

The cPCI-6640 features a CFast card slot. Follow the instructions below to install a CFast card to the cPCI-6640.

1. The mounting hardware for the CFast card includes 1x bracket and 2x M2.5 screws (P/N 58-10442-0000).

![Metal dental implant with two screws on a red textured surface (no text or symbols visible)](.cpci-6640-50m-00112-1000-10/ada747b36671e922e1985db5e92255cb1dd1ceb348dfea8af6842724b12bafe1.jpg)

2. CFast slot is located at the top edge of the card, below the space for the 2.5" SATA drive. Insert the CFast card as shown below. Place the bracket over the card and align it with the two screw holes indicated

![CFast 32GB\nMade in Taiwan\nCE 32GB\nC152075 L194\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 32GB\nCE 620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000](.cpci-6640-50m-00112-1000-10/f0402814c76d4139c0f5fb876fa27ef282da91a269d3c35bfe9eb62361c1e915.jpg)

3. While holding the bracket in place, flip the blade over and insert the two screws through the holes as marked. Tighten the screws to secure the CFast card,

![ADLINK\nCE\n17\n20\n30\n40\n50\n60\n70\n80\n90\n100\n110\n120\n130\n140\n150\n160\n170\n180\n190\n200\n210\n220\n230\n240\n250\n260\n270\n280\n290\n300\n310\n320\n330\n340\n350\n360\n370\n380\n390\n400\n410\n420\n430\n440\n450\n460\n470\n480\n490\n500\n510\n520\n530\n540\n550\n560\n570\n580\n590\n600\n610\n620\n630\n640\n650\n660\n670\n680\n690\n700\n710\n720\n730\n740\n750\n760\n770\n780\n790\n800\n810\n820\n830\n840\n850\n860\n870\n880\n890\n900](.cpci-6640-50m-00112-1000-10/6c0b7cc68ffbc0a88163c5df57505686fd996450ad396739d3b0dc641b1ff873.jpg)

4. The CFast card is now ready for use.

# 4.3 2.5" SATA Drive Installation

The cPCI-6640 features an onboard 2.5" SATA drive connector.

1. The mounting hardware for the 2.5" SATA drive includes 4x M3 screws and 4x 5.5mm hex standoffs (P/N 58-10331-000E).

![Close-up of metallic screw and four small mechanical components on a textured pink surface (no text or symbols visible)](.cpci-6640-50m-00112-1000-10/f803b352bf55f3d28933fbc9337d8a3447d5277c5b988df60d5e81e7bf891795.jpg)

2. Install the 4 standoffs to the bottom of the 2.5" drive as shown below.

![Metallic electronic device casing with connectors and a gold-colored connector, placed on a red textured surface (no visible text or symbols)](.cpci-6640-50m-00112-1000-10/ecf039556348801a3701c6d1ade606d4943e61e2db7f90509cdd1fc4bdf0601f.jpg)

3. Install the 2.5" SATA drive into the connector on the blade as shown.

![Close-up of a Intel 350 DCS 98070 Series 48068 processor on a circuit board, surrounded by electronic components and wiring (no readable text or symbols on the device itself).](.cpci-6640-50m-00112-1000-10/cc9f1b556edfc28a3a8fbb9d2c01b172f1860e75c7cae45fb267e726815bd95b.jpg)

4. Flip the board over, and ensure that the four mounting holes are aligned with the standoffs as shown below.

![51-65319-0A20\nADLINK\nCE\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-460000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46000\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC-46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nPLC 46\nFLP M458585AAOS 271](.cpci-6640-50m-00112-1000-10/38d9b7ef47145a4e95a6ac7f7a68666ec443598fa40e3490cc8c32840d078c70.jpg)

5. Insert and tighten the four screws to secure the drive.

![ADLINK\nPLA10000\n上接32800V 1.111112565555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555](.cpci-6640-50m-00112-1000-10/88bd510eedeaf7a988e3b1cd470af927069f5790e6321e815329c311c9a94ffe.jpg)

6. The 2.5" SATA drive is now ready for use.

# 4.4 Installing the cPCI-6640 to the Chassis

The cPCI-6640 must be installed in a system slot of a 6U CompactPCI chassis (host mode only). These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.

2. Remove the blank face cover from the selected slot, if necessary.

3. Press down on the release catches of the cPCI-6640 ejector handles.

4. Remove the black plastic caps securing the mounting screws to the front panel.

5. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.

6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module front panel.

7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

# 4.5 Power Sequence

![This image displays a technical schematic diagram detailing power distribution and voltage specifications for a motherboard, specifically labeled 'Coffee Lake-H.'\n\n**Left Column (Specifications):**\n*   **Coffee Lake-H (6+2) TDP=45W**\n    *   VCC 0~1.52V 128A\n    *   VCCGT 0~1.52V 32A\n    *   VCCSA 0~1.52V 11.1A\n    *   VCCIO 0.95V 6.4A\n    *   VCCSTG 1.05V 0.02A\n    *   VCCST 1.05V 0.06A\n    *   VCCPLL 1.05V 0.15A\n    *   VCCPLL_OC 1.2V 0.130A\n    *   VDDQ 1.2V 3.3A\n*   **DDR4 SODIMM x 2**\n    *   VDDQ 1.2V 8A\n    *   VPP 2.5V 2A\n    *   VTT 0.6V 1A\n*   **CNL-PCH-H TDP=2.8W**\n    *   VCCPRIM_1P05 1.05V 7.59A\n    *   VCCPRIM_3P3 3.3V 1.65A\n    *   VCCPRIM_1P8 1.8V 0.882A (marked with a small green 'VRM' box)\n\n**Top Section:**\n*   **J1 connector** (in a red box)\n    *   P_+5V0_A 31.67A\n    *   18A\n\n**Main Diagram (Power Rails):**\n*   **PU1** (43.23A + 3.75A) connects to:\n    *   1. CPU (P_+VCORE): 128A\n    *   2. CPU (P_+VCCSA): 11.1A\n*   **PU2** (10.81A) connects to:\n    *   1. CPU (P_+VCCGT): 32A\n*   **PU9** (1.35A) connects to:\n    *   1. CPU (P_+0V95_VCCIO): 6.4A\n*   **PU10** (P_+3V3_A 5.92A) splits into:\n    *   **TPS2560** (2A / 5.4A) connects to:\n        *   1. 2 x DVI-I Connector: 1A\n        *   2. SATA Connector: 1A\n    *   1. 6 x USB3.0 Connector: 5.4A\n    *   **PU13** (P_+1V15_A 0.3A) connects to:\n        *   1. PCN: 1.65A\n        *   2. 2 x PTN3355: 0.12A\n        *   3. LAN I219: 0.16A\n        *   4. 7 x LAN I210: 1.57A\n        *   5. P7C9X113: 0.11A\n*   **PU11** (P_+2V5_VPP 2A)\n*   **PU12** (P_+0V6_VTT 0.75A / P_+1V2_VDDQ 12.18A) connects to:\n    *   1. 2 x DDR4 w/wo ECC SO-DIMM (8A)\n    *   1. CPU (VccPLL_OC): 0.13A\n    *   2. CPU (VDDQ): 3.3A\n*   **PU14** (P_+1V0_A 7.82A) connects to:\n    *   1. PCH: 7.59A\n    *   1. CPU (VCCSTG): 0.02A\n    *   **PQ5** (P_+1V05_VCCSTG 0.02A)\n    *   **PQ4** (P_+1V05_VCCST 0.06A) connects to:\n        *   1. CPU (VCCST): 0.06A\n    *   1. CPU (VccPLL): 0.15A\n*   **PU15** (P48V_POE 0.3A) connects to:\n    *   1. 2 x RJ45: 0.3A](.cpci-6640-50m-00112-1000-10/e6c4ac88ecfa02d3fa8b3d864fe5d70df623b31fdfe3db12d4e4eecab36f4004.jpg)

![Based on the provided flowchart/block diagram, here is the accurate and concise description of the labeled blocks and connections:\n\n**1. Power Input Section (Top Left)**\n*   **Block:** `J1` (Red) labeled `P_+5V0_A`. Text above reads `Power-in`.\n    *   **Connection:** Output `P_+5V0_A` connects to `U30 (1)` and `P_5V_P_IC_A`.\n*   **Block:** `P_5V_P_IC_A`.\n    *   **Connection:** Connects to `EN` of `P_48V_POE`. Text note: `P_5V_P_IC_A pull up enable`.\n*   **Block:** `U30 (1)`.\n    *   **Connection:** Output `P_+5V0_A PGD` connects to `EN` of `P_+3V3_A`. Text note: `P_+5V0_A pull up enable`.\n*   **Block:** `P_+3V3_A` (Red, 2).\n    *   **Connection:** Output `P_+3V3_A PGD` connects to `EN` of `P_+1V0_A`.\n*   **Block:** `P_48V_POE` (Red, 2).\n    *   **Connection:** Input `EN` connected to `P_5V_P_IC_A`.\n*   **Block:** `P_+1V0_A` (Red, 3).\n    *   **Connection:** Output `P_+1V05_A PGD` connects to `U32,U34 (4)`.\n*   **Block:** `U32,U34 (4)`.\n    *   **Connection:** Output `PCH_DPWR0K` (Right) and `PCH_RSMRST-L` (Right).\n\n**2. PCH Voltage Sequencing (Middle)**\n*   **Input:** `PCH_SLP_S4-L (5)`.\n    *   **Connection:** Connects to `EN` of `P_+1V05_VCCST`.\n*   **Block:** `P_+1V05_VCCST` (Red, 6.1).\n    *   **Connection:** Output `P_+1V05_VCCST PG (6.1)` connects to `P_+1V05_VCCSTG` block and a logic circuit below.\n*   **Logic Circuit:**\n    *   **Connection:** Input from `P_+1V05_VCCST`. Output `P_+2V5_VPP PGD (6.2)` connects to `EN` of `P_+2V5_VPP`.\n    *   **Text:** `rising quickly`, `falling slowly`.\n*   **Block:** `P_+2V5_VPP` (Red, 6.2).\n    *   **Connection:** Output `P_+2V5_VPP PGD (6.2)` connects to `EN` of `P_+1V2_VDDQ`.\n*   **Block:** `P_+1V2_VDDQ` (Red, 7).\n    *   **Connection:** Output `P_+1V2_VDDQ PGD (7)` connects to `D4_VTT_CNTL`.\n\n**3. PCH Block Connections (Right Side)**\n*   **Block:** `PCH` (Large rectangle).\n    *   **Inputs/Outputs:**\n        *   `PCH_DPWR0K` -) `DPWR0K` (Top Right).\n        *   `PCH_RSMRST-L` -) `RSMRST#` (Top Right).\n        *   `PCH_SLP_S4-L (5)` -) `SLP_S4#` (Middle Right, arrow points left).\n        *   `PCH_SLP_S3-L (5.1)` -) `SLP_S3#` (Middle Right, arrow points left).\n        *   `PCH_SLP_S0-L (5.2)` -) `SLP_S0#` (Middle Right, arrow points left).\n        *   `P_+3V3_LAN_A (7)` -) `SLP_LAN#` (Middle Right, arrow points left).\n\n**4. CPU Power Logic (Bottom Left/Center)**\n*   **Block:** `P_+1V05_VCCSTG` (Red, 6.1).\n    *   **Connections:** Input `EN` from `P_+1V05_VCCST PG` and `PCH_SLP_S3-L`. Output `P_+1V05_VCCSTG`.\n*   **Block:** `P_+1V2_VDDQ` (Red, 7).\n    *   **Connection:** Input `EN` from `P_+1V2_VDDQ_EN (7)`. Output `P_+1V2_VDDQ_PG (7)`.\n*   **Block:** `D4_VTT_CNTL` (9.1).\n    *   **Connection:** Input from `P_+1V2_VDDQ_PG (7)`. Output `D4_VTT_EN` connects to `EN` of `P_+0V6_VTT`.\n    *   **Text:** `CPU will assert DDR_VTT_CNTL after VCCST_PWRGD`.\n*   **Block:** `P_+0V6_VTT` (Red, 9.2).\n    *   **Connection:** Output `PG`.\n*   **Gate:** `U38 U36` (AND gate).\n    *   **Inputs:** `PCH_SLP_S3-L`, `P_+1V2_VDDQ_PG`, `P_+1V05_VCCST_PG`.\n    *   **Output:** `P_+0V95_VCCIO_EN`.\n*   **Block:** `P_+0V95_VCCIO` (Red, 8).\n    *   **Connection:** Output `P_+0V95_VCCIO_PG` connects to `U31 U38`.\n*   **Gate:** `U31 U38` (AND gate).\n    *   **Inputs:** `PCH_SLP_S3-L`, `P_+1V2_VDDQ_PG`, `P_+0V95_VCCIO_PG`.\n    *   **Output:** Connects to `U33`.\n*   **Gate:** `U33` (Buffer/Inverter).\n    *   **Output:** `H_VCCST_PG (9)` connects to `VCCST_PWRGD` (CPU input).\n\n**5. CPU Core Power Logic (Bottom Center)**\n*   **Block:** `P_+VCORE` (Red, 10).\n    *   **Connections:** Input `EN`. Output `PG`.\n    *   **Text:** `PG P_+VCORE P_+VCCSA`, `PG P_+VCCGT`.\n*   **Gate:** `U35` (AND gate).\n    *   **Inputs:** `P_+VCORE`, `P_+VCCSA`, `P_+VCCGT`.\n    *   **Output:** Connects to `PCH_PWR0K (10)` and `U37`.\n*   **Gate:** `U37` (Buffer).\n    *   **Output:** `SYS_PWR0K (11)`.\n\n**6. CPU Block (Bottom Right)**\n*   **Block:** `CPU` (Large rectangle).\n    *   **Input:** `VCCST_PWRGD`.\n    *   **Outputs:** `PCH_PWR0K` and `SYS_PWR0K` (arrows point left towards PCH block).](.cpci-6640-50m-00112-1000-10/bf709e9e8e5b31234bdd9c7396aa33f1674c56ea93a635d7fa37e31d10f6da74.jpg)

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# 5 Driver Installation

The cPCI-6640 drivers are available the ADLINK website (https://www.adlinktech.com/Products/CompactPCI/6UCompactPCI2.0Blades/cPCI-6640\_Series). ADLINK provides validated drivers for Windows 10 64-bit. We recommend using these drivers to ensure compatibility.

# 5.1 cPCI-6640 Drivers

The following describes the cPCI-6640 driver installation procedures for Windows 10 64-bit.

1. Install the Windows 10 operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.
2. Install the chipset driver by extracting and running the program in ...\Chipset\Intel\_Chipset\_10.1.17541.8066.zip.
3. Install the graphics driver and utilities by extracting and running the program in
...\Graphics\Intel\_Graphics\_Driver\_win64.zip.
4. Install the Intel Rapid Storage Technology Utility by extracting and running the program in ...\RST\Intel\_Rapid\_Storage\_Technology\_16.0.2.1086.zip.
5. Install the Intel® Management Engine Interface driver for Intel® AMT support by extracting and running the program in:

CM Series Chipset supporting Xeon Processors: ...\Intel\_ME\_Corporate\_12.0.3.1091.zip or

QM Series Chipset supporting i7/i5/i3/Celeron Processors ...\Intel\_ME\_Consumer\_12.0.3.1091.zip

6. Install the Intel Serial Rapid IO driver by extracting and running the program in ...\SIO\Intel\_Serial\_IO\_30.100.1727.1.zip.

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# 6 BIOS Setup Utility

The following chapter describes basic navigation for the AMI EFI BIOS setup utility.

# 6.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt; Press DEL to run Setup &gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![An icon depicting a white document with a folded upper-right corner and faint horizontal lines, featuring a large red checkmark superimposed over the center.](.cpci-6640-50m-00112-1000-10/015b27093b4b9a45bd562b52557a14b7aedaf02f5b2e4e5f66600322a15b29c2.jpg)
NOTE:

In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![**BIOS Setup Utility** points downward to **Screens**.\n\nFrom **Screens**, a row of blocks connects horizontally with double-headed arrows: **Screen 1** \$\leftrightarrow\$ **Screen 2** \$\leftrightarrow\$ **Screen 3** \$\leftrightarrow\$ **Screen 4** \$\leftrightarrow\$ **Screen 5**. A dotted arrow from **Left and Right Keys to Select a Setup Screen** points to **Screen 1**.\n\n**Screens** also points downward to the label **Items**. Below this label are two rows of square blocks containing the symbol **±**:\n\n*   **Top Row:** Three **±** squares connected by double-headed arrows.\n    *   A dotted arrow from **Tab Key to Select Fields** points to this row.\n    *   A dotted arrow from **± To Change Field Values** points to this row.\n*   **Bottom Row:** Three **±** squares connected by double-headed arrows.\n*   **Vertical Connection:** Down and Up arrows connect the top and bottom rows.\n    *   A dotted arrow from **Up and Down Keys to Select a Setup Item** points to these vertical arrows.\n*   **Fields:** The label **Fields** is on the left, connected via lines to the left side of both rows of **±** squares.](.cpci-6640-50m-00112-1000-10/6d8edd972104a9cdf1f2401bf49760eaa456926bf52faea869084b485b90d52e.jpg)

![The image displays a white document icon with a folded upper right corner and faint horizontal lines, featuring a large red checkmark overlaid on top.](.cpci-6640-50m-00112-1000-10/9435f6e729200dc008c14dd08f2a45eb91aeda080265cb248f08e1c215bbe0d0.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

→← Left/Right. The Left and Right &lt; Arrow &gt; keys allow you to select a setup screen. For example: Main screen, Advanced screen, Chipset screen, and so on.
↑↓ Up/Down The Up and Down &lt; Arrow &gt; keys allow you to select a setup item or sub-screen.
+- Plus/Minus The Plus and Minus &lt; Arrow &gt; keys allow you to change the field value of a particular setup item. For example: Date and Time.

Tab The &lt; Tab &gt; key allows you to select setup fields.

ESC The &lt;Esc&gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt;Esc&gt; key to exit the setup without saving your changes. Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

# 6.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main BIOS Setup menu is shown below.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Boot</td><td>Security</td><td>Save &amp; Exit</td><td>Server Mgmt</td></tr><tr><td>-BIOS Information-System Information-Stepping-System Date-Access Level</td><td>-CPU ▶Configuration-USB ▶Configuration-AMT ▶Configuration-Super IO ▶Configuration-Serial Console Redirection ▶-Miscellaneous-Network ▶Stack Configuration-Intel® i210 Gigabit Network Connection – [MAC address]...-Intel® i210 Gigabit Network Connection – [MAC address]</td><td>-System ▶Agent (SA) Configuration-PCH-IO ▶Configuration</td><td>-Password Description-Secure Boot Menu ▶</td><td>-Boot Configuration</td><td>-Save Options-Boot Override</td><td>-BMC Self Test Status-BMC Device ID-BMC Device Revision-BMCFirmware Revision-IPMI Version-BMCIntreface(s)</td></tr></table>

![The image displays a white document icon with the top-right corner folded down. Faint horizontal gray lines appear near the bottom of the page. A large, bold red checkmark is overlaid on the document.](.cpci-6640-50m-00112-1000-10/1b42d79054452d8a17bf534bef1afe80fab8b50dbf23f0e50d9f13a58e100daf.jpg)
NOTE:

▶ indicates a submenu
Gray text indicates info only

# 6.2.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info onlyAmerican Megatrends</td><td>Display vendor name of system BIOS</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display version of booting BIOS</td></tr><tr><td>Build Date</td><td>Info only</td><td>Date the BIOS was built</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Platform MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Platform GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Intel Management Engine Version</td></tr></table>

# 6.2.2 System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU Board Version</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display Intel CPU Brand Information</td></tr></table>

# 6.2.3 Stepping

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GT Info</td><td>Info only</td><td></td></tr><tr><td>CPU Frequency</td><td>Info only</td><td></td></tr><tr><td>Total Memory</td><td>Info only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info only</td><td></td></tr><tr><td>PCH SKU</td><td>Info only</td><td></td></tr><tr><td>Stepping</td><td>Info only</td><td></td></tr></table>

# 6.2.4 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX).</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds.</td></tr></table>

# 6.2.5 Access Level

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Access Level</td><td>Info only</td><td>Displays current user</td></tr></table>

# 6.3 Advanced

This menu contains the settings for most of the user interfaces in the system.

6.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Manufacturer, model</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU Information</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Revision</td></tr><tr><td>Speed</td><td>Info only</td><td>Display CPU Speed.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display L1 Data Cache size</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display L1 Instruction Cache size</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display L2 Data Cache size</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display L3 Data Cache size</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Display L4 Data Cache size</td></tr><tr><td>VMX</td><td>Info only</td><td></td></tr><tr><td>SMX/TXT</td><td>Info only</td><td></td></tr><tr><td>Boot performance mode</td><td>Max Battery Max Non-Turbo Performance Turbo Perfromance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled or Disabled Hyper-Threading Technology</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Intel® SpeedStepTM</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported</td></tr><tr><td>Intel® Speed Shift Technology</td><td>Disabled Enabled</td><td>Enable/Disable Intel® Speed Shift Technology support.</td></tr><tr><td>Turbo Mode</td><td>Disabled Enabled</td><td>Enable/Disable processor Turbo Mode</td></tr><tr><td>Configurable TDP Boot Mode</td><td>Nominal Deactivate</td><td>Configurable TDP Mode as Nominal/Deactivate TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero</td></tr><tr><td>Platform PL1 Enable</td><td>Disabled Enabled</td><td>When a processor thermal sensor trips (either core), the PROCHOT# will be driven. If bidirection is enabled, external agents can drive PROCHOT# to throttle the processor</td></tr><tr><td>Platform PL1 Power</td><td>0</td><td>Platform Power Limit 1 Power in Milli Watts.BIOS will round to the nearest 1/8W when programming. Any value can be programmed between Max and Min Power Limits (specified by PACKAGE_POWER_SKU_MSR). For 12.50W, enter 12500. This setting will act as the new PL1 value for the Package RAPL algorithm.</td></tr><tr><td>Platform PL1 Time Window</td><td>0</td><td>Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform TDP value should be maintained.</td></tr><tr><td>C state</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Package C State Limit</td><td>C0/C1C2C3C6C7C7SC8C9C10CPU DefaultAuto</td><td>Maximum Package C State Limit Setting.CPU Default: Leaves to Factory default value.Auto: Initializes to deepest available Package C State Limit</td></tr><tr><td>Active Processor Cores</td><td>All12345</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>Intel (VMX)Virtualization Technology</td><td>DisabledEnabled</td><td>Enable/Disable VMX capability</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>Enable/Disable VT-d capability</td></tr><tr><td>DTS SMM</td><td>DisabledEnabledCritical Temp Reporting (Out of spec)</td><td>Disabled: ACPI thermal management uses EC reported temperature values.Enabled: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.Out of Spec: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enable/Disable utilization of additional hardware capabilities provided by Intel® Trusted Execution Technology. Changes require a full power cycle to take effect.</td></tr></table>

# 6.3.2 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module version</td><td>Info only</td><td></td></tr><tr><td>USB Controllers:</td><td>Info only</td><td></td></tr><tr><td>USB Devices:</td><td>Info only</td><td>.</td></tr><tr><td>XHCI Compliance Mode</td><td>EnabledDisabled</td><td>Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications</td></tr><tr><td>xDCI Support</td><td>EnabledDisabled</td><td>Workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by XHCI driver</td></tr><tr><td>USB Port Disable Override</td><td>EnabledDisabled</td><td>Enable/Disable USB Mass Storage Driver Support</td></tr></table>

# 6.3.3 AMT Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>AMT BIOS Features</td><td>EnabledDisabled</td><td>When disabled AMT BIOS features are no longer supported and user is no longer able to access MEBx setupNote: This does not disable manageability features in firmware</td></tr><tr><td>MEBx Hotkey Pressed</td><td>DisabledEnabled</td><td>Enable it to press Ctrl+P to enter MEBx</td></tr></table>

# 6.3.4 Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT6106D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>Submenu</td><td></td></tr></table>

Super IO Management > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Change Settings</td><td>AUTOIO=3F8;IRQ=4;IO=3F8;IRQ=3,4,5,7,9,10,11,12IO=2F8;IRQ=3,4,5,7,9,10,11,12IO=3E8;IRQ=3,4,5,7,9,10,11,12IO=2E8;IRQ=3,4,5,7,9,10,11,12</td><td>Select an optimal setting for Super IO device</td></tr></table>

Super IO Management > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Change Settings</td><td>AUTOIO=3F8;IRQ=4;IO=3F8;IRQ=3,4,5,7,9,10,11,12IO=2F8;IRQ=3,4,5,7,9,10,11,12IO=3E8;IRQ=3,4,5,7,9,10,11,12IO=2E8;IRQ=3,4,5,7,9,10,11,12</td><td>Select an optimal setting for Super IO device</td></tr></table>

# 6.3.5 Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Console Redirection</td><td>Info only</td><td></td></tr><tr><td colspan="3">COM1~2</td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection enable or disable</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

# Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOdd</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareSoftware</td><td>Hardware flow control uses RTC/CTS. Software flow control uses XON/XOFF</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>Disabled Enable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>Disabled Enable</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>Disabled Enable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100 LINUX XTERMR6 SCO ESCN VT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

# 6.3.6 Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Trusted Computing</td><td>Submenu</td><td>Trusted Computing Settings</td></tr><tr><td>Network</td><td>Do not launch UEFI</td><td>Controls the execution of UEFI Network OpROM</td></tr></table>

# Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>DisabledEnabled</td><td></td></tr></table>

# 6.3.7 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>IPv4 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>IPv4 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 HTTP boot support. If disabled, IPv4 HTTP boot support will not be available.</td></tr><tr><td>IPv6 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>IPv6 HTTP Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 HTTP boot support. If disabled, IPv6 HTTP boot support will not be available.</td></tr><tr><td>IPSEC Certificate</td><td>Enabled</td><td>Support to Enable/Disable IPSEC certificate for Ikev.</td></tr><tr><td>PXE boot wait time</td><td>0</td><td>Wait time in seconds to press ESC key to abort the PXE boot.Use either +/- or numeric keys to set the value.</td></tr><tr><td>Media detect count</td><td>1</td><td>Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value.</td></tr></table>

6.3.8 Intel i210 Gigabit Network Connection - [MAC address]

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NIC Configuration</td><td>Submenu</td><td>Configure the network device port</td></tr><tr><td>Blink LEDs</td><td>0</td><td>Press “Return” key to identify the physical network port by blinking the associated LED</td></tr><tr><td>UEFI Driver</td><td>Info only</td><td></td></tr><tr><td>Adapter PBA</td><td>Info only</td><td></td></tr><tr><td>Device Name</td><td>Info only</td><td></td></tr><tr><td>Chip Type</td><td>Info only</td><td></td></tr><tr><td>PCI Device ID</td><td>Info only</td><td></td></tr><tr><td>PCI Address</td><td>Info only</td><td></td></tr><tr><td>Link Status</td><td>Info only</td><td></td></tr><tr><td>MAC Address</td><td>Info only</td><td></td></tr><tr><td>Virtual MAC address</td><td>Info only</td><td></td></tr></table>

NIC Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Link Speed</td><td>Auto Negotiated10 Mbps Half10 Mbps Full100 Mbps Half100 Mbps Full</td><td></td></tr><tr><td>Wake on LAN</td><td>DisabledEnabled</td><td></td></tr></table>

# 6.4 Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>Submenu</td><td>System Agent (SA) Parameters</td></tr><tr><td>PCH-IO Configuration</td><td>Submenu</td><td>PCH parameters</td></tr></table>

# 6.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info only</td><td>Displays SA PCIe code revision</td></tr><tr><td>VT-d</td><td>Info only</td><td>Displays VT-d supported or not</td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td>Memory parameters</td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td>Graphics parameters</td></tr><tr><td>PEG Port Configuration</td><td>Submenu</td><td>PEG port parameters</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>EnabledDisabled</td><td>Enable/Disable above 4GB memory mapped BIOS assignment.</td></tr></table>

# Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display RC version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency</td></tr><tr><td>Memory Voltage</td><td>Info only</td><td>Display memory voltage</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Display memory timing parameters</td></tr><tr><td>Channel 0 Slot 0</td><td>Info only</td><td>Display memory Size</td></tr><tr><td>Channel 1 Slot 0</td><td>Info only</td><td>Display memory Size</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067, 1200..., 6200</td><td>Maximum memory frequency selections in MHz. Valid values should match the refclk, i.e. divided by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB, 1.25GB...3.5GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller.</td></tr></table>

Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>DisabledEnabled</td><td>If Enabled, it will not scan for External Gfx card on PEG and PCH PCIE ports</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIe</td><td>Select which IGFX/PEG/PCI Graphics device should be Primary Display.</td></tr><tr><td>Select PCIe Card</td><td>AutoElk Creek 4PEG Eval</td><td>Select the card used on the platformAuto: Skip GPIO based power enable to dGPU Elk Creek 4: dGPU Power Enable = ActiveLow PEG Eval: dGPU Power Enable = ActiveHigh</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture SizeNote: Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM support.</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M64M4M8M12M16M20M24M28M32M/F736M40M44M48M52M56M60M</td><td>Select DVMT 5.0 pre-allocated (fixed) graphics memory size used by the internal graphics device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMax</td><td>Select DVMT5.0 total graphics memory used by the internal graphics device.</td></tr></table>

PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG 0:1:0 / 0:1:1 / 0:1:2 / 0:6:0</td><td>Info only</td><td></td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or disable this root port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:0 max speed</td></tr><tr><td>PEG0 Slot Power Limit Value</td><td>Info only</td><td></td></tr><tr><td>PEG0 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG0 Physical Slot Number</td><td>Info only</td><td></td></tr><tr><td colspan="3"></td></tr><tr><td>Gen3 RxCTLE Control</td><td>Submenu</td><td></td></tr><tr><td>PCIe Rx CEM Test Mode</td><td>DisabledEnabled</td><td>Enable/Disable PEG Rx CEM Loopback Mode</td></tr><tr><td>PCIe Spread Spectrum Clocking</td><td>EnabledDisabled</td><td>Allows disabling Spread Spectrum Clocking for compliance testing</td></tr></table>

Gen3 RxCTLE Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Bundle0</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle0 (Lane0, Lane1)</td></tr><tr><td>Bundle1</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle1 (Lane2, Lane3)</td></tr><tr><td>Bundle2</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle2 (Lane4, Lane5)</td></tr><tr><td>Bundle3</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle3 (Lane6, Lane7)</td></tr><tr><td>Bundle4</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle4 (Lane8, Lane9)</td></tr><tr><td>Bundle5</td><td>[Max-Value, Min-Value, Step-Value] = [0x0F, 0x00, 0x01]</td><td>Gen3 RxCTLE setting for Bundle5 (Lane10, Lane11)</td></tr><tr><td>Bundle6</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle6 (Lane12, Lane13)</td></tr><tr><td>Bundle7</td><td>Info only</td><td>Gen3 RxCTLE setting for Bundle7 (Lane14, Lane15)</td></tr><tr><td>PEG10 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG0 RxCTLE adaptive behaviour</td></tr><tr><td>PEG11 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG1 RxCTLE adaptive behavior</td></tr><tr><td>PEG12 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG2 RxCTLE adaptive behavior</td></tr><tr><td>DMI RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides DMI RxCTLE adaptive behavior</td></tr></table>

6.4.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuraiton</td><td>Submenu</td><td>Configure Serial IRQ Mode.</td></tr><tr><td>SATA And RST Configuration</td><td>Submenu</td><td>Enable/Disable SMBus Support.</td></tr><tr><td>SerialIO Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCH LAN Controller</td><td>EnabledDisabled</td><td>Enable/Disable onboard NIC</td></tr><tr><td>Wake on LAN For S5 Enable</td><td>EnabledDisabled</td><td>Enable/Disable integrated LAN to wake the system only for S5.</td></tr><tr><td>Serial IRQ Mode</td><td>QuietContinuous</td><td>Configure Serial IRQ Mode</td></tr><tr><td>High Precision Timer</td><td>EnabledDisabled</td><td>Enable or Disable the High Precision Event Timer</td></tr><tr><td>PCIE PLL SSC</td><td>Auto0.0%~2.0%</td><td>PCIe PLL SSC percentage. Auto – Keep HW default, no BIOS override. Range is 0.0%-2.0%</td></tr><tr><td>SPD Write Disable</td><td>TrueFalse</td><td>Enable/Disable setting SPD write disable. For security recommendations, SPD write disable bit must be set.</td></tr><tr><td>State After G3</td><td>Info only</td><td></td></tr></table>

PCIe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Configuration</td><td colspan="2">Info only</td></tr><tr><td>PCI Express Clock Gating</td><td>DisabledEnabled</td><td>PCI Express Clock Gating Enable/Disable for each root port</td></tr><tr><td>DMI Link ASPM Control</td><td>DisabledL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link</td></tr><tr><td>PCIE Port assigned to LAN</td><td>Info only</td><td></td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td>Enable when using Compliance Load Board</td></tr><tr><td>PCIe-USB Glitch W/A</td><td>DisabledEnabled</td><td>PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG port.</td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td>When Disabled, prevents PCIE root port function swap. If any function other than  $0^{th}$  is enabled,  $0^{th}$  will become visible.</td></tr><tr><td>PCIe Root Port X</td><td>Submenu</td><td></td></tr></table>

PCIe Configuration > PCIe Root PortX

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Root PortX</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in Slot</td><td>Built-In: a built-in device is connected to this root port. Slot Implemented bit will be clear.Slot: this root port connects to user-accessible slot. Slot Implemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisableL0sL1L0sL1Auto</td><td>Set the ASPM Level:Force L0s – Force all inks to L0s StateAuto – BIOS auto configureDisable – Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 substates settings.</td></tr><tr><td>Gen3 Eq Phase3 Method</td><td>HardwareStatic Coeff.</td><td>PCIe Gens3 Equalization Phase 3 Method</td></tr><tr><td>UPTP</td><td>Info only</td><td>Upstream Port Transmitter Preset</td></tr><tr><td>DPTP</td><td>Info only</td><td>Downstream Port Transmitter Preset</td></tr><tr><td>ACS</td><td>EnabledDisabled</td><td>Enable/Disable Access Control ServicesExtended Capability</td></tr><tr><td>PTM</td><td>EnabledDisabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>EnabledDisabled</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>EnabledDisabled</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>EnabledDisabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>EnabledDisabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>EnabledDisabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable</td></tr><tr><td>CER</td><td>EnabledDisabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable</td></tr><tr><td>CTO</td><td>EnabledDisabled</td><td>PCI Express Completion Timer TO Enable/Disable.</td></tr><tr><td>SEFE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable</td></tr><tr><td>SENFE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>EnabledDisabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable</td></tr><tr><td>PME SCI</td><td>EnabledDisabled</td><td>PCI Express PME SCI Enable/Disable</td></tr><tr><td>Hot Plug</td><td>EnabledDisabled</td><td>PCI Express Hot Plug Enable/Disable</td></tr><tr><td>Advanced Error Reporting</td><td>EnabledDisabled</td><td>Advanced Error Reporting Enable/Disable</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable</td></tr><tr><td>Detect Timeout</td><td>Info only</td><td>The number of milliseconds reference code will wait for link to exit Detect State for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>Info only</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge</td></tr><tr><td>Reserved Memory</td><td>Info only</td><td>Resreved Memory for this Root Bridge (1-20) MB</td></tr><tr><td>Reserved I/O</td><td>Info only</td><td>Reserved I/O (4K/8K/12K/16K/20K) range for this root bridge</td></tr><tr><td colspan="3">PCH PCIe LTR Configuration</td></tr><tr><td>LTR</td><td>EnabledDisabled</td><td>PCH PCIE Latency Reporting</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override. Manual: Manually enter override values. Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Force LTR Override</td><td>DisabledEnabled</td><td>Force LTR Override for PCH PCIE.</td></tr><tr><td>LRT Lock</td><td>DisabledEnabled</td><td>PCIE LTR configuration lock</td></tr></table>

SATA And RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA And RST Configuration</td><td colspan="2">Info only</td></tr><tr><td>SATA Controller(s)</td><td>DisabledEnabled</td><td>Enable/Disable SATA Device</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST PremiumWith Intel OptaneSystem Acceleration</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back)</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td></td></tr><tr><td>Aggressive LPM Support</td><td>EnabledDisabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support</td></tr><tr><td>Serial ATA Port X, X = 0-7</td><td colspan="2">Info only</td></tr><tr><td>Software Preserve</td><td colspan="2">Info only</td></tr><tr><td>Port X</td><td>EnabledDisabled</td><td>Enable or Disable SATA Port.</td></tr><tr><td>Hot Plug</td><td>EnabledDisabled</td><td>Designates this port as Hot Pluggable</td></tr><tr><td>Configured as eSATA</td><td colspan="2">Info only</td></tr><tr><td>External</td><td>EnabledDisabled</td><td>Marks this port as external</td></tr><tr><td>Spin Up Device</td><td>Disabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to solid state drive or hard disk drive</td></tr><tr><td>SATA Port X DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port X DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>DTTO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO configuration</td></tr><tr><td>DITO Value</td><td>Info only</td><td>Display DITO value</td></tr><tr><td>DM Value</td><td>Info only</td><td>Display DM value</td></tr></table>

SATA And RST Configuration > Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HDD Unlock</td><td>DisabledEnabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>DisabledEnabled</td><td>If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.</td></tr></table>

Serial IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C0 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Serial IO Controller</td></tr><tr><td>I2C1 Controller</td><td>DisabledEnabled</td><td>Enables/Disables Serial IO Controller</td></tr></table>

# 6.5 Security

# 6.5.1 Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Configure/Clear Administrator Password. When pressing enter, a menu will be popped up for creating new password. When password installed, press enter without inputting password, it will clear password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Configure/Clear User Password. When pressing enter, a menu will be popped up for creating new password. When password installed, press enter without inputting password, it will clear password</td></tr><tr><td>Secure Boot Menu</td><td>Submenu</td><td></td></tr></table>

# Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td>Show Secure Boot status.</td></tr><tr><td>Secure Boot Control</td><td>DisabledEnabled</td><td>Secure Boot can be enabled if:1. System running in User mode with enrolled Platform Key (PK)2. CSM function is disabled.</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode options:If Custom mode, Secure Boot Policy variables can be configured by a physically present user without full authentication.</td></tr></table>

# 6.6 Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard NumLock state after system boot.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enabled: will show splash screen during POST. Disabled: will show boot message during POST.</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enable or disabled Fast boot feature. Most probes are skipped to reduce time cost during boot.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices Only All SATA Devices</td><td>If Last Boot SATA Devices Only, Only last boot SATA device will be available in Post. If All SATA Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>VGA Support</td><td>Auto EFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo will NOT be shown during post. EFI driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>Disabled Full Initial Partial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Deivces Support</td><td>Disabled Enabled</td><td>If Disabled, PS2 devices will be skipped.</td></tr><tr><td>Network Stack Driver Support</td><td>Disabled Enabled</td><td>If Disabled, Network Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>Disabled Enabled</td><td>If disable, Redirection function will be disabled.</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr></table>

# 6.7 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Reset</td><td>Save changes and reset the system.</td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system without saving any changes.</td><td>Exit system setup without saving the changes.</td></tr><tr><td>Save Changes and Reset</td><td>Reset the system with saving any changes.</td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system and discard any changes.</td><td>Reset the system after without the changes.</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Default</td><td></td><td>Restore/Load the Default values for all the setup options.</td></tr><tr><td>Save as User Default</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Default</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr><tr><td>UEFI: Built-in EFI Shell</td><td></td><td></td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td></td></tr></table>

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# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:
▷ Turn off power and unplug any power cords/cables.
▶ To avoid electrical shock and/or damage to equipment:
▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);
▶ Make sure to use recommended voltage and power source settings;
▶ Always install and operate equipment near an easily accessible electrical socket-outlet;
▷ Secure the power cord (do not place any object on/over the power cord);
▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard safety warning symbol. It features a red triangle with rounded corners containing a large white exclamation point in the center. Directly below the triangle, the word 'WARNING' is printed in black capital letters.](.cpci-6640-50m-00112-1000-10/d309725a29bae7b214b0b255bf1c569f5f63b82749b9130c94aca6a675674855.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.cpci-6640-50m-00112-1000-10/cpci-6640-50m-00112-1000-10.pdf)