# cPCI-6870 Series

Low Power 6U CompactPCI Processor Blade with Mobile Intel® GS45 Express Chipset

# User's Manual

![Green printed circuit board with various components and connectors, no visible text or symbols](.cpci-6870-50-15069-1010-201-en/1faae49fc06dc6623d6d947be3bcf832eb6eb4f4395851e16979425fedf14ca0.jpg)

Manual Rev. 2.01

Revision Date: August 30, 2011

Part No: 50-15069-1010

![Circular black-and-white recycling symbol with three white arrows forming a triangle (no text or symbols)](.cpci-6870-50-15069-1010-201-en/7b29e99aa855a7d909636e8ced3fc588c859d52a8445d20f2098abc7493b225c.jpg)

Recycled Paper

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2010/11/09</td><td>Initial Release</td></tr><tr><td>2.01</td><td>2011/08/30</td><td>Remove VGA function from the RJ-45 connector on the front panel for models with ordering numbers ending in “xx30” and higher; SCSI and floppy not supported on current model RTMs; add SW6 description; update addresses</td></tr></table>

# Preface

# Copyright 2010-2011 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Using this Manual

# Audience and Scope

The cPCI-6870 User's Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating industrial grade CompactPCI modules.

# Manual Organization

This manual is organized as follows:

Chapter 1, Overview: Introduces the cPCI-6870, its features, block diagrams, and package contents.

Chapter 2, Specifications: Presents detailed specification information, and power consumption.

Chapter 3, Functional Description: Describes the cPCI-6870's main functions.

Chapter 4, Board Interfaces: Describes the cPCI-6870 board interfaces, pin definitions, and jumper settings.

Chapter 5, Getting Started: Describes the installation instructions of the cPCI-6870.

Chapter 6, Driver Installation: Describes the driver installation procedures.

Chapter 7, Utilities: Describes the Watchdog Timer and Preboot Execution Environment functions.

Chapter 8, BIOS Setup Utility: Describes the AMIBIOS®8 BIOS setup utility.

Chapter 9, IPMI User Guide: Provides relevant information for the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI).

Important Safety Instructions: Presents safety instructions all users must follow for the proper setup, installation and usage of equipment and/or software.

Getting Service: Contact information for ADLINK's worldwide offices.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![This image is an icon depicting a white sheet of paper with a folded upper-right corner. Faint horizontal lines run across the page, resembling a form or lined paper. A large red checkmark is prominently displayed in the center of the document.](.cpci-6870-50-15069-1010-201-en/c8abd36eacfa57f7be4bd40defeffa5b5d079c83cd35c44398c496b6cd5d9678.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![This is a cropped image showing the upper portion of a standard yellow triangular warning sign. It has a thick black border and features a large black exclamation mark centered within the yellow background.](.cpci-6870-50-15069-1010-201-en/dcfcc45adf4a3a60949a5b708dcf9bf7c710527358b82654be4c921eb8186e56.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning sign featuring a red triangle with a white border. Inside the triangle is a large white exclamation mark centered in the middle.](.cpci-6870-50-15069-1010-201-en/13cd2a95465903944958db33b649ffed7d7663744fb90395d4983d97369869ea.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

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# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Tables.... xi

# List of Figures ...... xiii

# 1 Overview .... 1

1.1 Introduction.... 1
1.2 Features.... 2
1.3 Block Diagram 3
1.4 Product List.... 4
1.5 Package Contents 5

# 2 Specifications.... 7

2.1 cPCI-6870 SBC Specifications 7
2.2 I/O Connectivity Tables.... 10
2.3 Power Requirements 13

# 3 Functional Description 15

3.1 CPU 15
3.2 Chipset.... 17
3.3 Super I/O 20
3.4 Battery 20
3.5 PMC/XMC Sites 20

# 4 Board Interfaces.... 21

4.1 cPCI-6870 SBC Board Layout 21
4.2 cPCI-6870 SBC Front Panel 22
4.3 Connector Pin Assignments 23
4.4 Switch and Jumper Settings 42

# 5 Getting Started 47

5.1 Memory Module Installation 47
5.2 Hard Drive Installation.... 48
5.3 CompactFlash Card Installation.... 52
5.4 Installing the cPCI-6870 SBC to the Chassis.... 53
5.5 Installing the RTM to the Chassis 54

# 6 Driver Installation.... 55

6.1 Driver Installation Procedure.... 55
6.2 SCSI Driver 56

# 7 Utilities....57

7.1 Watchdog Timer.... 57
7.2 Preboot Execution Environment (PXE).... 62

# 8 BIOS Setup Utility 63

8.1 Starting the BIOS 63
8.2 Main Setup.... 67
8.3 Advanced BIOS Setup 68
8.4 Advanced PCI/PnP Settings 77
8.5 Boot Settings 78
8.6 Security Setup.... 81
8.7 Chipset Setup 84
8.8 Exit Menu 88

# 9 IPMI User Guide 91

9.1 Introduction 91
9.2 Summary of Commands Supported by BMR-AVR-cPCI ... 91
9.3 OEM Commands Summary Table 95
9.4 CompactPCI Address Map 99
9.5 Communications with IPMC.... 100
9.6 IPMI Sensors List.... 100
9.7 Relevant Documents.... 100

Important Safety Instructions.... 101

Getting Service.... 103

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# List of Tables

Table 2-1: SBC I/O Connectivity ...... 10

Table 2-2: RTM I/O Connectivity (pt. 1) 11

Table 2-3: RTM I/O Connectivity (pt. 2) 12

Table 2-4: CompactPCI Input Voltage Characteristics ..... 13

Table 2-5: Idle Mode Power Consumption 14

Table 2-6: 100% CPU Usage Power Consumption 14

Table 4-1: cPCI-6870 Front Panel Status LED Descriptions ... 22

Table 4-2: USB Connector Pin Definition 23

Table 4-3: RJ-45 Serial/VGA Port Pin Definition 23

Table 4-4: PS/2 Keyboard/Mouse Connector Pin Definition .... 24

Table 4-5: GbE Connector Pin Definitions 24

Table 4-6: GbE LED CN12 Status Definitions 24

Table 4-7: COM1-2 Serial Port Connector Pin Definition ..... 25

Table 4-8: Onboard Serial Port Connector Pin Definition ..... 25

Table 4-9: SATA Connector Pin Definition 26

Table 4-10: DB-6920SAT SATA Connector Pin Definition ..... 26

Table 4-11: PMC Connector Pin Definitions 27

Table 4-12: XMC Connector Pin Definition 29

Table 4-13: 68-pin SCSI Connector Pin Definition 30

Table 4-14: Floppy Connector Pin Definition 31

Table 4-15: PIM Connector (JN1-R) Pin Definition 32

Table 4-16: PIM Connector (JN2-R) Pin Definition 33

Table 4-17: CompactFlash Connector Pin Definition ..... 34

Table 4-18: DB-6920SAT/CF Connector Pin Definition .... 35

Table 4-19: DB-R6000L2 Connector Pin Definition 36

Table 4-20: CompactPCI J1 Connector Pin Definition ...... 37

Table 4-21: CompactPCI J2 Connector Pin Definition ...... 38

Table 4-22: CompactPCI J3 Connector Pin Definition ...... 39

Table 4-23: CompactPCI J4 Connector Pin Definition ...... 40

Table 4-24: CompactPCI J5 Connector Pin Definition ...... 41

Table 4-25: Mode Switch Settings 42

Table 4-26: PMC Clock Switch Settings 43

Table 4-27: PMC V(I/O) Switch Settings 43

Table 4-28: COM1/Debug Switch Settings 44

Table 4-29: Front/Rear VGA Selection Switch Settings ...... 44

Table 4-30: COM/VGA Mode Selection Switch Settings ..... 45

Table 4-31: PICMG 2.16 Switch Settings 46

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# List of Figures

Figure 1-1: cPCI-6870 Series Block Diagram.... 3

Figure 4-1: cPCI-6870 SBC Board Layout.... 21

Figure 4-2: cPCI-6870 Series Front Panel Layout.... 22

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# 1 Overview

# 1.1 Introduction

The cPCI-6870 Series is a 6U CompactPCI single board computer in single slot (4HP) width form factor featuring a low power, small form factor mobile Intel® chipset and supporting 45nm process Core™2 Duo and Celeron® processors. The cPCI-6870 provides up to 8GB dual channel DDR3-800/1066 memory capacity and implements the Mobile Intel® GS45 Graphics and Memory Controller Hub and ICH9M-SFF I/O Controller Hub to provide a full feature set and optimal performance.

The cPCI-6870 Series supports a 64bit/66MHz CompactPCI bus, two PMC sites with 64-bit/66MHz PCI bus or two PCI-Express x8 XMC sites, four PCI-Express Gigabit Ethernet ports (two on front panel, two for PICMG 2.16), a SATA connector for an onboard 2.5" SATA HDD, and CompactFlash socket support via the Rear Transition Module (RTM). For flexibility of use, the cPCI-6870 Series can be installed in a standard CompactPCI system slot as system master, or peripheral slot as a PCI device. The cPCI-6870 Series is ideally suited for factory automation, transportation and military applications.

# 1.2 Features

▶ 6U CompactPCI SBC in 4HP width form factor
- μFC-BGA package Intel® CoreTM2 Duo or Celeron® processor, up to 2.26GHz
▶ 1066/800/667 MHz Front Side Bus depending on processor
▶ Mobile Intel® GS45 Memory Controller Hub and ICH9M-SFF I/O Hub
▶ Dual Channel DDR3 non-ECC SDRAM at 800 or 1066MHz via two SO-DIMM sockets, up to 8GB
▶ 64-bit/66MHz CompactPCI Interface based on PCI specifications, 3.3V and 5V signaling
▶ Supports operation in system slot as system master or in peripheral slot with connectivity to CompactPCI bus (optional isolation from CompactPCI bus)
▶ Dual PMC sites with 64-bit/133MHz PCI bus
▶ Dual XMC sites with PCI-Express x8 lane
▶ Four PCI-Express® Gigabit Ethernet ports, two at front, two for PICMG 2.16
▶ Onboard CompactFlash socket
▶ 2.5" SATA HDD direct connector onboard, occupies outer PMC/ XMC site
▶ Optional -20°C to 70°C extended temperature support
▶ RTM models available with multiple I/O options: SATA, HD audio, COM, USB, Gigabit Ethernet, PS/2 KB/MS, PIM, SAS, CF, SD socket
▶ Hardware RAID on SATA, SAS interfaces supported (dependent on RTM module)

# 1.3 Block Diagram

![**Blocks:**\n*   Front Panel\n*   Intel® Core™2 Duo Celeron®\n*   PCIe to PCI Bridge\n*   PCIe Switch\n*   PMC2/XMC2\n*   PMC1/XMC1\n*   2.5' SATA HDD\n*   CF\n*   Intel® GS45 GMCH\n*   DDR3 800/1066 SO-DIMM (top)\n*   DDR3 800/1066 SO-DIMM (bottom)\n*   Intel® ICH9M-SFF Enhanced\n*   Intel® 82574L (top right)\n*   Intel® 82574L (bottom right)\n*   BIOS (left)\n*   BIOS (right)\n*   Intel® 82574L (left)\n*   Intel® 82574LL\n*   Pericom PI7C9X130\n*   Super I/O ITE8783\n*   IPMI BMC\n*   RTM\n*   J2\n*   J1\n\n**Connections:**\n*   **Intel® Core™2 Duo Celeron®** connects to **Intel® GS45 GMCH** via **FSB 667/800/1066MHz**.\n*   **Intel® Core™2 Duo Celeron®** connects to **RTM** via **VGA*, PS/2, COM3/4, FDD**, PIM, PCIe x4** (dashed).\n*   **Intel® GS45 GMCH** connects to **DDR3 800/1066 SO-DIMM** (top and bottom).\n*   **Intel® GS45 GMCH** connects to **RTM** via **LVDS**.\n*   **Intel® GS45 GMCH** connects to **PCIe Switch** via **PCIe x8**.\n*   **Intel® GS45 GMCH** connects to **PCIe to PCI Bridge** via **PCIe x4**.\n*   **PCIe Switch** connects to **PMC1/XMC1** via **PCIe x8**.\n*   **PCIe Switch** connects to **RTM** via **PCIe x4** (dashed).\n*   **PCIe to PCI Bridge** connects to **Front Panel** via **VGA*** (dashed).\n*   **PCIe to PCI Bridge** connects to **PMC1/XMC1** via **PCI-X 64b/133M**.\n*   **PMC2/XMC2** connects via **PIM** (dashed).\n*   **PMC1/XMC1** connects to **ICH9M-SFF Enhanced** via **SATA0**.\n*   **2.5' SATA HDD** connects to **PMC1/XMC1**.\n*   **CF** connects to **ICH9M-SFF Enhanced** via **SATA1**.\n*   **Front Panel** connects to **ICH9M-SFF Enhanced** via **USB1/2**.\n*   **ICH9M-SFF Enhanced** connects to **Intel® 82574L** (top right) and **Intel® 82574L** (bottom right) via **PCIe x1**.\n*   **Intel® 82574L** (top right and bottom right) connects to **RTM** via **2.16 GbE (2x)**.\n*   **ICH9M-SFF Enhanced** connects to **RTM** via **SATA2/3, USB (6x), HDA**.\n*   **ICH9M-SFF Enhanced** connects to **BIOS** (left and right) via **SPI**.\n*   **ICH9M-SFF Enhanced** connects to **Intel® 82574L** (left) via **PCIe x1**.\n*   **Intel® 82574L** (left) connects to **Front Panel** via **GbE1**.\n*   **ICH9M-SFF Enhanced** connects to **Intel® 82574LL** via **PCIe x1**.\n*   **Intel® 82574LL** connects to **Front Panel** via **GbE2**.\n*   **ICH9M-SFF Enhanced** connects to **Pericom PI7C9X130** via **PCIe x2**.\n*   **Pericom PI7C9X130** connects to **J2** via **PCI 64b/66M**.\n*   **ICH9M-SFF Enhanced** connects to **Super I/O ITE8783** via **LPC**.\n*   **Super I/O ITE8783** connects to **Front Panel** via **COM1** and **Status LEDs**.\n*   **Super I/O ITE8783** connects to **J1** via **KB/MS, FDD, COM3/4** (dashed).\n*   **Super I/O ITE8783** connects to **IPMI BMC** via **COM2**.\n*   **IPMI BMC** connects to **J1** via **IPMB0/1**.](.cpci-6870-50-15069-1010-201-en/e4481e22cbfa5428883ad8ab9666d4095cd3ceef600c9d2f82b70525f539fff2.jpg)

Figure 1-1: cPCI-6870 Series Block Diagram

![The image displays a white document icon with a folded top-right corner. Faint horizontal gray lines run across the lower portion of the paper, resembling text. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6870-50-15069-1010-201-en/4f7c7c7acea1459006187c21034da82a6a29d52ea29637f2d07edfce9148e105.jpg)
NOTE:

\*VGA is not supported on the front panel of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM and the front panel RJ-45 connector is a dedicated serial port.

\*\*Floppy support is not available on current model RTMs.

# 1.4 Product List

Products included in the cPCI-6870 Series include:

# Processor Blade

▶ cPCI-6870: 4HP width (single-slot) 6U CompactPCI blade featuring single Intel® Core™2 Duo or Celeron® processor, dual channel DDR3-800/1066 SDRAM via two SO-DIMM sockets, two PMC/XMC sites, 2x USB, 2x GbE, RJ-45 COM/VGA\*, SATA, and CF socket

![The image displays a digital icon of a white document or page with a folded top-right corner. Faint gray horizontal lines run across the page, simulating text. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6870-50-15069-1010-201-en/d393cd59eeaf234ca01622be5a210fd10a9f7d582957a01c14a6696518a34554.jpg)
NOTE:

\*VGA is not supported on the front panel RJ-45 connector of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM and the RJ-45 connector is a dedicated serial port.

# Rear Transition Modules

▶ cPCI-R6001P: 4HP width RTM with VGA, 2x COM, 3x USB, 2x GbE, PIM, SATA
▶ cPCI-R6002: 4HP width RTM with VGA, 2x COM, 3x USB, 2x GbE, SATA
▶ cPCI-R6002D: 8HP width RTM with VGA, 2x COM, 3x USB, 2x GbE, SATA, DB-R6000L2 riser card provides 2x USB, KB/MS, Mic-in, Line-out and removable SATA direct connector (DB-6920SAT) for 2.5" SATA HDD
▶ cPCI-R6101: 4HP width RTM with 4x GbE, 4x USB, SATA, VGA, PS/2 KB/MS, CF & SD sockets
▶ cPCI-R6111: 4HP width RTM with 2x GbE, 4x USB, SATA, VGA, PS/2 KB/MS, CF, & SD sockets
▶ cPCI-R6201: 8HP width RTM with 2x GbE, 4x USB, 2x COM, VGA, 2x SATA, Mic-in, Line-out, PS/2 KB/MS, 8x SAS

# Adapter Kit

▶ DB-CF-SA: CompactFlash socket kit for cPCI-R6001D & cPCI-R6201 RTMs, including DB-6920CF adapter board, card guide and screws to replace SATA adapter with CompactFlash socket

# 1.5 Package Contents

The cPCI-6870 is packaged with the components listed below (RTMs and adapter kits are optional). If any of the items in the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of non-standard configurations may vary depending on customer requests.

# Processor Blade

▶ The cPCI-6870 Series Processor Blade
▷ CPU, RAM will differ depending on options selected
▶ Thermal module is assembled on the board
▶ RJ-45 to DB-9 cable for RJ-45 COM port
▶ RJ-45 to DB-15 cable for RJ-45 VGA port
(Not included with ordering numbers ending in "xx30" and higher.)
▶ DB-6920SAT SATA adapter card
▶ 2.5" SATA HDD mounting kit, including HDD bracket and screws for HDD
▶ ADLINK All-in-One CD
▶ User's manual

# Rear Transition Module

The cPCI-R6001P, cPCI-R6002(D) $^{*}$ , cPCI-R6101, cPCI-R6111 or cPCI-R6201 RTM

\*Replaces cPCI-R6001(D).

▶ The DB-SATA kit (cPCI-R6002D, cPCI-R6111, cPCI-R6201 only)

▶ 2.5" HDD bracket (cPCI-R6002D, cPCI-R6201 only)

▶ Y-cable for PS/2 combo port (cPCI-R6002D, cPCI-R6101, cPCI-R6111, cPCI-R6201 only)

▶ DVI to VGA (DB-15) adapter (cPCI-R6002, cPCI-R6001P, cPCI-R6002D, cPCI-R6201 only)

# Adapter Kit

The DB-CF-SA kit (for cPCI-R6002D, cPCI-R6201 RTM)

▷ DB-6920CF adapter board
▷ Screw pack
▷ CF card guide

![A white document icon with horizontal lines and a folded top-left corner, featuring a large red checkmark.](.cpci-6870-50-15069-1010-201-en/cb439d5f1935cd05567621777e7c26a60144588bada8d459d27aa671acad8ed9.jpg)
NOTE:

The contents of non-standard cPCI-6870 configurations may vary depending on customer requests.

![A yellow triangular warning sign with a black border containing a large black exclamation point in the center.](.cpci-6870-50-15069-1010-201-en/0a77d4d41c051842c3c23a7606c12a40f45ee5f6874581dcad3b09b08b281d1a.jpg)
CAUTION:

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

2.1 cPCI-6870 SBC Specifications

<table><tr><td>CompactPCI Standard</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev.2.0PICMG® 2.9 System Management Bus Rev. 1.0PICMG® 2.16 Packet Switching Backplane Rev.1.0</td></tr><tr><td rowspan="4">Mechanical</td><td>Standard 6U CompactPCI®</td></tr><tr><td>Board size: 233.23 mm x 160mm</td></tr><tr><td>Single slot (4HP, 20.32mm) width</td></tr><tr><td>CompactPCI® connectors J1, J2, J3, J4 and J5 for cPCI-6870</td></tr><tr><td rowspan="4">Processor</td><td>μFC-BGA Intel® CoreTM2 Duo processor SP9300, 6MB L2 cache, 2.26GHz, 1066MHz FSB</td></tr><tr><td>μFC-BGA LV Intel® CoreTM2 Duo processor SL9400, 6MB L2 cache, 1.86GHz, 1066MHz FSB</td></tr><tr><td>μFC-BGA ULV Intel® CoreTM2 Duo processor SU9300, 3MB L2 cache, 1.2GHz, 800MHz FSB</td></tr><tr><td>μFC-BGA Intel® Celeron® processor ULV 723, 1MB L2 cache, 1.2GHz, 800MHz FSB</td></tr><tr><td>Chipset</td><td>Intel® GS45 Graphics Memory Controller Hub (GMCH)Intel® I/O Controller Hub 9M Enhanced (Intel ICH9M-Enhanced)SFF</td></tr><tr><td>Memory</td><td>Dual channel DDR3-800/1066 SDRAMTwo SO-DIMM socketsMaximum 8GB capacity</td></tr><tr><td>CompactPCI Bus</td><td>PCI 64-bit/ 66MHz; V(I/O) 3.3V and 5V signalingSupports operation in system slot or in peripheral slot withconnectivity to CompactPCI bus (Universal Mode)</td></tr><tr><td>PMC/XMC</td><td>Two PCI 64-bit/133MHz PMC sites, V(I/O) 3.3V or 5VOr two PCI-Express x8 XMC sites</td></tr><tr><td>Ethernet</td><td>Four PCI-Express® x1 Intel® 82574L GbE controllersTwo 10/100/1000BASE-T egress portsTwo 10/100/1000BASE-T ports on rear panel, optional PICMG 2.16 support by switch selection</td></tr><tr><td>Graphics</td><td>Integrated in Intel® GS45 Express Chipset (GMCH)Intel® Gen 5.0 integrated graphics engineIntel® Dynamic Video Memory Technology (Intel® DVMT 5.0)Microsoft® Direct X 10 supportAnalog RGB signal to front or rear by switch selection $^{3}$  VGA port on front panel via RJ-45 to DB-15 adapter cable $^{3}$ (shared with RJ-45 COM port)Analog RGB up to QXGA</td></tr><tr><td>Serial Ports</td><td>One 16C550 compatible RJ-45 RS-232 port on front panel (shared with RJ-45 VGA port) $^{3}$ Two serial ports routed to rear I/O</td></tr><tr><td rowspan="2">Storage Interfaces</td><td>2.5” SATA HDD direct connector onboard</td></tr><tr><td>CompactFlash Type II socket onboard $^{1}$ </td></tr><tr><td>BIOS</td><td>AMIBIOS®8, dual 16Mbit SPI flash memory, supports failover</td></tr><tr><td>IPMI Interface</td><td>Supports PICMG® 2.9 secondary system management bus IPMI functions implemented as defined by IPMI Spec. v1.5; ATmega128L-8AU Baseboard Management Controller (BMC) with 128KB programmable in-system flash, 4KB EEPROM, and 4KB internal SDRAM</td></tr><tr><td>Faceplate I/O</td><td>2x USB 2.0 ports2x 10/100/1000BASE-T Ethernet portsRJ-45 serial port or VGA port $^{3}$ 2x PMC/XMC slots</td></tr><tr><td>Onboard Peripherals</td><td>Serial ATA connector (signal + power)CompactFlash socket</td></tr><tr><td>Supported OS</td><td>Red Hat Enterprise 5.1 x86_64Red Hat Enterprise Linux 5.1 i386Microsoft® Windows® 7 x86 EditionMicrosoft® Windows® Server 2008 x64 Edition (Intel does not provide INF and graphics driver)Microsoft® Windows® Server 2003 32-bit Edition (Intel does not provide graphics driver)Microsoft® Windows® Vista x64 Edition (Intel does not provide graphics driver)Microsoft® Windows® XP Professional SP3 32-bit EditionMicrosoft® Windows® 2000 Professional SP4Other OS support upon request</td></tr><tr><td>Operating Temperature $^{1}$ </td><td>0°C to 60°C standard-20°C to 70°C extended temperature (optional)</td></tr><tr><td>Storage Temperature</td><td>-40°C to 85°C</td></tr><tr><td>Humidity</td><td>20% to 95% non-condensing</td></tr><tr><td>Shock</td><td>15G peak-to-peak, 11ms duration, non-operating</td></tr><tr><td>Vibration $^{2}$ </td><td>Operating: 2Grms. 5 to 500Hz, each axis (without HDD)</td></tr><tr><td>Compliance</td><td>CE EN55022, FCC Class A</td></tr></table>

# Notes:

1. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Forced airflow with 6 CFM is required to allow safe operation of the CPU at full loading. Temperature limit of optional mass storage devices may affect the thermal specification.
2. The hard drive limits the operational vibration tolerance. When application requires higher specification for anti-vibration, it is recommended to use a solid state drive (SSD) or Compact-Flash card.
3. VGA is not supported on the front panel RJ-45 connector (CN11) of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM and the RJ-45 connector is a dedicated serial port.

![The image displays an icon of a white document with a folded top-left corner and faint horizontal gray lines. A large, bold red checkmark is superimposed diagonally across the document.](.cpci-6870-50-15069-1010-201-en/d2061236d113e587ee6ee839110ccd2f43c4236fb7913b4f48e06a393670036d.jpg)
NOTE:

Specifications are subject to change without prior notice.

# 2.2 I/O Connectivity Tables

# Processor Blade

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-6870</td></tr><tr><td>Faceplate</td><td>Board</td></tr><tr><td>Gigabit Ethernet</td><td>2</td><td>—</td></tr><tr><td>COM1</td><td> $1^{(1)}$  (RJ-45)</td><td>—</td></tr><tr><td>USB 2.0</td><td>2</td><td>—</td></tr><tr><td>PMC/XMC</td><td>—</td><td>2</td></tr><tr><td>VGA</td><td> $1^{(1)}$  (RJ-45)</td><td>—</td></tr><tr><td>Serial ATA</td><td>—</td><td> $1^{(2)}$ </td></tr><tr><td>Compact Flash</td><td>—</td><td>1</td></tr><tr><td>Reset Button</td><td>1</td><td>—</td></tr></table>

Table 2-1: SBC I/O Connectivity

# Notes:

1. RJ-45 connector shared by COM port and VGA port. COM and VGA cannot be used simultaneously. (VGA is not supported on the front panel RJ-45 connector (CN11) of models with ordering numbers ending in "xx30" and higher.)
2. 2.5" HDD occupies the same space as the outer PMC/XMC site and cannot be installed simultaneously.

RTMs

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-R6001P (4HP)</td><td colspan="2">cPCI-R6002 (4HP)</td><td colspan="2">cPCI-R6002D (8HP)</td></tr><tr><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td></tr><tr><td>GbE</td><td>2</td><td>—</td><td>2</td><td>—</td><td>2</td><td>—</td></tr><tr><td>USB 2.0</td><td>2</td><td>1 (5-pin)</td><td>2</td><td>1 (5-pin)</td><td>4</td><td>1 (5-pin)</td></tr><tr><td>COM</td><td>1(DB-9)</td><td> $1^{(1)}$ (10-pin)</td><td>1 (DB-9)</td><td> $1^{(1)}$ (10-pin)</td><td>1 (DB-9)</td><td> $1^{(1)}$ (10-pin)</td></tr><tr><td>VGA</td><td>1</td><td>—</td><td>1</td><td>—</td><td>1</td><td>—</td></tr><tr><td>PIM</td><td>—</td><td>1</td><td>—</td><td>—</td><td>—</td><td>—</td></tr><tr><td>SATA</td><td>—</td><td>1 (7-pin)</td><td>—</td><td>1 (7-pin)</td><td>—</td><td> $2^{(2)}$ </td></tr><tr><td>CF</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td><td> $1^{(2)}$  (opt.)</td></tr><tr><td>Mic-in</td><td>—</td><td>—</td><td>—</td><td>—</td><td>1</td><td>—</td></tr><tr><td>Line-out</td><td>—</td><td>—</td><td>—</td><td>—</td><td>1</td><td>—</td></tr><tr><td>PS/2 KB/MS</td><td>—</td><td>—</td><td>—</td><td>—</td><td>1</td><td>—</td></tr><tr><td>SD</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td></tr><tr><td>SAS</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td></tr></table>

Table 2-2: RTM I/O Connectivity (pt. 1)

# Notes:

1. Tx, Rx signals only
2. One 7-pin signal connector for external HDD and one direct connector for onboard 2.5" SATA HDD. Optional Compact-Flash slot is supported by replacing SATA connector adapter with CompactFlash adapter. SATA HDD and CF cannot be used simultaneously.

RTMs (cont'd)

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-R6101 (4HP)</td><td colspan="2">cPCI-R6111 (4HP)</td><td colspan="2">cPCI-R6201 (8HP)</td></tr><tr><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td></tr><tr><td>GbE</td><td>4</td><td>—</td><td>2</td><td>—</td><td>2</td><td>—</td></tr><tr><td>USB 2.0</td><td>4</td><td>—</td><td>4</td><td>—</td><td>3</td><td>1 (5-pin)</td></tr><tr><td>COM</td><td>1 (RJ-45)</td><td>—</td><td>—</td><td>—</td><td>—</td><td> $1^{(1)}$ (10-pin)</td></tr><tr><td>VGA</td><td>1</td><td>—</td><td>1</td><td>—</td><td>1</td><td>—</td></tr><tr><td>PIM</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td><td>—</td></tr><tr><td>SATA</td><td>—</td><td>1 (7-pin)</td><td>—</td><td>1 (for 2.5” HDD)</td><td>—</td><td> $2^{(2)}$ </td></tr><tr><td>CF</td><td>—</td><td> $1^{(5)}$ </td><td>—</td><td> $1^{(3)}$ </td><td>—</td><td> $1^{(2)}$  (opt.)</td></tr><tr><td>Mic-in</td><td>—</td><td>—</td><td>—</td><td>—</td><td>1</td><td>—</td></tr><tr><td>Line-out</td><td>—</td><td>—</td><td>—</td><td>—</td><td>1</td><td>—</td></tr><tr><td>PS/2 KB/MS</td><td>1</td><td>—</td><td>1</td><td>—</td><td>1</td><td>—</td></tr><tr><td>SD</td><td>—</td><td>1</td><td>—</td><td>1</td><td>—</td><td>—</td></tr><tr><td>SAS</td><td>—</td><td>—</td><td>—</td><td>—</td><td>4 (SFF-8088)</td><td>4 (SFF-8087)</td></tr></table>

Table 2-3: RTM I/O Connectivity (pt. 2)

# Notes:

1. Tx, Rx signals only
2. One 7-pin signal connector for external HDD and one direct connector for onboard 2.5" SATA HDD. Optional Compact-Flash slot is supported by replacing SATA connector adapter with CompactFlash adapter. SATA HDD and CF cannot be used simultaneously.
3. Converted from USB

# 2.3 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

Table 2-4: CompactPCI Input Voltage Characteristics

# Power Consumption

This section provides information on the power consumption of cPCI-6870 Series with different CPUs, 2GB soldered onboard memory, 2x 2GB SO-DIMM memory, 100GB onboard SATA HDD and cPCI-R6002 installed. The systems were tested in Idle Mode and Full Load Mode under Windows XP running Burn-in Test 6.0. The cPCI-6870 is powered by 5V, 3.3V and optional +12V.

Idle Mode under Windows XP

<table><tr><td>CPU</td><td colspan="2">SV CoreTM2 Duo SP9300</td><td colspan="2">LV CoreTM2 Duo SL9400</td><td colspan="2">ULV CoreTM2 Duo SU9300</td><td colspan="2">ULV Celeron® M 723</td></tr><tr><td>Voltage (V)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td></tr><tr><td>+3.3</td><td>3.49</td><td>11.52</td><td>3.47</td><td>11.45</td><td>3.49</td><td>11.53</td><td>3.55</td><td>11.73</td></tr><tr><td>+5</td><td>5.32</td><td>26.61</td><td>3.12</td><td>15.60</td><td>3.14</td><td>15.71</td><td>3.41</td><td>17.08</td></tr><tr><td>Total</td><td></td><td>38.13</td><td></td><td>27.05</td><td></td><td>27.24</td><td></td><td>28.81</td></tr></table>

Table 2-5: Idle Mode Power Consumption

100% CPU Usage under Windows XP

<table><tr><td>CPU</td><td colspan="2">SV CoreTM2 Duo SP9300</td><td colspan="2">LV CoreTM2 Duo SL9400</td><td colspan="2">ULV CoreTM2 Duo SU9300</td><td colspan="2">ULV Celeron® M 723</td></tr><tr><td>Voltage (V)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Voltage (A)</td><td>Current (W)</td><td>Power (A)</td><td>Current (W)</td></tr><tr><td>+3.3</td><td>3.46</td><td>11.44</td><td>3.47</td><td>11.45</td><td>3.49</td><td>11.53</td><td>3.55</td><td>11.73</td></tr><tr><td>+5</td><td>6.54</td><td>32.70</td><td>5.24</td><td>26.20</td><td>4.07</td><td>20.39</td><td>4.11</td><td>20.57</td></tr><tr><td>Total</td><td></td><td>44.14</td><td></td><td>37.65</td><td></td><td>31.93</td><td></td><td>32.30</td></tr></table>

Table 2-6: 100% CPU Usage Power Consumption

# 3 Functional Description

The following sections describe the cPCI-6870 Series features and functions.

# 3.1 CPU

The following table lists the processors supported by the cPCI-6870 Series and their power ratings.

<table><tr><td>Features</td><td>Intel®CoreTM2 DuoSP9300</td><td>Intel®CoreTM2 DuoSL9400</td><td>Intel®CoreTM2 DuoSU9300</td><td>Intel®Celeron®722</td><td>Intel®Celeron®723</td></tr><tr><td>Clock</td><td>2.26 GHz</td><td>1.86 GHz</td><td>1.2 GHz</td><td>1.2 GHz</td><td>1.2 GHz</td></tr><tr><td>L2 cache</td><td>6MB</td><td>6MB</td><td>3MB</td><td>1MB</td><td>1MB</td></tr><tr><td>FSB</td><td>1066MHz</td><td>1066MHz</td><td>800MHz</td><td>800MHz</td><td>800MHz</td></tr><tr><td>Max. Power (TDP $^{1}$ )</td><td>25 W</td><td>17 W</td><td>10 W</td><td>5.5 W</td><td>10 W</td></tr><tr><td> $T_{junction, MAX}^{2}$ </td><td>105°C</td><td>105°C</td><td>105°C</td><td>100°C</td><td>100°C</td></tr><tr><td>Process</td><td>45nm</td><td>45nm</td><td>45nm</td><td>45nm</td><td>45nm</td></tr><tr><td># of cores</td><td>2</td><td>2</td><td>2</td><td>1</td><td>1</td></tr></table>

# Notes:

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.
2. The maximum supported operating temperature.

# Intel® Core™2 Duo Processor

The Intel® Core™2 Duo mobile processors are high-performance, low-power processors based on the Intel® Core™ microarchitecture for Intel® Centrino® 2 technology. The following list outlines the key features of this processor:

▶ Dual-core processor for mobile with enhanced performance
▶ Supports Intel architecture with Intel® Wide Dynamic Execution
▶ Supports L1 cache-to-cache (C2C) transfer
▶ On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each core

The processor in DC-XE, standard voltage (SV) and LV have an on-die, up to 6-MB second-level, shared cache with Advanced Transfer Cache architecture
The processor in ULV single-core and dual-core have an on-die, up to 3-MB second-level, shared cache with Advanced Transfer Cache architecture
▶ Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets
The processor in DC-XE, SV and LV are offered at 1066-MHz, source-synchronous front side bus (FSB)
▶ Advanced power management features including Enhanced Intel SpeedStep® Technology and dynamic FSB frequency switching
▶ Digital thermal sensor (DTS)
Intel® 64 architecture
▶ Supports enhanced Intel® Virtualization Technology
▶ Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM)
▶ Supports PSI2 functionality
▶ SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies
▶ Execute Disable Bit support for enhanced security
Intel® Deep Power Down low-power state with P\_LVL6 I/O support
▶ Support for Intel® Trusted Execution Technology
▶ Half ratio support (N/2) for core to bus ratio

# Intel® Celeron® Processor 722, 723

The Intel® Celeron® 722, 723 processor are based on 45 nm process technology in small form factor (SFF). The following list provides some of the key features of this processor:

▶ Single core with enhanced performance
▶ Ultra Low Voltage
▶ Supports L1 cache-to-cache transfer

▶ On-die, primary 32-KB instruction cache and 32-KB write-back data cache
▶ On-die, 1-MB second level shared cache with advanced transfer cache architecture
▶ 800-MHz source-synchronous front side bus (FSB)
▶ Supports Intel® architecture with Intel® Wide Dynamic Execution
▶ Digital Thermal Sensor (DTS)
▶ 956-ball Micro-FCBGA packaging technology
▶ Execute Disable Bit support for enhanced security
Intel® 64 architecture (formerly Intel® EM64T)
▶ Architectural and performance enhancements of the Core microarchitecture.

# 3.2 Chipset

The cPCI-6870 Series incorporates the Mobile Intel® 82GS45 Graphics and Memory Controller Hub (GMCH) and 82801IUX I/O Controller Hub (ICH9M-SFF).

# Intel® GS45 Graphics Memory Controller Hub

The following outlines the key features of GS45 GMCH.

# Processor Support

Intel® Core™2 Duo, Intel® Core™2 Solo, and Intel® Cel-eron® mobile processors based on the 45-nm process
▶ 800-MHz and 1066-MHz FSBSupport for Dynamic FSB Frequency Switching
▶ Support for Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) (DMA)
36-bit interface to addressing, allowing the CPU to access the entire 64 GB of the GMCH's memory address space

# System Memory Support

▶ Supports DDR2 and DDR3 SDRAM (DDR3 only on cPCI-6870)
▶ Support for DDR3 at 667, 800 and 1066 MHz
▶ Two Memory Channel Configurations supported in Dual-channel Asymmetric
▶ 8-GB maximum memory support
▶ Support for x8 and x16 DDR2 and DDR3 devices
▶ 64-bit wide per channel
▶ No support for ECC

# Direct Management Interface

▶ Chip-to-chip interface between GMCH and 82801 GMB/GHM
▶ Configurable as x2 or x4 DMI lanes
▶ 2-GB/s (1-GB/s each direction) point-to-point interface to ICH
▶ 32-bit downstream address

# Integrated Graphics

Intel Gen 5.0 integrated graphics engine with ten, fully-programmable cores
▶ 533-MHz core render clock @ 1.05-V core voltage
▶ Low-power configuration: 320-MHz core render clock at 1.05-V core voltage
▶ Supports HDMI/DVI, DP, TV-Out, LVDS, CRT and SDVO (the cPCI-6870 implements analog CRT only)
Intel® Dynamic Video Memory Technology (Intel® DVMT 5.0)
▶ Microsoft DirectX10 support
▶ Single channel LVDS interface support: 1x18 bpp (LVDS signals are routed to J5 connector)
▶ Integrated 300-MHz DAC analog CRT
▶ Analog monitor support up to QXGA
▶ Support for CRT Hot-Plug

# Intel® ICH9M-SFF Mobile I/O Controller Hub

The ICH9M-SFF provides extensive I/O support. Functions and capabilities include:

▶ ACPI Power Management Logic Support
▶ Integrated Serial ATA host controllers with independent DMA operation on up to four ports and AHCI support.
▶ Supports data transfer rates of up to 3.0 Gb/s (300 MB/s).
The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI\* mode using memory space. Software that uses legacy mode will not have AHCI\* capabilities.

▶ Provides 6 PCI Express x1 ports, supporting the PCI Express Base Specification, Revision 1.1. Each Root Port supports 2.5GB/s bandwidth in each direction (5 GB/s concurrent). The cPCI-6870 utilizes four PCI Express ports 3-6 for four Gigabit Ethernet controllers and configures the PCI Express ports 1-2 to PCI-Express x2 for connecting PCI Express to PCI bridge to support 64bit/66MHz CompactPCI bus..

▶ Enhanced DMA controller, interrupt controller, and timer functions

▶ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices

▶ Supports Intel® High Definition Audio

▶ Supports Intel® Virtualization Technology for Directed I/O

▶ PCI Local Bus Specification, Revision 2.3 support for 33MHz PCI operations

\*AHCI is a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware.

# 3.3 Super I/O

The ITE IT8783F Super I/O is on a Low Pin Count interface supporting PS/2 keyboard/mouse, three 16C550-compatible serial ports, floppy drive interface, hardware monitor function to monitor CPU voltage, CPU temperature, power supply voltages and system temperature, and Watch Dog Timer with time resolution from minimum 1 second or minute to maximum 65,535 seconds or minutes.

# 3.4 Battery

The cPCI-6870 is provided with a 3.0V coin cell lithium battery for the Real Time Clock (RTC). The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. A Rayovac BR2032 is equipped on board by default.

# 3.5 PMC/XMC Sites

The cPCI-6870 series supports two PMC sites for front panel I/O expansion. The PMC sites provide a maximum 64bit/133MHz PCI bus link using a Pericom PI7C9X130 PCI-Express-to-PCI bridge and PCI-Express x4 link. The PMC site supports +3.3V or +5V signaling.

The JN1/4 and JN2/5 connectors provide the signals for the 32-bit PCI bus. The JN3/6 connector provides the 64 bit extension for the PMC interface. The JN7 connector in PMC/XMC 2 supports user defined I/O signals and is routed to the CompactPCI J4 connector to rear I/O.

The cPCI-6870 provides two PCIe x8 XMC interfaces sharing the same space as the PMC sites for high speed I/O expansion such as 10GbE or high-end graphics.

# 4 Board Interfaces

# 4.1 cPCI-6870 SBC Board Layout

![SW2 SW5\nU1\nCN3\nCN4\nCN2\nU3\nU5\nJ4\nCN7\nCN6\nCN8\nCN9/10\nCN11\nCN12\nU18\nU15\nU16\nU29\nU26\nU28\nJ1\nJ5\nJ4\nJ3\nJ2\nJ1\nSW3 SW1\nSW6\nSW10\nSW9\nSW13\nSW12\nSW8\nSW7](.cpci-6870-50-15069-1010-201-en/95b3f76ac5701c4495f7f4f5894c69daa5fee27e67ae6fe0db9dc22d50fb5ec0.jpg)

<table><tr><td>U26</td><td>CPU</td><td>CN3</td><td>SATA adapter card conn.</td></tr><tr><td>U18</td><td>North Bridge GS45</td><td>CN7/8</td><td>SO-DIMM socket</td></tr><tr><td>U3</td><td>South Bridge ICH9M-SFF</td><td>CN9/10</td><td>USB ports</td></tr><tr><td>U16/28</td><td>PCIe to PCI Bridge</td><td>CN11</td><td>COM/VGA port*</td></tr><tr><td>U4/5/29/39</td><td>Intel 82574L GbE controllers</td><td>CN12</td><td>LAN ports</td></tr><tr><td>U15</td><td>PCIe Switch</td><td>J1-J5</td><td>CompactPCI connectors</td></tr><tr><td>U1</td><td>Super I/O</td><td>JN1-JN7</td><td>PMC connectors</td></tr><tr><td>CN2/6</td><td>XMC connectors</td><td>SW1~13</td><td>Switches</td></tr><tr><td>CN4</td><td>CompactFlash socket</td><td>SW4</td><td>Clear CMOS button</td></tr></table>

Figure 4-1: cPCI-6870 SBC Board Layout

![The image displays a white icon of a document with a folded top-left corner and faint horizontal lines, featuring a large, bold red checkmark drawn diagonally across the center.](.cpci-6870-50-15069-1010-201-en/eca2294201ad0218301364b424ed17ec80425d51c8d287346328814889e19b2c.jpg)
NOTE:

\*VGA is not supported on CN11 of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM and the RJ-45 connector is a dedicated serial port.

# 4.2 cPCI-6870 SBC Front Panel

![GbE 1/2\nPMC/XMC 1\nPMC/XMC 2\nCOM/VGA*\n2x USB 2.0\nStatus LEDs](.cpci-6870-50-15069-1010-201-en/e60cd61f97fd2ceb676b354ecee72a457ef7b07c60486f528e767223d1932cf5.jpg)

Figure 4-2: cPCI-6870 Series Front Panel Layout

# Status LEDs

![The image displays the flag of Japan, featuring a large, solid red circle centered on a plain white rectangular background.](.cpci-6870-50-15069-1010-201-en/9ce5669527691bce03f80ea9a818579f87813f2bce0e403259ae89fafca0900b.jpg)

WDT

![The image features a large, solid yellow circle centered horizontally on a white background. Thin strips of the white background are visible at the very top and bottom edges of the frame. There is no text present.](.cpci-6870-50-15069-1010-201-en/72be4e11fb718edc39ee7cf8acb36535bddd1817d4b35625a739e51567c53665.jpg)

HD

![The image displays a single, solid blue circle centered on a white background. There is no text present.](.cpci-6870-50-15069-1010-201-en/26347f978b1d257495a036b41c043e9e8df9be71e8bc4547b80ef9a995f5f054.jpg)

HW

![A solid, bright green circle is centered within a white rectangular background.](.cpci-6870-50-15069-1010-201-en/b3cb553030121f3d7264841da797aae818ea7a13f5c235679952c1356a54a1da.jpg)

PW

RST

![The image displays a black outline of a horizontally oriented rectangle with rounded corners, resembling a pill or lozenge shape, set against a plain white background. There is no text visible in the image.](.cpci-6870-50-15069-1010-201-en/28dfce7fd2f6269d814a6ae102eb77e321ba0c0058f5e3e8c92bef9200672fe2.jpg)

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="2">Power (PW)</td><td rowspan="2">Green</td><td>OFF</td><td>System is off</td></tr><tr><td>ON</td><td>System is on</td></tr><tr><td rowspan="4">Hot Swap (HW)</td><td rowspan="4">Blue</td><td>OFF</td><td>Handles closed, System is on</td></tr><tr><td>Fast Blink</td><td>Preparing to shut down system (LED: 0.1s on, 0.9s off)</td></tr><tr><td>ON</td><td>Handles open and SBC ready to be removed</td></tr><tr><td>Slow Blink</td><td>Voltages out of tolerance: 3.3V, 5V, 12V, 1.5V over ±5% (LED: 2s on, 1s off)</td></tr><tr><td rowspan="2">WDT (WDT)</td><td rowspan="2">Red</td><td>OFF</td><td>No Watchdog event</td></tr><tr><td>ON</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">HDD (HD)</td><td rowspan="2">Amber</td><td>OFF</td><td>No HDD activity</td></tr><tr><td>Blink</td><td>Data read/write in process</td></tr></table>

Table 4-1: cPCI-6870 Front Panel Status LED Descriptions

\*VGA is not supported on front panel RJ-45 of models with ordering numbers ending in "xx30" and higher.

# 4.3 Connector Pin Assignments

USB Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![1\n2\n3\n4](.cpci-6870-50-15069-1010-201-en/b42bf871c63378fdc8ea2dcc1493725de846be00c0d5aea70f4f975ed2fcacd9.jpg)

Table 4-2: USB Connector Pin Definition

RJ-45 COM/VGA\* Port (CN-11)

<table><tr><td>Pin #</td><td>COM Signal</td><td>VGA Signal</td></tr><tr><td>1</td><td>DCD#</td><td>DDCDAT_5V</td></tr><tr><td>2</td><td>RTS#</td><td>HSYNC</td></tr><tr><td>3</td><td>DSR#</td><td>VSYNC</td></tr><tr><td>4</td><td>TXD</td><td>DDCCLK_5V</td></tr><tr><td>5</td><td>RXD</td><td>BLUE</td></tr><tr><td>6</td><td>GND</td><td>GND</td></tr><tr><td>7</td><td>CTS#</td><td>GREEN</td></tr><tr><td>8</td><td>DTR#</td><td>RED</td></tr></table>

![1\n6](.cpci-6870-50-15069-1010-201-en/314c8de0b06b8d1565fb9ab6f5ca6f82c8ae8e32da50f0e5386ecb01c9c17a36.jpg)

Table 4-3: RJ-45 Serial/VGA Port Pin Definition
![The image displays a digital icon of a white document with horizontal lines, overlaid with a large red checkmark.](.cpci-6870-50-15069-1010-201-en/31d5eb0b5c97db821053eeb358ca268be7bdd99541d7d02d946d0f2857e58e9d.jpg)
NOTE:

\*VGA is not supported on CN11 of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM and the RJ-45 connector is a dedicated serial port.

PS/2 Keyboard/Mouse Connector (CN11-R)

<table><tr><td>Pin #</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+5V</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

![6\n5\n4\n3\n2 1](.cpci-6870-50-15069-1010-201-en/dfd836cc571bf211106dbe39606665bcd4f36879357a54faa336ecde0ba83b02.jpg)

Table 4-4: PS/2 Keyboard/Mouse Connector Pin Definition

RJ-45 Gigabit Ethernet Connectors (CN12, CN20-R, CN21-R)

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>BI_DA+</td></tr><tr><td>2</td><td>TX-</td><td>BI_DA-</td></tr><tr><td>3</td><td>RX+</td><td>BI_DB+</td></tr><tr><td>4</td><td>--</td><td>BI_DC+</td></tr><tr><td>5</td><td>--</td><td>BI_DC-</td></tr><tr><td>6</td><td>RX-</td><td>BI_DB-</td></tr><tr><td>7</td><td>--</td><td>BI_DD+</td></tr><tr><td>8</td><td>--</td><td>BI_DD-</td></tr></table>

![1\n8\nActivity\nSpeed](.cpci-6870-50-15069-1010-201-en/df81fb79a9f002e50f51ecba15541f799cce815a6e090f9a37997d1bab725aff.jpg)

Table 4-5: GbE Connector Pin Definitions

<table><tr><td colspan="2">Status (CN4, CN5)</td><td>Speed LED(Green/Amber)</td><td>Activity LED(Amber)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Amber</td><td>ON</td></tr><tr><td>Active</td><td>Amber</td><td>Blinking</td></tr></table>

Table 4-6: GbE LED CN12 Status Definitions

DB-9 Serial Port (CN9-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD, Data carrier detect</td></tr><tr><td>2</td><td>RXD, Receive data</td></tr><tr><td>3</td><td>TXD, Transmit data</td></tr><tr><td>4</td><td>DTR, Data terminal ready</td></tr><tr><td>5</td><td>IsoGND, Isolated ground</td></tr><tr><td>6</td><td>DSR, Data set ready</td></tr><tr><td>7</td><td>RTS, Request to send</td></tr><tr><td>8</td><td>CTS, Clear to send</td></tr><tr><td>9</td><td>RI, Ring indicator</td></tr></table>

![6\n1\n5](.cpci-6870-50-15069-1010-201-en/cd7f7a1c7ea7cba8169ad6f2677b8a38e4ce5a8c40ab72f3335ad030217fa874.jpg)

Table 4-7: COM1-2 Serial Port Connector Pin Definition
Onboard Serial Port Connector (CN10-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>Not used</td></tr><tr><td>2</td><td>Not used</td></tr><tr><td>3</td><td>RXD, Receive data</td></tr><tr><td>4</td><td>Not used</td></tr><tr><td>5</td><td>TXD, Transmit data</td></tr><tr><td>6</td><td>Not used</td></tr><tr><td>7</td><td>Not used</td></tr><tr><td>8</td><td>Not used</td></tr><tr><td>9</td><td>IsoGND, Isolated ground</td></tr><tr><td>10</td><td>Not used</td></tr></table>

![1\n2\n9\n10](.cpci-6870-50-15069-1010-201-en/a5a4a3f76bfa33e5436ee2868d31b69661280ffa10fa87b981d4ee9443383e3f.jpg)

Table 4-8: Onboard Serial Port Connector Pin Definition

Serial ATA Connectors (CN1-R)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX+</td></tr><tr><td>3</td><td>TX-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX-</td></tr><tr><td>6</td><td>RX+</td></tr><tr><td>7</td><td>GND</td></tr></table>

![The image displays a schematic line drawing of an HDMI Type A connector port. The diagram shows a vertical rectangular outline representing the port's housing, featuring L-shaped mounting brackets at the top and bottom corners. Inside the housing, there is a central vertical strip of small black rectangles representing the electrical contacts. On the right side of the drawing, two vertical red lines are present. Next to the top red line is the red number '1', and next to the bottom red line is the red number '7'.](.cpci-6870-50-15069-1010-201-en/c7e537ce0f1c8cd54cca48991ec76dd2e099f87067df441e7c392f89b51ed42c.jpg)
Table 4-9: SATA Connector Pin Definition

Serial ATA Connector on DB-6920SAT

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>NC</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>Reserved</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>12V</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-6870-50-15069-1010-201-en/61ece1989d73db7da25cbeb03c2376dbcafcd845ca8b7623a6db22518cb4222e.jpg)

Table 4-10: DB-6920SAT SATA Connector Pin Definition

PMC Connector (JN1/4, JN2/5, JN3/6, JN7)

<table><tr><td>Pin#</td><td>JN1/4 Signal</td><td>JN2/5 Signal</td><td>JN3/6 Signal</td><td>JN7 Signal</td></tr><tr><td>1</td><td>PMC_TCK</td><td>P12V</td><td>NC</td><td>PIO1</td></tr><tr><td>2</td><td>N12V</td><td>PMC_TRST-L</td><td>GND</td><td>PIO2</td></tr><tr><td>3</td><td>GND</td><td>PMC_TMS</td><td>GND</td><td>PIO3</td></tr><tr><td>4</td><td>PCIX_INTA-L</td><td>NC (PMC_TDO)</td><td>PCIX_CBE-L7</td><td>PIO4</td></tr><tr><td>5</td><td>PCIX_INTB-L</td><td>PMC_TDI</td><td>PCIX_CBE-L6</td><td>PIO5</td></tr><tr><td>6</td><td>PCIX_INTC-L</td><td>GND</td><td>PCIX_CBE-L5</td><td>PIO6</td></tr><tr><td>7</td><td>PMC_MOD-L1</td><td>GND</td><td>PCIX_CBE-L4</td><td>PIO7</td></tr><tr><td>8</td><td>P5V</td><td>NC</td><td>GND</td><td>PIO8</td></tr><tr><td>9</td><td>PCIX_INTD-L</td><td>NC</td><td>PMC_VIO</td><td>PIO9</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>PCIX_PAR64</td><td>PIO10</td></tr><tr><td>11</td><td>GND</td><td>PMC_MOD-L2</td><td>PCIX_AD63</td><td>PIO11</td></tr><tr><td>12</td><td>P3V3_PMCAUX</td><td>P3V3</td><td>PCIX_AD62</td><td>PIO12</td></tr><tr><td>13</td><td>CLK66_PCIX_PMC</td><td>PMC_RST-L</td><td>PCIX_AD61</td><td>PIO13</td></tr><tr><td>14</td><td>GND</td><td>PMC_MOD-L3</td><td>GND</td><td>PIO14</td></tr><tr><td>15</td><td>GND</td><td>P3V3</td><td>GND</td><td>PIO15</td></tr><tr><td>16</td><td>PCIX_GNT-L0</td><td>PMC_MOD-L4</td><td>PCIX_AD60</td><td>PIO16</td></tr><tr><td>17</td><td>PCIX_REQ-L0</td><td>PMC_PME-L</td><td>PCIX_AD59</td><td>PIO17</td></tr><tr><td>18</td><td>P5V</td><td>GND</td><td>PCIX_AD58</td><td>PIO18</td></tr><tr><td>19</td><td>PMC_VIO</td><td>PCIX_AD30</td><td>PCIX_AD57</td><td>PIO19</td></tr><tr><td>20</td><td>PCIX_AD31</td><td>PCIX_AD29</td><td>GND</td><td>PIO20</td></tr><tr><td>21</td><td>PCIX_AD28</td><td>GND</td><td>GND</td><td>PIO21</td></tr><tr><td>22</td><td>PCIX_AD27</td><td>PCIX_AD26</td><td>PCIX_AD56</td><td>PIO22</td></tr><tr><td>23</td><td>PCIX_AD25</td><td>PCIX_AD24</td><td>PCIX_AD55</td><td>PIO23</td></tr><tr><td>24</td><td>GND</td><td>PCIX_AD23</td><td>PCIX_AD54</td><td>PIO24</td></tr><tr><td>25</td><td>GND</td><td>PMC_IDSEL</td><td>PCIX_AD53</td><td>PIO25</td></tr><tr><td>26</td><td>PCIX_CBE-L3</td><td>PCIX_AD23</td><td>GND</td><td>PIO26</td></tr><tr><td>27</td><td>PCIX_AD22</td><td>P3V3</td><td>GND</td><td>PIO27</td></tr><tr><td>28</td><td>PCIX_AD21</td><td>PCIX_AD20</td><td>PCIX_AD52</td><td>PIO28</td></tr><tr><td>29</td><td>PCIX_AD19</td><td>PCIX_AD18</td><td>PCIX_AD51</td><td>PIO29</td></tr><tr><td>30</td><td>P5V</td><td>GND</td><td>PCIX_AD50</td><td>PIO30</td></tr><tr><td>31</td><td>PCIX_FRAME-L</td><td>PCIX_AD16</td><td>PCIX_AD49</td><td>PIO31</td></tr><tr><td>32</td><td>PCIX_AD17</td><td>PCIX_CBE-L2</td><td>GND</td><td>PIO32</td></tr></table>

![64\n63\n2\n1](.cpci-6870-50-15069-1010-201-en/8395bf4b9e5e5bbc868e7cba99e5f08be3ecccc937b6b83c85f714965290d7d1.jpg)

Table 4-11: PMC Connector Pin Definitions

<table><tr><td>Pin#</td><td>JN1/4 Signal</td><td>JN2/5 Signal</td><td>JN3/6 Signal</td><td>JN7 Signal</td></tr><tr><td>33</td><td>PCIX_FRAME-L</td><td>GND</td><td>GND</td><td>PIO33</td></tr><tr><td>34</td><td>GND</td><td>NC</td><td>PCIX_AD48</td><td>PIO34</td></tr><tr><td>35</td><td>GND</td><td>PCIX_TRDY-L</td><td>PCIX_AD47</td><td>PIO35</td></tr><tr><td>36</td><td>PCIX_IRDY-L</td><td>P3V3</td><td>PCIX_AD46</td><td>PIO36</td></tr><tr><td>37</td><td>PCIX_DEVSEL-L</td><td>GND</td><td>PCIX_AD45</td><td>PIO37</td></tr><tr><td>38</td><td>P5V</td><td>PCIX_STOP-L</td><td>GND</td><td>PIO38</td></tr><tr><td>39</td><td>PCIX_PCIXCAP</td><td>PCIX_PERR-L</td><td>GND</td><td>PIO39</td></tr><tr><td>40</td><td>PCIX_LOCK-L</td><td>GND</td><td>PCIX_AD44</td><td>PIO40</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td><td>PCIX_AD43</td><td>PIO41</td></tr><tr><td>42</td><td>NC</td><td>PCIX_SERR-L</td><td>PCIX_AD42</td><td>PIO42</td></tr><tr><td>43</td><td>PCIX_PAR</td><td>PCIX_CBE-L1</td><td>PCIX_AD41</td><td>PIO43</td></tr><tr><td>44</td><td>GND</td><td>GND</td><td>GND</td><td>PIO44</td></tr><tr><td>45</td><td>PMC_VIO</td><td>PCIX_AD14</td><td>GND</td><td>PIO45</td></tr><tr><td>46</td><td>PCIX_AD15</td><td>PCIX_AD13</td><td>PCIX_AD40</td><td>PIO46</td></tr><tr><td>47</td><td>PCIX_AD12</td><td>PCIX_M66EN</td><td>PCIX_AD39</td><td>PIO47</td></tr><tr><td>48</td><td>PCIX_AD11</td><td>PCIX_AD10</td><td>PCIX_AD38</td><td>PIO48</td></tr><tr><td>49</td><td>PCIX_AD9</td><td>PCIX_AD8</td><td>PCIX_AD37</td><td>PIO49</td></tr><tr><td>50</td><td>P5V</td><td>P3V3</td><td>GND</td><td>PIO50</td></tr><tr><td>51</td><td>GND</td><td>PCIX_AD7</td><td>GND</td><td>PIO51</td></tr><tr><td>52</td><td>PCIX_CBE-L0</td><td>NC</td><td>PCIX_AD36</td><td>PIO52</td></tr><tr><td>53</td><td>PCIX_AD6</td><td>P3V3</td><td>PCIX_AD35</td><td>PIO53</td></tr><tr><td>54</td><td>PCIX_AD5</td><td>NC</td><td>PCIX_AD34</td><td>PIO54</td></tr><tr><td>55</td><td>PCIX_AD4</td><td>NC</td><td>PCIX_AD33</td><td>PIO55</td></tr><tr><td>56</td><td>GND</td><td>GND</td><td>GND</td><td>PIO56</td></tr><tr><td>57</td><td>PMC_VIO</td><td>NC</td><td>GND</td><td>PIO57</td></tr><tr><td>58</td><td>PCIX_AD3</td><td>NC</td><td>PCIX_AD32</td><td>PIO58</td></tr><tr><td>59</td><td>PCIX_AD2</td><td>GND</td><td>NC</td><td>PIO59</td></tr><tr><td>60</td><td>PCIX_AD1</td><td>NC</td><td>NC</td><td>PIO60</td></tr><tr><td>61</td><td>PCIX_AD0</td><td>PCIX_ACK64-L</td><td>NC</td><td>PIO61</td></tr><tr><td>62</td><td>P5V</td><td>P3V3</td><td>GND</td><td>PIO62</td></tr><tr><td>63</td><td>GND</td><td>GND</td><td>GND</td><td>PIO63</td></tr><tr><td>64</td><td>PCIX_REQ64-L</td><td>NC</td><td>NC</td><td>PIO64</td></tr></table>

Table 4-11: PMC Connector Pin Definitions (cont'd)

XMC Connectors (CN2, CN6)
![F1\nA1\nF19\nA19](.cpci-6870-50-15069-1010-201-en/f3d6116744471ff8e3985bdebeca5806f8f43cf8eff7203c3b7562c1d26b1079.jpg)

<table><tr><td>Pin#</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>PETp0</td><td>PETn0</td><td>3.3V</td><td>PETp1</td><td>PETn1</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>TRST#</td><td>GND</td><td>GND</td><td>MRSTI#</td></tr><tr><td>3</td><td>PETp2</td><td>PETn2</td><td>3.3V</td><td>PETp3</td><td>PETn3</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>TCK</td><td>GND</td><td>GND</td><td>MRSTO#</td></tr><tr><td>5</td><td>PETp4</td><td>PETn4</td><td>3.3V</td><td>PETp5</td><td>PETn5</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>TMS</td><td>GND</td><td>GND</td><td>+12V</td></tr><tr><td>7</td><td>PETp6</td><td>PETn6</td><td>3.3V</td><td>PETp7</td><td>PETn7</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>TDI</td><td>GND</td><td>GND</td><td>-12V</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>TDO</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>PERp0</td><td>PERn0</td><td>MBIST#</td><td>PERp1</td><td>PERn1</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>MPRESENT#</td></tr><tr><td>13</td><td>PERp2</td><td>PERn2</td><td>3.3V AUX</td><td>PERp3</td><td>PERn3</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>MSDA</td></tr><tr><td>15</td><td>PERp4</td><td>PERn4</td><td>NC</td><td>PERp5</td><td>PERn5</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>MVMRO</td><td>GND</td><td>GND</td><td>MSCL</td></tr><tr><td>17</td><td>PERp6</td><td>PERn6</td><td>NC</td><td>PERp7</td><td>PERn7</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>19</td><td>REFCLK+0</td><td>REFCLK-0</td><td>NC</td><td>WAKE#</td><td>ROOT0#</td><td>NC</td></tr></table>

Table 4-12: XMC Connector Pin Definition

68-pin SCSI Connector (CN12-R)\*

<table><tr><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td></tr><tr><td>SCSI-SDP12</td><td>1</td><td>35</td><td>SCSI-SDN12</td></tr><tr><td>SCSI-SDP13</td><td>2</td><td>36</td><td>SCSI-SDN13</td></tr><tr><td>SCSI-SDP14</td><td>3</td><td>37</td><td>SCSI-SDN14</td></tr><tr><td>SCSI-SDP15</td><td>4</td><td>38</td><td>SCSI-SDN15</td></tr><tr><td>SCSI-SDP1-P1</td><td>5</td><td>39</td><td>SCSI-SDP1-N1</td></tr><tr><td>SCSI-SDP0</td><td>6</td><td>40</td><td>SCSI-SDN0</td></tr><tr><td>SCSI-SDP1</td><td>7</td><td>41</td><td>SCSI-SDN1</td></tr><tr><td>SCSI-SDP2</td><td>8</td><td>42</td><td>SCSI-SDN2</td></tr><tr><td>SCSI-SDP3</td><td>9</td><td>43</td><td>SCSI-SDN3</td></tr><tr><td>SCSI-SDP4</td><td>10</td><td>44</td><td>SCSI-SDN4</td></tr><tr><td>SCSI-SDP5</td><td>11</td><td>45</td><td>SCSI-SDN5</td></tr><tr><td>SCSI-SDP6</td><td>12</td><td>46</td><td>SCSI-SDN6</td></tr><tr><td>SCSI-SDP7</td><td>13</td><td>47</td><td>SCSI-SDN7</td></tr><tr><td>SCSI-SDP0-P0</td><td>14</td><td>48</td><td>SCSI-SDP0-N0</td></tr><tr><td>GND</td><td>15</td><td>49</td><td>GND</td></tr><tr><td>DIFFSEN</td><td>16</td><td>50</td><td>NC</td></tr><tr><td>P3V3_SCSI</td><td>17</td><td>51</td><td>P3V3_SCSI</td></tr><tr><td>P3V3_SCSI</td><td>18</td><td>52</td><td>P3V3_SCSI</td></tr><tr><td>NC</td><td>19</td><td>53</td><td>NC</td></tr><tr><td>GND</td><td>20</td><td>54</td><td>GND</td></tr><tr><td>SCSI-SATN-P</td><td>21</td><td>55</td><td>SCSI-SATN-N</td></tr><tr><td>GND</td><td>22</td><td>56</td><td>GND</td></tr><tr><td>SCSI-SBSY-P</td><td>23</td><td>57</td><td>SCSI-SBSY-N</td></tr><tr><td>SCSI-SACK-P</td><td>24</td><td>58</td><td>SCSI-SACK-N</td></tr><tr><td>SCSI-SRST-P</td><td>25</td><td>59</td><td>SCSI-SRST-N</td></tr><tr><td>SCSI-SMSG-P</td><td>26</td><td>60</td><td>SCSI-SMSG-N</td></tr><tr><td>SCSI-SSEL-P</td><td>27</td><td>61</td><td>SCSI-SSEL-N</td></tr><tr><td>SCSI-SCD-P</td><td>28</td><td>62</td><td>SCSI-SCD-N</td></tr><tr><td>SCSI-SREQ-P</td><td>29</td><td>63</td><td>SCSI-SREQ-N</td></tr><tr><td>SCSI-SIO-P</td><td>30</td><td>64</td><td>SCSI-SIO-N</td></tr><tr><td>SCSI-SDP8</td><td>31</td><td>65</td><td>SCSI-SDN8</td></tr><tr><td>SCSI-SDP9</td><td>32</td><td>66</td><td>SCSI-SDN9</td></tr><tr><td>SCSI-SDP10</td><td>33</td><td>67</td><td>SCSI-SDN10</td></tr><tr><td>SCSI-SDP11</td><td>34</td><td>68</td><td>SCSI-SDN11</td></tr></table>

![1\n35\n34\n68](.cpci-6870-50-15069-1010-201-en/bb77eef265a37b5f8d57460aef539e9a7e0ff29affa5d14c340d1c28ef5a7682.jpg)

Table 4-13: 68-pin SCSI Connector Pin Definition

Floppy Connector 34-pin (CN4-R)\*

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>Extended Density</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>No Connect</td></tr><tr><td>5</td><td>NC</td><td>6</td><td>Data Rate</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>Index</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>Motor A Select</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>Drive B Select</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>Drive A Select</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>Motor B Select</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>Step Direction</td></tr><tr><td>19</td><td>GND</td><td>20</td><td>Step Pulse</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>Write Data</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>Write Gate</td></tr><tr><td>25</td><td>GND</td><td>26</td><td>Track 0</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>Write Protect</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>Read Data</td></tr><tr><td>31</td><td>GND</td><td>32</td><td>Side 1</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>Disk Change</td></tr></table>

![1\n2\n33\n34](.cpci-6870-50-15069-1010-201-en/13299ffec3f77f895264b0131b0fa0b6f2a002550a7be66e1951e40ff3e0beeb.jpg)

Table 4-14: Floppy Connector Pin Definition
![The image displays a white piece of paper with a folded top-right corner. Faint horizontal grey lines run across the lower portion of the page. A large, bold red checkmark is superimposed diagonally over the document.](.cpci-6870-50-15069-1010-201-en/7c5c0f13b78e8bafe15393b466b642afd62178bfd4cbb48d2141d2da00aebc42.jpg)
NOTE:

\*SCSI and floppy are not supported on current model RTMs. These pin definitions are provided for customers with older model RTMs.

PIM Connector (JN1-R)

<table><tr><td>Pin#</td><td>Signal Name</td><td>Signal Name</td><td>Pin#</td></tr><tr><td>1</td><td>PIM1</td><td>PIM2</td><td>2</td></tr><tr><td>3</td><td>PIM3</td><td>PIM4</td><td>4</td></tr><tr><td>5</td><td>PIM5</td><td>PIM6</td><td>6</td></tr><tr><td>7</td><td>PIM7</td><td>PIM8</td><td>8</td></tr><tr><td>9</td><td>PIM9</td><td>PIM10</td><td>10</td></tr><tr><td>11</td><td>PIM11</td><td>PIM12</td><td>12</td></tr><tr><td>13</td><td>PIM13</td><td>PIM14</td><td>14</td></tr><tr><td>15</td><td>PIM15</td><td>PIM16</td><td>16</td></tr><tr><td>17</td><td>PIM17</td><td>PIM18</td><td>18</td></tr><tr><td>19</td><td>PIM19</td><td>PIM20</td><td>20</td></tr><tr><td>21</td><td>PIM21</td><td>PIM22</td><td>22</td></tr><tr><td>23</td><td>PIM23</td><td>PIM24</td><td>24</td></tr><tr><td>25</td><td>PIM25</td><td>PIM26</td><td>26</td></tr><tr><td>27</td><td>PIM27</td><td>PIM28</td><td>28</td></tr><tr><td>29</td><td>PIM29</td><td>PIM30</td><td>30</td></tr><tr><td>31</td><td>PIM31</td><td>PIM32</td><td>32</td></tr><tr><td>33</td><td>PIM33</td><td>PIM34</td><td>34</td></tr><tr><td>35</td><td>PIM35</td><td>PIM36</td><td>36</td></tr><tr><td>37</td><td>PIM37</td><td>PIM38</td><td>38</td></tr><tr><td>39</td><td>PIM39</td><td>PIM40</td><td>40</td></tr><tr><td>41</td><td>PIM41</td><td>PIM42</td><td>42</td></tr><tr><td>43</td><td>PIM43</td><td>PIM44</td><td>44</td></tr><tr><td>45</td><td>PIM45</td><td>PIM46</td><td>46</td></tr><tr><td>47</td><td>PIM47</td><td>PIM48</td><td>48</td></tr><tr><td>49</td><td>PIM49</td><td>PIM50</td><td>50</td></tr><tr><td>51</td><td>PIM51</td><td>PIM52</td><td>52</td></tr><tr><td>53</td><td>PIM53</td><td>PIM54</td><td>54</td></tr><tr><td>55</td><td>PIM55</td><td>PIM56</td><td>56</td></tr><tr><td>57</td><td>PIM57</td><td>PIM58</td><td>58</td></tr><tr><td>59</td><td>PIM59</td><td>PIM60</td><td>60</td></tr><tr><td>61</td><td>PIM61</td><td>PIM62</td><td>62</td></tr><tr><td>63</td><td>PIM63</td><td>PIM64</td><td>64</td></tr></table>

![64\n63\n2\n1](.cpci-6870-50-15069-1010-201-en/0655f90ced0866499584dacbd02bd9863187f4a4c9c6200f419d8b7b43157853.jpg)

Table 4-15: PIM Connector (JN1-R) Pin Definition

PIM Connector (JN2-R)

<table><tr><td>Pin#</td><td>Signal Name</td><td>Signal Name</td><td>Pin#</td></tr><tr><td>1</td><td>NC</td><td>NC</td><td>2</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>4</td></tr><tr><td>5</td><td>P5V</td><td>NC</td><td>6</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>8</td></tr><tr><td>9</td><td>NC</td><td>P3V3</td><td>10</td></tr><tr><td>11</td><td>NC</td><td>NC</td><td>12</td></tr><tr><td>13</td><td>GND</td><td>NC</td><td>14</td></tr><tr><td>15</td><td>NC</td><td>NC</td><td>16</td></tr><tr><td>17</td><td>NC</td><td>GND</td><td>18</td></tr><tr><td>19</td><td>NC</td><td>NC</td><td>20</td></tr><tr><td>21</td><td>P5V</td><td>NC</td><td>22</td></tr><tr><td>23</td><td>NC</td><td>NC</td><td>24</td></tr><tr><td>25</td><td>NC</td><td>P3V3</td><td>26</td></tr><tr><td>27</td><td>NC</td><td>NC</td><td>28</td></tr><tr><td>29</td><td>GND</td><td>NC</td><td>30</td></tr><tr><td>31</td><td>NC</td><td>NC</td><td>32</td></tr><tr><td>33</td><td>NC</td><td>GND</td><td>34</td></tr><tr><td>35</td><td>NC</td><td>NC</td><td>36</td></tr><tr><td>37</td><td>P5V</td><td>NC</td><td>38</td></tr><tr><td>39</td><td>NC</td><td>NC</td><td>40</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td><td>42</td></tr><tr><td>43</td><td>NC</td><td>NC</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>NC</td><td>46</td></tr><tr><td>47</td><td>NC</td><td>NC</td><td>48</td></tr><tr><td>49</td><td>NC</td><td>GND</td><td>50</td></tr><tr><td>51</td><td>NC</td><td>NC</td><td>52</td></tr><tr><td>53</td><td>P5V</td><td>NC</td><td>54</td></tr><tr><td>55</td><td>NC</td><td>NC</td><td>56</td></tr><tr><td>57</td><td>NC</td><td>P3V3</td><td>58</td></tr><tr><td>59</td><td>NC</td><td>NC</td><td>60</td></tr><tr><td>61</td><td>NC</td><td>NC</td><td>62</td></tr><tr><td>63</td><td>NC</td><td>NC</td><td>64</td></tr></table>

![64\n63\n2\n1](.cpci-6870-50-15069-1010-201-en/00068f213083d60b379040fba91f7dd8f5b78e8212c22a7705d2d2ef27f8e5d8.jpg)

Table 4-16: PIM Connector (JN2-R) Pin Definition

CompactFlash Connector

<table><tr><td>Signal Name</td><td>Pin#</td><td>Pin#</td><td>Signal Name</td></tr><tr><td>GND</td><td>1</td><td>26</td><td>GND</td></tr><tr><td>DD3</td><td>2</td><td>27</td><td>DD11</td></tr><tr><td>DD4</td><td>3</td><td>28</td><td>DD12</td></tr><tr><td>DD5</td><td>4</td><td>29</td><td>DD13</td></tr><tr><td>DD6</td><td>5</td><td>30</td><td>DD14</td></tr><tr><td>DD7</td><td>6</td><td>31</td><td>DD15</td></tr><tr><td>CS1J</td><td>7</td><td>32</td><td>CS3J</td></tr><tr><td>GND</td><td>8</td><td>33</td><td>GND</td></tr><tr><td>GND</td><td>9</td><td>34</td><td>SDIORJ</td></tr><tr><td>GND</td><td>10</td><td>35</td><td>SDIOWJ</td></tr><tr><td>GND</td><td>11</td><td>36</td><td>5V</td></tr><tr><td>GND</td><td>12</td><td>37</td><td>IRQ15</td></tr><tr><td>5V</td><td>13</td><td>38</td><td>5V</td></tr><tr><td>GND</td><td>14</td><td>39</td><td>PCSEL</td></tr><tr><td>GND</td><td>15</td><td>40</td><td>NC</td></tr><tr><td>GND</td><td>16</td><td>41</td><td>BRSTDRVJ</td></tr><tr><td>GND</td><td>17</td><td>42</td><td>SDIORDY</td></tr><tr><td>DA2</td><td>18</td><td>43</td><td>NC</td></tr><tr><td>DA1</td><td>19</td><td>44</td><td>SDACKJ</td></tr><tr><td>DA0</td><td>20</td><td>45</td><td>IDEACTJ</td></tr><tr><td>DD0</td><td>21</td><td>46</td><td>DIAG</td></tr><tr><td>DD1</td><td>22</td><td>47</td><td>DD8</td></tr><tr><td>DD2</td><td>23</td><td>48</td><td>DD9</td></tr><tr><td>IOIS16J</td><td>24</td><td>49</td><td>DD10</td></tr><tr><td>GND</td><td>25</td><td>50</td><td>GND</td></tr></table>

![1\n26\n25\n50](.cpci-6870-50-15069-1010-201-en/96a7ce02f4923da0802d5de912c6855b2d711089f8548fe37eb82cbd4d3087a6.jpg)

Table 4-17: CompactFlash Connector Pin Definition

DB-6920SAT/CF Connector (CN3, CN6-R)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>GND</td><td>1</td><td>2</td><td>GND</td></tr><tr><td>GND</td><td>3</td><td>4</td><td>GND</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>GND</td><td>13</td><td>14</td><td>GND</td></tr><tr><td>GND</td><td>15</td><td>16</td><td>GND</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>GND</td><td>19</td><td>20</td><td>GND</td></tr><tr><td>GND</td><td>21</td><td>22</td><td>GND</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>GND</td></tr><tr><td>GND</td><td>27</td><td>28</td><td>GND</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>P3V3</td><td>31</td><td>32</td><td>P5V</td></tr><tr><td>P3V3</td><td>33</td><td>34</td><td>P5V</td></tr><tr><td>P3V3</td><td>35</td><td>36</td><td>P5V</td></tr><tr><td>P3V3</td><td>37</td><td>38</td><td>P5V</td></tr><tr><td>P1V8</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>P1V8</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>P1V8</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>GND</td><td>45</td><td>46</td><td>GND</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>SATA-TXN0</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>SATA-TXP0</td></tr><tr><td>SATA-RXN0</td><td>51</td><td>52</td><td>GND</td></tr><tr><td>SATA-RXP0</td><td>53</td><td>54</td><td>GND</td></tr><tr><td>GND</td><td>55</td><td>56</td><td>RESET#</td></tr><tr><td>GND</td><td>57</td><td>58</td><td>GND</td></tr><tr><td>GND</td><td>59</td><td>60</td><td>GND</td></tr></table>

![1\n2\n59\n60](.cpci-6870-50-15069-1010-201-en/9bac6725d90727dfc37865af57ed15ba27e0cc1c831fdaed9ee1c71b5bff26fe.jpg)

Table 4-18: DB-6920SAT/CF Connector Pin Definition

DB-R6000L2 Connector (CN14-R)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>SATA-T1P</td><td>1</td><td>2</td><td>USB-P3</td></tr><tr><td>SATA-T1N</td><td>3</td><td>4</td><td>USB-N3</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>SATA-R1P</td><td>7</td><td>8</td><td>USB-OC3#</td></tr><tr><td>SATA-R1N</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>GND</td><td>13</td><td>14</td><td>USB-P2</td></tr><tr><td>HAD_RST-L</td><td>15</td><td>16</td><td>USB-N2</td></tr><tr><td>HAD_SYNC</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>HAD_SDOUT</td><td>19</td><td>20</td><td>USB-OC2#</td></tr><tr><td>HAD_BIT_CLK</td><td>21</td><td>22</td><td>GND</td></tr><tr><td>HAD_SDIN0</td><td>23</td><td>24</td><td>PS2-KBC</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>PS2-KBD</td></tr><tr><td>HAD_SDIN1</td><td>27</td><td>28</td><td>PS2-MSD</td></tr><tr><td>HAD_SDIN2</td><td>29</td><td>30</td><td>PS2-MSC</td></tr><tr><td>HAD_SDIN3</td><td>31</td><td>32</td><td>GND</td></tr><tr><td>GND</td><td>33</td><td>34</td><td>RESET#</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>GND</td></tr><tr><td>GND</td><td>37</td><td>38</td><td>GND</td></tr><tr><td>GND</td><td>39</td><td>40</td><td>GND</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>GND</td></tr><tr><td>GND</td><td>43</td><td>44</td><td>GND</td></tr><tr><td>GND</td><td>45</td><td>46</td><td>GND</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>GND</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>GND</td></tr><tr><td>P5V</td><td>51</td><td>52</td><td>P1V8</td></tr><tr><td>P5V</td><td>53</td><td>54</td><td>P1V8</td></tr><tr><td>P5V</td><td>55</td><td>56</td><td>P1V8</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>NC</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>NC</td></tr><tr><td>GND</td><td>61</td><td>62</td><td>GND</td></tr></table>

![2\n1\n61\n62\n60\n59](.cpci-6870-50-15069-1010-201-en/b2968940c86a92d2fe9cfa7bc97961d5b88b97ea7fe0e4e83da884fdb3af48f6.jpg)

Table 4-19: DB-R6000L2 Connector Pin Definition

CompactPCI J1 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK#</td><td>+5V</td><td>TMS#</td><td>NC</td><td>TDI#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>IRQA#</td><td>IRQB#</td><td>IRQC#</td><td>+5V</td><td>IRQD#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>+5V_IPMB</td><td>HEALTHY#</td><td>V(I/O)</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>RESET#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>+3.3V</td><td>CLK0</td><td>AD31</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD30</td><td>AD29</td><td>AD28</td><td>GND</td><td>AD27</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD26</td><td>GND</td><td>V(I/O)</td><td>AD25</td><td>AD24</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CBE3#</td><td>IDSEL</td><td>AD23</td><td>GND</td><td>AD22</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD21</td><td>GND</td><td>+3.3V</td><td>AD20</td><td>AD19</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD18</td><td>AD17</td><td>AD16</td><td>GND</td><td>CBE2#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BDSEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>PCIXCAP</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>CBE1#</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD15</td><td>AD14</td><td>GND</td><td>AD13</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD12</td><td>GND</td><td>VIO</td><td>AD11</td><td>AD10</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD9</td><td>AD8</td><td>M66EN</td><td>CBE0#</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD7</td><td>GND</td><td>+3.3V</td><td>AD6</td><td>AD5</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD4</td><td>AD3</td><td>+5V</td><td>AD2</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD1</td><td>+5V</td><td>V(I/O)</td><td>AD0</td><td>ACK64#</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr></table>

Table 4-20: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>NC</td><td>CBE7#</td><td>GND</td><td>CBE6#</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>CBE5#</td><td>GND</td><td>V(I/O)</td><td>CBE4#</td><td>PAR64</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD63</td><td>AD62</td><td>AD61</td><td>GND</td><td>AD60</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD59</td><td>GND</td><td>V(I/O)</td><td>AD58</td><td>AD57</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD56</td><td>AD55</td><td>AD54</td><td>GND</td><td>AD53</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD52</td><td>GND</td><td>V(I/O)</td><td>AD51</td><td>AD50</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD49</td><td>AD48</td><td>AD47</td><td>GND</td><td>AD46</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD45</td><td>GND</td><td>V(I/O)</td><td>AD44</td><td>AD43</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD42</td><td>AD41</td><td>AD40</td><td>GND</td><td>AD39</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD38</td><td>GND</td><td>V(I/O)</td><td>AD37</td><td>AD36</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD35</td><td>AD34</td><td>AD33</td><td>GND</td><td>AD32</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>DEG#</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>GND</td><td>RSTBTN#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr></table>

Table 4-21: CompactPCI J2 Connector Pin Definition

CompactPCI J3 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>HDA_RST#</td><td>HDA_SYNC</td><td>HDA_BIT_CLK</td><td>HDA_SDOUT</td><td>HDA_SDIN0</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>HDA_SDIN1</td><td>HDA_SDIN2</td><td>NC</td><td>HDA_DOCK_EN#</td><td>HAD_DOCK_RST#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>KBDATA</td><td>KBCLK</td><td>NC</td><td>MSDATA</td><td>MSCLK</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>SATA-TX3+</td><td>SATA-TX3-</td><td>GND</td><td>SATA-TX2+</td><td>SATA-TX2-</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>SATA-RX3+</td><td>SATA-RX3-</td><td>GND</td><td>SATA-RX2+</td><td>SATA-RX2-</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>COM4-TX</td><td>COM4-RX</td><td>COM3-DCD#</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>COM3-RX</td><td>COM3-TX</td><td>COM3-DTR#</td><td>COM3-DSR#</td><td>COM3-RTS#</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>COM3-CTS#</td><td>COM3-RI#</td><td>RGB-BLUE</td><td>RGB-RED</td><td>RGB-GREEN</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>USB-OC3#</td><td>RGB-DDCCLK</td><td>RGB-DDCDAT</td><td>RGB-HSYNC</td><td>RGB-VSYNC</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>USB-P3+</td><td>USB-P3-</td><td>GND</td><td>USB-P4+</td><td>USB-P4-</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>USB-P5+</td><td>USB-P5-</td><td>GND</td><td>USB-P6+</td><td>USB-P6-</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>USB-P7+</td><td>USB-P7-</td><td>GND</td><td>USB-P8+</td><td>USB-P8-</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>USB-OC4#</td><td>USB-OC5#</td><td>USB-OC6#</td><td>USB-OC7#</td><td>USB-OC8#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>LAND_TXD1+</td><td>LAND_TXD1-</td><td>GND</td><td>LAND_TXD3+</td><td>LAND_TXD3-</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>LAND_TXD0+</td><td>LAND_TXD0-</td><td>GND</td><td>LAND_TXD2+</td><td>LAND_TXD2-</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LANC_TXD1+</td><td>LANC_TXD1-</td><td>GND</td><td>LANC_TXD3+</td><td>LANC_TXD3-</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LANC_TXD1+</td><td>LANC_TXD0-</td><td>GND</td><td>LANC_TXD2+</td><td>LANC_TXD2-</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>P5V</td><td>P5V</td><td>P12V</td><td>P5V</td><td>P5V</td><td>GND</td></tr></table>

Table 4-22: CompactPCI J3 Connector Pin Definition

![High Definition audio\nKeyboard/Mouse\nSerial ATA\nSerial ports\nUSB ports\nEthernet ports\nRGB](.cpci-6870-50-15069-1010-201-en/7f760cf442eb9d18bff19875c5c7cad97741da0515b6e0dafceed9388c70be92.jpg)

CompactPCI J4 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>PMC IO:61</td><td>PMC IO:63</td><td>NC</td><td>PMC IO:62</td><td>PMC IO:64</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PMC IO:57</td><td>PMC IO:59</td><td>NC</td><td>PMC IO:58</td><td>PMC IO:60</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>PMC IO:53</td><td>PMC IO:55</td><td>NC</td><td>PMC IO:54</td><td>PMC IO:56</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>PMC IO:49</td><td>PMC IO:51</td><td>NC</td><td>PMC IO:50</td><td>PMC IO:52</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>PMC IO:45</td><td>PMC IO:47</td><td>NC</td><td>PMC IO:46</td><td>PMC IO:48</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>PMC IO:41</td><td>PMC IO:43</td><td>NC</td><td>PMC IO:42</td><td>PMC IO:44</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>PMC IO:37</td><td>PMC IO:39</td><td>NC</td><td>PMC IO:38</td><td>PMC IO:40</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>PMC IO:33</td><td>PMC IO:35</td><td>NC</td><td>PMC IO:34</td><td>PMC IO:36</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>15</td><td>GND</td><td>PMC IO:29</td><td>PMC IO:31</td><td>NC</td><td>PMC IO:30</td><td>PMC IO:32</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PMC IO:25</td><td>PMC IO:27</td><td>NC</td><td>PMC IO:26</td><td>PMC IO:28</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PMC IO:21</td><td>PMC IO:23</td><td>NC</td><td>PMC IO:22</td><td>PMC IO:24</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PMC IO:17</td><td>PMC IO:19</td><td>NC</td><td>PMC IO:18</td><td>PMC IO:20</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PMC IO:13</td><td>PMC IO:15</td><td>NC</td><td>PMC IO:14</td><td>PMC IO:16</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>PMC IO:9</td><td>PMC IO:11</td><td>NC</td><td>PMC IO:10</td><td>PMC IO:12</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>PMC IO:5</td><td>PMC IO:7</td><td>NC</td><td>PMC IO:6</td><td>PMC IO:8</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>PMC IO:1</td><td>PMC IO:3</td><td>NC</td><td>PMC IO:2</td><td>PMC IO:4</td><td>GND</td></tr></table>

Table 4-23: CompactPCI J4 Connector Pin Definition

CompactPCI J5 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>PCIE-TX0+</td><td>PCIE-TX0+</td><td>GND</td><td>PCIE-RX0+</td><td>PCIE-RX0-</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PCIE-TX1+</td><td>PCIE-TX1-</td><td>GND</td><td>PCIE-RX1+</td><td>PCIE-RX1-</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PCIE-TX2+</td><td>PCIE-TX2-</td><td>GND</td><td>PCIE-RX2+</td><td>PCIE-RX2-</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>PCIE-TX3+</td><td>PCIE-TX3-</td><td>GND</td><td>PCIE-RX3+</td><td>PCIE-RX3-</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>PCIE-CLK+</td><td>PCIE-CLK-</td><td>GND</td><td>RESET#</td><td>RTM_IN#</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>GND</td><td>GND</td><td>RTC</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>LVDS_DATA3-</td><td>LVDS_DATA3+</td><td>NC</td><td>LVDS_CLK</td><td>LVDS_DATA</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>GPIO1</td><td>GPIO2</td><td>GPIO3</td><td>GPIO4</td><td>GPIO5</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>LAND_100#</td><td>LANC_100#</td><td>NC</td><td>LANC_1G#</td><td>LAND_1G#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>NC</td><td>GPIO6</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>MTR0#</td><td>INDEX#</td><td>GPIO7</td><td>NC</td><td>DENSEL#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>DIR#</td><td>NC</td><td>GPIO8</td><td>DRVA#</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>TRK0#</td><td>WGATE#</td><td>DETECT#</td><td>WDATA#</td><td>STEP#</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>DSKCHG#</td><td>HDSEL#</td><td>NC</td><td>RDATA#</td><td>WRPORT#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>LVDS_DATA0-</td><td>LVDS_DATA0+</td><td>GND</td><td>LVDS_DATA1-</td><td>LVDS_DATA1+</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>LVDS_DATA2-</td><td>LVDS_DATA2+</td><td>GND</td><td>LVDS_CLK-</td><td>LVDS_CLD+</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>LAND_LINK_ACT#</td><td>+3.3V</td><td>LANC_LINK_ACT#</td><td>+3.3V</td><td>GND</td></tr></table>

Table 4-24: CompactPCI J5 Connector Pin Definition

![PCI-Express x4\nGPIO\nFloppy\nEthernet port\nLVDS](.cpci-6870-50-15069-1010-201-en/65e15eff08c8b6b5f220b0ce43d4fe98a12e237582df9e13b8407c7af4da3178.jpg)

# 4.4 Switch and Jumper Settings

# Mode Switch (SW2)

Switch SW2 is a multi purpose switch that allows users to define the board operating mode. Four pins independently control the mode setting. All are set to OFF by default.

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/28a1eda4645b1e087d41d6687d1a5f78bbd415f5852c9036b753bfca9477dd0c.jpg)

<table><tr><td>Pin#</td><td>Status</td><td>Description</td></tr><tr><td rowspan="2">1</td><td>OFF</td><td>Universal Mode: The cPCI-6870 in a peripheral slot has CompactPCI bus communication with the host board in the system slot. The cPCI-6870 can boot-up in a peripheral slot and be recognized by the host board in the system slot as a PCI device.</td></tr><tr><td>ON</td><td>Satellite Mode: The cPCI-6870 in a peripheral slot has no CompactPCI bus communication with the host board in the system slot. The cPCI-6870 behaves a as standalone blade in the peripheral slot.</td></tr><tr><td rowspan="2">2</td><td>OFF</td><td>When the system does not include a CMM (Chassis Management Module), set this pin to OFF to allow IPMI to run in &quot;without CMM mode&quot;.</td></tr><tr><td>ON</td><td>When the system includes a CMM, set this pin to ON to allow IPMI to run in &quot;with CMM mode&quot;.</td></tr><tr><td rowspan="2">3</td><td>OFF</td><td>The cPCI-6870 cannot boot-up when installed in a peripheral slot if there is no host board in the system slot.</td></tr><tr><td>ON</td><td>The cPCI-6870 is able to boot-up when installed in a peripheral slot if there is no host board in the system slot. The cPCI-6870 behaves as a system board in all slots. (Set this pin to &quot;ON&quot; if the cPCI-6870 is installed in a blade server backplane).</td></tr><tr><td rowspan="2">4</td><td>OFF</td><td>The cPCI-6870 power on/off state is controlled by the ejector handle state.</td></tr><tr><td>ON</td><td>Force the ejector handle state to &quot;closed&quot;.</td></tr></table>

Table 4-25: Mode Switch Settings

# Clear CMOS Switch (SW4)

Press switch SW4 to clear the CMOS and reset the CMOS values to default.

![The image displays a simple diagram featuring a black rectangle on the left. A red arrow points to the right, leading to a larger black rectangle. At the bottom right corner, there are white markings or illegible text.](.cpci-6870-50-15069-1010-201-en/0b00698478cdccc27c7f5d2fa6832f463f1b6e1f565dd8c9d84e3eb431e28556.jpg)

# PMC Clock Switch (SW1)

Switch SW1 sets the PCI bus clock of the two PMC sites. All are set OFF by default.

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/5b4d32eb7f417875e4f2da8ee3f6ab2c22091ab5bb0ce24f5a968c1519387cfd.jpg)

<table><tr><td>Mode</td><td>1</td><td>2</td><td>3</td><td>4</td></tr><tr><td>PCI-X 133MHz</td><td>OFF</td><td>OFF</td><td>OFF</td><td>OFF</td></tr><tr><td>PCI-X 100MHz</td><td>OFF</td><td>OFF</td><td>OFF</td><td>ON</td></tr><tr><td>PCI-X 66MHz</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>PCI 66MHz</td><td>ON</td><td>ON</td><td>ON</td><td>OFF</td></tr><tr><td>PCI 33MHz</td><td>ON</td><td>OFF</td><td>ON</td><td>OFF</td></tr></table>

Table 4-26: PMC Clock Switch Settings

# PMC V(I/O) Switch (SW5)

Switch SW5 sets the signaling voltage of the two PMC sites.

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/7f1952ae78f2f6ad94952c7dd7c4ff088dc5a1c54e76f75359353137a790ba8a.jpg)

<table><tr><td>Mode</td><td>1</td><td>2</td><td>3</td><td>4</td></tr><tr><td>PMC V(I/O) = 5V</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td>PMC V(I/O) = 3.3V</td><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td></tr></table>

Table 4-27: PMC V(I/O) Switch Settings

# COM1/Debug Switch (SW9, SW10 pins 1-2)

Switches SW9 and SW10 (pins 1, 2) set the RJ-45 serial port (CN11) as a standard RS-232 serial port or as an IPMI debugging port.

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/d86566744c2869244090e3ac3d1b08ac19709bdc763fae2889b8689a8966fd68.jpg)

SW9

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/dd3827b395c28dfaa15c2db4b3629a0da1a706d1dea3103495cde42df0a31f50.jpg)

SW10

<table><tr><td rowspan="2">Mode</td><td colspan="4">SW9</td><td colspan="2">SW10</td></tr><tr><td>1</td><td>2</td><td>3</td><td>4</td><td>1</td><td>2</td></tr><tr><td>RS-232 COM port (default)</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td><td>ON</td><td>OFF</td></tr><tr><td>IPMI debugging port</td><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td><td>OFF</td><td>ON</td></tr></table>

Table 4-28: COM1/Debug Switch Settings

# Front/Rear VGA Selection Switch (SW10 pins 3-4)\*

Switch SW10 (pins 3, 4) sets the VGA output to the front panel RJ-45 port (CN11) or the VGA port on the RTM. The default VGA output is set to rear I/O. To enable Front VGA output, the COM/VGA Mode Selection Switches (SW7-8, SW12-13)\* must be set to VGA mode.

![ON\n1 2 3 4](.cpci-6870-50-15069-1010-201-en/2634e1ffa64e7cf025ad19f5f76c683767db4f9a29680f31c59998b98d44ea3b.jpg)

<table><tr><td>Mode</td><td>3</td><td>4</td></tr><tr><td>Rear VGA output (default)</td><td>ON</td><td>OFF</td></tr><tr><td>Front VGA output</td><td>OFF</td><td>ON</td></tr></table>

Table 4-29: Front/Rear VGA Selection Switch Settings

![The image displays a white sheet of paper with a folded top-right corner and faint horizontal lines running across it. A large, bold red checkmark is superimposed over the document, angled from the bottom left to the top right.](.cpci-6870-50-15069-1010-201-en/0510eba449861ae1ce3ed9feb065736ee517673ba8e25b0e3a58253ab9c99bc6.jpg)
NOTE:

\*VGA is not supported the front panel RJ-45 connector (CN11) of models with ordering numbers ending in "xx30" and higher. On these models, SW10 is set to "Rear VGA output" and the RJ-45 connector is a dedicated serial port.

# COM/VGA Mode Selection Switches (SW7-8, SW12-13)\*

The front panel RJ-45 port (CN11) is designed to support RS-232 or VGA output by connecting separate adapter cables. CN11 is set to RS-232 COM port by default. Please note that if VGA mode is selected, switch SW10 should be set to Front VGA mode.

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/c978306ccae8f693b7684d470b5d7f970872f001dc84ddc63895310c74c68c93.jpg)

SW7

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/9802e1a76e5ee8587f69bf3b16c619aefc14af90b09575fdd7b614eb1c4245a6.jpg)

SW8

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/3f29a8ad17371493080aa3fa5ff15ce18593718fa8e1e1db1b73bf719ef0a110.jpg)

SW12

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/ac8aa65f7cbd68fd0ce87eb226c0b361e28a9f24ef4d2337d16b1232d6682821.jpg)

SW13

<table><tr><td>Mode</td><td>SW7, SW8</td><td>SW12, SW13</td></tr><tr><td>COM Mode</td><td>All OFF</td><td>All ON</td></tr><tr><td>VGA Mode</td><td>All ON</td><td>All OFF</td></tr></table>

Table 4-30: COM/VGA Mode Selection Switch Settings

![A white document icon with horizontal lines and a folded top-left corner, featuring a large red checkmark superimposed over it.](.cpci-6870-50-15069-1010-201-en/ee7a3d36fdc287a7acdb212bc5d0d0fa0cba5ec46e2dc4b0c8305aba70b38acf.jpg)
NOTE:

\*VGA is not supported the front panel RJ-45 connector (CN11) of models with ordering numbers ending in "xx30" and higher. On these models, VGA is directly routed to the RTM, the RJ-45 connector is a dedicated serial port, switches SW7-8 and SW12-13 are not installed.

# PICMG 2.16 Switches (SW1-R, SW2-R, SW3-R, SW4-R)

The RTM supports GbE3 and GbE4 on either the 2.16 backplane or via rear I/O. The PICMG® 2.16 backplane and rear I/O cannot be accessed simultaneously. Switches SW1-R to SW4-R must be set to connect GbE3 and GbE4 to either the 2.16 backplane or to the RTM. The following table shows how to set the switches to enable GbE3 and GbE4 for either the 2.16 backplane or the RTM. All switches are set to ON by default (rear I/O).

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/a134e7e2028644f0f79debda14ac58ad10489eec61e6dbc9ec9dc9f8c1389419.jpg)

SW1-R

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/0df8bde2177b0575b7f40fecf48f4544c3751bf2f03e3b04e5f216efacdcb997.jpg)

SW2-R

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/80ea9c55bc8a03815e00ed8dab5481ceb18bc5ae091e1e4d8fd5e66b85e64ef2.jpg)

SW3-R

![1\n2\n3\n4\nON](.cpci-6870-50-15069-1010-201-en/2f2e50c6861e21f616572619edb9e2fe8af5aad61132e7808888eac93135ff97.jpg)

SW4-R

<table><tr><td>Connect GbE3/4 to</td><td>GbE3(SW1-R, SW2-R)</td><td>GbE4(SW3-R, SW4-R)</td></tr><tr><td>PICMG® 2.16 Backplane</td><td>All OFF</td><td>All OFF</td></tr><tr><td>Rear faceplate RJ-45 connectors (default)</td><td>All ON</td><td>All ON</td></tr></table>

Table 4-31: PICMG 2.16 Switch Settings

# IPMC Mode Switch (SW6)

Switch SW6 is for debugging-purpose only and set to All OFF by default. Please do NOT change settings.

# 5 Getting Started

This chapter describes the installation of the following components to the cPCI-6870 and rear transition modules:

▶ Memory module
▶ 2.5" SATA hard drive
▶ CompactFlash card
▶ cPCI-6870 CPU module installation to chassis
▶ RTM installation to chassis

# 5.1 Memory Module Installation

The cPCI-6870 Series supports dual channel DDR3-800/1066 memory in two 200-pin SO-DIMM sockets.

# Installing the Memory Module

1. Align the notch in the memory module with the key on the SO-DIMM slot.
2. Press down on the module until it is properly seated in the socket.

# 5.2 Hard Drive Installation

The cPCI-6870 and cPCI-R6001D provide space to install a slim type 2.5" Serial-ATA hard drive.

# Installing a SATA Hard Drive - cPCI-6870

![The image displays a digital icon representing a document. It features a white sheet of paper with faint horizontal lines and a folded upper-right corner. A large, thick red checkmark is superimposed over the left side of the paper.](.cpci-6870-50-15069-1010-201-en/2e378afb589c86812fade38b000655f030a507313b53836449804c0a53416b60.jpg)
NOTE:

Install a CF card to the cPCI-6870 before installing the hard drive (see “Installing a CF card – cPCI-6870” on page 52).

1. Attach the DB-6920SAT adapter board to the SATA hard drive connectors. Position the hard drive on the HDD bracket provided as shown below. Be sure the adapter board is under HDD bracket to avoid damaging the hard drive connectors.

![HDD Bracket\nDB-6920SAT\nSATA HDD](.cpci-6870-50-15069-1010-201-en/631a033c22144ba4bdf493eff2c74e5fadb34390f4dfdd1f2c853be733179cf3.jpg)

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point centered vertically and horizontally.](.cpci-6870-50-15069-1010-201-en/c1a1ff01ffd2f1121f9769a11fd1d8b4a16855ce77a1f80cb1eefab18be348fa.jpg)
CAUTION:

Make sure the adapter board is under the HDD bracket to avoid damaging the hard drive connectors.

2. Secure the HDD to the bracket with four screws provided.

![Close-up of a hard disk computer chassis with red arrows pointing to its top panel (no visible text or symbols)](.cpci-6870-50-15069-1010-201-en/e904d5647d37f56b62ec9e386d0d75d3a27156b1cf8792419f3a28e421269082.jpg)

3. Position the hard drive assembly on the cPCI-6870 so that the standoffs are aligned with the screw holes on the board, and the connector on the DB-6920SAT adapter board is aligned with the board-to-board connector (CN3).

![S/N:\n9748EA3010\nI/O\nPNC setting\nP21133 PNC OFF OFF OFF OF (167AOUT)\nP21168 PNC OFF OFF OFF\nP21153 PNC OFF OFF OFF\nP21153 PNC ON OFF ON OFF\nP21153 PNC ON OFF ON\nP21153 PNC frequency setting\nP21153 PNC OFF OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC OFF OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON OFF\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC ON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC CON\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC Con\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNCCON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNC CON\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCon\nP21153 PNCCON\nP21153 PNCCON\nP21153 PNCCON\nP21153 PNCCON\nP2. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0.\nCE](.cpci-6870-50-15069-1010-201-en/a003eb88f30d74edd5d6e4106b5c268e592a08f50897e99683ed84deb696ced0.jpg)

4. Press the DB-6920SAT adapter onto the board-to-board connector until it is properly seated. Secure the adapter to the board with the two screws provided.

![Close-up of an electronic device with a red arrow pointing to a component, mounted on a circuit board (no readable text or symbols)](.cpci-6870-50-15069-1010-201-en/96464107c1ff7689af8f7dc1edc7bff4a40bdeb2fc69746dc8ce69d185cef453.jpg)

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black, uppercase letters.](.cpci-6870-50-15069-1010-201-en/8c4b96f36f141c48d007e754cbb63c5bd1eb09e1dc1a3ad67d494917a510453f.jpg)

Support the hard drive assembly when turning the board over to proceed with step 5.

5. Secure the hard drive with two screws from the solder side of the board.

![Close-up of a green printed circuit board with multiple electronic components and red arrows indicating disassembly or repair (no readable text or symbols)](.cpci-6870-50-15069-1010-201-en/a158d7b435f97b1e65cb38dcb66d28311f5cf34fafe632d45164bc351add4c71.jpg)

# Removing the SATA Hard Drive - cPCI-6870

Reverse steps 5 through 1 above to remove the SATA hard drive.

![This image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.cpci-6870-50-15069-1010-201-en/1747e7c08b146a0e8d0bde2fd01ca116e3d28edaa5fcbe9cf10670c7bd5901af.jpg)

When removing the hard drive, be careful to hold the adapter board and lift upwards in a vertical motion to disconnect it from the board-to-board connector. This will avoid damaging the adapter board and connectors.

# 5.3 CompactFlash Card Installation

The cPCI-6870 has an onboard CompactFlash socket and the cPCI-R6001D RTM supports a removable CompactFlash socket in the same space as the 2.5" SATA HDD. Contact your sales representative to purchase a DB-CF-SA CompactFlash adapter kit for the cPCI-R6001D.

# Installing a CF card – cPCI-6870

Insert the CF card into the CF slot on the cPCI-6870 (CN4 - see Figure 4-1: cPCI-6870 SBC Board Layout). If necessary, first remove the hard drive assembly by reversing the steps described in “Installing a SATA Hard Drive - cPCI-6870” on page 48 above.

# 5.4 Installing the cPCI-6870 SBC to the Chassis

The cPCI-6870 may be installed in a system or peripheral slot of a 6U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.

2. Remove the blank face cover from the selected slot, if necessary.

3. Press down on the release catches of the cPCI-6870 ejector handles.

4. Remove the black plastic caps securing the mounting screws to the front panel.

5. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.

6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module front panel.

7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

# 5.5 Installing the RTM to the Chassis

The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-6870 Series and related RTMs, make sure the RTM is the correct matching model.

![The image displays a standard warning sign featuring a yellow triangle with a black border. Inside the triangle is a large black exclamation point. Directly below the triangle, the text 'CAUTION:' is printed in black, capital letters.](.cpci-6870-50-15069-1010-201-en/cfe3d5d3491a54d9b100a8bfe108a83da78e82ccebf5eafe5977c9eae04fc4ef.jpg)

You must install the correct RTM to enable functions (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs.

# 6 Driver Installation

The cPCI-6870 drivers can be found on the ADLINK All-In-One CD at X:\cPCI\cPCI-6870\, the cPCI-R6001(D) drivers can be found at X:cPCI\cPCI-R6001(D)\, or from the ADLINK website (http://www.adlinktech.com). ADLINK provides validated drivers for chipset, graphics, LAN, and SATA/AHCI on Windows XP Professional, Windows XP x64 Edition and Windows Vista x64 Edition.

# 6.1 Driver Installation Procedure

Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation. The driver installation procedures for Windows XP are described below.

1. Install the chipset driver by extracting and running the program in ...\Chipset
\Intel\_INF\_Update\_Utility\_WinAlIOS\_v9.0.0.1008.zip.

2. Install the graphics driver and utilities by extracting and running the program in ...\Graphics

\Intel\_Integrated\_Graphics\_WinXP32\_v14383.zip.

3. Install the LAN drivers by extracting and running the program in ...\LAN

\Intel\_Network\_Adapter\_WinXP32\_Win2000\_Win2003\_v14.0.zip.

4. Install the audio driver for RTM cPCI-R6001D by extracting and running the program in ...\\Audio\\Professional\

Realtek\_WDM\_Audio\_WinXP32\_Win2003\_v2.21.zip.

We recommend using the drivers provided on the ADLINK All-in-One CD or downloading them from the ADLINK website to ensure compatibility. Contact ADLINK to get support for VxWorks BSP.

![The image features a white document icon with faint gray horizontal lines near the bottom. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6870-50-15069-1010-201-en/0390965bd3b5d97bce3c40d783f0caa80676e2f10bf2f3b723eccdec8157bd9c.jpg)
NOTE:

SCSI is not supported on current model RTMs. If your RTM supports SCSI, refer to "SCSI Driver" on page 56.

# 6.2 SCSI Driver

![The image displays a white document icon with blue horizontal lines and a folded top-right corner, overlaid with a large red checkmark.](.cpci-6870-50-15069-1010-201-en/092260da6dbc414227c18b52e93a89730c63a491b21ff52d3a9181f5dfa55831.jpg)
NOTE:

SCSI is not supported on current model RTMs. If your RTM supports SCSI, follow the instructions below.

The SCSI driver is available from the ADLINK All-In-One CD at X:cPCI\cPCI-R6001(D)\SCSI or from the ADLINK website (http://www.adlinktech.com). The installation procedure for Windows XP is described below. It is not necessary to install the SCSI driver on Windows 2003 Server and Vista as it has a built-in driver.

1. Click Start, right-click on My Computer, then select Properties from the drop-down menu.
2. Click on the Hardware tab, then click Device Manager.
3. Right-click on the SCSI Controller item, then click Properties from the drop-down menu.
4. From the General tab, click Reinstall Driver.
5. Select Yes, this time only and click Next when the Upgrade Device Driver Wizard window appears.
6. Select Install from a list on specific location [Advanced], then click Next.
7. Uncheck Search removable media [floppy, CD-ROM...], and check Include this location in the search:, then click Browse.
8. Select the xp\_x86 folder from this directory on the ADLINK All-In-One CD: ...X:\cPCI\cPCI-R6001(D)\SCSI.
9. Click OK, then click Next.
10. Click Continue Anyway to go on, and click Finish to complete the installation.

# 7 Utilities

# 7.1 Watchdog Timer

This section describes the operation of the cPCI-6870's watchdog timer (WDT). The primary function of the WDT is to monitor the cPCI-6870's operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

▶ enabling and disabling
▶ reloading timeout value

The cPCI-6870 custom WDT circuit is implemented using the internal IO of the ITE Super I/O IT8783 which is at address 2Eh of LPC. The basic functions of the WDT include:

▶ Starting the timer countdown
▶ Enabling or disabling WDT
▶ Enabling or disabling WDT countdown LED ON
▶ Reloading the timeout value to keep the watchdog from timing out
▶ Setting the range of the timeout period from 1 to 65535 seconds or minutes
▶ Sending a RESET signal to the system when the watchdog times out

# Using the Watchdog in an Application

The following section describes using the WDT functions in an application. The WDT reset function is explained in the previous section. This can be controlled through the registers in the cPCI-6870's Super I/O.

An application using the reset feature enables the watchdog function, sets the count-down period, and reloads the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after its counter reaches zero.

For a detailed programming sample, refer to the sample code provided on the ADLINK All-In-One CD. You can find it in the following directory: X:\cPCI\cPCI-6870\WDT.

# Sample Code

The sample program written in C shown below offers an interactive way to test the Watchdog Timer under DOS.

```c
#include&lt;stdio.h&gt;
#include&lt;dos.h&gt;

#define IT8783_ID1 0x87
#define IT8783_ID2 0x83

static unsigned int IT8783_ioPort = 0x2e;

//Check index port
void Enter_IT8783_Config(unsigned int flag)
{
    if(flag) IT8783_ioPort = 0x4e;

    switch(IT8783_ioPort)
    {
    case 0x2E: //Address port = 0x2E, enter keys = 0x87, 0x01, 0x55, 0x55
    outportb(0x2E, 0x87);
    outportb(0x2E, 0x01);
    outportb(0x2E, 0x55);
    outportb(0x2E, 0x55);
    break;
    case 0x4E: //Address port = 0x4E, enter keys = 0x87, 0x01, 0x55, 0xAA
    outportb(0x4E, 0x87);
    outportb(0x4E, 0x01);
    outportb(0x4E, 0x55);
    outportb(0x4E, 0xAA);
    break;
    default:
    break;
    }
}
```

```txt
//Exit index port
void Exit_IT8783_Config(unsigned int flag)
{
    if(flag) IT8783_ioPort = 0x4e;

    outportb(IT8783_ioPort, 0x02);
    outportb(IT8783_ioPort+1, 0x02);
}

//Check chip
void Get_IT8783_ID(unsigned int &ID1, unsigned int &ID2)
{
    outportb(IT8783_ioPort, 0x20);
    ID1 = inportb(IT8783_ioPort+1);
    outportb(IT8783_ioPort, 0x21);
    ID2 = inportb(IT8783_ioPort+1);
}

//WDT and LED program
void IT8783_3_WDTRun(unsigned int count_value, unsigned int PLEDflag) //for cPCI-6870
{
    unsigned long tempCount;
    unsigned int registerValue;

    outportb(IT8783_ioPort, 0x07);
    outportb(IT8783_ioPort+1, 0x07);// Device 7

    outportb(IT8783_ioPort, 0xf8);
    outportb(IT8783_ioPort+1, 0x00);// PLED mapping to nothing, disable PLED function

    if(PLEDflag == 1)
    {
    outportb(IT8783_ioPort, 0x2D);
    registerValue = inportb(IT8783_ioPort + 1);
    registerValue |= 0x01; // set Pin109 is GPIO function GP60
    outportb(IT8783_ioPort+1, registerValue);

    outportb(IT8783_ioPort, 0xC5);
    registerValue = inportb(IT8783_ioPort + 1);
```

```solidity
registerValue &= 0xfe;    // set GP60 is alternate function
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0xCD);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0x01;    // set GP60 is output
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0xf8);
outportb(IT8783_ioPort+1, 0x30); // PLED mapping to GP60

outportb(IT8783_ioPort, 0xf9);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0x02;
registerValue &= 0xfb;
outportb(IT8783_ioPort+1, registerValue);
}
outportb(IT8783_ioPort, 0x71);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0xD0;    // set Mouse & Keyboard interrupt Enable
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0x73);
outportb(IT8783_ioPort+1, count_value);
// set WDT count LSB
tempCount = tempCount >> 8;
outportb(IT8783_ioPort, 0x74);
outportb(IT8783_ioPort+1, count_value);
// set WDT count MSB

if(count_value >= 60)
{
    outportb(IT8783_ioPort, 0x72);
    registerValue = importb(IT8783_ioPort+1);
    registerValue &= 0x8f;
    registerValue |= 0x10;    // enable WDT output through PowerOK!
    outportb(IT8783_ioPort+1, registerValue);
    // set WDT count is minute
```

```c
tempCount = count_value / 60;
if((count_value%60) > 30)
    tempCount++;
if(tempCount > 65535)
    tempCount = 65535;
printf("WDT timeout in %d minutes.\n", tempCount);
}
else
{
    outportb(IT8783_ioPort, 0x72);
    registerValue = importb(IT8783_ioPort+1);
    registerValue |= 0x80;

    tempCount = count_value;
    if(tempCount != 0)
    {
    printf("WDT timeout in %d seconds.\n", tempCount);
    registerValue |= 0x40; //Enable WDT output through KBRST
    }
    else
    {
    printf("WDT is Disabled.\n");
    registerValue &= 0xbf; //Disable WDT output through KBRST
    }

    outportb(IT8783_ioPort+1, registerValue);
    // set WDT count is second
}
```

# 7.2 Preboot Execution Environment (PXE)

The cPCI-6870 series supports the Intel® Preboot Execution Environment (PXE) that is capable of booting up or executing an OS installation through an Ethernet ports. To use PXE, there must be a DHCP server on the network with one or more servers running PXE and MTFTP services. It could be a Windows® 2003 server running DHCP, PXE, and MTFTP services or a dedicated DHCP server with one or more additional servers running PXE and MTFTP services.

To build a network environment with PXE support:

1. Setup a DHCP server with PXE tag configuration
2. Install the PXE and MTFTP services
3. Make a boot image file on the PXE server (i.e. the boot server)
4. Enable the PXE boot function on the client computer

# 8 BIOS Setup Utility

The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt; Press DEL to run Setup &gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.

![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST3B410A 007A](.cpci-6870-50-15069-1010-201-en/462851dfb0b5863bbb7965a156fa41e9075c0e2bd02d804a978f5a1ac49b35a6.jpg)

Note: In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="6">System Overview</td><td rowspan="8">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.</td></tr><tr><td colspan="6">AMIBIOS</td></tr><tr><td colspan="6">Version :08.00.15</td></tr><tr><td colspan="6">Build Date:03/11/10</td></tr><tr><td colspan="6">ID :C6870T08</td></tr><tr><td colspan="6">Processor</td></tr><tr><td colspan="6">Speed :255MHz</td></tr><tr><td colspan="6">Count :255</td></tr><tr><td colspan="6">System Memory</td><td rowspan="4">← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">Size :2013MB</td></tr><tr><td colspan="6">System Time [17:45:15]</td></tr><tr><td colspan="6">System Date [Tue 01/01/2002]</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

These keys include &lt;F1&gt;, &lt;F10&gt;, &lt;Enter&gt;, &lt;ESC&gt;, &lt;Arrow&gt; keys, and so on.

![The flowchart describes the navigation and interaction within a BIOS Setup Utility.\n\n**Blocks:**\n*   **BIOS Setup Utility**\n*   **Screens**\n*   **Left and Right Keys to Select a Setup Screen**\n*   **Screen 1**, **Screen 2**, **Screen 3**, **Screen 4**, **Screen 5**\n*   **Items**\n*   **Tab Key to Select Fields**\n*   **(± symbol in boxes)** (appearing in two rows of three boxes each)\n*   **± To Change Field Values**\n*   **Fields**\n*   **Up and Down Keys to Select a Setup Item**\n\n**Connections:**\n*   A downward arrow connects **BIOS Setup Utility** to **Screens**.\n*   A downward arrow connects **Screens** to a horizontal row of boxes: **Screen 1** ↔ **Screen 2** ↔ **Screen 3** ↔ **Screen 4** ↔ **Screen 5**.\n*   A dashed arrow connects **Left and Right Keys to Select a Setup Screen** to the area between Screen 1 and Screen 2.\n*   A downward arrow connects **Screens** to **Items**.\n*   Below **Items**, there is a row of three boxes containing the **±** symbol, connected by double-headed horizontal arrows.\n*   A dashed arrow connects **Tab Key to Select Fields** to the first box in the **Items** row.\n*   A dashed arrow connects **± To Change Field Values** to the boxes in the **Items** row.\n*   Vertical arrows (one pointing down, one pointing up) are situated between the top row of **±** boxes and the bottom row of **±** boxes.\n*   A bracket connects the label **Fields** to the bottom row of **±** boxes.\n*   A dashed arrow connects **Up and Down Keys to Select a Setup Item** to the vertical arrows.](.cpci-6870-50-15069-1010-201-en/e7d7111273c1acd8e841c00e4c02a81082a1a9b20b8835f4c2fa68da3ad3f947.jpg)

Note: There is a hot key legend located in the right frame on most setup screens.

The &lt; F8 &gt; key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the &lt; F8 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

# Hotkey Descriptions

F1 The &lt; F1 &gt; key allows you to display the General Help screen.

Press the &lt; F1 &gt; key to open the General Help screen.

![General Help\n↔ Select Screen ↓↑ Select Item\n+- Change Screen Enter Go to Sub Screen\nPGDN Next Page PGUP Previous Page\nHome Go to Top of the Screen End Go to Bottom of Screen\nF2/F3 Change Colors F7 Discard Changes\nF8 Load Failsafe Defaults F9 Load Optimal Defaults\nF10 Save and Exit ESC Exit\n(Ok)](.cpci-6870-50-15069-1010-201-en/a57c04e97a74cf9e7685001006b49b9db67551f5c5c1e770cb657e2f9e93f5ab.jpg)

F10 The &lt; F10 &gt; key allows you to save any changes you have made and exit Setup. Press the &lt; F10 &gt; key to save your changes. The following screen will appear:

![Save configuration changes and exit now?\n(Ok) (Cancel)](.cpci-6870-50-15069-1010-201-en/b423e5e9e8d082af65f319310c7e776dce9da37c4778c5bf071b67a7cce2aed5.jpg)

Press the &lt;Enter&gt; key to save the configuration and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

ESC The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. The following screen will appear:

![Discard changes and exit setup now?\n(Ok) (Cancel)](.cpci-6870-50-15069-1010-201-en/362b0f493b0cd00ff2d54705cad6edc9877c174cab9b4ee0e00cef0dd63d3649.jpg)

Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

Enter The &lt; Enter &gt; key allows you to display or change the setup option listed for a particular setup item. The &lt; Enter &gt; key can also allow you to display the setup sub-screens.

# 8.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="6">System Overview</td><td rowspan="3">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.</td></tr><tr><td colspan="6">AMIBIOS</td></tr><tr><td colspan="6">Version :08.00.15</td></tr><tr><td colspan="6">Build Date:03/11/10</td><td rowspan="5">Use [+] or [-] toconfigure system Time.</td></tr><tr><td colspan="6">ID :C6870T08</td></tr><tr><td colspan="6">Processor</td></tr><tr><td colspan="6">Speed :255MHz</td></tr><tr><td colspan="6">Count :255</td></tr><tr><td colspan="6">System Memory</td><td>← Select Screen</td></tr><tr><td rowspan="2" colspan="6">Size :2013MB</td><td>↑↓ Select Item</td></tr><tr><td>+- Change Field</td></tr><tr><td colspan="6">System Time [17:45:15]</td><td>Tab Select Field</td></tr><tr><td rowspan="3" colspan="6">System Date [Tue 01/01/2002]</td><td>F1 General Help</td></tr><tr><td>F10 Save and Exit</td></tr><tr><td>ESC Exit</td></tr></table>

# System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the &lt;Arrow&gt; keys. Enter new values using the keyboard. Press the &lt;Tab&gt; key or the &lt;Arrow&gt; keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

Note: The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

# 8.3 Advanced BIOS Setup

Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Advanced BIOS Setup screen is shown below.

The sub menus are described on the following pages.

<table><tr><td colspan="2">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td>CPU ConfigurationIDE ConfigurationSuperIO ConfigurationHardware Health ConfigurationRemote Access ConfigurationUSB Configuration</td><td>Configure CPU.← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# CPU Configuration

You can use this screen to select options for the CPU Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.

# BIOS SETUP UTILITY

# Advanced

# Configure advanced CPU settings

Module Version:3F.11

Manufacturer:Intel

Frequency :255MHz

FSB Speed :1068MHz

Cache L1 :0 KB

Cache L2 :0 KB

Ratio Actual Value:10

Core Multi-Processing

Intel(R) SpeedStep(tm) tech

[Enabled]

[Enabled]

When disabled, disable one execution core of each CPU die.

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Core Multi-Processing

This item enables/disables multi-core processing functionality for multi-core processors (default: Enabled).

# Intel®Speedstep™ Tech

Intel SpeedStep technology allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production (default: Enabled)..

# IDE Configuration

You can use this screen to select options for the IDE Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.

# Advanced

▶ Primary IDE Master
▶ Secondary IDE Master
▶ Third IDE Master
▶ Fourth IDE Master
: [Not Detected]
: [Not Detected]
: [Not Detected]
: [Not Detected]

While entering setup, BIOS auto detects the presence of IDE devices. This displays the status of auto detection of IDE devices.

← Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Super IO Configuration

You can use this screen to select options for the Super IO settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

Advanced

<table><tr><td>OnBoard Floppy Controller</td><td>[Enabled]</td><td rowspan="10">Allows BIOS to Enable or Disable Floppy Controller.</td></tr><tr><td>Floppy A</td><td>[1.44 MB 3 $\frac{1}{2}$ &quot;]</td></tr><tr><td>Serial Port1 Address</td><td>[3F8]</td></tr><tr><td>Serial Port1 IRQ</td><td>[4]</td></tr><tr><td>Serial Port2 Address</td><td>[2F8]</td></tr><tr><td>Serial Port2 IRQ</td><td>[10]</td></tr><tr><td>Serial Port3 Address</td><td>[3E8]</td></tr><tr><td>Serial Port3 IRQ</td><td>[3]</td></tr><tr><td>Serial Port4 Address</td><td>[2E8]</td></tr><tr><td>Serial Port4 IRQ</td><td>[11]</td></tr><tr><td></td><td></td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Onboard Floppy Controller

Options: Disabled, Enabled

# Floppy Drive A

You can use this screen to specify options for the floppy drive settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

Options: Disabled, 360 KB 5 $\frac{1}{4}$ ", 1.2 MB 5 $\frac{1}{4}$ ", 720 KB 3 $\frac{1}{2}$ ", 1.44 MB 3 $\frac{1}{2}$ ", 2.88 MB 3 $\frac{1}{2}$ ".

# Serial Port1/2/3/4 Address/IRQ

Select an address and a corresponding interrupt for serial ports 1-4.

Address Options: 3F8, 3E8, 2F8, 2E8.

IRQ Options: 3, 4, 10, 11

# Hardware Health Configuration

This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>Hardware Health Configuration</td><td rowspan="6"></td></tr><tr><td>Current CPU1 Temperature :57℃/134℉ System Temperature :57℃/134℉</td></tr><tr><td>+3.3Vin : 0.962 U</td></tr><tr><td>+5Vin : 1.552 U</td></tr><tr><td>+12Vin : 3.757 U</td></tr><tr><td>+1.5Vin : 0.662 U</td></tr><tr><td></td><td>← Select Screen ↑↓ Select Item F1 General Help F10 Save and Exit ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Remote Access Configuration

Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td colspan="2">Configure Remote Access type and parameters</td></tr><tr><td>Remote Access</td><td>[Enabled]</td></tr><tr><td>Serial port number</td><td>[COM1]</td></tr><tr><td>Base Address, IRQ</td><td>[3F8h, 4]</td></tr><tr><td>Serial Port Mode</td><td>[115200 8,n,1]</td></tr><tr><td>Flow Control</td><td>[None]</td></tr><tr><td>Redirection After BIOS POST</td><td>[Always]</td></tr><tr><td>Terminal Type</td><td>[ANSI]</td></tr><tr><td>UT-UTF8 Combo Key Support</td><td>[Enabled]</td></tr><tr><td>Sredir Memory Display Delay</td><td>[No Delay]</td></tr><tr><td></td><td></td></tr></table>

# Remote Access

Select this option to Enable or Disable the BIOS remote access feature.

![The image shows a white document icon with faint horizontal lines and a folded top-right corner. A large, red checkmark is superimposed on the document, running diagonally from the lower left to the upper right.](.cpci-6870-50-15069-1010-201-en/6894815ad88e4ee906ed468872c0ef2c7431f74f804210017bcd75c2c46eb10c.jpg)
NOTE:

Enabling Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot.

# Serial Port Number

Select the serial port you want to use for the remote access interface. You can set the value for this option to COM1 or COM2.

![The image shows a white document icon with a folded upper-right corner and faint horizontal lines running across the page. A large, red checkmark is superimposed over the document, angling upwards from the bottom left to the top right.](.cpci-6870-50-15069-1010-201-en/e960e77d1b05ce896f5e2741de13cc73fe0cb6f718c419a59234c9c03cd5f118.jpg)
NOTE:

If you have changed the resource assignment of the serial ports in Advanced> SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the Remote Access options.

# Serial Port Mode

Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1.

# Flow Control

Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software.

# Redirection After BIOS POST

This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.

▶ Disabled: Set this value to turn off the redirection after POST
▶ Boot Loader: Set this value to allow the redirection to be active during POST and Boot Loader.
▶ Always: Set this value to allow the redirection to be always active.

# Terminal Type

This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8.

# VT-UTF8 Combo Key Support

This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled and Disabled.

# Sredir Memory Display Delay

This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec.

# USB Configuration

You can use this screen to select options for the USB Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>USB Configuration</td><td>Options</td></tr><tr><td>Module Version - 2.24.5-13.4</td><td>Disabled</td></tr><tr><td>USB Devices Enabled :</td><td></td></tr><tr><td>1 Keyboard, 1 Mouse, 3 Drives</td><td>2 USB Ports</td></tr><tr><td></td><td>4 USB Ports</td></tr><tr><td>USB Functions [10 USB Ports]</td><td>6 USB Ports</td></tr><tr><td>USB 2.0 Controller [Enabled]</td><td>8 USB Ports</td></tr><tr><td>USB 2.0 Controller Mode [HiSpeed]</td><td>10 USB Ports</td></tr><tr><td>►USB Mass Storage Device Configuration</td><td>Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# USB Functions

Set this value to allow the system to Disable, Enable, and select a set number of onboard USB ports.

# USB 2.0 Controller

If USB Functions is set to Disabled, this option will have no effect. Setting this option to Enabled will allow USB 2.0 functionality to all USB ports.

# USB 2.0 Controller Mode

The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps).

# USB Mass Storage Device Configuration

This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>USB Mass Storage Device ConfigurationUSB Mass Storage Reset Delay [20 Sec]Device #1 USB Flash DiskEmulation Type [Auto]</td><td>Number of secondsPOST waits for theUSB mass storagedevice after startunit command.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# 8.4 Advanced PCI/PnP Settings

Select the PCI/PnP tab from the setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Plug and Play BIOS Setup screen is shown below.

<table><tr><td colspan="6">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td>IRQ3</td><td></td><td>[Reserved]</td><td></td><td rowspan="3">Available: SpecifiedIRQ is available to beused by PCI/PnPdevices.</td><td></td></tr><tr><td>IRQ4</td><td></td><td>[Reserved]</td><td></td><td></td></tr><tr><td>IRQ5</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ7</td><td></td><td>[Available]</td><td></td><td rowspan="7">Reserved: SpecifiedIRQ is reserved foruse by Legacy ISAdevices.</td><td></td></tr><tr><td>IRQ9</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ10</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ11</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ14</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ15</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>DMA Channel 0</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>DMA Channel 1</td><td></td><td>[Available]</td><td rowspan="5" colspan="3">← Select Screen↑↓ Select Item+ - Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td>DMA Channel 3</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 5</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 6</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 7</td><td></td><td>[Available]</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# IRQ/DMA Channel

Set this value to allow the IRQ/DMA channel settings to be modified.

▶ Available: This setting allows the specified IRQ/DMA channel to be used by a PCI/PnP device.
▶ Reserved: This setting allows the specified IRQ/DMA channel to be used by a legacy ISA device.

# 8.5 Boot Settings

Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys.

The Boot Settings screen is shown below:

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Boot Settings</td><td rowspan="4">Configure Settings during System Boot.</td></tr><tr><td colspan="5">▶ Boot Settings Configuration</td></tr><tr><td colspan="5">▶ Boot Device Priority</td></tr><tr><td colspan="5">▶ Removable Drives</td></tr><tr><td colspan="5"></td><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Boot Settings Configuration

Use this screen to select options for the Boot Settings Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Boot</td></tr><tr><td colspan="2">Boot Settings Configuration</td></tr><tr><td>Quick Boot</td><td>[Enabled]</td></tr><tr><td>Quiet Boot</td><td>[Disabled]</td></tr><tr><td>Bootup Num-Lock</td><td>[On]</td></tr><tr><td></td><td></td></tr></table>

# Quick Boot

Enabling this setting will cause the BIOS Power-On Self Test routine to skip some of its tests during bootup for faster system boot.

# Quiet Boot

When this feature is enabled, the BIOS will display the OEM logo during the boot-up sequence, hiding normal POST messages. When it is disabled, the BIOS will display the normal POST messages, instead of the OEM logo.

# Bootup Num-Lock

This option sets the Num Lock status when the system is powered on. Setting it to On will turn on the Num Lock key when the system is booted up. Setting it to Off will not enable the Num Lock key on bootup.

# Boot Device Priority

The items allow you to set the sequence of boot devices where BIOS attempts to load the disk operating system. First press &lt;Enter&gt; to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press &lt;+&gt;, &lt;-&gt; or &lt;PageUp&gt;, &lt;PageDown&gt; key to move it up/down in the priority list.

# Boot Device Groups

The Boot devices are listed in groups by device type. First press &lt;Enter&gt; to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press &lt;+&gt;, &lt;-&gt; or &lt;PageUp&gt;, &lt;PageDown&gt; key to move it up/down in the priority list. Only the first device in each device group will be available for selection in the Boot Device Priority option.

# 8.6 Security Setup

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Security Settings</td><td rowspan="2" colspan="2">Install or Change the password.</td></tr><tr><td rowspan="2" colspan="5">Supervisor Password :Not InstalledUser Password :Not InstalledChange Supervisor PasswordChange User PasswordClear User Password</td></tr><tr><td colspan="2">← Select Screen↑↓ Select ItemEnter ChangeF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="7">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Password Support

# Two Levels of Password Protection

Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password.

The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure.

# Remember the Password

Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM.

To access the sub menu for the following items, select the item and press &lt; Enter&gt;:

▶ Change Supervisor Password
▶ Change User Password
▶ Clear User Password

# Supervisor Password

Indicates whether a supervisor password has been set.

# User Password

Indicates whether a user password has been set.

# Change Supervisor Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the supervisor password.

# Change User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the user password.

# Clear User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to clear the user password.

# Change Supervisor Password

Select Change Supervisor Password from the Security Setup menu and press &lt; Enter &gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# Change User Password

Select Change User Password from the Security Setup menu and press &lt;Enter&gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# 8.7 Chipset Setup

Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of the items in the left frame of the screen to go to the sub menu for that item. The Chipset BIOS Setup screen is shown below.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Advanced Chipset Settings</td><td rowspan="3">Configure North Bridge features.</td></tr><tr><td colspan="5">WARNING: Setting wrong values in below sections may cause system to malfunction.</td></tr><tr><td colspan="5">▶ North Bridge Configuration▶ South Bridge ConfigurationFront LAN ROM Init [Disabled]Rear LAN ROM Init [Disabled]CPCI-R6000 SCSI ROM Init [Disabled]</td></tr><tr><td colspan="5"></td><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# North Bridge Configuration

You can use this screen to select options for the North Bridge Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td></td><td>Chipset</td></tr><tr><td>North Bridge Chipset ConfigurationBoots Graphic Adapter Priority [PEG/PCI]Internal Graphics Mode Select [Enabled, 32MB]Boot Display Device [CRT + LVDS]Flat Panel Type [1024x768 ]</td><td>Select which graphics controller to use as the primary boot device.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# Boot Graphic Adapter Priority

Select which graphics controller to use as the primary boot device.

▶ IGD: Built-in chipset graphic only
▶ PCI/IGD: Detect PCI graphics first, then built-in chipset graphics (PCI includes PCI slot and PCI Express x1/x4 slot, PCI will be first)
▶ PCI/PEG: Detect PCI graphics first, then PCI Express x16 graphics
▶ PEG/IGD: Detect PCI Express x16 graphics first, then built-in chipset graphics
▶ PEG/PCI: Detect PCI Express x16 graphics first, then PCI graphics, then built-in chipset graphics

# Internal Graphics Mode Select

Select the amount of system memory (32M/64M/128M) used by the internal graphics device.

# Boot Display Device

This item allows the user to configure the type of external display used.

▶ CRT: Only CRT display
▶ CRT+DVI: Both CRT and DVI display (default)
▶ CRT+LVDS: Both CRT and LVDS display

# Flat Panel Type

When LVDS is selected from Boot Display Device, this option allows the output resolution to be set for the LVDS device you want to use. Available resolutions: 640x480, 800x600, 1024x768, 1280x1024.

# South Bridge Configuration

You can use this screen to select options for the South Bridge Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option.

![Chipset\nHDA Controller (Enabled) Options\nEnabled\nDisabled\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.cpci-6870-50-15069-1010-201-en/6a076ec892f4539197cd4d49da690e60802ce36db601fc56a76e4f6033b915ee.jpg)

# HDA Controller

Set this value to Enable/Disable the HDA Controller.

# 8.8 Exit Menu

Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Exit BIOS Setup screen is shown below.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Exit Options</td><td>Exit system setup after saving the changes.</td></tr><tr><td rowspan="3" colspan="5">Save Changes and ExitDiscard Changes and ExitDiscard ChangesLoad Optimal DefaultsLoad Failsafe Defaults</td><td rowspan="2">F10 key can be used for this operation.</td></tr><tr></tr><tr><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Save Changes and Exit

When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect.

Save Configuration Changes and Exit Now?

[Ok] [Cancel]

appears in the window. Select Ok to save changes and exit.

# Discard Changes and Exit

Select this option to quit Setup without making any permanent changes to the system configuration.

Discard Changes and Exit Setup Now?

[Ok] [Cancel]

appears in the window. Select Ok to discard changes and exit.

# Discard Changes

Select Discard Changes from the Exit menu and press &lt; Enter &gt;.

Select Ok to discard changes.

# Load Optimal Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems.

Select Load Optimal Defaults from the Exit menu and press &lt;Enter&gt;.

Select Ok to load optimal defaults.

# Load Failsafe Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the FailSafe Setup options if your computer is experiencing system configuration problems.

Select Load Fail-Safe Defaults from the Exit menu and press &lt;Enter&gt;.

Load FailSafe Defaults?

[Ok] [Cancel]

appears in the window. Select Ok to load FailSafe defaults.

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# 9 IPMI User Guide

# 9.1 Introduction

This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 2.0. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.

# 9.2 Summary of Commands Supported by BMR-AVR-cPCI

The table below lists all the commands supported by the BMR-AVR-cPCI. For detailed information on supported commands, please refer to the Intelligent Platform Management Interface Specification downloadable from the Intel website (http://www.intel.com/design/servers/ipmi/spec.htm).

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>Description</td></tr><tr><td colspan="5">IPM Device “Global” Commands</td></tr><tr><td>Get Device ID</td><td>20.1</td><td>App</td><td>01h</td><td>This command is used to retrieve the Intelligent Device’s Hardware Revision, Firmware/Software Revision, and Sensor and Event Interface Command specification revision information.</td></tr><tr><td>Cold Reset</td><td>20.2</td><td>App</td><td>02h</td><td>This command directs the Responder to perform a ‘Cold Reset’ of itself.</td></tr><tr><td>Warm Reset</td><td>20.3</td><td>App</td><td>03h</td><td>This command directs the Responder to perform a ‘Warm Reset’ of itself.</td></tr><tr><td>Get Self Test Results</td><td>20.4</td><td>App</td><td>04h</td><td>This command directs the device to return its Self Test results, if any.</td></tr><tr><td>Get Device GUID</td><td>20.8</td><td>App</td><td>08h</td><td>This command returns a GUID (Globally Unique ID), also referred to as a UUID (Universally Unique IDentifier), for the management controller.</td></tr><tr><td>Broadcast “Get Device ID”</td><td>20.9</td><td>App</td><td>01h</td><td>This is a broadcast version of the ‘Get Device ID’ command that is provided for the ‘discovery’ of Intelligent Devices on the IPMB</td></tr><tr><td colspan="5">IPMI Messaging Support Commands</td></tr><tr><td>Send Message</td><td>22.7</td><td>App</td><td>34h</td><td>The Send Message command is used for bridging IPMI messages between channels, and between the system management software (SMS) and a given channel.</td></tr><tr><td colspan="5">BMC Watchdog Timer</td></tr><tr><td>Reset Watchdog Timer</td><td>27.5</td><td>App</td><td>22h</td><td>The Reset Watchdog Timer command is used for starting and restarting the Watchdog Timer from the initial countdown value that was specified in the Set Watchdog Timer command.</td></tr><tr><td>Set Watchdog Timer</td><td>27.6</td><td>App</td><td>24h</td><td>The Set Watchdog Timer command is used for initializing and configuring the watchdog timer. The command is also used for stopping the timer.</td></tr><tr><td>Get Watchdog Timer</td><td>27.7</td><td>App</td><td>25h</td><td>This command retrieves the current settings and present countdown of the watchdog timer.</td></tr><tr><td colspan="5">Event Commands</td></tr><tr><td>Set Event Receiver</td><td>29.1</td><td>S/E</td><td>00h</td><td>This global command tells a controller where to send Event Messages.</td></tr><tr><td>Get Event Receiver</td><td>29.2</td><td>S/E</td><td>01h</td><td>This global command is used to retrieve the present setting for the Event Receiver Slave Address and LUN. This command is only applicable to management controllers that act as IPMB Event Generators.</td></tr><tr><td>Platform Event (a.k.a. “Event Message”)</td><td>29.3</td><td>S/E</td><td>02h</td><td>This command may be thought of as a request for the BMC to process the event data that the command contains. Typically, the data will be logged to the System Event Log (SEL).</td></tr><tr><td colspan="5">Sensor Device Commands</td></tr><tr><td>Get Device SDR Info</td><td>35.2</td><td>S/E</td><td>20h</td><td>This command returns general information about the collection of sensors in a Dynamic Sensor Device.</td></tr><tr><td>Get Device SDR</td><td>35.3</td><td>S/E</td><td>21h</td><td>The ‘Get Device SDR’ command allows SDR information for sensors for a Sensor Device (typically implemented in a satellite management controller) to be returned.</td></tr><tr><td>Reserve Device SDR Repository</td><td>35.4</td><td>S/E</td><td>22h</td><td>This command is used to obtain a Reservation ID.</td></tr><tr><td>Set Sensor Hysteresis</td><td>35.6</td><td>S/E</td><td>24h</td><td>This command provides a mechanism for setting the hysteresis values associated with the thresholds of a sensor that has threshold based event generation.</td></tr><tr><td>Get Sensor Hysteresis</td><td>35.7</td><td>S/E</td><td>25h</td><td>This command retrieves the present hysteresis values for the specified sensor.</td></tr><tr><td>Set Sensor Threshold</td><td>35.8</td><td>S/E</td><td>26h</td><td>This command is used to set the specified threshold for the given sensor.</td></tr><tr><td>Get Sensor Threshold</td><td>35.9</td><td>S/E</td><td>27h</td><td>This command retrieves the threshold for the given sensor.</td></tr><tr><td>Set Sensor Event Enable</td><td>35.10</td><td>S/E</td><td>28h</td><td>This command provides the ability to disable or enable Event Message Generation for individual sensor events. The command is also used to enable or disable sensors in their entirety using the disable scanning bit.</td></tr><tr><td>Get Sensor Event Enable</td><td>35.11</td><td>S/E</td><td>29h</td><td>This command returns the enabled/ disabled state for Event Message Generation from the selected sensor. The command also returns the enabled/ disabled state for scanning on the sensor.</td></tr><tr><td>Get Sensor Event Status</td><td>35.13</td><td>S/E</td><td>2Bh</td><td>The Get Sensor Event Status command is provided to support systems where sensor polling is used in addition to, or instead of, Event Messages for event detection.</td></tr><tr><td>Get Sensor Reading</td><td>35.14</td><td>S/E</td><td>2Dh</td><td>This command returns the present reading for sensor. The sensor device may return a stored version of a periodically updated reading, or the sensor device may scan to obtain the reading after receiving the request.</td></tr><tr><td>Get Sensor Type</td><td>35.16</td><td>S/E</td><td>2Fh</td><td>This command is used to assign the Sensor Type and Event/Reading Type to a specified sensor.</td></tr><tr><td colspan="5">FRU Device Commands</td></tr><tr><td>Get FRU Inventory Area Info</td><td>34.1</td><td>Stora ge</td><td>10h</td><td>Returns overall the size of the FRU Inventory Area in this device, in bytes.</td></tr><tr><td>Read FRU Data</td><td>34.2</td><td>Stora ge</td><td>11h</td><td>The command returns the specified data from the FRU Inventory Info area.</td></tr><tr><td>Write FRU Data</td><td>34.3</td><td>Stora ge</td><td>12h</td><td>The command writes the specified byte or word to the FRU Inventory Info area.</td></tr></table>

# 9.3 OEM Commands Summary Table

<table><tr><td>Command</td><td>NetFn Code</td><td>Cmd Code</td></tr><tr><td>OemShowRevision</td><td>OEM (C0h)</td><td>12h</td></tr><tr><td>OemRescanGaInput</td><td>OEM (C0h)</td><td>22h</td></tr><tr><td>OemTestFunction</td><td>OEM (C0h)</td><td>30h</td></tr><tr><td>OemSetBlueLEDLongBlinking</td><td>OEM (C0h)</td><td>31h</td></tr><tr><td>OemReportGeoAddress</td><td>OEM (C0h)</td><td>F0h</td></tr><tr><td>OemEnableSmbus</td><td>OEM (C0h)</td><td>F2h</td></tr><tr><td>OemDisableSmbus</td><td>OEM (C0h)</td><td>F3h</td></tr><tr><td>OemDispDebugVariable</td><td>OEM (C0h)</td><td>F4h</td></tr><tr><td>OemResetHost</td><td>OEM (C0h)</td><td>F5h</td></tr><tr><td>OemPowerOff</td><td>OEM (C0h)</td><td>F6h</td></tr><tr><td>OemPowerOn</td><td>OEM (C0h)</td><td>F7h</td></tr></table>

# OemShowRevision

This command is used to show the current information of the firmware including the firmware revision, the product ID, and additional features.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>12h</td><td>OEM defined command</td></tr><tr><td rowspan="11">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>A5h</td><td>Internal check byte. Always A5h</td></tr><tr><td>2</td><td>*Firmware Rev</td><td>‘V’ in ASCII code for verification</td></tr><tr><td>3</td><td>*Firmware Rev</td><td>Revision info high byte</td></tr><tr><td>4</td><td>*Firmware Rev</td><td>Revision info low byte</td></tr><tr><td>5</td><td>*Product ID</td><td>‘P’ in ASCII code for verification</td></tr><tr><td>6</td><td>*Product ID</td><td>Product info high byte</td></tr><tr><td>7</td><td>*Product ID</td><td>Product info low byte</td></tr><tr><td>8</td><td>*Special info</td><td>‘S’ in ASCII code for verification</td></tr><tr><td>9</td><td>*Special info</td><td>Addition info byte</td></tr><tr><td>10</td><td>5Ah</td><td>Internal check byte. Always 5Ah</td></tr></table>

# OemRescanGaInput

This command is used to rescan the geo-address input pins and reset the IPMB address according to the input value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>22h</td><td>OEM defined command</td></tr><tr><td rowspan="2">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>New IPMB address</td><td>New IPMB address value</td></tr></table>

# OemTestFunction

Internal test purposes only.

# OemSetBlueLEDLongBlinking

This command is used to enable or disable the slow blink of the blue HotSwap LED when a voltage is detected to be over $\pm5\%$ out of range for five seconds (see Table 4-1 on page 22). This function is set to enabled by default.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="3">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>31h</td><td>OEM defined command</td></tr><tr><td>2</td><td>00h or 01h</td><td>00h: disable slow blink capability01h: enable slow blink capability</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemReportGeoAddress

This command can report the IPMB address, the GA pin input status, and the event forwarding control value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F0h</td><td>OEM defined command</td></tr><tr><td rowspan="4">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>IPMB address</td><td>IPMB address value</td></tr><tr><td>2</td><td>GA value</td><td>GA pin input status</td></tr><tr><td>3</td><td>Control value</td><td>Current control value of event forwarding</td></tr></table>

# OemEnableSmbus

This command is used to turn on the I2C bus when it is off during boot up process. Usually BIOS will perform this command after booting in boards with ServerWorks chipset.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F2h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDisableSmbus

This command is used to shut down I2C bus access.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F3h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDispDebugVariable

This command can report up to 5 interval values for debug purposes. For developers only.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F4h</td><td>OEM defined command</td></tr><tr><td rowspan="6">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>*Debug variable 1</td><td></td></tr><tr><td>2</td><td>*Debug variable 2</td><td></td></tr><tr><td>3</td><td>*Debug variable 3</td><td></td></tr><tr><td>4</td><td>*Debug variable 4</td><td></td></tr><tr><td>5</td><td>*Debug variable 5</td><td></td></tr></table>

# OemResetHost

This command is implemented to control the system's status if rebooting is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F5h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOff

This command is implemented to control the system's status if power-off is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F6h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOn

This command is implemented to control the system's status if power-on is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F7h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# 9.4 CompactPCI Address Map

Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.

<table><tr><td colspan="4">CompactPCI Peripheral Address Mapping</td></tr><tr><td>Geo. Addr.</td><td>IPMB Addr.</td><td>Geo. Addr.</td><td>IPMB Addr.</td></tr><tr><td>0</td><td>Disabled</td><td>16</td><td>D0h</td></tr><tr><td>1</td><td>B0h</td><td>17</td><td>D2h</td></tr><tr><td>2</td><td>B2h</td><td>18</td><td>D4h</td></tr><tr><td>3</td><td>B4h</td><td>19</td><td>D6h</td></tr><tr><td>4</td><td>B6h</td><td>20</td><td>D8h</td></tr><tr><td>5</td><td>B8h</td><td>21</td><td>DAh</td></tr><tr><td>6</td><td>Bah</td><td>22</td><td>DCh</td></tr><tr><td>7</td><td>BCh</td><td>23</td><td>DEh</td></tr><tr><td>8</td><td>BEh</td><td>24</td><td>E0h</td></tr><tr><td>9</td><td>Coh</td><td>25</td><td>E2h</td></tr><tr><td>10</td><td>C4h</td><td>26</td><td>E4h</td></tr><tr><td>11</td><td>C6h</td><td>27</td><td>E6h</td></tr><tr><td>12</td><td>C8h</td><td>28</td><td>E8h</td></tr><tr><td>13</td><td>CAh</td><td>29</td><td>EAh</td></tr><tr><td>14</td><td>CCh</td><td>30</td><td>ECh</td></tr><tr><td>15</td><td>CEh</td><td>31</td><td>Disabled</td></tr></table>

# 9.5 Communications with IPMC

Operating systems need to use a serial port to communicate with the IPMC. The resource setting of the serial port must be IO: 0x3E8 and IRQ: 3. The communication setting of the serial port must be BaudRate: 9600, DataBit: 8, ParityCheck: None, StopBit: 1, and FlowControl: None. In Windows XP, use "COM3" to communicate with the IPMC.

# 9.6 IPMI Sensors List

<table><tr><td>Sensor Number</td><td>Sensor name</td><td>Normal Reading</td><td>Remark</td></tr><tr><td>00h</td><td>BMC Watchdog</td><td></td><td></td></tr><tr><td>01h</td><td>3.3V</td><td>3.3 V</td><td></td></tr><tr><td>02h</td><td>5V</td><td>5 V</td><td></td></tr><tr><td>03h</td><td>12V</td><td>12 V</td><td></td></tr><tr><td>04h</td><td>SYSTEM Temp</td><td>25°C</td><td></td></tr><tr><td>05h</td><td>CPU Temp</td><td>40°C</td><td></td></tr><tr><td>06h</td><td>BIOS CHANGE</td><td></td><td></td></tr><tr><td>07h</td><td>BIOS POST ERROR</td><td></td><td></td></tr></table>

# 9.7 Relevant Documents

<table><tr><td>Document Title</td><td>Revision</td><td>Source</td></tr><tr><td>Intelligent Platform Management Interface Specification v2.0</td><td>Document Revision 1.1 February 20, 2002</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/spec.htm</td></tr><tr><td>PICMG 2.9 D1.0 CompactPCI System Management Specification</td><td>January 21, 2000</td><td></td></tr><tr><td>Intelligent Platform Management Bus Communications Protocol Specification v0.9</td><td>Document Revision 0.15 June 24, 1997</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr></table>

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:
▷ Turn off power and unplug any power cords/cables.
▶ To avoid electrical shock and/or damage to equipment:
▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);
▶ Make sure to use recommended voltage and power source settings;
▶ Always install and operate equipment near an easily accessible electrical socket-outlet;
▷ Secure the power cord (do not place any object on/over the power cord);
▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard warning sign featuring a dark red triangle with a white exclamation point in the center. Below the triangle, the text 'WARNING:' is printed in black capital letters.](.cpci-6870-50-15069-1010-201-en/5e67b6f242871df3617dd8d34b8410290e2cbff12bfa59c50176dbf06f24fe80.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
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新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

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Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

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Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
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Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

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Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
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Tel: +86-10-5885-8666

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Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园
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2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,
High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

Tel: +49-211-495-5552

Fax: +49-211-495-5557

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

神田 374 ビル 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address:서울시 서초구 서초동 1675-12 모인터빌딩 8 층

8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu,

Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross,

JP Nagar Phase I, Bangalore - 560078, India

Tel: +91-80-65605817

Fax: +91-80-22443548

Email: india@adlinktech.com
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