# cPCI-6880 Series

Low Power 6U CompactPCI Processor Blade with 45nm Intel® Core™2 Duo Processor

# User's Manual

![Back view of a computer motherboard with visible CPU socket, RAM slots, and connectors (no text or symbols)](.cpci-6880-50-15066-1020-202-en/0c7c47de3112eea119c0d1389d612fd0aec1c836e39394282507cd9cd4ef1e23.jpg)

Manual Rev. 2.02

Revision Date: April 26, 2009

Part No: 50-15066-1020

![Circular black-and-white recycling symbol with three white arrows forming a triangle (no text or symbols)](.cpci-6880-50-15066-1020-202-en/70d17ef004fef4f8b64a74dc9ec180352f18ccfe098adb29d943f5e5ec5cc0dc.jpg)

Recycled Paper

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2009/07/29</td><td>Initial Release</td></tr><tr><td>2.01</td><td>2010/03/17</td><td>Correct block diagram, serial port specification, GbE pin definition, cPCI-R6000P RTM board layout, assembly and front panel drawings, J1 pin definition, Mode Switch settings, Status LED label; add PMC connector pin definitions</td></tr><tr><td>2.02</td><td>2011/04/26</td><td>Remove TMDS signals from J5 pinout; correct Hot Swap LED default status; update addresses</td></tr></table>

# Preface

# Copyright 2009-2011 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Using this Manual

# Audience and Scope

The cPCI-6880 User's Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating CompactPCI systems.

# Manual Organization

This manual is organized as follows:

Chapter 1, Overview: Introduces the cPCI-6880, its features, block diagrams, and package contents.

Chapter 2, Specifications: Presents detailed specification information, and power consumption.

Chapter 3, Functional Description: Describes the cPCI-6880's main functions.

Chapter 4, Board Interfaces: Describes the cPCI-6880 board interfaces, pin definitions, and jumper settings.

Chapter 5, Getting Started: Describes the installation instructions of the cPCI-6880.

Chapter 6, Driver Installation: Describes the driver installation procedures.

Chapter 7, Utilities: Describes the Watchdog Timer and Preboot Execution Environment functions.

Chapter 8, BIOS Setup Utility: Describes the AMIBIOS®8 BIOS setup utility.

Chapter 9, IPMI User Guide: Provides relevant information for the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI).

Important Safety Instructions: Presents safety instructions all users must follow for the proper setup, installation and usage of equipment and/or software.

Getting Service: Contact information for ADLINK's worldwide offices.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon featuring a folded top-right corner and faint horizontal gray lines. A large red checkmark is overlaid diagonally across the center of the document.](.cpci-6880-50-15066-1020-202-en/80076b2927f292af44f30d91c7a42887f00610a657d6a6c22e7f32e948a72acc.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign featuring a black exclamation point in the center.](.cpci-6880-50-15066-1020-202-en/d616afbf42e8669b796a7add0ae9c6ca9531893b5acdea419ba084fd7bf08ecb.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning sign. It features a red equilateral triangle with a thick white border. In the center of the triangle is a large white exclamation point.](.cpci-6880-50-15066-1020-202-en/0ab1b92eb65cd133260848d8f1a6f11ac71c4d1687868193fe550b06175d1d1f.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

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# Table of Contents

# Revision History...... ii

# Preface...... iii

# List of Tables.... xi

# List of Figures ...... xiii

# 1 Overview .... 1

1.1 Introduction.... 1
1.2 Features.... 2
1.3 Block Diagram 3
1.4 Product List.... 4
1.5 Package Contents 5

# 2 Specifications.... 7

2.1 cPCI-6880 SBC Specifications 7
2.2 cPCI-R6000 RTM Specifications 10
2.3 I/O Connectivity Table 12
2.4 Power Requirements 14

# 3 Functional Description 17

3.1 CPU 17
3.2 Chipset.... 20
3.3 DVI 22
3.4 Super I/O 22
3.5 Battery 23
3.6 PMC Site 23
3.7 Onboard USB Flash.... 23
3.8 FWH Flash Memory & Failover 24

# 4 Board Interfaces.... 25

4.1 cPCI-6880 SBC Board Layout 25
4.2 cPCI-6880 SBC Front Panel 26
4.3 cPCI-6880 SBC Assembly Layout 27
4.4 cPCI-R6000 RTM Board Layout 28
4.5 cPCI-R6000 RTM Front Panel 29
4.6 cPCI-R6000D RTM Board Layout.... 30
4.7 cPCI-R6000D RTM Front Panel 31
4.8 cPCI-R6000D RTM Assembly Layout.... 32
4.9 cPCI-R6000P RTM Board Layout.... 33
4.10 cPCI-R6000P RTM Front Panel.... 34
4.11 Connector Pin Assignments.... 35
4.12 Switch and Jumper Settings 55

# 5 Getting Started.... 59

5.1 CPU and Heatsink 59
5.2 Memory Module Installation.... 60
5.3 Hard Drive Installation.... 61
5.4 CompactFlash Card Installation.... 66
5.5 Installing the cPCI-6880 SBC to the Chassis.... 69
5.6 Installing the cPCI-R6000 RTM to the Chassis.... 70

# 6 Driver Installation.... 71

6.1 Driver Installation Procedure.... 71
6.2 SCSI Driver 72

# 7 Utilities.... 73

7.1 Watchdog Timer.... 73
7.2 Preboot Execution Environment (PXE).... 78

# 8 BIOS Setup Utility 79

8.1 Starting the BIOS.... 79
8.2 Main Setup.... 83
8.3 Advanced BIOS Setup 84

8.4 Advanced PCI/PnP Settings 93
8.5 Boot Settings 94
8.6 Security Setup 97
8.7 Chipset Setup 100
8.8 Exit Menu.... 104

# 9 IPMI User Guide.... 107

9.1 Introduction.... 107
9.2 Summary of Commands Supported by BMR-AVR-cPCI. 107
9.3 OEM Commands Summary Table.... 109
9.4 CompactPCI Address Map 113
9.5 Communications with IPMC 114
9.6 IPMI Sensors List.... 114
9.7 Relevant Documents 115

# Important Safety Instructions.... 117

# Getting Service.... 119

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# List of Tables

Table 2-1: SBC I/O Connectivity ...... 12

Table 2-2: RTM I/O Connectivity 13

Table 2-3: CompactPCI Input Voltage Characteristics ..... 14

Table 2-4: Idle Mode Power Consumption 15

Table 2-5: 100% CPU Usage Power Consumption 15

Table 4-1: cPCI-6880 Front Panel Status LED Descriptions ... 26

Table 4-2: USB Connector Pin Definition 35

Table 4-3: RJ-45 Serial Port Pin Definition 35

Table 4-4: PS/2 Keyboard/Mouse Connector Pin Definition .... 35

Table 4-5: GbE Connector Pin Definitions 36

Table 4-6: GbE LED CN4, CN5 Status Definitions .... 36

Table 4-7: GbE LED CN20-R, CN21-R Status Definitions ..... 36

Table 4-8: COM1-2 Serial Port Connector Pin Definition ..... 37

Table 4-9: Onboard Serial Port Connector Pin Definition ..... 37

Table 4-10: DVI-I Connector Pin Definition (J6) 38

Table 4-11: DVI-I (Analog only) Connector Pin Def'n (CNY1) ... 39

Table 4-12: SATA Connector Pin Definition 39

Table 4-13: DB-6910SAT SATA Connector Pin Definition ..... 40

Table 4-14: PMC Connector Pin Definitions 42

Table 4-15: 68-pin SCSI Pin Definition 43

Table 4-16: Floppy Connector Pin Definition 44

Table 4-17: PIM Connector (JN1-R) Pin Definition 45

Table 4-18: PIM Connector (JN2-R) Pin Definition 46

Table 4-19: CompactFlash Connector Pin Definition 47

Table 4-20: DB-6880CF, DB-6920CF/SAT Connector Pin Def'n 48

Table 4-21: DB-R6000L2 Connector Pin Definition 49

Table 4-22: CompactPCI J1 Connector Pin Definition .... 50

Table 4-23: CompactPCI J2 Connector Pin Definition .... 51

Table 4-24: CompactPCI J3 Connector Pin Definition .... 52

Table 4-25: CompactPCI J4 Connector Pin Definition .... 53

Table 4-26: CompactPCI J5 Connector Pin Definition .... 54

Table 4-27: Mode Switch Settings 55

Table 4-28: COM1/Debug Switch Settings 56

Table 4-29: USB Flash Data Protection Switch Settings ..... 56

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# List of Figures

Figure 1-1: cPCI-6880 Series Block Diagram.... 3
Figure 4-1: cPCI-6880 SBC Board Layout.... 25
Figure 4-2: cPCI-6880 Series Front Panel Layout.... 26
Figure 4-3: cPCI-6880 SBC Assembly Layout.... 27
Figure 4-4: cPCI-R6000 RTM Board Layout.... 28
Figure 4-5: cPCI-R6000 RTM Front Panel.... 29
Figure 4-6: cPCI-R6000D RTM Board Layout 30
Figure 4-7: cPCI-R6000D RTM Front Panel 31
Figure 4-8: cPCI-R6000D RTM Assembly Layout 32
Figure 4-9: cPCI-R6000P RTM Board Layout 33
Figure 4-10: cPCI-R6000P RTM Front Panel 34

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# 1 Overview

# 1.1 Introduction

The cPCI-6880 Series is a 6U CompactPCI single board computer in single slot (4HP) width form factor featuring a low power Intel® mobile chipset and 45nm Core™2 Duo processor with high performance 1066MHz front-side bus (FSB). The cPCI-6880 provides up to 8GB dual channel DDR2-667/800 memory capacity, one channel of soldered onboard memory up to 4GB, and the other channel via SODIMM socket. The cPCI-6880 Series implements the Mobile Intel® GM45 Memory Controller Hub and ICH9M I/O Hub for optimal performance.

The cPCI-6880 Series supports a 64bit/66MHz CompactPCI bus, one PMC site with 64-bit/66MHz PCI bus, four PCI-Express gigabit Ethernet ports (two on front panel, two for PICMG 2.16), a SATA connector for an onboard 2.5" SATA HDD (or CompactFlash socket via adapter), onboard 4GB USB NAND flash for solid-state storage, and SCSI RAID 1 support via the Rear Transition Module (RTM). For flexibility of use, the cPCI-6880 Series can be installed in a standard CompactPCI system slot as system master, or peripheral slot as PCI device. The cPCI-6880 Series is ideally suited for factory automation, transportation and military applications.

# 1.2 Features

▶ 6U CompactPCI SBC in 4HP width form factor
Intel® Core™2 Duo or Celeron® processor, up to 2.53GHz in μFC-PGA package (Socket P)
▶ Front Side Bus 1066/800/667 MHz depending on processor
▶ Mobile Intel® GM45 Graphics Memory Controller Hub and ICH9M I/O Controller Hub
▶ Dual Channel DDR2 non-ECC SDRAM at 667 or 800MHz
▶ One channel for soldered memory up to 4GB; one channel for SO-DIMM socket up to 4GB memory (max. 8GB total)
▶ 64-bit/66MHz CompactPCI Interface based on PCI specifications, 3.3V and 5V signaling
▶ Supports operation in system slot as system master or in peripheral slot with connectivity to CompactPCI bus
▶ One PMC site with 64-bit/66MHz PCI bus, 3.3V VIO only
▶ DVI-I port on front panel to support digital or analog graphics output
▶ Single channel LVDS interface support: 1x18 bpp (LVDS signals are routed to J5 connector)
▶ Four PCI-Express® Gigabit Ethernet ports, two at front, two for PICMG 2.16
▶ One SATA connector for onboard 2.5" SATA HDD and onboard 4GB USB NAND flash for storage options
▶ Optional CompactFlash socket by DB-CF-SB adapter
▶ Optional -20\~70°C extended temperature support
▶ SCSI RAID 1 support on RTM
▶ High definition audio ports on RTM
▶ Up to three SATA ports on RTM

# 1.3 Block Diagram

![**Labeled Blocks:**\n*   Intel® CPU\n*   Intel® GM45\n*   Soldered\n*   SO-DIMM\n*   TXR\n*   FRONT PANEL\n*   Super I/O\n*   BMC\n*   Intel® ICH9M\n*   NAND Flash 4GB\n*   BIOS\n*   2.5' HDD/CF\n*   PCIe to PCI bridge\n*   PMC\n*   PCI universal bridge\n*   Intel® 82573L (four instances)\n*   J1, J2, J3, J4, J5\n\n**Connections:**\n*   **Intel® CPU** connects to **Intel® GM45** (FSB 667/800/1067MHz)\n*   **Intel® CPU** connects to **J5** (PCIe x1)\n*   **Soldered** connects to **SO-DIMM**\n*   **SO-DIMM** connects to **Intel® GM45** (Dual Channel DDR2-667/800)\n*   **Intel® GM45** connects to **TXR** (SDVO)\n*   **TXR** connects to **FRONT PANEL** (DVI-I)\n*   **Intel® GM45** connects to **J5** (LVDS)\n*   **Intel® GM45** connects to **J5** (SATA2)\n*   **Intel® GM45** connects to **J5** (Floppy)\n*   **Intel® GM45** connects to **J4** (RGB)\n*   **Intel® GM45** connects to **Super I/O** (RGB)\n*   **Intel® GM45** connects to **Intel® ICH9M** (DMI)\n*   **Super I/O** connects to **FRONT PANEL** (COM1)\n*   **Super I/O** connects to **FRONT PANEL** (USB 1/2/3)\n*   **Super I/O** connects to **Intel® ICH9M** (LPC)\n*   **Super I/O** connects to **J3** (KB/MS)\n*   **Super I/O** connects to **J3** (SATA 1/4)\n*   **Super I/O** connects to **J3** (USB 5/6/7/8/9/10)\n*   **Super I/O** connects to **J3** (COM 3/4)\n*   **BMC** connects to **J4** (PIM)\n*   **BMC** connects to **J3** (RGB)\n*   **Intel® ICH9M** connects to **NAND Flash 4GB** (USB 4)\n*   **Intel® ICH9M** connects to **BIOS** (SPI)\n*   **Intel® ICH9M** connects to **2.5' HDD/CF** (SATA 0)\n*   **Intel® ICH9M** connects to **PCIe to PCI bridge** (PCIe x2)\n*   **Intel® ICH9M** connects to **Intel® 82573L** (PCIe x1) which connects to **FRONT PANEL** (GbE1)\n*   **Intel® ICH9M** connects to **Intel® 82573L** (PCIe x1) which connects to **FRONT PANEL** (GbE2)\n*   **Intel® ICH9M** connects to **Intel® 82573L** (PCIe x1) which connects to **J3** (GbE3 (2.16))\n*   **Intel® ICH9M** connects to **Intel® 82573L** (PCIe x1) which connects to **J3** (GbE4 (2.16))\n*   **Intel® ICH9M** connects to **J3** (HD Audio)\n*   **PCIe to PCI bridge** connects to **PCI universal bridge**\n*   **PCI universal bridge** connects to **J1** (PCI 64b/66M)\n*   **PMC** connects to **PCI universal bridge** (PCI 64b/66M)\n*   **PMC** connects to **J2** (IPMB)](.cpci-6880-50-15066-1020-202-en/5cbfd9eab7d011a0e493c6793ccf55432e1527828adfb88c99c62a7a4c5372ca.jpg)

Figure 1-1: cPCI-6880 Series Block Diagram

# 1.4 Product List

Products included in the cPCI-6880 Series include:

# Processor Blade

▶ cPCI-6880: 4HP (single-slot) width 6U CompactPCI featuring single Intel® Core™2 Duo or Celeron processor; 1GB, 2GB or 4GB soldered onboard memory and additional 1GB, 2GB or 4GB by SO-DIMM socket; embedded 4GB USB NAND flash onboard; removable SATA connector adapter (DB-6920SAT); one PMC site and I/O: 3x USB, 2x GbE, RJ-45 COM, DVI-I; equipped with J1, J2, J3, J5 connectors without PIM support.
▶ cPCI-6880P: 4HP (single-slot) width 6U CompactPCI featuring single Intel® Core™2 Duo or Celeron processor; 1GB, 2GB or 4GB soldered onboard memory and additional 1GB, 2GB or 4GB by SO-DIMM socket; embedded 4GB USB NAND flash onboard; removable SATA connector adapter (DB-6920SAT); one PMC site and I/O: 3x USB, 2x GbE, RJ-45 COM, DVI-I; equipped with J1, J2, J3, J4, J5 connectors with PIM support.

# Rear Transition Modules

▶ cPCI-R6000: 4HP width Rear Transition Module for CPCI-6880 SBCs with VGA, 2x COM, 3x USB, 2x GbE, SCSI, 2x SATA, and Floppy
▶ cPCI-R6000P: 4HP width Rear Transition Module for CPCI-6880 SBCs with VGA, 2x COM, 3x USB, 2x GbE, PIM, 2x SATA, and Floppy (supports cPCI-6880P only)
▶ cPCI-R6000D: 8HP width Rear Transition Module for CPCI-6880 SBCs with VGA, 2x COM, 3x USB, 2x GbE, SCSI, 2x SATA, and Floppy. The DB-R6000L2 riser card provides 2x USB, KB/MS, Mic-in, Line-out and removable SATA direct connector (DB-6920SAT) for 2.5" SATA HDD direct connection.

# Adapter Kits

▶ DB-CF-SA: CompactFlash socket kit for RTM cPCI-R6000D, including DB-6920CF adapter board, card guide and screws to replace SATA adapter with Compact-Flash socket
▶ DB-CF-SB: CompactFlash socket kit for SBC cPCI-6880, including DB-6880CF adapter board, card guide and screws to replace SATA adapter with CompactFlash socket

# 1.5 Package Contents

The cPCI-6880 is packaged with the components listed below (RTMs and adapter kits are optional). If any of the items in the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of non-standard configurations may vary depending on customer requests.

# Processor Blade

▶ The cPCI-6880 Series Processor Blade
▷ CPU, RAM will differ depending on options selected
▶ Thermal module is assembled on the board
▶ RJ-45 to DB-9 cable
▶ DVI to D-sub VGA adapter
▶ DB-6920SAT SATA adapter card
▶ 2.5" SATA HDD mounting kit, including HDD bracket and screws for HDD and adapter card
▶ ADLINK All-in-One CD
▶ User's manual

# Rear Transition Module

The cPCI-R6000, cPCI-R6000P or cPCI-R6000D RTM
▶ The DB-SATA kit (cPCI-R6000D only)
▶ 2.5" HDD bracket (cPCI-R6000D only)
▶ Y-cable for PS/2 combo port (8HP version only)
▶ DVI to VGA (DB-15) adapter
▶ Ultra-320 SCSI cable (cPCI-R6000, cPCI-R6000D only)

# Adapter Kits

▶ The DB-CF-SA kit (for cPCI-R6000D RTM)
▷ DB-6920CF adapter board
▷ Screw pack
▷ CF card guide
▶ The DB-CF-SB kit (for SBC cPCI-6880)
▷ DB-6880CF adapter board
▷ Screw pack
▷ CF card guide

![The image displays a white document icon with a folded top-left corner. Horizontal gray lines are visible on the page, representing text. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6880-50-15066-1020-202-en/ed49700bd5454ef8567be3f760ff54095d0bd7148797f769dbbd9a3b6dea4936.jpg)
NOTE:

The contents of non-standard cPCI-6880 configurations may vary depending on customer requests.

![The image shows a yellow triangular warning sign with a black border. Inside the triangle is a large, black exclamation point centered vertically. The sign is set against a white background.](.cpci-6880-50-15066-1020-202-en/23b71fb59311f7ca909650bdd1077ca91bf3c7f716ac8d4901797bce43de9135.jpg)
CAUTION:

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

2.1 cPCI-6880 SBC Specifications

<table><tr><td>CompactPCI Standard</td><td>PICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev.2.0PICMG® 2.9 System Management Bus Rev. 1.0PICMG® 2.16 Packet Switching Backplane Rev.1.0</td></tr><tr><td rowspan="4">Mechanical</td><td>Standard 6U CompactPCI®</td></tr><tr><td>Board size: 233.23 mm x 160mm</td></tr><tr><td>Single slot (4HP, 20.32mm) width</td></tr><tr><td>CompactPCI® connectors J1, J2, J3 and J5 for cPCI-6880;CompactPCI® connectors J1, J2, J3, J4 and J5 for cPCI-6880P</td></tr><tr><td rowspan="6">Processor</td><td>Intel® 45nm CoreTM2 Duo processor T9400, 6MB L2 cache, 2.53GHz, 1066MHz FSB in μFC-PGA package (Socket P)</td></tr><tr><td>Intel® 45nm CoreTM2 Duo processor P8400, 3MB L2 cache, 2.26GHz, 1066MHz FSB in μFC-PGA package (Socket P)</td></tr><tr><td>Intel® 65nm CoreTM2 Duo processor T7500, 4MB L2 cache, 2.2GHz, 800MHz FSB in μFC-PGA package (Socket P)</td></tr><tr><td>Intel® Celeron® Processor T3100, 45nm dual-core, 1MB L2 cache, 1.93GHz, 800MHz FSB in μFC-PGA package (Socket P)</td></tr><tr><td>Intel® 65nm Celeron Processor 575, single-core, 1MB L2 cache, 2.0GHz, 667MHz FSB in μFC-PGA package (Socket P)</td></tr><tr><td>Passive heatsink with forced air cooling</td></tr><tr><td>Chipset</td><td>Mobile Intel® GM45 Express Chipset with 82GM45 Graphics and Memory Controller Hub and 82801IBM I/O Controller Hub (ICH9M)</td></tr><tr><td>Memory</td><td>Dual channel DDR2-667/800 non-ECC memoryOne channel for soldered onboard memory, up to 4GBOne channel for single SO-DIMM socket, up to 4GBMaximum 8GB capacity</td></tr><tr><td>CompactPCI Bus</td><td>PCI 64-bit/ 66MHz; V(I/O) 3.3V and 5V signalingSupports operation in system slot or in peripheral slot with connectivity to CompactPCI bus (Universal Mode)</td></tr><tr><td>PMC</td><td>One PCI 64-bit/ 66MHz PMC site, V(I/O) 3.3V only</td></tr><tr><td>Ethernet</td><td>Four PCI-Express® x1 Intel® 82573L GbE controllersTwo 10/100/1000BASE-T egress portsTwo 10/100/1000BASE-T PICMG 2.16 ports</td></tr><tr><td>Graphics</td><td>Integrated in Intel® GM45 Express Chipset (GMCH)Intel® Gen 5.0 integrated graphics engineIntel® Dynamic Video Memory Technology (Intel® DVMT 5.0)Microsoft® Direct X 10 supportDVI-I port on front panel, supporting digital and CRT outputAnalog RGB up to QXGA</td></tr><tr><td>Serial Ports</td><td>One 16C550 compatible RJ-45 RS-232 port on front panelTwo serial ports routed to rear I/O</td></tr><tr><td rowspan="3">Storage Interfaces</td><td>USB NAND Flash 4GB onboard(supports standard operating temperature range only)</td></tr><tr><td>2.5” SATA HDD direct connector onboard</td></tr><tr><td>Optional CompactFlash Type II socket onboard $^{1}$ </td></tr><tr><td>BIOS</td><td>AMIBIOS®8, dual 16Mbit SPI flash memory</td></tr><tr><td>IPMI Interface</td><td>Supports PICMG® 2.9 secondary system management busIPMI functions implemented as defined by IPMI Spec. v1.5;ATmega128L-8AU Baseboard Management Controller (BMC)with 128KB programmable in-system flash, 4KB EEPROM, and4KB internal SDRAM</td></tr><tr><td>Faceplate I/O</td><td>3x USB 2.0 ports2x 10/100/1000BASE-T Ethernet portsDVI-I port (supports VGA port via DVI-to-VGA adapter)RJ-45 serial portPMC slot</td></tr><tr><td>Onboard Peripherals</td><td>Serial ATA connector (optional CompactFlash socket) $^{1}$ USB NAND Flash 4GB</td></tr><tr><td>Supported OS</td><td>Windows XP ProfessionalWindows XP x64 EditionWindows Vista x64 EditionRed Hat Enterprise 5.1Other OS support upon request</td></tr><tr><td>Operating Temperature $^{2}$ </td><td>0°C to 60°C standard-20°C to 70°C extended temperature (optional)</td></tr><tr><td>Storage temperature</td><td>-40°C to 85°C</td></tr><tr><td>Humidity</td><td>20% to 95% non-condensing</td></tr><tr><td>Shock</td><td>15G peak-to-peak, 11ms duration, non-operating</td></tr><tr><td>Vibration $^{3}$ </td><td>Operating: 1.88Grms. 5 to 500Hz, each axis (without HDD)</td></tr><tr><td>Compliance</td><td>CE EN55022, FCC Class A</td></tr></table>

# Notes:

1. The SATA HDD connector comes in a removable adapter design (DB-6920SAT) and can be replaced with a Compact-Flash socket adapter (DB-6880CF) to accommodate a CF card. The 2.5" hard drive space is reserved. A CompactFlash card and SATA HDD cannot be used/connected simultaneously.
2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Forced airflow with 16 CFM is required. Temperature limit of optional mass storage devices may affect the thermal specification.
3. The hard drive limits the operational vibration tolerance. When application requires higher specification for anti-vibration, it is recommended to use a solid state drive (SSD), CompactFlash card, or onboard USB NAND flash.

![An icon depicting a white document with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.cpci-6880-50-15066-1020-202-en/d917839c612176ce6285d6939a676469c73552036de4d1389c0041fca91ca498.jpg)
NOTE:

Specifications are subject to change without prior notice.

# 2.2 cPCI-R6000 RTM Specifications

<table><tr><td rowspan="4">Mechanical</td><td>Standard 6U CompactPCI® rear I/O</td></tr><tr><td>Board size: 233.23 mm x 80mm</td></tr><tr><td>Single-slot (4HP, 20.32mm) or dual-slot (8HP, 40.64mm) width</td></tr><tr><td>CompactPCI® connectors rJ3 and rJ5 on cPCI-R6000(D)CompactPCI® connectors rJ3, rJ4 and rJ5 on cPCI-R6000P</td></tr><tr><td rowspan="6">Rear Panel I/O</td><td>cPCI-R6000 (4HP)</td></tr><tr><td>2x USB2.0 ports2x 10/100/1000BASE-T Ethernet portsDVI-I port (analog signal only)DB-15 serial portExternal 68-pin SCSI socket</td></tr><tr><td>cPCI-R6000P (4HP)</td></tr><tr><td>2x USB 2.0 ports2x 10/100/1000BASE-T Ethernet portsDVI-I port (analog signal only)DB-15 serial portPIM (rear PMC) slot</td></tr><tr><td>cPCI-R6000D (8HP)</td></tr><tr><td>4x USB 2.0 ports2x 10/100/1000BASE-T Ethernet portsDVI-I port (analog signal only)DB-15 serial portPS/2 Keyboard Mouse portMic-in, Line-out ports</td></tr><tr><td rowspan="6">Onboard Peripherals</td><td>cPCI-R6000 (4HP)</td></tr><tr><td>USB 2.0 5-pin headerRS-232 10-pin header (Tx, Rx signals only)Internal 68-pin SCSI socket2x 7-pin Serial ATA connectorsFloppy connector</td></tr><tr><td>cPCI-R6000P (4HP)</td></tr><tr><td>USB 2.0 5-pin headerRS-232 10-pin header (Tx, Rx signals only)Floppy connector2x 7-pin Serial ATA connectorsRear PMC connectors (PIM)</td></tr><tr><td>cPCI-R6000D (8HP)</td></tr><tr><td>USB 2.0 5-pin headerRS-232 10-pin header (Tx, Rx signal only)Internal 68-pin SCSI socket2x 7-pin Serial ATA connectorsFloppy connectorSerial ATA direct connector (optional CF socket) $^1$ </td></tr><tr><td rowspan="4">SCSI</td><td>cPCI-R6000-965, cPCI-R6000-965D</td></tr><tr><td>LSI® Logic LSI53C1020 PCI-X Ultra320 SCSI ControllerIntegrated RAID on PCI-X 64-bit/133MHz bus</td></tr><tr><td>320MB per second data transfer rate</td></tr><tr><td>Supports RAID 1 (mirroring)</td></tr></table>

# Notes:

1. The Serial ATA connector comes in a removable adapter design (DB-6920SAT) and can be replaced by a CompactFlash socket adapter (DB-6920CF). The CompactFlash and SATA HDD share the same space and cannot be installed simultaneously.

# 2.3 I/O Connectivity Table

SBC

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-6880(P)</td></tr><tr><td>Faceplate</td><td>Board</td></tr><tr><td>Gigabit Ethernet</td><td>Y x2</td><td></td></tr><tr><td>COM 1</td><td>Y(RJ-45)</td><td></td></tr><tr><td>USB 2.0</td><td>Y x2</td><td></td></tr><tr><td>PMC</td><td></td><td>Y</td></tr><tr><td>DVI-I</td><td>Y</td><td></td></tr><tr><td>Serial ATA</td><td></td><td>Y</td></tr><tr><td>Compact Flash</td><td></td><td> $Optional^{(1)}$ </td></tr><tr><td>USB Flash</td><td></td><td>Y</td></tr><tr><td>GP LED</td><td>Y x4</td><td></td></tr><tr><td>Reset Button</td><td>Y</td><td></td></tr></table>

Table 2-1: SBC I/O Connectivity

RTM

<table><tr><td rowspan="2">Function</td><td colspan="2">cPCI-R6000 (4HP)</td><td colspan="2">cPCI-R6000P (4HP)</td><td colspan="2">cPCI-R6000D (8HP)</td></tr><tr><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td><td>Faceplate</td><td>Board</td></tr><tr><td>Gigabit Ethernet</td><td>Y x2 (2.16)</td><td></td><td>Y x2 (2.16)</td><td></td><td>Y x2 (2.16)</td><td></td></tr><tr><td>COM 2</td><td>Y (DB-9)</td><td></td><td>Y (DB-9)</td><td></td><td>Y (DB-9)</td><td></td></tr><tr><td>COM 4</td><td></td><td></td><td></td><td>Y (10-pin)</td><td></td><td>Y (10-pin)</td></tr><tr><td>USB 2.0</td><td>Y x2</td><td>Y (5-pin)</td><td>Y x2</td><td>Y (5-pin)</td><td>Y x4</td><td>Y (5-pin)</td></tr><tr><td>PIM</td><td></td><td></td><td></td><td>Y</td><td></td><td></td></tr><tr><td>VGA</td><td>Y</td><td></td><td>Y</td><td></td><td>Y</td><td></td></tr><tr><td>Serial ATA</td><td></td><td>Y x2 (7-pin)</td><td></td><td>Y x2 (7-pin)</td><td></td><td> $Y \times 3^{(2)}$ </td></tr><tr><td>Compact Flash</td><td></td><td></td><td></td><td></td><td></td><td> $opt.^{(3)}$ </td></tr><tr><td>PS/2 KB/MS</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Mic-in</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>Line-out</td><td></td><td></td><td></td><td></td><td>Y</td><td></td></tr><tr><td>SCSI</td><td>Y</td><td>Y</td><td></td><td></td><td>Y</td><td>Y</td></tr><tr><td>Floppy</td><td></td><td>Y</td><td></td><td>Y</td><td></td><td>Y</td></tr></table>

Table 2-2: RTM I/O Connectivity

# Notes:

1. Optional CompactFlash socket adapter kit (DB-CF-SB) for CompactFlash card installation (2.5"HDD and CF share the same space and cannot be installed simultaneously)
2. Two 7-pin SATA connectors for external HDDs and one connector for onboard 2.5" SATA HDD
3. Optional CF socket adapter kit (DB-CF-SA) for additional CF socket (CF and 2.5" HDD share the same space and cannot be installed simultaneously)

# 2.4 Power Requirements

In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires.

The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.

<table><tr><td>Voltage</td><td>Nominal Value</td><td>Tolerance</td><td>Max. Ripple (P - P)</td></tr><tr><td>5V</td><td>+5.0 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>3.3V</td><td>+3.3 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>+12V</td><td>+12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>-12V</td><td>-12 VDC</td><td>+5% / -5%</td><td>240 mV</td></tr><tr><td>V I/O (PCI I/O Buffer Voltage)</td><td>+3.3 VDC or +5 VDC</td><td>+5% / -3%</td><td>50 mV</td></tr><tr><td>GND</td><td></td><td></td><td></td></tr></table>

Table 2-3: CompactPCI Input Voltage Characteristics

# Power Consumption

This section provides information on the power consumption of cPCI-6880 Series with different CPUs, 2GB soldered onboard memory, 2GB SO-DIMM memory, 100GB onboard SATA HDD and cPCI-R6000 installed. The systems were tested in Idle Mode and Full Load Mode under Windows XP running Intel Thermal Analysis Tool. The cPCI-6880 is powered by 5V, 3.3V and optional + 12V.

Idle Mode under Windows XP

<table><tr><td>CPU</td><td colspan="2">Core 2 Duo T9400</td><td colspan="2">Core 2 Duo T7500</td><td colspan="2">Core 2 Duo P8400</td><td colspan="2">Celeron 575</td></tr><tr><td>Voltage (V)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td></tr><tr><td>+3.3</td><td>2.136</td><td>7.0488</td><td>2.112</td><td>6.9696</td><td>2.114</td><td>6.9762</td><td>2.105</td><td>6.9465</td></tr><tr><td>+5</td><td>2.577</td><td>12.885</td><td>2.578</td><td>12.89</td><td>2.62</td><td>13.1</td><td>3.136</td><td>15.68</td></tr><tr><td>+12V</td><td>0.0342</td><td>0.4104</td><td>0.0345</td><td>0.414</td><td>0.0334</td><td>0.4008</td><td>0.0344</td><td>0.4128</td></tr><tr><td>Total</td><td></td><td>20.3442</td><td></td><td>20.2736</td><td></td><td>20.477</td><td></td><td>23.0393</td></tr></table>

Table 2-4: Idle Mode Power Consumption

100% CPU Usage under Windows XP

<table><tr><td>CPU</td><td colspan="2">Core 2 Duo T9400</td><td colspan="2">Core 2 Duo T7500</td><td colspan="2">Core 2 Duo P8400</td><td colspan="2">Celeron 575</td></tr><tr><td>Voltage (V)</td><td>Current (A)</td><td>Power (W)</td><td>Current (A)</td><td>Power (W)</td><td>Voltage (A)</td><td>Current (W)</td><td>Power (A)</td><td>Current (W)</td></tr><tr><td>+3.3</td><td>2.204</td><td>7.2732</td><td>2.177</td><td>7.1841</td><td>2.171</td><td>7.1643</td><td>2.171</td><td>7.1643</td></tr><tr><td>+5</td><td>8.463</td><td>42.315</td><td>8.751</td><td>43.755</td><td>6.233</td><td>31.165</td><td>5.108</td><td>25.54</td></tr><tr><td>+12V</td><td>0.0351</td><td>0.4212</td><td>0.0329</td><td>0.3948</td><td>0.0318</td><td>0.3816</td><td>0.0332</td><td>0.3984</td></tr><tr><td>Total</td><td></td><td>50.0094</td><td></td><td>51.3339</td><td></td><td>38.7109</td><td></td><td>33.1027</td></tr></table>

Table 2-5: 100% CPU Usage Power Consumption

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# 3 Functional Description

The following sections describe the cPCI-6880 Series features and functions.

# 3.1 CPU

The following table lists the processors supported by the cPCI-6880 Series and their power ratings.

<table><tr><td>Features</td><td>Intel®CoreTM2 DuoT9400</td><td>Intel®CoreTM2 DuoP8400</td><td>Intel®CoreTM2 DuoT7500</td><td>Intel®Celeron®T3100</td><td>Intel®Celeron®575</td></tr><tr><td>Clock</td><td>2.53 GHz</td><td>2.26 GHz</td><td>2.2 GHz</td><td>1.93 GHz</td><td>2.0 GHz</td></tr><tr><td>L2 cache</td><td>6MB</td><td>3MB</td><td>4MB</td><td>1MB</td><td>1MB</td></tr><tr><td>FSB</td><td>1066MHz</td><td>1066MHz</td><td>800MHz</td><td>800MHz</td><td>667MHz</td></tr><tr><td>Max. Power (TDP $^{1}$ )</td><td>35W</td><td>25W</td><td>35W</td><td>35W</td><td>31W</td></tr><tr><td> $T_{junction\_MAX}^{2}$ </td><td>105°C</td><td>105°C</td><td>100°C</td><td>105°C</td><td>100°C</td></tr><tr><td>Process</td><td>45nm</td><td>45nm</td><td>65nm</td><td>45nm</td><td>65nm</td></tr><tr><td># of cores</td><td>2</td><td>2</td><td>2</td><td>2</td><td>1</td></tr></table>

# Notes:

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.
2. The maximum supported operating temperature.

# Intel® Core™2 Duo Processor

The Intel® Core™2 Duo mobile processors are high-performance, low-power processors based on the Intel® Core™ microarchitecture for Intel® Centrino® 2 technology. The following list outlines the key features of this processor:

▶ Dual-core processor for mobile with enhanced performance
▶ Supports Intel architecture with Intel® Wide Dynamic Execution
▶ Supports L1 cache-to-cache (C2C) transfer
▶ On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each core

The processor in DC-XE, standard voltage (SV) and LV have an on-die, up to 6-MB second-level, shared cache with Advanced Transfer Cache architecture
The processor in ULV single-core and dual-core have an on-die, up to 3-MB second-level, shared cache with Advanced Transfer Cache architecture
▶ Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets
The processor in DC-XE, SV and LV are offered at 1066-MHz, source-synchronous front side bus (FSB)
▶ Advanced power management features including Enhanced Intel SpeedStep® Technology and dynamic FSB frequency switching
▶ Digital thermal sensor (DTS)
Intel® 64 architecture
▶ Supports enhanced Intel® Virtualization Technology
▶ Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded Thermal Management (EMTTM)
▶ Supports PSI2 functionality
▶ SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies
▶ Execute Disable Bit support for enhanced security
Intel® Deep Power Down low-power state with P\_LVL6 I/O support
▶ Support for Intel® Trusted Execution Technology
▶ Half ratio support (N/2) for core to bus ratio

# Intel® Celeron® Processor T3100

The Intel® Celeron® Processor T3100 is a dual-core and 45nm process CPU that provides a low-cost mobile computing solution. The following list provides some of the key features of this processor:

▶ Dual-Core processor for mobile with enhanced performance
▶ Supports Intel architecture with Intel® Wide Dynamic Execution
▶ On-die, primary 32-KB instruction cache and 32-KB write-back data cache in each core

▶ L1 Cache to Cache (C2C) transfer
▶ On-die, 1-MB second level shared cache with advanced transfer cache architecture
▶ Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3)
▶ 800-MHz Source-Synchronous Front Side Bus (FSB)
▶ Digital Thermal Sensor (DTS)
Intel® 64 Technology
▶ PSI2 functionality
▶ Execute Disable Bit support for enhanced security
▶ Half ratio support (N/2) for Core to Bus ratio
Intel® Deeper Sleep low-power state with P\_LVL4 I/O Support (SFF processor only) processor only)

# Intel® Celeron® Processor 575

The following list provides some of the key features of this processor:

▶ Single core
▶ On-die, primary 32-KB instruction cache and 32-KB write-back data cache
▶ On-die, 1-MB second level shared cache with advanced transfer cache architecture
▶ 667-MHz source-synchronous front side bus (FSB)
▶ Supports Intel® architecture with dynamic execution
▶ Data prefetch logic
▶ Micro-FCPGA packaging technology
▶ MMX™ technology, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Supplemental Streaming SIMD Extensions 3 (SSSE 3)
▶ Digital Thermal Sensor (DTS)
▶ Execute Disable Bit support for enhanced security
Intel® 64 architecture (formerly Intel® EM64T)
▶ Architectural and performance enhancements of the Core microarchitecture.

# 3.2 Chipset

The cPCI-6880 Series incorporates the Mobile Intel® GM45 Graphics Memory Controller Hub (GMCH) and 82801IBM ICH9 Mobile (ICH9M) I/O Controller Hub.

# Intel® GM45 Graphics Memory Controller Hub

The following outlines the key features of GM45 GMCH.

# Processor Support

Intel® Core™2 Extreme, Intel® Core™2 Quad, and Intel® Core™2 Duo mobile processors based on the 45-nm process
Intel® Pentium® Dual Core and Intel® Celeron® mobile processors on 45 nm technology
Intel® Celeron® 575 processors on 65 nm technology
▶ 667-MHz, 800-MHz and 1066-MHz FSB
▶ Support for Dynamic FSB Frequency Switching
▶ Support for Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) (DMA)
36-bit interface to addressing, allowing the CPU to access the entire 64 GB of the GMCH's memory address space

# System Memory Support

▶ Supports DDR2 and DDR3 SDRAM (DDR2 only in cPCI-6880)
▶ Support for DDR2 at 667 MHz and 800 MHz
▶ Support for DDR3 at 667, 800 and 1066 MHz
▶ Support for DDR3 at 667 MHz when FSB is 667 MHz only
▶ Two Memory Channel Configurations supported in Dual-channel Asymmetric
▶ 8-GB maximum memory support
▶ Support for x8 and x16 DDR2 and DDR3 devices
▶ 64-bit wide per channel
▶ No support for ECC

# Direct Management Interface

▶ Chip-to-chip interface between (G)MCH and 82801 GMB/GHM
▶ Configurable as x2 or x4 DMI lanes
▶ 2-GB/s (1-GB/s each direction) point-to-point interface to ICH
▶ 32-bit downstream address

# Integrated Graphics

Intel Gen 5.0 integrated graphics engine with ten, fully-programmable cores
▶ 533-MHz core render clock @ 1.05-V core voltage
▶ Supports iHDMI/DVI, DP, TV-Out, LVDS, CRT and SDVO (the cPCI-6880 implements analog CRT, SDVO and LVDS only)
Intel® Dynamic Video Memory Technology (Intel® DVMT 5.0)
▶ Microsoft DirectX10 support
▶ Single channel LVDS interface support: 1x18 bpp (LVDS signals are routed to J5 connector)
▶ Integrated 300-MHz DAC analog CRT
▶ Analog monitor support up to QXGA
▶ Support for CRT Hot-Plug

# Intel® ICH9 Mobile I/O Controller Hub

The ICH9M provides extensive I/O support. Functions and capabilities include:

▶ ACPI Power Management Logic Support
▶ Integrated Serial ATA host controllers with independent DMA operation on up to four ports and AHCI support.
▶ Supports data transfer rates of up to 3.0 Gb/s (300 MB/s).
The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI\* mode using memory space. Software that uses legacy mode will not have AHCI\* capabilities.

▶ Provides 6 PCI Express x1 ports, supporting the PCI Express Base Specification, Revision 1.1. Each Root Port supports 2.5GB/s bandwidth in each direction (5 GB/s concurrent). The cPCI-6880 utilizes four PCI Express ports 3-6 for four Gigabit Ethernet controllers and configures the PCI Express ports 1-2 to PCI-Express x2 for connecting PCI Express to PCI bridge to support 64bit/66MHz CompactPCI bus..
▶ Enhanced DMA controller, interrupt controller, and timer functions
▶ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
▶ Supports Intel® High Definition Audio
▶ Supports Intel® Virtualization Technology for Directed I/O
▶ PCI Local Bus Specification, Revision 2.3 support for 33MHz PCI operations

\* AHCI is a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware.

# 3.3 DVI

The Silicon Image SDVO PanelLink Transmitter Sil1362 is designed into the cPCI-6880 to convert the SDVO signal to a DVI interface. The Sil1362A is fully compliant with Intel SDVO 1.0 and DVI 1.0.

# 3.4 Super I/O

The ITE IT8783F Super I/O is on a Low Pin Count interface supporting PS/2 keyboard/mouse, three 16C550-compatible serial ports, floppy drive interface, hardware monitor function to monitor CPU voltage, CPU temperature, power supply voltages and system temperature, and Watch Dog Timer with time resolution from minimum 1 second or minute to maximum 65,535 seconds or minutes.

# 3.5 Battery

The cPCI-6880 is provided with a 3.0V coin cell lithium battery for the Real Time Clock (RTC). The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. A Panasonic CR2032 is equipped on board by default.

# 3.6 PMC Site

The cPCI-6880 series supports a PMC site for front panel I/O expansion. The PMC site provides a 64-bit/66MHz PCI bus link using a Tundra Tsi384 PCI-Express-to-PCI bridge. The PMC site supports +3.3V signaling only.

The JN1 and JN2 connectors provide the signals for the 32-bit PCI bus. The JNX1 connector provides the 64 bit extension for the PMC interface. The optional JN3 connector equipped in the cPCI-6880P version supports user defined I/O signals and is routed to the CompactPCI J4 connector to rear I/O.

# 3.7 Onboard USB Flash

The cPCI-6880 provides a 4GB USB interface solid state NAND flash device onboard as a mass storage or boot device option. The cPCI-6880 uses one SST 4GB NAND Flash device on IDE bus which is converted from USB to IDE controller. The 4GB USB flash supports installation of Windows XP embedded or Linux operating systems or can simply be used as a storage device like a USB flash drive. Below are the key features of the SST NAND Flash:

▶ Low Current Operations:
▶ Active mode: 85mA Typical
▷ Sleep mode: 160 uA Typical
▶ Data security through user-selectable protection zones with advance NAND management technology.
▶ 10 Million write cycles
▶ Data retention for 3 years
▶ Multi-tasking Technology enables fast sustained write performance (Host-to=Flash) for up to 8MByte/sec

▶ Fast Sustained read performance (Flash-to-Host) for up to 30 MByte/sec
▶ 0 °C to 70 °C operating temperature

# 3.8 FWH Flash Memory & Failover

The cPCI-6880 series is designed with two onboard 16Mbit redundant SPI serial Flash devices for failover purposes, the BIOS1 FWH and BIOS2 FWH. The system BIOS will be flashed to both BIOS1 and BIOS2 FWHs at the factory. The BIOS1 device is the default boot BIOS. If the BIOS1 FWH fails to boot, the system will trigger the flash recovery procedure that will display the following messages on screen, indicating that the contents of the BIOS2 FWH are being copied to the BIOS1 FWH.

![American\nMegatrends\nwww.ami.com\nBIOS2\nStarting FLASH Recovery.\nNURAM data will be destroyed.\nCMOS data will be preserved.\nEnding FLASH Recovery.\nFLASH Update completed successfully.\nBooting BIOS1...](.cpci-6880-50-15066-1020-202-en/1ab8446435be5aab9eca35b979c263d379e41ce42c88da570c7c90f2a8195db0.jpg)

After the flash recovery procedure is complete, the display will show “Booting BIOS1...” and then the system will reboot automatically.

If the BIOS1 FWH fails to be properly flashed with the contents of the BIOS2 FWH or the BIOS1 FWH is not functional, the display will show “Booting BIOS2...” and the system will boot directly from the BIOS2 FWH.

# 4 Board Interfaces

# 4.1 cPCI-6880 SBC Board Layout

![SW2\nU5\nU4\nJN1\nJN2\nSW3\nSWX1\nJNX1\nJN3\nCN3\nCN4\nUX1\nU12\nJ5\nJ4\nCN5\nU15\nU14\nJ3\nUX4\nJ6\nUXX\nBT\nJ2\nCN6\nU21\nCN7\nCN8\nCN9\nUX18\nCN10\nJ1](.cpci-6880-50-15066-1020-202-en/79b86dc5a249e60c24668c74cc0858680dbc6771c3c3b449538cd1b785ffa54e.jpg)

<table><tr><td>U21</td><td>CPU socket</td><td>CN10</td><td>SATA/CF adapter card conn.</td></tr><tr><td>U15</td><td>GM45 GMCH</td><td>CN3</td><td>SO-DIMM socket</td></tr><tr><td>U5</td><td>ICH9M I/O Controller Hub</td><td>JN1-3/JNX1</td><td>PMC  $connectors^1$ </td></tr><tr><td>U4</td><td>PCIe-to-PCI Bridge</td><td>J1-J5</td><td>CompactPCI  $connectors^2$ </td></tr><tr><td>U12/14, UX1/4</td><td>Intel 82573L GbE controllers</td><td>SW2</td><td>Clear CMOS button</td></tr><tr><td>UX18</td><td>PCI to PCI universal Bridge</td><td>SW3/SWX1</td><td>Switches</td></tr><tr><td>UXX</td><td>Soldered memory chips</td><td>CN4/5</td><td>LAN ports</td></tr><tr><td>BT</td><td>Battery</td><td>CN6</td><td>COM port</td></tr><tr><td>J6</td><td>DVI-I connector</td><td>CN7-9</td><td>USB ports</td></tr></table>

Figure 4-1: cPCI-6880 SBC Board Layout

1. JN3 is populated on cPCI-6880P only
2. J4 is populated on cPCI-6880P only

# 4.2 cPCI-6880 SBC Front Panel

![PMC slot\nGbE1 GbE2\nDVI-I\nCOM 3x USB 2.0\nUSB\nRDT\nStatus LEDs\nDebug LEDs](.cpci-6880-50-15066-1020-202-en/a7542a1d22c5c2160b5d27558c300a16730f97c294b6e048e50976b93a41b50f.jpg)

Figure 4-2: cPCI-6880 Series Front Panel Layout

Status LEDs

<table><tr><td>LED</td><td>Color</td><td>Condition</td><td>Indication</td></tr><tr><td rowspan="3">Power (PW)</td><td rowspan="3">Green</td><td>OFF</td><td>System is off</td></tr><tr><td>ON</td><td>System is on</td></tr><tr><td>Blink</td><td>Failure to power on (Payload power failure)</td></tr><tr><td rowspan="4">Hot Swap (HW)</td><td rowspan="4">Blue</td><td>OFF</td><td>Handles closed, System is on</td></tr><tr><td>Fast Blink</td><td>Preparing to shut down system (LED: 0.1s on, 0.9s off)</td></tr><tr><td>ON</td><td>Handles open and SBC ready to be removed</td></tr><tr><td>Slow  $Blink^1$ </td><td>Voltages out of tolerance: 3.3V, 5V, 12V, 1.5V over ±5% (LED: 2s on, 1s off)</td></tr><tr><td rowspan="2">WDT (WDT)</td><td rowspan="2">Red</td><td>OFF</td><td>No Watchdog event</td></tr><tr><td>ON</td><td>Watchdog event alert</td></tr><tr><td rowspan="2">HDD (HD)</td><td rowspan="2">Amber</td><td>OFF</td><td>No HDD activity</td></tr><tr><td>Blink</td><td>Data read/write in process</td></tr></table>

Table 4-1: cPCI-6880 Front Panel Status LED Descriptions

Note $^{1}$ : Disabled by default. See “OemSetBlueLEDLongBlinking” on page 110.

# Debug LEDs

These LEDs are for debugging purposes. When the system is in normal operation, LEDs #2 and #3 are always ON.

<table><tr><td>1</td></tr><tr><td>2</td></tr><tr><td>3</td></tr><tr><td>4</td></tr></table>

# 4.3 cPCI-6880 SBC Assembly Layout

This section describes the final assembly layout of the cPCI-6880 Series. The cPCI-6880 is equipped by default with a removable DB-6920SAT adapter card to directly mount a 2.5" SATA hard drive to the SBC. The DB-6920SAT can be replaced by the DB-6880CF adapter board to provide a CompactFlash slot. Please contact your sales representative to purchase the DB-6880CF adapter and screw pack.

![SATA HDD\nHeat sink\nDB-6920SAT (default)](.cpci-6880-50-15066-1020-202-en/d3c21cf8d635665502f04d5042e62860f7c8a44ac6eb8114b546bf7cf14cc6ee.jpg)

![Heat sink\nDB-6880CF](.cpci-6880-50-15066-1020-202-en/532867f811ce2f754eb33dc3502f4902fd31401d66b5d5058616b714acb1fc3e.jpg)

Figure 4-3: cPCI-6880 SBC Assembly Layout

# 4.4 cPCI-R6000 RTM Board Layout

![82.53\nCN4-R\nrJ5\nCN2-R\nU26-R\nCNY1-R\nCN9-R\nSW3-R SW4-R\nCN15-R\nrJ3\nSW1-R SW2-R\nCN14-R\nCN16-R\nCN21-R\nJP1-R\nCN1-R\nCN10-R\nU31-R\nCN12-R\nCN5-R](.cpci-6880-50-15066-1020-202-en/079edc80ba30e435814f5096782a890ffd862e34178580dda9a03d38987090de.jpg)

<table><tr><td>U26-R</td><td>PCIe-to-PCI bridge</td><td>CN14-R</td><td>DB-R6000L2  $connector^1$ </td></tr><tr><td>U31-R</td><td>LSI53C1020 SCSI controller</td><td>CN12-R</td><td>External SCSI connector</td></tr><tr><td>JP1-R</td><td>USB pin header (5-pin)</td><td>CN15/16-R</td><td>USB ports</td></tr><tr><td>CN1/2-R</td><td>SATA port (7-pin)</td><td>CN20/21-R</td><td>GbE ports</td></tr><tr><td>CN5-R</td><td>Internal SCSI connector</td><td>CNY1-R</td><td>DVI to VGA adapter</td></tr><tr><td>CN9-R</td><td>Serial port</td><td>rJ3/5</td><td>CompactPCI Connectors</td></tr><tr><td>CN10-R</td><td>Serial pin header (10-pin)</td><td>SW1~4-R</td><td>Switches</td></tr><tr><td>CN4-R</td><td>Floppy connector</td><td></td><td></td></tr></table>

Figure 4-4: cPCI-R6000 RTM Board Layout

1. Used for cPCI-R6000D – shown here for clarity.

# 4.5 cPCI-R6000 RTM Front Panel

![SCSI\nGbE x2\nUSB 2.0 x2\nCOM\nVGA](.cpci-6880-50-15066-1020-202-en/e06aa7c3e4cfaa07d07cb9470358f5819cc33ed40d6f2417b3ff9b4f1c7d8b46.jpg)

Figure 4-5: cPCI-R6000 RTM Front Panel

# 4.6 cPCI-R6000D RTM Board Layout

![82.53\nCN4-R\nCN2-R\nCN19-R\nCN18-R\nCN11-R\nDB-R6000L2\n233.2±0.15\nJP1-R\nCN6-R\nCN1-R\nU31-R\nCN12-R\nCN10-R\nCN5-R](.cpci-6880-50-15066-1020-202-en/933f8bfb1ef7e429ab6d809e33b375afd944de0b36b72e55abb589f8b5406fbd.jpg)

<table><tr><td>CN1/2-R</td><td>SATA port (7-pin)</td><td>CN11-R</td><td>PS/2 KB/MS port</td></tr><tr><td>CN4-R</td><td>Floppy connector</td><td>CN12-R</td><td>External SCSI connector</td></tr><tr><td>CN5-R</td><td>Internal SCSI connector</td><td>CN18/19-R</td><td>USB ports</td></tr><tr><td>CN6-R</td><td>DB-6920SAT/DB-6920CF connector</td><td>JP1-R</td><td>USB pin header (5-pin)</td></tr><tr><td>CN10-R</td><td>Serial pin header (10-pin)</td><td></td><td></td></tr></table>

Figure 4-6: cPCI-R6000D RTM Board Layout

# 4.7 cPCI-R6000D RTM Front Panel

![Line-out\nMic-in\nPS/2\nUSB 2.0 x2\nSCSI\nGbE x2\nUSB 2.0 x2\nCOM\nVGA](.cpci-6880-50-15066-1020-202-en/db5aa72041972b944e1a9eb4e73139bcf2cdd870247e9c0927d19cfe3ef33181.jpg)

Figure 4-7: cPCI-R6000D RTM Front Panel

# 4.8 cPCI-R6000D RTM Assembly Layout

![82.53\n2.5' HDD bracket\nDVI to VGA adapter\nDB-6920SAT (default)\n233.2±0.15](.cpci-6880-50-15066-1020-202-en/303140617e0ba64abb30a42bbdfe4bc6739567e32a22d8d8bc5c342aec0933e4.jpg)

![82.53\nDB-6920CF\nDVI to VGA adapter\n233.2±0.15](.cpci-6880-50-15066-1020-202-en/f450f933372f080843b430b32d409db0fc0b113856996dada31374fbe2c2c411.jpg)

Figure 4-8: cPCI-R6000D RTM Assembly Layout

# 4.9 cPCI-R6000P RTM Board Layout

![82.53\nCN4-R\nrJ5\nCN2-R\nCNY1-R\nSW3-R SW4-R\nC9-R\nrJ3\nSW1-R SW2-R\nC15-R\nJP1-R\nCNI-R\nCNI10-R\nCNI2-R\nCNI21-R\nCNI20-R\nJN1-R\nJN2-R](.cpci-6880-50-15066-1020-202-en/6b8b2798682469f2989356f7ee9cc2b47c5b8a48ec45aaa43b401b0b40095836.jpg)

<table><tr><td>JP1-R</td><td>USB pin header (5-pin)</td><td>CN15/16-R</td><td>USB ports</td></tr><tr><td>CN1/2-R</td><td>SATA port (7-pin)</td><td>CN20/21-R</td><td>GbE ports</td></tr><tr><td>JN1/2-R</td><td>PIM connectors</td><td>CNY1-R</td><td>DVI-to-VGA adapter</td></tr><tr><td>CN9-R</td><td>Serial port (DB-9)</td><td>rJ3/5</td><td>CompactPCI Connectors</td></tr><tr><td>CN10-R</td><td>Serial pin header (10-pin)</td><td>SW1~4-R</td><td>Switches</td></tr><tr><td>CN4-R</td><td>Floppy connector</td><td></td><td></td></tr></table>

Figure 4-9: cPCI-R6000P RTM Board Layout

# 4.10 cPCI-R6000P RTM Front Panel

![PIM\nGbE x2\nUSB 2.0 x2\nCOM\nVGA](.cpci-6880-50-15066-1020-202-en/66589caeb5a9056134befb1b671317c6e3f97b2c91699cd3a0d3c20b5c75e395.jpg)

Figure 4-10: cPCI-R6000P RTM Front Panel

# 4.11 Connector Pin Assignments

USB Connectors (CN7-9, CN2-L, CN3-L, CN15-R, CN16-R, JP1-R)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![1\n2\n3\n4](.cpci-6880-50-15066-1020-202-en/0eb3e3ee95c18eb9d6ff43c9d4f017a2ed8311ad4e1b20d918de28856374de1b.jpg)

Table 4-2: USB Connector Pin Definition

RJ-45 Serial Port (CN-6)

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>DCD#, Data carrier detect</td></tr><tr><td>2</td><td>RTS#, Request to send</td></tr><tr><td>3</td><td>DSR#, Data set ready</td></tr><tr><td>4</td><td>TXD, Transmit data</td></tr><tr><td>5</td><td>RXD, Receive data</td></tr><tr><td>6</td><td>GND, ground</td></tr><tr><td>7</td><td>CTS#, Clear to send</td></tr><tr><td>8</td><td>DTR#, Data terminal ready</td></tr></table>

![1\n6](.cpci-6880-50-15066-1020-202-en/d626d5afbb37ffbf6febc74f52c690a4018cbc16d304c633c5d88f906cde80e6.jpg)

Table 4-3: RJ-45 Serial Port Pin Definition
PS/2 Keyboard/Mouse Connector (CN11-R)

<table><tr><td>Pin #</td><td>Signal</td><td>Function</td></tr><tr><td>1</td><td>KBDATA</td><td>Keyboard Data</td></tr><tr><td>2</td><td>MSDATA</td><td>Mouse Data</td></tr><tr><td>3</td><td>GND</td><td>Ground</td></tr><tr><td>4</td><td>+5V</td><td>Power</td></tr><tr><td>5</td><td>KBCLK</td><td>Keyboard Clock</td></tr><tr><td>6</td><td>MSCLK</td><td>Mouse Clock</td></tr></table>

![6\n5\n4\n3\n2 1](.cpci-6880-50-15066-1020-202-en/c482ae448c86dc5b3a5423225c2522f83d78269e8fad81406907eec973461c9b.jpg)

Table 4-4: PS/2 Keyboard/Mouse Connector Pin Definition

RJ-45 Gigabit Ethernet Connectors (CN4, CN5, CN20-R, CN21-R)

<table><tr><td>Pin #</td><td>10BASE-T/100BASE-TX</td><td>1000BASE-T</td></tr><tr><td>1</td><td>TX+</td><td>BI_DA+</td></tr><tr><td>2</td><td>TX-</td><td>BI_DA-</td></tr><tr><td>3</td><td>RX+</td><td>BI_DB+</td></tr><tr><td>4</td><td>--</td><td>BI_DC+</td></tr><tr><td>5</td><td>--</td><td>BI_DC-</td></tr><tr><td>6</td><td>RX-</td><td>BI_DB-</td></tr><tr><td>7</td><td>--</td><td>BI_DD+</td></tr><tr><td>8</td><td>--</td><td>BI_DD-</td></tr></table>

![1\n8\nActivity Speed](.cpci-6880-50-15066-1020-202-en/29e4d698c7865dddbfd162295f299494c280c37364e7de93e0edd4949bacb8f0.jpg)

Table 4-5: GbE Connector Pin Definitions

<table><tr><td colspan="2">Status (CN4, CN5)</td><td>Speed LED (Green/Amber)</td><td>Activity LED (Amber)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Amber</td><td>ON</td></tr><tr><td>Active</td><td>Amber</td><td>Blinking</td></tr></table>

Table 4-6: GbE LED CN4, CN5 Status Definitions

<table><tr><td colspan="2">Status (CN20-R, CN21-R)</td><td>Speed LED (Green/Amber)</td><td>Activity LED (Amber)</td></tr><tr><td colspan="2">Network link is not established or system powered off</td><td>OFF</td><td>OFF</td></tr><tr><td rowspan="2">10 Mbps</td><td>Link</td><td>OFF</td><td>ON</td></tr><tr><td>Active</td><td>OFF</td><td>Blinking</td></tr><tr><td rowspan="2">100 Mbps</td><td>Link</td><td>Amber</td><td>ON</td></tr><tr><td>Active</td><td>Amber</td><td>Blinking</td></tr><tr><td rowspan="2">1000 Mbps</td><td>Link</td><td>Green</td><td>ON</td></tr><tr><td>Active</td><td>Green</td><td>Blinking</td></tr></table>

Table 4-7: GbE LED CN20-R, CN21-R Status Definitions

DB-9 Serial Port (CN9-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>DCD, Data carrier detect</td></tr><tr><td>2</td><td>RXD, Receive data</td></tr><tr><td>3</td><td>TXD, Transmit data</td></tr><tr><td>4</td><td>DTR, Data terminal ready</td></tr><tr><td>5</td><td>IsoGND, Isolated ground</td></tr><tr><td>6</td><td>DSR, Data set ready</td></tr><tr><td>7</td><td>RTS, Request to send</td></tr><tr><td>8</td><td>CTS, Clear to send</td></tr><tr><td>9</td><td>RI, Ring indicator</td></tr></table>

![6\n1\n5](.cpci-6880-50-15066-1020-202-en/bb7fbf55a83de3c7e510b801a7218781d78cd3b818c2822c74c6ea3fbdfa596b.jpg)

Table 4-8: COM1-2 Serial Port Connector Pin Definition
Onboard Serial Port Connector (CN10-R)

<table><tr><td>Pin #</td><td>RS-232</td></tr><tr><td>1</td><td>Not used</td></tr><tr><td>2</td><td>Not used</td></tr><tr><td>3</td><td>RXD, Receive data</td></tr><tr><td>4</td><td>Not used</td></tr><tr><td>5</td><td>TXD, Transmit data</td></tr><tr><td>6</td><td>Not used</td></tr><tr><td>7</td><td>Not used</td></tr><tr><td>8</td><td>Not used</td></tr><tr><td>9</td><td>IsoGND, Isolated ground</td></tr><tr><td>10</td><td>Not used</td></tr></table>

![9\n1\n10\n2](.cpci-6880-50-15066-1020-202-en/5aaa37295fccbc5a5c1849aaa669d0716c3bc7c9734a2a7abf0a2d72cf2f25e7.jpg)

Table 4-9: Onboard Serial Port Connector Pin Definition

DVI-I Connector (J6)
![Front view of a 24-pin D-sub connector (no text or symbols visible)](.cpci-6880-50-15066-1020-202-en/265781d181c943a61ed06d2d837995a81cf9332ae883c728dbe220e1a4944077.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>TMDS Data2-</td><td>16</td><td>Hot Plug Detect</td></tr><tr><td>2</td><td>TMDS Data2+</td><td>17</td><td>TMDS Data0-</td></tr><tr><td>3</td><td>TMDS Data2/4 Shield</td><td>18</td><td>TMDSData0+</td></tr><tr><td>4</td><td>TMDS Data4-</td><td>19</td><td>TMDS Data0/5 Shield</td></tr><tr><td>5</td><td>TMDS Data4+</td><td>20</td><td>TMDS Data5-</td></tr><tr><td>6</td><td>DDC Clock [SCL]</td><td>21</td><td>TMDS Data5+</td></tr><tr><td>7</td><td>DDC Data [SDA]</td><td>22</td><td>TMDS Clock Shield</td></tr><tr><td>8</td><td>Analog vertical sync</td><td>23</td><td>TMDS Clock +</td></tr><tr><td>9</td><td>TMDS Data1-</td><td>24</td><td>TMDS Clock -</td></tr><tr><td>10</td><td>TMDS Data1+</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>TMDS Data1/3 Shield</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>TMDS Data3-</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>TMDS Data3+</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 4-10: DVI-I Connector Pin Definition (J6)

DVI-I (Analog only) Connector (CNY1-R)
![Front view of a D-sub connector with pin numbering (no text or symbols)](.cpci-6880-50-15066-1020-202-en/bd71ff2cd8ab9688fddd2aeab324ed829d5968ccab0ef25493366789ae518f0a.jpg)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>16</td><td>NC</td></tr><tr><td>2</td><td>NC</td><td>17</td><td>NC</td></tr><tr><td>3</td><td>GND</td><td>18</td><td>NC</td></tr><tr><td>4</td><td>NC</td><td>19</td><td>GND</td></tr><tr><td>5</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>6</td><td>DDCCLK_5V</td><td>21</td><td>NC</td></tr><tr><td>7</td><td>DDCDAT_5V</td><td>22</td><td>GND</td></tr><tr><td>8</td><td>VSYNC</td><td>23</td><td>NC</td></tr><tr><td>9</td><td>NC</td><td>24</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>C1</td><td>Analog Red</td></tr><tr><td>11</td><td>GND</td><td>C2</td><td>Analog Green</td></tr><tr><td>12</td><td>NC</td><td>C3</td><td>Analog Blue</td></tr><tr><td>13</td><td>NC</td><td>C4</td><td>Analog Horizontal Sync</td></tr><tr><td>14</td><td>+5 V Power</td><td>C5</td><td>Analog GND Return</td></tr><tr><td>15</td><td>GND</td><td></td><td></td></tr></table>

Table 4-11: DVI-I (Analog only) Connector Pin Definition (CNY1)

Serial ATA Connectors (CN1-R, CN2-R)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TX+</td></tr><tr><td>3</td><td>TX-</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RX-</td></tr><tr><td>6</td><td>RX+</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n7](.cpci-6880-50-15066-1020-202-en/7a4d278a1871b31b5d0e644fb33b07566df3ba42db9846c8ae10e73170c3319f.jpg)

Table 4-12: SATA Connector Pin Definition

Serial ATA Connector on DB-6920SAT

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>S1</td><td>GND</td></tr><tr><td>S2</td><td>TX+</td></tr><tr><td>S3</td><td>TX-</td></tr><tr><td>S4</td><td>GND</td></tr><tr><td>S5</td><td>RX-</td></tr><tr><td>S6</td><td>RX+</td></tr><tr><td>S7</td><td>GND</td></tr><tr><td>P1</td><td>NC</td></tr><tr><td>P2</td><td>NC</td></tr><tr><td>P3</td><td>NC</td></tr><tr><td>P4</td><td>GND</td></tr><tr><td>P5</td><td>GND</td></tr><tr><td>P6</td><td>GND</td></tr><tr><td>P7</td><td>5V</td></tr><tr><td>P8</td><td>5V</td></tr><tr><td>P9</td><td>5V</td></tr><tr><td>P10</td><td>GND</td></tr><tr><td>P11</td><td>Reserved</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13~P15</td><td>12V</td></tr></table>

![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-6880-50-15066-1020-202-en/9c19c7c3455501bcff65cabebac45bf903e4c29c1bb7e0e447b27143d049190b.jpg)

Table 4-13: DB-6910SAT SATA Connector Pin Definition

PMC Connector (JN1, JN2, JN3, JNX1)

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td><td>JN3 Signal</td><td>JNX1 Signal</td></tr><tr><td>1</td><td>PMC_TCK</td><td>P12V</td><td>PIO1</td><td>NC</td></tr><tr><td>2</td><td>N12V</td><td>PMC_TRST-L</td><td>PIO2</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PMC_TMS</td><td>PIO3</td><td>GND</td></tr><tr><td>4</td><td>PCIX_INTA-L</td><td>NC (PMC_TDO)</td><td>PIO4</td><td>PCIX_CBE-L7</td></tr><tr><td>5</td><td>PCIX_INTB-L</td><td>PMC_TDI</td><td>PIO5</td><td>PCIX_CBE-L6</td></tr><tr><td>6</td><td>PCIX_INTC-L</td><td>GND</td><td>PIO6</td><td>PCIX_CBE-L5</td></tr><tr><td>7</td><td>PMC_MOD-L1</td><td>GND</td><td>PIO7</td><td>PCIX_CBE-L4</td></tr><tr><td>8</td><td>P5V</td><td>NC</td><td>PIO8</td><td>GND</td></tr><tr><td>9</td><td>PCIX_INTD-L</td><td>NC</td><td>PIO9</td><td>PMC_VIO</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>PIO10</td><td>PCIX_PAR64</td></tr><tr><td>11</td><td>GND</td><td>PMC_MOD-L2</td><td>PIO11</td><td>PCIX_AD63</td></tr><tr><td>12</td><td>P3V3_PMCAUX</td><td>P3V3</td><td>PIO12</td><td>PCIX_AD62</td></tr><tr><td>13</td><td>CLK66_PCIX_PMC</td><td>PMC_RST-L</td><td>PIO13</td><td>PCIX_AD61</td></tr><tr><td>14</td><td>GND</td><td>PMC_MOD-L3</td><td>PIO14</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>P3V3</td><td>PIO15</td><td>GND</td></tr><tr><td>16</td><td>PCIX_GNT-L0</td><td>PMC_MOD-L4</td><td>PIO16</td><td>PCIX_AD60</td></tr><tr><td>17</td><td>PCIX_REQ-L0</td><td>PMC_PME-L</td><td>PIO17</td><td>PCIX_AD59</td></tr><tr><td>18</td><td>P5V</td><td>GND</td><td>PIO18</td><td>PCIX_AD58</td></tr><tr><td>19</td><td>PMC_VIO</td><td>PCIX_AD30</td><td>PIO19</td><td>PCIX_AD57</td></tr><tr><td>20</td><td>PCIX_AD31</td><td>PCIX_AD29</td><td>PIO20</td><td>GND</td></tr><tr><td>21</td><td>PCIX_AD28</td><td>GND</td><td>PIO21</td><td>GND</td></tr><tr><td>22</td><td>PCIX_AD27</td><td>PCIX_AD26</td><td>PIO22</td><td>PCIX_AD56</td></tr><tr><td>23</td><td>PCIX_AD25</td><td>PCIX_AD24</td><td>PIO23</td><td>PCIX_AD55</td></tr><tr><td>24</td><td>GND</td><td>PCIX_AD23</td><td>PIO24</td><td>PCIX_AD54</td></tr><tr><td>25</td><td>GND</td><td>PMC_IDSEL</td><td>PIO25</td><td>PCIX_AD53</td></tr><tr><td>26</td><td>PCIX_CBE-L3</td><td>PCIX_AD23</td><td>PIO26</td><td>GND</td></tr><tr><td>27</td><td>PCIX_AD22</td><td>P3V3</td><td>PIO27</td><td>GND</td></tr><tr><td>28</td><td>PCIX_AD21</td><td>PCIX_AD20</td><td>PIO28</td><td>PCIX_AD52</td></tr><tr><td>29</td><td>PCIX_AD19</td><td>PCIX_AD18</td><td>PIO29</td><td>PCIX_AD51</td></tr><tr><td>30</td><td>P5V</td><td>GND</td><td>PIO30</td><td>PCIX_AD50</td></tr><tr><td>31</td><td>PCIX_FRAME-L</td><td>PCIX_AD16</td><td>PIO31</td><td>PCIX_AD49</td></tr><tr><td>32</td><td>PCIX_AD17</td><td>PCIX_CBE-L2</td><td>PIO32</td><td>GND</td></tr></table>

![64\n63\n2\n1](.cpci-6880-50-15066-1020-202-en/98a5a6a9d4864f6dea51be5657ab2fd7ab0e9c93400ba29d6553c7656cc42888.jpg)

Table 4-14: PMC Connector Pin Definitions

<table><tr><td>Pin#</td><td>JN1 Signal</td><td>JN2 Signal</td><td>JN3 Signal</td><td>JNX1 Signal</td></tr><tr><td>33</td><td>PCIX_FRAME-L</td><td>GND</td><td>PIO33</td><td>GND</td></tr><tr><td>34</td><td>GND</td><td>NC</td><td>PIO34</td><td>PCIX_AD48</td></tr><tr><td>35</td><td>GND</td><td>PCIX_TRDY-L</td><td>PIO35</td><td>PCIX_AD47</td></tr><tr><td>36</td><td>PCIX_IRDY-L</td><td>P3V3</td><td>PIO36</td><td>PCIX_AD46</td></tr><tr><td>37</td><td>PCIX_DEVSEL-L</td><td>GND</td><td>PIO37</td><td>PCIX_AD45</td></tr><tr><td>38</td><td>P5V</td><td>PCIX_STOP-L</td><td>PIO38</td><td>GND</td></tr><tr><td>39</td><td>PCIX_PCIXCAP</td><td>PCIX_PERR-L</td><td>PIO39</td><td>GND</td></tr><tr><td>40</td><td>PCIX_LOCK-L</td><td>GND</td><td>PIO40</td><td>PCIX_AD44</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td><td>PIO41</td><td>PCIX_AD43</td></tr><tr><td>42</td><td>NC</td><td>PCIX_SERR-L</td><td>PIO42</td><td>PCIX_AD42</td></tr><tr><td>43</td><td>PCIX_PAR</td><td>PCIX_CBE-L1</td><td>PIO43</td><td>PCIX_AD41</td></tr><tr><td>44</td><td>GND</td><td>GND</td><td>PIO44</td><td>GND</td></tr><tr><td>45</td><td>PMC_VIO</td><td>PCIX_AD14</td><td>PIO45</td><td>GND</td></tr><tr><td>46</td><td>PCIX_AD15</td><td>PCIX_AD13</td><td>PIO46</td><td>PCIX_AD40</td></tr><tr><td>47</td><td>PCIX_AD12</td><td>PCIX_M66EN</td><td>PIO47</td><td>PCIX_AD39</td></tr><tr><td>48</td><td>PCIX_AD11</td><td>PCIX_AD10</td><td>PIO48</td><td>PCIX_AD38</td></tr><tr><td>49</td><td>PCIX_AD9</td><td>PCIX_AD8</td><td>PIO49</td><td>PCIX_AD37</td></tr><tr><td>50</td><td>P5V</td><td>P3V3</td><td>PIO50</td><td>GND</td></tr><tr><td>51</td><td>GND</td><td>PCIX_AD7</td><td>PIO51</td><td>GND</td></tr><tr><td>52</td><td>PCIX_CBE-L0</td><td>NC</td><td>PIO52</td><td>PCIX_AD36</td></tr><tr><td>53</td><td>PCIX_AD6</td><td>P3V3</td><td>PIO53</td><td>PCIX_AD35</td></tr><tr><td>54</td><td>PCIX_AD5</td><td>NC</td><td>PIO54</td><td>PCIX_AD34</td></tr><tr><td>55</td><td>PCIX_AD4</td><td>NC</td><td>PIO55</td><td>PCIX_AD33</td></tr><tr><td>56</td><td>GND</td><td>GND</td><td>PIO56</td><td>GND</td></tr><tr><td>57</td><td>PMC_VIO</td><td>NC</td><td>PIO57</td><td>GND</td></tr><tr><td>58</td><td>PCIX_AD3</td><td>NC</td><td>PIO58</td><td>PCIX_AD32</td></tr><tr><td>59</td><td>PCIX_AD2</td><td>GND</td><td>PIO59</td><td>NC</td></tr><tr><td>60</td><td>PCIX_AD1</td><td>NC</td><td>PIO60</td><td>NC</td></tr><tr><td>61</td><td>PCIX_AD0</td><td>PCIX_ACK64-L</td><td>PIO61</td><td>NC</td></tr><tr><td>62</td><td>P5V</td><td>P3V3</td><td>PIO62</td><td>GND</td></tr><tr><td>63</td><td>GND</td><td>GND</td><td>PIO63</td><td>GND</td></tr><tr><td>64</td><td>PCIX_REQ64-L</td><td>NC</td><td>PIO64</td><td>NC</td></tr></table>

Table 4-14: PMC Connector Pin Definitions (cont'd)

68-pin SCSI Connector (CN12-R)

<table><tr><td>Signal</td><td>Pin #</td><td>Pin #</td><td>Signal</td></tr><tr><td>SCSI-SDP12</td><td>1</td><td>35</td><td>SCSI-SDN12</td></tr><tr><td>SCSI-SDP13</td><td>2</td><td>36</td><td>SCSI-SDN13</td></tr><tr><td>SCSI-SDP14</td><td>3</td><td>37</td><td>SCSI-SDN14</td></tr><tr><td>SCSI-SDP15</td><td>4</td><td>38</td><td>SCSI-SDN15</td></tr><tr><td>SCSI-SDP1-P1</td><td>5</td><td>39</td><td>SCSI-SDP1-N1</td></tr><tr><td>SCSI-SDP0</td><td>6</td><td>40</td><td>SCSI-SDN0</td></tr><tr><td>SCSI-SDP1</td><td>7</td><td>41</td><td>SCSI-SDN1</td></tr><tr><td>SCSI-SDP2</td><td>8</td><td>42</td><td>SCSI-SDN2</td></tr><tr><td>SCSI-SDP3</td><td>9</td><td>43</td><td>SCSI-SDN3</td></tr><tr><td>SCSI-SDP4</td><td>10</td><td>44</td><td>SCSI-SDN4</td></tr><tr><td>SCSI-SDP5</td><td>11</td><td>45</td><td>SCSI-SDN5</td></tr><tr><td>SCSI-SDP6</td><td>12</td><td>46</td><td>SCSI-SDN6</td></tr><tr><td>SCSI-SDP7</td><td>13</td><td>47</td><td>SCSI-SDN7</td></tr><tr><td>SCSI-SDP0-P0</td><td>14</td><td>48</td><td>SCSI-SDP0-N0</td></tr><tr><td>GND</td><td>15</td><td>49</td><td>GND</td></tr><tr><td>DIFFSEN</td><td>16</td><td>50</td><td>NC</td></tr><tr><td>P3V3_SCSI</td><td>17</td><td>51</td><td>P3V3_SCSI</td></tr><tr><td>P3V3_SCSI</td><td>18</td><td>52</td><td>P3V3_SCSI</td></tr><tr><td>NC</td><td>19</td><td>53</td><td>NC</td></tr><tr><td>GND</td><td>20</td><td>54</td><td>GND</td></tr><tr><td>SCSI-SATN-P</td><td>21</td><td>55</td><td>SCSI-SATN-N</td></tr><tr><td>GND</td><td>22</td><td>56</td><td>GND</td></tr><tr><td>SCSI-SBSY-P</td><td>23</td><td>57</td><td>SCSI-SBSY-N</td></tr><tr><td>SCSI-SACK-P</td><td>24</td><td>58</td><td>SCSI-SACK-N</td></tr><tr><td>SCSI-SRST-P</td><td>25</td><td>59</td><td>SCSI-SRST-N</td></tr><tr><td>SCSI-SMSG-P</td><td>26</td><td>60</td><td>SCSI-SMSG-N</td></tr><tr><td>SCSI-SSEL-P</td><td>27</td><td>61</td><td>SCSI-SSEL-N</td></tr><tr><td>SCSI-SCD-P</td><td>28</td><td>62</td><td>SCSI-SCD-N</td></tr><tr><td>SCSI-SREQ-P</td><td>29</td><td>63</td><td>SCSI-SREQ-N</td></tr><tr><td>SCSI-SIO-P</td><td>30</td><td>64</td><td>SCSI-SIO-N</td></tr><tr><td>SCSI-SDP8</td><td>31</td><td>65</td><td>SCSI-SDN8</td></tr><tr><td>SCSI-SDP9</td><td>32</td><td>66</td><td>SCSI-SDN9</td></tr><tr><td>SCSI-SDP10</td><td>33</td><td>67</td><td>SCSI-SDN10</td></tr><tr><td>SCSI-SDP11</td><td>34</td><td>68</td><td>SCSI-SDN11</td></tr></table>

![1\n35\n34\n68](.cpci-6880-50-15066-1020-202-en/20d0708a1d9d517381569c2ba0932fe0900649f85d1238717839023cbe047d0d.jpg)

Table 4-15: 68-pin SCSI Pin Definition

Floppy Connector 34-pin (CN4-R)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>Extended Density</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>No Connect</td></tr><tr><td>5</td><td>NC</td><td>6</td><td>Data Rate</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>Index</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>Motor A Select</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>Drive B Select</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>Drive A Select</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>Motor B Select</td></tr><tr><td>17</td><td>GND</td><td>18</td><td>Step Direction</td></tr><tr><td>19</td><td>GND</td><td>20</td><td>Step Pulse</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>Write Data</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>Write Gate</td></tr><tr><td>25</td><td>GND</td><td>26</td><td>Track 0</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>Write Protect</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>Read Data</td></tr><tr><td>31</td><td>GND</td><td>32</td><td>Side 1</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>Disk Change</td></tr></table>

![1\n2\n33\n34](.cpci-6880-50-15066-1020-202-en/ce7e7c826455a7771b4305d8da29132f306613c5297faaeacc81ba0f98f54207.jpg)

Table 4-16: Floppy Connector Pin Definition

PIM Connector (JN1-R)

<table><tr><td>Pin#</td><td>Signal Name</td><td>Signal Name</td><td>Pin#</td></tr><tr><td>1</td><td>PIM1</td><td>PIM2</td><td>2</td></tr><tr><td>3</td><td>PIM3</td><td>PIM4</td><td>4</td></tr><tr><td>5</td><td>PIM5</td><td>PIM6</td><td>6</td></tr><tr><td>7</td><td>PIM7</td><td>PIM8</td><td>8</td></tr><tr><td>9</td><td>PIM9</td><td>PIM10</td><td>10</td></tr><tr><td>11</td><td>PIM11</td><td>PIM12</td><td>12</td></tr><tr><td>13</td><td>PIM13</td><td>PIM14</td><td>14</td></tr><tr><td>15</td><td>PIM15</td><td>PIM16</td><td>16</td></tr><tr><td>17</td><td>PIM17</td><td>PIM18</td><td>18</td></tr><tr><td>19</td><td>PIM19</td><td>PIM20</td><td>20</td></tr><tr><td>21</td><td>PIM21</td><td>PIM22</td><td>22</td></tr><tr><td>23</td><td>PIM23</td><td>PIM24</td><td>24</td></tr><tr><td>25</td><td>PIM25</td><td>PIM26</td><td>26</td></tr><tr><td>27</td><td>PIM27</td><td>PIM28</td><td>28</td></tr><tr><td>29</td><td>PIM29</td><td>PIM30</td><td>30</td></tr><tr><td>31</td><td>PIM31</td><td>PIM32</td><td>32</td></tr><tr><td>33</td><td>PIM33</td><td>PIM34</td><td>34</td></tr><tr><td>35</td><td>PIM35</td><td>PIM36</td><td>36</td></tr><tr><td>37</td><td>PIM37</td><td>PIM38</td><td>38</td></tr><tr><td>39</td><td>PIM39</td><td>PIM40</td><td>40</td></tr><tr><td>41</td><td>PIM41</td><td>PIM42</td><td>42</td></tr><tr><td>43</td><td>PIM43</td><td>PIM44</td><td>44</td></tr><tr><td>45</td><td>PIM45</td><td>PIM46</td><td>46</td></tr><tr><td>47</td><td>PIM47</td><td>PIM48</td><td>48</td></tr><tr><td>49</td><td>PIM49</td><td>PIM50</td><td>50</td></tr><tr><td>51</td><td>PIM51</td><td>PIM52</td><td>52</td></tr><tr><td>53</td><td>PIM53</td><td>PIM54</td><td>54</td></tr><tr><td>55</td><td>PIM55</td><td>PIM56</td><td>56</td></tr><tr><td>57</td><td>PIM57</td><td>PIM58</td><td>58</td></tr><tr><td>59</td><td>PIM59</td><td>PIM60</td><td>60</td></tr><tr><td>61</td><td>PIM61</td><td>PIM62</td><td>62</td></tr><tr><td>63</td><td>PIM63</td><td>PIM64</td><td>64</td></tr></table>

![64\n63\n2\n1](.cpci-6880-50-15066-1020-202-en/52261ed8e8f786f82f3df30e60bf8532f82621628a0fff51fa5b7aca72e75d52.jpg)

Table 4-17: PIM Connector (JN1-R) Pin Definition

PIM Connector (JN2-R)

<table><tr><td>Pin#</td><td>Signal Name</td><td>Signal Name</td><td>Pin#</td></tr><tr><td>1</td><td>NC</td><td>NC</td><td>2</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>4</td></tr><tr><td>5</td><td>P5V</td><td>NC</td><td>6</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>8</td></tr><tr><td>9</td><td>NC</td><td>P3V3</td><td>10</td></tr><tr><td>11</td><td>NC</td><td>NC</td><td>12</td></tr><tr><td>13</td><td>GND</td><td>NC</td><td>14</td></tr><tr><td>15</td><td>NC</td><td>NC</td><td>16</td></tr><tr><td>17</td><td>NC</td><td>GND</td><td>18</td></tr><tr><td>19</td><td>NC</td><td>NC</td><td>20</td></tr><tr><td>21</td><td>P5V</td><td>NC</td><td>22</td></tr><tr><td>23</td><td>NC</td><td>NC</td><td>24</td></tr><tr><td>25</td><td>NC</td><td>P3V3</td><td>26</td></tr><tr><td>27</td><td>NC</td><td>NC</td><td>28</td></tr><tr><td>29</td><td>GND</td><td>NC</td><td>30</td></tr><tr><td>31</td><td>NC</td><td>NC</td><td>32</td></tr><tr><td>33</td><td>NC</td><td>GND</td><td>34</td></tr><tr><td>35</td><td>NC</td><td>NC</td><td>36</td></tr><tr><td>37</td><td>P5V</td><td>NC</td><td>38</td></tr><tr><td>39</td><td>NC</td><td>NC</td><td>40</td></tr><tr><td>41</td><td>NC</td><td>P3V3</td><td>42</td></tr><tr><td>43</td><td>NC</td><td>NC</td><td>44</td></tr><tr><td>45</td><td>GND</td><td>NC</td><td>46</td></tr><tr><td>47</td><td>NC</td><td>NC</td><td>48</td></tr><tr><td>49</td><td>NC</td><td>GND</td><td>50</td></tr><tr><td>51</td><td>NC</td><td>NC</td><td>52</td></tr><tr><td>53</td><td>P5V</td><td>NC</td><td>54</td></tr><tr><td>55</td><td>NC</td><td>NC</td><td>56</td></tr><tr><td>57</td><td>NC</td><td>P3V3</td><td>58</td></tr><tr><td>59</td><td>NC</td><td>NC</td><td>60</td></tr><tr><td>61</td><td>NC</td><td>NC</td><td>62</td></tr><tr><td>63</td><td>NC</td><td>NC</td><td>64</td></tr></table>

![64\n63\n2\n1](.cpci-6880-50-15066-1020-202-en/30947b0fdc2834efc5bf902ea26a38cf8a4a84b97f16cade9d28a39fa2f30bf7.jpg)

Table 4-18: PIM Connector (JN2-R) Pin Definition

CompactFlash Connector (CN13)

<table><tr><td>Signal Name</td><td>Pin#</td><td>Pin#</td><td>Signal Name</td></tr><tr><td>GND</td><td>1</td><td>26</td><td>GND</td></tr><tr><td>DD3</td><td>2</td><td>27</td><td>DD11</td></tr><tr><td>DD4</td><td>3</td><td>28</td><td>DD12</td></tr><tr><td>DD5</td><td>4</td><td>29</td><td>DD13</td></tr><tr><td>DD6</td><td>5</td><td>30</td><td>DD14</td></tr><tr><td>DD7</td><td>6</td><td>31</td><td>DD15</td></tr><tr><td>CS1J</td><td>7</td><td>32</td><td>CS3J</td></tr><tr><td>GND</td><td>8</td><td>33</td><td>GND</td></tr><tr><td>GND</td><td>9</td><td>34</td><td>SDIORJ</td></tr><tr><td>GND</td><td>10</td><td>35</td><td>SDIOWJ</td></tr><tr><td>GND</td><td>11</td><td>36</td><td>5V</td></tr><tr><td>GND</td><td>12</td><td>37</td><td>IRQ15</td></tr><tr><td>5V</td><td>13</td><td>38</td><td>5V</td></tr><tr><td>GND</td><td>14</td><td>39</td><td>PCSEL</td></tr><tr><td>GND</td><td>15</td><td>40</td><td>NC</td></tr><tr><td>GND</td><td>16</td><td>41</td><td>BRSTDRVJ</td></tr><tr><td>GND</td><td>17</td><td>42</td><td>SDIORDY</td></tr><tr><td>DA2</td><td>18</td><td>43</td><td>NC</td></tr><tr><td>DA1</td><td>19</td><td>44</td><td>SDACKJ</td></tr><tr><td>DA0</td><td>20</td><td>45</td><td>IDEACTJ</td></tr><tr><td>DD0</td><td>21</td><td>46</td><td>DIAG</td></tr><tr><td>DD1</td><td>22</td><td>47</td><td>DD8</td></tr><tr><td>DD2</td><td>23</td><td>48</td><td>DD9</td></tr><tr><td>IOIS16J</td><td>24</td><td>49</td><td>DD10</td></tr><tr><td>GND</td><td>25</td><td>50</td><td>GND</td></tr></table>

![Technical line drawing of a mechanical assembly with no visible text or symbols](.cpci-6880-50-15066-1020-202-en/281e307b686a0bcfddcff9ec34bece6b93f55de27575595d6d7d22b92744324d.jpg)

![1\n26\n25\n50](.cpci-6880-50-15066-1020-202-en/e29b35755c488b4c80af69417210600376357ffa5418f07fd6c134eaabef4341.jpg)

Table 4-19: CompactFlash Connector Pin Definition

DB-6880CF, DB-6920CF/SAT Connector (CN10, CN6-R)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>GND</td><td>1</td><td>2</td><td>GND</td></tr><tr><td>GND</td><td>3</td><td>4</td><td>GND</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>GND</td><td>7</td><td>8</td><td>GND</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>GND</td><td>13</td><td>14</td><td>GND</td></tr><tr><td>GND</td><td>15</td><td>16</td><td>GND</td></tr><tr><td>GND</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>GND</td><td>19</td><td>20</td><td>GND</td></tr><tr><td>GND</td><td>21</td><td>22</td><td>GND</td></tr><tr><td>GND</td><td>23</td><td>24</td><td>GND</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>GND</td></tr><tr><td>GND</td><td>27</td><td>28</td><td>GND</td></tr><tr><td>GND</td><td>29</td><td>30</td><td>GND</td></tr><tr><td>P3V3</td><td>31</td><td>32</td><td>P5V</td></tr><tr><td>P3V3</td><td>33</td><td>34</td><td>P5V</td></tr><tr><td>P3V3</td><td>35</td><td>36</td><td>P5V</td></tr><tr><td>P3V3</td><td>37</td><td>38</td><td>P5V</td></tr><tr><td>P1V8</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>P1V8</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>P1V8</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>GND</td><td>45</td><td>46</td><td>GND</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>SATA-TXN0</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>SATA-TXP0</td></tr><tr><td>SATA-RXN0</td><td>51</td><td>52</td><td>GND</td></tr><tr><td>SATA-RXP0</td><td>53</td><td>54</td><td>GND</td></tr><tr><td>GND</td><td>55</td><td>56</td><td>RESET#</td></tr><tr><td>GND</td><td>57</td><td>58</td><td>GND</td></tr><tr><td>GND</td><td>59</td><td>60</td><td>GND</td></tr></table>

![1\n2\n59\n60](.cpci-6880-50-15066-1020-202-en/7a43ca4db9ce84d12e55434cf975c41909d0c1bb08b39cd26946bd91f8bba148.jpg)

Table 4-20: DB-6880CF, DB-6920CF/SAT Connector Pin Definition

DB-R6000L2 Connector (CN14)

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>SATA-T1P</td><td>1</td><td>2</td><td>USB-P3</td></tr><tr><td>SATA-T1N</td><td>3</td><td>4</td><td>USB-N3</td></tr><tr><td>GND</td><td>5</td><td>6</td><td>GND</td></tr><tr><td>SATA-R1P</td><td>7</td><td>8</td><td>USB-OC3#</td></tr><tr><td>SATA-R1N</td><td>9</td><td>10</td><td>GND</td></tr><tr><td>GND</td><td>11</td><td>12</td><td>GND</td></tr><tr><td>GND</td><td>13</td><td>14</td><td>USB-P2</td></tr><tr><td>HAD_RST-L</td><td>15</td><td>16</td><td>USB-N2</td></tr><tr><td>HAD_SYNC</td><td>17</td><td>18</td><td>GND</td></tr><tr><td>HAD_SDOUT</td><td>19</td><td>20</td><td>USB-OC2#</td></tr><tr><td>HAD_BIT_CLK</td><td>21</td><td>22</td><td>GND</td></tr><tr><td>HAD_SDIN0</td><td>23</td><td>24</td><td>PS2-KBC</td></tr><tr><td>GND</td><td>25</td><td>26</td><td>PS2-KBD</td></tr><tr><td>HAD_SDIN1</td><td>27</td><td>28</td><td>PS2-MSD</td></tr><tr><td>HAD_SDIN2</td><td>29</td><td>30</td><td>PS2-MSC</td></tr><tr><td>HAD_SDIN3</td><td>31</td><td>32</td><td>GND</td></tr><tr><td>GND</td><td>33</td><td>34</td><td>RESET#</td></tr><tr><td>GND</td><td>35</td><td>36</td><td>GND</td></tr><tr><td>GND</td><td>37</td><td>38</td><td>GND</td></tr><tr><td>GND</td><td>39</td><td>40</td><td>GND</td></tr><tr><td>GND</td><td>41</td><td>42</td><td>GND</td></tr><tr><td>GND</td><td>43</td><td>44</td><td>GND</td></tr><tr><td>GND</td><td>45</td><td>46</td><td>GND</td></tr><tr><td>GND</td><td>47</td><td>48</td><td>GND</td></tr><tr><td>GND</td><td>49</td><td>50</td><td>GND</td></tr><tr><td>P5V</td><td>51</td><td>52</td><td>P1V8</td></tr><tr><td>P5V</td><td>53</td><td>54</td><td>P1V8</td></tr><tr><td>P5V</td><td>55</td><td>56</td><td>P1V8</td></tr><tr><td>P5V</td><td>57</td><td>58</td><td>NC</td></tr><tr><td>P5V</td><td>59</td><td>60</td><td>NC</td></tr><tr><td>GND</td><td>61</td><td>62</td><td>GND</td></tr></table>

![2\n1\n61\n62\n60\n59](.cpci-6880-50-15066-1020-202-en/a3b5c2c0d1c98f59a3b176b7ea025c9f1f1bbe482f645241385e86d27c444ed0.jpg)

Table 4-21: DB-R6000L2 Connector Pin Definition

CompactPCI J1 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK#</td><td>+5V</td><td>TMS#</td><td>NC</td><td>TDI#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>IRQA#</td><td>IRQB#</td><td>IRQC#</td><td>+5V</td><td>IRQD#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>+5V_IPMB</td><td>HEALTHY#</td><td>V(I/O)</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>NC</td><td>NC</td><td>RESET#</td><td>GND</td><td>GNT0#</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ0#</td><td>GND</td><td>+3.3V</td><td>CLK0</td><td>AD31</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD30</td><td>AD29</td><td>AD28</td><td>GND</td><td>AD27</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD26</td><td>GND</td><td>V(I/O)</td><td>AD25</td><td>AD24</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>CBE3#</td><td>IDSEL</td><td>AD23</td><td>GND</td><td>AD22</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD21</td><td>GND</td><td>+3.3V</td><td>AD20</td><td>AD19</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD18</td><td>AD17</td><td>AD16</td><td>GND</td><td>CBE2#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>BDSEL#</td><td>TRDY#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>PCIXCAP</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>CBE1#</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD15</td><td>AD14</td><td>GND</td><td>AD13</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD12</td><td>GND</td><td>VIO</td><td>AD11</td><td>AD10</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD9</td><td>AD8</td><td>M66EN</td><td>CBE0#</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD7</td><td>GND</td><td>+3.3V</td><td>AD6</td><td>AD5</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD4</td><td>AD3</td><td>+5V</td><td>AD2</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD1</td><td>+5V</td><td>V(I/O)</td><td>AD0</td><td>ACK64#</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr></table>

Table 4-22: CompactPCI J1 Connector Pin Definition

CompactPCI J2 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>SYSEN#</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>NC</td><td>CBE7#</td><td>GND</td><td>CBE6#</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>CBE5#</td><td>GND</td><td>V(I/O)</td><td>CBE4#</td><td>PAR64</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD63</td><td>AD62</td><td>AD61</td><td>GND</td><td>AD60</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD59</td><td>GND</td><td>V(I/O)</td><td>AD58</td><td>AD57</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD56</td><td>AD55</td><td>AD54</td><td>GND</td><td>AD53</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD52</td><td>GND</td><td>V(I/O)</td><td>AD51</td><td>AD50</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD49</td><td>AD48</td><td>AD47</td><td>GND</td><td>AD46</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD45</td><td>GND</td><td>V(I/O)</td><td>AD44</td><td>AD43</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD42</td><td>AD41</td><td>AD40</td><td>GND</td><td>AD39</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD38</td><td>GND</td><td>V(I/O)</td><td>AD37</td><td>AD36</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD35</td><td>AD34</td><td>AD33</td><td>GND</td><td>AD32</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>DEG#</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>GND</td><td>RSTBTN#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>GA4</td><td>GA3</td><td>GA2</td><td>GA1</td><td>GA0</td><td>GND</td></tr></table>

Table 4-23: CompactPCI J2 Connector Pin Definition

CompactPCI J3 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>HDA_RST#</td><td>HDA_SYNC</td><td>HDA_BIT_CLK</td><td>HDA_SDOUT</td><td>HDA_SDIN0</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>HDA_SDIN1</td><td>HDA_SDIN2</td><td>NC</td><td>HDA_DOCK_EN#</td><td>HDA_DOCK_RST#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>KBDATA</td><td>KBCLK</td><td>NC</td><td>MSDATA</td><td>MSCLK</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>SATA-TX4+</td><td>SATA-TX4-</td><td>GND</td><td>SATA-TX1+</td><td>SATA-TX1-</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>SATA-RX4+</td><td>SATA-RX4-</td><td>GND</td><td>SATA-RX1+</td><td>SATA-RX1-</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>COM4-TX</td><td>COM4-RX</td><td>COM3-DCD#</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>COM3-RX</td><td>COM3-TX</td><td>COM3-DTR#</td><td>COM3-DSR#</td><td>COM3-RTS#</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>COM3-CTS#</td><td>COM3-RI#</td><td>RGB-BLUE</td><td>RGB-RED</td><td>RGB-GREEN</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>USB-OC4#</td><td>RGB-DDCCLK</td><td>RGB-DDCDAT</td><td>RGB-HSYNC</td><td>RGB-VSYNC</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>USB-P4+</td><td>USB-P4-</td><td>GND</td><td>USB-P5+</td><td>USB-P5-</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>USB-P6+</td><td>USB-P6-</td><td>GND</td><td>USB-P7+</td><td>USB-P7-</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>USB-P8+</td><td>USB-P8-</td><td>GND</td><td>USB-P9+</td><td>USB-P9-</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>USB-OC5#</td><td>USB-OC6#</td><td>USB-OC7#</td><td>USB-OC8#</td><td>USB-OC9#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>LAN2_TXD1+</td><td>LAN2_TXD1-</td><td>GND</td><td>LAN2_TXD3+</td><td>LAN2_TXD3-</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>LAN2_TXD0+</td><td>LAN2_TXD0-</td><td>GND</td><td>LAN2_TXD2+</td><td>LAN2_TXD2-</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>LAN3_TXD1+</td><td>LAN3_TXD1-</td><td>GND</td><td>LAN3_TXD3+</td><td>LAN3_TXD3-</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>LAN3_TXD1+</td><td>LAN3_TXD0-</td><td>GND</td><td>LAN3_TXD2+</td><td>LAN3_TXD2-</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>P5V</td><td>P5V</td><td>P12V</td><td>P5V</td><td>P5V</td><td>GND</td></tr></table>

Table 4-24: CompactPCI J3 Connector Pin Definition

![High Definition audio\nKeyboard/Mouse\nSerial ATA\nSerial ports\nUSB ports\nEthernet ports\nRGB](.cpci-6880-50-15066-1020-202-en/189aa734f858f2467e9b78adb660c6f29d36ac32a3e6b64461394b5f85e4067e.jpg)

CompactPCI J4 Connector Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>PMC IO:61</td><td>PMC IO:63</td><td>NC</td><td>PMC IO:62</td><td>PMC IO:64</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PMC IO:57</td><td>PMC IO:59</td><td>NC</td><td>PMC IO:58</td><td>PMC IO:60</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>PMC IO:53</td><td>PMC IO:55</td><td>NC</td><td>PMC IO:54</td><td>PMC IO:56</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>PMC IO:49</td><td>PMC IO:51</td><td>NC</td><td>PMC IO:50</td><td>PMC IO:52</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>PMC IO:45</td><td>PMC IO:47</td><td>NC</td><td>PMC IO:46</td><td>PMC IO:48</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>PMC IO:41</td><td>PMC IO:43</td><td>NC</td><td>PMC IO:42</td><td>PMC IO:44</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>PMC IO:37</td><td>PMC IO:39</td><td>NC</td><td>PMC IO:38</td><td>PMC IO:40</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>PMC IO:33</td><td>PMC IO:35</td><td>NC</td><td>PMC IO:34</td><td>PMC IO:36</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>15</td><td>GND</td><td>PMC IO:29</td><td>PMC IO:31</td><td>NC</td><td>PMC IO:30</td><td>PMC IO:32</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PMC IO:25</td><td>PMC IO:27</td><td>NC</td><td>PMC IO:26</td><td>PMC IO:28</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PMC IO:21</td><td>PMC IO:23</td><td>NC</td><td>PMC IO:22</td><td>PMC IO:24</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PMC IO:17</td><td>PMC IO:19</td><td>NC</td><td>PMC IO:18</td><td>PMC IO:20</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PMC IO:13</td><td>PMC IO:15</td><td>NC</td><td>PMC IO:14</td><td>PMC IO:16</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>PMC IO:9</td><td>PMC IO:11</td><td>NC</td><td>PMC IO:10</td><td>PMC IO:12</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>PMC IO:5</td><td>PMC IO:7</td><td>NC</td><td>PMC IO:6</td><td>PMC IO:8</td><td>GND</td></tr><tr><td>25</td><td>GND</td><td>PMC IO:1</td><td>PMC IO:3</td><td>NC</td><td>PMC IO:2</td><td>PMC IO:4</td><td>GND</td></tr></table>

Table 4-25: CompactPCI J4 Connector Pin Definition

![The image displays a white document icon with a folded top-left corner. A large red checkmark is centered on the page, overlaid on faint horizontal gray lines that suggest text or a list.](.cpci-6880-50-15066-1020-202-en/9662bc302162cda51418d8ab54a4a9e35b5228ea437e06d0389e95843a56f41e.jpg)
NOTE:

J4 connector on cPCI-6880P only.

CompactPCI J5 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>GND</td><td>PCIE-TX+</td><td>PCIE-TX-</td><td>GND</td><td>PCIE-RX+</td><td>PCIE-RX-</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>PCIE-CLK+</td><td>PCIE-CLK-</td><td>GND</td><td>RESET#</td><td>NC</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>GND</td><td>GND</td><td>RTC</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>LVDS_DATA3-</td><td>LVDS_DATA3+</td><td>NC</td><td>LVDS_CLK</td><td>LVDS_DATA</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>GPIO1</td><td>GPIO2</td><td>GPIO3</td><td>GPIO4</td><td>GPIO5</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>LAN2_100#</td><td>LAN3_100#</td><td>NC</td><td>LAN3_1G#</td><td>LAN2_1G#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>SATA-TX5+</td><td>SATA-TX5-</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>NC</td><td>NC</td><td>RTM_ID0</td><td>SATA-RX5+</td><td>SATA-RX5-</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>MTR0#</td><td>INDEX#</td><td>RTM_ID1</td><td>NC</td><td>DENSEL#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>DIR#</td><td>NC</td><td>RTM_ID2</td><td>DRVA#</td><td>NC</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>TRK0#</td><td>WGATE#</td><td>DETECT#</td><td>WDATA#</td><td>STEP#</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>DSKCHG#</td><td>HDSEL#</td><td>NC</td><td>RDATA#</td><td>WRPORT#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>LVDS_DATA0-</td><td>LVDS_DATA0+</td><td>GND</td><td>LVDS_DATA1-</td><td>LVDS_DATA1+</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>LVDS_DATA2-</td><td>LVDS_DATA2+</td><td>GND</td><td>LVDS_CLK-</td><td>LVDS_CLD+</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>NC</td><td>LAN2_LINK_ACT#</td><td>+3.3V</td><td>LAN3_LINK_ACT#</td><td>+3.3V</td><td>GND</td></tr></table>

Table 4-26: CompactPCI J5 Connector Pin Definition

![PCI-Express x1\nGPIO\nSerial ATA\nFloppy\nEthernet port\nLVDS](.cpci-6880-50-15066-1020-202-en/e3efe78323e629911c5866adfa075be15b7f6e59bf4346e641608227dba8c3c4.jpg)

# 4.12 Switch and Jumper Settings

# Clear CMOS Switch (SW2)

Press the switch SW2 to clear the CMOS and reset the CMOS values to default.

![The image displays a simple diagram consisting of a small black rectangle on the left, followed by a red arrow pointing to the right, and then a larger black rectangle on the far right.](.cpci-6880-50-15066-1020-202-en/b100a774de6dc4cc46e21800b36d9a4f997dcf7eeb1ace465810000734ed5935.jpg)

# Mode Switch (SW3)

The Switch SW3 is a multi purpose switch that allows users to define the board operating mode. Four pins independently control the mode setting. All pins are set to OFF by default.

![ON\n1 2 3 4](.cpci-6880-50-15066-1020-202-en/ecc1e390cb8af36a4bd69fad716672e3ba7fcb2c829e098cc6e7aa47a9353204.jpg)

<table><tr><td>Pin#</td><td>Status</td><td>Description</td></tr><tr><td rowspan="2">1</td><td>OFF</td><td>When the system does not include a CMM (Chassis Management Module), set this pin to OFF to allow IPMI to run in &quot;without CMM mode&quot;.</td></tr><tr><td>ON</td><td>When the system includes a CMM, set this pin to ON to allow IPMI to run in &quot;with CMM mode&quot;.</td></tr><tr><td rowspan="2">2</td><td>OFF</td><td>The board is controlled by IPMI with boot-up/shutdown (recommended).</td></tr><tr><td>ON</td><td>The board is not controlled by IPMI with bootup/shutdown.</td></tr><tr><td rowspan="2">3</td><td>OFF</td><td>The cPCI-6880 cannot boot-up when installed in a peripheral slot when there is no host board in the system slot.</td></tr><tr><td>ON</td><td>The cPCI-6880 is able to boot-up when installed in a peripheral slot when there is no host board in the system slot.</td></tr><tr><td rowspan="2">4</td><td>OFF</td><td>Universal Mode: The cPCI-6880 in a peripheral slot has CompactPCI bus communication with the host board in the system slot. The cPCI-6880 can boot-up in a peripheral slot and be recognized by the host board in the system slot as a PCI device.</td></tr><tr><td>ON</td><td>Satellite Mode: The cPCI-6880 in a peripheral slot has no CompactPCI bus communication with the host board in the system slot. The cPCI-6880 behaves as a standalone blade in the peripheral slot.</td></tr></table>

Table 4-27: Mode Switch Settings

# COM1/Debug Switch (SWX1)

Switch SWX1 sets the RJ-45 serial port (CN6) as a standard RS-232 serial port or as an IPMI debugging port.

![ON\n1 2 3 4](.cpci-6880-50-15066-1020-202-en/e946c2368762e8aa7bb86d2cdadd9b70db9320f10232dc5b6227143df54b62ee.jpg)

<table><tr><td>Mode</td><td>1</td><td>2</td><td>3</td><td>4</td></tr><tr><td>RS-232 COM port (default)</td><td>ON</td><td>ON</td><td>OFF</td><td>OFF</td></tr><tr><td>IPMI debugging port</td><td>OFF</td><td>OFF</td><td>ON</td><td>ON</td></tr></table>

Table 4-28: COM1/Debug Switch Settings

# USB Flash Data Protection Switch (SWY1)

Switch SWY1 can be set to Write Protect Mode to protect the data stored on onboard USB NAND flash from inadvertent system writes or erases, and from viruses. The Write Protect Mode feature protects the full address space of the data stored on the flash media.

![The image features a black background with the word 'ON' in white text centered at the top. Below this, there are two vertical rectangular blocks side-by-side. The left block consists of a black upper section and a white lower section, while the right block consists of a white upper section and a black lower section. Underneath these blocks are the numbers '1' and '2' in white, centered beneath the left and right blocks respectively.](.cpci-6880-50-15066-1020-202-en/76308dd7a21de6294f40d4326009f424f6e0b98ca624ec5b82d4e654f2ff888d.jpg)

<table><tr><td>Mode</td><td>1</td><td>2</td></tr><tr><td>Data overwrite is allowed (default)</td><td>ON</td><td>OFF</td></tr><tr><td>Data overwrite is not allowed</td><td>ON</td><td>ON</td></tr></table>

Table 4-29: USB Flash Data Protection Switch Settings

# PICMG 2.16 Switches (SW1-R, SW2-R, SW3-R, SW4-R)

The cPCI-R6000(D) supports GbE3 and GbE4 on either the 2.16 backplane or via Rear I/O. The PICMG® 2.16 backplane and rear I/O cannot be accessed simultaneously. Switches SW1-R to SW4-R must be set to connect GbE3 and GbE4 to either the 2.16 backplane or to the RTM. The following table shows how to set the switches to enable GbE3 and GbE4 for either the 2.16 backplane or the RTM. All switches are set to ON by default.

![1\n2\n3\n4\nON](.cpci-6880-50-15066-1020-202-en/2b918845837cf871b85af611e09563238a1419f75e8802597a4b549d1cdd1c5e.jpg)

SW1-R

![1\n2\n3\n4\nON](.cpci-6880-50-15066-1020-202-en/17edc9b1444610d554252002beb87f2c922646de64180b3bee3c48bc1ab4bc90.jpg)

SW2-R

![1\n2\n3\n4\nON](.cpci-6880-50-15066-1020-202-en/5f0a92c6b3eaf822194a11ea992be11121d4f49ad05655cdb4948e56200c84d6.jpg)

SW3-R

![1\n2\n3\n4\nON](.cpci-6880-50-15066-1020-202-en/68781a4a50c84f4b50e0425f06e101589a25f1bb5cfa6065b036bededd6f49c0.jpg)

SW4-R

<table><tr><td>Connect GbE3/4 to</td><td>GbE3(SW1-R, SW2-R)</td><td>GbE4(SW3-R, SW4-R)</td></tr><tr><td>PICMG® 2.16 Backplane</td><td>All OFF</td><td>All OFF</td></tr><tr><td>Rear faceplate RJ-45 connectors (default)</td><td>All ON</td><td>All ON</td></tr></table>

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# 5 Getting Started

This chapter describes the installation of the following components to the cPCI-6880 and rear transition modules:

▶ Memory module
▶ 2.5" SATA hard drive
▶ CompactFlash card
▶ cPCI-6880 CPU module installation to chassis
▶ RTM installation to chassis

# 5.1 CPU and Heatsink

The cPCI-6880 Series comes with CPU and heatsink pre-installed. Uninstalling the heatsink is not recommended. If it is necessary to do so, please check that the thermal pad is not damaged before you re-install the heatsink to the board. Contact ADLINK to obtain the appropriate thermal pad for the cPCI-6880 or for any other assistance.

# 5.2 Memory Module Installation

The cPCI-6880 Series supports dual channel DDR2-667/800 memory without ECC. One channel is assigned to soldered onboard memory, and the other one channel is assigned to a 200-pin SO-DIMM socket. Contact your ADLINK sales representative for qualified SO-DIMM memory module information.

# Installing the Memory Module

Align the notch in the memory module with the key on the SO-DIMM slot. Press down on the module until it is properly seated in the socket.

![A5\nD7\nZG1002 8000PM\nNUR4 AMD320011BB\nINTeI\nIntel\nCatal\n90 H. K.\n1586\n1587\n1588\n1589\n1590\n1591\n1592\n1593\n1594\n1595\n1596\n1597\n1598\n1599\n1600\n1601\n1602\n1603\n1604\n1605\n1606\n1607\n1608\n1609\n1610\n1611\n1612\n1613\n1614\n1615\n1616\n1617\n1618\n1619\n1620\n1621\n1622\n1623\n1624\n1625\n1626\n1627\n1628\n1629\n1630\n1631\n1632\n1633\n1634\n1635\n1636\n1637\n1638\n1639\n1640\n1641\n1642\n1643\n1644\n1645\n1646\n1647\n1648\n1649\n1650\n1651\n1652\n1653\n1654\n1655\n1656\n1657\n1658\n1659\n1660\n1661\n1662\n1663\n1664\n1665\n1666\n1667\n1668\n1669\n1670\n1671\n1672\n1673\n1674\n1675\n1676\n1677\n1678\n1679\n1680\n1681\n1682\n1683\n1684\n1685\n1686\n1687\n1688\n1689\n1690\n1691\n1692\n1693\n1694\n1695\n1696\n1697\n1698\n1699\n1700](.cpci-6880-50-15066-1020-202-en/809e61458bc90c16d994daf1211a027b2aaa02fe041560b4b8ed5cf75a61ebb3.jpg)

# 5.3 Hard Drive Installation

The cPCI-6880 and cPCI-R6000D provide space to install a slim type 2.5" Serial-ATA hard drive.

# Installing a SATA Hard Drive - cPCI-6880

1. Attach the SATA hard drive to the HDD bracket provided by securing the four screws as shown below. Make sure to orient the hard drive with the connectors at the end of the bracket with the cut-out indicated by the red box.

![Interior view of an electronic circuit board with green PCB modules and mounting holes (no visible text or symbols)](.cpci-6880-50-15066-1020-202-en/2ac52f2f20cf4dd086729f6ce2e7721af275880f297ce0a1f8a46ab8b3a8ebb9.jpg)

![Close-up of a hard disk drive with red arrows pointing to mounting points and red circles highlighting features.](.cpci-6880-50-15066-1020-202-en/cac352777569dd0c08f2736cf31d6ec70a71a3028a07dfe89004bac40767948d.jpg)

2. Attach the DB-6920SAT adapter board to the hard drive connectors.

![Close-up of a hard disk drive with visible circuit board and battery (no readable text or symbols)](.cpci-6880-50-15066-1020-202-en/e948998e5f3f03cf237d69b002483e8a742ab0d6120a667e00682411505097b1.jpg)

3. Position the hard drive assembly on the cPCI-6880 so that the standoffs on the hard drive align with the screw holes on the board, and the connector on the DB-6920SAT adapter board is aligned with the board-to-board connector (CN10).
4. Press the DB-6920SAT adapter to the board-to-board connector until it is properly seated. Secure the adapter to the board with the two screws provided.

![The drive is recommended by Swaglar for the\ndistribution. For product information or technical\nsupport, please contact your system OEM.\nCAUTION: but returns back to put push on\nby power or means any bit at break.](.cpci-6880-50-15066-1020-202-en/1bf15d66653529fd9a6a2cfeb3da175dcde5a77119808f4efc012adf62e38edd.jpg)

5. Secure the hard drive with five screws from the board's solder side.

![Circuit board photo with red circles highlighting specific components and yellow connectors, showing circuitry and component labels like ERM1, RC 2, and Q219P-11.](.cpci-6880-50-15066-1020-202-en/1f7f212b4ce37cd8c9fa6ae315261eff1ef512e238669391c707dc79cd0f1522.jpg)

![The image shows a standard warning sign featuring a yellow triangle with a thick black border and a large black exclamation point in the center. Below the triangle is the word 'CAUTION:' printed in black capital letters.](.cpci-6880-50-15066-1020-202-en/de33ba4ca54e8e0d412ae09ec784aff5437981c1c2522cc6984bb77a5c93d850.jpg)

When removing the hard drive, be careful to grasp the adapter board and lift upwards in a vertical motion to disconnect it from the board-to-board connector. This will avoid damaging the adapter board and connectors.

# Installing a SATA Hard Drive - cPCI-R6000D RTM

1. Attach the DB-6920SAT adapter board to the hard drive connectors.

![©CEC\nG. M. L. 12\nM-300\n1000000000000000000000000000000000000000000000000000000000000000000000\nDATA\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\n12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\n12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 12.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: R: 23.5876/4.917\nR: R: 23.5876/4.917\nR: R: R: 23.5876/4.917\nR: R: R: R: 23.5876/4.917\nR: R: R: R: R: 23.5876/4.917\nR: R: R: R: R: 23.5876/4.917\nR: R: R: R: R: 23.5876/4.917\nR: R: R: R: R: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.917\nR: 23.5876/4.91](.cpci-6880-50-15066-1020-202-en/a6e44f4936619c68c41a93c9aa286efa2dbbd49eb842872f5c6768a53596c3ce.jpg)

2. Screw the hard drive to the bracket provided as shown.

![HITACHI\nTravelstar™\nSATA\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\nSATA\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n10.000-20.000\n11.16/24/25 18:39:37\n11.16/24/25 18:39:37\n11.16/24/25 18:39:37\n11.16/24/25 18:39:37\n11.16/24/25 18:39:37\n11.16/24/25 18.39:37\n11.16/24/25 18.39:37\n11.16/24/25 18.39:37\n11.16/24/25 18.39:37\n11.16/24/25 18.39:37\n11.16/24/35 18:39:37\n11.16/24/35 18:39:37\n11.16/24/35 18:39:37\n11.16/24/35 18:39:37\n11.16/24/35 18:39:37\n11.16/24/45 18:39:37\n11.16/24/45 18:39:37\n11.16/24/45 18:39:37\n11.16/24/45 18:39:37\n11.16/24/45 18:39:37\n11.15/24/45 18:39:37\n11.15/24/45 18:39:37\n11.15/24/45 18:39:37\n11.15/24/45 18:39:37\n11.15/24/45 18:39:37](.cpci-6880-50-15066-1020-202-en/6589235e804933bbe17bf0bbeb26e4fbad823c03d73304e2bea4226864877c4d.jpg)

3. Align the hard drive and bracket assembly with the board-to-board connector and standoffs and press down until it is properly seated. Secure the adapter and hard drive with 6x screws as shown.

![烧杯专用\n40530161\nThe power in the following by Target for 2008\nSignal processing and voltage regulation: 1.0V, 1.5V, 2.0V, 2.5V, 3.0V, 3.5V, 4.0V, 4.5V, 5.0V, 5.5V, 6.0V, 6.5V, 7.0V, 7.5V, 8.0V, 8.5V, 9.0V, 9.5V, 10.0V, 10.5V, 11.0V, 11.5V, 12.0V, 12.5V, 13.0V, 13.5V, 14.0V, 14.5V, 15.0V, 15.5V, 16.0V, 16.5V, 17.0V, 17.5V, 18.0V, 18.5V, 19.0V, 19.5V, 20.0V, 20.5V, 21.0V, 21.5V, 22.0V, 22.5V, 23.0V, 23.5V, 24.0V, 24.5V, 25.0V, 25.5V, 26.0V, 26.5V, 27.0V, 27.5V, 28.0V, 28.5V, 29.0V, 29.5V, 30.0V, 30.5V, 31.0V, 31.5V, 32.0V, 32.5V, 33.0V, 33.5V, 34.0V, 34.5V, 35.0V, 35.5V, 36.0V, 36.5V, 37.0V, 37.5V, 38.0V, 38.5V, 39.0V, 39.5V, 40.0V, 40.5V, 41.0V, 41.5V, 42.0V, 42.5V, 43.0V, 43.5V, 44.0V, 44.5V, 45.0V, 45.5V, 46.0V, 46.5v\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772M\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772N\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772P\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772S\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772R\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772C\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772U\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08772G\nT4A08769H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08699H\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU\nT4A08669KU](.cpci-6880-50-15066-1020-202-en/95b2294671adbcbb16bc698eba117b3592389006e69722e568ec3b7c355aeba9.jpg)

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Below the triangle, the text 'CAUTION:' appears in black capital letters.](.cpci-6880-50-15066-1020-202-en/4d2556a4c7fc0dc594c2c9331b2fb2bd9d13e2580a0bd21ae93cd97b5d10e02e.jpg)

When removing the hard drive, be careful to grasp the adapter board and lift upwards in a vertical motion to disconnect it from the board-to-board connector. This will avoid damaging the adapter board and connectors.

# 5.4 CompactFlash Card Installation

CompactFlash storage is required by some industrial applications for its resistance to vibration and convenient installation/replacement. The cPCI-6880 and cPCI-R6000D support a removable CompactFlash socket in the same space of 2.5" SATA HDD. Contact your sales representative to purchase a CompactFlash socket kit (DB-CF-SB for CPCI-6880, DB-CF-SA for cPCI-R6000D) that provides an internal CF card slot.

# Installing a CF card - cPCI-6880

Press the CF adapter (DB-6880CF) to the board-to-board connector (CN10) until it is properly seated. Insert the CF card into the CF slot on the adapter then install the card retaining bracket with the 2 screws provided to prevent the CF card from sliding out of the slot.

# Installing a CF card - cPCI-R6000D RTM

1. Remove the Layer 2 Adapter DB-R6000L2 by loosening the 4 screws as shown below.

![Close-up of a green printed circuit board with multiple ports and connectors, marked with red circles highlighting specific components (no readable text or symbols)](.cpci-6880-50-15066-1020-202-en/541716cc361e8f86a5e358d5e4a382b433b8f6ccb4da622cc5a7dfe9a989bc76.jpg)

2. Install the DB-6920CF adapter to the RTM using the board-to-board connector.
3. Secure the DB-6920CF to the RTM using two screws from the solder side of Layer 2 Adapter of RTM.

![Close-up of a green printed circuit board with soldering tools and component highlights (no readable text or symbols)](.cpci-6880-50-15066-1020-202-en/2f66508d57ab7cb8dceca49b122efa8e65f16a7daad77219484bf78e3d750e8e.jpg)

4. Reinstall the Layer 2 Adapter to the RTM.

5. Insert the CF card into the CF slot on the adapter, then replace the card retaining bracket to prevent the CF card from sliding out of the slot.

![Close-up of a green printed circuit board with a compact flash module and red annotations highlighting features (no readable text or symbols)](.cpci-6880-50-15066-1020-202-en/70ea449c0511f2b12e46b8778c4d7c61d6bd17b5cf5d43480347916c94f4c9c9.jpg)

# 5.5 Installing the cPCI-6880 SBC to the Chassis

The cPCI-6880 may be installed in a system or peripheral slot of a 6U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off.

2. Remove the blank face cover from the selected slot, if necessary.

3. Press down on the release catches of the cPCI-6880 ejector handles.

4. Remove the black plastic caps securing the mounting screws to the front panel.

5. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.

6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module front panel.

7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary.

# 5.6 Installing the cPCI-R6000 RTM to the Chassis

The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-6880 Series and related RTMs, make sure the RTM is the correct matching model.

![The image displays a white piece of paper with a folded top-right corner and horizontal lines running across it. A large, bold red checkmark is superimposed over the center of the document.](.cpci-6880-50-15066-1020-202-en/6abee4b4491b587aeceadf1c71d13593913d2fa93295fb69815f0c737ff5e308.jpg)
NOTE:

You must install the correct RTM to enable functions (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs.

# 6 Driver Installation

The cPCI-6880 drivers are available from the ADLINK All-In-One CD at X:\cPCI\cPCI-6880\, the cPCI-R6000(D) drivers are available at X:cPCI\cPCI-R6000(D)\, or from the ADLINK website (http://www.adlinktech.com). ADLINK provides validated drivers for chipset, graphics, LAN, and SATA/AHCI on Windows XP Professional, Windows XP x64 Edition and Windows Vista x64 Edition.

# 6.1 Driver Installation Procedure

The following describes the driver installation procedures for Windows XP.

1. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.

![The image features a simple icon of a document. It shows a white sheet of paper with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed over the center of the paper.](.cpci-6880-50-15066-1020-202-en/79928e5220638c47a34d1bc5e7e1f4f3c22aa4afdc2d357eca652ff92a4c5a4a.jpg)
NOTE:

In order to enable AHCI mode, you must pre-install the Intel® Matrix Storage Manager driver using the F6 installation method described in ...\SATA AHCI\readme.txt.

2. Install the chipset driver by extracting and running the program in ...\Chipset\Windows XP & Vista\ Intel\_INF\_Update\_Utility\_All\_WinOS\_v9.0.0.1008.zip.
3. Install the graphics driver and utilities by extracting and running the program in ...\Graphics\Windows XP Professional\Intel\_Graphics\_Adapter\_WinXP32\_v14.38.1.zip.
4. Install the LAN drivers by extracting and running the program in ...\LAN\Windows XP Professional\ Intel\_Network\_Adapter\_WinXP32\_Win2003\_v14.0.zip.
5. Install the Intel Matrix Storage Manager Utility by extracting and running the program in ...\SATA AHCI\Intel\_Matrix\_Storage\_Manager\_All\_WinOS\_v8.8.0.1009.zip.
6. Install the SCSI driver for RTM cPCI-R6000(D) if required. Refer to "SCSI Driver" on page 72.

7. Install the audio driver for RTM cPCI-R6000D by extracting and running the program in ...\\Audio\\Professional\\Realtek\_WDM\_Audio\_WinXP32\_Win2003\_v2.21.zip.

We recommend using the drivers provided on the ADLINK All-in-One CD or downloading them from the ADLINK website to ensure compatibility. Contact ADLINK to get support for VxWorks BSP.

# 6.2 SCSI Driver

The SCSI driver is available from the ADLINK All-In-One CD at X:cPCI\cPCI-R6000(D)\SCSI or from the ADLINK website (http://www.adlinktech.com). The installation procedure for Windows XP is described below. It is not necessary to install the SCSI driver on Windows 2003 Server and Vista as it has a built-in driver.

1. Click Start, right-click on My Computer, then select Properties from the drop-down menu.
2. Click on the Hardware tab, then click Device Manager.
3. Right-click on the SCSI Controller item, then click Properties from the drop-down menu.
4. From the General tab, click Reinstall Driver.
5. Select Yes, this time only and click Next when the Upgrade Device Driver Wizard window appears.
6. Select Install from a list on specific location [Advanced], then click Next.
7. Uncheck Search removable media [floppy, CD-ROM...], and check Include this location in the search:, then click Browse.
8. Select the xp\_x86 folder from this directory on the ADLINK All-In-One CD: ...X:\cPCI\cPCI-R6000(D)\SCSI.
9. Click OK, then click Next.
10. Click Continue Anyway to go on, and click Finish to complete the installation.

# 7 Utilities

# 7.1 Watchdog Timer

This section describes the operation of the cPCI-6880's watchdog timer (WDT). The primary function of the WDT is to monitor the cPCI-6880's operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

▶ enabling and disabling
▶ reloading timeout value

The cPCI-6880 custom WDT circuit is implemented using the internal IO of the ITE SuperIO IT8783 which is at address 2Eh of LPC. The basic functions of the WDT include:

▶ Starting the timer countdown
▶ Enabling or disabling WDT
▶ Enabling or disabling WDT countdown LED ON
▶ Reloading the timeout value to keep the watchdog from timing out
▶ Setting the range of the timeout period from 1 to 65535 seconds or minutes
▶ Sending a RESET signal to the system when the watchdog times out

# Using the Watchdog in an Application

The following section describes using the WDT functions in an application. The WDT reset function is explained in the previous section. This can be controlled through the registers in the cPCI-6880's SuperIO.

An application using the reset feature enables the watchdog function, sets the count-down period, and reloads the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after its counter reaches zero.

For a detailed programming sample, refer to the sample code provided on the ADLINK All-In-One CD. You can find it in the following directory: X:\cPCI\cPCI-6880\WDT.

# Sample Code

The sample program written in C shown below offers an interactive way to test the Watchdog Timer under DOS.

```c
#include&lt;stdio.h&gt;
#include&lt;dos.h&gt;

#define IT8783_ID1 0x87
#define IT8783_ID2 0x83

static unsigned int IT8783_ioPort = 0x2e;

//Check index port
void Enter_IT8783_Config(unsigned int flag)
{
    if(flag) IT8783_ioPort = 0x4e;

    switch(IT8783_ioPort)
    {
    case 0x2E: //Address port = 0x2E, enter keys = 0x87, 0x01, 0x55, 0x55
    outportb(0x2E, 0x87);
    outportb(0x2E, 0x01);
    outportb(0x2E, 0x55);
    outportb(0x2E, 0x55);
    break;
    case 0x4E: //Address port = 0x4E, enter keys = 0x87, 0x01, 0x55, 0xAA
    outportb(0x4E, 0x87);
    outportb(0x4E, 0x01);
    outportb(0x4E, 0x55);
    outportb(0x4E, 0xAA);
    break;
    default:
    break;
    }
}
```

```lisp
//Exit index port
void Exit_IT8783_Config(unsigned int flag)
{
    if(flag) IT8783_ioPort = 0x4e;

    outportb(IT8783_ioPort, 0x02);
    outportb(IT8783_ioPort+1, 0x02);
}

//Check chip
void Get_IT8783_ID(unsigned int &ID1, unsigned int &ID2)
{
    outportb(IT8783_ioPort, 0x20);
    ID1 = inportb(IT8783_ioPort+1);
    outportb(IT8783_ioPort, 0x21);
    ID2 = inportb(IT8783_ioPort+1);
}

//WDT and LED blink program
void IT8783_WDTRun(unsigned int count_value, unsigned int PLEDflag)
{
    unsigned long tempCount;
    unsigned int registerValue;

    outportb(IT8783_ioPort, 0x07);
    outportb(IT8783_ioPort+1, 0x07); // Device 7

    outportb(IT8783_ioPort, 0xf8);
    outportb(IT8783_ioPort+1, 0x00); // PLED mapping to nothing, disable PLED function

    if(PLEDflag == 1)
    {
    outportb(IT8783_ioPort, 0x27);
    registerValue = inportb(IT8783_ioPort + 1);
    registerValue |= 0x80;    // set Pin09 is GPIO function GP37
    outportb(IT8783_ioPort+1, registerValue);

    outportb(IT8783_ioPort, 0xc2);
    registerValue = inportb(IT8783_ioPort + 1);
```

```c
registerValue &= 0x7fb; // set GP37 is alternate function
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0xca);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0x80; // set GP42 is output
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0xf8);
outportb(IT8783_ioPort+1, 0x1f); // PLED mapping to GP37

outportb(IT8783_ioPort, 0xf9);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0x02;
registerValue &= 0xfb;
outportb(IT8783_ioPort+1, registerValue);
}
outportb(IT8783_ioPort, 0x71);
registerValue = importb(IT8783_ioPort + 1);
registerValue |= 0xD0; // set Mouse & Keyboard interrupt Enable
outportb(IT8783_ioPort+1, registerValue);

outportb(IT8783_ioPort, 0x73);
outportb(IT8783_ioPort+1, count_value); // set WDT count LSB
tempCount = tempCount >> 8;
outportb(IT8783_ioPort, 0x74);
outportb(IT8783_ioPort+1, count_value); // set WDT count MSB

if(count_value >= 60)
{
    outportb(IT8783_ioPort, 0x72);
    registerValue = importb(IT8783_ioPort+1);
    registerValue &= 0x7f;
    registerValue |= 0x40; // enable WDT output through KBRST
    outportb(IT8783_ioPort+1, registerValue); // set WDT count is minute
```

```c
tempCount = count_value / 60;
if((count_value%60) > 30)
    tempCount++;
if(tempCount > 65535)
    tempCount = 65535;
printf("WDT timeout in %d minutes.\n", tempCount);
}
else
{
    outportb(IT8783_ioPort, 0x72);
    registerValue = inportb(IT8783_ioPort+1);
    registerValue |= 0x80;

    tempCount = count_value;
    if(tempCount != 0)
    {
    printf("WDT timeout in %d seconds.\n", tempCount);
    registerValue |= 0x40; //Enable WDT output through KBRST
    }
    else
    {
    printf("WDT is Disabled.\n");
    registerValue &= 0xbf; //Disable WDT output through KBRST
    }

    outportb(IT8783_ioPort+1, registerValue); // set WDT count is second
}
```

# 7.2 Preboot Execution Environment (PXE)

The cPCI-6880 series supports the Intel® Preboot Execution Environment (PXE) that is capable of booting up or executing an OS installation through an Ethernet ports. To use PXE, there must be a DHCP server on the network with one or more servers running PXE and MTFTP services. It could be a Windows® 2003 server running DHCP, PXE, and MTFTP services or a dedicated DHCP server with one or more additional servers running PXE and MTFTP services.

To build a network environment with PXE support:

1. Setup a DHCP server with PXE tag configuration
2. Install the PXE and MTFTP services
3. Make a boot image file on the PXE server (i.e. the boot server)
4. Enable the PXE boot function on the client computer

# 8 BIOS Setup Utility

The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt; Press DEL to run Setup &gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus.

![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST3B410A 007A](.cpci-6880-50-15066-1020-202-en/ff2b063001a49ee471cee899d8e80fb8faa5524225d0de049ea078d3dff02c4f.jpg)

Note: In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="6">System Overview</td><td rowspan="5">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.</td></tr><tr><td colspan="6">AMIBIOS</td></tr><tr><td colspan="6">Version :08.00.15Build Date:05/26/09ID:C6880T25</td></tr><tr><td colspan="6">Processor</td></tr><tr><td colspan="6">Speed :255MHzCount :255</td></tr><tr><td colspan="6">System MemorySize :477MB</td><td rowspan="2">← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">System Time System Date [17:04:44][Tue 01/01/2002]</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

These keys include &lt;F1&gt;, &lt;F10&gt;, &lt;Enter&gt;, &lt;ESC&gt;, &lt;Arrow&gt; keys, and so on.

![Based on the provided image, here is the accurate description of the flowchart blocks and their connections:\n\n**Labeled Blocks:**\n*   BIOS Setup Utility\n*   Screens\n*   Left and Right Keys to Select a Setup Screen\n*   Screen 1\n*   Screen 2\n*   Screen 3\n*   Screen 4\n*   Screen 5\n*   Items\n*   Tab Key to Select Fields\n*   (±) (Three squares containing the plus-minus symbol, arranged in a top row)\n*   ± To Change Field Values\n*   Fields\n*   (±) (Three squares containing the plus-minus symbol, arranged in a bottom row)\n*   Up and Down Keys to Select a Setup Item\n\n**Connections:**\n*   **BIOS Setup Utility** connects via a downward arrow to **Screens**.\n*   **Left and Right Keys to Select a Setup Screen** connects via a dotted arrow to **Screen 1**.\n*   **Screen 1** connects to **Screen 2**, which connects to **Screen 3**, **Screen 4**, and **Screen 5** in a linear sequence using double-headed arrows.\n*   A downward arrow connects the **Screens** row (visually aligned with Screen 3) to **Items**.\n*   **Tab Key to Select Fields** connects via a dotted arrow to the first **(±)** square in the **Items** row.\n*   The three **(±)** squares in the **Items** row are connected horizontally by double-headed arrows.\n*   **± To Change Field Values** connects via a dotted arrow to the third **(±)** square.\n*   Vertical arrows (one pointing down, one pointing up) connect the top row of **(±)** squares to the bottom row of **(±)** squares.\n*   **Fields** is connected via a bracket to the bottom row of **(±)** squares.\n*   **Up and Down Keys to Select a Setup Item** connects via a dotted arrow to the vertical arrows between the rows.](.cpci-6880-50-15066-1020-202-en/1eb0dc49140b0fce62cefd469482057ca78bb8de7b844008aaac6efba58d89d7.jpg)

Note: There is a hot key legend located in the right frame on most setup screens.

The &lt; F8 &gt; key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the &lt; F8 &gt; key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings.

# Hotkey Descriptions

F1 The &lt; F1 &gt; key allows you to display the General Help screen.

Press the &lt; F1 &gt; key to open the General Help screen.

<table><tr><td colspan="4">General Help</td></tr><tr><td>←→</td><td>Select Screen</td><td>↓↑</td><td>Select Item</td></tr><tr><td>+-</td><td>Change Screen</td><td>Enter</td><td>Go to Sub Screen</td></tr><tr><td>PGDN</td><td>Next Page</td><td>PGUP</td><td>Previous Page</td></tr><tr><td>Home</td><td>Go to Top of the Screen</td><td>End</td><td>Go to Bottom of Screen</td></tr><tr><td>F2/F3</td><td>Change Colors</td><td>F7</td><td>Discard Changes</td></tr><tr><td>F8</td><td>Load Failsafe Defaults</td><td>F9</td><td>Load Optimal Defaults</td></tr><tr><td>F10</td><td>Save and Exit</td><td>ESC</td><td>Exit</td></tr><tr><td colspan="4">[Ok]</td></tr></table>

F10 The &lt; F10 &gt; key allows you to save any changes you have made and exit Setup. Press the &lt; F10 &gt; key to save your changes. The following screen will appear:

<table><tr><td colspan="2">Save configuration changes and exit now?</td></tr><tr><td>[Ok]</td><td>[Cancel]</td></tr></table>

Press the &lt;Enter&gt; key to save the configuration and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

ESC The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. The following screen will appear:

<table><tr><td colspan="2">Discard changes and exit setup now?</td></tr><tr><td>[Ok]</td><td>[Cancel]</td></tr></table>

Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

Enter The &lt; Enter &gt; key allows you to display or change the setup option listed for a particular setup item. The &lt; Enter &gt; key can also allow you to display the setup sub-screens.

# 8.2 Main Setup

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">System Overview</td><td rowspan="5" colspan="2">Use [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.</td></tr><tr><td colspan="5">AMIBIOS</td></tr><tr><td colspan="5">Version :08.00.15Build Date:05/26/09ID:C6880T25</td></tr><tr><td colspan="5">Processor</td></tr><tr><td colspan="5">Speed :255MHzCount :255</td></tr><tr><td colspan="5">System MemorySize :477MB</td><td rowspan="2" colspan="2">← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="5">System Time [17:04:44]System Date [Tue 01/01/2002]</td></tr></table>

# System Time/System Date

Use this option to change the system time and date. Highlight System Time or System Date using the &lt;Arrow&gt; keys. Enter new values using the keyboard. Press the &lt;Tab&gt; key or the &lt;Arrow&gt; keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

Note: The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00.

# 8.3 Advanced BIOS Setup

Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Advanced BIOS Setup screen is shown below.

The sub menus are described on the following pages.

<table><tr><td colspan="2">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td>CPU ConfigurationIDE ConfigurationSuperIO ConfigurationHardware Health ConfigurationRemote Access ConfigurationUSB Configuration</td><td>Configure CPU.Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# CPU Configuration

You can use this screen to select options for the CPU Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.

# BIOS SETUP UTILITY

# Advanced

# Configure advanced CPU settings

Module Version:3F.11

Manufacturer:Intel

Frequency :255MHz

FSB Speed :1068MHz

Cache L1 :0 KB

Cache L2 :0 KB

Ratio Actual Value:10

Core Multi-Processing

Intel(R) SpeedStep(tm) tech

[Enabled]

[Enabled]

When disabled, disable one execution core of each CPU die.

← Select Screen

↑↓ Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# Core Multi-Processing

This item enables/disables multi-core processing functionality for multi-core processors (default: Enabled).

# Intel®Speedstep™ Tech

Intel SpeedStep technology allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production (default: Enabled)..

# IDE Configuration

You can use this screen to select options for the IDE Configuration Settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.

<table><tr><td colspan="3">BIOS SETUP UTILITY</td></tr><tr><td colspan="3">Advanced</td></tr><tr><td colspan="2">IDE Configuration</td><td>Options</td></tr><tr><td>SATA#1 ConfigurationConfigure SATA#1 asSATA#2 Configuration</td><td>[Compatible][IDE][Enhanced]</td><td>DisabledCompatibleEnhanced</td></tr><tr><td>Primary IDE MasterPrimary IDE SlaveSecondary IDE MasterSecondary IDE SlaveThird IDE MasterFourth IDE Master</td><td>: [Not Detected]: [Not Detected]: [Not Detected]: [Not Detected]: [Not Detected]</td><td>Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# SATA#1 Configuration

This item specifies whether the SATA#1 is initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced (default: Compatible).

# Configure SATA#1 as

This item specifies whether the SATA#1 support IDEs or AHCI operation. The settings are IDE and AHCI (default: IDE).

# SATA#2 Configuration

This item specifies whether the SATA#2 is initialized in Compatible or Enhanced mode of operation. The settings are Disabled, Compatible and Enhanced (default: Enhanced).

# Super IO Configuration

You can use this screen to select options for the Super IO settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="3">Advanced</td></tr><tr><td>OnBoard Floppy Controller</td><td>[Enabled]</td><td rowspan="10">Allows BIOS to Enable or Disable Floppy Controller.</td></tr><tr><td>Floppy A</td><td>[1.44 MB 3 $\frac{1}{2}$ &quot;]</td></tr><tr><td>Serial Port1 Address</td><td>[3F8]</td></tr><tr><td>Serial Port1 IRQ</td><td>[4]</td></tr><tr><td>Serial Port2 Address</td><td>[2F8]</td></tr><tr><td>Serial Port2 IRQ</td><td>[10]</td></tr><tr><td>Serial Port3 Address</td><td>[3E8]</td></tr><tr><td>Serial Port3 IRQ</td><td>[3]</td></tr><tr><td>Serial Port4 Address</td><td>[2E8]</td></tr><tr><td>Serial Port4 IRQ</td><td>[11]</td></tr><tr><td></td><td></td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# Onboard Floppy Controller

Options: Disabled, Enabled

# Floppy Drive A

You can use this screen to specify options for the floppy drive settings. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

Options: Disabled, 360 KB 5 $\frac{1}{4}$ ", 1.2 MB 5 $\frac{1}{4}$ ", 720 KB 3 $\frac{1}{2}$ ", 1.44 MB 3 $\frac{1}{2}$ ", 2.88 MB 3 $\frac{1}{2}$ ".

# Serial Port1/2/3/4 Address/IRQ

Select an address and a corresponding interrupt for serial ports 1-4.

Address Options: 3F8, 3E8, 2F8, 2E8.

IRQ Options: 3, 4, 10, 11

# Hardware Health Configuration

This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. The options are Enabled and Disabled.

<table><tr><td colspan="3">BIOS SETUP UTILITY</td></tr><tr><td colspan="3">Advanced</td></tr><tr><td colspan="2">Hardware Health Configuration</td><td rowspan="2">Enables HardwareHealth MonitoringDevice.</td></tr><tr><td>H/W Health Function</td><td>[Enabled]</td></tr><tr><td>Ssystem Temperature</td><td>:30°C/86°F</td><td></td></tr><tr><td>CPU Temperature</td><td>:61°C/141°F</td><td></td></tr><tr><td>CPU Core</td><td>:1.088 U</td><td></td></tr><tr><td>1.05V</td><td>:1.024 U</td><td></td></tr><tr><td>3.3V</td><td>:3.120 U</td><td></td></tr><tr><td>1.8V</td><td>:1.840 U</td><td></td></tr><tr><td>5V</td><td>:4.784 U</td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td>UBAT</td><td>:3.008 U</td><td></td></tr></table>

# Remote Access Configuration

Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td colspan="2">Configure Remote Access type and parameters</td></tr><tr><td>Remote Access</td><td>[Enabled]</td></tr><tr><td>Serial port number</td><td>[COM1]</td></tr><tr><td>Base Address, IRQ</td><td>[3F8h, 4]</td></tr><tr><td>Serial Port Mode</td><td>[115200 8,n,1]</td></tr><tr><td>Flow Control</td><td>[None]</td></tr><tr><td>Redirection After BIOS POST</td><td>[Always]</td></tr><tr><td>Terminal Type</td><td>[ANSI]</td></tr><tr><td>UT-UTF8 Combo Key Support</td><td>[Enabled]</td></tr><tr><td>Sredir Memory Display Delay</td><td>[No Delay]</td></tr><tr><td></td><td></td></tr></table>

# Remote Access

Select this option to Enable or Disable the BIOS remote access feature.

![The image shows a white document icon with a folded top-right corner and faint horizontal lines. A large, bold red checkmark is superimposed over the left side of the document.](.cpci-6880-50-15066-1020-202-en/69715ccd4697a6dd8fb8d8f43a8ec31d293041b3cae9203979a50effbeeabcc4.jpg)
NOTE:

Enabling Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot.

# Serial Port Number

Select the serial port you want to use for the remote access interface. You can set the value for this option to COM1 or COM2.

![The image displays a graphic icon featuring a white sheet of paper with horizontal grey lines and a folded top-right corner. Superimposed over the paper is a large, bold red checkmark that curves upwards from the bottom left to the top right.](.cpci-6880-50-15066-1020-202-en/1a262a144106dc58e387d96007326a1cc5ee605999283fc893650a99b9fbdb2f.jpg)
NOTE:

If you have changed the resource assignment of the serial ports in Advanced> SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the Remote Access options.

# Serial Port Mode

Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1.

# Flow Control

Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software.

# Redirection After BIOS POST

This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always.

▶ Disabled: Set this value to turn off the redirection after POST
▶ Boot Loader: Set this value to allow the redirection to be active during POST and Boot Loader.
▶ Always: Set this value to allow the redirection to be always active.

# Terminal Type

This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8.

# VT-UTF8 Combo Key Support

This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled and Disabled.

# Sredir Memory Display Delay

This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec.

# USB Configuration

You can use this screen to select options for the USB Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;+&gt; and &lt;-&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY Advanced</td></tr><tr><td>USB Configuration</td><td>Options</td></tr><tr><td>Module Version - 2.24.5-13.4</td><td>Disabled</td></tr><tr><td>USB Devices Enabled :</td><td></td></tr><tr><td>1 Keyboard, 1 Mouse, 3 Drives</td><td>2 USB Ports</td></tr><tr><td></td><td>4 USB Ports</td></tr><tr><td>USB Functions [10 USB Ports]</td><td>6 USB Ports</td></tr><tr><td>USB 2.0 Controller [Enabled]</td><td>8 USB Ports</td></tr><tr><td>USB 2.0 Controller Mode [HiSpeed]</td><td>10 USB Ports</td></tr><tr><td>►USB Mass Storage Device Configuration</td><td>Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# USB Functions

Set this value to allow the system to Disable, Enable, and select a set number of onboard USB ports.

# USB 2.0 Controller

If USB Functions is set to Disabled, this option will have no effect. Setting this option to Enabled will allow USB 2.0 functionality to all USB ports.

# USB 2.0 Controller Mode

The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps).

# USB Mass Storage Device Configuration

This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Advanced</td></tr><tr><td>USB Mass Storage Device ConfigurationUSB Mass Storage Reset Delay [20 Sec]Device #1 USB Flash DiskEmulation Type [Auto]</td><td>Number of secondsPOST waits for theUSB mass storagedevice after startunit command.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# 8.4 Advanced PCI/PnP Settings

Select the PCI/PnP tab from the setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Plug and Play BIOS Setup screen is shown below.

<table><tr><td colspan="6">Main Advanced PCIPnP Boot Security Chipset Exit</td></tr><tr><td>IRQ3</td><td></td><td>[Reserved]</td><td></td><td rowspan="3">Available: SpecifiedIRQ is available to beused by PCI/PnPdevices.</td><td></td></tr><tr><td>IRQ4</td><td></td><td>[Reserved]</td><td></td><td></td></tr><tr><td>IRQ5</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ7</td><td></td><td>[Available]</td><td></td><td rowspan="7">Reserved: SpecifiedIRQ is reserved foruse by Legacy ISAdevices.</td><td></td></tr><tr><td>IRQ9</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ10</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ11</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ14</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>IRQ15</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>DMA Channel 0</td><td></td><td>[Available]</td><td></td><td></td></tr><tr><td>DMA Channel 1</td><td></td><td>[Available]</td><td rowspan="5" colspan="3">← Select Screen↑↓ Select Item+ - Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td>DMA Channel 3</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 5</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 6</td><td></td><td>[Available]</td></tr><tr><td>DMA Channel 7</td><td></td><td>[Available]</td></tr></table>

v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.

# IRQ/DMA Channel

Set this value to allow the IRQ/DMA channel settings to be modified.

▶ Available: This setting allows the specified IRQ/DMA channel to be used by a PCI/PnP device.
▶ Reserved: This setting allows the specified IRQ/DMA channel to be used by a legacy ISA device.

# 8.5 Boot Settings

Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys.

The Boot Settings screen is shown below:

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Boot Settings</td><td rowspan="4">Configure Settings during System Boot.</td></tr><tr><td colspan="5">▶ Boot Settings Configuration</td></tr><tr><td colspan="5">▶ Boot Device Priority</td></tr><tr><td colspan="5">▶ Removable Drives</td></tr><tr><td colspan="5"></td><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Boot Settings Configuration

Use this screen to select options for the Boot Settings Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td colspan="2">Boot</td></tr><tr><td colspan="2">Boot Settings Configuration</td></tr><tr><td>Quick Boot</td><td>[Enabled]</td></tr><tr><td>Quiet Boot</td><td>[Disabled]</td></tr><tr><td>Bootup Num-Lock</td><td>[On]</td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr><tr><td></td><td>Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system.</td></tr><tr><td></td><td>← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="2">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Quick Boot

Enabling this setting will cause the BIOS Power-On Self Test routine to skip some of its tests during bootup for faster system boot.

# Quiet Boot

When this feature is enabled, the BIOS will display the OEM logo during the boot-up sequence, hiding normal POST messages. When it is disabled, the BIOS will display the normal POST messages, instead of the OEM logo.

# Bootup Num-Lock

This option sets the Num Lock status when the system is powered on. Setting it to On will turn on the Num Lock key when the system is booted up. Setting it to Off will not enable the Num Lock key on bootup.

# Boot Device Priority

The items allow you to set the sequence of boot devices where BIOS attempts to load the disk operating system. First press &lt;Enter&gt; to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press &lt;+&gt;, &lt;-&gt; or &lt;PageUp&gt;, &lt;PageDown&gt; key to move it up/down in the priority list.

# Boot Device Groups

The Boot devices are listed in groups by device type. First press &lt;Enter&gt; to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press &lt;+&gt;, &lt;-&gt; or &lt;PageUp&gt;, &lt;PageDown&gt; key to move it up/down in the priority list. Only the first device in each device group will be available for selection in the Boot Device Priority option.

# 8.6 Security Setup

<table><tr><td colspan="7">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset</td><td>Exit</td></tr><tr><td colspan="5">Security Settings</td><td rowspan="2" colspan="2">Install or Change the password.</td></tr><tr><td rowspan="2" colspan="5">Supervisor Password :Not InstalledUser Password :Not InstalledChange Supervisor PasswordChange User PasswordClear User Password</td></tr><tr><td colspan="2">← Select Screen↑↓ Select ItemEnter ChangeF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="7">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Password Support

# Two Levels of Password Protection

Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first.

The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password.

The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure.

# Remember the Password

Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM.

To access the sub menu for the following items, select the item and press &lt; Enter&gt;:

▶ Change Supervisor Password
▶ Change User Password
▶ Clear User Password

# Supervisor Password

Indicates whether a supervisor password has been set.

# User Password

Indicates whether a user password has been set.

# Change Supervisor Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the supervisor password.

# Change User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to change the user password.

# Clear User Password

Select this option and press &lt; Enter &gt; to access the sub menu. You can use the sub menu to clear the user password.

# Change Supervisor Password

Select Change Supervisor Password from the Security Setup menu and press &lt; Enter &gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# Change User Password

Select Change User Password from the Security Setup menu and press &lt;Enter&gt;.

Enter New Password:

Type the password and press &lt; Enter &gt;. The screen does not display the characters entered. Retype the password as prompted and press &lt; Enter &gt;. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes.

# 8.7 Chipset Setup

Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of the items in the left frame of the screen to go to the sub menu for that item. The Chipset BIOS Setup screen is shown below.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Advanced Chipset Settings</td><td rowspan="3">Configure North Bridge features.</td></tr><tr><td colspan="5">WARNING: Setting wrong values in below sections may cause system to malfunction.</td></tr><tr><td colspan="5">▶ North Bridge Configuration▶ South Bridge ConfigurationFront LAN ROM Init [Disabled]Rear LAN ROM Init [Disabled]CPCI-R6000 SCSI ROM Init [Disabled]</td></tr><tr><td colspan="5"></td><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# North Bridge Configuration

You can use this screen to select options for the North Bridge Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option.

<table><tr><td colspan="2">BIOS SETUP UTILITY</td></tr><tr><td></td><td>Chipset</td></tr><tr><td>North Bridge Chipset ConfigurationBoots Graphic Adapter Priority [PEG/PCI]Internal Graphics Mode Select [Enabled, 32MB]Boot Display Device [CRT + LVDS]Flat Panel Type [1024x768 ]</td><td>Select which graphics controller to use as the primary boot device.← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit</td></tr></table>

# Boot Graphic Adapter Priority

Select which graphics controller to use as the primary boot device.

▶ IGD: Built-in chipset graphic only
▶ PCI/IGD: Detect PCI graphics first, then built-in chipset graphics (PCI includes PCI slot and PCI Express x1/x4 slot, PCI will be first)
▶ PCI/PEG: Detect PCI graphics first, then PCI Express x16 graphics
▶ PEG/IGD: Detect PCI Express x16 graphics first, then built-in chipset graphics
▶ PEG/PCI: Detect PCI Express x16 graphics first, then PCI graphics, then built-in chipset graphics

# Internal Graphics Mode Select

Select the amount of system memory (32M/64M/128M) used by the internal graphics device.

# Boot Display Device

This item allows the user to configure the type of external display used.

▶ CRT: Only CRT display
▶ CRT+DVI: Both CRT and DVI display (default)
▶ CRT+LVDS: Both CRT and LVDS display

# Flat Panel Type

When LVDS is selected from Boot Display Device, this option allows the output resolution to be set for the LVDS device you want to use. Available resolutions: 640x480, 800x600, 1024x768, 1280x1024.

# South Bridge Configuration

You can use this screen to select options for the South Bridge Configuration. Use the up and down &lt;Arrow&gt; keys to select an item. Use the &lt;Plus&gt; and &lt;Minus&gt; keys to change the value of the selected option.

![Chipset\nHDA Controller (Enabled) Options\nEnabled\nDisabled\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.cpci-6880-50-15066-1020-202-en/d811c9d355b21d5c3617e5843fd480e91fac10d294ffc5ba0eb8ef0653d5360e.jpg)

# HDA Controller

Set this value to Enable/Disable the HDA Controller.

# 8.8 Exit Menu

Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the &lt;Arrow&gt; keys. The Exit BIOS Setup screen is shown below.

<table><tr><td colspan="6">BIOS SETUP UTILITY</td></tr><tr><td>Main</td><td>Advanced</td><td>PCIPnP</td><td>Boot</td><td>Security</td><td>Chipset Exit</td></tr><tr><td colspan="5">Exit Options</td><td>Exit system setup after saving the changes.</td></tr><tr><td rowspan="3" colspan="5">Save Changes and ExitDiscard Changes and ExitDiscard ChangesLoad Optimal DefaultsLoad Failsafe Defaults</td><td rowspan="2">F10 key can be used for this operation.</td></tr><tr></tr><tr><td>← Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit</td></tr><tr><td colspan="6">v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.</td></tr></table>

# Save Changes and Exit

When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect.

Save Configuration Changes and Exit Now?

[Ok] [Cancel]

appears in the window. Select Ok to save changes and exit.

# Discard Changes and Exit

Select this option to quit Setup without making any permanent changes to the system configuration.

Discard Changes and Exit Setup Now?

[Ok] [Cancel]

appears in the window. Select Ok to discard changes and exit.

# Discard Changes

Select Discard Changes from the Exit menu and press &lt; Enter &gt;.

Select Ok to discard changes.

# Load Optimal Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems.

Select Load Optimal Defaults from the Exit menu and press &lt;Enter&gt;.

Select Ok to load optimal defaults.

# Load Failsafe Defaults

Automatically sets all Setup options to a complete set of default settings when you select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the FailSafe Setup options if your computer is experiencing system configuration problems.

Select Load Fail-Safe Defaults from the Exit menu and press &lt;Enter&gt;.

Load FailSafe Defaults?

[Ok] [Cancel]

appears in the window. Select Ok to load FailSafe defaults.

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# 9 IPMI User Guide

# 9.1 Introduction

This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 1.5. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification.

# 9.2 Summary of Commands Supported by BMR-AVR-cPCI

The table below lists all the commands supported by the BMR-AVR-cPCI. The rightmost column indicates if the command is required by PICMG 3.0/ PICMG 2.9, or is optional.

<table><tr><td>Command</td><td>IPMI Spec</td><td>NetFn</td><td>CMD</td><td>IPM Controller Req (PICMG 2.9)</td></tr><tr><td colspan="5">IPM Device “Global” Commands</td></tr><tr><td>Get Device ID</td><td>17.1</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td>Cold Reset</td><td>17.2</td><td>App</td><td>02h</td><td>Optional</td></tr><tr><td>Warm Reset</td><td>17.3</td><td>App</td><td>03h</td><td>Optional</td></tr><tr><td>Get Self Test Results</td><td>17.4</td><td>App</td><td>04h</td><td>Mandatory</td></tr><tr><td>Get Device GUID</td><td>17.8</td><td>App</td><td>08h</td><td>Optional</td></tr><tr><td>Broadcast “Get Device ID”</td><td>17.9</td><td>App</td><td>01h</td><td>Mandatory</td></tr><tr><td colspan="5">IPMI Messaging Support Commands</td></tr><tr><td>Send Message</td><td>18.7</td><td>App</td><td>34h</td><td>Optional</td></tr><tr><td colspan="5">BMC Watchdog Timer</td></tr><tr><td>Reset Watchdog Timer</td><td>21.5</td><td>App</td><td>22h</td><td>Optional</td></tr><tr><td>Set Watchdog Timer</td><td>21.6</td><td>App</td><td>24h</td><td>Optional</td></tr><tr><td>Get Watchdog Timer</td><td>21.7</td><td>App</td><td>25h</td><td>Optional</td></tr><tr><td colspan="5">Event Commands</td></tr><tr><td>Set Event Receiver</td><td>23.1</td><td>S/E</td><td>00h</td><td>Optional</td></tr><tr><td>Get Event Receiver</td><td>23.2</td><td>S/E</td><td>01h</td><td>Optional</td></tr><tr><td>Platform Event (a.k.a. “Event Message”)</td><td>23.3</td><td>S/E</td><td>02h</td><td>Optional</td></tr><tr><td colspan="5">Sensor Device Commands</td></tr><tr><td>Get Device SDR Info</td><td>29.2</td><td>S/E</td><td>20h</td><td>Optional</td></tr><tr><td>Get Device SDR</td><td>29.3</td><td>S/E</td><td>21h</td><td>Optional</td></tr><tr><td>Reserve Device SDR Repository</td><td>29.4</td><td>S/E</td><td>22h</td><td>Optional</td></tr><tr><td>Set Sensor Hysteresis</td><td>29.6</td><td>S/E</td><td>24h</td><td>Optional</td></tr><tr><td>Get Sensor Hysteresis</td><td>29.7</td><td>S/E</td><td>25h</td><td>Optional</td></tr><tr><td>Set Sensor Threshold</td><td>29.8</td><td>S/E</td><td>26h</td><td>Optional</td></tr><tr><td>Get Sensor Threshold</td><td>29.9</td><td>S/E</td><td>27h</td><td>Optional</td></tr><tr><td>Set Sensor Event Enable</td><td>29.10</td><td>S/E</td><td>28h</td><td>Optional</td></tr><tr><td>Get Sensor Event Enable</td><td>29.11</td><td>S/E</td><td>29h</td><td>Optional</td></tr><tr><td>Get Sensor Event Status</td><td>29.13</td><td>S/E</td><td>2Bh</td><td>Optional</td></tr><tr><td>Get Sensor Reading</td><td>29.14</td><td>S/E</td><td>2Dh</td><td>Optional</td></tr><tr><td>Get Sensor Type</td><td>29.16</td><td>S/E</td><td>2Fh</td><td>Optional</td></tr><tr><td colspan="5">FRU Device Commands</td></tr><tr><td>Get FRU Inventory Area Info</td><td>28.1</td><td>Storage</td><td>10h</td><td>Optional</td></tr><tr><td>Read FRU Data</td><td>28.2</td><td>Storage</td><td>11h</td><td>Optional</td></tr><tr><td>Write FRU Data</td><td>28.3</td><td>Storage</td><td>12h</td><td>Optional</td></tr></table>

# 9.3 OEM Commands Summary Table

<table><tr><td>Command</td><td>NetFn Code</td><td>Cmd Code</td></tr><tr><td>OemShowRevision</td><td>OEM (C0h)</td><td>12h</td></tr><tr><td>OemRescanGaInput</td><td>OEM (C0h)</td><td>22h</td></tr><tr><td>OemTestFunction</td><td>OEM (C0h)</td><td>30h</td></tr><tr><td>OemSetBlueLEDLongBlinking</td><td>OEM (C0h)</td><td>31h</td></tr><tr><td>OemReportGeoAddress</td><td>OEM (C0h)</td><td>F0h</td></tr><tr><td>OemEnableSmbus</td><td>OEM (C0h)</td><td>F2h</td></tr><tr><td>OemDisableSmbus</td><td>OEM (C0h)</td><td>F3h</td></tr><tr><td>OemDispDebugVariable</td><td>OEM (C0h)</td><td>F4h</td></tr><tr><td>OemResetHost</td><td>OEM (C0h)</td><td>F5h</td></tr><tr><td>OemPowerOff</td><td>OEM (C0h)</td><td>F6h</td></tr><tr><td>OemPowerOn</td><td>OEM (C0h)</td><td>F7h</td></tr></table>

# OemShowRevision

This command is used to show the current information of the firmware including the firmware revision, the product ID, and additional features.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>12h</td><td>OEM defined command</td></tr><tr><td rowspan="11">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>A5h</td><td>Internal check byte. Always A5h</td></tr><tr><td>2</td><td>*Firmware Rev</td><td>‘V’ in ASCII code for verification</td></tr><tr><td>3</td><td>*Firmware Rev</td><td>Revision info high byte</td></tr><tr><td>4</td><td>*Firmware Rev</td><td>Revision info low byte</td></tr><tr><td>5</td><td>*Product ID</td><td>‘P’ in ASCII code for verification</td></tr><tr><td>6</td><td>*Product ID</td><td>Product info high byte</td></tr><tr><td>7</td><td>*Product ID</td><td>Product info low byte</td></tr><tr><td>8</td><td>*Special info</td><td>‘S’ in ASCII code for verification</td></tr><tr><td>9</td><td>*Special info</td><td>Addition info byte</td></tr><tr><td>10</td><td>5Ah</td><td>Internal check byte. Always 5Ah</td></tr></table>

# OemRescanGaInput

This command is used to rescan the geo-address input pins and reset the IPMB address according to the input value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>22h</td><td>OEM defined command</td></tr><tr><td rowspan="2">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>New IPMB address</td><td>New IPMB address value</td></tr></table>

# OemTestFunction

Internal test purposes only.

# OemSetBlueLEDLongBlinking

This command is used to enable or disable the slow blink of the blue Hot Swap LED when a voltage is detected to be over $\pm5\%$ out of range for five seconds (see Table 4-1 on page 26). This function is set to disabled by default.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="3">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>31h</td><td>OEM defined command</td></tr><tr><td>2</td><td>00h or 01h</td><td>00h: disable slow blink capability01h: enable slow blink capability</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemReportGeoAddress

This command can report the IPMB address, the GA pin input status, and the event forwarding control value.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F0h</td><td>OEM defined command</td></tr><tr><td rowspan="4">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>IPMB address</td><td>IPMB address value</td></tr><tr><td>2</td><td>GA value</td><td>GA pin input status</td></tr><tr><td>3</td><td>Control value</td><td>Current control value of event forwarding</td></tr></table>

# OemEnableSmbus

This command is used to turn on the I2C bus when it is off during boot up process. Usually BIOS will perform this command after booting in boards with ServerWorks chipset.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F2h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDisableSmbus

This command is used to shut down I2C bus access.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F3h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemDispDebugVariable

This command can report up to 5 interval values for debug purposes. For developers only.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F4h</td><td>OEM defined command</td></tr><tr><td rowspan="6">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>*Debug variable 1</td><td></td></tr><tr><td>2</td><td>*Debug variable 2</td><td></td></tr><tr><td>3</td><td>*Debug variable 3</td><td></td></tr><tr><td>4</td><td>*Debug variable 4</td><td></td></tr><tr><td>5</td><td>*Debug variable 5</td><td></td></tr></table>

# OemResetHost

This command is implemented to control the system's status if rebooting is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F5h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOff

This command is implemented to control the system's status if power-off is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F6h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# OemPowerOn

This command is implemented to control the system's status if power-on is required. Operators can control the system remotely.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>C0h</td><td>NetFn/LUN for OEM</td></tr><tr><td>1</td><td>F7h</td><td>OEM defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# 9.4 CompactPCI Address Map

Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.

<table><tr><td colspan="4">CompactPCI Peripheral Address Mapping</td></tr><tr><td>Geo. Addr.</td><td>IPMB Addr.</td><td>Geo. Addr.</td><td>IPMB Addr.</td></tr><tr><td>0</td><td>Disabled</td><td>16</td><td>D0h</td></tr><tr><td>1</td><td>B0h</td><td>17</td><td>D2h</td></tr><tr><td>2</td><td>B2h</td><td>18</td><td>D4h</td></tr><tr><td>3</td><td>B4h</td><td>19</td><td>D6h</td></tr><tr><td>4</td><td>B6h</td><td>20</td><td>D8h</td></tr><tr><td>5</td><td>B8h</td><td>21</td><td>DAh</td></tr><tr><td>6</td><td>Bah</td><td>22</td><td>DCh</td></tr><tr><td>7</td><td>BCh</td><td>23</td><td>DEh</td></tr><tr><td>8</td><td>BEh</td><td>24</td><td>E0h</td></tr><tr><td>9</td><td>Coh</td><td>25</td><td>E2h</td></tr><tr><td>10</td><td>C4h</td><td>26</td><td>E4h</td></tr><tr><td>11</td><td>C6h</td><td>27</td><td>E6h</td></tr><tr><td>12</td><td>C8h</td><td>28</td><td>E8h</td></tr><tr><td>13</td><td>CAh</td><td>29</td><td>EAh</td></tr><tr><td>14</td><td>CCh</td><td>30</td><td>ECh</td></tr><tr><td>15</td><td>CEh</td><td>31</td><td>Disabled</td></tr></table>

# 9.5 Communications with IPMC

Operating systems need to use a serial port to communicate with the IPMC. The resource setting of the serial port must be IO: 0x3E8 and IRQ: 3. The communication setting of the serial port must be BaudRate: 9600, DataBit: 8, ParityCheck: None, StopBit: 1, and FlowControl: None. In Windows XP, use "COM3" to communicate with the IPMC.

# 9.6 IPMI Sensors List

<table><tr><td>Sensor Number</td><td>Sensor name</td><td>Normal Reading</td><td>Remark</td></tr><tr><td>01h</td><td>BMC Watchdog</td><td></td><td></td></tr><tr><td>02h</td><td>3.3V</td><td>3.3 V</td><td></td></tr><tr><td>03h</td><td>5V</td><td>5 V</td><td></td></tr><tr><td>04h</td><td>12V</td><td>12 V</td><td></td></tr><tr><td>05h</td><td>1.5V</td><td>1.5 V</td><td></td></tr><tr><td>06h</td><td>CPU0 Temp</td><td>40°C</td><td></td></tr><tr><td>07h</td><td>CPU1 Temp</td><td>40°C</td><td></td></tr><tr><td>08h</td><td>SYSTEM Temp</td><td>25°C</td><td></td></tr><tr><td>09h</td><td>Power Good</td><td></td><td></td></tr><tr><td>0ah</td><td>SYS_PWROK</td><td></td><td></td></tr><tr><td>0bh</td><td>BIOS CHANGE</td><td></td><td></td></tr><tr><td>0ch</td><td>BIOS POST ERROR</td><td></td><td></td></tr></table>

# 9.7 Relevant Documents

<table><tr><td>Document Title</td><td>Revision</td><td>Source</td></tr><tr><td>Intelligent Platform Management Interface Specification v1.5</td><td>Document Revision 1.1 February 20, 2002</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr><tr><td>PICMG 2.9 D1.0 CompactPCI System Management Specification</td><td>January 21, 2000</td><td></td></tr><tr><td>Intelligent Platform Management Bus Communications Protocol Specification v0.9</td><td>Document Revision 0.15 June 24, 1997</td><td>Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm</td></tr></table>

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# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:
▷ Turn off power and unplug any power cords/cables.
▶ To avoid electrical shock and/or damage to equipment:
▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);
▶ Make sure to use recommended voltage and power source settings;
▶ Always install and operate equipment near an easily accessible electrical socket-outlet;
▷ Secure the power cord (do not place any object on/over the power cord);
▷ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,
▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image features a standard warning symbol consisting of a red triangle containing a white exclamation point. Directly beneath the triangle is the word 'WARNING!' printed in black, bold, capital letters.](.cpci-6880-50-15066-1020-202-en/bec8af98ce55b22a571bfda87f7889018711cd72511554b4631a079266b1d14d.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085)
Rm. 801, Power Creative E, No. 1, B/D
Shang Di East Rd., Beijing, 100085 China

Tel: +86-10-5885-8666

Fax: +86-10-5885-8625

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

Address: 深圳市南山区科技园南区高新南七道 数字技术园
A1 栋 2 楼 C 区 (518057)
2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7,
High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

Tel: +49-211-495-5552

Fax: +49-211-495-5557

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

神田 374 ビル 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 서울시 서초구 서초동 1506-25 한도 B/D 2 층

2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu,

Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross,

JP Nagar Phase I, Bangalore - 560078, India

Tel: +91-80-65605817

Fax: +91-80-22443548

Email: india@adlinktech.com
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