# cPCI-6920 Series Dual Quad-Core Intel® Xeon® Processors 6U Compact PCI Processor Blade with XMC Site User's Manual ![Back view of a computer motherboard with visible CPU socket, RAM slots, and drive bays (no text or labels)](.cpci-6920-50-15065-1020-202/3899c3059b093d5f9afddaf998059284b894422475b2a62ece3a61bed056e146.jpg) ![Interior view of a computer motherboard showing CPU socket, RAM slots, and drive bays (no text or labels visible)](.cpci-6920-50-15065-1020-202/748abaa488aaca2867fcc695395b1022bdfb376fb8773670e57e5477e707132b.jpg) Manual Rev.: 2.02 Revision Date: June 18, 2010 Part No: 50-15065-1020 ![Circular black-and-white recycling symbol with three chasing arrows forming a triangle (no text or symbols)](.cpci-6920-50-15065-1020-202/a5f9d4fccf4b72cccbe796cc3bf3aea89a008ee6e2c19cc88fb583bdea4055a2.jpg) Recycled Paper # Revision History
RevisionRelease DateDescription of Change(s)
2.002008/10/27Initial Release
2.012009/07/16Correct specifications (RAID support, RTM COM pinouts, SATA connector pinouts, J5 pinouts), BIOS corrections, COM port routing.
2.022010/06/18Update SATA RAID support, RTM support (cPCI-R6000), default CMOS battery; correct GbE, J1, J3 pin assignments; update IPMI User Guide.
# Preface # Copyright 2010 ADLINK Technology Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Using this Manual # Audience and Scope The cPCI-6920 User's Manual is intended for hardware technicians and systems operators with knowledge of installing, configuring and operating industrial grade computer systems. # Manual Organization This manual is organized as follows: Chapter 1, Introduction: Introduces the cPCI-6920, its features, block diagrams, and package contents. Chapter 2, Specifications: Presents detailed specification information. Chapter 3, Functional Description: Describes the cPCI-6920 main functions. Chapter 4, Board Interfaces: Describes the cPCI-6920 board interfaces. Chapter 5, Getting Started: Describes the installation of components to the cPCI-6920 and rear transition modules. Chapter 6, Driver Installation: Provides information on how to install the cPCI-6920 device drivers. Chapter 7, Utilities: Describes the utilities of the cPCI-6920 Series. Chapter 8, BIOS Setup: Describes basic navigation for the AMIBIOS®8 BIOS setup utility. Chapter 9, IPMI User Guide: Provides relevant information for the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI). Important Safety Instructions: Presents safety instructions all users must follow for the proper setup, installation and usage of equipment and/or software. Getting Service: Contact information for ADLINK's worldwide offices. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image displays a graphic of a white document with horizontal black lines, resembling a notepad or checklist. A large, red checkmark is prominently overlaid on the document, slanting upwards from left to right. The top-left corner of the paper is folded down.](.cpci-6920-50-15065-1020-202/c7f2b1d06e5cf7c9c21ec5077216121e0f19dcb74251fb2fb4a240e3a177de1c.jpg) NOTE: Additional information, aids, and tips that help users perform tasks. ![The image displays a yellow triangular warning sign with a black outline. Centered inside the triangle is a large black exclamation point. To the left of the sign is a black vertical line.](.cpci-6920-50-15065-1020-202/66d5569a15089813c9f2c730446c1707f0328bf5d2cc26c23eccc7004b007227.jpg) CAUTION: Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image displays a standard warning symbol consisting of a red triangle with a white exclamation point inside it, set against a white background.](.cpci-6920-50-15065-1020-202/26de4896cc260b3f2c5a8fd03de9b5266005a2a84de4826835d3dee3bba0f0c0.jpg) WARNING: Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. This page intentionally left blank. # Table of Contents # Revision History...... ii # Preface...... iii # List of Figures ...... xi # List of Tables...... xiii # 1 Introduction ...... 1 1.1 Overview.... 1 1.2 Features.... 2 1.3 Block Diagram 3 1.4 Product List.... 4 1.5 Package Contents 5 # 2 Specifications.... 7 2.1 cPCI-6920 SBC Specifications 7 2.2 cPCI-R6000 RTM Specifications 10 2.3 I/O Connectivity Table 11 2.4 Power Requirements 13 # 3 Functional Description 15 3.1 Processors.... 15 3.2 Chipset.... 18 3.3 Memory.... 19 3.4 ATI ES1000 Graphics Controller 19 3.5 PCI-E to PCI Bridge 20 3.6 PMC/XMC Site.... 20 3.7 Onboard USB Flash.... 20 3.8 Super I/O 21 3.9 Battery 21 # 4 Board Interfaces.... 23 4.1 cPCI-6920 SBC Board Layout 23 4.2 cPCI-6920 SBC Front Panel 24 4.3 cPCI-6920 SBC Assembly Layout 25 4.4 cPCI-6920D SBC Board Layout.... 26 4.5 cPCI-6920D SBC Front Panel 27 4.6 cPCI-R6000 RTM Board Layout 28 4.7 cPCI-R6000 RTM Front Panel 29 4.8 cPCI-R6000D RTM Board Layout 30 4.9 cPCI-R6000D RTM Front Panel 31 4.10 cPCI-R6000D RTM Assembly Layoutl 32 4.11 Connector Pin Assignments.... 33 4.12 Switch and Jumper Settings 52 # 5 Getting Started.... 55 5.1 CPU and Heatsink 55 5.2 Memory Module Installation 56 5.3 CompactFlash Card Installation.... 58 5.4 Hard Drive Installation.... 62 5.5 Installing the cPCI-6920 to the Chassis 67 5.6 RTM (cPCI-R6000) Installation 68 # 6 Driver Installation.... 69 6.1 Installing the VGA Driver.... 70 6.2 Installing the SCSI Driver.... 71 # 7 Utilities.... 73 7.1 Watchdog Timer.... 73 7.2 Preboot Execution Environment (PXE).... 78 # 8 BIOS Setup 79 8.1 Starting the BIOS.... 79 8.2 Main Setup.... 83 8.3 Advanced BIOS Setup 84 8.3.1 CPU Configuration....85 8.3.2 IDE Configuration 88 8.3.3 Floppy Configuration....89 8.3.4 Super IO Configuration 90 8.3.5 Hardware Health Configuration 92 8.3.6 USB Configuration....93 8.3.7 AHCI Configuration....96 8.3.8 Remote Access Configuration 97 8.4 Advanced PCI/PnP Settings 99 8.5 Boot Settings 101 8.5.1 Boot Settings Configuration.... 101 8.5.2 Boot Device Priority 103 8.5.3 Boot Device Groups.... 103 8.6 Security Setup 104 8.7 Chipset Setup 107 8.8 Exit Menu.... 109 # 9 IPMI User Guide.... 111 9.1 Introduction.... 111 9.2 Summary of Commands Supported by IPMC.... 111 9.3 OEM Commands Summary Table.... 113 9.4 CompactPCI Address Map 117 9.5 Communications with IPMC.... 117 9.6 IPMI Sensors List.... 118 9.7 Relevant Documents 119 # Important Safety Instructions.... 121 # Getting Service.... 123 This page intentionally left blank. # List of Figures Figure 1-1: cPCI-6920 Series Functional Block Diagram....3 Figure 4-1: cPCI-6920 Board Layout 23 Figure 4-2: cPCI-6920 Front Panel Layout 24 Figure 4-3: cPCI-6920 SBC Assembly Layout....25 Figure 4-4: cPCI-6920D Board Layout....26 Figure 4-5: cPCI-6920D Front Panel Layout....27 Figure 4-6: cPCI-R6000 RTM Board Layout....28 Figure 4-7: cPCI-R6000 RTM Front Panel....29 Figure 4-8: cPCI-R6000D RTM Board Layout 30 Figure 4-9: cPCI-R6000D RTM Front Panel 31 Figure 4-10: cPCI-R6000D RTM Assembly Layout .... 32 This page intentionally left blank. # List of Tables Table 4-1: cPCI-6920 Front Panel System LED Descriptions ..... 24 Table 4-2: USB Connector Pin Definition....33 Table 4-3: VGA Connector Pin Definition .... 33 Table 4-4: GbE Connector Pin Definitions....34 Table 4-5: CN7, CN8 Ethernet LED Status Definitions....34 Table 4-6: GbE LED CN20-R, CN21-R Status Definitions....34 Table 4-7: PS/2 Keyboard/Mouse Connector Pin Definition....35 Table 4-8: DB-15 Serial Port Connector Pin Definition....35 Table 4-9: Onboard Serial Port Connector Pin Definition ...... 36 Table 4-10: DVI-I Connector Pin Definition....36 Table 4-11: Serial ATA Connector Pin Definition....37 Table 4-12: Serial ATA Connector on DB-6920SAT Pin Definition... 37 Table 4-13: 68-pin SCSI Pin Definition 38 Table 4-14: Floppy Connector Pin Definition 39 Table 4-15: CompactFlash Connector Pin Definition....40 Table 4-16: DB-6920L2 Connector Pin Definition....42 Table 4-17: DB-6920CF/DB-6920SAT Connector Pin Definition..... 43 Table 4-18: PMC Connector Pin Definition....45 Table 4-19: XMC Connector Pin Definition....46 Table 4-20: DB-R6000L2 Connector Pin Definition 47 Table 4-21: CompactPCI J1 Connector Pin Definition....48 Table 4-22: CompactPCI J2 Connector Pin Definition....49 Table 4-23: CompactPCI J3 Connector Pin Definition....50 Table 4-24: CompactPCI J5 Connector Pin Definition....51 Table 4-25: Reset Switch (SW1) Settings....52 Table 4-26: Boot Device Switch (SW3) Settings....52 This page intentionally left blank. # 1 Introduction # 1.1 Overview The cPCI-6920 Series is a 6U CompactPCI single board computer in single slot (4HP) or dual slot (8HP) width form factor featuring server class chipset and low voltage Quad-Core/Dual-Core Intel® Xeon® processor(s) with high-performance 1066MHz front-side bus (FSB). The single slot version provides one CPU socket which can be equipped with one Quad-Core Intel Xeon (L5408) or one Dual-Core Intel Xeon (LV 5138) processor, and provides two SO-RDIMM sockets for up to 8GB memory capacity. The dual slot version provides two CPU sockets which can be equipped with two Quad-Core Intel Xeon (L5408) or two Dual-Core Intel Xeon (LV 5138) processors, and provides four SO-RDIMM sockets for up to 16GB memory capacity. The cPCI-6920 Series implements the server class Intel® 5100 Memory Controller Hub and ICH9R I/O Hub for optimal performance. The cPCI-6920 Series supports a 64bit/66MHz CompactPCI bus, one PMC site with 64-bit/66MHz PCI bus or PCI-Express x8 XMC, four PCI-Express® Gigabit Ethernet ports (two on front panel, two for PICMG 2.16), a CompactFlash socket and onboard 4GB USB NAND flash for solid-state storage, optional onboard 2.5" SATA HDD, and SCSI RAID 1 support via the Rear Transition Module (RTM). For flexibility of use, the cPCI-6920 Series can be installed in a standard CompactPCI system slot as system master, or peripheral slot as stand-alone server blade without CompactPCI bus communication. The cPCI-6920 Series is ideally suited for datacom, telecom and military applications. # 1.2 Features ▶ 6U CompactPCI SBC in 4HP or 8HP width form factor ▶ Single/Dual Quad-Core Intel® Xeon processor(s) 2.13GHz, 12MB L2 cache ▶ Front Side Bus 1066MHz ▶ Server class Intel® 5100 Memory Controller Hub and ICH9R I/O Hub ▶ Dual Channel DDR2 registered and ECC SDRAM at 667MHz ▶ Two/four SO-RDIMM sockets for maximum up to 16GB memory ▶ 64bit/66MHz CompactPCI Interface based on PCI specifications ▶ Supports operation in system slot as system master or in peripheral slot as stand-alone server blade without connectivity to CompactPCI bus ▶ One PMC site with 64-bit/66MHz PCI bus or PCI-Express x8 XMC ▶ Four PCI-Express® Gigabit Ethernet ports, two at front, two for PICMG2.16 ▶ One CompactFlash socket and onboard 4GB USB NAND flash for storage option ▶ Optional 2.5" SATA HDD onboard by DB-SATA adapter kit ▶ SCSI hardware RAID 1 support at RTM ▶ SATA software RAID 0/1/5/10 support # 1.3 Block Diagram ![**Labeled Blocks:**\n* Dual Channel DDR2-667\n* DDR2 SO-RDIMM (4 blocks)\n* Intel® Quad/Dual-Core Processor (2 blocks)\n* Intel® 5100 MCH\n* Intel® 82571EB (2 blocks)\n* PMC XMC.3\n* ATI ES1000\n* PCI-E to PCI Bridge (2 blocks)\n* Intel® ICH9R\n* CF / 2.5' HDD\n* BIOS\n* Flash\n* SIO W83627UHG\n* IPMI BMC\n* FRONT PANEL\n* J5, J3, J2, J1 (Right-side vertical headers)\n\n**Connections:**\n* FSB 1066 MHz\n* PCIE x4\n* GbE 1/2\n* GbE x2 (2.16)\n* PCIE x8\n* DMI\n* PCI 64b/66M\n* RGB\n* PCI 32b/33M\n* PCEx1\n* SATA0\n* SATA 1/2/3\n* USB 4/5/6/7\n* USB 0/1/2/3\n* SPI\n* USB10\n* LPC\n* COM 1\n* PS/2 KB/MS\n* IPMB\n* COM 3\n* PCI 64b/133M](.cpci-6920-50-15065-1020-202/e1102693684387bec628f92aaf5be5d903a041a7ad87b6d3ed09ba0c1c900ea4.jpg) Figure 1-1: cPCI-6920 Series Functional Block Diagram # 1.4 Product List Products included in the cPCI-6920 Series include: # SBC ▶ cPCI-6920: 4HP (single-slot) width 6U CompactPCI featuring single Dual or Quad-Core Intel® Xeon processor; 1GB, 2GB or 4GB memory by SO-RDIMM; 4GB USB NAND flash on board; removable CompactFlash socket (DB-6920CF), 2xUSB, 2xGbE, VGA ▶ cPCI-6920D: 8HP (dual-slot) width 6U CompactPCI featuring single/dual Dual or Quad-Core Intel® Xeon processor(s); 1GB, 2GB, 4GB, 8GB memory on SO-RDIMM; 4GB USB NAND flash onboard, removable CompactFlash socket (DB-6920CF), 2x USB, 2x GbE, VGA. The DB-6920L2 adapter provides a PMC/XMC site, 2x USB, COM, KB/MS # Rear Transition Module ▶ cPCI-R6000: 4HP width Rear Transition Module for CPCI-6920 SBCs with VGA, 2x COM, 3x USB, 2x GbE, SCSI, 2x SATA, Floppy ▶ cPCI-R6000D: 8HP width Rear Transition Module for CPCI-6920 SBCs with VGA, 2x COM, 3x USB, 2x GbE, SCSI, 2x SATA, Floppy. The DB-R6000L2 adapter is assembled to provide 2x USB, KB/MS, Mic-in, Line-out and removable SATA direct connector (DB-6920SAT) for 2.5" SATA HDD direct connection. # Adapter Kits DB-SATA: includes DB-6920SAT adapter board and screws for 2.5" SATA hard drive installation ▶ DB-CF-SA: includes DB-6920CF adapter board and screws for CompactFlash card # 1.5 Package Contents The cPCI-6920 is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the cPCI-6920 Series are non-standard configurations and may vary depending on customer requests. # CPU module ▶ cPCI-6920 Series CPU Module ▷ CPU, RAM specifications will differ depending on options selected ▶ Thermal module is assembled on the board DB-6920CF adapter board is assembled on the board ▶ Y-cable for PS/2 combo port (8HP version only) ▶ DB-SATA kit (DB-6920SAT adapter board, screws, standoffs) ▶ ADLINK All-in-One CD ▶ User's manual # Rear Transition Module ▶ The cPCI-R6000 series ▶ The DB-SATA kit (8HP version only) ▶ 2.5" HDD bracket (8HP version only) ▶ Y-cable for PS/2 combo port (8HP version only) ▶ DVI to VGA (DB-15) adapter ▶ Ultra-320 SCSI cable # Adapter Kits ▶ DB-CF-SA kit ▷ DB-6920CF adapter board ▶ Screw and standoff accessory pack ▷ CF card guide ![The image displays a graphic of a white sheet of paper with faint horizontal grey lines, resembling a document or form. Overlaid on the paper is a large, bold red checkmark (or tick mark) drawn diagonally from the bottom left to the top right.](.cpci-6920-50-15065-1020-202/0f6b9968438fe420b6eaf12ad851dd4a49aafca4664f99fd520730b9a23fa1b2.jpg) NOTE: The contents of non-standard cPCI-6920 configurations may vary depending on the customer's requirements. ![The image displays a yellow triangular warning sign with a thick black border. Centered inside the triangle is a large black exclamation point. A horizontal black line runs across the top edge of the sign.](.cpci-6920-50-15065-1020-202/8d4ab8e9e0006f3c651a815017c5265ceeea658a7748810d728f5f3a0044953b.jpg) CAUTION: This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components. # 2 Specifications # 2.1 cPCI-6920 SBC Specifications
CompactPCI®StandardsPICMG® 2.0 CompactPCI® Rev. 3.0PICMG® 2.1 Hot Swap Specification Rev.2.0PICMG® 2.9 System Management Bus Rev. 1.0PCIMG® 2.16 Packet Switching Backplane Rev.1.0
MechanicalStandard 6U CompactPCI®Board size: 233.35mm x 160mmSingle slot (4HP, 20.32mm); Dual slot (8HP, 40.64mm) widthCompactPCI® connectors with J1, J2, J3 and J5
ProcessorFC-LGA771 Quad-Core Intel® Xeon Processor L5408 2.13GHz in 45nm process technology, 12MB on die L2 cacheFC-LGA771 Dual-Core Intel® Xeon Processor LV 5138 2.13GHz in 65nm process technology, 4MB on die L2 cachePassive heatsink4HP cPCI-6920 series support single processor8HP cPCI-6920D series support up to dual processors
ChipsetIntel 5100 Memory Controller Hub (MCH)Intel ICH9R I/O Controller Hub (ICH)
FSB1066 MHz
Host MemoryDual channel DDR2-667 Registered ECC memoryTwo SO-RDIMM sockets for 4HP version; four SO-RDIMM sockets for 8HP versionMaximum up to 16GB capacity
CompactPCIBusPCI 64bit/ 66MHz; V(I/O) 3.3V onlySupports operation in system slot as system master or in peripheral slot as stand-alone server blade without connectivity to CompactPCI bus
PMC/XMCOne PCI 64bit/ 66MHz PMC or PCI-Express x8 XMC site
GigabitEthernetTwo PCI-Express® x4 Intel® 82571EB dual port Gigabit Ethernet controllersTwo 10/100/1000BASE-T egress portsTwo 10/100/1000BASE-T PICMG 2.16 ports(can be routed to optional cPCI-R6000(D) RTM)
GraphicsATI ES1000 graphics controller with 2D acceleratorDDR2-533 64MB graphics memoryDB-15 front panel VGA portAnalog RGB up to 32bit 1600x1200@60Hz refresh rate
Serial PortOne 16C550 compatible DB-9 RS-232 port from Super IO W83627UHG
Storage Interface $^{1}$ USB NAND Flash 4GB onboardCompactFlash Type II socket onboard $^{1}$ Optional 2.5” SATA HDD direct connector onboard
BIOSAMI Workstation BIOS, SPI flash memory
IPMI InterfaceSupports PICMG® 2.9 secondary system management busImplements IPMI functions defined by IPMI Specification v1.5ATmega128L-8AU Baseboard Management Controller(BMC) with 128KB programmable in-System Flash, 4KB EEPROM, and 4KB internal SDRAM
Faceplate I/O4HP (cPCI-6920):2x USB2.0 ports2x 10/100/1000BAST-T Ethernet portsAnalog DB-15 VGA port8HP (cPCI-6920D):4x USB2.0 ports2x 10/100/1000BASE-T Ethernet portsAnalog DB-15 VGA portDB-9 RS-232 portPS/2 Keyboard/ Mouse Combo portPMC/XMC slot
Onboard PeripheralsCompactFlash socket (optional Serial ATA connector) $^{1}$ USB NAND Flash 4GB
OS CompatibilityMicrosoft Windows XP Professional SP2Microsoft Windows Server 2003Fedora Core 8Other OS support upon request
EnvironmentalOperating Temperature $^{2,3}$ : 0 to 55°C with forced air flowStorage Temperature: -40°C to 85°CHumidity: 20% to 90%@60°C non-condensingShock: 15G peak-to-peak, 11ms duration, non-operatingVibration $^{4}$ : Operating 1.88Grms, 5-500Hz, each axis w/o hard drive.
EMICE EN55022FCC Class A
# Notes: 1. The CompactFlash socket comes with a removable adapter design (DB-6920CF) and can be replaced with a SATA HDD connector adapter (DB-6920SAT) to directly connect a 2.5" SATA HDD. The 2.5" hard drive space is reserved. The CompactFlash and SATA HDD cannot be installed simultaneously. 2. ADLINK-certified thermal design. The thermal performance is dependent on the chassis cooling design. Forced airflow with 30CFM is required. Temperature limit of optional mass storage devices may affect the thermal specification. 3. The system can be operated in an environment with ambient temperature between $50^{\circ}$ C and $55^{\circ}$ C, but not exceeding 96 hours per instance, 360 hours per year, and a maximum o.f 15 instances per year 4. The hard drive limits the operational vibration. When application requires higher specification for anti-vibration, it is recommended to use a flash disk or onboard USB NAND flash. # 2.2 cPCI-R6000 RTM Specifications
MechanicalStandard 6U CompactPCI® rear I/OBoard size: 233.35mm x 80mmSingle slot (4HP, 20.32mm); Dual slot (8HP, 40.64mm) widthCompactPCI® connectors with rJ3 and rJ5
Faceplate I/O4HP (cPCI-R6000):2x USB2.0 ports2x 10/100/1000BASE-T Ethernet portsDVI-I port (Analog signal only)DB-15 serial portExternal 68-pin SCSI socket8HP (cPCI-R6000D):4x USB2.0 ports2x 10/100/1000BAST-T Ethernet portsDVI-I port (Analog signal only)DB-15 serial portExternal 68-pin SCSI socketPS/2 Keyboard Mouse portMic-in, Line-out ports
Onboard Peripherals4HP (cPCI-R6000):USB 2.0 5-pin headerRS-232 10-pin header (Tx, Rx signals only)Internal 68-pin SCSI socketFloppy connector2x 7-pin Serial ATA connectors8HP (cPCI-R6000D):USB 2.0 5-pin headerRS-232 10-pin header (Tx, Rx signals only)Internal 68-pin SCSI socketFloppy connector2x 7-pin Serial ATA connectorsSerial ATA direct $connector^1$ (opt. CompactFlash $socket)^1$
SCSILSI® Logic LSI53C1020 PCI-X Ultra320 SCSI Controller on PCI-X 64-bit/133MHz bus320MB per second data transfer rateSupports RAID 1 (mirroring)
# Notes: 1. The Serial ATA connector comes in a removable adapter design (DB-6920SAT) and can be replaced with the CompactFlash socket adapter (DB-6920CF). The CompactFlash and SATA HDD share the same space and cannot be installed simultaneously. # 2.3 I/O Connectivity Table
cPCI-6920 (4HP)cPCI-6920D (8HP)
FaceplateOnboardFaceplateOnboard
Gigabit EthernetY x2Y x2
COM 1Y (DB-9)
COM 2
COM 4
USB 2.0Y x2Y x4
PMC/XMCY
VGAYY
Serial ATA $Optional^{(1)}$ $Optional^{(1)}$
Compact FlashYY
PS/2 KB/MSY
USB FlashYY
SCSI
GP LEDY x4Y x4
Reset ButtonYY
# Notes: 1. Optional SATA HDD adapter kit (DB-SATA) for 2.5" SATA HDD onboard mounting (2.5"HDD and CF share the same space and cannot be installed simultaneously).
cPCI-R6000 (4HP)cPCI-R6000D (8HP)
FaceplateOnboardFaceplateOnboard
Gigabit EthernetY x2 (2.16)Y x2 (2.16)
COM 1
COM 2Y (DB-9)Y (DB-9)
COM 4Y (10-pin)Y (10-pin)
USB 2.0Y x2Y (5-pin)Y x4Y (5-pin)
PMC/XMC
VGAYY
Serial ATAY x2 (7-pin)Y x3(2)
Compact FlashOptional(3)
PS/2 KB/MSY
USB Flash
SCSIYYYY
FloppyYY
AudioY
GP LED
Reset Button
# Notes: 2. Two 7-pin SATA connectors for external HDDs and one connector for onboard 2.5" SATA HDD. 3. Optional CF socket adapter kit (DB-CF-SA) for additional CF socket (CF and 2.5" HDD share the same space and cannot be installed simultaneously). # 2.4 Power Requirements In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires of each voltage. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires of each voltage. The tolerance of the voltage lines described in the CompactPCI specification (PICMG 2.0 R3.0) is +5%/-3% for 5, 3.3 V and ±5% for ±12V. This specification is for power delivered to each slot and it includes both the power supply and the backplane tolerance.
VoltageNominal ValueToleranceMax. Ripple (P - P)
5V+5.0 VDC+5% / -3%50 mV
3.3V+3.3 VDC+5% / -3%50 mV
+12V+12 VDC+5% / -5%240 mV
-12V-12 VDC+5% / -5%240 mV
V I/O (PCI I/O Buffer Voltage)+3.3 VDC or +5 VDC+5% / -3%50 mV
GND
# Power Consumption This section provides information on the power consumption of cPCI-6920 Series when using 1x/2x Dual-Core Intel® Xeon® LV 5138 or 1x/2x Quad-Core Intel® Xeon® L5408 processor(s) with 4x 2GB SO-RDIMM and onboard 60GB SATA hard drive. The systems were tested in Idle Mode and Full Loading Mode under Windows XP.
1x Dual-Core LV 5138
Windows® XP, Idle
Power requirement+3.3V+5VTotal
Current (A)9.134.46
Watts (W)30.1322.3052.43
Windows® XP, CPU 100% Usage
Power requirement+3.3V+5VTotal
Current (A)14.639.74
Watts (W)40.3048.7092.00
2x Dual-Core LV 5138
Windows® XP, Idle
Power requirement+3.3V+5VTotal
Current (A)10.844.67
Watts (W)35.7723.3559.12
Windows® XP, CPU 100% Usage
Power requirement+3.3V+5VTotal
Current (A)14.1416.93
Watts (W)46.6684.65131.31
1x Quad-Core L5408
Windows® XP, Idle
Power requirement+3.3V+5VTotal
Current (A)10.692.54
Watts (W)35.2812.7047.98
Windows® XP, CPU 100% Usage
Power requirement+3.3V+5VTotal
Current (A)11.9413.93
Watts (W)39.4069.65109.05
2x Quad-Core L5408
Windows® XP, Idle
Power requirement+3.3V+5VTotal
Current (A)11.063.00
Watts (W)36.5015.0051.50
Windows® XP, CPU 100% Usage
Power requirement+3.3V+5VTotal
Current (A)13.2317.63
Watts (W)43.6688.15131.81
# 3 Functional Description The following sections describe the cPCI-6920 Series features and functions. # 3.1 Processors The 4HP cPCI-6920 supports a single processor and the 8HP cPCI-6920D supports dual processors in the FC-LGA771 package. The following table lists the processors supported by the cPCI-6920 Series and their power ratings.
FeaturesQuad-Core Intel® Xeon® Processor L5408Dual-Core Intel® Xeon® Processor LV 5138
Clock2.13GHz2.13GHz
L2 cache12MB4MB
FSB1066MHz1066MHz
Maximum Power (TDP $^{1}$ )40W35W
Nominal T $_{CASE\_MAX}$ 72°C70.8°C
Short-Term T $_{CASE\_MAX}$ $^{2}$ 87°C85.8°C
# Notes: 1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate. 2. The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances per year, as compliant with NEBS Level 3. # Quad-Core Intel® L5408 Processor The Quad-Core Intel® Xeon® Processor L5408 is a low power, low voltage, server-class processor utilizing four 45-nm Hi-k next generation Intel® Core™ microarchitecture cores. The processor is manufactured on Intel's 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. Some key features include on-die, primary 32-kB instruction cache and 32-kB write-back data cache in each core and 12 MB (2 x 6MB) Level 2 cache with Intel® Advanced Smart Cache Architecture. The processors' Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced effective bus latency and improved performance. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible. Enhanced thermal and power management capabilities are implemented including Intel® Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. These technologies are targeted for dual processor configurations in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations. Additional features of the Quad-Core Intel® Xeon® Processor L5408 include Intel® Wide Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Streaming SIMD Extensions 4.1 (SSE4.1). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. The Quad-Core Intel® Xeon® Processor L5408 supports Intel® 64 Architecture as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. # Dual-Core Intel® LV 5138 Processor The Dual-Core Intel® Xeon® Processor LV 5138 is a 64-bit server-class processor utilizing two Intel microarchitecture cores. These processors are based on Intel's 65 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. Some key features include on-die, 32 KB Level 1 instruction and data caches and 4 MB Level 2 cache with Advanced Transfer Cache Architecture. The processors' Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible. Enhanced thermal and power management capabilities are implemented including Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. These technologies are targeted for dual processor in enterprise environments. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep® Technology provides power management capabilities to servers and workstations. Additional features of the Dual-Core Intel® Xeon® Processor LV 5138 include Advanced Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient double-precision floating point, SIMD integer, and memory management operations. The Dual-Core Intel® Xeon® Processor LV 5138 also supports Intel® Extended Memory 64 Technology (Intel® EM64T) as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. # 3.2 Chipset The cPCI-6920 Series incorporates the Intel® 5100 Memory Controller Hub (MCH) and I/O Controller Hub (ICH9R). # Intel® 5100 Memory Controller Hub The Intel® 5100 Memory Controller Hub Chipset is designed for systems based on the Dual-Core Intel® Xeon® processor 5100 series and Quad-Core Intel® Xeon® processor 5400 series and supports FSB operation of 1066 MT/s. The Intel® 5100 MCH provides two FSB processor interfaces, two DDR2 memory channels, six x4 PCI Express bus interfaces configurable to form x4, x8 or x16 ports, an Enterprise South Bridge Interface (ESI), and three SMBus interfaces for system management, PCI Hot Plug\* control and DIMM Serial Presence Detect (SPD). The Intel® 5100 Memory Controller Hub Chipset device has DMA Engine (Crystal Beach [CB]) capabilities and supports Intel® I/O Acceleration Technology (Intel® I/OAT). # Intel® I/O Controller Hub 9R The ICH9R is an I/O controller hub supporting various I/O interfaces including six PCI Express x1 ports, Serial ATA host controllers supporting up to six SATA ports at a speed of 3 Gb/s, twelve external USB 2.0 ports with port disable capability, a System Management Bus interface (SMBus), a Serial Peripheral Interface (SPI) and a Low Pin Count bus (LPC) for BIOS and firmware storage. Additionally, the ICH9R contains a PCI Controller supporting up to four Bus Masters (PCI Local Bus Specification, Rev. 2.3 compliant), an integrated 10/100/1000 LAN controller and a dedicated ESI port for communication with the MCH. The ICH9R component provides the data buffering and arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance. The ICH9R component is ACPI compliant Suspend to RAM, Suspend to Disk, and Soft-Off power management states. Through the use of the integrated LAN functions, the ICH9R also supports Alert Standard Format for remote management. Figure 1-1: cPCI-6920 Series Functional Block Diagram shows a block diagram of the Intel® 5100 MCH Chipset based platform. # 3.3 Memory The cPCI-6920 Series supports dual channel, registered, ECC DDR2 SDRAM operating at 667MHz. In the 4HP version, Channel 0 is connected to two 200-pin horizontal SO-RDIMM sockets; in the 8HP version, each channel (Channels 0/1) connects to two vertical SO-RDIMM sockets (four sockets). Available COTS DDR2-667 SO-RDIMM densities are 1GB, 2GB, and 4GB. The cPCI-6920 Series supports up to 16GB of physical memory using the largest system memory configuration supported by 2Gb DRAM devices. All DIMMs must consist of x4 or x8 DDR2 DRAMs. Up to eight different types of DIMMs can be installed. The same type of DIMM does not need to be installed in each rank. A rank on one DIMM can be different than a rank on another DIMM. ![The image displays a white document icon with a folded upper-right corner and faint horizontal lines representing text, overlaid with a large, bold red checkmark.](.cpci-6920-50-15065-1020-202/ff9ad4a960bd75bc4797f746ddb2fdda5ea24ea1031397172bebb6bc99870417.jpg) NOTE: Memory configuration changes can only be performed at the factory. Failure to comply with the above may result in damage to your board or improper operation. # 3.4 ATI ES1000 Graphics Controller The ATI ES1000 Graphics Controller provides proven and reliable 2D graphics performance for today's applications in 16-bit or 32-bit color. Detailed features are as follows: ▶ 32-bit PCI bus (Rev 2.2), 3.3 V with bus mastering support ▶ Highly-optimized 128-bit engine, capable of processing multiple pixels/clock ▶ Optimized handling of fonts and text using ATI proprietary techniques ▶ Acceleration in 8/16/32 bpp modes (8bpp indexed color mode); also enhanced with 4444 aRGB 16 bit mode and 88 alpha/index 16 bit mode ▶ Single resolution, up to 1600x1200, at 75Hz refresh rate, and 16 bit color (panel display maximum refresh rate for 1600x1200 is 60Hz) ▶ Support for up to 256MB local frame buffer, or display from system memory via SMA, in either linear or tiled addressing modes ▶ Virtual desktop support ▶ Supports JEDEC compatible DDR1 or DDR2 SDRAM or SGRAM ▶ Total memory sizes from 8MB to 256MB # 3.5 PCI-E to PCI Bridge The cPCI-6920 Series is designed using the Tundra Tsi384 PCI-Express-to-PCI bridge to downgrade PCI-Express links from the Intel chipset to PCI bus. One Tsi384 (U46\*) is used to convert the PCI-Express x4 link from the Intel 5100 MCH to a PCI-X 64-bit/133MHz bus on J1 for CompactPCI support. The second Tsi384 (U2-L\*) is to convert a PCI-Express x1 link from the Intel ICH9R to a PCI 64-bit/66MHz bus for the PMC site (cPCI-6920D only). The Tsi384 supports 3.3V signaling only. Note\*: See Figure 4-1: cPCI-6920 Board Layout and Figure 4-4: cPCI-6920D Board Layout. # 3.6 PMC/XMC Site The cPCI-6920 series supports a PMC/XMC site for front panel I/O expansion. The PMC site provides a 64bit/66MHz PCI bus link using a Tundra Tsi384 PCI-Express-to-PCI bridge and PCI-Express x1 link from the Intel® ICH9R I/O Hub. The PMC supports +3.3V signaling with no +5V tolerance. The JN3 connector provides a x8 PCI-Express Link from the Intel® 5100 MCH for the XMC interface. XMC provides a higher transfer speed for I/O expansion than PMC. # 3.7 Onboard USB Flash The cPCI-6920 provides a 4GB USB interface solid state NAND flash device onboard as a mass storage or boot device option. The cPCI-6920 uses two Hynix 16Gbit NAND Flash devices with MLC (Multi-Level Cell) NAND cell and a USB 2.0 controller to enhance NAND management. The 4GB USB flash supports installation of Windows XP embedded or Linux operating systems or can simply be used as a storage device like a USB flash drive. # 3.8 Super I/O The Winbond W83627UHG Super I/O is supports PS/2 keyboard/mouse, 16550-compatible serial ports, floppy drive interface, and hardware monitor function to monitor CPU voltage, power supply voltages and system temperature. # 3.9 Battery The cPCI-6920 is provided with a 3.0V “coin cell” lithium battery for the Real Time Clock (RTC). The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. Rayovac BR2032 is equipped on board by default. This page intentionally left blank. # 4 Board Interfaces This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the cPCI-6920 Series. # 4.1 cPCI-6920 SBC Board Layout ![SW1\nCN2\nCN3\nCN5\nU7\nCN7\nCN8\nU25\nU26\nCN10\nU31\nSW3\nU9\nU11\nCN6\nBT\nSO-RDIMM5\nSO-RDIMM6\nU49\nU46\nJ5\nJ3\nJ2\nJ1](.cpci-6920-50-15065-1020-202/433214bf4168aaecced23eea95b2f0e00f152d1041754e9805addb1d5d236923.jpg)
U49CPU socketCN3/5USB ports
U46PCIe to PCI bridgeCN6DB-6920SAT/DB-6920CF connector
U31North BridgeCN7/8GbE ports
U25/26GbE Controller 82571EBCN10VGA port
U7Super I/O W83627UHGSO-RDIMMxSO-RDIMMs
U9South BridgeBTBattery socket
U11VGA controllerJ1/2/4/5CompactPCI Connectors
CN2LEDSW1/3Switches
Figure 4-1: cPCI-6920 Board Layout # 4.2 cPCI-6920 SBC Front Panel ![System LEDs\nVGA\nUSB\nGbE 2/1\nReset\nUSB 2.0 x2](.cpci-6920-50-15065-1020-202/ba440099693b07403cba4da5c06e4f6ff4f49671e6e33fbc5ae432783e454265.jpg) Figure 4-2: cPCI-6920 Front Panel Layout # System LEDs ![WDT HD\nPW HW\nRST](.cpci-6920-50-15065-1020-202/66217154cc160b21b437a3327f18ab602e23ae5dcb4e83dcab5db7d8481eab6d.jpg)
LEDColorConditionIndication
Power (PW)GreenOFFSystem is off
ONSystem is on
BlinkFail to power on
HotSwap (HW)BlueOFFHandles closed, System is on
Fast BlinkPreparing to shut down system (LED: 0.1s on, 0.9s off.)
ONHandles open and SBC ready to be removed
Slow BlinkVoltages out of tolerance: 3.3V, 5V, 12V, 1.5V over ±5% (LED 2s on, 1s off)
WDT (WDT)RedOFFNo Watchdog event
ONWatchdog event alert
HDD (HD)AmberOFFNo read/write access to HDD
BlinkData read/write in process
Table 4-1: cPCI-6920 Front Panel System LED Descriptions # 4.3 cPCI-6920 SBC Assembly Layout This section describes the final assembly layout of cPCI-6920 Series. The single-slot width cPCI-6920 provides two 200-pin SO-RDIMM sockets for DDR2-667 SO-RDIMM memory and is equipped with a removable DB-6920CF adapter card to provide CompactFlash slot as standard. The DB-6920CF can be replaced with a DB-6920SAT adapter board to directly mount a 2.5" SATA hard drive. Please contact your sales representative to purchase the DB-6920SAT. ![DB-6920CF (default)\nHeat sink 2\nSO-RDIMM 1\nSO-RDIMM 2\nHeat sink 1](.cpci-6920-50-15065-1020-202/fe0e71a5ed82b98ae907394694e03c4797d0e88d5cdec58cb081dfde0a944cab.jpg) ![SATA HDD\nSO-RDIMM 1\nSO-RDIMM 2\nDB-6920SAT](.cpci-6920-50-15065-1020-202/0394bf78e52d9b3a13849c72b784f1c821fbf8c99d5860afffccf06bb5307acd.jpg) Figure 4-3: cPCI-6920 SBC Assembly Layout # 4.4 cPCI-6920D SBC Board Layout The dual-slot width cPCI-6920D is comprised of the cPCI-6920 single-slot main board and the DB-6920L2 riser card to expand I/O connectivity with PS/2, COM, 2x USB ports and a PMC/XMC site. ![U2-L\nSW2-L SW1-L\nCN2-L\nCN3-L\nCN4-L\nCN1-L\nSO RDIMM1 SO-RDIM2 SO-RDIM3 SO-RDIM4\nU48 U49\nJN3 JN1 JN2\nJN4\nDB-6920L2](.cpci-6920-50-15065-1020-202/256e7a4d08ea711766384493b1cb64d1d63e3e2d4e50cb6b96d224e4f6804377.jpg)
U49CPU 0JN4PMC connectors
U48CPU 1JN3XMC connector
SO-RDIMMxSO-RDIMM socketsU2-LPCIe to PCI bridge
JN1PMC connectorsSW1-LSwitch 1
JN2PMC connectorsSW2-LSwitch 2
CN1-LPS/2 Keyboard Mouse portCN3-LUSB port
CN2-LUSB portCN4-LCOM port
Figure 4-4: cPCI-6920D Board Layout # 4.5 cPCI-6920D SBC Front Panel ![PMC/XMC\nUSB 2.0 x2\nCOM\nPS/2\nWOR HD\nPFC RS\nPUCXMC\nUSB\nCOM\nKEMUS\nVGA\nReset\nUSB 2.0x2\nGbE 1/2\nVGA](.cpci-6920-50-15065-1020-202/bf73376be8f663988e519c96eb73dd9e0e421cc1489aa934f636ad936a737c72.jpg) Figure 4-5: cPCI-6920D Front Panel Layout # 4.6 cPCI-R6000 RTM Board Layout ![82.53\nCN4-R\nrJ5\nCN2-R\nU26-R\nCNY1-R\nCN9-R\nSW3-R SW4-R\nCN15-R\nrJ3\nSW1-R SW2-R\nCN14-R\nCN16-R\nCN21-R\nJP1-R\nCN1-R\nCN10-R\nU31-R\nCN12-R\nCN5-R](.cpci-6920-50-15065-1020-202/252122e9e6ada8b7c45db93b1c47395e58169d93e68e4959556d965764fba28a.jpg)
U26-RPCIe-to-PCI bridgeCN14-RDB-R6000L2 connector $^{1}$
U31-RLSI53C1020 SCSI controllerCN12-RExternal SCSI connector
JP1-RUSB pin header (5-pin)CN15/16-RUSB ports
CN1/2-RSATA port (7-pin)CN20/21-RGbE ports
CN5-RInternal SCSI connectorCNY1-RDVI to VGA adapter
CN9-RSerial portrJ3/5CompactPCI Connectors
CN10-RSerial pin header (10-pin)SW1~4-RSwitches
CN4-RFloppy connector
Figure 4-6: cPCI-R6000 RTM Board Layout Note(1): Used for cPCI-R6000D RTM – shown here for clarity. # 4.7 cPCI-R6000 RTM Front Panel ![SCSI\nGbE x2\nUSB 2.0 x2\nCOM\nVGA](.cpci-6920-50-15065-1020-202/026421697c100510ec38866ef6e54d26aea531e2c8060218d390ff798c302a84.jpg) Figure 4-7: cPCI-R6000 RTM Front Panel # 4.8 cPCI-R6000D RTM Board Layout ![82.53\nCN4-R\nCN2-R\nCN19-R\nCN18-R\nCN11-R\nDB-R6000L2\n233.2±0.15\nJP1-R\nCN1-R\nCN10-R\nCN6-R\nU31-R\nCN12-R\nCN5-R](.cpci-6920-50-15065-1020-202/6bbd4942b7b32f2852b7cb559bcd6c41e7532a280ebb8bc6649b754c2220c409.jpg)
CN1/2-RSATA port (7-pin)CN11-RPS/2 KB/MS port
CN4-RFloppy connectorCN12-RExternal SCSI connector
CN5-RInternal SCSI connectorCN18/19-RUSB ports
CN6-RDB-6920SAT/DB-6920CF connectorJP1-RUSB pin header (5-pin)
CN10-RSerial pin header (10-pin)
Figure 4-8: cPCI-R6000D RTM Board Layout # 4.9 cPCI-R6000D RTM Front Panel ![Line-out\nMic-in\nPS/2\nUSB 2.0 x2\nSCSI\nGbE x2\nUSB 2.0 x2\nCOM\nVGA](.cpci-6920-50-15065-1020-202/b0c6cebb8dad7f6b166948e7a94b4630f05e5e508f9a811d1a1c286290c379de.jpg) Figure 4-9: cPCI-R6000D RTM Front Panel # 4.10 cPCI-R6000D RTM Assembly Layoutl ![82.53\n2.5' HDD bracket\nDVI to VGA adapter\nDB-6920SAT (default)\n233.2±0.15](.cpci-6920-50-15065-1020-202/8e041b7fb854eb92fa127138a9a9868447f70c8f57419751ad28c074b514dd92.jpg) ![82.53\nDB-6920CF\nDVI to VGA adapter\n233.2±0.15](.cpci-6920-50-15065-1020-202/624e54b67613a03680ea6eefa8db4abb2d9fa5e1d3ba339b8fefddee5ea564ac.jpg) Figure 4-10: cPCI-R6000D RTM Assembly Layout # 4.11 Connector Pin Assignments USB Connectors (CN3,CN5, CN2-L, CN3-L, CN15-R, CN16-R, JP1-R)
Pin #Signal Name
1Vcc
2UV0-
3UV0+
4GND
![1\n2\n3\n4](.cpci-6920-50-15065-1020-202/fcfe909e5329d62ae4c48b28db98f26f0b1fb312343ac7e6b890219172ec2d45.jpg) Table 4-2: USB Connector Pin Definition DB-15 VGA Connector (CN10)
Signal NamePin #Pin #Signal Name
Red12Green
Blue34N.C.
GND56GND
GND78GND
+5V.910GND
N.C.1112CRTDATA
HSYNC1314VSYNC
CRTCLK15
![Technical line drawing of a rectangular electronic component with multiple pins and mounting holes (no text or symbols)](.cpci-6920-50-15065-1020-202/5e598735d983d600df10a897fd3701c05502f3764a01c61eac860a54c0a44ab7.jpg) Table 4-3: VGA Connector Pin Definition RJ-45 Gigabit Ethernet Connectors (CN7, CN8, CN20-R, CN21-R)
Pin #10BASE-T/100BASE-TX1000BASE-T
1TX+BI_DA+
2TX-BI_DA-
3RX+BI_DB+
4--BI_DC+
5--BI_DC-
6RX-BI_DB-
7--BI_DD+
8--BI_DD-
![1\n8\nActivity Speed](.cpci-6920-50-15065-1020-202/98d671f59d6cf0fc531ead42be85e70c7ab79c02ea2b10cfb8138a2da019d5ea.jpg) Table 4-4: GbE Connector Pin Definitions
Status (CN4, CN5)Speed LED (Green/Amber)Activity LED (Amber)
Network link is not established or system powered offOFFOFF
10 MbpsLinkOFFON
ActiveOFFBlinking
100 MbpsLinkGreenON
ActiveGreenBlinking
1000 MbpsLinkAmberON
ActiveAmberBlinking
Table 4-5: CN7, CN8 Ethernet LED Status Definitions
Status (CN20-R, CN21-R)Speed LED (Green/Amber)Activity LED (Amber)
Network link is not established or system powered offOFFOFF
10 MbpsLinkOFFON
ActiveOFFBlinking
100 MbpsLinkAmberON
ActiveAmberBlinking
1000 MbpsLinkGreenON
ActiveGreenBlinking
Table 4-6: GbE LED CN20-R, CN21-R Status Definitions # PS/2 Keyboard/Mouse Connector (CN1-L, CN11-R)
Pin #SignalFunction
1KBDATAKeyboard Data
2MSDATAMouse Data
3GNDGround
4+5VPower
5KBCLKKeyboard Clock
6MSCLKMouse Clock
![6\n5\n4\n3\n2 1](.cpci-6920-50-15065-1020-202/67f61147ed50f33b8bfe32727be4f12b0773dbe2c72e063c6be5ccef761d48ea.jpg) Table 4-7: PS/2 Keyboard/Mouse Connector Pin Definition # DB-9 Serial Port (CN4-L, CN9-R)
Pin #RS-232
1DCD, Data carrier detect
2RXD, Receive data
3TXD, Transmit data
4DTR, Data terminal ready
5GND, Ground
6DSR, Data set ready
7RTS, Request to send
8CTS, Clear to send
9RI, Ring indicator
![6\n1\n5](.cpci-6920-50-15065-1020-202/24d6066b2d73c492b89ebcd8914234fc708ee78686ce9b7e2a150ff77b676790.jpg) Table 4-8: DB-15 Serial Port Connector Pin Definition # Onboard Serial Port Connector (CN10-R)
Pin #RS-232
1Not used
2Not used
3RXD, Receive data
4Not used
5TXD, Transmit data
6Not used
7Not used
8Not used
9IsoGND, Isolated ground
10Not used
![9\n1\n10\n2](.cpci-6920-50-15065-1020-202/e33a1974d0e59156b88e4e2a2892289acce32c694835358c80a8ee500fc9e6b6.jpg) Table 4-9: Onboard Serial Port Connector Pin Definition # DVI-I Connector (CNY1-R) ![1 2 3 4 5 6 7 8\n9 10 11 12 13 14 15 16\n17 18 19 20 21 22 23 24\nC1 C2\nC3 C4\nC5](.cpci-6920-50-15065-1020-202/abe3a8029ccd04b20ab0b92a671cc7836f695c2c41bebaab10a2f748d27872a6.jpg)
Pin #SignalPin #Signal
1NC16NC
2NC17NC
3GND18NC
4NC19GND
5NC20NC
6DDCCLK_5V21NC
7DDCDAT_5V22GND
8VSYNC23NC
9NC24NC
10NCC1RED
11GNDC2GREEN
12NCC3BLUE
13NCC4HSYNC
14P5VC5GND
15GND
Table 4-10: DVI-I Connector Pin Definition Serial ATA Connectors (CN5/7)
Pin #Signal
1GND
2TX+
3TX-
4GND
5RX-
6RX+
7GND
![1\n7](.cpci-6920-50-15065-1020-202/2161a3018b5500e0a83536010e066481f77114e7541ab3d8f7e1143aee083b38.jpg) Table 4-11: Serial ATA Connector Pin Definition Serial ATA Connector on DB-6920SAT
Pin #Signal
S1GND
S2TX+
S3TX-
S4GND
S5RX-
S6RX+
S7GND
P1NC
P2NC
P3NC
P4GND
P5GND
P6GND
P75V
P85V
P95V
P10GND
P11Reserved
P12GND
P13~P1512V
![S1\nSignal\nS7\nP1\nPower\nP15](.cpci-6920-50-15065-1020-202/d76387ee3c84eb64eff5e2abe6130fdfd25c64d36d7f43eb8192118422747f39.jpg) Table 4-12: Serial ATA Connector on DB-6920SAT Pin Definition 68-pin SCSI Connector (CN5-R, CN12-R)
SignalPin #Pin #Signal
SCSI-SDP12135SCSI-SDN12
SCSI-SDP13236SCSI-SDN13
SCSI-SDP14337SCSI-SDN14
SCSI-SDP15438SCSI-SDN15
SCSI-SDP1-P1539SCSI-SDP1-N1
SCSI-SDP0640SCSI-SDN0
SCSI-SDP1741SCSI-SDN1
SCSI-SDP2842SCSI-SDN2
SCSI-SDP3943SCSI-SDN3
SCSI-SDP41044SCSI-SDN4
SCSI-SDP51145SCSI-SDN5
SCSI-SDP61246SCSI-SDN6
SCSI-SDP71347SCSI-SDN7
SCSI-SDP0-P01448SCSI-SDP0-N0
GND1549GND
DIFFSEN1650NC
P3V3_SCSI1751P3V3_SCSI
P3V3_SCSI1852P3V3_SCSI
NC1953NC
GND2054GND
SCSI-SATN-P2155SCSI-SATN-N
GND2256GND
SCSI-SBSY-P2357SCSI-SBSY-N
SCSI-SACK-P2458SCSI-SACK-N
SCSI-SRST-P2559SCSI-SRST-N
SCSI-SMSG-P2660SCSI-SMSG-N
SCSI-SSEL-P2761SCSI-SSEL-N
SCSI-SCD-P2862SCSI-SCD-N
SCSI-SREQ-P2963SCSI-SREQ-N
SCSI-SIO-P3064SCSI-SIO-N
SCSI-SDP83165SCSI-SDN8
SCSI-SDP93266SCSI-SDN9
SCSI-SDP103367SCSI-SDN10
SCSI-SDP113468SCSI-SDN11
![1\n35\n34\n68](.cpci-6920-50-15065-1020-202/90ca31e1586be3dc8d70b6328f5e8af056cbd8073cc5a81ce1ff8f79ad5be7fe.jpg) Table 4-13: 68-pin SCSI Pin Definition Floppy Connector 34-pin (CN4-R)
Pin #SignalPin #Signal
1GND2Extended Density
3GND4No Connect
5NC6Data Rate
7GND8Index
9GND10Motor A Select
11GND12Drive B Select
13GND14Drive A Select
15GND16Motor B Select
17GND18Step Direction
19GND20Step Pulse
21GND22Write Data
23GND24Write Gate
25GND26Track 0
27GND28Write Protect
29GND30Read Data
31GND32Side 1
33GND34Disk Change
![1\n2\n33\n34](.cpci-6920-50-15065-1020-202/6e5ad447bd063e876920bf0f3c44ed316453a8c3aa2d60191c395ec63b3470d4.jpg) Table 4-14: Floppy Connector Pin Definition CompactFlash Connector on DB-6920CF
Signal NamePin#Pin#Signal Name
GND126GND
DD3227DD11
DD4328DD12
DD5429DD13
DD6530DD14
DD7631DD15
CS1J732CS3J
GND833GND
GND934SDIORJ
GND1035SDIOWJ
GND11365V
GND1237IRQ15
5V13385V
GND1439PCSEL
GND1540NC
GND1641BRSTDRVJ
GND1742SDIORDY
DA21843NC
DA11944SDACKJ
DA02045IDEACTJ
DD02146DIAG
DD12247DD8
DD22348DD9
IOIS16J2449DD10
GND2550GND
![Pure technical line drawing of a mechanical or electrical component without any text, numbers, or symbols](.cpci-6920-50-15065-1020-202/84716343c15a91a7c9bddf4f014064e2092bcc4daa634dee93dbc1735fa27084.jpg) ![1\n26\n25\n50](.cpci-6920-50-15065-1020-202/5edd546f0d2a78a0acf0c3402f8d8e9e6a5ce6e7cac97bd6400c90c490bcac14.jpg) Table 4-15: CompactFlash Connector Pin Definition DB-6920L2 Connector (CN4)
Signal NamePin #Pin #Signal Name
GND12GND
PMC_TXP734PMC_RXP7
PMC_TXN756PMC_RXN7
GND78GND
PMC_TXP6910PMC_RXP6
PMC_TXN61112PMC_RXN6
GND1314GND
PMC_TXP51516PMC_RXP5
PMC_TXN51718PMC_RXN5
GND1920GND
PMC_TXP42122PMC_RXP4
PMC_TXN42324PMC_RXN4
GND2526GND
PMC_TXP32728PMC_RXP3
PMC_TXN32930PMC_RXN3
GND3132GND
PMC_TXP23334PMC_RXP2
PMC_TXN23536PMC_RXN2
GND3738GND
PMC_TXP13940PMC_RXP1
PMC_TXN14142PMC_RXN1
GND4344GND
PMC_TXP04546PMC_RXP0
PMC_TXN04748PMC_RXN0
GND4950GND
PCIE_TXP15152PCIE_RXP1
PCIE_TXN15354PCIE_RXN1
GND5556GND
CLK100_B2B_P5758PLTRST_LPC-L
CLK100_B2B_N5960GND
GND6162COM1_DTR-L
GND6364COM1_RST-L
![199\n120\n1\n2](.cpci-6920-50-15065-1020-202/0646f9967cdfdf321083b60f238f950875b627411c02f735637e5f26c67d9e5a.jpg)
Signal NamePin #Pin #Signal Name
CLK100_XMC_P6566COM1_RI-L
CLK100_XMC_N6768COM1_DCD-L
GND6970COM1_DSR-L
USB2_FRONT_C-P7172COM1_CTS-L
USB2_FRONT_C-N7374COM1_SOUT
GND7576COM1_SIN
USB3_FRONT_C-P7778GND
USB3_FRONT_C-N7980IPMI_DEB_RX
GND8182IPMI_DEB_TX
USB2_OC-L8384GND
USB3_OC-L8586IPM_CLK
GND8788IPM_DAT
B2B_SATA_RXP08990XMC_RST-L
B2B_SATA_RXN09192KBCLK
GND9394KBDATA
B2B_SATA_TXP09596MSDATA
B2B_SATA_TXN09798MSCLK
GND99100GND
P5V_STB101102P12V
P5V_STB103104P12V
N12V105106P5V
P3V3107108P5V
P3V3109110P5V
P3V3111112P5V
P3V3113114P5V
P3V3115116P5V
P3V3117118P5V
GND119120GND
Table 4-16: DB-6920L2 Connector Pin Definition DB-6920CF/DB-6920SAT Connector (CN6, CN6-R)
Signal NamePin #Pin #Signal Name
GND12GND
GND34GND
GND56GND
GND78GND
GND910GND
GND1112GND
GND1314GND
GND1516GND
GND1718GND
GND1920GND
GND2122GND
GND2324GND
GND2526GND
GND2728GND
GND2930GND
P3V33132P5V
P3V33334P5V
P3V33536P5V
P3V33738P5V
P1V83940NC
P1V84142NC
P1V84344NC
GND4546GND
GND4748SATA-TXN0
GND4950SATA-TXP0
SATA-RXN05152GND
SATA-RXP05354GND
GND5556RESET#
GND5758GND
GND5960GND
![1\n2\n59\n60](.cpci-6920-50-15065-1020-202/3dce6e71d8d96293183334867ec9c7e372e4969ee7582a19f49c4f8ddfa4f703.jpg) Table 4-17: DB-6920CF/DB-6920SAT Connector Pin Definition PMC Connector (JN1, JN2, JN3, JNX1)
Pin#JN1 SignalJN2 SignalJN3 SignalJNX1 Signal
1PMC_TCKP12VPIO1NC
2N12VPMC_TRST-LPIO2GND
3GNDPMC_TMSPIO3GND
4PCIX_INTA-LNC (PMC_TDO)PIO4PCIX_CBE-L7
5PCIX_INTB-LPMC_TDIPIO5PCIX_CBE-L6
6PCIX_INTC-LGNDPIO6PCIX_CBE-L5
7PMC_MOD-L1GNDPIO7PCIX_CBE-L4
8P5VNCPIO8GND
9PCIX_INTD-LNCPIO9PMC_VIO
10NCNCPIO10PCIX_PAR64
11GNDPMC_MOD-L2PIO11PCIX_AD63
12P3V3_PMCAUXP3V3PIO12PCIX_AD62
13CLK66_PCIX_PMCPMC_RST-LPIO13PCIX_AD61
14GNDPMC_MOD-L3PIO14GND
15GNDP3V3PIO15GND
16PCIX_GNT-L0PMC_MOD-L4PIO16PCIX_AD60
17PCIX_REQ-L0PMC_PME-LPIO17PCIX_AD59
18P5VGNDPIO18PCIX_AD58
19PMC_VIOPCIX_AD30PIO19PCIX_AD57
20PCIX_AD31PCIX_AD29PIO20GND
21PCIX_AD28GNDPIO21GND
22PCIX_AD27PCIX_AD26PIO22PCIX_AD56
23PCIX_AD25PCIX_AD24PIO23PCIX_AD55
24GNDPCIX_AD23PIO24PCIX_AD54
25GNDPMC_IDSELPIO25PCIX_AD53
26PCIX_CBE-L3PCIX_AD23PIO26GND
27PCIX_AD22P3V3PIO27GND
28PCIX_AD21PCIX_AD20PIO28PCIX_AD52
29PCIX_AD19PCIX_AD18PIO29PCIX_AD51
30P5VGNDPIO30PCIX_AD50
31PCIX_FRAME-LPCIX_AD16PIO31PCIX_AD49
32PCIX_AD17PCIX_CBE-L2PIO32GND
33PCIX_FRAME-LGNDPIO33GND
![64\n63\n2\n1](.cpci-6920-50-15065-1020-202/c51182ac134a747d1be9846280f3111e6bb61ed4a03241c769dc0b23b8c10452.jpg)
Pin#JN1 SignalJN2 SignalJN3 SignalJNX1 Signal
34GNDNCPIO34PCIX_AD48
35GNDPCIX_TRDY-LPIO35PCIX_AD47
36PCIX_IRDY-LP3V3PIO36PCIX_AD46
37PCIX_DEVSEL-LGNDPIO37PCIX_AD45
38P5VPCIX_STOP-LPIO38GND
39PCIX_PCIXCAPPCIX_PERR-LPIO39GND
40PCIX_LOCK-LGNDPIO40PCIX_AD44
41NCP3V3PIO41PCIX_AD43
42NCPCIX_SERR-LPIO42PCIX_AD42
43PCIX_PARPCIX_CBE-L1PIO43PCIX_AD41
44GNDGNDPIO44GND
45PMC_VIOPCIX_AD14PIO45GND
46PCIX_AD15PCIX_AD13PIO46PCIX_AD40
47PCIX_AD12PCIX_M66ENPIO47PCIX_AD39
48PCIX_AD11PCIX_AD10PIO48PCIX_AD38
49PCIX_AD9PCIX_AD8PIO49PCIX_AD37
50P5VP3V3PIO50GND
51GNDPCIX_AD7PIO51GND
52PCIX_CBE-L0NCPIO52PCIX_AD36
53PCIX_AD6P3V3PIO53PCIX_AD35
54PCIX_AD5NCPIO54PCIX_AD34
55PCIX_AD4NCPIO55PCIX_AD33
56GNDGNDPIO56GND
57PMC_VIONCPIO57GND
58PCIX_AD3NCPIO58PCIX_AD32
59PCIX_AD2GNDPIO59NC
60PCIX_AD1NCPIO60NC
61PCIX_AD0PCIX_ACK64-LPIO61NC
62P5VP3V3PIO62GND
63GNDGNDPIO63GND
64PCIX_REQ64-LNCPIO64NC
Table 4-18: PMC Connector Pin Definition XMC Connector (JN3) ![F1\nA1\nF19\nA19](.cpci-6920-50-15065-1020-202/f6e72e9a065f754790e89f76a2c9c863c178f1af91a54b1935eb39f2272cfbb6.jpg)
Pin#ABCDEF
1PETp0PETn03.3VPETp1PETn1VPWR
2GNDGNDTRST#GNDGNDMRSTI#
3PETp2PETn23.3VPETp3PETn3VPWR
4GNDGNDTCKGNDGNDMRSTO#
5PETp4PETn43.3VPETp5PETn5VPWR
6GNDGNDTMSGNDGND+12V
7PETp6PETn63.3VPETp7PETn7VPWR
8GNDGNDTDIGNDGND-12V
9NCNCNCNCNCVPWR
10GNDGNDTDOGNDGNDGA0
11PERp0PERn0MBIST#PERp1PERn1VPWR
12GNDGNDGA1GNDGNDMPRESENT#
13PERp2PERn23.3V AUXPERp3PERn3VPWR
14GNDGNDGA2GNDGNDMSDA
15PERp4PERn4NCPERp5PERn5VPWR
16GNDGNDMVMROGNDGNDMSCL
17PERp6PERn6NCPERp7PERn7NC
18GNDGNDNCGNDGNDNC
19REFCLK+0REFCLK-0NCWAKE#ROOT0#NC
Table 4-19: XMC Connector Pin Definition DB-R6000L2 Connector (CN14)
Signal NamePin #Pin #Signal Name
SATA-T1P12USB-P3
SATA-T1N34USB-N3
GND56GND
SATA-R1P78USB-OC3#
SATA-R1N910GND
GND1112GND
GND1314USB-P2
HAD_RST-L1516USB-N2
HAD_SYNC1718GND
HAD_SDOUT1920USB-OC2#
HAD_BIT_CLK2122GND
HAD_SDIN02324PS2-KBC
GND2526PS2-KBD
HAD_SDIN12728PS2-MSD
HAD_SDIN22930PS2-MSC
HAD_SDIN33132GND
GND3334RESET#
GND3536GND
GND3738GND
GND3940GND
GND4142GND
GND4344GND
GND4546GND
GND4748GND
GND4950GND
P5V5152P1V8
P5V5354P1V8
P5V5556P1V8
P5V5758NC
P5V5960NC
GND6162GND
![2\n1\n61\n62\n60\n59](.cpci-6920-50-15065-1020-202/59f84d24809d7034b1459c7ec40b98737d33be602a5772dd59e2bdb2f450ca8c.jpg) Table 4-20: DB-R6000L2 Connector Pin Definition CompactPCI J1 Connector Pin Assignment
PinZABCDEF
1GNDP5V_STBN12V_STBCPCI_TRST-LP12V_CPCIJ1P5V_STBGND
2GNDCPCI_TCKP5V_STBCPCI_TMSNCCPCI_TDIGND
3GNDJCPCI_INTA-LJCPCI_INTB-LJCPCI_INTC-LP5V_STBJCPCI_INTD-LGND
4GNDP5V_IPMBJCPCI_HEALTHY-LCPCI_VIONCNCGND
5GNDNCNCJCPCI_RESET-LGNDCPCI_GNT-L0GND
6GNDJCPCI_REQ-L0CPCI_PRESENT-LP3V3_STBCPCI_CLK0JCPCI_AD31GND
7GNDAD30JCPCI_AD29JCPCI_AD28GNDJCPCI_AD27GND
8GNDJCPCI_AD26GNDCPCI_VIOJCPCI_AD25JCPCI_AD24GND
9GNDJCPCI_CBE-L3JCPCI_IDSELJCPCI_AD23GNDJCPCI_AD22GND
10GNDJCPCI_AD21GNDP3V3_STBJCPCI_AD20JCPCI_AD19GND
11GNDJCPCI_AD18JCPCI_AD17JCPCI_AD16GNDJCPCI_BE-L2GND
12-14Key
15GNDP3V3_STBJCPCI_FRAME-LJCPCIIRDY-LCPCI_BDSEL-LJCPCI_TRDY-LGND
16GNDJCPCI_DEVSEL-LCPCI_PCIXCAPCPCI_VIOJCPCI_STOP-LJCPCI_LOCK-LGND
17GNDP3V3_STBIPMB_SCLIPMB_SDAGNDJCPCI_PERR-LGND
18GNDJCPCI_SERR-LGNDP3V3_STBJCPCI_PARJCPCI_CBE-L1GND
19GNDP3V3_STBJCPCI_AD15JCPCI_AD14GNDJCPCI_AD13GND
20GNDJCPCI_AD12GNDCPCI_VIOJCPCI_AD11JCPCI_AD10GND
21GNDP3V3_STBJCPCI_AD9JCPCI_AD8CPCI_M66ENJCPCI_CBE-L0GND
22GNDJCPCI_AD7GNDP3V3_STBJCPCI_AD6JCPCI_AD5GND
23GNDP3V3_STBJCPCI_AD4JCPCI_AD3P5V_STBJCPCI_AD2GND
24GNDJCPCI_AD1P5V_STBCPCI_VIOAD0ACKGND
25GNDP5V_STBJCPCI_REQ64-LJCPCI_ENUM-LP3V3_STBP5V_STBGND
Table 4-21: CompactPCI J1 Connector Pin Definition Note: There is a yellow coding key in the J1 Connector to prevent plugging the blade into a 5V backplane. ![Image showing a pixelated barcode with a yellow 'J' logo centered over a grid of dots.](.cpci-6920-50-15065-1020-202/a0e977d6e33f12a918f1502ed3a866cc67cc899c918f074f7f37a4ba9094acb4.jpg) CompactPCI J2 Connector Pin Assignment
PinZABCDEF
1GNDCPCI_CLK1GNDJCPCI_REQ-L1CPCI_GNT-L1JCPCI_REQ-L2GND
2GNDCPCI_CLK2CPCI_CLK3SYSEN-LCPCI_GNT-L2JCPCI_REQ-L3GND
3GNDCPCI_CLK4GNDCPCI_GNT-L3JCPCI_REQ-L4JCPCI_GNT-L4GND
4GNDCPCI_VIONCJCPCI_CBE-L7GNDJCPCI_CBE-L6GND
5GNDJCPCI_CBE-L5GNDCPCI_VIOJCPCI_CBE-L4JCPCI_PAR64GND
6GNDJCPCI_AD63JCPCI_AD62JCPCI_AD61GNDJCPCI_AD60GND
7GNDJCPCI_AD59GNDCPCI_VIOJCPCI_AD58JCPCI_AD57GND
8GNDJCPCI_AD56JCPCI_AD55JCPCI_AD54GNDJCPCI_AD53GND
9GNDJCPCI_AD52GNDCPCI_VIOJCPCI_AD51JCPCI_AD50GND
10GNDJCPCI_AD49JCPCI_AD48JCPCI_AD47GNDJCPCI_AD46GND
11GNDJCPCI_AD45GNDCPCI_VIOJCPCI_AD44JCPCI_AD43GND
12GNDJCPCI_AD42JCPCI_AD41JCPCI_AD40GNDJCPCI_AD39GND
13GNDJCPCI_AD38GNDCPCI_VIOJCPCI_AD37JCPCI_AD36GND
14GNDJCPCI_AD35JCPCI_AD34JCPCI_AD33GNDJCPCI_AD32GND
15GNDNCGNDCPCI_FAL-LJCPCI_REQ-L5CPCI_GNT-L5GND
16GNDNCNCCPCI_DEG-LGNDNCGND
17GNDNCGNDJ2_RSTBTN-LJCPCI_REQ-L6CPCI_GNT-L6GND
18GNDNCNCNCGNDNCGND
19GNDGNDGNDNCNCNCGND
20GNDCPCI_CLK5GNDNCGNDNCGND
21GNDCPCI_CLK6GNDNCNCNCGND
22GNDGA4GA3GA2GA1GA0GND
Table 4-22: CompactPCI J2 Connector Pin Definition CompactPCI J3 Pin Assignment
PinZABCDEF
1GNDHDA_RST-LHDA_SYNCHDA_BIT_CLKHDA_SDOUTHAD_SDIN0GND
2GNDHAD_SDIN1HAD_SDIN2HAD_SDIN3NCNCGND
3GNDPS2-KBDPS2-KBCNCPS2-MSDPS2-MSCGND
4GNDSATA-T1PSATA-T1NGNDSATA-T2PSATA-T2NGND
5GNDGNDGNDNCGNDGNDGND
6GNDSATA-R1PSATA-R1NGNDSATA-R2PSATA-R2NGND
7GNDCOM4-TXCOM4-RXCOM2-DCDI2C_CLKI2C_DATGND
8GNDCOM2-RXCOM2-TXCOM2-DTRCOM2-DSRCOM2-RTSGND
9GNDCOM2-CTSCOM2-RIRGB-BLUERGB-REDRGB-GREENGND
10GNDUSB-OC9-LRGB-DDCCLKRGB-DDCDATRGB-HSYNCRGB-VSYNCGND
11GNDUSB-P8USB-N8GNDUSB-P9USB-N9GND
12GNDUSB-P6USB-N6GNDUSB-P7USB-N7GND
13GNDUSB-P4USB-N4GNDUSB-P5USB-N5GND
14GNDUSB-OC4-LUSB-OC5-LUSB-OC6-LUSB-OC7-LUSB-OC8-LGND
15GNDLANBA_TXDP1LANBA_TXDN1GNDLANBA_TXDP3LANBA_TXDN3GND
16GNDLANBA_TXDP0LANBA_TXDN0GNDLANBA_TXDP2LANBA_TXDN2GND
17GNDLANBB_TXDP1LANBB_TXDN1GNDLANBB_TXDP3LANBB_TXDN3GND
18GNDLANBB_TXDP0LANBB_TXDN0GNDLANBB_TXDP2LANBB_TXDN2GND
19GNDP5VP5VP12VP5VP5VGND
Table 4-23: CompactPCI J3 Connector Pin Definition ![| Category | Value |\n|---|---|\n| High definition audio | 100 |\n| PS/2 keyboard/Mouse | 80 |\n| Serial ATA | 75 |\n| Serial port | 70 |\n| USB port | 65 |\n| Ethernet port | 60 |\n| RGB | 55 |\n| I2C | 50 |](.cpci-6920-50-15065-1020-202/8d593583f5fff2bf4c1d6d6e3a19db5c6a3b8c002eae8413bf73b17d1ed6116a.jpg) CompactPCI J5 Pin Assignment
PinZABCDEF
1GNDPCIE-TP0PCIE-TN0GNDPCIE-RP0PCIE-RN0GND
2GNDPCIE-TP1PCIE-TN1GNDPCIE-RP1PCIE-RN1GND
3GNDPCIE-TP2PCIE-TN2GNDPCIE-RP2PCIE-RN2GND
4GNDPCIE-TP3PCIE-TN3GNDPCIE-RP3PCIERN3GND
5GNDGNDGNDGNDGNDGNDGND
6GNDCLKP0CLKN0GNDRESET-LNCGND
7GNDNCNCNCNCNCGND
8GNDNCNCNCNCNCGND
9GNDGPIO13GPIO16GPIO33GPIO34GPIO56GND
10GNDNCNCGNDNCNCGND
11GNDNCNCGNDNCNCGND
12GNDNCNCNCNCNCGND
13GNDLANBA_100-LLANBB_100-LNCLANBB_1G-LLANBA_1G-LGND
14GNDNCNCGNDSATA-T3PSATA-T3NGND
15GNDNCNCNCSATA-R3PSATA-R3NGND
16GNDMTR0-LINDEX-LRTM_ID1NCDENSEL-LGND
17GNDDIR-LNCRTM_ID2DSEL0-LNCGND
18GNDTRK0-LWGATE-LDETECT-LWDATA-LSTEP-LGND
19GNDDSKCHG-LHDSEL-LNCRDATA-LWRPORT-LGND
20GNDNCNCGNDNCNCGND
21GNDNCNCGNDNCNCGND
22GNDP1V8_LANLANBA_LINKLANBA_ACT#LANBB_LINKLANBB_ACT#GND
Table 4-24: CompactPCI J5 Connector Pin Definition ![PCI-Express x4\nGPIO\nSerial ATA\nFloppy\nEthernet port](.cpci-6920-50-15065-1020-202/c84c6c096e2939f89608df8bcd206a3adcfbba075eb4cc12b9bb54b004169a02.jpg) # 4.12 Switch and Jumper Settings # Reset Switch (SW1) When the Switch SW1 is set to Chassis Reset Enable, a cPCI-6920 SBC installed in a system slot will be reset when the reset button on the front panel is pressed, and all peripheral cards on the CompactPCI bus will be reset. A cPCI-6920 installed in a peripheral slot will not be reset due to isolation from the CompactPCI bus. ![1\n2\nNO](.cpci-6920-50-15065-1020-202/94492151d184183420a12fc6b9007a6971affd59e92bf17561bc1a20e2ea93c1.jpg)
Mode12
Chassis Reset Enable (default)ONOFF
Chassis Reset DisableOFFOFF
Table 4-25: Reset Switch (SW1) Settings # Boot Device Switch (SW3) The Switch SW3 sets the system to boot from the onboard SPI BIOS. The default is setting is ON. ![1\n2\nNO](.cpci-6920-50-15065-1020-202/abe4a0c220adc819b85441e1439a865d8eed6684f14fac798861791274e7d2a8.jpg)
Mode12
Boot by SPI BIOS (Default)ONON
Table 4-26: Boot Device Switch (SW3) Settings ![The image displays a red triangular warning sign with a large white exclamation point in its center. Below the triangle is the text 'WARNING!' in black, uppercase letters.](.cpci-6920-50-15065-1020-202/a30201a4314a00da414e811e3a43055b4407e990d47f57d640247b4b1e4bde97.jpg) Changing this setting may cause the system to fail to boot. # Debugging Switch (SW1-L) The Switch SW1-L is located on the DB-6920L2 adapter board and is reserved for debugging purposes. The default setting is "pin 1 OFF", "pins 2-4 ON". Do not change these settings. ![ON\n1 2 3 4](.cpci-6920-50-15065-1020-202/52b338253332aa66cfb636730345f02d70351c002ab92bd001edcd226af41607.jpg) # COM1 & IPMI Switch (SW2-L) The Switch SW2-L is located on the DB-6920L2 adapter board to set DB-9 port (CN4-L) as a standard RS-232 serial port or IPMI debugging port. ![ON\n1 2 3 4](.cpci-6920-50-15065-1020-202/0909ab5dd3e6e0cc2b44c8314923ee6d5936b043066b47107ff6a10e64d1e85f.jpg)
Mode1234
RS-232 COM port (default)ONONOFFOFF
IPMI debugging portOFFOFFONON
# Clear CMOS (SW5) The cPCI-6920 comes with Clear CMOS switch to reset the CMOS values to default. Press the Switch SW5 located on the solder side near the J1 connector to clear the CMOS. ![Simple diagram showing a black rectangle with a red arrow pointing to its side, no text or symbols present.](.cpci-6920-50-15065-1020-202/11804b989de16754444fcb7400e72d78ba91205c4fce41f2aff63bb9601e9690.jpg) # PICMG 2.16 Switches (SW1-R, SW2-R, SW3-R, SW4-R) The cPCI-R6000(D) supports GbE3 and GbE4 on either the 2.16 backplane or rear I/O. The PICMG® 2.16 backplane and rear I/O cannot be accessed simultaneously. Switches SW1-R to SW4-R must be set to connect GbE3 and GbE4 to either the 2.16 backplane or to the RTM. The following table shows how to set the switches to enable either the 2.16 backplane or RTM for GbE3 and GbE4. All switches are set to ON by default. ![1\n2\n3\n4\nON](.cpci-6920-50-15065-1020-202/dda8f7aedbc13321556532cdb208cffe2f84faa29e09934f90c6c7dcc3b58bbe.jpg) SW1-R ![1\n2\n3\n4\nON](.cpci-6920-50-15065-1020-202/bea5ec88c6ee239121f441b47da5ba63383270c0cf9d8c55ddaaf1f1bc90c487.jpg) SW2-R ![1\n2\n3\n4\nON](.cpci-6920-50-15065-1020-202/ab0f703fcf43b47b8bec3a04e19204974dc367aaba9dc7b29c300b2229fdc91b.jpg) SW3-R ![1\n2\n3\n4\nON](.cpci-6920-50-15065-1020-202/156bdf04840bef0a1108a2a441adb7e22be0b93aa871f5eeb74a6f72714651ee.jpg) SW4-R
Connect GbE3/4 toGbE3(SW1-R, SW2-R)GbE4(SW3-R, SW4-R)
PICMG® 2.16 BackplaneAll OFFAll OFF
Rear faceplate RJ-45 connectors (default)All ONAll ON
# 5 Getting Started This chapter describes the installation of the following components to the cPCI-6920 and rear transition modules: ▶ Memory module ▶ CompactFlash card ▶ 2.5" SATA Hard Drive Disk ▶ CPU module installation to chassis ▶ RTM installation to chassis # 5.1 CPU and Heatsink The 4HP cPCI-6920 supports one Dual/Quad-Core Intel® LV Xeon® processor and the 8HP cPCI-6920D supports up to two Dual/Quad-Core Intel® LV Xeon® processors. The cPCI-6920 Series comes with CPU(s) and heatsink pre-installed. Removal of heatsink/CPU by users is not recommended. Please contact your ADLINK service representative for assistance. # 5.2 Memory Module Installation The cPCI-6920 series supports DDR2-667 registered memory modules with ECC via two SO-RDIMM sockets in the 4HP version and four SO-RDIMM sockets in the 8HP version. The SO-RDIMM modules have a 200-pin footprint and are notched to facilitate correct installation in the SO-RDIMM sockets. # Installing the Memory Modules 1. Install sequence: SO-RDIMM4, SO-RDIMM3, SO-RDIMM2, SO-RDIMM1 in 8HP version (below left) and SO-RDIMM6, SO-RDIMM5 in 4HP version (below right). ![Interior view of an electronic circuit board with multiple CPU and memory chips (no visible text or labels)](.cpci-6920-50-15065-1020-202/466cd00bcf9e4ee56d2ebf42a08490d27f0ec54e2805c2e9b7a1e51f7d906bcd.jpg) ![Close-up of an electronic circuit board with visible components and a red arrow pointing to a specific area (no text or symbols present)](.cpci-6920-50-15065-1020-202/c18aa039c26822e1eff3c0f969cdf322406277a14c1346c48ee49cddafb70131.jpg) 2. Align the notch in the memory module with the key on the SO-RDIMM slot. ![Close-up of a hand holding a green computer motherboard with visible RAM chips and a red circle highlighting a specific chip (no text or symbols present)](.cpci-6920-50-15065-1020-202/3da22f0660973effe049c34620180aa8b6d08780574a4a184c24ae4c38e7fa84.jpg) ![Close-up of a hand pressing a green circuit board with a red circle highlighting a specific component (no visible text or symbols)](.cpci-6920-50-15065-1020-202/6b3e83fa83dfa6f000d0c8130113250d815b395ee8949def621f2e237214f04f.jpg) 3. Press down on the module until is it is properly seated in the socket. ![Close-up of hands installing a green circuit board with multiple RAM chips and a CPU socket (no visible text or symbols)](.cpci-6920-50-15065-1020-202/2f07b3533daca0de5bdc170ee480629d3ceb34961a9a12b80f9e2a52b0342aef.jpg) ![Close-up of a hand inserting a green circuit board into black memory chips (no visible text or symbols)](.cpci-6920-50-15065-1020-202/09d9cd58273c3b0a060b9a67aa3645c7cb4de0fb6e58c661f22fecde3bf8355b.jpg) # 5.3 CompactFlash Card Installation Both 4HP and 8HP versions of the cPCI-6920 are equipped with a removable CompactFlash adapter (DB-6920CF) that provides an internal CF card slot. In the cPCI-R6000D RTM, a DB-CF-SA kit (DB-6920CF adapter card) can be installed for an additional CompactFlash slot. CompactFlash storage is required by some industrial applications for its resistance to vibration and convenient installation/replacement. ![The image displays a white document icon featuring faint horizontal lines and a folded top-right corner. A large, bold red checkmark is superimposed over the document, running diagonally from the bottom left to the top right.](.cpci-6920-50-15065-1020-202/008ba0d58764e1aa5da6b7bcaf2127461b2f3a058f62eebc2bfb425af793bf04.jpg) NOTE: For the 8HP cPCI-6920D, the Layer 2 Adapter (DB-6920L2) must be removed before installing the CompactFlash card. To remove DB-6920L2 adapter, remove the 4x screws and 2x standoffs from the front panel and adapter board as shown below. ![Back view of an electronic computer motherboard with visible CPU socket, ports, and connectors (no text or symbols)](.cpci-6920-50-15065-1020-202/1a6d98a376b12b480a0ae3979474b4280a19f0656cf038f51d2f63beb1f3576b.jpg) # Installing a CF card - cPCI-6920 Series 1. Remove the card retaining bracket from CF adapter by removing the two screws. ![Close-up of a green printed circuit board with a red circle highlighting a component (no visible text or symbols)](.cpci-6920-50-15065-1020-202/ad2df558d7300746837a8d4835feb63f4b0ff41c8f6df92bcf871b37616d0581.jpg) 2. Insert the CF card into the CF slot on the adapter then replace the card retaining bracket to prevent the CF card from sliding out of the slot. ![Close-up of a green computer motherboard with visible CPU socket, RAM slots, and connectors (no readable text or symbols)](.cpci-6920-50-15065-1020-202/3ee71ef30b4f5979249acc4ca5404477a4c784b8e69d818b76d1c786adb30401.jpg) 3. Reinstall the DB-6920L2 adapter as required for the 8HP cPCI-6920D. # Installing a CF card - cPCI-R6000D RTM 1. Remove the Layer 2 Adapter DB-R6000L2 by loosening the 4 screws as shown below. ![Close-up of a green printed circuit board with multiple ports and connectors, marked with red circles highlighting specific components (no readable text or symbols)](.cpci-6920-50-15065-1020-202/17ce549c1b697f7c0fa0deec89a44d69206860453a77fb6d6314e99385f0b09b.jpg) 2. Install the DB-6920CF adapter to the RTM using the board-to-board connector. 3. Secure the DB-6920CF to the RTM using two screws from the solder side of Layer 2 Adapter of RTM. ![Close-up of a green printed circuit board with soldering tools and component highlights (no readable text or symbols)](.cpci-6920-50-15065-1020-202/ec73970773ebafc7bd5123cd243b8e4a2ed7d8def85f9af023ccb3cca98ea8e3.jpg) 4. Reinstall the Layer 2 Adapter to the RTM. 5. Insert the CF card into the CF slot on the adapter, then replace the card retaining bracket to prevent the CF card from sliding out of the slot. ![ComposePlate®](.cpci-6920-50-15065-1020-202/6f97445630f3648532a20ba3f5e73362aedd83acd78ec2b417f68d28acdc9163.jpg) # 5.4 Hard Drive Installation The cPCI-6920 Series provides space to install a slim type 2.5" Serial-ATA hard drive. The DB-SATA adapter kit (DB-6920SAT adapter and standoffs) is included in the package for hard drive installation. Before installing a hard drive, please remove the DB-6920CF adapter from board. The cPCI-R6000D RTM comes with a SATA HDD adapter as standard. ![The image displays a white document icon featuring a folded top-left corner. A large, bold red checkmark is superimposed over the document, which has faint horizontal lines running across the lower portion.](.cpci-6920-50-15065-1020-202/74ff11c00115034f8f4a883771bd178ab64d5f26eddf8811ed43b1431940dafb.jpg) NOTE: For the 8HP cPCI-6920D, the Layer 2 Adapter (DB-6920L2) must be removed before installing hard drive as described in Section 5.3 CompactFlash Card Installation above. # Installing a Hard Drive - cPCI-6920 Series 1. Attach the four standoffs provided with the DB-SATA adapter kit onto the SATA hard drive as shown below. ![Green hard disk computer with four red-circled mounting points and a QR code on the circuit (no readable text or symbols)](.cpci-6920-50-15065-1020-202/b07a028563282dd61d8285c6bb0824f173503703e1ffbc0d920ae99692eb8081.jpg) 2. Attach the DB-6920SAT adapter board to the hard drive connectors. ![CATA\n©CEC\nM-2000\nW-1800\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G](.cpci-6920-50-15065-1020-202/b166f6975b6dd309b0e91f4e9e268c225fa8f1dc0064130a78a02af329700b58.jpg) 3. Position the hard drive assembly on the cPCI-6920 so that the standoffs on the hard drive align with the screw holes on the board, and the connector on the DB-6920SAT adapter board is aligned with the board-to-board connector (CN6). 4. Press the DB-6920SAT adapter to the board-to-board connector until it is properly seated. Secure the adapter to the board with the two screws provided. ![T₃\nN1000M 1815 T\nLBS\nR2000M\nGIBAL\nHOLD\nSINCH\nP/N: D426142 M.C: D41166\n11000071 J6HEADS 6300C71](.cpci-6920-50-15065-1020-202/7fdb56209b7d877d3f2491ed1bb1c3e806f635c442593d5ca8bfc5695f2461e8.jpg) 5. Secure the hard drive with four screws from the board's solder side. ![Close-up of a green printed circuit board with multiple circular annotations highlighting specific components (no readable text or symbols)](.cpci-6920-50-15065-1020-202/ade9feee08d928b9df659583e9ccf8d41fbc10d5402382df562ae123fdec820d.jpg) 6. Reinstall the DB-6920L2 adapter as required for the 8HP cPCI-6920D. ![The image displays a standard safety warning sign. It features a yellow triangle with a black border containing a black exclamation point in the center. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.cpci-6920-50-15065-1020-202/a69d7da0bae27e3e8d7b41e15b5a3f4eef3e0d2ee661f36a07dad266285826e7.jpg) When removing the hard drive, be careful to grasp the adapter board and lift upwards in a vertical motion to disconnect it from the board-to-board connector. This will avoid damaging the adapter board and connectors. # Installing a Hard Drive - cPCI-R6000D RTM 1. Attach the DB-6920SAT adapter board to the hard drive connectors. ![CATA\n©CEC\nM-2000\nW-1800\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5V 1.5V\n1.5V 1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G\n1.5G](.cpci-6920-50-15065-1020-202/fed4d81d10bb2d4ef62c2152a06822c7e4b97bfc5222742bdfb6257cf91afc22.jpg) 2. Screw the hard drive to the bracket provided as shown. ![HITACHI\nTravelstar™\n2017-03-04 00:00:58\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA\nSATA](.cpci-6920-50-15065-1020-202/7090c043b64fc6c0b5a5bba85776618787455d25d8039a7655dd3bd20730fb75.jpg) 3. Align the hard drive and bracket assembly with the board-to-board connector and standoffs and press down until it is properly seated. Secure the adapter and hard drive with 6x screws as shown. ![403030161\n烧杯专用\nSTABRITTEAM\nTALAWAR\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHU\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUMA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUIA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINHUA\nSINNHAUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANUANU(nl)](.cpci-6920-50-15065-1020-202/1a491a880420454bcb0b8baacac54151b0f5ec5f06737f1e0e5b83f81a2d242a.jpg) # 5.5 Installing the cPCI-6920 to the Chassis The cPCI-6920 may be installed in a system or peripheral slot of a 6U CompactPCI chassis. These instructions are for reference only. Refer to the user guide that comes with the chassis for more information. 1. Be sure to select the correct slot depending on the operational purpose of the module. The system power may now be powered on or off. 2. Remove the blank face cover from the selected slot, if necessary. 3. Press down on the release catches of the cPCI-6920 ejector handles. 4. Remove the black plastic caps securing the mounting screws to the front panel. 5. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are bent pins on the backplane or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis. 6. Push the ejector handles outwards to secure the module in place, and then fasten the screws on the module front panel. 7. Connect the cables and peripherals to the board, and then turn the chassis on if necessary. # 5.6 RTM (cPCI-R6000) Installation The installation and removal procedures for a RTM are the same as those for CompactPCI boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs. Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the cPCI-6920 Series and related RTMs, make sure the RTM is the correct matching model. ![The image displays a white document icon with horizontal lines suggesting text and a folded top-left corner. A large red checkmark is superimposed diagonally across the center of the document.](.cpci-6920-50-15065-1020-202/dc0ad35b2f85692298c07c98965b9056d9482e0c728ff184ec4b64996aa213cb.jpg) NOTE: You must install the correct RTM to enable functions (I/O interfaces) on the rear panel. Installation of non-compatible RTMs may damage the system board and/or other RTMs. # 6 Driver Installation The cPCI-6920 drivers are available from the ADLINK All-In-One CD at X:\cPCI\cPCI-6920\, or from the ADLINK website (http://www.adlinktech.com). The following describes the driver installation procedures for Windows® XP and Windows® Server 2003: 1. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation. 2. Install the chipset driver by running the program ...\Chipset\Inflnst\_AUTOL\_8.6.0.1006.exe. 3. Install the VGA driver and utilities. Refer to Section 6.1 for details on how to install the VGA driver in Windows® operating systems. 4. Install the LAN drivers by running the program ...\LAN\PRO2KXP\_13.exe. 5. Install the SCSI driver for RTM cPCI-R6000(D) if required. Refer to Section 6.2. We recommend using the drivers provided on the ADLINK All-in-One CD or downloaded from the ADLINK website to ensure compatibility. Contact ADLINK to get support for VxWorks BSP drivers. # 6.1 Installing the VGA Driver 1. Click Start, right-click on My Computer, then select Properties from the drop-down menu. 2. Click on the Hardware tab, then click Device Manager. 3. Right-click on the Video Controller (VGA Compatible) item, then click Properties from the drop-down menu. 4. From the General tab, click Reinstall Driver. 5. Click Next when the Upgrade Device Driver Wizard window appears. 6. Select Search for a suitable driver for my device (recommended), then click Next. 7. Check the Specify a location option, and then click Next. 8. When prompted to locate the file, click Browse, then select the C2\_29263.inf from this directory on the ADLINK All-In-One CD: ...\VGA\2KXP\_INF\. 9. When the file is found, click OK, then click Next. 10. Follow screen procedures to install the drivers, and then restart the system to complete installation. # 6.2 Installing the SCSI Driver The SCSI driver installation procedure for Windows XP is described as below. It is not necessary to install the SCSI driver on Windows 2003 Server as it has a built-in driver. 1. Click Start, right-click on My Computer, then select Properties from the drop-down menu. 2. Click on the Hardware tab, then click Device Manager. 3. Right-click on the Video Controller (VGA Compatible) item, then click Properties from the drop-down menu. 4. From the General tab, click Reinstall Driver. 5. Select Yes, this time only and click Next when the Upgrade Device Driver Wizard window appears. 6. Select Install from a list on specific location [Advanced], then click Next. 7. Uncheck Search removable media [floppy, CD-ROM...], and check Include this location in the search:, then click Browse. 8. Select the xp\_x86 folder from this directory on the ADLINK All-In-One CD: ...X:\cPCI\cPCI-6920\SCSI. 9. Click OK, then click Next. 10. Click Continue Anyway to go on, and click Finish to complete the installation. This page intentionally left blank. # 7 Utilities # 7.1 Watchdog Timer This section describes the operation of the cPCI-6920's watchdog timer (WDT). The primary function of the WDT is to monitor the cPCI-6920's operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application: ▶ enabling and disabling ▶ reloading timeout value The cPCI-6920 custom WDT circuit is implemented using the internal IO of the Winbond SuperIO W83627UHG which is at 2Eh of LPC. The basic functions of the WDT include: ▶ Starting the timer countdown ▶ Enabling or disabling WDT ▶ Enabling or disabling WDT countdown LED ON ▶ Reloading the timeout value to keep the watchdog from timing out ▶ Setting the range of the timeout period from 1 to 15300 seconds ▶ Sending a RESET signal to the system when the watchdog times out # Using the Watchdog in an Application The following section describes using the WDT functions in an application. The WDT reset function is explained in the previous section. This can be controlled through the registers in the cPCI-6920's SuperIO. An application using the reset feature enables the watchdog function, sets the count-down period, and reloads the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after its counter reaches zero. ADLINK provides a demo DOS utility in the ADLINK All-In-One CD. You can find it in the following directory: X:\cPCI\cPCI-6920\WDT. # Sample Code The sample program written in C shown below offers an interactive way to test the Watchdog Timer under DOS. ```c #include<stdio.h> #include<dos.h> static unsigned int W83627UHG_ioPort = 0x2e; void Enter_W83627UHG_Config(unsigned int flag) { if(flag) W83627UHG_ioPort = 0x4e; outportb(W83627UHG_ioPort, 0x87); outportb(W83627UHG_ioPort, 0x87); } void Get_W83627UHG_ID(unsigned int &ID1, unsigned int &ID2) { outportb(W83627UHG_ioPort, 0x20); ID1 = inportb(W83627UHG_ioPort+1); outportb(W83627UHG_ioPort, 0x21); ID2 = inportb(W83627UHG_ioPort+1); } void W83627UHG_WDT_Run(unsigned int count_value, unsigned int PLEDflag) { unsigned int tempCount, registerValue; outportb(W83627UHG_ioPort, 0x07); outportb(W83627UHG_ioPort+1, 8); // CR07 set Logical Device 8 if(count_value >= 60) { outportb(W83627UHG_ioPort, 0xf5); registerValue = inportb(W83627UHG_ioPort+1); registerValue |= 0x04; outportb(W83627UHG_ioPort+1, registerValue); // set Minute mode ``` ```txt tempCount = count_value / 60; if((count_value%60) > 30) tempCount++; if(tempCount > 255) tempCount = 255; printf("WDT timeout in %d minutes.\n", tempCount); } else { outportb(W83627UHG_ioPort, 0xf5); registerValue = importb(W83627UHG_ioPort+1); registerValue &= 0xfb; outportb(W83627UHG_ioPort+1, registerValue); / / set second mode tempCount = count_value; } if(tempCount) { outportb(W83627UHG_ioPort, 0x30); registerValue = importb(W83627UHG_ioPort+1); registerValue |= 0x01; outportb(W83627UHG_ioPort+1, registerValue); / / set WDTO# and PLED are active. outportb(W83627UHG_ioPort, 0xf5); registerValue = importb(W83627UHG_ioPort+1); registerValue |= 0x02; outportb(W83627UHG_ioPort+1, registerValue); / / Enable KCB reset. if(PLEDflag) { outportb(W83627UHG_ioPort, 0x07); outportb(W83627UHG_ioPort+1, 9); // CR07 set Logical Device 9 outportb(W83627UHG_ioPort, 0x30); registerValue = importb(W83627UHG_ioPort+1); ``` ```txt registerValue |= 0x02; // set GPIO2 is active outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe4); registerValue = inportb(W83627UHG_ioPort+1); registerValue &= 0xf7; // set GPIO23 is output function outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe5); registerValue = inportb(W83627UHG_ioPort+1); registerValue &= 0xf7; // set GPIO23 is Low outportb(W83627UHG_ioPort+1, registerValue); } printf("WDT timeout in %d seconds.\n", tempCount); } else { outportb(W83627UHG_ioPort, 0x07); outportb(W83627UHG_ioPort+1, 9); // CR07 set Logical Device 9 outportb(W83627UHG_ioPort, 0x30); registerValue = inportb(W83627UHG_ioPort+1); registerValue |= 0x02; // set GPIO2 is active outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe4); registerValue = inportb(W83627UHG_ioPort+1); registerValue &= 0xf7; // set GPIO23 is output function outportb(W83627UHG_ioPort+1, registerValue); outportb(W83627UHG_ioPort, 0xe5); ``` ```c registerValue = importb(W83627UHG_ioPort+1); registerValue |= 0x08; // set GPIO23 is High outportb(W83627UHG_ioPort+1, registerValue); printf("WDT is Disabled.\n"); } outportb(W83627UHG_ioPort, 0x07); outportb(W83627UHG_ioPort+1, 8); // CR07 set Logical Device 8; outportb(W83627UHG_ioPort, 0xf6); outportb(W83627UHG_ioPort+1, tempCount); // set WDT count value.. } void Exit_W83627UHG_Config(unsigned int flag) { if(flag) W83627UHG_ioPort = 0x4e; outportb(W83627UHG_ioPort, 0xaa); ``` # 7.2 Preboot Execution Environment (PXE) The cPCI-6920 series supports the Intel® Preboot Execution Environment (PXE) that is capable of booting up or executing an OS installation through an Ethernet ports. To use PXE, there must be a DHCP server on the network with one or more servers running PXE and MTFTP services. It could be a Windows® 2003 server running DHCP, PXE, and MTFTP services or a dedicated DHCP server with one or more additional servers running PXE and MTFTP services. To build a network environment with PXE support: 1. Setup a DHCP server with PXE tag configuration 2. Install the PXE and MTFTP services 3. Make a boot image file on the PXE server (i.e. the boot server) 4. Enable the PXE boot function on the client computer # 8 BIOS Setup The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility. # 8.1 Starting the BIOS To enter the setup screen, follow these steps: 1. Power on the motherboard 2. Press the < Delete > key on your keyboard when you see the following text prompt: < Press DEL to run Setup > 3. After you press the <Delete> key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu, such as Chipset and Power menus. ![American\nMegatrends\nwww.ami.com\nAMIBIOS (C) 2002 American Megatrends, Inc.\nBIOS Date: 10/08/07 12:39:39 Ver: 08.00.04\nIntel(R) Celeron(R) M Processor\nPress DEL to run Setup\nChecking NURAM..\nUSB Device(s): 2 Keyboards, 2 Mice, 1 Hub, 1 Storage Device\n1024MB OK\nAuto-Detecting Pri Master..IDE Hard Disk\nAuto-Detecting Pri Slave...ATAPI CDROM\nPri Master: 3.20 ST3B410A 007A](.cpci-6920-50-15065-1020-202/bdb1cc8cf9d44500fa5ad550dab09aa89b222499be6c5af2f29cf58fc2f80c43.jpg) Note: In most cases, the <Delete> key is used to invoke the setup screen. There are several cases that use other keys, such as <F1>, <F2>, and so on. # Setup Menu The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide. The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be. The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.
BIOS SETUP UTILITY
MainAdvancedPCIPnPBootSecurityChipset Exit
System OverviewUse [ENTER], [TAB]or [SHIFT-TAB] toselect a field.Use [+] or [-] toconfigure system Time.
AMIBIOS
Version :08.00.15Build Date:09/23/08ID :CP692000
Processor
Speed :255MHzCount :255
System MemorySize :512MB← Select Screen↑↓ Select Item+- Change FieldTab Select FieldF1 General HelpF10 Save and ExitESC Exit
System Time [04:50:52]System Date [Tue 01/01/2002]
# Navigation The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process. These keys include <F1>, <F10>, <Enter>, <ESC>, <Arrow> keys, and so on. ![This flowchart diagram describes the navigation structure of a BIOS Setup Utility.\n\n**Blocks and Labels:**\n* **BIOS Setup Utility** (Top center box)\n* **Screens** (Text label)\n* **Left and Right Keys to Select a Setup Screen** (Left box)\n* **Screen 1**, **Screen 2**, **Screen 3**, **Screen 4**, **Screen 5** (Horizontal row of boxes)\n* **Items** (Text label)\n* **Tab Key to Select Fields** (Left box)\n* **Fields** (Text label)\n* **+ To Change Field Values** (Right box)\n* **Up and Down Keys to Select a Setup Item** (Right box)\n* Three boxes containing a plus sign (+) in the 'Items' row.\n* Three boxes containing a plus sign (+) in the bottom row.\n\n**Connections:**\n1. **BIOS Setup Utility** connects via a downward arrow to the text **Screens**.\n2. **Left and Right Keys to Select a Setup Screen** connects via a dashed arrow to the row of screens.\n3. The screen boxes are connected horizontally by double-headed arrows: **Screen 1** \$\leftrightarrow\$ **Screen 2** \$\leftrightarrow\$ **Screen 3** \$\leftrightarrow\$ **Screen 4** \$\leftrightarrow\$ **Screen 5**.\n4. An arrow points downward from the screen row to the text **Items**.\n5. **Tab Key to Select Fields** connects via a dashed arrow to the first box in the **Items** row.\n6. The three boxes in the **Items** row are connected horizontally by double-headed arrows.\n7. **+ To Change Field Values** connects via a dashed arrow to the middle box in the **Items** row.\n8. Between the **Items** row and the bottom row, there are vertical arrows pointing down and up.\n9. **Up and Down Keys to Select a Setup Item** connects via a dashed arrow to these vertical arrows.\n10. The text **Fields** is positioned to the left of the bottom row and connected to it via a bracket.\n11. The bottom row of three boxes (containing plus signs) is connected horizontally by double-headed arrows.](.cpci-6920-50-15065-1020-202/20b1c6c7ed5f05b65db20636cd4bc1d067e10db3d772a715b14bf802b3d036f2.jpg) Note: There is a hot key legend located in the right frame on most setup screens. The < F8 > key on your keyboard is the Fail-Safe key. It is not displayed on the key legend by default. To set the Fail-Safe settings of the BIOS, press the < F8 > key on your keyboard. It is located on the upper row of a standard 101 keyboard. The Fail-Safe settings allow the motherboard to boot up with the least amount of options set. This can lessen the probability of conflicting settings. # Hotkey Descriptions F1 The < F1 > key allows you to display the General Help screen. Press the < F1 > key to open the General Help screen.
General Help
←→Select Screen↓↑Select Item
+-Change ScreenEnterGo to Sub Screen
PGDNNext PagePGUPPrevious Page
HomeGo to Top of the ScreenEndGo to Bottom of Screen
F2/F3Change ColorsF7Discard Changes
F8Load Failsafe DefaultsF9Load Optimal Defaults
F10Save and ExitESCExit
[Ok]
F10 The < F10 > key allows you to save any changes you have made and exit Setup. Press the < F10 > key to save your changes. The following screen will appear:
Save configuration changes and exit now?
[Ok][Cancel]
Press the <Enter> key to save the configuration and exit. You can also use the <Arrow> key to select Cancel and then press the <Enter> key to abort this function and return to the previous screen. ESC The < Esc > key allows you to discard any changes you have made and exit the Setup. Press the < Esc > key to exit the setup without saving your changes. The following screen will appear:
Discard changes and exit setup now?
[Ok][Cancel]
Press the <Enter> key to discard changes and exit. You can also use the <Arrow> key to select Cancel and then press the <Enter> key to abort this function and return to the previous screen. Enter The < Enter > key allows you to display or change the setup option listed for a particular setup item. The < Enter > key can also allow you to display the setup sub-screens. # 8.2 Main Setup When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. There are two Main Setup options. They are described in this section. The Main BIOS Setup screen is shown below.
BIOS SETUP UTILITY
MainAdvancedPCIPnPBootSecurityChipset Exit
System OverviewUse [ENTER], [TAB] or [SHIFT-TAB] to select a field.
AMIBIOS
Version :08.00.15
Build Date:09/23/08Use [+] or [-] to configure system Time.
ID :CP692000
Processor
Speed :255MHz
Count :255
System Memory← Select Screen ↑↓ Select Item +- Change Field Tab Select Field F1 General Help F10 Save and Exit ESC Exit
Size :512MB
System Time [04:50:52] System Date [Tue 01/01/2002]
# System Time/System Date Use this option to change the system time and date. Highlight System Time or System Date using the <Arrow> keys. Enter new values using the keyboard. Press the <Tab> key or the <Arrow> keys to move between fields. The date must be entered in MM/DD/YY format. The time is entered in HH:MM:SS format. Note: The time is in 24-hour format. For example, 5:30 A.M. appears as 05:30:00, and 5:30 P.M. as 17:30:00. # 8.3 Advanced BIOS Setup Select the Advanced tab from the setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the <Arrow> keys. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages.
BIOS SETUP UTILITY
Main Advanced PCIPnP Boot Security Chipset Exit
Advanced SettingsWARNING: Setting wrong values in below sections may cause system to malfunction.CPU ConfigurationIDE ConfigurationFloppy ConfigurationSuperIO ConfigurationHardware Health ConfigurationUSB ConfigurationAHCI ConfigurationRemote Access ConfigurationConfigure CPU.Select Screen↑↓ Select ItemEnter Go to Sub ScreenF1 General HelpF10 Save and ExitESC Exit
# 8.3.1 CPU Configuration You can use this screen to select options for the CPU Configuration Settings. Use the up and down <Arrow> keys to select an item. Use the <+> and <-> keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the CPU Configuration screen is shown below.
BIOS SETUP UTILITY
Configure advanced CPU settings Module Version:3F.09Disable: Disable GU3 Enable: Enable GU3
Manufacturer:Intel
Frequency :255MHz FSB Speed :127MHz Cache L1 :0 KB Cache L2 :0 KB Ratio Status:Unlocked (Min:06, Max:08) Ratio Actual Value:8
Hardware Prefetcher [Enabled]← Select Screen ↑↓ Select Item +- Change Option
Adjacent Cache Line Prefetch [Enabled]
Max CPUID Value Limit [Disabled]
Intel(R) Virtualization Tech [Enabled]F1 General Help
Execute-Disable Bit Capability [Enabled]F10 Save and Exit
Core Multi-Processing [Enabled]ESC Exit
PECI [Disabled]
Intel(R) SpeedStep(tm) tech [Disabled]
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Hardware Prefetcher When enabled, the processor's hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor. When disabled, the processor's hardware prefetcher will be disabled. # Adjacent Cache Line Prefetch When enabled, the processor will retrieve the currently requested cache line, as well as the subsequent cache line. When disabled, the processor will only retrieve the currently requested cache line. # Max CPUID Value Limit When the computer is booted up, the operating system executes the CPUID instruction to identify the processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input value CPUID recognized. This determines the kind of basic information CPUID can provide the operating system. This option allows you to circumvent problems with older operating systems. When Enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When Disabled, the processor will return the actual maximum CPUID input value of the processor when queried. # Intel(R) Virtualization Tech Intel Virtualization Technology is a set of platform features that support virtualization of platform hardware and multiple software environments. When enabled, it offers data center managers the ability to consolidate multiple workloads on one physical server system. # Execute-Disable Bit Capability Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempt to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation. # Core Multi-Processing This item enables/disables multi-core processing functionality for multi-core processors. # PECI Enables/disables the Platform Environment Control Interface (PECI). # Intel(R) Speedstep(tm) Tech Intel SpeedStep technology allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production. # 8.3.2 IDE Configuration You can use this screen to select options for the IDE Configuration Settings. Use the up and down <Arrow> keys to select an item. Use the <+> and <-> keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the IDE Configuration screen is shown below.
IDE ConfigurationOptions
SATA#1 Configuration Configure SATA#1 as[Compatible] [IDE]Disabled Compatible Enhanced
► Primary IDE Master: [Not Detected]
► Primary IDE Slave: [Not Detected]
► Secondary IDE Master: [Not Detected]
► Secondary IDE Slave: [Not Detected]
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
# SATA#1 Configuration This item specifies which mode the SATA channels should be initialized in. The settings are Disabled, Compatible and Enhanced. When running in Compatible mode, SATA channel can be configured as a legacy IDE channel. # IDE Master/Slave Select one of the hard disk drives to configure it. Press <Enter> to access its sub menu. # 8.3.3 Floppy Configuration You can use this screen to select options for the Floppy Configuration Settings. Use the up and down <Arrow> keys to select an item. Use the <+> and <-> keys to change the value of the selected option. A description of the selected item appears on the right side of the screen. The settings are described on the following pages. An example of the Floppy Configuration screen is shown below.
BIOS SETUP UTILITY
Advanced
Floppy ConfigurationSelect the type offloppy driveconnected to thesystem.
Floppy A [1.44 MB 3 $\frac{1}{2}$ "]
← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
Options: 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3 1/2", 1.44 MB 3 1/2", 2.88 MB 3 1/2". # 8.3.4 Super IO Configuration You can use this screen to select options for the Super IO settings. Use the up and down <Arrow> keys to select an item. Use the <+> and <-> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
BIOS SETUP UTILITY Advanced
Configure Win627UHG Super IO Chipset
UART1 to FRONT PANEL [Enabled] UART2 to REAR [Enabled] UART3 to IPMC [Enabled] UART4 to REAR [Enabled] OnBoard Floppy Controller [Enabled]Allows BIOS to Select Serial Port Base Addresses.
← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# UART1 to FRONT PANEL This option sets the UART1 to the Front Panel. ▶ Disabled: Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable. ▶ Enabled: Set this value to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for the interrupt address. # UART2 to REAR This option sets the UART2 to Rear I/O. ▶ Disabled: Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable. ▶ Enabled: Set this value to allow the serial port to use 2F8 as its I/O port address and IRQ 10 for the interrupt address. # UART3 to IPMC This option sets the UART3 to IPMC. ▶ Disabled: Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable. ▶ Enabled: Set this value to allow the serial port to use 3E8 as its I/O port address and IRQ 3 for the interrupt address. # UART4 to REAR This option sets the UART4 to Rear I/O. ▶ Disabled: Set this value to prevent the serial port from accessing any system resources. When this option is set to Disabled, the serial port physically becomes unavailable. ▶ Enabled: Set this value to allow the serial port to use 2E8 as its I/O port address and IRQ 11 for the interrupt address. # 8.3.5 Hardware Health Configuration This option displays the current status of all of the monitored hardware devices/components such as voltages and temperatures. The options are Enabled and Disabled.
BIOS SETUP UTILITY
Advanced
H/W Health Function[Enabled]Enables HardwareHealth MonitoringDevice.
Module CPU Temperature Reading :66°C/150°F
VCORE:1.135 V
+3.30V:3.206 V
+1.8V:1.840 V
+5V:4.812 V
+12V:12.090 V
← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# 8.3.6 USB Configuration You can use this screen to select options for the USB Configuration. Use the up and down <Arrow> keys to select an item. Use the <+> and <-> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below.
USB Configuration Module Version - 2.24.3-13.4 USB Devices Enabled: 1 Drive Legacy USB Support [Enabled] Port 64/60 Emulation [Disabled] USB 2.0 Controller Mode [HiSpeed] BIOS EHCI Hand-Off [Enabled]Enables support for legacy USB. AUTO option disables legacy support if no USB devices are connected. ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit
►USB Mass Storage Device Configuration
# Legacy USB Support Legacy USB Support refers to USB mouse and keyboard support. Normally if this option is not enabled, any attached USB mouse or USB keyboard will not become available until a USB compatible operating system is fully booted with all USB drivers loaded. When this option is enabled, any attached USB mouse or USB keyboard can control the system even when there are no USB drivers loaded on the system. Set this value to enable or disable the Legacy USB Support. ▶ Disabled: Set this value to prevent the use of any USB device in DOS or during system boot. ▶ Enabled: Set this value to allow the use of USB devices during boot and while using DOS. ▶ Auto: This option auto detects USB Keyboards or Mice and if found, allows them to be utilized during boot and while using DOS. # Port 64/60 Emulation This option uses USB to receive the IO port 64/60 trap to emulate the legacy keyboard controller. # USB 2.0 Controller Mode The USB 2.0 Controller Mode configures the data rate of the USB port. The options are FullSpeed (12 Mbps) and HiSpeed (480 Mbps). # BIOS EHCI hand-off This option provides a workaround for operating systems without ECHI hand-off support. The EHCI ownership change should claim by EHCI driver. # USB Mass Storage Device Configuration This is a submenu for configuring the USB Mass Storage Class Devices when BIOS finds they are in use on USB ports. Emulation Type can be set according to the type of attached USB mass storage device(s). If set to Auto, USB devices less than 530MB will be emulated as Floppy and those greater than 530MB will remain as hard drive. The Forced FDD option can be used to force a hard disk type drive (such as a Zip drive) to boot as FDD.
BIOS SETUP UTILITY
Advanced
USB Mass Storage Device ConfigurationUSB Mass Storage Reset Delay [20 Sec]Device #1 Generic STORAGE DEVICEEmulation Type [Auto]If Auto, USB devices less than 530MB will be emulated as Floppy and remaining as hard drive. Forced FDD option can be used to force a HDD formatted drive to boot as FDD (Ex. ZIP drive).← Select Screen↑↓ Select Item+- Change OptionF1 General HelpF10 Save and ExitESC Exit
# 8.3.7 AHCI Configuration Select the Advanced tab from the setup screen to enter the AHCI Configuration Setup screen. You can display the AHCI Setup options by highlighting it using the <Arrow> keys. ![BIOS SETUP UTILITY\nAdvanced\nAHCI Settings\n▶ AHCI Port0 (Not Detected)\n▶ AHCI Port1 (Not Detected)\n▶ AHCI Port2 (Not Detected)\n▶ AHCI Port3 (Not Detected)\nWhile entering setup,\nBIOS auto detects the\npresence of IDE\ndevices. This displays\nthe status of auto\ndetection of IDE\ndevices.](.cpci-6920-50-15065-1020-202/744207233db12dda6eeb2601b46f1efcc4a5f4cd8248594ccde3bdf6b7b3af58.jpg) ![BIOS SETUP UTILITY\nAdvanced\nAHCI Port0\nDevice :Not Detected\nSATA Port0 (Auto)\nS.M.A.R.T. (Enabled)\nSelect the type\nof device connected\nto the system.](.cpci-6920-50-15065-1020-202/aa40516547163f6066b2a734c220282de7b5e71dc5c55ca8787e2757047becfe.jpg) # SATA Port0/1/2/3 Select the type of device connected to the system. # S.M.A.R.T S.M.A.R.T. (Self-Monitoring Analysis and Reporting Technology) is a utility that monitors your disk status to predict hard disk failure. # 8.3.8 Remote Access Configuration Remote access configuration provides the settings to allow remote access by another computer to get POST messages and send commands through serial port access.
BIOS SETUP UTILITY
Advanced
Configure Remote Access type and parameters
Remote Access[Enabled]
Serial port number[COM1]
Base Address, IRQ[3F8h, 4]
Serial Port Mode[115200 8,n,1]
Flow Control[None]
Redirection After BIOS POST[Always]
Terminal Type[ANSI]
UT-UTF8 Combo Key Support[Enabled]
Sredir Memory Display Delay[No Delay]
# Remote Access Select this option to Enable or Disable the BIOS remote access feature. Note: Enabling Remote Access requires a dedicated serial port connection. Once both serial ports are configured to disabled, you should set this value to Disabled or it may cause abnormal boot. # Serial Port Number Select the serial port you want to use for the remote access interface. You can set the value for this option to COM1, COM2 or COM4. Note: If you have changed the resource assignment of the serial ports in Advanced> SuperIO Configuration, you must Save Changes and Exit, reboot the system, and enter the setup menu again in order to see those changes reflected in the available Remote Access options. # Serial Port Mode Select the baud rate you want the serial port to use for console redirection. The options are 115200 8,n,1; 57600 8,n,1; 19200 8,n,1; and 09600 8,n,1. # Flow Control Set this option to select Flow Control for console redirection. The settings for this value are None, Hardware, or Software. # Redirection After BIOS POST This option allows you to set Redirection configuration after BIOS POST. The settings for this value are Disabled, Boot Loader, or Always. ▶ Disabled: Set this value to turn off the redirection after POST ▶ Boot Loader: Set this value to allow the redirection to be active during POST and Boot Loader. ▶ Always: Set this value to allow the redirection to be always active. # Terminal Type This option is used to select either VT100/VT-UTF8 or ANSI terminal type. The settings for this value are ANSI, VT100, or VT-UTF8. # VT-UTF8 Combo Key Support This option enables VT-UTF8 Combination Key Support for ANSI/VT100 terminals. The settings for this value are Enabled or Disabled. # Sredir Memory Display Delay This option gives the delay in seconds to display memory information. The options for this value are No Delay, Delay 1 Sec, Delay 2 Sec, or Delay 4 Sec. # 8.4 Advanced PCI/PnP Settings Select the PCI/PnP tab from the setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the <Arrow> keys. The Plug and Play BIOS Setup screen is shown below.
BIOS SETUP UTILITY
MainAdvancedPCIPnPBootSecurityChipset Exit
Advanced PCI/PnP SettingsClear NURAM during System Boot.
WARNING: Setting wrong values in below sections may cause system to malfunction.
Clear NURAM[No]
Plug & Play O/S[No]
PCI Latency Timer[64]
IRQ3[Available]
IRQ4[Available]
IRQ5[Available]
IRQ7[Available]← Select Screen
IRQ9[Available]↑↓ Select Item
IRQ10[Available]+- Change Option
IRQ11[Available]F1 General Help
IRQ14[Available]F10 Save and Exit
IRQ15[Available]ESC Exit
# Clear NVRAM Set this to enable/disable Clear NVRAM during system boot # Plug & Play O/S ▶ No: Let the BIOS configure all the devices in the system. ▶ Yes: Let the operating system configure Plug and Play (PnP) devices not required for boot if your system has a Plug and Play operating system. # PCI Latency Timer Value in units of PCI clocks for the PCI device latency timer register. # IRQ Channel Set this value to allow the IRQ/DMA channel settings to be modified. ▶ Available: This setting allows the specified IRQ/DMA channel to be used by a PCI/PnP device. ▶ Reserved: This setting allows the specified IRQ/DMA channel to be used by a legacy ISA device. # 8.5 Boot Settings Select the Boot tab from the setup screen to enter the Boot BIOS Setup screen. You can select any of the items in the left frame of the screen, such as Boot Device Priority, to go to the sub menu for that item. You can display a Boot BIOS Setup option by highlighting it using the <Arrow> keys. The Boot Settings screen is shown below: ![BIOS SETUP UTILITY\nMain Advanced PCIPnP Boot Security Chipset Exit\nBoot Settings\n► Boot Settings Configuration\n► Boot Device Priority\n► Removable Drives\nConfigure Settings\nduring System Boot.\n← Select Screen\n↑↓ Select Item\nEnter Go to Sub Screen\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.cpci-6920-50-15065-1020-202/8c7b00814c4f8ee0c46bb3faa44a47eb8ecb9e84fb5d79a9e562f8846b44703d.jpg) # 8.5.1 Boot Settings Configuration Use this screen to select options for the Boot Settings Configuration. Use the up and down <Arrow> keys to select an item. Use the <Plus> and <Minus> keys to change the value of the selected option. The settings are described on the following pages. The screen is shown below. # BIOS SETUP UTILITY # Boot # Boot Settings Configuration Quick Boot Quiet Boot Bootup Num-Lock [Enabled] [Disabled] [On] Allows BIOS to skip certain tests while booting. This will decrease the time needed to boot the system. ← Select Screen ↑↓ Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit v02.61 (C) Copyright 1985-2006, American Megatrends, Inc. # Quick Boot Enabling this setting will cause the BIOS power-on self test routine to skip some of its tests during bootup for faster system boot. # Quiet Boot When this feature is enabled, the BIOS will display the OEM logo during the boot-up sequence, hiding normal POST messages. When it is disabled, the BIOS will display the normal POST messages, instead of the OEM logo. # Bootup Num-Lock This option sets the Num Lock status when the system is powered on. Setting to [On] will turn on the Num Lock key when the system is powered on. Setting to [Off] will allow users to use the arrow keys on the numeric keypad. # 8.5.2 Boot Device Priority The items allow you to set the sequence of boot devices where BIOS attempts to load the disk operating system. First press <Enter> to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or <PageUp>, <PageDown> key to move it up/down in the priority list. # 8.5.3 Boot Device Groups The Boot devices are listed in groups by device type. First press <Enter> to enter the sub-menu. Then you may use the arrow keys to select the desired device, then press <+>, <-> or <PageUp>, <PageDown> key to move it up/down in the priority list. Only the first device in each device group will be available for selection in the Boot Device Priority option. # 8.6 Security Setup
BIOS SETUP UTILITY
MainAdvancedPCIPnPBootSecurityChipsetExit
Security SettingsInstall or Change the password.
Supervisor Password :Not InstalledUser Password :Not InstalledChange Supervisor PasswordChange User PasswordClear User Password
← Select Screen↑↓ Select ItemEnter ChangeF1 General HelpF10 Save and ExitESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc. # Password Support # Two Levels of Password Protection Provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password. The Supervisor and User passwords activate two different levels of password security. If you select password support, you are prompted for a one to six character password. Type the password on the keyboard. The password does not appear on the screen when typed. Make sure you write it down. If you forget it, you must drain NVRAM and re-configure. # Remember the Password Keep a record of the new password when the password is changed. If you forget the password, you must erase the system configuration information in NVRAM. To access the sub menu for the following items, select the item and press < Enter>: ▶ Change Supervisor Password ▶ Change User Password ▶ Clear User Password # Supervisor Password Indicates whether a supervisor password has been set. # User Password Indicates whether a user password has been set. # Change Supervisor Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the supervisor password. # Change User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to change the user password. # Clear User Password Select this option and press < Enter > to access the sub menu. You can use the sub menu to clear the user password. # Change Supervisor Password Select Change Supervisor Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes. # Change User Password Select Change User Password from the Security Setup menu and press < Enter >. Enter New Password: Type the password and press < Enter >. The screen does not display the characters entered. Retype the password as prompted and press < Enter >. If the password confirmation is incorrect, an error message appears. The password is stored in NVRAM after completes. # 8.7 Chipset Setup Select the Chipset tab from the setup screen to enter the Chipset BIOS Setup screen. You can select any of the items in the left frame of the screen to go to the sub menu for that item. The Chipset BIOS Setup screen is shown below. ![BIOS SETUP UTILITY\nMain Advanced PCIPnP Boot Security Chipset Exit\nAdvanced Chipset Settings Options\nUSB Functions (12 USB Ports)\nUSB 2.0 Controller (Enabled)\nSMBUS Controller (Enabled)\nOnboard LAN BIOS Init (Disabled)\nREAR SCSI BIOS Init (Disabled)\nClkGen Spread Spectrum (Disabled)\n← Select Screen\n↑↓ Select Item\n+- Change Option\nF1 General Help\nF10 Save and Exit\nESC Exit\nv02.61 (C) Copyright 1985-2006, American Megatrends, Inc.](.cpci-6920-50-15065-1020-202/167e9154ae444a23ed895322537011675c2717ab43822684c409f1c0f0a5bfe9.jpg) # USB Functions Set this value to allow the system to disable, enable, and select a set number of onboard USB ports. # USB 2.0 Controller This option takes effect only when USB Functions are enabled. Enabling will allow USB 2.0 functionality to all USB ports. # SMBus Controller Set this value to enable/disable the SMBus Controller # Onboard LAN BIOS Init Set this value to enable/disable the invoking of onboard LAN's PXE ROM. Disabling can shorten the POST time by not initializing LAN PXE ROM. Enable it if boot from LAN is needed. # Rear SCSI BIOS Init Set this value to enable/disable the invoking of REAR SCSI ROM. Disabling can shorten the POST time without initializing SCSI ROM. Enable it if boot from SCSI is needed. # ClkGen Spread Spectrum This field enables/disables support of the ClkGen Spread Spectrum function. # 8.8 Exit Menu Select the Exit tab from the setup screen to enter the Exit BIOS Setup screen. You can display an Exit BIOS Setup option by highlighting it using the <Arrow> keys. The Exit BIOS Setup screen is shown below.
Main Advanced PCIPnP Boot Security Chipset Exit
Exit Options Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults Load Failsafe DefaultsExit system setup after saving the changes. F10 key can be used for this operation. ← Select Screen ↑↓ Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit
v02.61 (C) Copyright 1985-2006, American Megatrends, Inc.
# Save Changes and Exit When you have completed the system configuration changes, select this option to leave Setup and reboot the computer so the new system configuration parameters can take effect. Save Configuration Changes and Exit Now? [Ok] [Cancel] appears in the window. Select Ok to save changes and exit. # Discard Changes and Exit Select this option to quit Setup without making any permanent changes to the system configuration. Discard Changes and Exit Setup Now? [Ok] [Cancel] appears in the window. Select Ok to discard changes and exit. # Discard Changes Select Discard Changes from the Exit menu and press < Enter >. Select Ok to discard changes. # Load Optimal Defaults Automatically sets all Setup options to a complete set of default settings when you select this option. The Optimal settings are designed for maximum system performance, but may not work best for all computer applications. In particular, do not use the Optimal Setup options if your computer is experiencing system configuration problems. Select Load Optimal Defaults from the Exit menu and press <Enter>. This page intentionally left blank. Select Ok to load optimal defaults. # Load Failsafe Defaults Automatically sets all Setup options to a complete set of default settings when you select this option. The Failsafe settings are designed for maximum system stability, but not maximum performance. Select the FailSafe Setup options if your computer is experiencing system configuration problems. Select Load Fail-Safe Defaults from the Exit menu and press <Enter>. Load FailSafe Defaults? [Ok] [Cancel] appears in the window. Select Ok to load FailSafe defaults. # 9 IPMI User Guide # 9.1 Introduction This chapter is written for those who already have a basic understanding of the newest implementation of the baseboard management controller (BMC) of the Intelligent Platform Management Interface (IPMI) specification rev. 1.5. It also describes the OEM extension IPMI command usages which are not listed in the IPMI specification. # 9.2 Summary of Commands Supported by IPMC The table below lists all the commands supported by the IPMC. The rightmost column indicates if the command is required by PICMG 3.0/PICMG 2.9, or is optional.
CommandIPMI SpecNetFnCMDIPM Controller Req (PICMG 3.0/2.9)
IPM Device “Global” Commands
Get Device ID17.1App01hMandatory/Mandatory
Cold Reset17.2App02hOptional/Optional
Warm Reset17.3App03hOptional/Optional
Get Self Test Results17.4App04hMandatory/Mandatory
Get Device GUID17.8App08hOptional/Optional
Broadcast “Get Device ID”17.9App01hMandatory/Mandatory
IPMI Messaging Support Commands
Send Message18.7App34hOptional/Optional
BMC Watchdog Timer
Reset Watchdog Timer21.5App22hMandatory/Optional
Set Watchdog Timer21.6App24hMandatory/Optional
Get Watchdog Timer21.7App25hMandatory/Optional
Event Commands
Set Event Receiver23.1S/E00hMandatory/Optional
Get Event Receiver23.2S/E01hMandatory/Optional
Platform Event (a.k.a. “Event Message”)23.3S/E02hMandatory/Optional
Sensor Device Commands
Get Device SDR Info29.2S/E20hMandatory/Optional
Get Device SDR29.3S/E21hMandatory/Optional
Reserve Device SDR Repository29.4S/E22hMandatory/Optional
Set Sensor Hysteresis29.6S/E24hOptional/Optional
Get Sensor Hysteresis29.7S/E25hOptional/Optional
Set Sensor Threshold29.8S/E26hOptional/Optional
Get Sensor Threshold29.9S/E27hOptional/Optional
Set Sensor Event Enable29.10S/E28hOptional/Optional
Get Sensor Event Enable29.11S/E29hOptional/Optional
Get Sensor Event Status29.13S/E2BhOptional/Optional
Get Sensor Reading29.14S/E2DhMandatory/Optional
Get Sensor Type29.16S/E2FhOptional/Optional
FRU Device Commands
Get FRU Inventory Area Info28.1Storage10hMandatory/Optional
Read FRU Data28.2Storage11hMandatory/Optional
Write FRU Data28.3Storage12hMandatory/Optional
# 9.3 OEM Commands Summary Table
CommandNetFn CodeCmd Code
OemShowRevisionOEM (C0h)12h
OemRescanGaInputOEM (C0h)22h
OemTestFunctionOEM (C0h)30h
OemSetBlueLEDLongBlinkingOEM (C0h)31h
OemReportGeoAddressOEM (C0h)F0h
OemEnableSmbusOEM (C0h)F2h
OemDisableSmbusOEM (C0h)F3h
OemDispDebugVariableOEM (C0h)F4h
OemResetHostOEM (C0h)F5h
OemPowerOffOEM (C0h)F6h
OemPowerOnOEM (C0h)F7h
# OemShowRevision This command is used to show the current information of the firmware including the firmware revision, the product ID, and additional features.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
112hOEM defined command
Response0Complete Code00h means OK
1A5hInternal check byte. Always A5h
2*Firmware Rev‘V’ in ASCII code for verification
3*Firmware RevRevision info high byte
4*Firmware RevRevision info low byte
5*Product ID‘P’ in ASCII code for verification
6*Product IDProduct info high byte
7*Product IDProduct info low byte
8*Special info‘S’ in ASCII code for verification
9*Special infoAddition info byte
105AhInternal check byte. Always 5Ah
# OemRescanGaInput This command is used to rescan the geo-address input pins and reset the IPMB address according to the input value.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
122hOEM defined command
Response0Complete Code00h means OK
1New IPMB addressNew IPMB address value
# OemTestFunction Internal test purposes only. # OemSetBlueLEDLongBlinking This command is used to enable/disable the slow blinking of the blue HotSwap LED when a voltage is detected to be over $\pm5\%$ out of range for five seconds (see Table 4-1 on page 24). Disabled by default.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
131hOEM defined command
200h or 01h00h: disable slow blink capability01h: enable slow blink capability
Response0Complete Code00h means OK
# OemReportGeoAddress This command can report the IPMB address, the GA pin input status, and the event forwarding control value.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F0hOEM defined command
Response0Complete Code00h means OK
1IPMB addressIPMB address value
2GA valueGA pin input status
3Control valueCurrent control value of event forwarding
# OemEnableSmbus This command is used to turn on the I2C bus when it is off during boot up process. Usually BIOS will perform this command after booting in boards with ServerWorks chipset.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F2hOEM defined command
Response0Complete Code00h means OK
# OemDisableSmbus This command is used to shut down I2C bus access.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F3hOEM defined command
Response0Complete Code00h means OK
# OemDispDebugVariable This command can report up to 5 interval values for debug purposes. For developers only.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F4hOEM defined command
Response0Complete Code00h means OK
1*Debug variable 1
2*Debug variable 2
3*Debug variable 3
4*Debug variable 4
5*Debug variable 5
# OemResetHost This command is implemented to control the system's status if rebooting is required. Operators can control the system remotely.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F5hOEM defined command
Response0Complete Code00h means OK
# OemPowerOff This command is implemented to control the system's status if power-off is required. Operators can control the system remotely.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F6hOEM defined command
Response0Complete Code00h means OK
# OemPowerOn This command is implemented to control the system's status if power-on is required. Operators can control the system remotely.
ActionByteValueDescription
Request0C0hNetFn/LUN for OEM
1F7hOEM defined command
Response0Complete Code00h means OK
# 9.4 CompactPCI Address Map Since more than one system may be installed in a single chassis, we allocate each IPMB address based on GA input as peripheral cards. The CompactPCI Peripheral Address Mapping Table is given below.
CompactPCI Peripheral Address Mapping
Geo. Addr.IPMB Addr.Geo. Addr.IPMB Addr.
0Disabled16D0h
1B0h17D2h
2B2h18D4h
3B4h19D6h
4B6h20D8h
5B8h21DAh
6Bah22DCh
7BCh23DEh
8BEh24E0h
9Coh25E2h
10C4h26E4h
11C6h27E6h
12C8h28E8h
13CAh29EAh
14CCh30ECh
15CEh31Disabled
# 9.5 Communications with IPMC Operating systems need to use a serial port to communicate with the IPMC. The resource setting of the serial port must be IO: 0x3E8 and IRQ: 3. The communication setting of the serial port must be BaudRate: 9600, DataBit: 8, ParityCheck: None, StopBit: 1, and FlowControl: None. In Windows XP, use "COM3" to communicate with the IPMC. # 9.6 IPMI Sensors List
Sensor NumberSensor nameNormal ReadingSensor Reading Value of IPMI Get Sensor Reading Command
01hBMC WatchdogTimeout action:000b = no action001b = Hard Reset000b = Power Down011b = Power Cycle100b - 111b = reserved
02h3.3V3.3 VRaw data of 3.3V sensor
03h5V5 VRaw data of 5.0V sensor
04h12V12 VRaw data of 12.0V sensor
05h1.5V1.5 VRaw data of 1.5V sensor
06hCPU0 Temp40°CRaw data of CPU0 Temp sensor
07hCPU1 Temp40°CRaw data of CPU1 Temp sensor
08hSYSTEM Temp25°CRaw data of SYSTEM Temp sensor
09hPower Good3.3V, 5V, and 12V status:0x01= Power Good0x02 = Power Fail
0ahSYS_PWROKAll system power status:0x01 = SYS_PWR OK0x02 = SYS_PWR Fail
0bhBIOS CHANGECurrent Bios Number:0x01 = Bios10x02 = Bios2
0chBIOS POST ERRORPost error status and Bios Recovery status:0x00 = BIOS_NONE0x01 = BIOS_RESET0x02 = BIOS_ROM_CHECK0x04= BIOS_HARDWARE_INIT0x20= BIOS_BURN_FINISH
# 9.7 Relevant Documents
Document TitleRevisionSource
Intelligent Platform Management Interface Specification v1.5Document Revision 1.1 February 20, 2002Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm
PICMG 2.9 D1.0 CompactPCI System Management SpecificationJanuary 21, 2000
Intelligent Platform Management Bus Communications Protocol Specification v0.9Document Revision 0.15 June 24, 1997Intel Corp.http://www.intel.com/design/servers/ipmi/license_ipmi.htm
This page intentionally left blank. # Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. ▶ Read these safety instructions carefully. - Keep this user’s manual for future reference. ▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment. ▶ When installing/mounting or uninstalling/removing equipment: ▷ Turn off power and unplug any power cords/cables. ▶ To avoid electrical shock and/or damage to equipment: ▷ Keep equipment away from water or liquid sources; ▷ Keep equipment away from high heat or high humidity; ▷ Keep equipment properly ventilated (do not block or cover ventilation openings); ▶ Make sure to use recommended voltage and power source settings; ▶ Always install and operate equipment near an easily accessible electrical socket-outlet; ▷ Secure the power cord (do not place any object on/over the power cord); ▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and, ▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. ▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. ![The image features a maroon triangle containing a large white exclamation point. Below the triangle, the word 'WARNING:' is printed in bold, black, capital letters.](.cpci-6920-50-15065-1020-202/34375f4cfda0090e47462f26565c2e42256c098b2dcb497961a33a47eb21dd2c.jpg) Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately. ▶ Equipment must be serviced by authorized technicians when: ▷ The power cord or plug is damaged; ▷ Liquid has penetrated the equipment; ▷ It has been exposed to high humidity/moisture; $\triangleright$ It is not functioning or does not function according to the user's manual; ▷ It has been dropped and/or damaged; and/or, ▷ It has an obvious sign of breakage. # Getting Service Contact us should you require any service or assistance. # ADLINK Technology, Inc. Address: 9F, No.166 Jian Yi Road, Chungho City, Taipei County 235, Taiwan 台北縣中和市建一路 166 號 9 樓 Tel: +886-2-8226-5877 Fax: +886-2-8226-5717 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com # ADLINK Technology Beijing Address: 北京市海淀区上地东路 1 号盈创动力大厦 E 座 801 室(100085) Rm. 801, Power Creative E, No. 1, B/D Shang Di East Rd., Beijing, 100085 China Tel: +86-10-5885-8666 Fax: +86-10-5885-8625 Email: market@adlinktech.com # ADLINK Technology Shanghai Address: 上海市漕河泾高科技开发区钦江路 333 号 39 幢 4 层 (200233) 4F, Bldg 39, Caoheting Science & Technology Park, No.333 Qinjiang Rd., Shanghai, 200233 China Tel: +86-21-6495-5210 Fax: +86-21-5450-0414 Email: market@adlinktech.com # ADLINK Technology Shenzhen Address: 深圳市南山区科技园南区高新南七道 数字技术园 A1 栋 2 楼 C 区 (518057) 2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 China Tel: +86-755-2643-4858 Fax: +86-755-2664-6353 Email: market@adlinktech.com # ADLINK Technology, Inc. (German Liaison Office) Address: Nord Carree 3, 40477 Duesseldorf, Germany Tel: +49-211-495-5552 Fax: +49-211-495-5557 Email: emea@adlinktech.com # ADLINK Technology, Inc. (French Liaison Office) Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France Tel: +33 (0) 1 60 12 35 66 Fax: +33 (0) 1 60 12 35 66 Email: france@adlinktech.com # ADLINK Technology Japan Corporation Address: 151-0072 東京都渋谷区幡ヶ谷 1-1-2 朝日生命幡ヶ谷ビル 8F Asahiseimei Hatagaya Bldg. 8F 1-1-2 Hatagaya, Shibuya-ku, Tokyo 151-0072, Japan Tel: +81-3-4455-3722 Fax: +81-3-5333-6040 Email: japan@adlinktech.com # ADLINK Technology, Inc. (Korean Liaison Office) Address: 서울시 서초구 서초동 1506-25 한도 B/D 2 층 2F, Hando B/D, 1506-25, Seocho-Dong, Seocho-Gu, Seoul 137-070, Korea Tel: +82-2-2057-0565 Fax: +82-2-2057-0563 Email: korea@adlinktech.com # ADLINK Technology Singapore Pte. Ltd. Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584 Tel: +65-6844-2261 Fax: +65-6844-2263 Email: singapore@adlinktech.com # ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office) Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross, JP Nagar Phase I, Bangalore - 560078, India Tel: +91-80-65605817 Fax: +91-80-22443548 Email: india@adlinktech.com [🔗 Link to the original document](.cpci-6920-50-15065-1020-202/cpci-6920-50-15065-1020-202.pdf)